drivers/net/wireless/ath/ath9k/ath9k.h

   1 /*
   2  * Copyright (c) 2008-2009 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #ifndef ATH9K_H
  18 #define ATH9K_H
  19
  20 #include <linux/etherdevice.h>
  21 #include <linux/device.h>
  22 #include <net/mac80211.h>
  23 #include <linux/leds.h>
  24
  25 #include "hw.h"
  26 #include "rc.h"
  27 #include "debug.h"
  28
  29 struct ath_node;
  30
  31 /* Macro to expand scalars to 64-bit objects */
  32
  33 #define ito64(x) (sizeof(x) == 8) ?                     \
  34         (((unsigned long long int)(x)) & (0xff)) :      \
  35         (sizeof(x) == 16) ?                             \
  36         (((unsigned long long int)(x)) & 0xffff) :      \
  37         ((sizeof(x) == 32) ?                            \
  38          (((unsigned long long int)(x)) & 0xffffffff) : \
  39          (unsigned long long int)(x))
  40
  41 /* increment with wrap-around */
  42 #define INCR(_l, _sz)   do {                    \
  43                 (_l)++;                         \
  44                 (_l) &= ((_sz) - 1);            \
  45         } while (0)
  46
  47 /* decrement with wrap-around */
  48 #define DECR(_l,  _sz)  do {                    \
  49                 (_l)--;                         \
  50                 (_l) &= ((_sz) - 1);            \
  51         } while (0)
  52
  53 #define A_MAX(a, b) ((a) > (b) ? (a) : (b))
  54
  55 #define ASSERT(exp) BUG_ON(!(exp))
  56
  57 #define TSF_TO_TU(_h,_l) \
  58         ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
  59
  60 #define ATH_TXQ_SETUP(sc, i)        ((sc)->tx.txqsetup & (1<<i))
  61
  62 static const u8 ath_bcast_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
  63
  64 struct ath_config {
  65         u32 ath_aggr_prot;
  66         u16 txpowlimit;
  67         u8 cabqReadytime;
  68 };
  69
  70 /*************************/
  71 /* Descriptor Management */
  72 /*************************/
  73
  74 #define ATH_TXBUF_RESET(_bf) do {                               \
  75                 (_bf)->bf_stale = false;                        \
  76                 (_bf)->bf_lastbf = NULL;                        \
  77                 (_bf)->bf_next = NULL;                          \
  78                 memset(&((_bf)->bf_state), 0,                   \
  79                        sizeof(struct ath_buf_state));           \
  80         } while (0)
  81
  82 #define ATH_RXBUF_RESET(_bf) do {               \
  83                 (_bf)->bf_stale = false;        \
  84         } while (0)
  85
  86 /**
  87  * enum buffer_type - Buffer type flags
  88  *
  89  * @BUF_HT: Send this buffer using HT capabilities
  90  * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX)
  91  * @BUF_AGGR: Indicates whether the buffer can be aggregated
  92  *      (used in aggregation scheduling)
  93  * @BUF_RETRY: Indicates whether the buffer is retried
  94  * @BUF_XRETRY: To denote excessive retries of the buffer
  95  */
  96 enum buffer_type {
  97         BUF_HT                  = BIT(1),
  98         BUF_AMPDU               = BIT(2),
  99         BUF_AGGR                = BIT(3),
 100         BUF_RETRY               = BIT(4),
 101         BUF_XRETRY              = BIT(5),
 102 };
 103
 104 struct ath_buf_state {
 105         int bfs_nframes;
 106         u16 bfs_al;
 107         u16 bfs_frmlen;
 108         int bfs_seqno;
 109         int bfs_tidno;
 110         int bfs_retries;
 111         u8 bf_type;
 112         u32 bfs_keyix;
 113         enum ath9k_key_type bfs_keytype;
 114 };
 115
 116 #define bf_nframes              bf_state.bfs_nframes
 117 #define bf_al                   bf_state.bfs_al
 118 #define bf_frmlen               bf_state.bfs_frmlen
 119 #define bf_retries              bf_state.bfs_retries
 120 #define bf_seqno                bf_state.bfs_seqno
 121 #define bf_tidno                bf_state.bfs_tidno
 122 #define bf_keyix                bf_state.bfs_keyix
 123 #define bf_keytype              bf_state.bfs_keytype
 124 #define bf_isht(bf)             (bf->bf_state.bf_type & BUF_HT)
 125 #define bf_isampdu(bf)          (bf->bf_state.bf_type & BUF_AMPDU)
 126 #define bf_isaggr(bf)           (bf->bf_state.bf_type & BUF_AGGR)
 127 #define bf_isretried(bf)        (bf->bf_state.bf_type & BUF_RETRY)
 128 #define bf_isxretried(bf)       (bf->bf_state.bf_type & BUF_XRETRY)
 129
 130 struct ath_buf {
 131         struct list_head list;
 132         struct ath_buf *bf_lastbf;      /* last buf of this unit (a frame or
 133                                            an aggregate) */
 134         struct ath_buf *bf_next;        /* next subframe in the aggregate */
 135         struct sk_buff *bf_mpdu;        /* enclosing frame structure */
 136         struct ath_desc *bf_desc;       /* virtual addr of desc */
 137         dma_addr_t bf_daddr;            /* physical addr of desc */
 138         dma_addr_t bf_buf_addr;         /* physical addr of data buffer */
 139         bool bf_stale;
 140         u16 bf_flags;
 141         struct ath_buf_state bf_state;
 142         dma_addr_t bf_dmacontext;
 143 };
 144
 145 struct ath_descdma {
 146         struct ath_desc *dd_desc;
 147         dma_addr_t dd_desc_paddr;
 148         u32 dd_desc_len;
 149         struct ath_buf *dd_bufptr;
 150 };
 151
 152 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
 153                       struct list_head *head, const char *name,
 154                       int nbuf, int ndesc);
 155 void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd,
 156                          struct list_head *head);
 157
 158 /***********/
 159 /* RX / TX */
 160 /***********/
 161
 162 #define ATH_MAX_ANTENNA         3
 163 #define ATH_RXBUF               512
 164 #define WME_NUM_TID             16
 165 #define ATH_TXBUF               512
 166 #define ATH_TXMAXTRY            13
 167 #define ATH_MGT_TXMAXTRY        4
 168 #define WME_BA_BMP_SIZE         64
 169 #define WME_MAX_BA              WME_BA_BMP_SIZE
 170 #define ATH_TID_MAX_BUFS        (2 * WME_MAX_BA)
 171
 172 #define TID_TO_WME_AC(_tid)                             \
 173         ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \
 174          (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \
 175          (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \
 176          WME_AC_VO)
 177
 178 #define WME_AC_BE   0
 179 #define WME_AC_BK   1
 180 #define WME_AC_VI   2
 181 #define WME_AC_VO   3
 182 #define WME_NUM_AC  4
 183
 184 #define ADDBA_EXCHANGE_ATTEMPTS    10
 185 #define ATH_AGGR_DELIM_SZ          4
 186 #define ATH_AGGR_MINPLEN           256 /* in bytes, minimum packet length */
 187 /* number of delimiters for encryption padding */
 188 #define ATH_AGGR_ENCRYPTDELIM      10
 189 /* minimum h/w qdepth to be sustained to maximize aggregation */
 190 #define ATH_AGGR_MIN_QDEPTH        2
 191 #define ATH_AMPDU_SUBFRAME_DEFAULT 32
 192 #define ATH_AMPDU_LIMIT_MAX        (64 * 1024 - 1)
 193 #define ATH_AMPDU_LIMIT_DEFAULT    ATH_AMPDU_LIMIT_MAX
 194
 195 #define IEEE80211_SEQ_SEQ_SHIFT    4
 196 #define IEEE80211_SEQ_MAX          4096
 197 #define IEEE80211_MIN_AMPDU_BUF    0x8
 198 #define IEEE80211_HTCAP_MAXRXAMPDU_FACTOR 13
 199 #define IEEE80211_WEP_IVLEN        3
 200 #define IEEE80211_WEP_KIDLEN       1
 201 #define IEEE80211_WEP_CRCLEN       4
 202 #define IEEE80211_MAX_MPDU_LEN     (3840 + FCS_LEN +            \
 203                                     (IEEE80211_WEP_IVLEN +      \
 204                                      IEEE80211_WEP_KIDLEN +     \
 205                                      IEEE80211_WEP_CRCLEN))
 206
 207 /* return whether a bit at index _n in bitmap _bm is set
 208  * _sz is the size of the bitmap  */
 209 #define ATH_BA_ISSET(_bm, _n)  (((_n) < (WME_BA_BMP_SIZE)) &&           \
 210                                 ((_bm)[(_n) >> 5] & (1 << ((_n) & 31))))
 211
 212 /* return block-ack bitmap index given sequence and starting sequence */
 213 #define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1))
 214
 215 /* returns delimiter padding required given the packet length */
 216 #define ATH_AGGR_GET_NDELIM(_len)                                       \
 217         (((((_len) + ATH_AGGR_DELIM_SZ) < ATH_AGGR_MINPLEN) ?           \
 218           (ATH_AGGR_MINPLEN - (_len) - ATH_AGGR_DELIM_SZ) : 0) >> 2)
 219
 220 #define BAW_WITHIN(_start, _bawsz, _seqno) \
 221         ((((_seqno) - (_start)) & 4095) < (_bawsz))
 222
 223 #define ATH_DS_BA_SEQ(_ds)         ((_ds)->ds_us.tx.ts_seqnum)
 224 #define ATH_DS_BA_BITMAP(_ds)      (&(_ds)->ds_us.tx.ba_low)
 225 #define ATH_DS_TX_BA(_ds)          ((_ds)->ds_us.tx.ts_flags & ATH9K_TX_BA)
 226 #define ATH_AN_2_TID(_an, _tidno)  (&(_an)->tid[(_tidno)])
 227
 228 #define ATH_TX_COMPLETE_POLL_INT        1000
 229
 230 enum ATH_AGGR_STATUS {
 231         ATH_AGGR_DONE,
 232         ATH_AGGR_BAW_CLOSED,
 233         ATH_AGGR_LIMITED,
 234 };
 235
 236 struct ath_txq {
 237         u32 axq_qnum;
 238         u32 *axq_link;
 239         struct list_head axq_q;
 240         spinlock_t axq_lock;
 241         u32 axq_depth;
 242         u8 axq_aggr_depth;
 243         u32 axq_totalqueued;
 244         bool stopped;
 245         bool axq_tx_inprogress;
 246         struct ath_buf *axq_linkbuf;
 247
 248         /* first desc of the last descriptor that contains CTS */
 249         struct ath_desc *axq_lastdsWithCTS;
 250
 251         /* final desc of the gating desc that determines whether
 252            lastdsWithCTS has been DMA'ed or not */
 253         struct ath_desc *axq_gatingds;
 254
 255         struct list_head axq_acq;
 256 };
 257
 258 #define AGGR_CLEANUP         BIT(1)
 259 #define AGGR_ADDBA_COMPLETE  BIT(2)
 260 #define AGGR_ADDBA_PROGRESS  BIT(3)
 261
 262 struct ath_atx_tid {
 263         struct list_head list;
 264         struct list_head buf_q;
 265         struct ath_node *an;
 266         struct ath_atx_ac *ac;
 267         struct ath_buf *tx_buf[ATH_TID_MAX_BUFS];
 268         u16 seq_start;
 269         u16 seq_next;
 270         u16 baw_size;
 271         int tidno;
 272         int baw_head;   /* first un-acked tx buffer */
 273         int baw_tail;   /* next unused tx buffer slot */
 274         int sched;
 275         int paused;
 276         u8 state;
 277 };
 278
 279 struct ath_atx_ac {
 280         int sched;
 281         int qnum;
 282         struct list_head list;
 283         struct list_head tid_q;
 284 };
 285
 286 struct ath_tx_control {
 287         struct ath_txq *txq;
 288         int if_id;
 289         enum ath9k_internal_frame_type frame_type;
 290 };
 291
 292 #define ATH_TX_ERROR        0x01
 293 #define ATH_TX_XRETRY       0x02
 294 #define ATH_TX_BAR          0x04
 295
 296 #define ATH_RSSI_LPF_LEN                10
 297 #define RSSI_LPF_THRESHOLD              -20
 298 #define ATH9K_RSSI_BAD                  0x80
 299 #define ATH_RSSI_EP_MULTIPLIER     (1<<7)
 300 #define ATH_EP_MUL(x, mul)         ((x) * (mul))
 301 #define ATH_RSSI_IN(x)             (ATH_EP_MUL((x), ATH_RSSI_EP_MULTIPLIER))
 302 #define ATH_LPF_RSSI(x, y, len) \
 303     ((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y))
 304 #define ATH_RSSI_LPF(x, y) do {                                         \
 305     if ((y) >= RSSI_LPF_THRESHOLD)                                      \
 306         x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN);      \
 307 } while (0)
 308 #define ATH_EP_RND(x, mul)                                              \
 309         ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul))
 310
 311 struct ath_node {
 312         struct ath_softc *an_sc;
 313         struct ath_atx_tid tid[WME_NUM_TID];
 314         struct ath_atx_ac ac[WME_NUM_AC];
 315         u16 maxampdu;
 316         u8 mpdudensity;
 317         int last_rssi;
 318 };
 319
 320 struct ath_tx {
 321         u16 seq_no;
 322         u32 txqsetup;
 323         int hwq_map[ATH9K_WME_AC_VO+1];
 324         spinlock_t txbuflock;
 325         struct list_head txbuf;
 326         struct ath_txq txq[ATH9K_NUM_TX_QUEUES];
 327         struct ath_descdma txdma;
 328 };
 329
 330 struct ath_rx {
 331         u8 defant;
 332         u8 rxotherant;
 333         u32 *rxlink;
 334         int bufsize;
 335         unsigned int rxfilter;
 336         spinlock_t rxflushlock;
 337         spinlock_t rxbuflock;
 338         struct list_head rxbuf;
 339         struct ath_descdma rxdma;
 340 };
 341
 342 int ath_startrecv(struct ath_softc *sc);
 343 bool ath_stoprecv(struct ath_softc *sc);
 344 void ath_flushrecv(struct ath_softc *sc);
 345 u32 ath_calcrxfilter(struct ath_softc *sc);
 346 int ath_rx_init(struct ath_softc *sc, int nbufs);
 347 void ath_rx_cleanup(struct ath_softc *sc);
 348 int ath_rx_tasklet(struct ath_softc *sc, int flush);
 349 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
 350 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
 351 int ath_tx_setup(struct ath_softc *sc, int haltype);
 352 void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx);
 353 void ath_draintxq(struct ath_softc *sc,
 354                      struct ath_txq *txq, bool retry_tx);
 355 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an);
 356 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an);
 357 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq);
 358 int ath_tx_init(struct ath_softc *sc, int nbufs);
 359 void ath_tx_cleanup(struct ath_softc *sc);
 360 struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb);
 361 int ath_txq_update(struct ath_softc *sc, int qnum,
 362                    struct ath9k_tx_queue_info *q);
 363 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
 364                  struct ath_tx_control *txctl);
 365 void ath_tx_tasklet(struct ath_softc *sc);
 366 void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb);
 367 bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno);
 368 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
 369                       u16 tid, u16 *ssn);
 370 int ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
 371 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
 372
 373 /********/
 374 /* VIFs */
 375 /********/
 376
 377 struct ath_vif {
 378         int av_bslot;
 379         __le64 tsf_adjust; /* TSF adjustment for staggered beacons */
 380         enum nl80211_iftype av_opmode;
 381         struct ath_buf *av_bcbuf;
 382         struct ath_tx_control av_btxctl;
 383         u8 bssid[ETH_ALEN]; /* current BSSID from config_interface */
 384 };
 385
 386 /*******************/
 387 /* Beacon Handling */
 388 /*******************/
 389
 390 /*
 391  * Regardless of the number of beacons we stagger, (i.e. regardless of the
 392  * number of BSSIDs) if a given beacon does not go out even after waiting this
 393  * number of beacon intervals, the game's up.
 394  */
 395 #define BSTUCK_THRESH                   (9 * ATH_BCBUF)
 396 #define ATH_BCBUF                       4
 397 #define ATH_DEFAULT_BINTVAL             100 /* TU */
 398 #define ATH_DEFAULT_BMISS_LIMIT         10
 399 #define IEEE80211_MS_TO_TU(x)           (((x) * 1000) / 1024)
 400
 401 struct ath_beacon_config {
 402         u16 beacon_interval;
 403         u16 listen_interval;
 404         u16 dtim_period;
 405         u16 bmiss_timeout;
 406         u8 dtim_count;
 407 };
 408
 409 struct ath_beacon {
 410         enum {
 411                 OK,             /* no change needed */
 412                 UPDATE,         /* update pending */
 413                 COMMIT          /* beacon sent, commit change */
 414         } updateslot;           /* slot time update fsm */
 415
 416         u32 beaconq;
 417         u32 bmisscnt;
 418         u32 ast_be_xmit;
 419         u64 bc_tstamp;
 420         struct ieee80211_vif *bslot[ATH_BCBUF];
 421         struct ath_wiphy *bslot_aphy[ATH_BCBUF];
 422         int slottime;
 423         int slotupdate;
 424         struct ath9k_tx_queue_info beacon_qi;
 425         struct ath_descdma bdma;
 426         struct ath_txq *cabq;
 427         struct list_head bbuf;
 428 };
 429
 430 void ath_beacon_tasklet(unsigned long data);
 431 void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif);
 432 int ath_beaconq_setup(struct ath_hw *ah);
 433 int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif);
 434 void ath_beacon_return(struct ath_softc *sc, struct ath_vif *avp);
 435
 436 /*******/
 437 /* ANI */
 438 /*******/
 439
 440 #define ATH_STA_SHORT_CALINTERVAL 1000    /* 1 second */
 441 #define ATH_AP_SHORT_CALINTERVAL  100     /* 100 ms */
 442 #define ATH_ANI_POLLINTERVAL      100     /* 100 ms */
 443 #define ATH_LONG_CALINTERVAL      30000   /* 30 seconds */
 444 #define ATH_RESTART_CALINTERVAL   1200000 /* 20 minutes */
 445
 446 struct ath_ani {
 447         bool caldone;
 448         int16_t noise_floor;
 449         unsigned int longcal_timer;
 450         unsigned int shortcal_timer;
 451         unsigned int resetcal_timer;
 452         unsigned int checkani_timer;
 453         struct timer_list timer;
 454 };
 455
 456 /********************/
 457 /*   LED Control    */
 458 /********************/
 459
 460 #define ATH_LED_PIN     1
 461 #define ATH_LED_ON_DURATION_IDLE        350     /* in msecs */
 462 #define ATH_LED_OFF_DURATION_IDLE       250     /* in msecs */
 463
 464 enum ath_led_type {
 465         ATH_LED_RADIO,
 466         ATH_LED_ASSOC,
 467         ATH_LED_TX,
 468         ATH_LED_RX
 469 };
 470
 471 struct ath_led {
 472         struct ath_softc *sc;
 473         struct led_classdev led_cdev;
 474         enum ath_led_type led_type;
 475         char name[32];
 476         bool registered;
 477 };
 478
 479 /********************/
 480 /* Main driver core */
 481 /********************/
 482
 483 /*
 484  * Default cache line size, in bytes.
 485  * Used when PCI device not fully initialized by bootrom/BIOS
 486 */
 487 #define DEFAULT_CACHELINE       32
 488 #define ATH_DEFAULT_NOISE_FLOOR -95
 489 #define ATH_REGCLASSIDS_MAX     10
 490 #define ATH_CABQ_READY_TIME     80      /* % of beacon interval */
 491 #define ATH_MAX_SW_RETRIES      10
 492 #define ATH_CHAN_MAX            255
 493 #define IEEE80211_WEP_NKID      4       /* number of key ids */
 494
 495 /*
 496  * The key cache is used for h/w cipher state and also for
 497  * tracking station state such as the current tx antenna.
 498  * We also setup a mapping table between key cache slot indices
 499  * and station state to short-circuit node lookups on rx.
 500  * Different parts have different size key caches.  We handle
 501  * up to ATH_KEYMAX entries (could dynamically allocate state).
 502  */
 503 #define ATH_KEYMAX              128     /* max key cache size we handle */
 504
 505 #define ATH_TXPOWER_MAX         100     /* .5 dBm units */
 506 #define ATH_RSSI_DUMMY_MARKER   0x127
 507 #define ATH_RATE_DUMMY_MARKER   0
 508
 509 #define SC_OP_INVALID           BIT(0)
 510 #define SC_OP_BEACONS           BIT(1)
 511 #define SC_OP_RXAGGR            BIT(2)
 512 #define SC_OP_TXAGGR            BIT(3)
 513 #define SC_OP_FULL_RESET        BIT(4)
 514 #define SC_OP_PREAMBLE_SHORT    BIT(5)
 515 #define SC_OP_PROTECT_ENABLE    BIT(6)
 516 #define SC_OP_RXFLUSH           BIT(7)
 517 #define SC_OP_LED_ASSOCIATED    BIT(8)
 518 #define SC_OP_WAIT_FOR_BEACON   BIT(12)
 519 #define SC_OP_LED_ON            BIT(13)
 520 #define SC_OP_SCANNING          BIT(14)
 521 #define SC_OP_TSF_RESET         BIT(15)
 522 #define SC_OP_WAIT_FOR_CAB      BIT(16)
 523 #define SC_OP_WAIT_FOR_PSPOLL_DATA BIT(17)
 524 #define SC_OP_WAIT_FOR_TX_ACK   BIT(18)
 525 #define SC_OP_BEACON_SYNC       BIT(19)
 526
 527 struct ath_bus_ops {
 528         void            (*read_cachesize)(struct ath_softc *sc, int *csz);
 529         void            (*cleanup)(struct ath_softc *sc);
 530         bool            (*eeprom_read)(struct ath_hw *ah, u32 off, u16 *data);
 531 };
 532
 533 struct ath_wiphy;
 534
 535 struct ath_softc {
 536         struct ieee80211_hw *hw;
 537         struct device *dev;
 538
 539         spinlock_t wiphy_lock; /* spinlock to protect ath_wiphy data */
 540         struct ath_wiphy *pri_wiphy;
 541         struct ath_wiphy **sec_wiphy; /* secondary wiphys (virtual radios); may
 542                                        * have NULL entries */
 543         int num_sec_wiphy; /* number of sec_wiphy pointers in the array */
 544         int chan_idx;
 545         int chan_is_ht;
 546         struct ath_wiphy *next_wiphy;
 547         struct work_struct chan_work;
 548         int wiphy_select_failures;
 549         unsigned long wiphy_select_first_fail;
 550         struct delayed_work wiphy_work;
 551         unsigned long wiphy_scheduler_int;
 552         int wiphy_scheduler_index;
 553
 554         struct tasklet_struct intr_tq;
 555         struct tasklet_struct bcon_tasklet;
 556         struct ath_hw *sc_ah;
 557         void __iomem *mem;
 558         int irq;
 559         spinlock_t sc_resetlock;
 560         spinlock_t sc_serial_rw;
 561         spinlock_t ani_lock;
 562         struct mutex mutex;
 563
 564         u8 curbssid[ETH_ALEN];
 565         u8 bssidmask[ETH_ALEN];
 566         u32 intrstatus;
 567         u32 sc_flags; /* SC_OP_* */
 568         u16 curtxpow;
 569         u16 curaid;
 570         u16 cachelsz;
 571         u8 nbcnvifs;
 572         u16 nvifs;
 573         u8 tx_chainmask;
 574         u8 rx_chainmask;
 575         u32 keymax;
 576         DECLARE_BITMAP(keymap, ATH_KEYMAX);
 577         u8 splitmic;
 578         atomic_t ps_usecount;
 579         enum ath9k_int imask;
 580         enum ath9k_ht_extprotspacing ht_extprotspacing;
 581         enum ath9k_ht_macmode tx_chan_width;
 582
 583         struct ath_config config;
 584         struct ath_rx rx;
 585         struct ath_tx tx;
 586         struct ath_beacon beacon;
 587         struct ieee80211_rate rates[IEEE80211_NUM_BANDS][ATH_RATE_MAX];
 588         const struct ath_rate_table *hw_rate_table[ATH9K_MODE_MAX];
 589         const struct ath_rate_table *cur_rate_table;
 590         struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
 591
 592         struct ath_led radio_led;
 593         struct ath_led assoc_led;
 594         struct ath_led tx_led;
 595         struct ath_led rx_led;
 596         struct delayed_work ath_led_blink_work;
 597         int led_on_duration;
 598         int led_off_duration;
 599         int led_on_cnt;
 600         int led_off_cnt;
 601
 602         int beacon_interval;
 603
 604         struct ath_ani ani;
 605         struct ath9k_node_stats nodestats;
 606 #ifdef CONFIG_ATH9K_DEBUG
 607         struct ath9k_debug debug;
 608 #endif
 609         struct ath_bus_ops *bus_ops;
 610         struct ath_beacon_config cur_beacon_conf;
 611         struct delayed_work tx_complete_work;
 612 };
 613
 614 struct ath_wiphy {
 615         struct ath_softc *sc; /* shared for all virtual wiphys */
 616         struct ieee80211_hw *hw;
 617         enum ath_wiphy_state {
 618                 ATH_WIPHY_INACTIVE,
 619                 ATH_WIPHY_ACTIVE,
 620                 ATH_WIPHY_PAUSING,
 621                 ATH_WIPHY_PAUSED,
 622                 ATH_WIPHY_SCAN,
 623         } state;
 624         int chan_idx;
 625         int chan_is_ht;
 626 };
 627
 628 int ath_reset(struct ath_softc *sc, bool retry_tx);
 629 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc);
 630 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc);
 631 int ath_cabq_update(struct ath_softc *);
 632
 633 static inline void ath_read_cachesize(struct ath_softc *sc, int *csz)
 634 {
 635         sc->bus_ops->read_cachesize(sc, csz);
 636 }
 637
 638 static inline void ath_bus_cleanup(struct ath_softc *sc)
 639 {
 640         sc->bus_ops->cleanup(sc);
 641 }
 642
 643 extern struct ieee80211_ops ath9k_ops;
 644
 645 irqreturn_t ath_isr(int irq, void *dev);
 646 void ath_cleanup(struct ath_softc *sc);
 647 int ath_attach(u16 devid, struct ath_softc *sc);
 648 void ath_detach(struct ath_softc *sc);
 649 const char *ath_mac_bb_name(u32 mac_bb_version);
 650 const char *ath_rf_name(u16 rf_version);
 651 void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw);
 652 void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
 653                            struct ath9k_channel *ichan);
 654 void ath_update_chainmask(struct ath_softc *sc, int is_ht);
 655 int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
 656                     struct ath9k_channel *hchan);
 657 void ath_radio_enable(struct ath_softc *sc);
 658 void ath_radio_disable(struct ath_softc *sc);
 659
 660 #ifdef CONFIG_PCI
 661 int ath_pci_init(void);
 662 void ath_pci_exit(void);
 663 #else
 664 static inline int ath_pci_init(void) { return 0; };
 665 static inline void ath_pci_exit(void) {};
 666 #endif
 667
 668 #ifdef CONFIG_ATHEROS_AR71XX
 669 int ath_ahb_init(void);
 670 void ath_ahb_exit(void);
 671 #else
 672 static inline int ath_ahb_init(void) { return 0; };
 673 static inline void ath_ahb_exit(void) {};
 674 #endif
 675
 676 static inline void ath9k_ps_wakeup(struct ath_softc *sc)
 677 {
 678         if (atomic_inc_return(&sc->ps_usecount) == 1)
 679                 if (sc->sc_ah->power_mode !=  ATH9K_PM_AWAKE) {
 680                         sc->sc_ah->restore_mode = sc->sc_ah->power_mode;
 681                         ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
 682                 }
 683 }
 684
 685 static inline void ath9k_ps_restore(struct ath_softc *sc)
 686 {
 687         if (atomic_dec_and_test(&sc->ps_usecount))
 688                 if ((sc->hw->conf.flags & IEEE80211_CONF_PS) &&
 689                     !(sc->sc_flags & (SC_OP_WAIT_FOR_BEACON |
 690                                       SC_OP_WAIT_FOR_CAB |
 691                                       SC_OP_WAIT_FOR_PSPOLL_DATA |
 692                                       SC_OP_WAIT_FOR_TX_ACK)))
 693                         ath9k_hw_setpower(sc->sc_ah,
 694                                           sc->sc_ah->restore_mode);
 695 }
 696
 697
 698 void ath9k_set_bssid_mask(struct ieee80211_hw *hw);
 699 int ath9k_wiphy_add(struct ath_softc *sc);
 700 int ath9k_wiphy_del(struct ath_wiphy *aphy);
 701 void ath9k_tx_status(struct ieee80211_hw *hw, struct sk_buff *skb);
 702 int ath9k_wiphy_pause(struct ath_wiphy *aphy);
 703 int ath9k_wiphy_unpause(struct ath_wiphy *aphy);
 704 int ath9k_wiphy_select(struct ath_wiphy *aphy);
 705 void ath9k_wiphy_set_scheduler(struct ath_softc *sc, unsigned int msec_int);
 706 void ath9k_wiphy_chan_work(struct work_struct *work);
 707 bool ath9k_wiphy_started(struct ath_softc *sc);
 708 void ath9k_wiphy_pause_all_forced(struct ath_softc *sc,
 709                                   struct ath_wiphy *selected);
 710 bool ath9k_wiphy_scanning(struct ath_softc *sc);
 711 void ath9k_wiphy_work(struct work_struct *work);
 712
 713 void ath9k_iowrite32(struct ath_hw *ah, u32 reg_offset, u32 val);
 714 unsigned int ath9k_ioread32(struct ath_hw *ah, u32 reg_offset);
 715
 716 #endif /* ATH9K_H */