drivers/net/wireless/ath/ath9k/ath9k.h

   1 /*
   2  * Copyright (c) 2008-2011 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #ifndef ATH9K_H
  18 #define ATH9K_H
  19
  20 #include <linux/etherdevice.h>
  21 #include <linux/device.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/leds.h>
  24 #include <linux/completion.h>
  25
  26 #include "debug.h"
  27 #include "common.h"
  28 #include "mci.h"
  29 #include "dfs.h"
  30
  31 /*
  32  * Header for the ath9k.ko driver core *only* -- hw code nor any other driver
  33  * should rely on this file or its contents.
  34  */
  35
  36 struct ath_node;
  37
  38 /* Macro to expand scalars to 64-bit objects */
  39
  40 #define ito64(x) (sizeof(x) == 1) ?                     \
  41         (((unsigned long long int)(x)) & (0xff)) :      \
  42         (sizeof(x) == 2) ?                              \
  43         (((unsigned long long int)(x)) & 0xffff) :      \
  44         ((sizeof(x) == 4) ?                             \
  45          (((unsigned long long int)(x)) & 0xffffffff) : \
  46          (unsigned long long int)(x))
  47
  48 /* increment with wrap-around */
  49 #define INCR(_l, _sz)   do {                    \
  50                 (_l)++;                         \
  51                 (_l) &= ((_sz) - 1);            \
  52         } while (0)
  53
  54 /* decrement with wrap-around */
  55 #define DECR(_l,  _sz)  do {                    \
  56                 (_l)--;                         \
  57                 (_l) &= ((_sz) - 1);            \
  58         } while (0)
  59
  60 #define TSF_TO_TU(_h,_l) \
  61         ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
  62
  63 #define ATH_TXQ_SETUP(sc, i)        ((sc)->tx.txqsetup & (1<<i))
  64
  65 struct ath_config {
  66         u16 txpowlimit;
  67         u8 cabqReadytime;
  68 };
  69
  70 /*************************/
  71 /* Descriptor Management */
  72 /*************************/
  73
  74 #define ATH_TXBUF_RESET(_bf) do {                               \
  75                 (_bf)->bf_stale = false;                        \
  76                 (_bf)->bf_lastbf = NULL;                        \
  77                 (_bf)->bf_next = NULL;                          \
  78                 memset(&((_bf)->bf_state), 0,                   \
  79                        sizeof(struct ath_buf_state));           \
  80         } while (0)
  81
  82 #define ATH_RXBUF_RESET(_bf) do {               \
  83                 (_bf)->bf_stale = false;        \
  84         } while (0)
  85
  86 /**
  87  * enum buffer_type - Buffer type flags
  88  *
  89  * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX)
  90  * @BUF_AGGR: Indicates whether the buffer can be aggregated
  91  *      (used in aggregation scheduling)
  92  */
  93 enum buffer_type {
  94         BUF_AMPDU               = BIT(0),
  95         BUF_AGGR                = BIT(1),
  96 };
  97
  98 #define bf_isampdu(bf)          (bf->bf_state.bf_type & BUF_AMPDU)
  99 #define bf_isaggr(bf)           (bf->bf_state.bf_type & BUF_AGGR)
 100
 101 #define ATH_TXSTATUS_RING_SIZE 512
 102
 103 #define DS2PHYS(_dd, _ds)                                               \
 104         ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
 105 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
 106 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
 107
 108 struct ath_descdma {
 109         void *dd_desc;
 110         dma_addr_t dd_desc_paddr;
 111         u32 dd_desc_len;
 112 };
 113
 114 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
 115                       struct list_head *head, const char *name,
 116                       int nbuf, int ndesc, bool is_tx);
 117
 118 /***********/
 119 /* RX / TX */
 120 /***********/
 121
 122 #define ATH_RXBUF               512
 123 #define ATH_TXBUF               512
 124 #define ATH_TXBUF_RESERVE       5
 125 #define ATH_MAX_QDEPTH          (ATH_TXBUF / 4 - ATH_TXBUF_RESERVE)
 126 #define ATH_TXMAXTRY            13
 127
 128 #define TID_TO_WME_AC(_tid)                             \
 129         ((((_tid) == 0) || ((_tid) == 3)) ? IEEE80211_AC_BE :   \
 130          (((_tid) == 1) || ((_tid) == 2)) ? IEEE80211_AC_BK :   \
 131          (((_tid) == 4) || ((_tid) == 5)) ? IEEE80211_AC_VI :   \
 132          IEEE80211_AC_VO)
 133
 134 #define ATH_AGGR_DELIM_SZ          4
 135 #define ATH_AGGR_MINPLEN           256 /* in bytes, minimum packet length */
 136 /* number of delimiters for encryption padding */
 137 #define ATH_AGGR_ENCRYPTDELIM      10
 138 /* minimum h/w qdepth to be sustained to maximize aggregation */
 139 #define ATH_AGGR_MIN_QDEPTH        2
 140 #define ATH_AMPDU_SUBFRAME_DEFAULT 32
 141
 142 #define IEEE80211_SEQ_SEQ_SHIFT    4
 143 #define IEEE80211_SEQ_MAX          4096
 144 #define IEEE80211_WEP_IVLEN        3
 145 #define IEEE80211_WEP_KIDLEN       1
 146 #define IEEE80211_WEP_CRCLEN       4
 147 #define IEEE80211_MAX_MPDU_LEN     (3840 + FCS_LEN +            \
 148                                     (IEEE80211_WEP_IVLEN +      \
 149                                      IEEE80211_WEP_KIDLEN +     \
 150                                      IEEE80211_WEP_CRCLEN))
 151
 152 /* return whether a bit at index _n in bitmap _bm is set
 153  * _sz is the size of the bitmap  */
 154 #define ATH_BA_ISSET(_bm, _n)  (((_n) < (WME_BA_BMP_SIZE)) &&           \
 155                                 ((_bm)[(_n) >> 5] & (1 << ((_n) & 31))))
 156
 157 /* return block-ack bitmap index given sequence and starting sequence */
 158 #define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1))
 159
 160 /* return the seqno for _start + _offset */
 161 #define ATH_BA_INDEX2SEQ(_seq, _offset) (((_seq) + (_offset)) & (IEEE80211_SEQ_MAX - 1))
 162
 163 /* returns delimiter padding required given the packet length */
 164 #define ATH_AGGR_GET_NDELIM(_len)                                       \
 165        (((_len) >= ATH_AGGR_MINPLEN) ? 0 :                             \
 166         DIV_ROUND_UP(ATH_AGGR_MINPLEN - (_len), ATH_AGGR_DELIM_SZ))
 167
 168 #define BAW_WITHIN(_start, _bawsz, _seqno) \
 169         ((((_seqno) - (_start)) & 4095) < (_bawsz))
 170
 171 #define ATH_AN_2_TID(_an, _tidno)  (&(_an)->tid[(_tidno)])
 172
 173 #define IS_CCK_RATE(rate) ((rate >= 0x18) && (rate <= 0x1e))
 174
 175 #define ATH_TX_COMPLETE_POLL_INT        1000
 176
 177 enum ATH_AGGR_STATUS {
 178         ATH_AGGR_DONE,
 179         ATH_AGGR_BAW_CLOSED,
 180         ATH_AGGR_LIMITED,
 181 };
 182
 183 #define ATH_TXFIFO_DEPTH 8
 184 struct ath_txq {
 185         int mac80211_qnum; /* mac80211 queue number, -1 means not mac80211 Q */
 186         u32 axq_qnum; /* ath9k hardware queue number */
 187         void *axq_link;
 188         struct list_head axq_q;
 189         spinlock_t axq_lock;
 190         u32 axq_depth;
 191         u32 axq_ampdu_depth;
 192         bool stopped;
 193         bool axq_tx_inprogress;
 194         struct list_head axq_acq;
 195         struct list_head txq_fifo[ATH_TXFIFO_DEPTH];
 196         u8 txq_headidx;
 197         u8 txq_tailidx;
 198         int pending_frames;
 199         struct sk_buff_head complete_q;
 200 };
 201
 202 struct ath_atx_ac {
 203         struct ath_txq *txq;
 204         int sched;
 205         struct list_head list;
 206         struct list_head tid_q;
 207         bool clear_ps_filter;
 208 };
 209
 210 struct ath_frame_info {
 211         struct ath_buf *bf;
 212         int framelen;
 213         enum ath9k_key_type keytype;
 214         u8 keyix;
 215         u8 retries;
 216         u8 rtscts_rate;
 217 };
 218
 219 struct ath_buf_state {
 220         u8 bf_type;
 221         u8 bfs_paprd;
 222         u8 ndelim;
 223         u16 seqno;
 224         unsigned long bfs_paprd_timestamp;
 225 };
 226
 227 struct ath_buf {
 228         struct list_head list;
 229         struct ath_buf *bf_lastbf;      /* last buf of this unit (a frame or
 230                                            an aggregate) */
 231         struct ath_buf *bf_next;        /* next subframe in the aggregate */
 232         struct sk_buff *bf_mpdu;        /* enclosing frame structure */
 233         void *bf_desc;                  /* virtual addr of desc */
 234         dma_addr_t bf_daddr;            /* physical addr of desc */
 235         dma_addr_t bf_buf_addr; /* physical addr of data buffer, for DMA */
 236         bool bf_stale;
 237         struct ath_buf_state bf_state;
 238 };
 239
 240 struct ath_atx_tid {
 241         struct list_head list;
 242         struct sk_buff_head buf_q;
 243         struct ath_node *an;
 244         struct ath_atx_ac *ac;
 245         unsigned long tx_buf[BITS_TO_LONGS(ATH_TID_MAX_BUFS)];
 246         int bar_index;
 247         u16 seq_start;
 248         u16 seq_next;
 249         u16 baw_size;
 250         int tidno;
 251         int baw_head;   /* first un-acked tx buffer */
 252         int baw_tail;   /* next unused tx buffer slot */
 253         int sched;
 254         int paused;
 255         u8 state;
 256 };
 257
 258 struct ath_node {
 259         struct ath_softc *sc;
 260         struct ieee80211_sta *sta; /* station struct we're part of */
 261         struct ieee80211_vif *vif; /* interface with which we're associated */
 262         struct ath_atx_tid tid[IEEE80211_NUM_TIDS];
 263         struct ath_atx_ac ac[IEEE80211_NUM_ACS];
 264         int ps_key;
 265
 266         u16 maxampdu;
 267         u8 mpdudensity;
 268
 269         bool sleeping;
 270
 271 #if defined(CONFIG_MAC80211_DEBUGFS) && defined(CONFIG_ATH9K_DEBUGFS)
 272         struct dentry *node_stat;
 273 #endif
 274 };
 275
 276 #define AGGR_CLEANUP         BIT(1)
 277 #define AGGR_ADDBA_COMPLETE  BIT(2)
 278 #define AGGR_ADDBA_PROGRESS  BIT(3)
 279
 280 struct ath_tx_control {
 281         struct ath_txq *txq;
 282         struct ath_node *an;
 283         u8 paprd;
 284         struct ieee80211_sta *sta;
 285 };
 286
 287 #define ATH_TX_ERROR        0x01
 288
 289 /**
 290  * @txq_map:  Index is mac80211 queue number.  This is
 291  *  not necessarily the same as the hardware queue number
 292  *  (axq_qnum).
 293  */
 294 struct ath_tx {
 295         u16 seq_no;
 296         u32 txqsetup;
 297         spinlock_t txbuflock;
 298         struct list_head txbuf;
 299         struct ath_txq txq[ATH9K_NUM_TX_QUEUES];
 300         struct ath_descdma txdma;
 301         struct ath_txq *txq_map[IEEE80211_NUM_ACS];
 302         u32 txq_max_pending[IEEE80211_NUM_ACS];
 303         u16 max_aggr_framelen[IEEE80211_NUM_ACS][4][32];
 304 };
 305
 306 struct ath_rx_edma {
 307         struct sk_buff_head rx_fifo;
 308         u32 rx_fifo_hwsize;
 309 };
 310
 311 struct ath_rx {
 312         u8 defant;
 313         u8 rxotherant;
 314         u32 *rxlink;
 315         u32 num_pkts;
 316         unsigned int rxfilter;
 317         spinlock_t rxbuflock;
 318         struct list_head rxbuf;
 319         struct ath_descdma rxdma;
 320         struct ath_rx_edma rx_edma[ATH9K_RX_QUEUE_MAX];
 321
 322         struct sk_buff *frag;
 323 };
 324
 325 int ath_startrecv(struct ath_softc *sc);
 326 bool ath_stoprecv(struct ath_softc *sc);
 327 void ath_flushrecv(struct ath_softc *sc);
 328 u32 ath_calcrxfilter(struct ath_softc *sc);
 329 int ath_rx_init(struct ath_softc *sc, int nbufs);
 330 void ath_rx_cleanup(struct ath_softc *sc);
 331 int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp);
 332 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
 333 void ath_txq_lock(struct ath_softc *sc, struct ath_txq *txq);
 334 void ath_txq_unlock(struct ath_softc *sc, struct ath_txq *txq);
 335 void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq);
 336 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
 337 bool ath_drain_all_txq(struct ath_softc *sc, bool retry_tx);
 338 void ath_draintxq(struct ath_softc *sc,
 339                      struct ath_txq *txq, bool retry_tx);
 340 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an);
 341 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an);
 342 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq);
 343 int ath_tx_init(struct ath_softc *sc, int nbufs);
 344 int ath_txq_update(struct ath_softc *sc, int qnum,
 345                    struct ath9k_tx_queue_info *q);
 346 void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop);
 347 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
 348                  struct ath_tx_control *txctl);
 349 void ath_tx_tasklet(struct ath_softc *sc);
 350 void ath_tx_edma_tasklet(struct ath_softc *sc);
 351 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
 352                       u16 tid, u16 *ssn);
 353 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
 354 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
 355
 356 void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an);
 357 void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc,
 358                        struct ath_node *an);
 359
 360 /********/
 361 /* VIFs */
 362 /********/
 363
 364 struct ath_vif {
 365         int av_bslot;
 366         bool primary_sta_vif;
 367         __le64 tsf_adjust; /* TSF adjustment for staggered beacons */
 368         struct ath_buf *av_bcbuf;
 369 };
 370
 371 /*******************/
 372 /* Beacon Handling */
 373 /*******************/
 374
 375 /*
 376  * Regardless of the number of beacons we stagger, (i.e. regardless of the
 377  * number of BSSIDs) if a given beacon does not go out even after waiting this
 378  * number of beacon intervals, the game's up.
 379  */
 380 #define BSTUCK_THRESH                   9
 381 #define ATH_BCBUF                       8
 382 #define ATH_DEFAULT_BINTVAL             100 /* TU */
 383 #define ATH_DEFAULT_BMISS_LIMIT         10
 384 #define IEEE80211_MS_TO_TU(x)           (((x) * 1000) / 1024)
 385
 386 struct ath_beacon_config {
 387         int beacon_interval;
 388         u16 listen_interval;
 389         u16 dtim_period;
 390         u16 bmiss_timeout;
 391         u8 dtim_count;
 392         bool enable_beacon;
 393 };
 394
 395 struct ath_beacon {
 396         enum {
 397                 OK,             /* no change needed */
 398                 UPDATE,         /* update pending */
 399                 COMMIT          /* beacon sent, commit change */
 400         } updateslot;           /* slot time update fsm */
 401
 402         u32 beaconq;
 403         u32 bmisscnt;
 404         u32 bc_tstamp;
 405         struct ieee80211_vif *bslot[ATH_BCBUF];
 406         int slottime;
 407         int slotupdate;
 408         struct ath9k_tx_queue_info beacon_qi;
 409         struct ath_descdma bdma;
 410         struct ath_txq *cabq;
 411         struct list_head bbuf;
 412
 413         bool tx_processed;
 414         bool tx_last;
 415 };
 416
 417 void ath9k_beacon_tasklet(unsigned long data);
 418 bool ath9k_allow_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif);
 419 void ath9k_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif,
 420                          u32 changed);
 421 void ath9k_beacon_assign_slot(struct ath_softc *sc, struct ieee80211_vif *vif);
 422 void ath9k_beacon_remove_slot(struct ath_softc *sc, struct ieee80211_vif *vif);
 423 void ath9k_set_tsfadjust(struct ath_softc *sc, struct ieee80211_vif *vif);
 424 void ath9k_set_beacon(struct ath_softc *sc);
 425
 426 /*******************/
 427 /* Link Monitoring */
 428 /*******************/
 429
 430 #define ATH_STA_SHORT_CALINTERVAL 1000    /* 1 second */
 431 #define ATH_AP_SHORT_CALINTERVAL  100     /* 100 ms */
 432 #define ATH_ANI_POLLINTERVAL_OLD  100     /* 100 ms */
 433 #define ATH_ANI_POLLINTERVAL_NEW  1000    /* 1000 ms */
 434 #define ATH_LONG_CALINTERVAL_INT  1000    /* 1000 ms */
 435 #define ATH_LONG_CALINTERVAL      30000   /* 30 seconds */
 436 #define ATH_RESTART_CALINTERVAL   1200000 /* 20 minutes */
 437 #define ATH_ANI_MAX_SKIP_COUNT  10
 438
 439 #define ATH_PAPRD_TIMEOUT       100 /* msecs */
 440 #define ATH_PLL_WORK_INTERVAL   100
 441
 442 void ath_tx_complete_poll_work(struct work_struct *work);
 443 void ath_reset_work(struct work_struct *work);
 444 void ath_hw_check(struct work_struct *work);
 445 void ath_hw_pll_work(struct work_struct *work);
 446 void ath_rx_poll(unsigned long data);
 447 void ath_start_rx_poll(struct ath_softc *sc, u8 nbeacon);
 448 void ath_paprd_calibrate(struct work_struct *work);
 449 void ath_ani_calibrate(unsigned long data);
 450 void ath_start_ani(struct ath_softc *sc);
 451 void ath_stop_ani(struct ath_softc *sc);
 452 void ath_check_ani(struct ath_softc *sc);
 453 int ath_update_survey_stats(struct ath_softc *sc);
 454 void ath_update_survey_nf(struct ath_softc *sc, int channel);
 455 void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type);
 456
 457 /**********/
 458 /* BTCOEX */
 459 /**********/
 460
 461 #define ATH_DUMP_BTCOEX(_s, _val)                               \
 462         do {                                                    \
 463                 len += snprintf(buf + len, size - len,          \
 464                                 "%20s : %10d\n", _s, (_val));   \
 465         } while (0)
 466
 467 enum bt_op_flags {
 468         BT_OP_PRIORITY_DETECTED,
 469         BT_OP_SCAN,
 470 };
 471
 472 struct ath_btcoex {
 473         bool hw_timer_enabled;
 474         spinlock_t btcoex_lock;
 475         struct timer_list period_timer; /* Timer for BT period */
 476         u32 bt_priority_cnt;
 477         unsigned long bt_priority_time;
 478         unsigned long op_flags;
 479         int bt_stomp_type; /* Types of BT stomping */
 480         u32 btcoex_no_stomp; /* in usec */
 481         u32 btcoex_period; /* in msec */
 482         u32 btscan_no_stomp; /* in usec */
 483         u32 duty_cycle;
 484         u32 bt_wait_time;
 485         int rssi_count;
 486         struct ath_gen_timer *no_stomp_timer; /* Timer for no BT stomping */
 487         struct ath_mci_profile mci;
 488         u8 stomp_audio;
 489 };
 490
 491 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
 492 int ath9k_init_btcoex(struct ath_softc *sc);
 493 void ath9k_deinit_btcoex(struct ath_softc *sc);
 494 void ath9k_start_btcoex(struct ath_softc *sc);
 495 void ath9k_stop_btcoex(struct ath_softc *sc);
 496 void ath9k_btcoex_timer_resume(struct ath_softc *sc);
 497 void ath9k_btcoex_timer_pause(struct ath_softc *sc);
 498 void ath9k_btcoex_handle_interrupt(struct ath_softc *sc, u32 status);
 499 u16 ath9k_btcoex_aggr_limit(struct ath_softc *sc, u32 max_4ms_framelen);
 500 void ath9k_btcoex_stop_gen_timer(struct ath_softc *sc);
 501 int ath9k_dump_btcoex(struct ath_softc *sc, u8 *buf, u32 size);
 502 #else
 503 static inline int ath9k_init_btcoex(struct ath_softc *sc)
 504 {
 505         return 0;
 506 }
 507 static inline void ath9k_deinit_btcoex(struct ath_softc *sc)
 508 {
 509 }
 510 static inline void ath9k_start_btcoex(struct ath_softc *sc)
 511 {
 512 }
 513 static inline void ath9k_stop_btcoex(struct ath_softc *sc)
 514 {
 515 }
 516 static inline void ath9k_btcoex_handle_interrupt(struct ath_softc *sc,
 517                                                  u32 status)
 518 {
 519 }
 520 static inline u16 ath9k_btcoex_aggr_limit(struct ath_softc *sc,
 521                                           u32 max_4ms_framelen)
 522 {
 523         return 0;
 524 }
 525 static inline void ath9k_btcoex_stop_gen_timer(struct ath_softc *sc)
 526 {
 527 }
 528 static inline int ath9k_dump_btcoex(struct ath_softc *sc, u8 *buf, u32 size)
 529 {
 530         return 0;
 531 }
 532 #endif /* CONFIG_ATH9K_BTCOEX_SUPPORT */
 533
 534 struct ath9k_wow_pattern {
 535         u8 pattern_bytes[MAX_PATTERN_SIZE];
 536         u8 mask_bytes[MAX_PATTERN_SIZE];
 537         u32 pattern_len;
 538 };
 539
 540 /********************/
 541 /*   LED Control    */
 542 /********************/
 543
 544 #define ATH_LED_PIN_DEF                 1
 545 #define ATH_LED_PIN_9287                8
 546 #define ATH_LED_PIN_9300                10
 547 #define ATH_LED_PIN_9485                6
 548 #define ATH_LED_PIN_9462                4
 549
 550 #ifdef CONFIG_MAC80211_LEDS
 551 void ath_init_leds(struct ath_softc *sc);
 552 void ath_deinit_leds(struct ath_softc *sc);
 553 void ath_fill_led_pin(struct ath_softc *sc);
 554 #else
 555 static inline void ath_init_leds(struct ath_softc *sc)
 556 {
 557 }
 558
 559 static inline void ath_deinit_leds(struct ath_softc *sc)
 560 {
 561 }
 562 static inline void ath_fill_led_pin(struct ath_softc *sc)
 563 {
 564 }
 565 #endif
 566
 567 /*******************************/
 568 /* Antenna diversity/combining */
 569 /*******************************/
 570
 571 #define ATH_ANT_RX_CURRENT_SHIFT 4
 572 #define ATH_ANT_RX_MAIN_SHIFT 2
 573 #define ATH_ANT_RX_MASK 0x3
 574
 575 #define ATH_ANT_DIV_COMB_SHORT_SCAN_INTR 50
 576 #define ATH_ANT_DIV_COMB_SHORT_SCAN_PKTCOUNT 0x100
 577 #define ATH_ANT_DIV_COMB_MAX_PKTCOUNT 0x200
 578 #define ATH_ANT_DIV_COMB_INIT_COUNT 95
 579 #define ATH_ANT_DIV_COMB_MAX_COUNT 100
 580 #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO 30
 581 #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO2 20
 582
 583 #define ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA -1
 584 #define ATH_ANT_DIV_COMB_LNA1_DELTA_HI -4
 585 #define ATH_ANT_DIV_COMB_LNA1_DELTA_MID -2
 586 #define ATH_ANT_DIV_COMB_LNA1_DELTA_LOW 2
 587
 588 enum ath9k_ant_div_comb_lna_conf {
 589         ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2,
 590         ATH_ANT_DIV_COMB_LNA2,
 591         ATH_ANT_DIV_COMB_LNA1,
 592         ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2,
 593 };
 594
 595 struct ath_ant_comb {
 596         u16 count;
 597         u16 total_pkt_count;
 598         bool scan;
 599         bool scan_not_start;
 600         int main_total_rssi;
 601         int alt_total_rssi;
 602         int alt_recv_cnt;
 603         int main_recv_cnt;
 604         int rssi_lna1;
 605         int rssi_lna2;
 606         int rssi_add;
 607         int rssi_sub;
 608         int rssi_first;
 609         int rssi_second;
 610         int rssi_third;
 611         bool alt_good;
 612         int quick_scan_cnt;
 613         int main_conf;
 614         enum ath9k_ant_div_comb_lna_conf first_quick_scan_conf;
 615         enum ath9k_ant_div_comb_lna_conf second_quick_scan_conf;
 616         bool first_ratio;
 617         bool second_ratio;
 618         unsigned long scan_start_time;
 619 };
 620
 621 void ath_ant_comb_scan(struct ath_softc *sc, struct ath_rx_status *rs);
 622 void ath_ant_comb_update(struct ath_softc *sc);
 623
 624 /********************/
 625 /* Main driver core */
 626 /********************/
 627
 628 /*
 629  * Default cache line size, in bytes.
 630  * Used when PCI device not fully initialized by bootrom/BIOS
 631 */
 632 #define DEFAULT_CACHELINE       32
 633 #define ATH_REGCLASSIDS_MAX     10
 634 #define ATH_CABQ_READY_TIME     80      /* % of beacon interval */
 635 #define ATH_MAX_SW_RETRIES      30
 636 #define ATH_CHAN_MAX            255
 637
 638 #define ATH_TXPOWER_MAX         100     /* .5 dBm units */
 639 #define ATH_RATE_DUMMY_MARKER   0
 640
 641 enum sc_op_flags {
 642         SC_OP_INVALID,
 643         SC_OP_BEACONS,
 644         SC_OP_RXFLUSH,
 645         SC_OP_ANI_RUN,
 646         SC_OP_PRIM_STA_VIF,
 647         SC_OP_HW_RESET,
 648 };
 649
 650 /* Powersave flags */
 651 #define PS_WAIT_FOR_BEACON        BIT(0)
 652 #define PS_WAIT_FOR_CAB           BIT(1)
 653 #define PS_WAIT_FOR_PSPOLL_DATA   BIT(2)
 654 #define PS_WAIT_FOR_TX_ACK        BIT(3)
 655 #define PS_BEACON_SYNC            BIT(4)
 656 #define PS_WAIT_FOR_ANI           BIT(5)
 657
 658 struct ath_rate_table;
 659
 660 struct ath9k_vif_iter_data {
 661         const u8 *hw_macaddr; /* phy's hardware address, set
 662                                * before starting iteration for
 663                                * valid bssid mask.
 664                                */
 665         u8 mask[ETH_ALEN]; /* bssid mask */
 666         int naps;      /* number of AP vifs */
 667         int nmeshes;   /* number of mesh vifs */
 668         int nstations; /* number of station vifs */
 669         int nwds;      /* number of WDS vifs */
 670         int nadhocs;   /* number of adhoc vifs */
 671 };
 672
 673 struct ath_softc {
 674         struct ieee80211_hw *hw;
 675         struct device *dev;
 676
 677         struct survey_info *cur_survey;
 678         struct survey_info survey[ATH9K_NUM_CHANNELS];
 679
 680         struct tasklet_struct intr_tq;
 681         struct tasklet_struct bcon_tasklet;
 682         struct ath_hw *sc_ah;
 683         void __iomem *mem;
 684         int irq;
 685         spinlock_t sc_serial_rw;
 686         spinlock_t sc_pm_lock;
 687         spinlock_t sc_pcu_lock;
 688         struct mutex mutex;
 689         struct work_struct paprd_work;
 690         struct work_struct hw_check_work;
 691         struct work_struct hw_reset_work;
 692         struct completion paprd_complete;
 693
 694         unsigned int hw_busy_count;
 695         unsigned long sc_flags;
 696
 697         u32 intrstatus;
 698         u16 ps_flags; /* PS_* */
 699         u16 curtxpow;
 700         bool ps_enabled;
 701         bool ps_idle;
 702         short nbcnvifs;
 703         short nvifs;
 704         unsigned long ps_usecount;
 705
 706         struct ath_config config;
 707         struct ath_rx rx;
 708         struct ath_tx tx;
 709         struct ath_beacon beacon;
 710         struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
 711
 712 #ifdef CONFIG_MAC80211_LEDS
 713         bool led_registered;
 714         char led_name[32];
 715         struct led_classdev led_cdev;
 716 #endif
 717
 718         struct ath9k_hw_cal_data caldata;
 719         int last_rssi;
 720
 721 #ifdef CONFIG_ATH9K_DEBUGFS
 722         struct ath9k_debug debug;
 723 #endif
 724         struct ath_beacon_config cur_beacon_conf;
 725         struct delayed_work tx_complete_work;
 726         struct delayed_work hw_pll_work;
 727         struct timer_list rx_poll_timer;
 728
 729 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
 730         struct ath_btcoex btcoex;
 731         struct ath_mci_coex mci_coex;
 732         struct work_struct mci_work;
 733 #endif
 734
 735         struct ath_descdma txsdma;
 736
 737         struct ath_ant_comb ant_comb;
 738         u8 ant_tx, ant_rx;
 739         struct dfs_pattern_detector *dfs_detector;
 740         u32 wow_enabled;
 741
 742 #ifdef CONFIG_PM_SLEEP
 743         atomic_t wow_got_bmiss_intr;
 744         atomic_t wow_sleep_proc_intr; /* in the middle of WoW sleep ? */
 745         u32 wow_intr_before_sleep;
 746 #endif
 747 };
 748
 749 void ath9k_tasklet(unsigned long data);
 750 int ath_cabq_update(struct ath_softc *);
 751
 752 static inline void ath_read_cachesize(struct ath_common *common, int *csz)
 753 {
 754         common->bus_ops->read_cachesize(common, csz);
 755 }
 756
 757 extern struct ieee80211_ops ath9k_ops;
 758 extern int ath9k_modparam_nohwcrypt;
 759 extern int led_blink;
 760 extern bool is_ath9k_unloaded;
 761
 762 u8 ath9k_parse_mpdudensity(u8 mpdudensity);
 763 irqreturn_t ath_isr(int irq, void *dev);
 764 int ath9k_init_device(u16 devid, struct ath_softc *sc,
 765                     const struct ath_bus_ops *bus_ops);
 766 void ath9k_deinit_device(struct ath_softc *sc);
 767 void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw);
 768 void ath9k_reload_chainmask_settings(struct ath_softc *sc);
 769
 770 bool ath9k_uses_beacons(int type);
 771
 772 #ifdef CONFIG_ATH9K_PCI
 773 int ath_pci_init(void);
 774 void ath_pci_exit(void);
 775 #else
 776 static inline int ath_pci_init(void) { return 0; };
 777 static inline void ath_pci_exit(void) {};
 778 #endif
 779
 780 #ifdef CONFIG_ATH9K_AHB
 781 int ath_ahb_init(void);
 782 void ath_ahb_exit(void);
 783 #else
 784 static inline int ath_ahb_init(void) { return 0; };
 785 static inline void ath_ahb_exit(void) {};
 786 #endif
 787
 788 void ath9k_ps_wakeup(struct ath_softc *sc);
 789 void ath9k_ps_restore(struct ath_softc *sc);
 790
 791 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate);
 792
 793 void ath_start_rfkill_poll(struct ath_softc *sc);
 794 extern void ath9k_rfkill_poll_state(struct ieee80211_hw *hw);
 795 void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
 796                                struct ieee80211_vif *vif,
 797                                struct ath9k_vif_iter_data *iter_data);
 798
 799 #endif /* ATH9K_H */