drivers/net/wireless/ath/ath9k/ath9k.h

   1 /*
   2  * Copyright (c) 2008-2009 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #ifndef ATH9K_H
  18 #define ATH9K_H
  19
  20 #include <linux/etherdevice.h>
  21 #include <linux/device.h>
  22 #include <net/mac80211.h>
  23 #include <linux/leds.h>
  24
  25 #include "hw.h"
  26 #include "rc.h"
  27 #include "debug.h"
  28
  29 struct ath_node;
  30
  31 /* Macro to expand scalars to 64-bit objects */
  32
  33 #define ito64(x) (sizeof(x) == 8) ?                     \
  34         (((unsigned long long int)(x)) & (0xff)) :      \
  35         (sizeof(x) == 16) ?                             \
  36         (((unsigned long long int)(x)) & 0xffff) :      \
  37         ((sizeof(x) == 32) ?                            \
  38          (((unsigned long long int)(x)) & 0xffffffff) : \
  39          (unsigned long long int)(x))
  40
  41 /* increment with wrap-around */
  42 #define INCR(_l, _sz)   do {                    \
  43                 (_l)++;                         \
  44                 (_l) &= ((_sz) - 1);            \
  45         } while (0)
  46
  47 /* decrement with wrap-around */
  48 #define DECR(_l,  _sz)  do {                    \
  49                 (_l)--;                         \
  50                 (_l) &= ((_sz) - 1);            \
  51         } while (0)
  52
  53 #define A_MAX(a, b) ((a) > (b) ? (a) : (b))
  54
  55 #define ASSERT(exp) BUG_ON(!(exp))
  56
  57 #define TSF_TO_TU(_h,_l) \
  58         ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
  59
  60 #define ATH_TXQ_SETUP(sc, i)        ((sc)->tx.txqsetup & (1<<i))
  61
  62 static const u8 ath_bcast_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
  63
  64 struct ath_config {
  65         u32 ath_aggr_prot;
  66         u16 txpowlimit;
  67         u8 cabqReadytime;
  68 };
  69
  70 /*************************/
  71 /* Descriptor Management */
  72 /*************************/
  73
  74 #define ATH_TXBUF_RESET(_bf) do {                               \
  75                 (_bf)->bf_stale = false;                        \
  76                 (_bf)->bf_lastbf = NULL;                        \
  77                 (_bf)->bf_next = NULL;                          \
  78                 memset(&((_bf)->bf_state), 0,                   \
  79                        sizeof(struct ath_buf_state));           \
  80         } while (0)
  81
  82 #define ATH_RXBUF_RESET(_bf) do {               \
  83                 (_bf)->bf_stale = false;        \
  84         } while (0)
  85
  86 /**
  87  * enum buffer_type - Buffer type flags
  88  *
  89  * @BUF_HT: Send this buffer using HT capabilities
  90  * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX)
  91  * @BUF_AGGR: Indicates whether the buffer can be aggregated
  92  *      (used in aggregation scheduling)
  93  * @BUF_RETRY: Indicates whether the buffer is retried
  94  * @BUF_XRETRY: To denote excessive retries of the buffer
  95  */
  96 enum buffer_type {
  97         BUF_HT                  = BIT(1),
  98         BUF_AMPDU               = BIT(2),
  99         BUF_AGGR                = BIT(3),
 100         BUF_RETRY               = BIT(4),
 101         BUF_XRETRY              = BIT(5),
 102 };
 103
 104 struct ath_buf_state {
 105         int bfs_nframes;
 106         u16 bfs_al;
 107         u16 bfs_frmlen;
 108         int bfs_seqno;
 109         int bfs_tidno;
 110         int bfs_retries;
 111         u8 bf_type;
 112         u32 bfs_keyix;
 113         enum ath9k_key_type bfs_keytype;
 114 };
 115
 116 #define bf_nframes              bf_state.bfs_nframes
 117 #define bf_al                   bf_state.bfs_al
 118 #define bf_frmlen               bf_state.bfs_frmlen
 119 #define bf_retries              bf_state.bfs_retries
 120 #define bf_seqno                bf_state.bfs_seqno
 121 #define bf_tidno                bf_state.bfs_tidno
 122 #define bf_keyix                bf_state.bfs_keyix
 123 #define bf_keytype              bf_state.bfs_keytype
 124 #define bf_isht(bf)             (bf->bf_state.bf_type & BUF_HT)
 125 #define bf_isampdu(bf)          (bf->bf_state.bf_type & BUF_AMPDU)
 126 #define bf_isaggr(bf)           (bf->bf_state.bf_type & BUF_AGGR)
 127 #define bf_isretried(bf)        (bf->bf_state.bf_type & BUF_RETRY)
 128 #define bf_isxretried(bf)       (bf->bf_state.bf_type & BUF_XRETRY)
 129
 130 struct ath_buf {
 131         struct list_head list;
 132         struct ath_buf *bf_lastbf;      /* last buf of this unit (a frame or
 133                                            an aggregate) */
 134         struct ath_buf *bf_next;        /* next subframe in the aggregate */
 135         struct sk_buff *bf_mpdu;        /* enclosing frame structure */
 136         struct ath_desc *bf_desc;       /* virtual addr of desc */
 137         dma_addr_t bf_daddr;            /* physical addr of desc */
 138         dma_addr_t bf_buf_addr;         /* physical addr of data buffer */
 139         bool bf_stale;
 140         u16 bf_flags;
 141         struct ath_buf_state bf_state;
 142         dma_addr_t bf_dmacontext;
 143 };
 144
 145 struct ath_descdma {
 146         struct ath_desc *dd_desc;
 147         dma_addr_t dd_desc_paddr;
 148         u32 dd_desc_len;
 149         struct ath_buf *dd_bufptr;
 150 };
 151
 152 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
 153                       struct list_head *head, const char *name,
 154                       int nbuf, int ndesc);
 155 void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd,
 156                          struct list_head *head);
 157
 158 /***********/
 159 /* RX / TX */
 160 /***********/
 161
 162 #define ATH_MAX_ANTENNA         3
 163 #define ATH_RXBUF               512
 164 #define WME_NUM_TID             16
 165 #define ATH_TXBUF               512
 166 #define ATH_TXMAXTRY            13
 167 #define ATH_11N_TXMAXTRY        10
 168 #define ATH_MGT_TXMAXTRY        4
 169 #define WME_BA_BMP_SIZE         64
 170 #define WME_MAX_BA              WME_BA_BMP_SIZE
 171 #define ATH_TID_MAX_BUFS        (2 * WME_MAX_BA)
 172
 173 #define TID_TO_WME_AC(_tid)                             \
 174         ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \
 175          (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \
 176          (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \
 177          WME_AC_VO)
 178
 179 #define WME_AC_BE   0
 180 #define WME_AC_BK   1
 181 #define WME_AC_VI   2
 182 #define WME_AC_VO   3
 183 #define WME_NUM_AC  4
 184
 185 #define ADDBA_EXCHANGE_ATTEMPTS    10
 186 #define ATH_AGGR_DELIM_SZ          4
 187 #define ATH_AGGR_MINPLEN           256 /* in bytes, minimum packet length */
 188 /* number of delimiters for encryption padding */
 189 #define ATH_AGGR_ENCRYPTDELIM      10
 190 /* minimum h/w qdepth to be sustained to maximize aggregation */
 191 #define ATH_AGGR_MIN_QDEPTH        2
 192 #define ATH_AMPDU_SUBFRAME_DEFAULT 32
 193 #define ATH_AMPDU_LIMIT_MAX        (64 * 1024 - 1)
 194 #define ATH_AMPDU_LIMIT_DEFAULT    ATH_AMPDU_LIMIT_MAX
 195
 196 #define IEEE80211_SEQ_SEQ_SHIFT    4
 197 #define IEEE80211_SEQ_MAX          4096
 198 #define IEEE80211_MIN_AMPDU_BUF    0x8
 199 #define IEEE80211_HTCAP_MAXRXAMPDU_FACTOR 13
 200 #define IEEE80211_WEP_IVLEN        3
 201 #define IEEE80211_WEP_KIDLEN       1
 202 #define IEEE80211_WEP_CRCLEN       4
 203 #define IEEE80211_MAX_MPDU_LEN     (3840 + FCS_LEN +            \
 204                                     (IEEE80211_WEP_IVLEN +      \
 205                                      IEEE80211_WEP_KIDLEN +     \
 206                                      IEEE80211_WEP_CRCLEN))
 207
 208 /* return whether a bit at index _n in bitmap _bm is set
 209  * _sz is the size of the bitmap  */
 210 #define ATH_BA_ISSET(_bm, _n)  (((_n) < (WME_BA_BMP_SIZE)) &&           \
 211                                 ((_bm)[(_n) >> 5] & (1 << ((_n) & 31))))
 212
 213 /* return block-ack bitmap index given sequence and starting sequence */
 214 #define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1))
 215
 216 /* returns delimiter padding required given the packet length */
 217 #define ATH_AGGR_GET_NDELIM(_len)                                       \
 218         (((((_len) + ATH_AGGR_DELIM_SZ) < ATH_AGGR_MINPLEN) ?           \
 219           (ATH_AGGR_MINPLEN - (_len) - ATH_AGGR_DELIM_SZ) : 0) >> 2)
 220
 221 #define BAW_WITHIN(_start, _bawsz, _seqno) \
 222         ((((_seqno) - (_start)) & 4095) < (_bawsz))
 223
 224 #define ATH_DS_BA_SEQ(_ds)         ((_ds)->ds_us.tx.ts_seqnum)
 225 #define ATH_DS_BA_BITMAP(_ds)      (&(_ds)->ds_us.tx.ba_low)
 226 #define ATH_DS_TX_BA(_ds)          ((_ds)->ds_us.tx.ts_flags & ATH9K_TX_BA)
 227 #define ATH_AN_2_TID(_an, _tidno)  (&(_an)->tid[(_tidno)])
 228
 229 enum ATH_AGGR_STATUS {
 230         ATH_AGGR_DONE,
 231         ATH_AGGR_BAW_CLOSED,
 232         ATH_AGGR_LIMITED,
 233 };
 234
 235 struct ath_txq {
 236         u32 axq_qnum;
 237         u32 *axq_link;
 238         struct list_head axq_q;
 239         spinlock_t axq_lock;
 240         u32 axq_depth;
 241         u8 axq_aggr_depth;
 242         u32 axq_totalqueued;
 243         bool stopped;
 244         struct ath_buf *axq_linkbuf;
 245
 246         /* first desc of the last descriptor that contains CTS */
 247         struct ath_desc *axq_lastdsWithCTS;
 248
 249         /* final desc of the gating desc that determines whether
 250            lastdsWithCTS has been DMA'ed or not */
 251         struct ath_desc *axq_gatingds;
 252
 253         struct list_head axq_acq;
 254 };
 255
 256 #define AGGR_CLEANUP         BIT(1)
 257 #define AGGR_ADDBA_COMPLETE  BIT(2)
 258 #define AGGR_ADDBA_PROGRESS  BIT(3)
 259
 260 struct ath_atx_tid {
 261         struct list_head list;
 262         struct list_head buf_q;
 263         struct ath_node *an;
 264         struct ath_atx_ac *ac;
 265         struct ath_buf *tx_buf[ATH_TID_MAX_BUFS];
 266         u16 seq_start;
 267         u16 seq_next;
 268         u16 baw_size;
 269         int tidno;
 270         int baw_head;   /* first un-acked tx buffer */
 271         int baw_tail;   /* next unused tx buffer slot */
 272         int sched;
 273         int paused;
 274         u8 state;
 275 };
 276
 277 struct ath_atx_ac {
 278         int sched;
 279         int qnum;
 280         struct list_head list;
 281         struct list_head tid_q;
 282 };
 283
 284 struct ath_tx_control {
 285         struct ath_txq *txq;
 286         int if_id;
 287         enum ath9k_internal_frame_type frame_type;
 288 };
 289
 290 #define ATH_TX_ERROR        0x01
 291 #define ATH_TX_XRETRY       0x02
 292 #define ATH_TX_BAR          0x04
 293
 294 struct ath_node {
 295         struct ath_softc *an_sc;
 296         struct ath_atx_tid tid[WME_NUM_TID];
 297         struct ath_atx_ac ac[WME_NUM_AC];
 298         u16 maxampdu;
 299         u8 mpdudensity;
 300 };
 301
 302 struct ath_tx {
 303         u16 seq_no;
 304         u32 txqsetup;
 305         int hwq_map[ATH9K_WME_AC_VO+1];
 306         spinlock_t txbuflock;
 307         struct list_head txbuf;
 308         struct ath_txq txq[ATH9K_NUM_TX_QUEUES];
 309         struct ath_descdma txdma;
 310 };
 311
 312 struct ath_rx {
 313         u8 defant;
 314         u8 rxotherant;
 315         u32 *rxlink;
 316         int bufsize;
 317         unsigned int rxfilter;
 318         spinlock_t rxflushlock;
 319         spinlock_t rxbuflock;
 320         struct list_head rxbuf;
 321         struct ath_descdma rxdma;
 322 };
 323
 324 int ath_startrecv(struct ath_softc *sc);
 325 bool ath_stoprecv(struct ath_softc *sc);
 326 void ath_flushrecv(struct ath_softc *sc);
 327 u32 ath_calcrxfilter(struct ath_softc *sc);
 328 int ath_rx_init(struct ath_softc *sc, int nbufs);
 329 void ath_rx_cleanup(struct ath_softc *sc);
 330 int ath_rx_tasklet(struct ath_softc *sc, int flush);
 331 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
 332 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
 333 int ath_tx_setup(struct ath_softc *sc, int haltype);
 334 void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx);
 335 void ath_draintxq(struct ath_softc *sc,
 336                      struct ath_txq *txq, bool retry_tx);
 337 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an);
 338 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an);
 339 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq);
 340 int ath_tx_init(struct ath_softc *sc, int nbufs);
 341 void ath_tx_cleanup(struct ath_softc *sc);
 342 struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb);
 343 int ath_txq_update(struct ath_softc *sc, int qnum,
 344                    struct ath9k_tx_queue_info *q);
 345 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
 346                  struct ath_tx_control *txctl);
 347 void ath_tx_tasklet(struct ath_softc *sc);
 348 void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb);
 349 bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno);
 350 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
 351                       u16 tid, u16 *ssn);
 352 int ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
 353 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
 354
 355 /********/
 356 /* VIFs */
 357 /********/
 358
 359 struct ath_vif {
 360         int av_bslot;
 361         __le64 tsf_adjust; /* TSF adjustment for staggered beacons */
 362         enum nl80211_iftype av_opmode;
 363         struct ath_buf *av_bcbuf;
 364         struct ath_tx_control av_btxctl;
 365         u8 bssid[ETH_ALEN]; /* current BSSID from config_interface */
 366 };
 367
 368 /*******************/
 369 /* Beacon Handling */
 370 /*******************/
 371
 372 /*
 373  * Regardless of the number of beacons we stagger, (i.e. regardless of the
 374  * number of BSSIDs) if a given beacon does not go out even after waiting this
 375  * number of beacon intervals, the game's up.
 376  */
 377 #define BSTUCK_THRESH                   (9 * ATH_BCBUF)
 378 #define ATH_BCBUF                       4
 379 #define ATH_DEFAULT_BINTVAL             100 /* TU */
 380 #define ATH_DEFAULT_BMISS_LIMIT         10
 381 #define IEEE80211_MS_TO_TU(x)           (((x) * 1000) / 1024)
 382
 383 struct ath_beacon_config {
 384         u16 beacon_interval;
 385         u16 listen_interval;
 386         u16 dtim_period;
 387         u16 bmiss_timeout;
 388         u8 dtim_count;
 389 };
 390
 391 struct ath_beacon {
 392         enum {
 393                 OK,             /* no change needed */
 394                 UPDATE,         /* update pending */
 395                 COMMIT          /* beacon sent, commit change */
 396         } updateslot;           /* slot time update fsm */
 397
 398         u32 beaconq;
 399         u32 bmisscnt;
 400         u32 ast_be_xmit;
 401         u64 bc_tstamp;
 402         struct ieee80211_vif *bslot[ATH_BCBUF];
 403         struct ath_wiphy *bslot_aphy[ATH_BCBUF];
 404         int slottime;
 405         int slotupdate;
 406         struct ath9k_tx_queue_info beacon_qi;
 407         struct ath_descdma bdma;
 408         struct ath_txq *cabq;
 409         struct list_head bbuf;
 410 };
 411
 412 void ath_beacon_tasklet(unsigned long data);
 413 void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif);
 414 int ath_beaconq_setup(struct ath_hw *ah);
 415 int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif);
 416 void ath_beacon_return(struct ath_softc *sc, struct ath_vif *avp);
 417
 418 /*******/
 419 /* ANI */
 420 /*******/
 421
 422 #define ATH_STA_SHORT_CALINTERVAL 1000    /* 1 second */
 423 #define ATH_AP_SHORT_CALINTERVAL  100     /* 100 ms */
 424 #define ATH_ANI_POLLINTERVAL      100     /* 100 ms */
 425 #define ATH_LONG_CALINTERVAL      30000   /* 30 seconds */
 426 #define ATH_RESTART_CALINTERVAL   1200000 /* 20 minutes */
 427
 428 struct ath_ani {
 429         bool caldone;
 430         int16_t noise_floor;
 431         unsigned int longcal_timer;
 432         unsigned int shortcal_timer;
 433         unsigned int resetcal_timer;
 434         unsigned int checkani_timer;
 435         struct timer_list timer;
 436 };
 437
 438 /********************/
 439 /*   LED Control    */
 440 /********************/
 441
 442 #define ATH_LED_PIN     1
 443 #define ATH_LED_ON_DURATION_IDLE        350     /* in msecs */
 444 #define ATH_LED_OFF_DURATION_IDLE       250     /* in msecs */
 445
 446 enum ath_led_type {
 447         ATH_LED_RADIO,
 448         ATH_LED_ASSOC,
 449         ATH_LED_TX,
 450         ATH_LED_RX
 451 };
 452
 453 struct ath_led {
 454         struct ath_softc *sc;
 455         struct led_classdev led_cdev;
 456         enum ath_led_type led_type;
 457         char name[32];
 458         bool registered;
 459 };
 460
 461 /********************/
 462 /* Main driver core */
 463 /********************/
 464
 465 /*
 466  * Default cache line size, in bytes.
 467  * Used when PCI device not fully initialized by bootrom/BIOS
 468 */
 469 #define DEFAULT_CACHELINE       32
 470 #define ATH_DEFAULT_NOISE_FLOOR -95
 471 #define ATH_REGCLASSIDS_MAX     10
 472 #define ATH_CABQ_READY_TIME     80      /* % of beacon interval */
 473 #define ATH_MAX_SW_RETRIES      10
 474 #define ATH_CHAN_MAX            255
 475 #define IEEE80211_WEP_NKID      4       /* number of key ids */
 476
 477 /*
 478  * The key cache is used for h/w cipher state and also for
 479  * tracking station state such as the current tx antenna.
 480  * We also setup a mapping table between key cache slot indices
 481  * and station state to short-circuit node lookups on rx.
 482  * Different parts have different size key caches.  We handle
 483  * up to ATH_KEYMAX entries (could dynamically allocate state).
 484  */
 485 #define ATH_KEYMAX              128     /* max key cache size we handle */
 486
 487 #define ATH_TXPOWER_MAX         100     /* .5 dBm units */
 488 #define ATH_RSSI_DUMMY_MARKER   0x127
 489 #define ATH_RATE_DUMMY_MARKER   0
 490
 491 #define SC_OP_INVALID           BIT(0)
 492 #define SC_OP_BEACONS           BIT(1)
 493 #define SC_OP_RXAGGR            BIT(2)
 494 #define SC_OP_TXAGGR            BIT(3)
 495 #define SC_OP_FULL_RESET        BIT(4)
 496 #define SC_OP_PREAMBLE_SHORT    BIT(5)
 497 #define SC_OP_PROTECT_ENABLE    BIT(6)
 498 #define SC_OP_RXFLUSH           BIT(7)
 499 #define SC_OP_LED_ASSOCIATED    BIT(8)
 500 #define SC_OP_WAIT_FOR_BEACON   BIT(12)
 501 #define SC_OP_LED_ON            BIT(13)
 502 #define SC_OP_SCANNING          BIT(14)
 503 #define SC_OP_TSF_RESET         BIT(15)
 504 #define SC_OP_WAIT_FOR_CAB      BIT(16)
 505 #define SC_OP_WAIT_FOR_PSPOLL_DATA BIT(17)
 506 #define SC_OP_WAIT_FOR_TX_ACK   BIT(18)
 507 #define SC_OP_BEACON_SYNC       BIT(19)
 508
 509 struct ath_bus_ops {
 510         void            (*read_cachesize)(struct ath_softc *sc, int *csz);
 511         void            (*cleanup)(struct ath_softc *sc);
 512         bool            (*eeprom_read)(struct ath_hw *ah, u32 off, u16 *data);
 513 };
 514
 515 struct ath_wiphy;
 516
 517 struct ath_softc {
 518         struct ieee80211_hw *hw;
 519         struct device *dev;
 520
 521         spinlock_t wiphy_lock; /* spinlock to protect ath_wiphy data */
 522         struct ath_wiphy *pri_wiphy;
 523         struct ath_wiphy **sec_wiphy; /* secondary wiphys (virtual radios); may
 524                                        * have NULL entries */
 525         int num_sec_wiphy; /* number of sec_wiphy pointers in the array */
 526         int chan_idx;
 527         int chan_is_ht;
 528         struct ath_wiphy *next_wiphy;
 529         struct work_struct chan_work;
 530         int wiphy_select_failures;
 531         unsigned long wiphy_select_first_fail;
 532         struct delayed_work wiphy_work;
 533         unsigned long wiphy_scheduler_int;
 534         int wiphy_scheduler_index;
 535
 536         struct tasklet_struct intr_tq;
 537         struct tasklet_struct bcon_tasklet;
 538         struct ath_hw *sc_ah;
 539         void __iomem *mem;
 540         int irq;
 541         spinlock_t sc_resetlock;
 542         spinlock_t sc_serial_rw;
 543         struct mutex mutex;
 544
 545         u8 curbssid[ETH_ALEN];
 546         u8 bssidmask[ETH_ALEN];
 547         u32 intrstatus;
 548         u32 sc_flags; /* SC_OP_* */
 549         u16 curtxpow;
 550         u16 curaid;
 551         u16 cachelsz;
 552         u8 nbcnvifs;
 553         u16 nvifs;
 554         u8 tx_chainmask;
 555         u8 rx_chainmask;
 556         u32 keymax;
 557         DECLARE_BITMAP(keymap, ATH_KEYMAX);
 558         u8 splitmic;
 559         atomic_t ps_usecount;
 560         enum ath9k_int imask;
 561         enum ath9k_ht_extprotspacing ht_extprotspacing;
 562         enum ath9k_ht_macmode tx_chan_width;
 563
 564         struct ath_config config;
 565         struct ath_rx rx;
 566         struct ath_tx tx;
 567         struct ath_beacon beacon;
 568         struct ieee80211_rate rates[IEEE80211_NUM_BANDS][ATH_RATE_MAX];
 569         const struct ath_rate_table *hw_rate_table[ATH9K_MODE_MAX];
 570         const struct ath_rate_table *cur_rate_table;
 571         struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
 572
 573         struct ath_led radio_led;
 574         struct ath_led assoc_led;
 575         struct ath_led tx_led;
 576         struct ath_led rx_led;
 577         struct delayed_work ath_led_blink_work;
 578         int led_on_duration;
 579         int led_off_duration;
 580         int led_on_cnt;
 581         int led_off_cnt;
 582
 583         int beacon_interval;
 584
 585         struct ath_ani ani;
 586         struct ath9k_node_stats nodestats;
 587 #ifdef CONFIG_ATH9K_DEBUG
 588         struct ath9k_debug debug;
 589 #endif
 590         struct ath_bus_ops *bus_ops;
 591         struct ath_beacon_config cur_beacon_conf;
 592 };
 593
 594 struct ath_wiphy {
 595         struct ath_softc *sc; /* shared for all virtual wiphys */
 596         struct ieee80211_hw *hw;
 597         enum ath_wiphy_state {
 598                 ATH_WIPHY_INACTIVE,
 599                 ATH_WIPHY_ACTIVE,
 600                 ATH_WIPHY_PAUSING,
 601                 ATH_WIPHY_PAUSED,
 602                 ATH_WIPHY_SCAN,
 603         } state;
 604         int chan_idx;
 605         int chan_is_ht;
 606 };
 607
 608 int ath_reset(struct ath_softc *sc, bool retry_tx);
 609 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc);
 610 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc);
 611 int ath_cabq_update(struct ath_softc *);
 612
 613 static inline void ath_read_cachesize(struct ath_softc *sc, int *csz)
 614 {
 615         sc->bus_ops->read_cachesize(sc, csz);
 616 }
 617
 618 static inline void ath_bus_cleanup(struct ath_softc *sc)
 619 {
 620         sc->bus_ops->cleanup(sc);
 621 }
 622
 623 extern struct ieee80211_ops ath9k_ops;
 624
 625 irqreturn_t ath_isr(int irq, void *dev);
 626 void ath_cleanup(struct ath_softc *sc);
 627 int ath_attach(u16 devid, struct ath_softc *sc);
 628 void ath_detach(struct ath_softc *sc);
 629 const char *ath_mac_bb_name(u32 mac_bb_version);
 630 const char *ath_rf_name(u16 rf_version);
 631 void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw);
 632 void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
 633                            struct ath9k_channel *ichan);
 634 void ath_update_chainmask(struct ath_softc *sc, int is_ht);
 635 int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
 636                     struct ath9k_channel *hchan);
 637 void ath_radio_enable(struct ath_softc *sc);
 638 void ath_radio_disable(struct ath_softc *sc);
 639
 640 #ifdef CONFIG_PCI
 641 int ath_pci_init(void);
 642 void ath_pci_exit(void);
 643 #else
 644 static inline int ath_pci_init(void) { return 0; };
 645 static inline void ath_pci_exit(void) {};
 646 #endif
 647
 648 #ifdef CONFIG_ATHEROS_AR71XX
 649 int ath_ahb_init(void);
 650 void ath_ahb_exit(void);
 651 #else
 652 static inline int ath_ahb_init(void) { return 0; };
 653 static inline void ath_ahb_exit(void) {};
 654 #endif
 655
 656 static inline void ath9k_ps_wakeup(struct ath_softc *sc)
 657 {
 658         if (atomic_inc_return(&sc->ps_usecount) == 1)
 659                 if (sc->sc_ah->power_mode !=  ATH9K_PM_AWAKE) {
 660                         sc->sc_ah->restore_mode = sc->sc_ah->power_mode;
 661                         ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
 662                 }
 663 }
 664
 665 static inline void ath9k_ps_restore(struct ath_softc *sc)
 666 {
 667         if (atomic_dec_and_test(&sc->ps_usecount))
 668                 if ((sc->hw->conf.flags & IEEE80211_CONF_PS) &&
 669                     !(sc->sc_flags & (SC_OP_WAIT_FOR_BEACON |
 670                                       SC_OP_WAIT_FOR_CAB |
 671                                       SC_OP_WAIT_FOR_PSPOLL_DATA |
 672                                       SC_OP_WAIT_FOR_TX_ACK)))
 673                         ath9k_hw_setpower(sc->sc_ah,
 674                                           sc->sc_ah->restore_mode);
 675 }
 676
 677
 678 void ath9k_set_bssid_mask(struct ieee80211_hw *hw);
 679 int ath9k_wiphy_add(struct ath_softc *sc);
 680 int ath9k_wiphy_del(struct ath_wiphy *aphy);
 681 void ath9k_tx_status(struct ieee80211_hw *hw, struct sk_buff *skb);
 682 int ath9k_wiphy_pause(struct ath_wiphy *aphy);
 683 int ath9k_wiphy_unpause(struct ath_wiphy *aphy);
 684 int ath9k_wiphy_select(struct ath_wiphy *aphy);
 685 void ath9k_wiphy_set_scheduler(struct ath_softc *sc, unsigned int msec_int);
 686 void ath9k_wiphy_chan_work(struct work_struct *work);
 687 bool ath9k_wiphy_started(struct ath_softc *sc);
 688 void ath9k_wiphy_pause_all_forced(struct ath_softc *sc,
 689                                   struct ath_wiphy *selected);
 690 bool ath9k_wiphy_scanning(struct ath_softc *sc);
 691 void ath9k_wiphy_work(struct work_struct *work);
 692
 693 void ath9k_iowrite32(struct ath_hw *ah, u32 reg_offset, u32 val);
 694 unsigned int ath9k_ioread32(struct ath_hw *ah, u32 reg_offset);
 695
 696 #endif /* ATH9K_H */