drivers/net/wireless/ath/ath9k/ath9k.h

   1 /*
   2  * Copyright (c) 2008-2011 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #ifndef ATH9K_H
  18 #define ATH9K_H
  19
  20 #include <linux/etherdevice.h>
  21 #include <linux/device.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/leds.h>
  24 #include <linux/completion.h>
  25
  26 #include "debug.h"
  27 #include "common.h"
  28 #include "mci.h"
  29
  30 /*
  31  * Header for the ath9k.ko driver core *only* -- hw code nor any other driver
  32  * should rely on this file or its contents.
  33  */
  34
  35 struct ath_node;
  36
  37 /* Macro to expand scalars to 64-bit objects */
  38
  39 #define ito64(x) (sizeof(x) == 1) ?                     \
  40         (((unsigned long long int)(x)) & (0xff)) :      \
  41         (sizeof(x) == 2) ?                              \
  42         (((unsigned long long int)(x)) & 0xffff) :      \
  43         ((sizeof(x) == 4) ?                             \
  44          (((unsigned long long int)(x)) & 0xffffffff) : \
  45          (unsigned long long int)(x))
  46
  47 /* increment with wrap-around */
  48 #define INCR(_l, _sz)   do {                    \
  49                 (_l)++;                         \
  50                 (_l) &= ((_sz) - 1);            \
  51         } while (0)
  52
  53 /* decrement with wrap-around */
  54 #define DECR(_l,  _sz)  do {                    \
  55                 (_l)--;                         \
  56                 (_l) &= ((_sz) - 1);            \
  57         } while (0)
  58
  59 #define TSF_TO_TU(_h,_l) \
  60         ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
  61
  62 #define ATH_TXQ_SETUP(sc, i)        ((sc)->tx.txqsetup & (1<<i))
  63
  64 struct ath_config {
  65         u16 txpowlimit;
  66         u8 cabqReadytime;
  67 };
  68
  69 /*************************/
  70 /* Descriptor Management */
  71 /*************************/
  72
  73 #define ATH_TXBUF_RESET(_bf) do {                               \
  74                 (_bf)->bf_stale = false;                        \
  75                 (_bf)->bf_lastbf = NULL;                        \
  76                 (_bf)->bf_next = NULL;                          \
  77                 memset(&((_bf)->bf_state), 0,                   \
  78                        sizeof(struct ath_buf_state));           \
  79         } while (0)
  80
  81 #define ATH_RXBUF_RESET(_bf) do {               \
  82                 (_bf)->bf_stale = false;        \
  83         } while (0)
  84
  85 /**
  86  * enum buffer_type - Buffer type flags
  87  *
  88  * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX)
  89  * @BUF_AGGR: Indicates whether the buffer can be aggregated
  90  *      (used in aggregation scheduling)
  91  */
  92 enum buffer_type {
  93         BUF_AMPDU               = BIT(0),
  94         BUF_AGGR                = BIT(1),
  95 };
  96
  97 #define bf_isampdu(bf)          (bf->bf_state.bf_type & BUF_AMPDU)
  98 #define bf_isaggr(bf)           (bf->bf_state.bf_type & BUF_AGGR)
  99
 100 #define ATH_TXSTATUS_RING_SIZE 512
 101
 102 #define DS2PHYS(_dd, _ds)                                               \
 103         ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
 104 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
 105 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
 106
 107 struct ath_descdma {
 108         void *dd_desc;
 109         dma_addr_t dd_desc_paddr;
 110         u32 dd_desc_len;
 111         struct ath_buf *dd_bufptr;
 112 };
 113
 114 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
 115                       struct list_head *head, const char *name,
 116                       int nbuf, int ndesc, bool is_tx);
 117 void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd,
 118                          struct list_head *head);
 119
 120 /***********/
 121 /* RX / TX */
 122 /***********/
 123
 124 #define ATH_RXBUF               512
 125 #define ATH_TXBUF               512
 126 #define ATH_TXBUF_RESERVE       5
 127 #define ATH_MAX_QDEPTH          (ATH_TXBUF / 4 - ATH_TXBUF_RESERVE)
 128 #define ATH_TXMAXTRY            13
 129
 130 #define TID_TO_WME_AC(_tid)                             \
 131         ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \
 132          (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \
 133          (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \
 134          WME_AC_VO)
 135
 136 #define ATH_AGGR_DELIM_SZ          4
 137 #define ATH_AGGR_MINPLEN           256 /* in bytes, minimum packet length */
 138 /* number of delimiters for encryption padding */
 139 #define ATH_AGGR_ENCRYPTDELIM      10
 140 /* minimum h/w qdepth to be sustained to maximize aggregation */
 141 #define ATH_AGGR_MIN_QDEPTH        2
 142 #define ATH_AMPDU_SUBFRAME_DEFAULT 32
 143
 144 #define IEEE80211_SEQ_SEQ_SHIFT    4
 145 #define IEEE80211_SEQ_MAX          4096
 146 #define IEEE80211_WEP_IVLEN        3
 147 #define IEEE80211_WEP_KIDLEN       1
 148 #define IEEE80211_WEP_CRCLEN       4
 149 #define IEEE80211_MAX_MPDU_LEN     (3840 + FCS_LEN +            \
 150                                     (IEEE80211_WEP_IVLEN +      \
 151                                      IEEE80211_WEP_KIDLEN +     \
 152                                      IEEE80211_WEP_CRCLEN))
 153
 154 /* return whether a bit at index _n in bitmap _bm is set
 155  * _sz is the size of the bitmap  */
 156 #define ATH_BA_ISSET(_bm, _n)  (((_n) < (WME_BA_BMP_SIZE)) &&           \
 157                                 ((_bm)[(_n) >> 5] & (1 << ((_n) & 31))))
 158
 159 /* return block-ack bitmap index given sequence and starting sequence */
 160 #define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1))
 161
 162 /* return the seqno for _start + _offset */
 163 #define ATH_BA_INDEX2SEQ(_seq, _offset) (((_seq) + (_offset)) & (IEEE80211_SEQ_MAX - 1))
 164
 165 /* returns delimiter padding required given the packet length */
 166 #define ATH_AGGR_GET_NDELIM(_len)                                       \
 167        (((_len) >= ATH_AGGR_MINPLEN) ? 0 :                             \
 168         DIV_ROUND_UP(ATH_AGGR_MINPLEN - (_len), ATH_AGGR_DELIM_SZ))
 169
 170 #define BAW_WITHIN(_start, _bawsz, _seqno) \
 171         ((((_seqno) - (_start)) & 4095) < (_bawsz))
 172
 173 #define ATH_AN_2_TID(_an, _tidno)  (&(_an)->tid[(_tidno)])
 174
 175 #define ATH_TX_COMPLETE_POLL_INT        1000
 176
 177 enum ATH_AGGR_STATUS {
 178         ATH_AGGR_DONE,
 179         ATH_AGGR_BAW_CLOSED,
 180         ATH_AGGR_LIMITED,
 181 };
 182
 183 #define ATH_TXFIFO_DEPTH 8
 184 struct ath_txq {
 185         int mac80211_qnum; /* mac80211 queue number, -1 means not mac80211 Q */
 186         u32 axq_qnum; /* ath9k hardware queue number */
 187         void *axq_link;
 188         struct list_head axq_q;
 189         spinlock_t axq_lock;
 190         u32 axq_depth;
 191         u32 axq_ampdu_depth;
 192         bool stopped;
 193         bool axq_tx_inprogress;
 194         struct list_head axq_acq;
 195         struct list_head txq_fifo[ATH_TXFIFO_DEPTH];
 196         u8 txq_headidx;
 197         u8 txq_tailidx;
 198         int pending_frames;
 199         struct sk_buff_head complete_q;
 200 };
 201
 202 struct ath_atx_ac {
 203         struct ath_txq *txq;
 204         int sched;
 205         struct list_head list;
 206         struct list_head tid_q;
 207         bool clear_ps_filter;
 208 };
 209
 210 struct ath_frame_info {
 211         struct ath_buf *bf;
 212         int framelen;
 213         enum ath9k_key_type keytype;
 214         u8 keyix;
 215         u8 retries;
 216 };
 217
 218 struct ath_buf_state {
 219         u8 bf_type;
 220         u8 bfs_paprd;
 221         u8 ndelim;
 222         u16 seqno;
 223         unsigned long bfs_paprd_timestamp;
 224 };
 225
 226 struct ath_buf {
 227         struct list_head list;
 228         struct ath_buf *bf_lastbf;      /* last buf of this unit (a frame or
 229                                            an aggregate) */
 230         struct ath_buf *bf_next;        /* next subframe in the aggregate */
 231         struct sk_buff *bf_mpdu;        /* enclosing frame structure */
 232         void *bf_desc;                  /* virtual addr of desc */
 233         dma_addr_t bf_daddr;            /* physical addr of desc */
 234         dma_addr_t bf_buf_addr; /* physical addr of data buffer, for DMA */
 235         bool bf_stale;
 236         struct ath_buf_state bf_state;
 237 };
 238
 239 struct ath_atx_tid {
 240         struct list_head list;
 241         struct sk_buff_head buf_q;
 242         struct ath_node *an;
 243         struct ath_atx_ac *ac;
 244         unsigned long tx_buf[BITS_TO_LONGS(ATH_TID_MAX_BUFS)];
 245         int bar_index;
 246         u16 seq_start;
 247         u16 seq_next;
 248         u16 baw_size;
 249         int tidno;
 250         int baw_head;   /* first un-acked tx buffer */
 251         int baw_tail;   /* next unused tx buffer slot */
 252         int sched;
 253         int paused;
 254         u8 state;
 255 };
 256
 257 struct ath_node {
 258 #ifdef CONFIG_ATH9K_DEBUGFS
 259         struct list_head list; /* for sc->nodes */
 260 #endif
 261         struct ieee80211_sta *sta; /* station struct we're part of */
 262         struct ieee80211_vif *vif; /* interface with which we're associated */
 263         struct ath_atx_tid tid[WME_NUM_TID];
 264         struct ath_atx_ac ac[WME_NUM_AC];
 265         int ps_key;
 266
 267         u16 maxampdu;
 268         u8 mpdudensity;
 269
 270         bool sleeping;
 271 };
 272
 273 #define AGGR_CLEANUP         BIT(1)
 274 #define AGGR_ADDBA_COMPLETE  BIT(2)
 275 #define AGGR_ADDBA_PROGRESS  BIT(3)
 276
 277 struct ath_tx_control {
 278         struct ath_txq *txq;
 279         struct ath_node *an;
 280         u8 paprd;
 281 };
 282
 283 #define ATH_TX_ERROR        0x01
 284
 285 /**
 286  * @txq_map:  Index is mac80211 queue number.  This is
 287  *  not necessarily the same as the hardware queue number
 288  *  (axq_qnum).
 289  */
 290 struct ath_tx {
 291         u16 seq_no;
 292         u32 txqsetup;
 293         spinlock_t txbuflock;
 294         struct list_head txbuf;
 295         struct ath_txq txq[ATH9K_NUM_TX_QUEUES];
 296         struct ath_descdma txdma;
 297         struct ath_txq *txq_map[WME_NUM_AC];
 298 };
 299
 300 struct ath_rx_edma {
 301         struct sk_buff_head rx_fifo;
 302         u32 rx_fifo_hwsize;
 303 };
 304
 305 struct ath_rx {
 306         u8 defant;
 307         u8 rxotherant;
 308         u32 *rxlink;
 309         unsigned int rxfilter;
 310         spinlock_t rxbuflock;
 311         struct list_head rxbuf;
 312         struct ath_descdma rxdma;
 313         struct ath_buf *rx_bufptr;
 314         struct ath_rx_edma rx_edma[ATH9K_RX_QUEUE_MAX];
 315
 316         struct sk_buff *frag;
 317 };
 318
 319 int ath_startrecv(struct ath_softc *sc);
 320 bool ath_stoprecv(struct ath_softc *sc);
 321 void ath_flushrecv(struct ath_softc *sc);
 322 u32 ath_calcrxfilter(struct ath_softc *sc);
 323 int ath_rx_init(struct ath_softc *sc, int nbufs);
 324 void ath_rx_cleanup(struct ath_softc *sc);
 325 int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp);
 326 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
 327 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
 328 bool ath_drain_all_txq(struct ath_softc *sc, bool retry_tx);
 329 void ath_draintxq(struct ath_softc *sc,
 330                      struct ath_txq *txq, bool retry_tx);
 331 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an);
 332 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an);
 333 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq);
 334 int ath_tx_init(struct ath_softc *sc, int nbufs);
 335 void ath_tx_cleanup(struct ath_softc *sc);
 336 int ath_txq_update(struct ath_softc *sc, int qnum,
 337                    struct ath9k_tx_queue_info *q);
 338 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
 339                  struct ath_tx_control *txctl);
 340 void ath_tx_tasklet(struct ath_softc *sc);
 341 void ath_tx_edma_tasklet(struct ath_softc *sc);
 342 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
 343                       u16 tid, u16 *ssn);
 344 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
 345 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
 346
 347 void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an);
 348 void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc,
 349                        struct ath_node *an);
 350
 351 /********/
 352 /* VIFs */
 353 /********/
 354
 355 struct ath_vif {
 356         int av_bslot;
 357         bool is_bslot_active, primary_sta_vif;
 358         __le64 tsf_adjust; /* TSF adjustment for staggered beacons */
 359         struct ath_buf *av_bcbuf;
 360 };
 361
 362 /*******************/
 363 /* Beacon Handling */
 364 /*******************/
 365
 366 /*
 367  * Regardless of the number of beacons we stagger, (i.e. regardless of the
 368  * number of BSSIDs) if a given beacon does not go out even after waiting this
 369  * number of beacon intervals, the game's up.
 370  */
 371 #define BSTUCK_THRESH                   9
 372 #define ATH_BCBUF                       4
 373 #define ATH_DEFAULT_BINTVAL             100 /* TU */
 374 #define ATH_DEFAULT_BMISS_LIMIT         10
 375 #define IEEE80211_MS_TO_TU(x)           (((x) * 1000) / 1024)
 376
 377 struct ath_beacon_config {
 378         int beacon_interval;
 379         u16 listen_interval;
 380         u16 dtim_period;
 381         u16 bmiss_timeout;
 382         u8 dtim_count;
 383 };
 384
 385 struct ath_beacon {
 386         enum {
 387                 OK,             /* no change needed */
 388                 UPDATE,         /* update pending */
 389                 COMMIT          /* beacon sent, commit change */
 390         } updateslot;           /* slot time update fsm */
 391
 392         u32 beaconq;
 393         u32 bmisscnt;
 394         u32 ast_be_xmit;
 395         u32 bc_tstamp;
 396         struct ieee80211_vif *bslot[ATH_BCBUF];
 397         int slottime;
 398         int slotupdate;
 399         struct ath9k_tx_queue_info beacon_qi;
 400         struct ath_descdma bdma;
 401         struct ath_txq *cabq;
 402         struct list_head bbuf;
 403
 404         bool tx_processed;
 405         bool tx_last;
 406 };
 407
 408 void ath_beacon_tasklet(unsigned long data);
 409 void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif);
 410 int ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_vif *vif);
 411 void ath_beacon_return(struct ath_softc *sc, struct ath_vif *avp);
 412 int ath_beaconq_config(struct ath_softc *sc);
 413 void ath_set_beacon(struct ath_softc *sc);
 414 void ath9k_set_beaconing_status(struct ath_softc *sc, bool status);
 415
 416 /*******/
 417 /* ANI */
 418 /*******/
 419
 420 #define ATH_STA_SHORT_CALINTERVAL 1000    /* 1 second */
 421 #define ATH_AP_SHORT_CALINTERVAL  100     /* 100 ms */
 422 #define ATH_ANI_POLLINTERVAL_OLD  100     /* 100 ms */
 423 #define ATH_ANI_POLLINTERVAL_NEW  1000    /* 1000 ms */
 424 #define ATH_LONG_CALINTERVAL_INT  1000    /* 1000 ms */
 425 #define ATH_LONG_CALINTERVAL      30000   /* 30 seconds */
 426 #define ATH_RESTART_CALINTERVAL   1200000 /* 20 minutes */
 427
 428 #define ATH_PAPRD_TIMEOUT       100 /* msecs */
 429
 430 void ath_reset_work(struct work_struct *work);
 431 void ath_hw_check(struct work_struct *work);
 432 void ath_hw_pll_work(struct work_struct *work);
 433 void ath_paprd_calibrate(struct work_struct *work);
 434 void ath_ani_calibrate(unsigned long data);
 435 void ath_start_ani(struct ath_common *common);
 436
 437 /**********/
 438 /* BTCOEX */
 439 /**********/
 440
 441 struct ath_btcoex {
 442         bool hw_timer_enabled;
 443         spinlock_t btcoex_lock;
 444         struct timer_list period_timer; /* Timer for BT period */
 445         u32 bt_priority_cnt;
 446         unsigned long bt_priority_time;
 447         int bt_stomp_type; /* Types of BT stomping */
 448         u32 btcoex_no_stomp; /* in usec */
 449         u32 btcoex_period; /* in usec */
 450         u32 btscan_no_stomp; /* in usec */
 451         u32 duty_cycle;
 452         struct ath_gen_timer *no_stomp_timer; /* Timer for no BT stomping */
 453         struct ath_mci_profile mci;
 454 };
 455
 456 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
 457 int ath9k_init_btcoex(struct ath_softc *sc);
 458 void ath9k_deinit_btcoex(struct ath_softc *sc);
 459 void ath9k_start_btcoex(struct ath_softc *sc);
 460 void ath9k_stop_btcoex(struct ath_softc *sc);
 461 void ath9k_btcoex_timer_resume(struct ath_softc *sc);
 462 void ath9k_btcoex_timer_pause(struct ath_softc *sc);
 463 void ath9k_btcoex_handle_interrupt(struct ath_softc *sc, u32 status);
 464 u16 ath9k_btcoex_aggr_limit(struct ath_softc *sc, u32 max_4ms_framelen);
 465 #else
 466 static inline int ath9k_init_btcoex(struct ath_softc *sc)
 467 {
 468         return 0;
 469 }
 470 static inline void ath9k_deinit_btcoex(struct ath_softc *sc)
 471 {
 472 }
 473 static inline void ath9k_start_btcoex(struct ath_softc *sc)
 474 {
 475 }
 476 static inline void ath9k_stop_btcoex(struct ath_softc *sc)
 477 {
 478 }
 479 static inline void ath9k_btcoex_handle_interrupt(struct ath_softc *sc,
 480                                                  u32 status)
 481 {
 482 }
 483 static inline u16 ath9k_btcoex_aggr_limit(struct ath_softc *sc,
 484                                           u32 max_4ms_framelen)
 485 {
 486         return 0;
 487 }
 488 #endif /* CONFIG_ATH9K_BTCOEX_SUPPORT */
 489
 490 /********************/
 491 /*   LED Control    */
 492 /********************/
 493
 494 #define ATH_LED_PIN_DEF                 1
 495 #define ATH_LED_PIN_9287                8
 496 #define ATH_LED_PIN_9300                10
 497 #define ATH_LED_PIN_9485                6
 498 #define ATH_LED_PIN_9462                4
 499
 500 #ifdef CONFIG_MAC80211_LEDS
 501 void ath_init_leds(struct ath_softc *sc);
 502 void ath_deinit_leds(struct ath_softc *sc);
 503 #else
 504 static inline void ath_init_leds(struct ath_softc *sc)
 505 {
 506 }
 507
 508 static inline void ath_deinit_leds(struct ath_softc *sc)
 509 {
 510 }
 511 #endif
 512
 513
 514 /* Antenna diversity/combining */
 515 #define ATH_ANT_RX_CURRENT_SHIFT 4
 516 #define ATH_ANT_RX_MAIN_SHIFT 2
 517 #define ATH_ANT_RX_MASK 0x3
 518
 519 #define ATH_ANT_DIV_COMB_SHORT_SCAN_INTR 50
 520 #define ATH_ANT_DIV_COMB_SHORT_SCAN_PKTCOUNT 0x100
 521 #define ATH_ANT_DIV_COMB_MAX_PKTCOUNT 0x200
 522 #define ATH_ANT_DIV_COMB_INIT_COUNT 95
 523 #define ATH_ANT_DIV_COMB_MAX_COUNT 100
 524 #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO 30
 525 #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO2 20
 526
 527 #define ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA -1
 528 #define ATH_ANT_DIV_COMB_LNA1_DELTA_HI -4
 529 #define ATH_ANT_DIV_COMB_LNA1_DELTA_MID -2
 530 #define ATH_ANT_DIV_COMB_LNA1_DELTA_LOW 2
 531
 532 enum ath9k_ant_div_comb_lna_conf {
 533         ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2,
 534         ATH_ANT_DIV_COMB_LNA2,
 535         ATH_ANT_DIV_COMB_LNA1,
 536         ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2,
 537 };
 538
 539 struct ath_ant_comb {
 540         u16 count;
 541         u16 total_pkt_count;
 542         bool scan;
 543         bool scan_not_start;
 544         int main_total_rssi;
 545         int alt_total_rssi;
 546         int alt_recv_cnt;
 547         int main_recv_cnt;
 548         int rssi_lna1;
 549         int rssi_lna2;
 550         int rssi_add;
 551         int rssi_sub;
 552         int rssi_first;
 553         int rssi_second;
 554         int rssi_third;
 555         bool alt_good;
 556         int quick_scan_cnt;
 557         int main_conf;
 558         enum ath9k_ant_div_comb_lna_conf first_quick_scan_conf;
 559         enum ath9k_ant_div_comb_lna_conf second_quick_scan_conf;
 560         int first_bias;
 561         int second_bias;
 562         bool first_ratio;
 563         bool second_ratio;
 564         unsigned long scan_start_time;
 565 };
 566
 567 /********************/
 568 /* Main driver core */
 569 /********************/
 570
 571 /*
 572  * Default cache line size, in bytes.
 573  * Used when PCI device not fully initialized by bootrom/BIOS
 574 */
 575 #define DEFAULT_CACHELINE       32
 576 #define ATH_REGCLASSIDS_MAX     10
 577 #define ATH_CABQ_READY_TIME     80      /* % of beacon interval */
 578 #define ATH_MAX_SW_RETRIES      30
 579 #define ATH_CHAN_MAX            255
 580
 581 #define ATH_TXPOWER_MAX         100     /* .5 dBm units */
 582 #define ATH_RATE_DUMMY_MARKER   0
 583
 584 #define SC_OP_INVALID                BIT(0)
 585 #define SC_OP_BEACONS                BIT(1)
 586 #define SC_OP_RXAGGR                 BIT(2)
 587 #define SC_OP_TXAGGR                 BIT(3)
 588 #define SC_OP_OFFCHANNEL             BIT(4)
 589 #define SC_OP_PREAMBLE_SHORT         BIT(5)
 590 #define SC_OP_PROTECT_ENABLE         BIT(6)
 591 #define SC_OP_RXFLUSH                BIT(7)
 592 #define SC_OP_LED_ASSOCIATED         BIT(8)
 593 #define SC_OP_LED_ON                 BIT(9)
 594 #define SC_OP_TSF_RESET              BIT(11)
 595 #define SC_OP_BT_PRIORITY_DETECTED   BIT(12)
 596 #define SC_OP_BT_SCAN                BIT(13)
 597 #define SC_OP_ANI_RUN                BIT(14)
 598 #define SC_OP_PRIM_STA_VIF           BIT(15)
 599
 600 /* Powersave flags */
 601 #define PS_WAIT_FOR_BEACON        BIT(0)
 602 #define PS_WAIT_FOR_CAB           BIT(1)
 603 #define PS_WAIT_FOR_PSPOLL_DATA   BIT(2)
 604 #define PS_WAIT_FOR_TX_ACK        BIT(3)
 605 #define PS_BEACON_SYNC            BIT(4)
 606
 607 struct ath_rate_table;
 608
 609 struct ath9k_vif_iter_data {
 610         const u8 *hw_macaddr; /* phy's hardware address, set
 611                                * before starting iteration for
 612                                * valid bssid mask.
 613                                */
 614         u8 mask[ETH_ALEN]; /* bssid mask */
 615         int naps;      /* number of AP vifs */
 616         int nmeshes;   /* number of mesh vifs */
 617         int nstations; /* number of station vifs */
 618         int nwds;      /* number of WDS vifs */
 619         int nadhocs;   /* number of adhoc vifs */
 620         int nothers;   /* number of vifs not specified above. */
 621 };
 622
 623 struct ath_softc {
 624         struct ieee80211_hw *hw;
 625         struct device *dev;
 626
 627         struct survey_info *cur_survey;
 628         struct survey_info survey[ATH9K_NUM_CHANNELS];
 629
 630         struct tasklet_struct intr_tq;
 631         struct tasklet_struct bcon_tasklet;
 632         struct ath_hw *sc_ah;
 633         void __iomem *mem;
 634         int irq;
 635         spinlock_t sc_serial_rw;
 636         spinlock_t sc_pm_lock;
 637         spinlock_t sc_pcu_lock;
 638         struct mutex mutex;
 639         struct work_struct paprd_work;
 640         struct work_struct hw_check_work;
 641         struct work_struct hw_reset_work;
 642         struct completion paprd_complete;
 643
 644         unsigned int hw_busy_count;
 645
 646         u32 intrstatus;
 647         u32 sc_flags; /* SC_OP_* */
 648         u16 ps_flags; /* PS_* */
 649         u16 curtxpow;
 650         bool ps_enabled;
 651         bool ps_idle;
 652         short nbcnvifs;
 653         short nvifs;
 654         unsigned long ps_usecount;
 655
 656         struct ath_config config;
 657         struct ath_rx rx;
 658         struct ath_tx tx;
 659         struct ath_beacon beacon;
 660         struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
 661
 662 #ifdef CONFIG_MAC80211_LEDS
 663         bool led_registered;
 664         char led_name[32];
 665         struct led_classdev led_cdev;
 666 #endif
 667
 668         struct ath9k_hw_cal_data caldata;
 669         int last_rssi;
 670
 671 #ifdef CONFIG_ATH9K_DEBUGFS
 672         struct ath9k_debug debug;
 673         spinlock_t nodes_lock;
 674         struct list_head nodes; /* basically, stations */
 675         unsigned int tx_complete_poll_work_seen;
 676 #endif
 677         struct ath_beacon_config cur_beacon_conf;
 678         struct delayed_work tx_complete_work;
 679         struct delayed_work hw_pll_work;
 680
 681 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
 682         struct ath_btcoex btcoex;
 683         struct ath_mci_coex mci_coex;
 684 #endif
 685
 686         struct ath_descdma txsdma;
 687
 688         struct ath_ant_comb ant_comb;
 689         u8 ant_tx, ant_rx;
 690 };
 691
 692 void ath9k_tasklet(unsigned long data);
 693 int ath_cabq_update(struct ath_softc *);
 694
 695 static inline void ath_read_cachesize(struct ath_common *common, int *csz)
 696 {
 697         common->bus_ops->read_cachesize(common, csz);
 698 }
 699
 700 extern struct ieee80211_ops ath9k_ops;
 701 extern int ath9k_modparam_nohwcrypt;
 702 extern int led_blink;
 703 extern bool is_ath9k_unloaded;
 704
 705 irqreturn_t ath_isr(int irq, void *dev);
 706 int ath9k_init_device(u16 devid, struct ath_softc *sc,
 707                     const struct ath_bus_ops *bus_ops);
 708 void ath9k_deinit_device(struct ath_softc *sc);
 709 void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw);
 710 void ath9k_reload_chainmask_settings(struct ath_softc *sc);
 711
 712 bool ath9k_uses_beacons(int type);
 713
 714 #ifdef CONFIG_ATH9K_PCI
 715 int ath_pci_init(void);
 716 void ath_pci_exit(void);
 717 #else
 718 static inline int ath_pci_init(void) { return 0; };
 719 static inline void ath_pci_exit(void) {};
 720 #endif
 721
 722 #ifdef CONFIG_ATH9K_AHB
 723 int ath_ahb_init(void);
 724 void ath_ahb_exit(void);
 725 #else
 726 static inline int ath_ahb_init(void) { return 0; };
 727 static inline void ath_ahb_exit(void) {};
 728 #endif
 729
 730 void ath9k_ps_wakeup(struct ath_softc *sc);
 731 void ath9k_ps_restore(struct ath_softc *sc);
 732
 733 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate);
 734
 735 void ath_start_rfkill_poll(struct ath_softc *sc);
 736 extern void ath9k_rfkill_poll_state(struct ieee80211_hw *hw);
 737 void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
 738                                struct ieee80211_vif *vif,
 739                                struct ath9k_vif_iter_data *iter_data);
 740
 741
 742 #endif /* ATH9K_H */