2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include <linux/etherdevice.h>
21 #include <linux/device.h>
22 #include <linux/interrupt.h>
23 #include <linux/leds.h>
24 #include <linux/completion.h>
31 * Header for the ath9k.ko driver core *only* -- hw code nor any other driver
32 * should rely on this file or its contents.
37 /* Macro to expand scalars to 64-bit objects */
39 #define ito64(x) (sizeof(x) == 1) ? \
40 (((unsigned long long int)(x)) & (0xff)) : \
42 (((unsigned long long int)(x)) & 0xffff) : \
44 (((unsigned long long int)(x)) & 0xffffffff) : \
45 (unsigned long long int)(x))
47 /* increment with wrap-around */
48 #define INCR(_l, _sz) do { \
50 (_l) &= ((_sz) - 1); \
53 /* decrement with wrap-around */
54 #define DECR(_l, _sz) do { \
56 (_l) &= ((_sz) - 1); \
59 #define TSF_TO_TU(_h,_l) \
60 ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
62 #define ATH_TXQ_SETUP(sc, i) ((sc)->tx.txqsetup & (1<<i))
69 /*************************/
70 /* Descriptor Management */
71 /*************************/
73 #define ATH_TXBUF_RESET(_bf) do { \
74 (_bf)->bf_stale = false; \
75 (_bf)->bf_lastbf = NULL; \
76 (_bf)->bf_next = NULL; \
77 memset(&((_bf)->bf_state), 0, \
78 sizeof(struct ath_buf_state)); \
81 #define ATH_RXBUF_RESET(_bf) do { \
82 (_bf)->bf_stale = false; \
86 * enum buffer_type - Buffer type flags
88 * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX)
89 * @BUF_AGGR: Indicates whether the buffer can be aggregated
90 * (used in aggregation scheduling)
97 #define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU)
98 #define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR)
100 #define ATH_TXSTATUS_RING_SIZE 64
102 #define DS2PHYS(_dd, _ds) \
103 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
104 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
105 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
109 dma_addr_t dd_desc_paddr
;
111 struct ath_buf
*dd_bufptr
;
114 int ath_descdma_setup(struct ath_softc
*sc
, struct ath_descdma
*dd
,
115 struct list_head
*head
, const char *name
,
116 int nbuf
, int ndesc
, bool is_tx
);
117 void ath_descdma_cleanup(struct ath_softc
*sc
, struct ath_descdma
*dd
,
118 struct list_head
*head
);
124 #define ATH_RXBUF 512
125 #define ATH_TXBUF 512
126 #define ATH_TXBUF_RESERVE 5
127 #define ATH_MAX_QDEPTH (ATH_TXBUF / 4 - ATH_TXBUF_RESERVE)
128 #define ATH_TXMAXTRY 13
130 #define TID_TO_WME_AC(_tid) \
131 ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \
132 (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \
133 (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \
136 #define ATH_AGGR_DELIM_SZ 4
137 #define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */
138 /* number of delimiters for encryption padding */
139 #define ATH_AGGR_ENCRYPTDELIM 10
140 /* minimum h/w qdepth to be sustained to maximize aggregation */
141 #define ATH_AGGR_MIN_QDEPTH 2
142 #define ATH_AMPDU_SUBFRAME_DEFAULT 32
144 #define IEEE80211_SEQ_SEQ_SHIFT 4
145 #define IEEE80211_SEQ_MAX 4096
146 #define IEEE80211_WEP_IVLEN 3
147 #define IEEE80211_WEP_KIDLEN 1
148 #define IEEE80211_WEP_CRCLEN 4
149 #define IEEE80211_MAX_MPDU_LEN (3840 + FCS_LEN + \
150 (IEEE80211_WEP_IVLEN + \
151 IEEE80211_WEP_KIDLEN + \
152 IEEE80211_WEP_CRCLEN))
154 /* return whether a bit at index _n in bitmap _bm is set
155 * _sz is the size of the bitmap */
156 #define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \
157 ((_bm)[(_n) >> 5] & (1 << ((_n) & 31))))
159 /* return block-ack bitmap index given sequence and starting sequence */
160 #define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1))
162 /* returns delimiter padding required given the packet length */
163 #define ATH_AGGR_GET_NDELIM(_len) \
164 (((_len) >= ATH_AGGR_MINPLEN) ? 0 : \
165 DIV_ROUND_UP(ATH_AGGR_MINPLEN - (_len), ATH_AGGR_DELIM_SZ))
167 #define BAW_WITHIN(_start, _bawsz, _seqno) \
168 ((((_seqno) - (_start)) & 4095) < (_bawsz))
170 #define ATH_AN_2_TID(_an, _tidno) (&(_an)->tid[(_tidno)])
172 #define ATH_TX_COMPLETE_POLL_INT 1000
174 enum ATH_AGGR_STATUS
{
180 #define ATH_TXFIFO_DEPTH 8
182 int mac80211_qnum
; /* mac80211 queue number, -1 means not mac80211 Q */
183 u32 axq_qnum
; /* ath9k hardware queue number */
185 struct list_head axq_q
;
190 bool axq_tx_inprogress
;
191 struct list_head axq_acq
;
192 struct list_head txq_fifo
[ATH_TXFIFO_DEPTH
];
201 struct list_head list
;
202 struct list_head tid_q
;
203 bool clear_ps_filter
;
206 struct ath_frame_info
{
209 enum ath9k_key_type keytype
;
214 struct ath_buf_state
{
219 unsigned long bfs_paprd_timestamp
;
223 struct list_head list
;
224 struct ath_buf
*bf_lastbf
; /* last buf of this unit (a frame or
226 struct ath_buf
*bf_next
; /* next subframe in the aggregate */
227 struct sk_buff
*bf_mpdu
; /* enclosing frame structure */
228 void *bf_desc
; /* virtual addr of desc */
229 dma_addr_t bf_daddr
; /* physical addr of desc */
230 dma_addr_t bf_buf_addr
; /* physical addr of data buffer, for DMA */
232 struct ath_buf_state bf_state
;
236 struct list_head list
;
237 struct sk_buff_head buf_q
;
239 struct ath_atx_ac
*ac
;
240 unsigned long tx_buf
[BITS_TO_LONGS(ATH_TID_MAX_BUFS
)];
245 int baw_head
; /* first un-acked tx buffer */
246 int baw_tail
; /* next unused tx buffer slot */
253 #ifdef CONFIG_ATH9K_DEBUGFS
254 struct list_head list
; /* for sc->nodes */
255 struct ieee80211_sta
*sta
; /* station struct we're part of */
256 struct ieee80211_vif
*vif
; /* interface with which we're associated */
258 struct ath_atx_tid tid
[WME_NUM_TID
];
259 struct ath_atx_ac ac
[WME_NUM_AC
];
268 #define AGGR_CLEANUP BIT(1)
269 #define AGGR_ADDBA_COMPLETE BIT(2)
270 #define AGGR_ADDBA_PROGRESS BIT(3)
272 struct ath_tx_control
{
278 #define ATH_TX_ERROR 0x01
279 #define ATH_TX_BAR 0x02
282 * @txq_map: Index is mac80211 queue number. This is
283 * not necessarily the same as the hardware queue number
289 spinlock_t txbuflock
;
290 struct list_head txbuf
;
291 struct ath_txq txq
[ATH9K_NUM_TX_QUEUES
];
292 struct ath_descdma txdma
;
293 struct ath_txq
*txq_map
[WME_NUM_AC
];
297 struct sk_buff_head rx_fifo
;
298 struct sk_buff_head rx_buffers
;
306 unsigned int rxfilter
;
307 spinlock_t rxbuflock
;
308 struct list_head rxbuf
;
309 struct ath_descdma rxdma
;
310 struct ath_buf
*rx_bufptr
;
311 struct ath_rx_edma rx_edma
[ATH9K_RX_QUEUE_MAX
];
313 struct sk_buff
*frag
;
316 int ath_startrecv(struct ath_softc
*sc
);
317 bool ath_stoprecv(struct ath_softc
*sc
);
318 void ath_flushrecv(struct ath_softc
*sc
);
319 u32
ath_calcrxfilter(struct ath_softc
*sc
);
320 int ath_rx_init(struct ath_softc
*sc
, int nbufs
);
321 void ath_rx_cleanup(struct ath_softc
*sc
);
322 int ath_rx_tasklet(struct ath_softc
*sc
, int flush
, bool hp
);
323 struct ath_txq
*ath_txq_setup(struct ath_softc
*sc
, int qtype
, int subtype
);
324 void ath_tx_cleanupq(struct ath_softc
*sc
, struct ath_txq
*txq
);
325 bool ath_drain_all_txq(struct ath_softc
*sc
, bool retry_tx
);
326 void ath_draintxq(struct ath_softc
*sc
,
327 struct ath_txq
*txq
, bool retry_tx
);
328 void ath_tx_node_init(struct ath_softc
*sc
, struct ath_node
*an
);
329 void ath_tx_node_cleanup(struct ath_softc
*sc
, struct ath_node
*an
);
330 void ath_txq_schedule(struct ath_softc
*sc
, struct ath_txq
*txq
);
331 int ath_tx_init(struct ath_softc
*sc
, int nbufs
);
332 void ath_tx_cleanup(struct ath_softc
*sc
);
333 int ath_txq_update(struct ath_softc
*sc
, int qnum
,
334 struct ath9k_tx_queue_info
*q
);
335 int ath_tx_start(struct ieee80211_hw
*hw
, struct sk_buff
*skb
,
336 struct ath_tx_control
*txctl
);
337 void ath_tx_tasklet(struct ath_softc
*sc
);
338 void ath_tx_edma_tasklet(struct ath_softc
*sc
);
339 int ath_tx_aggr_start(struct ath_softc
*sc
, struct ieee80211_sta
*sta
,
341 void ath_tx_aggr_stop(struct ath_softc
*sc
, struct ieee80211_sta
*sta
, u16 tid
);
342 void ath_tx_aggr_resume(struct ath_softc
*sc
, struct ieee80211_sta
*sta
, u16 tid
);
344 void ath_tx_aggr_wakeup(struct ath_softc
*sc
, struct ath_node
*an
);
345 void ath_tx_aggr_sleep(struct ieee80211_sta
*sta
, struct ath_softc
*sc
,
346 struct ath_node
*an
);
354 bool is_bslot_active
, primary_sta_vif
;
355 __le64 tsf_adjust
; /* TSF adjustment for staggered beacons */
356 struct ath_buf
*av_bcbuf
;
359 /*******************/
360 /* Beacon Handling */
361 /*******************/
364 * Regardless of the number of beacons we stagger, (i.e. regardless of the
365 * number of BSSIDs) if a given beacon does not go out even after waiting this
366 * number of beacon intervals, the game's up.
368 #define BSTUCK_THRESH 9
370 #define ATH_DEFAULT_BINTVAL 100 /* TU */
371 #define ATH_DEFAULT_BMISS_LIMIT 10
372 #define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024)
374 struct ath_beacon_config
{
384 OK
, /* no change needed */
385 UPDATE
, /* update pending */
386 COMMIT
/* beacon sent, commit change */
387 } updateslot
; /* slot time update fsm */
393 struct ieee80211_vif
*bslot
[ATH_BCBUF
];
396 struct ath9k_tx_queue_info beacon_qi
;
397 struct ath_descdma bdma
;
398 struct ath_txq
*cabq
;
399 struct list_head bbuf
;
405 void ath_beacon_tasklet(unsigned long data
);
406 void ath_beacon_config(struct ath_softc
*sc
, struct ieee80211_vif
*vif
);
407 int ath_beacon_alloc(struct ath_softc
*sc
, struct ieee80211_vif
*vif
);
408 void ath_beacon_return(struct ath_softc
*sc
, struct ath_vif
*avp
);
409 int ath_beaconq_config(struct ath_softc
*sc
);
410 void ath_set_beacon(struct ath_softc
*sc
);
411 void ath9k_set_beaconing_status(struct ath_softc
*sc
, bool status
);
417 #define ATH_STA_SHORT_CALINTERVAL 1000 /* 1 second */
418 #define ATH_AP_SHORT_CALINTERVAL 100 /* 100 ms */
419 #define ATH_ANI_POLLINTERVAL_OLD 100 /* 100 ms */
420 #define ATH_ANI_POLLINTERVAL_NEW 1000 /* 1000 ms */
421 #define ATH_LONG_CALINTERVAL_INT 1000 /* 1000 ms */
422 #define ATH_LONG_CALINTERVAL 30000 /* 30 seconds */
423 #define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes */
425 #define ATH_PAPRD_TIMEOUT 100 /* msecs */
427 void ath_reset_work(struct work_struct
*work
);
428 void ath_hw_check(struct work_struct
*work
);
429 void ath_hw_pll_work(struct work_struct
*work
);
430 void ath_paprd_calibrate(struct work_struct
*work
);
431 void ath_ani_calibrate(unsigned long data
);
432 void ath_start_ani(struct ath_common
*common
);
439 bool hw_timer_enabled
;
440 spinlock_t btcoex_lock
;
441 struct timer_list period_timer
; /* Timer for BT period */
443 unsigned long bt_priority_time
;
444 int bt_stomp_type
; /* Types of BT stomping */
445 u32 btcoex_no_stomp
; /* in usec */
446 u32 btcoex_period
; /* in usec */
447 u32 btscan_no_stomp
; /* in usec */
449 struct ath_gen_timer
*no_stomp_timer
; /* Timer for no BT stomping */
450 struct ath_mci_profile mci
;
453 int ath_init_btcoex_timer(struct ath_softc
*sc
);
454 void ath9k_btcoex_timer_resume(struct ath_softc
*sc
);
455 void ath9k_btcoex_timer_pause(struct ath_softc
*sc
);
457 /********************/
459 /********************/
461 #define ATH_LED_PIN_DEF 1
462 #define ATH_LED_PIN_9287 8
463 #define ATH_LED_PIN_9300 10
464 #define ATH_LED_PIN_9485 6
465 #define ATH_LED_PIN_9462 4
467 #ifdef CONFIG_MAC80211_LEDS
468 void ath_init_leds(struct ath_softc
*sc
);
469 void ath_deinit_leds(struct ath_softc
*sc
);
471 static inline void ath_init_leds(struct ath_softc
*sc
)
475 static inline void ath_deinit_leds(struct ath_softc
*sc
)
481 /* Antenna diversity/combining */
482 #define ATH_ANT_RX_CURRENT_SHIFT 4
483 #define ATH_ANT_RX_MAIN_SHIFT 2
484 #define ATH_ANT_RX_MASK 0x3
486 #define ATH_ANT_DIV_COMB_SHORT_SCAN_INTR 50
487 #define ATH_ANT_DIV_COMB_SHORT_SCAN_PKTCOUNT 0x100
488 #define ATH_ANT_DIV_COMB_MAX_PKTCOUNT 0x200
489 #define ATH_ANT_DIV_COMB_INIT_COUNT 95
490 #define ATH_ANT_DIV_COMB_MAX_COUNT 100
491 #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO 30
492 #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO2 20
494 #define ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA -1
495 #define ATH_ANT_DIV_COMB_LNA1_DELTA_HI -4
496 #define ATH_ANT_DIV_COMB_LNA1_DELTA_MID -2
497 #define ATH_ANT_DIV_COMB_LNA1_DELTA_LOW 2
499 enum ath9k_ant_div_comb_lna_conf
{
500 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2
,
501 ATH_ANT_DIV_COMB_LNA2
,
502 ATH_ANT_DIV_COMB_LNA1
,
503 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2
,
506 struct ath_ant_comb
{
525 enum ath9k_ant_div_comb_lna_conf first_quick_scan_conf
;
526 enum ath9k_ant_div_comb_lna_conf second_quick_scan_conf
;
531 unsigned long scan_start_time
;
534 /********************/
535 /* Main driver core */
536 /********************/
539 * Default cache line size, in bytes.
540 * Used when PCI device not fully initialized by bootrom/BIOS
542 #define DEFAULT_CACHELINE 32
543 #define ATH_REGCLASSIDS_MAX 10
544 #define ATH_CABQ_READY_TIME 80 /* % of beacon interval */
545 #define ATH_MAX_SW_RETRIES 30
546 #define ATH_CHAN_MAX 255
548 #define ATH_TXPOWER_MAX 100 /* .5 dBm units */
549 #define ATH_RATE_DUMMY_MARKER 0
551 #define SC_OP_INVALID BIT(0)
552 #define SC_OP_BEACONS BIT(1)
553 #define SC_OP_RXAGGR BIT(2)
554 #define SC_OP_TXAGGR BIT(3)
555 #define SC_OP_OFFCHANNEL BIT(4)
556 #define SC_OP_PREAMBLE_SHORT BIT(5)
557 #define SC_OP_PROTECT_ENABLE BIT(6)
558 #define SC_OP_RXFLUSH BIT(7)
559 #define SC_OP_LED_ASSOCIATED BIT(8)
560 #define SC_OP_LED_ON BIT(9)
561 #define SC_OP_TSF_RESET BIT(11)
562 #define SC_OP_BT_PRIORITY_DETECTED BIT(12)
563 #define SC_OP_BT_SCAN BIT(13)
564 #define SC_OP_ANI_RUN BIT(14)
565 #define SC_OP_PRIM_STA_VIF BIT(15)
567 /* Powersave flags */
568 #define PS_WAIT_FOR_BEACON BIT(0)
569 #define PS_WAIT_FOR_CAB BIT(1)
570 #define PS_WAIT_FOR_PSPOLL_DATA BIT(2)
571 #define PS_WAIT_FOR_TX_ACK BIT(3)
572 #define PS_BEACON_SYNC BIT(4)
574 struct ath_rate_table
;
576 struct ath9k_vif_iter_data
{
577 const u8
*hw_macaddr
; /* phy's hardware address, set
578 * before starting iteration for
581 u8 mask
[ETH_ALEN
]; /* bssid mask */
582 int naps
; /* number of AP vifs */
583 int nmeshes
; /* number of mesh vifs */
584 int nstations
; /* number of station vifs */
585 int nwds
; /* number of WDS vifs */
586 int nadhocs
; /* number of adhoc vifs */
587 int nothers
; /* number of vifs not specified above. */
591 struct ieee80211_hw
*hw
;
596 struct survey_info
*cur_survey
;
597 struct survey_info survey
[ATH9K_NUM_CHANNELS
];
599 struct tasklet_struct intr_tq
;
600 struct tasklet_struct bcon_tasklet
;
601 struct ath_hw
*sc_ah
;
604 spinlock_t sc_serial_rw
;
605 spinlock_t sc_pm_lock
;
606 spinlock_t sc_pcu_lock
;
608 struct work_struct paprd_work
;
609 struct work_struct hw_check_work
;
610 struct work_struct hw_reset_work
;
611 struct completion paprd_complete
;
613 unsigned int hw_busy_count
;
616 u32 sc_flags
; /* SC_OP_* */
617 u16 ps_flags
; /* PS_* */
623 unsigned long ps_usecount
;
625 struct ath_config config
;
628 struct ath_beacon beacon
;
629 struct ieee80211_supported_band sbands
[IEEE80211_NUM_BANDS
];
631 #ifdef CONFIG_MAC80211_LEDS
634 struct led_classdev led_cdev
;
637 struct ath9k_hw_cal_data caldata
;
640 #ifdef CONFIG_ATH9K_DEBUGFS
641 struct ath9k_debug debug
;
642 spinlock_t nodes_lock
;
643 struct list_head nodes
; /* basically, stations */
644 unsigned int tx_complete_poll_work_seen
;
646 struct ath_beacon_config cur_beacon_conf
;
647 struct delayed_work tx_complete_work
;
648 struct delayed_work hw_pll_work
;
649 struct ath_btcoex btcoex
;
650 struct ath_mci_coex mci_coex
;
652 struct ath_descdma txsdma
;
654 struct ath_ant_comb ant_comb
;
658 void ath9k_tasklet(unsigned long data
);
659 int ath_cabq_update(struct ath_softc
*);
661 static inline void ath_read_cachesize(struct ath_common
*common
, int *csz
)
663 common
->bus_ops
->read_cachesize(common
, csz
);
666 extern struct ieee80211_ops ath9k_ops
;
667 extern int ath9k_modparam_nohwcrypt
;
668 extern int led_blink
;
669 extern bool is_ath9k_unloaded
;
671 irqreturn_t
ath_isr(int irq
, void *dev
);
672 int ath9k_init_device(u16 devid
, struct ath_softc
*sc
,
673 const struct ath_bus_ops
*bus_ops
);
674 void ath9k_deinit_device(struct ath_softc
*sc
);
675 void ath9k_set_hw_capab(struct ath_softc
*sc
, struct ieee80211_hw
*hw
);
676 void ath9k_reload_chainmask_settings(struct ath_softc
*sc
);
678 void ath_radio_disable(struct ath_softc
*sc
, struct ieee80211_hw
*hw
);
679 bool ath9k_uses_beacons(int type
);
681 #ifdef CONFIG_ATH9K_PCI
682 int ath_pci_init(void);
683 void ath_pci_exit(void);
685 static inline int ath_pci_init(void) { return 0; };
686 static inline void ath_pci_exit(void) {};
689 #ifdef CONFIG_ATH9K_AHB
690 int ath_ahb_init(void);
691 void ath_ahb_exit(void);
693 static inline int ath_ahb_init(void) { return 0; };
694 static inline void ath_ahb_exit(void) {};
697 void ath9k_ps_wakeup(struct ath_softc
*sc
);
698 void ath9k_ps_restore(struct ath_softc
*sc
);
700 u8
ath_txchainmask_reduction(struct ath_softc
*sc
, u8 chainmask
, u32 rate
);
702 void ath_start_rfkill_poll(struct ath_softc
*sc
);
703 extern void ath9k_rfkill_poll_state(struct ieee80211_hw
*hw
);
704 void ath9k_calculate_iter_data(struct ieee80211_hw
*hw
,
705 struct ieee80211_vif
*vif
,
706 struct ath9k_vif_iter_data
*iter_data
);