drivers/net/wireless/ath/ath9k/ath9k.h

   1 /*
   2  * Copyright (c) 2008-2011 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #ifndef ATH9K_H
  18 #define ATH9K_H
  19
  20 #include <linux/etherdevice.h>
  21 #include <linux/device.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/leds.h>
  24 #include <linux/completion.h>
  25
  26 #include "debug.h"
  27 #include "common.h"
  28 #include "mci.h"
  29 #include "dfs.h"
  30 #include "spectral.h"
  31
  32 struct ath_node;
  33
  34 extern struct ieee80211_ops ath9k_ops;
  35 extern int ath9k_modparam_nohwcrypt;
  36 extern int led_blink;
  37 extern bool is_ath9k_unloaded;
  38
  39 struct ath_config {
  40         u16 txpowlimit;
  41 };
  42
  43 /*************************/
  44 /* Descriptor Management */
  45 /*************************/
  46
  47 #define ATH_TXSTATUS_RING_SIZE 512
  48
  49 /* Macro to expand scalars to 64-bit objects */
  50 #define ito64(x) (sizeof(x) == 1) ?                     \
  51         (((unsigned long long int)(x)) & (0xff)) :      \
  52         (sizeof(x) == 2) ?                              \
  53         (((unsigned long long int)(x)) & 0xffff) :      \
  54         ((sizeof(x) == 4) ?                             \
  55          (((unsigned long long int)(x)) & 0xffffffff) : \
  56          (unsigned long long int)(x))
  57
  58 #define ATH_TXBUF_RESET(_bf) do {                               \
  59                 (_bf)->bf_lastbf = NULL;                        \
  60                 (_bf)->bf_next = NULL;                          \
  61                 memset(&((_bf)->bf_state), 0,                   \
  62                        sizeof(struct ath_buf_state));           \
  63         } while (0)
  64
  65 #define DS2PHYS(_dd, _ds)                                               \
  66         ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
  67 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
  68 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
  69
  70 struct ath_descdma {
  71         void *dd_desc;
  72         dma_addr_t dd_desc_paddr;
  73         u32 dd_desc_len;
  74 };
  75
  76 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
  77                       struct list_head *head, const char *name,
  78                       int nbuf, int ndesc, bool is_tx);
  79
  80 /***********/
  81 /* RX / TX */
  82 /***********/
  83
  84 #define ATH_TXQ_SETUP(sc, i) ((sc)->tx.txqsetup & (1<<i))
  85
  86 /* increment with wrap-around */
  87 #define INCR(_l, _sz)   do {                    \
  88                 (_l)++;                         \
  89                 (_l) &= ((_sz) - 1);            \
  90         } while (0)
  91
  92 #define ATH_RXBUF               512
  93 #define ATH_TXBUF               512
  94 #define ATH_TXBUF_RESERVE       5
  95 #define ATH_MAX_QDEPTH          (ATH_TXBUF / 4 - ATH_TXBUF_RESERVE)
  96 #define ATH_TXMAXTRY            13
  97 #define ATH_MAX_SW_RETRIES      30
  98
  99 #define TID_TO_WME_AC(_tid)                             \
 100         ((((_tid) == 0) || ((_tid) == 3)) ? IEEE80211_AC_BE :   \
 101          (((_tid) == 1) || ((_tid) == 2)) ? IEEE80211_AC_BK :   \
 102          (((_tid) == 4) || ((_tid) == 5)) ? IEEE80211_AC_VI :   \
 103          IEEE80211_AC_VO)
 104
 105 #define ATH_AGGR_DELIM_SZ          4
 106 #define ATH_AGGR_MINPLEN           256 /* in bytes, minimum packet length */
 107 /* number of delimiters for encryption padding */
 108 #define ATH_AGGR_ENCRYPTDELIM      10
 109 /* minimum h/w qdepth to be sustained to maximize aggregation */
 110 #define ATH_AGGR_MIN_QDEPTH        2
 111 /* minimum h/w qdepth for non-aggregated traffic */
 112 #define ATH_NON_AGGR_MIN_QDEPTH    8
 113 #define ATH_TX_COMPLETE_POLL_INT   1000
 114 #define ATH_TXFIFO_DEPTH           8
 115 #define ATH_TX_ERROR               0x01
 116
 117 #define IEEE80211_SEQ_SEQ_SHIFT    4
 118 #define IEEE80211_SEQ_MAX          4096
 119 #define IEEE80211_WEP_IVLEN        3
 120 #define IEEE80211_WEP_KIDLEN       1
 121 #define IEEE80211_WEP_CRCLEN       4
 122 #define IEEE80211_MAX_MPDU_LEN     (3840 + FCS_LEN +            \
 123                                     (IEEE80211_WEP_IVLEN +      \
 124                                      IEEE80211_WEP_KIDLEN +     \
 125                                      IEEE80211_WEP_CRCLEN))
 126
 127 /* return whether a bit at index _n in bitmap _bm is set
 128  * _sz is the size of the bitmap  */
 129 #define ATH_BA_ISSET(_bm, _n)  (((_n) < (WME_BA_BMP_SIZE)) &&           \
 130                                 ((_bm)[(_n) >> 5] & (1 << ((_n) & 31))))
 131
 132 /* return block-ack bitmap index given sequence and starting sequence */
 133 #define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1))
 134
 135 /* return the seqno for _start + _offset */
 136 #define ATH_BA_INDEX2SEQ(_seq, _offset) (((_seq) + (_offset)) & (IEEE80211_SEQ_MAX - 1))
 137
 138 /* returns delimiter padding required given the packet length */
 139 #define ATH_AGGR_GET_NDELIM(_len)                                       \
 140        (((_len) >= ATH_AGGR_MINPLEN) ? 0 :                             \
 141         DIV_ROUND_UP(ATH_AGGR_MINPLEN - (_len), ATH_AGGR_DELIM_SZ))
 142
 143 #define BAW_WITHIN(_start, _bawsz, _seqno) \
 144         ((((_seqno) - (_start)) & 4095) < (_bawsz))
 145
 146 #define ATH_AN_2_TID(_an, _tidno)  (&(_an)->tid[(_tidno)])
 147
 148 #define IS_HT_RATE(rate)   (rate & 0x80)
 149 #define IS_CCK_RATE(rate)  ((rate >= 0x18) && (rate <= 0x1e))
 150 #define IS_OFDM_RATE(rate) ((rate >= 0x8) && (rate <= 0xf))
 151
 152 enum {
 153        WLAN_RC_PHY_OFDM,
 154        WLAN_RC_PHY_CCK,
 155 };
 156
 157 struct ath_txq {
 158         int mac80211_qnum; /* mac80211 queue number, -1 means not mac80211 Q */
 159         u32 axq_qnum; /* ath9k hardware queue number */
 160         void *axq_link;
 161         struct list_head axq_q;
 162         spinlock_t axq_lock;
 163         u32 axq_depth;
 164         u32 axq_ampdu_depth;
 165         bool stopped;
 166         bool axq_tx_inprogress;
 167         struct list_head axq_acq;
 168         struct list_head txq_fifo[ATH_TXFIFO_DEPTH];
 169         u8 txq_headidx;
 170         u8 txq_tailidx;
 171         int pending_frames;
 172         struct sk_buff_head complete_q;
 173 };
 174
 175 struct ath_atx_ac {
 176         struct ath_txq *txq;
 177         struct list_head list;
 178         struct list_head tid_q;
 179         bool clear_ps_filter;
 180         bool sched;
 181 };
 182
 183 struct ath_frame_info {
 184         struct ath_buf *bf;
 185         int framelen;
 186         enum ath9k_key_type keytype;
 187         u8 keyix;
 188         u8 rtscts_rate;
 189         u8 retries : 7;
 190         u8 baw_tracked : 1;
 191 };
 192
 193 struct ath_rxbuf {
 194         struct list_head list;
 195         struct sk_buff *bf_mpdu;
 196         void *bf_desc;
 197         dma_addr_t bf_daddr;
 198         dma_addr_t bf_buf_addr;
 199 };
 200
 201 /**
 202  * enum buffer_type - Buffer type flags
 203  *
 204  * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX)
 205  * @BUF_AGGR: Indicates whether the buffer can be aggregated
 206  *      (used in aggregation scheduling)
 207  */
 208 enum buffer_type {
 209         BUF_AMPDU               = BIT(0),
 210         BUF_AGGR                = BIT(1),
 211 };
 212
 213 #define bf_isampdu(bf)          (bf->bf_state.bf_type & BUF_AMPDU)
 214 #define bf_isaggr(bf)           (bf->bf_state.bf_type & BUF_AGGR)
 215
 216 struct ath_buf_state {
 217         u8 bf_type;
 218         u8 bfs_paprd;
 219         u8 ndelim;
 220         bool stale;
 221         u16 seqno;
 222         unsigned long bfs_paprd_timestamp;
 223 };
 224
 225 struct ath_buf {
 226         struct list_head list;
 227         struct ath_buf *bf_lastbf;      /* last buf of this unit (a frame or
 228                                            an aggregate) */
 229         struct ath_buf *bf_next;        /* next subframe in the aggregate */
 230         struct sk_buff *bf_mpdu;        /* enclosing frame structure */
 231         void *bf_desc;                  /* virtual addr of desc */
 232         dma_addr_t bf_daddr;            /* physical addr of desc */
 233         dma_addr_t bf_buf_addr; /* physical addr of data buffer, for DMA */
 234         struct ieee80211_tx_rate rates[4];
 235         struct ath_buf_state bf_state;
 236 };
 237
 238 struct ath_atx_tid {
 239         struct list_head list;
 240         struct sk_buff_head buf_q;
 241         struct sk_buff_head retry_q;
 242         struct ath_node *an;
 243         struct ath_atx_ac *ac;
 244         unsigned long tx_buf[BITS_TO_LONGS(ATH_TID_MAX_BUFS)];
 245         u16 seq_start;
 246         u16 seq_next;
 247         u16 baw_size;
 248         u8 tidno;
 249         int baw_head;   /* first un-acked tx buffer */
 250         int baw_tail;   /* next unused tx buffer slot */
 251
 252         s8 bar_index;
 253         bool sched;
 254         bool paused;
 255         bool active;
 256 };
 257
 258 struct ath_node {
 259         struct ath_softc *sc;
 260         struct ieee80211_sta *sta; /* station struct we're part of */
 261         struct ieee80211_vif *vif; /* interface with which we're associated */
 262         struct ath_atx_tid tid[IEEE80211_NUM_TIDS];
 263         struct ath_atx_ac ac[IEEE80211_NUM_ACS];
 264
 265         u16 maxampdu;
 266         u8 mpdudensity;
 267         s8 ps_key;
 268
 269         bool sleeping;
 270         bool no_ps_filter;
 271
 272 #ifdef CONFIG_ATH9K_STATION_STATISTICS
 273         struct ath_rx_rate_stats rx_rate_stats;
 274 #endif
 275 };
 276
 277 struct ath_tx_control {
 278         struct ath_txq *txq;
 279         struct ath_node *an;
 280         u8 paprd;
 281         struct ieee80211_sta *sta;
 282 };
 283
 284
 285 /**
 286  * @txq_map:  Index is mac80211 queue number.  This is
 287  *  not necessarily the same as the hardware queue number
 288  *  (axq_qnum).
 289  */
 290 struct ath_tx {
 291         u16 seq_no;
 292         u32 txqsetup;
 293         spinlock_t txbuflock;
 294         struct list_head txbuf;
 295         struct ath_txq txq[ATH9K_NUM_TX_QUEUES];
 296         struct ath_descdma txdma;
 297         struct ath_txq *txq_map[IEEE80211_NUM_ACS];
 298         struct ath_txq *uapsdq;
 299         u32 txq_max_pending[IEEE80211_NUM_ACS];
 300         u16 max_aggr_framelen[IEEE80211_NUM_ACS][4][32];
 301 };
 302
 303 struct ath_rx_edma {
 304         struct sk_buff_head rx_fifo;
 305         u32 rx_fifo_hwsize;
 306 };
 307
 308 struct ath_rx {
 309         u8 defant;
 310         u8 rxotherant;
 311         bool discard_next;
 312         u32 *rxlink;
 313         u32 num_pkts;
 314         unsigned int rxfilter;
 315         struct list_head rxbuf;
 316         struct ath_descdma rxdma;
 317         struct ath_rx_edma rx_edma[ATH9K_RX_QUEUE_MAX];
 318
 319         struct ath_rxbuf *buf_hold;
 320         struct sk_buff *frag;
 321
 322         u32 ampdu_ref;
 323 };
 324
 325 int ath_startrecv(struct ath_softc *sc);
 326 bool ath_stoprecv(struct ath_softc *sc);
 327 u32 ath_calcrxfilter(struct ath_softc *sc);
 328 int ath_rx_init(struct ath_softc *sc, int nbufs);
 329 void ath_rx_cleanup(struct ath_softc *sc);
 330 int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp);
 331 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
 332 void ath_txq_lock(struct ath_softc *sc, struct ath_txq *txq);
 333 void ath_txq_unlock(struct ath_softc *sc, struct ath_txq *txq);
 334 void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq);
 335 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
 336 bool ath_drain_all_txq(struct ath_softc *sc);
 337 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq);
 338 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an);
 339 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an);
 340 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq);
 341 int ath_tx_init(struct ath_softc *sc, int nbufs);
 342 int ath_txq_update(struct ath_softc *sc, int qnum,
 343                    struct ath9k_tx_queue_info *q);
 344 void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop);
 345 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
 346                  struct ath_tx_control *txctl);
 347 void ath_tx_cabq(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
 348                  struct sk_buff *skb);
 349 void ath_tx_tasklet(struct ath_softc *sc);
 350 void ath_tx_edma_tasklet(struct ath_softc *sc);
 351 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
 352                       u16 tid, u16 *ssn);
 353 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
 354 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
 355
 356 void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an);
 357 void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc,
 358                        struct ath_node *an);
 359 void ath9k_release_buffered_frames(struct ieee80211_hw *hw,
 360                                    struct ieee80211_sta *sta,
 361                                    u16 tids, int nframes,
 362                                    enum ieee80211_frame_release_type reason,
 363                                    bool more_data);
 364
 365 /********/
 366 /* VIFs */
 367 /********/
 368
 369 struct ath_vif {
 370         struct ath_node mcast_node;
 371         int av_bslot;
 372         bool primary_sta_vif;
 373         __le64 tsf_adjust; /* TSF adjustment for staggered beacons */
 374         struct ath_buf *av_bcbuf;
 375 };
 376
 377 struct ath9k_vif_iter_data {
 378         u8 hw_macaddr[ETH_ALEN]; /* address of the first vif */
 379         u8 mask[ETH_ALEN]; /* bssid mask */
 380         bool has_hw_macaddr;
 381
 382         int naps;      /* number of AP vifs */
 383         int nmeshes;   /* number of mesh vifs */
 384         int nstations; /* number of station vifs */
 385         int nwds;      /* number of WDS vifs */
 386         int nadhocs;   /* number of adhoc vifs */
 387 };
 388
 389 void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
 390                                struct ieee80211_vif *vif,
 391                                struct ath9k_vif_iter_data *iter_data);
 392
 393 /*******************/
 394 /* Beacon Handling */
 395 /*******************/
 396
 397 /*
 398  * Regardless of the number of beacons we stagger, (i.e. regardless of the
 399  * number of BSSIDs) if a given beacon does not go out even after waiting this
 400  * number of beacon intervals, the game's up.
 401  */
 402 #define BSTUCK_THRESH                   9
 403 #define ATH_BCBUF                       8
 404 #define ATH_DEFAULT_BINTVAL             100 /* TU */
 405 #define ATH_DEFAULT_BMISS_LIMIT         10
 406 #define IEEE80211_MS_TO_TU(x)           (((x) * 1000) / 1024)
 407
 408 #define TSF_TO_TU(_h,_l) \
 409         ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
 410
 411 struct ath_beacon_config {
 412         int beacon_interval;
 413         u16 listen_interval;
 414         u16 dtim_period;
 415         u16 bmiss_timeout;
 416         u8 dtim_count;
 417         bool enable_beacon;
 418         bool ibss_creator;
 419 };
 420
 421 struct ath_beacon {
 422         enum {
 423                 OK,             /* no change needed */
 424                 UPDATE,         /* update pending */
 425                 COMMIT          /* beacon sent, commit change */
 426         } updateslot;           /* slot time update fsm */
 427
 428         u32 beaconq;
 429         u32 bmisscnt;
 430         u32 bc_tstamp;
 431         struct ieee80211_vif *bslot[ATH_BCBUF];
 432         int slottime;
 433         int slotupdate;
 434         struct ath9k_tx_queue_info beacon_qi;
 435         struct ath_descdma bdma;
 436         struct ath_txq *cabq;
 437         struct list_head bbuf;
 438
 439         bool tx_processed;
 440         bool tx_last;
 441 };
 442
 443 void ath9k_beacon_tasklet(unsigned long data);
 444 void ath9k_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif,
 445                          u32 changed);
 446 void ath9k_beacon_assign_slot(struct ath_softc *sc, struct ieee80211_vif *vif);
 447 void ath9k_beacon_remove_slot(struct ath_softc *sc, struct ieee80211_vif *vif);
 448 void ath9k_set_beacon(struct ath_softc *sc);
 449 bool ath9k_csa_is_finished(struct ath_softc *sc, struct ieee80211_vif *vif);
 450 void ath9k_csa_update(struct ath_softc *sc);
 451
 452 /*******************/
 453 /* Link Monitoring */
 454 /*******************/
 455
 456 #define ATH_STA_SHORT_CALINTERVAL 1000    /* 1 second */
 457 #define ATH_AP_SHORT_CALINTERVAL  100     /* 100 ms */
 458 #define ATH_ANI_POLLINTERVAL_OLD  100     /* 100 ms */
 459 #define ATH_ANI_POLLINTERVAL_NEW  1000    /* 1000 ms */
 460 #define ATH_LONG_CALINTERVAL_INT  1000    /* 1000 ms */
 461 #define ATH_LONG_CALINTERVAL      30000   /* 30 seconds */
 462 #define ATH_RESTART_CALINTERVAL   1200000 /* 20 minutes */
 463 #define ATH_ANI_MAX_SKIP_COUNT    10
 464 #define ATH_PAPRD_TIMEOUT         100 /* msecs */
 465 #define ATH_PLL_WORK_INTERVAL     100
 466
 467 void ath_tx_complete_poll_work(struct work_struct *work);
 468 void ath_reset_work(struct work_struct *work);
 469 bool ath_hw_check(struct ath_softc *sc);
 470 void ath_hw_pll_work(struct work_struct *work);
 471 void ath_paprd_calibrate(struct work_struct *work);
 472 void ath_ani_calibrate(unsigned long data);
 473 void ath_start_ani(struct ath_softc *sc);
 474 void ath_stop_ani(struct ath_softc *sc);
 475 void ath_check_ani(struct ath_softc *sc);
 476 int ath_update_survey_stats(struct ath_softc *sc);
 477 void ath_update_survey_nf(struct ath_softc *sc, int channel);
 478 void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type);
 479 void ath_ps_full_sleep(unsigned long data);
 480
 481 /**********/
 482 /* BTCOEX */
 483 /**********/
 484
 485 #define ATH_DUMP_BTCOEX(_s, _val)                               \
 486         do {                                                    \
 487                 len += scnprintf(buf + len, size - len,         \
 488                                  "%20s : %10d\n", _s, (_val));  \
 489         } while (0)
 490
 491 enum bt_op_flags {
 492         BT_OP_PRIORITY_DETECTED,
 493         BT_OP_SCAN,
 494 };
 495
 496 struct ath_btcoex {
 497         spinlock_t btcoex_lock;
 498         struct timer_list period_timer; /* Timer for BT period */
 499         struct timer_list no_stomp_timer;
 500         u32 bt_priority_cnt;
 501         unsigned long bt_priority_time;
 502         unsigned long op_flags;
 503         int bt_stomp_type; /* Types of BT stomping */
 504         u32 btcoex_no_stomp; /* in msec */
 505         u32 btcoex_period; /* in msec */
 506         u32 btscan_no_stomp; /* in msec */
 507         u32 duty_cycle;
 508         u32 bt_wait_time;
 509         int rssi_count;
 510         struct ath_mci_profile mci;
 511         u8 stomp_audio;
 512 };
 513
 514 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
 515 int ath9k_init_btcoex(struct ath_softc *sc);
 516 void ath9k_deinit_btcoex(struct ath_softc *sc);
 517 void ath9k_start_btcoex(struct ath_softc *sc);
 518 void ath9k_stop_btcoex(struct ath_softc *sc);
 519 void ath9k_btcoex_timer_resume(struct ath_softc *sc);
 520 void ath9k_btcoex_timer_pause(struct ath_softc *sc);
 521 void ath9k_btcoex_handle_interrupt(struct ath_softc *sc, u32 status);
 522 u16 ath9k_btcoex_aggr_limit(struct ath_softc *sc, u32 max_4ms_framelen);
 523 void ath9k_btcoex_stop_gen_timer(struct ath_softc *sc);
 524 int ath9k_dump_btcoex(struct ath_softc *sc, u8 *buf, u32 size);
 525 #else
 526 static inline int ath9k_init_btcoex(struct ath_softc *sc)
 527 {
 528         return 0;
 529 }
 530 static inline void ath9k_deinit_btcoex(struct ath_softc *sc)
 531 {
 532 }
 533 static inline void ath9k_start_btcoex(struct ath_softc *sc)
 534 {
 535 }
 536 static inline void ath9k_stop_btcoex(struct ath_softc *sc)
 537 {
 538 }
 539 static inline void ath9k_btcoex_handle_interrupt(struct ath_softc *sc,
 540                                                  u32 status)
 541 {
 542 }
 543 static inline u16 ath9k_btcoex_aggr_limit(struct ath_softc *sc,
 544                                           u32 max_4ms_framelen)
 545 {
 546         return 0;
 547 }
 548 static inline void ath9k_btcoex_stop_gen_timer(struct ath_softc *sc)
 549 {
 550 }
 551 static inline int ath9k_dump_btcoex(struct ath_softc *sc, u8 *buf, u32 size)
 552 {
 553         return 0;
 554 }
 555 #endif /* CONFIG_ATH9K_BTCOEX_SUPPORT */
 556
 557 /********************/
 558 /*   LED Control    */
 559 /********************/
 560
 561 #define ATH_LED_PIN_DEF                 1
 562 #define ATH_LED_PIN_9287                8
 563 #define ATH_LED_PIN_9300                10
 564 #define ATH_LED_PIN_9485                6
 565 #define ATH_LED_PIN_9462                4
 566
 567 #ifdef CONFIG_MAC80211_LEDS
 568 void ath_init_leds(struct ath_softc *sc);
 569 void ath_deinit_leds(struct ath_softc *sc);
 570 void ath_fill_led_pin(struct ath_softc *sc);
 571 #else
 572 static inline void ath_init_leds(struct ath_softc *sc)
 573 {
 574 }
 575
 576 static inline void ath_deinit_leds(struct ath_softc *sc)
 577 {
 578 }
 579 static inline void ath_fill_led_pin(struct ath_softc *sc)
 580 {
 581 }
 582 #endif
 583
 584 /************************/
 585 /* Wake on Wireless LAN */
 586 /************************/
 587
 588 struct ath9k_wow_pattern {
 589         u8 pattern_bytes[MAX_PATTERN_SIZE];
 590         u8 mask_bytes[MAX_PATTERN_SIZE];
 591         u32 pattern_len;
 592 };
 593
 594 #ifdef CONFIG_ATH9K_WOW
 595 void ath9k_init_wow(struct ieee80211_hw *hw);
 596 int ath9k_suspend(struct ieee80211_hw *hw,
 597                   struct cfg80211_wowlan *wowlan);
 598 int ath9k_resume(struct ieee80211_hw *hw);
 599 void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled);
 600 #else
 601 static inline void ath9k_init_wow(struct ieee80211_hw *hw)
 602 {
 603 }
 604 static inline int ath9k_suspend(struct ieee80211_hw *hw,
 605                                 struct cfg80211_wowlan *wowlan)
 606 {
 607         return 0;
 608 }
 609 static inline int ath9k_resume(struct ieee80211_hw *hw)
 610 {
 611         return 0;
 612 }
 613 static inline void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled)
 614 {
 615 }
 616 #endif /* CONFIG_ATH9K_WOW */
 617
 618 /*******************************/
 619 /* Antenna diversity/combining */
 620 /*******************************/
 621
 622 #define ATH_ANT_RX_CURRENT_SHIFT 4
 623 #define ATH_ANT_RX_MAIN_SHIFT 2
 624 #define ATH_ANT_RX_MASK 0x3
 625
 626 #define ATH_ANT_DIV_COMB_SHORT_SCAN_INTR 50
 627 #define ATH_ANT_DIV_COMB_SHORT_SCAN_PKTCOUNT 0x100
 628 #define ATH_ANT_DIV_COMB_MAX_PKTCOUNT 0x200
 629 #define ATH_ANT_DIV_COMB_INIT_COUNT 95
 630 #define ATH_ANT_DIV_COMB_MAX_COUNT 100
 631 #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO 30
 632 #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO2 20
 633 #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO_LOW_RSSI 50
 634 #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO2_LOW_RSSI 50
 635
 636 #define ATH_ANT_DIV_COMB_LNA1_DELTA_HI -4
 637 #define ATH_ANT_DIV_COMB_LNA1_DELTA_MID -2
 638 #define ATH_ANT_DIV_COMB_LNA1_DELTA_LOW 2
 639
 640 struct ath_ant_comb {
 641         u16 count;
 642         u16 total_pkt_count;
 643         bool scan;
 644         bool scan_not_start;
 645         int main_total_rssi;
 646         int alt_total_rssi;
 647         int alt_recv_cnt;
 648         int main_recv_cnt;
 649         int rssi_lna1;
 650         int rssi_lna2;
 651         int rssi_add;
 652         int rssi_sub;
 653         int rssi_first;
 654         int rssi_second;
 655         int rssi_third;
 656         int ant_ratio;
 657         int ant_ratio2;
 658         bool alt_good;
 659         int quick_scan_cnt;
 660         enum ath9k_ant_div_comb_lna_conf main_conf;
 661         enum ath9k_ant_div_comb_lna_conf first_quick_scan_conf;
 662         enum ath9k_ant_div_comb_lna_conf second_quick_scan_conf;
 663         bool first_ratio;
 664         bool second_ratio;
 665         unsigned long scan_start_time;
 666
 667         /*
 668          * Card-specific config values.
 669          */
 670         int low_rssi_thresh;
 671         int fast_div_bias;
 672 };
 673
 674 void ath_ant_comb_scan(struct ath_softc *sc, struct ath_rx_status *rs);
 675
 676 /********************/
 677 /* Main driver core */
 678 /********************/
 679
 680 #define ATH9K_PCI_CUS198          0x0001
 681 #define ATH9K_PCI_CUS230          0x0002
 682 #define ATH9K_PCI_CUS217          0x0004
 683 #define ATH9K_PCI_CUS252          0x0008
 684 #define ATH9K_PCI_WOW             0x0010
 685 #define ATH9K_PCI_BT_ANT_DIV      0x0020
 686 #define ATH9K_PCI_D3_L1_WAR       0x0040
 687 #define ATH9K_PCI_AR9565_1ANT     0x0080
 688 #define ATH9K_PCI_AR9565_2ANT     0x0100
 689 #define ATH9K_PCI_NO_PLL_PWRSAVE  0x0200
 690 #define ATH9K_PCI_KILLER          0x0400
 691
 692 /*
 693  * Default cache line size, in bytes.
 694  * Used when PCI device not fully initialized by bootrom/BIOS
 695 */
 696 #define DEFAULT_CACHELINE       32
 697 #define ATH_CABQ_READY_TIME     80      /* % of beacon interval */
 698 #define ATH_TXPOWER_MAX         100     /* .5 dBm units */
 699 #define MAX_GTT_CNT             5
 700
 701 enum sc_op_flags {
 702         SC_OP_INVALID,
 703         SC_OP_BEACONS,
 704         SC_OP_ANI_RUN,
 705         SC_OP_PRIM_STA_VIF,
 706         SC_OP_HW_RESET,
 707         SC_OP_SCANNING,
 708 };
 709
 710 /* Powersave flags */
 711 #define PS_WAIT_FOR_BEACON        BIT(0)
 712 #define PS_WAIT_FOR_CAB           BIT(1)
 713 #define PS_WAIT_FOR_PSPOLL_DATA   BIT(2)
 714 #define PS_WAIT_FOR_TX_ACK        BIT(3)
 715 #define PS_BEACON_SYNC            BIT(4)
 716 #define PS_WAIT_FOR_ANI           BIT(5)
 717
 718 struct ath_softc {
 719         struct ieee80211_hw *hw;
 720         struct device *dev;
 721
 722         struct survey_info *cur_survey;
 723         struct survey_info survey[ATH9K_NUM_CHANNELS];
 724
 725         struct tasklet_struct intr_tq;
 726         struct tasklet_struct bcon_tasklet;
 727         struct ath_hw *sc_ah;
 728         void __iomem *mem;
 729         int irq;
 730         spinlock_t sc_serial_rw;
 731         spinlock_t sc_pm_lock;
 732         spinlock_t sc_pcu_lock;
 733         struct mutex mutex;
 734         struct work_struct paprd_work;
 735         struct work_struct hw_reset_work;
 736         struct completion paprd_complete;
 737         wait_queue_head_t tx_wait;
 738
 739         unsigned long sc_flags;
 740         unsigned long driver_data;
 741
 742         u8 gtt_cnt;
 743         u32 intrstatus;
 744         u16 ps_flags; /* PS_* */
 745         u16 curtxpow;
 746         bool ps_enabled;
 747         bool ps_idle;
 748         short nbcnvifs;
 749         short nvifs;
 750         unsigned long ps_usecount;
 751
 752         struct ath_config config;
 753         struct ath_rx rx;
 754         struct ath_tx tx;
 755         struct ath_beacon beacon;
 756         struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
 757
 758 #ifdef CONFIG_MAC80211_LEDS
 759         bool led_registered;
 760         char led_name[32];
 761         struct led_classdev led_cdev;
 762 #endif
 763
 764         struct ath9k_hw_cal_data caldata;
 765
 766 #ifdef CONFIG_ATH9K_DEBUGFS
 767         struct ath9k_debug debug;
 768 #endif
 769         struct ath_beacon_config cur_beacon_conf;
 770         struct delayed_work tx_complete_work;
 771         struct delayed_work hw_pll_work;
 772         struct timer_list sleep_timer;
 773
 774 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
 775         struct ath_btcoex btcoex;
 776         struct ath_mci_coex mci_coex;
 777         struct work_struct mci_work;
 778 #endif
 779
 780         struct ath_descdma txsdma;
 781
 782         struct ath_ant_comb ant_comb;
 783         u8 ant_tx, ant_rx;
 784         struct dfs_pattern_detector *dfs_detector;
 785         u32 wow_enabled;
 786         /* relay(fs) channel for spectral scan */
 787         struct rchan *rfs_chan_spec_scan;
 788         enum spectral_mode spectral_mode;
 789         struct ath_spec_scan spec_config;
 790
 791         struct ieee80211_vif *tx99_vif;
 792         struct sk_buff *tx99_skb;
 793         bool tx99_state;
 794         s16 tx99_power;
 795
 796 #ifdef CONFIG_ATH9K_WOW
 797         atomic_t wow_got_bmiss_intr;
 798         atomic_t wow_sleep_proc_intr; /* in the middle of WoW sleep ? */
 799         u32 wow_intr_before_sleep;
 800 #endif
 801 };
 802
 803 /********/
 804 /* TX99 */
 805 /********/
 806
 807 #ifdef CONFIG_ATH9K_TX99
 808 void ath9k_tx99_init_debug(struct ath_softc *sc);
 809 int ath9k_tx99_send(struct ath_softc *sc, struct sk_buff *skb,
 810                     struct ath_tx_control *txctl);
 811 #else
 812 static inline void ath9k_tx99_init_debug(struct ath_softc *sc)
 813 {
 814 }
 815 static inline int ath9k_tx99_send(struct ath_softc *sc,
 816                                   struct sk_buff *skb,
 817                                   struct ath_tx_control *txctl)
 818 {
 819         return 0;
 820 }
 821 #endif /* CONFIG_ATH9K_TX99 */
 822
 823 static inline void ath_read_cachesize(struct ath_common *common, int *csz)
 824 {
 825         common->bus_ops->read_cachesize(common, csz);
 826 }
 827
 828 void ath9k_tasklet(unsigned long data);
 829 int ath_cabq_update(struct ath_softc *);
 830 u8 ath9k_parse_mpdudensity(u8 mpdudensity);
 831 irqreturn_t ath_isr(int irq, void *dev);
 832 int ath_reset(struct ath_softc *sc);
 833 void ath_cancel_work(struct ath_softc *sc);
 834 void ath_restart_work(struct ath_softc *sc);
 835 int ath9k_init_device(u16 devid, struct ath_softc *sc,
 836                     const struct ath_bus_ops *bus_ops);
 837 void ath9k_deinit_device(struct ath_softc *sc);
 838 void ath9k_reload_chainmask_settings(struct ath_softc *sc);
 839 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate);
 840 void ath_start_rfkill_poll(struct ath_softc *sc);
 841 void ath9k_rfkill_poll_state(struct ieee80211_hw *hw);
 842 void ath9k_ps_wakeup(struct ath_softc *sc);
 843 void ath9k_ps_restore(struct ath_softc *sc);
 844
 845 #ifdef CONFIG_ATH9K_PCI
 846 int ath_pci_init(void);
 847 void ath_pci_exit(void);
 848 #else
 849 static inline int ath_pci_init(void) { return 0; };
 850 static inline void ath_pci_exit(void) {};
 851 #endif
 852
 853 #ifdef CONFIG_ATH9K_AHB
 854 int ath_ahb_init(void);
 855 void ath_ahb_exit(void);
 856 #else
 857 static inline int ath_ahb_init(void) { return 0; };
 858 static inline void ath_ahb_exit(void) {};
 859 #endif
 860
 861 #endif /* ATH9K_H */