2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 /* We can tune this as we go by monitoring really low values */
20 #define ATH9K_NF_TOO_LOW -60
22 /* AR5416 may return very high value (like -31 dBm), in those cases the nf
23 * is incorrect and we should use the static NF value. Later we can try to
24 * find out why they are reporting these values */
26 static bool ath9k_hw_nf_in_range(struct ath_hw
*ah
, s16 nf
)
28 if (nf
> ATH9K_NF_TOO_LOW
) {
29 DPRINTF(ah
->ah_sc
, ATH_DBG_CALIBRATE
,
30 "noise floor value detected (%d) is "
31 "lower than what we think is a "
32 "reasonable value (%d)\n",
33 nf
, ATH9K_NF_TOO_LOW
);
39 static int16_t ath9k_hw_get_nf_hist_mid(int16_t *nfCalBuffer
)
42 int16_t sort
[ATH9K_NF_CAL_HIST_MAX
];
45 for (i
= 0; i
< ATH9K_NF_CAL_HIST_MAX
; i
++)
46 sort
[i
] = nfCalBuffer
[i
];
48 for (i
= 0; i
< ATH9K_NF_CAL_HIST_MAX
- 1; i
++) {
49 for (j
= 1; j
< ATH9K_NF_CAL_HIST_MAX
- i
; j
++) {
50 if (sort
[j
] > sort
[j
- 1]) {
52 sort
[j
] = sort
[j
- 1];
57 nfval
= sort
[(ATH9K_NF_CAL_HIST_MAX
- 1) >> 1];
62 static void ath9k_hw_update_nfcal_hist_buffer(struct ath9k_nfcal_hist
*h
,
67 for (i
= 0; i
< NUM_NF_READINGS
; i
++) {
68 h
[i
].nfCalBuffer
[h
[i
].currIndex
] = nfarray
[i
];
70 if (++h
[i
].currIndex
>= ATH9K_NF_CAL_HIST_MAX
)
73 if (h
[i
].invalidNFcount
> 0) {
74 if (nfarray
[i
] < AR_PHY_CCA_MIN_BAD_VALUE
||
75 nfarray
[i
] > AR_PHY_CCA_MAX_HIGH_VALUE
) {
76 h
[i
].invalidNFcount
= ATH9K_NF_CAL_HIST_MAX
;
78 h
[i
].invalidNFcount
--;
79 h
[i
].privNF
= nfarray
[i
];
83 ath9k_hw_get_nf_hist_mid(h
[i
].nfCalBuffer
);
89 static void ath9k_hw_do_getnf(struct ath_hw
*ah
,
90 int16_t nfarray
[NUM_NF_READINGS
])
94 if (AR_SREV_9280_10_OR_LATER(ah
))
95 nf
= MS(REG_READ(ah
, AR_PHY_CCA
), AR9280_PHY_MINCCA_PWR
);
97 nf
= MS(REG_READ(ah
, AR_PHY_CCA
), AR_PHY_MINCCA_PWR
);
100 nf
= 0 - ((nf
^ 0x1ff) + 1);
101 DPRINTF(ah
->ah_sc
, ATH_DBG_CALIBRATE
,
102 "NF calibrated [ctl] [chain 0] is %d\n", nf
);
105 if (!AR_SREV_9285(ah
)) {
106 if (AR_SREV_9280_10_OR_LATER(ah
))
107 nf
= MS(REG_READ(ah
, AR_PHY_CH1_CCA
),
108 AR9280_PHY_CH1_MINCCA_PWR
);
110 nf
= MS(REG_READ(ah
, AR_PHY_CH1_CCA
),
111 AR_PHY_CH1_MINCCA_PWR
);
114 nf
= 0 - ((nf
^ 0x1ff) + 1);
115 DPRINTF(ah
->ah_sc
, ATH_DBG_CALIBRATE
,
116 "NF calibrated [ctl] [chain 1] is %d\n", nf
);
119 if (!AR_SREV_9280(ah
) && !AR_SREV_9287(ah
)) {
120 nf
= MS(REG_READ(ah
, AR_PHY_CH2_CCA
),
121 AR_PHY_CH2_MINCCA_PWR
);
123 nf
= 0 - ((nf
^ 0x1ff) + 1);
124 DPRINTF(ah
->ah_sc
, ATH_DBG_CALIBRATE
,
125 "NF calibrated [ctl] [chain 2] is %d\n", nf
);
130 if (AR_SREV_9280_10_OR_LATER(ah
))
131 nf
= MS(REG_READ(ah
, AR_PHY_EXT_CCA
),
132 AR9280_PHY_EXT_MINCCA_PWR
);
134 nf
= MS(REG_READ(ah
, AR_PHY_EXT_CCA
),
135 AR_PHY_EXT_MINCCA_PWR
);
138 nf
= 0 - ((nf
^ 0x1ff) + 1);
139 DPRINTF(ah
->ah_sc
, ATH_DBG_CALIBRATE
,
140 "NF calibrated [ext] [chain 0] is %d\n", nf
);
143 if (!AR_SREV_9285(ah
)) {
144 if (AR_SREV_9280_10_OR_LATER(ah
))
145 nf
= MS(REG_READ(ah
, AR_PHY_CH1_EXT_CCA
),
146 AR9280_PHY_CH1_EXT_MINCCA_PWR
);
148 nf
= MS(REG_READ(ah
, AR_PHY_CH1_EXT_CCA
),
149 AR_PHY_CH1_EXT_MINCCA_PWR
);
152 nf
= 0 - ((nf
^ 0x1ff) + 1);
153 DPRINTF(ah
->ah_sc
, ATH_DBG_CALIBRATE
,
154 "NF calibrated [ext] [chain 1] is %d\n", nf
);
157 if (!AR_SREV_9280(ah
) && !AR_SREV_9287(ah
)) {
158 nf
= MS(REG_READ(ah
, AR_PHY_CH2_EXT_CCA
),
159 AR_PHY_CH2_EXT_MINCCA_PWR
);
161 nf
= 0 - ((nf
^ 0x1ff) + 1);
162 DPRINTF(ah
->ah_sc
, ATH_DBG_CALIBRATE
,
163 "NF calibrated [ext] [chain 2] is %d\n", nf
);
169 static bool getNoiseFloorThresh(struct ath_hw
*ah
,
170 enum ieee80211_band band
,
174 case IEEE80211_BAND_5GHZ
:
175 *nft
= (int8_t)ah
->eep_ops
->get_eeprom(ah
, EEP_NFTHRESH_5
);
177 case IEEE80211_BAND_2GHZ
:
178 *nft
= (int8_t)ah
->eep_ops
->get_eeprom(ah
, EEP_NFTHRESH_2
);
188 static void ath9k_hw_setup_calibration(struct ath_hw
*ah
,
189 struct ath9k_cal_list
*currCal
)
191 REG_RMW_FIELD(ah
, AR_PHY_TIMING_CTRL4(0),
192 AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX
,
193 currCal
->calData
->calCountMax
);
195 switch (currCal
->calData
->calType
) {
196 case IQ_MISMATCH_CAL
:
197 REG_WRITE(ah
, AR_PHY_CALMODE
, AR_PHY_CALMODE_IQ
);
198 DPRINTF(ah
->ah_sc
, ATH_DBG_CALIBRATE
,
199 "starting IQ Mismatch Calibration\n");
202 REG_WRITE(ah
, AR_PHY_CALMODE
, AR_PHY_CALMODE_ADC_GAIN
);
203 DPRINTF(ah
->ah_sc
, ATH_DBG_CALIBRATE
,
204 "starting ADC Gain Calibration\n");
207 REG_WRITE(ah
, AR_PHY_CALMODE
, AR_PHY_CALMODE_ADC_DC_PER
);
208 DPRINTF(ah
->ah_sc
, ATH_DBG_CALIBRATE
,
209 "starting ADC DC Calibration\n");
211 case ADC_DC_INIT_CAL
:
212 REG_WRITE(ah
, AR_PHY_CALMODE
, AR_PHY_CALMODE_ADC_DC_INIT
);
213 DPRINTF(ah
->ah_sc
, ATH_DBG_CALIBRATE
,
214 "starting Init ADC DC Calibration\n");
218 REG_SET_BIT(ah
, AR_PHY_TIMING_CTRL4(0),
219 AR_PHY_TIMING_CTRL4_DO_CAL
);
222 static void ath9k_hw_reset_calibration(struct ath_hw
*ah
,
223 struct ath9k_cal_list
*currCal
)
227 ath9k_hw_setup_calibration(ah
, currCal
);
229 currCal
->calState
= CAL_RUNNING
;
231 for (i
= 0; i
< AR5416_MAX_CHAINS
; i
++) {
232 ah
->meas0
.sign
[i
] = 0;
233 ah
->meas1
.sign
[i
] = 0;
234 ah
->meas2
.sign
[i
] = 0;
235 ah
->meas3
.sign
[i
] = 0;
241 static bool ath9k_hw_per_calibration(struct ath_hw
*ah
,
242 struct ath9k_channel
*ichan
,
244 struct ath9k_cal_list
*currCal
)
246 bool iscaldone
= false;
248 if (currCal
->calState
== CAL_RUNNING
) {
249 if (!(REG_READ(ah
, AR_PHY_TIMING_CTRL4(0)) &
250 AR_PHY_TIMING_CTRL4_DO_CAL
)) {
252 currCal
->calData
->calCollect(ah
);
255 if (ah
->cal_samples
>= currCal
->calData
->calNumSamples
) {
256 int i
, numChains
= 0;
257 for (i
= 0; i
< AR5416_MAX_CHAINS
; i
++) {
258 if (rxchainmask
& (1 << i
))
262 currCal
->calData
->calPostProc(ah
, numChains
);
263 ichan
->CalValid
|= currCal
->calData
->calType
;
264 currCal
->calState
= CAL_DONE
;
267 ath9k_hw_setup_calibration(ah
, currCal
);
270 } else if (!(ichan
->CalValid
& currCal
->calData
->calType
)) {
271 ath9k_hw_reset_calibration(ah
, currCal
);
277 /* Assumes you are talking about the currently configured channel */
278 static bool ath9k_hw_iscal_supported(struct ath_hw
*ah
,
279 enum ath9k_cal_types calType
)
281 struct ieee80211_conf
*conf
= &ah
->ah_sc
->hw
->conf
;
283 switch (calType
& ah
->supp_cals
) {
284 case IQ_MISMATCH_CAL
: /* Both 2 GHz and 5 GHz support OFDM */
288 if (!(conf
->channel
->band
== IEEE80211_BAND_2GHZ
&&
296 static void ath9k_hw_iqcal_collect(struct ath_hw
*ah
)
300 for (i
= 0; i
< AR5416_MAX_CHAINS
; i
++) {
301 ah
->totalPowerMeasI
[i
] +=
302 REG_READ(ah
, AR_PHY_CAL_MEAS_0(i
));
303 ah
->totalPowerMeasQ
[i
] +=
304 REG_READ(ah
, AR_PHY_CAL_MEAS_1(i
));
305 ah
->totalIqCorrMeas
[i
] +=
306 (int32_t) REG_READ(ah
, AR_PHY_CAL_MEAS_2(i
));
307 DPRINTF(ah
->ah_sc
, ATH_DBG_CALIBRATE
,
308 "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",
309 ah
->cal_samples
, i
, ah
->totalPowerMeasI
[i
],
310 ah
->totalPowerMeasQ
[i
],
311 ah
->totalIqCorrMeas
[i
]);
315 static void ath9k_hw_adc_gaincal_collect(struct ath_hw
*ah
)
319 for (i
= 0; i
< AR5416_MAX_CHAINS
; i
++) {
320 ah
->totalAdcIOddPhase
[i
] +=
321 REG_READ(ah
, AR_PHY_CAL_MEAS_0(i
));
322 ah
->totalAdcIEvenPhase
[i
] +=
323 REG_READ(ah
, AR_PHY_CAL_MEAS_1(i
));
324 ah
->totalAdcQOddPhase
[i
] +=
325 REG_READ(ah
, AR_PHY_CAL_MEAS_2(i
));
326 ah
->totalAdcQEvenPhase
[i
] +=
327 REG_READ(ah
, AR_PHY_CAL_MEAS_3(i
));
329 DPRINTF(ah
->ah_sc
, ATH_DBG_CALIBRATE
,
330 "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
331 "oddq=0x%08x; evenq=0x%08x;\n",
333 ah
->totalAdcIOddPhase
[i
],
334 ah
->totalAdcIEvenPhase
[i
],
335 ah
->totalAdcQOddPhase
[i
],
336 ah
->totalAdcQEvenPhase
[i
]);
340 static void ath9k_hw_adc_dccal_collect(struct ath_hw
*ah
)
344 for (i
= 0; i
< AR5416_MAX_CHAINS
; i
++) {
345 ah
->totalAdcDcOffsetIOddPhase
[i
] +=
346 (int32_t) REG_READ(ah
, AR_PHY_CAL_MEAS_0(i
));
347 ah
->totalAdcDcOffsetIEvenPhase
[i
] +=
348 (int32_t) REG_READ(ah
, AR_PHY_CAL_MEAS_1(i
));
349 ah
->totalAdcDcOffsetQOddPhase
[i
] +=
350 (int32_t) REG_READ(ah
, AR_PHY_CAL_MEAS_2(i
));
351 ah
->totalAdcDcOffsetQEvenPhase
[i
] +=
352 (int32_t) REG_READ(ah
, AR_PHY_CAL_MEAS_3(i
));
354 DPRINTF(ah
->ah_sc
, ATH_DBG_CALIBRATE
,
355 "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
356 "oddq=0x%08x; evenq=0x%08x;\n",
358 ah
->totalAdcDcOffsetIOddPhase
[i
],
359 ah
->totalAdcDcOffsetIEvenPhase
[i
],
360 ah
->totalAdcDcOffsetQOddPhase
[i
],
361 ah
->totalAdcDcOffsetQEvenPhase
[i
]);
365 static void ath9k_hw_iqcalibrate(struct ath_hw
*ah
, u8 numChains
)
367 u32 powerMeasQ
, powerMeasI
, iqCorrMeas
;
368 u32 qCoffDenom
, iCoffDenom
;
369 int32_t qCoff
, iCoff
;
372 for (i
= 0; i
< numChains
; i
++) {
373 powerMeasI
= ah
->totalPowerMeasI
[i
];
374 powerMeasQ
= ah
->totalPowerMeasQ
[i
];
375 iqCorrMeas
= ah
->totalIqCorrMeas
[i
];
377 DPRINTF(ah
->ah_sc
, ATH_DBG_CALIBRATE
,
378 "Starting IQ Cal and Correction for Chain %d\n",
381 DPRINTF(ah
->ah_sc
, ATH_DBG_CALIBRATE
,
382 "Orignal: Chn %diq_corr_meas = 0x%08x\n",
383 i
, ah
->totalIqCorrMeas
[i
]);
387 if (iqCorrMeas
> 0x80000000) {
388 iqCorrMeas
= (0xffffffff - iqCorrMeas
) + 1;
392 DPRINTF(ah
->ah_sc
, ATH_DBG_CALIBRATE
,
393 "Chn %d pwr_meas_i = 0x%08x\n", i
, powerMeasI
);
394 DPRINTF(ah
->ah_sc
, ATH_DBG_CALIBRATE
,
395 "Chn %d pwr_meas_q = 0x%08x\n", i
, powerMeasQ
);
396 DPRINTF(ah
->ah_sc
, ATH_DBG_CALIBRATE
, "iqCorrNeg is 0x%08x\n",
399 iCoffDenom
= (powerMeasI
/ 2 + powerMeasQ
/ 2) / 128;
400 qCoffDenom
= powerMeasQ
/ 64;
402 if (powerMeasQ
!= 0) {
403 iCoff
= iqCorrMeas
/ iCoffDenom
;
404 qCoff
= powerMeasI
/ qCoffDenom
- 64;
405 DPRINTF(ah
->ah_sc
, ATH_DBG_CALIBRATE
,
406 "Chn %d iCoff = 0x%08x\n", i
, iCoff
);
407 DPRINTF(ah
->ah_sc
, ATH_DBG_CALIBRATE
,
408 "Chn %d qCoff = 0x%08x\n", i
, qCoff
);
410 iCoff
= iCoff
& 0x3f;
411 DPRINTF(ah
->ah_sc
, ATH_DBG_CALIBRATE
,
412 "New: Chn %d iCoff = 0x%08x\n", i
, iCoff
);
413 if (iqCorrNeg
== 0x0)
414 iCoff
= 0x40 - iCoff
;
418 else if (qCoff
<= -16)
421 DPRINTF(ah
->ah_sc
, ATH_DBG_CALIBRATE
,
422 "Chn %d : iCoff = 0x%x qCoff = 0x%x\n",
425 REG_RMW_FIELD(ah
, AR_PHY_TIMING_CTRL4(i
),
426 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF
,
428 REG_RMW_FIELD(ah
, AR_PHY_TIMING_CTRL4(i
),
429 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF
,
431 DPRINTF(ah
->ah_sc
, ATH_DBG_CALIBRATE
,
432 "IQ Cal and Correction done for Chain %d\n",
437 REG_SET_BIT(ah
, AR_PHY_TIMING_CTRL4(0),
438 AR_PHY_TIMING_CTRL4_IQCORR_ENABLE
);
441 static void ath9k_hw_adc_gaincal_calibrate(struct ath_hw
*ah
, u8 numChains
)
443 u32 iOddMeasOffset
, iEvenMeasOffset
, qOddMeasOffset
, qEvenMeasOffset
;
444 u32 qGainMismatch
, iGainMismatch
, val
, i
;
446 for (i
= 0; i
< numChains
; i
++) {
447 iOddMeasOffset
= ah
->totalAdcIOddPhase
[i
];
448 iEvenMeasOffset
= ah
->totalAdcIEvenPhase
[i
];
449 qOddMeasOffset
= ah
->totalAdcQOddPhase
[i
];
450 qEvenMeasOffset
= ah
->totalAdcQEvenPhase
[i
];
452 DPRINTF(ah
->ah_sc
, ATH_DBG_CALIBRATE
,
453 "Starting ADC Gain Cal for Chain %d\n", i
);
455 DPRINTF(ah
->ah_sc
, ATH_DBG_CALIBRATE
,
456 "Chn %d pwr_meas_odd_i = 0x%08x\n", i
,
458 DPRINTF(ah
->ah_sc
, ATH_DBG_CALIBRATE
,
459 "Chn %d pwr_meas_even_i = 0x%08x\n", i
,
461 DPRINTF(ah
->ah_sc
, ATH_DBG_CALIBRATE
,
462 "Chn %d pwr_meas_odd_q = 0x%08x\n", i
,
464 DPRINTF(ah
->ah_sc
, ATH_DBG_CALIBRATE
,
465 "Chn %d pwr_meas_even_q = 0x%08x\n", i
,
468 if (iOddMeasOffset
!= 0 && qEvenMeasOffset
!= 0) {
470 ((iEvenMeasOffset
* 32) /
471 iOddMeasOffset
) & 0x3f;
473 ((qOddMeasOffset
* 32) /
474 qEvenMeasOffset
) & 0x3f;
476 DPRINTF(ah
->ah_sc
, ATH_DBG_CALIBRATE
,
477 "Chn %d gain_mismatch_i = 0x%08x\n", i
,
479 DPRINTF(ah
->ah_sc
, ATH_DBG_CALIBRATE
,
480 "Chn %d gain_mismatch_q = 0x%08x\n", i
,
483 val
= REG_READ(ah
, AR_PHY_NEW_ADC_DC_GAIN_CORR(i
));
485 val
|= (qGainMismatch
) | (iGainMismatch
<< 6);
486 REG_WRITE(ah
, AR_PHY_NEW_ADC_DC_GAIN_CORR(i
), val
);
488 DPRINTF(ah
->ah_sc
, ATH_DBG_CALIBRATE
,
489 "ADC Gain Cal done for Chain %d\n", i
);
493 REG_WRITE(ah
, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
494 REG_READ(ah
, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |
495 AR_PHY_NEW_ADC_GAIN_CORR_ENABLE
);
498 static void ath9k_hw_adc_dccal_calibrate(struct ath_hw
*ah
, u8 numChains
)
500 u32 iOddMeasOffset
, iEvenMeasOffset
, val
, i
;
501 int32_t qOddMeasOffset
, qEvenMeasOffset
, qDcMismatch
, iDcMismatch
;
502 const struct ath9k_percal_data
*calData
=
503 ah
->cal_list_curr
->calData
;
505 (1 << (calData
->calCountMax
+ 5)) * calData
->calNumSamples
;
507 for (i
= 0; i
< numChains
; i
++) {
508 iOddMeasOffset
= ah
->totalAdcDcOffsetIOddPhase
[i
];
509 iEvenMeasOffset
= ah
->totalAdcDcOffsetIEvenPhase
[i
];
510 qOddMeasOffset
= ah
->totalAdcDcOffsetQOddPhase
[i
];
511 qEvenMeasOffset
= ah
->totalAdcDcOffsetQEvenPhase
[i
];
513 DPRINTF(ah
->ah_sc
, ATH_DBG_CALIBRATE
,
514 "Starting ADC DC Offset Cal for Chain %d\n", i
);
516 DPRINTF(ah
->ah_sc
, ATH_DBG_CALIBRATE
,
517 "Chn %d pwr_meas_odd_i = %d\n", i
,
519 DPRINTF(ah
->ah_sc
, ATH_DBG_CALIBRATE
,
520 "Chn %d pwr_meas_even_i = %d\n", i
,
522 DPRINTF(ah
->ah_sc
, ATH_DBG_CALIBRATE
,
523 "Chn %d pwr_meas_odd_q = %d\n", i
,
525 DPRINTF(ah
->ah_sc
, ATH_DBG_CALIBRATE
,
526 "Chn %d pwr_meas_even_q = %d\n", i
,
529 iDcMismatch
= (((iEvenMeasOffset
- iOddMeasOffset
) * 2) /
531 qDcMismatch
= (((qOddMeasOffset
- qEvenMeasOffset
) * 2) /
534 DPRINTF(ah
->ah_sc
, ATH_DBG_CALIBRATE
,
535 "Chn %d dc_offset_mismatch_i = 0x%08x\n", i
,
537 DPRINTF(ah
->ah_sc
, ATH_DBG_CALIBRATE
,
538 "Chn %d dc_offset_mismatch_q = 0x%08x\n", i
,
541 val
= REG_READ(ah
, AR_PHY_NEW_ADC_DC_GAIN_CORR(i
));
543 val
|= (qDcMismatch
<< 12) | (iDcMismatch
<< 21);
544 REG_WRITE(ah
, AR_PHY_NEW_ADC_DC_GAIN_CORR(i
), val
);
546 DPRINTF(ah
->ah_sc
, ATH_DBG_CALIBRATE
,
547 "ADC DC Offset Cal done for Chain %d\n", i
);
550 REG_WRITE(ah
, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
551 REG_READ(ah
, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |
552 AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE
);
555 /* This is done for the currently configured channel */
556 bool ath9k_hw_reset_calvalid(struct ath_hw
*ah
)
558 struct ieee80211_conf
*conf
= &ah
->ah_sc
->hw
->conf
;
559 struct ath9k_cal_list
*currCal
= ah
->cal_list_curr
;
564 if (!AR_SREV_9100(ah
) && !AR_SREV_9160_10_OR_LATER(ah
))
570 if (currCal
->calState
!= CAL_DONE
) {
571 DPRINTF(ah
->ah_sc
, ATH_DBG_CALIBRATE
,
572 "Calibration state incorrect, %d\n",
577 if (!ath9k_hw_iscal_supported(ah
, currCal
->calData
->calType
))
580 DPRINTF(ah
->ah_sc
, ATH_DBG_CALIBRATE
,
581 "Resetting Cal %d state for channel %u\n",
582 currCal
->calData
->calType
, conf
->channel
->center_freq
);
584 ah
->curchan
->CalValid
&= ~currCal
->calData
->calType
;
585 currCal
->calState
= CAL_WAITING
;
590 void ath9k_hw_start_nfcal(struct ath_hw
*ah
)
592 REG_SET_BIT(ah
, AR_PHY_AGC_CONTROL
,
593 AR_PHY_AGC_CONTROL_ENABLE_NF
);
594 REG_SET_BIT(ah
, AR_PHY_AGC_CONTROL
,
595 AR_PHY_AGC_CONTROL_NO_UPDATE_NF
);
596 REG_SET_BIT(ah
, AR_PHY_AGC_CONTROL
, AR_PHY_AGC_CONTROL_NF
);
599 void ath9k_hw_loadnf(struct ath_hw
*ah
, struct ath9k_channel
*chan
)
601 struct ath9k_nfcal_hist
*h
;
604 const u32 ar5416_cca_regs
[6] = {
614 if (AR_SREV_9285(ah
))
616 else if (AR_SREV_9280(ah
) || AR_SREV_9287(ah
))
623 for (i
= 0; i
< NUM_NF_READINGS
; i
++) {
624 if (chainmask
& (1 << i
)) {
625 val
= REG_READ(ah
, ar5416_cca_regs
[i
]);
627 val
|= (((u32
) (h
[i
].privNF
) << 1) & 0x1ff);
628 REG_WRITE(ah
, ar5416_cca_regs
[i
], val
);
632 REG_CLR_BIT(ah
, AR_PHY_AGC_CONTROL
,
633 AR_PHY_AGC_CONTROL_ENABLE_NF
);
634 REG_CLR_BIT(ah
, AR_PHY_AGC_CONTROL
,
635 AR_PHY_AGC_CONTROL_NO_UPDATE_NF
);
636 REG_SET_BIT(ah
, AR_PHY_AGC_CONTROL
, AR_PHY_AGC_CONTROL_NF
);
638 for (j
= 0; j
< 1000; j
++) {
639 if ((REG_READ(ah
, AR_PHY_AGC_CONTROL
) &
640 AR_PHY_AGC_CONTROL_NF
) == 0)
645 for (i
= 0; i
< NUM_NF_READINGS
; i
++) {
646 if (chainmask
& (1 << i
)) {
647 val
= REG_READ(ah
, ar5416_cca_regs
[i
]);
649 val
|= (((u32
) (-50) << 1) & 0x1ff);
650 REG_WRITE(ah
, ar5416_cca_regs
[i
], val
);
655 int16_t ath9k_hw_getnf(struct ath_hw
*ah
,
656 struct ath9k_channel
*chan
)
658 int16_t nf
, nfThresh
;
659 int16_t nfarray
[NUM_NF_READINGS
] = { 0 };
660 struct ath9k_nfcal_hist
*h
;
661 struct ieee80211_channel
*c
= chan
->chan
;
663 chan
->channelFlags
&= (~CHANNEL_CW_INT
);
664 if (REG_READ(ah
, AR_PHY_AGC_CONTROL
) & AR_PHY_AGC_CONTROL_NF
) {
665 DPRINTF(ah
->ah_sc
, ATH_DBG_CALIBRATE
,
666 "NF did not complete in calibration window\n");
668 chan
->rawNoiseFloor
= nf
;
669 return chan
->rawNoiseFloor
;
671 ath9k_hw_do_getnf(ah
, nfarray
);
673 if (getNoiseFloorThresh(ah
, c
->band
, &nfThresh
)
675 DPRINTF(ah
->ah_sc
, ATH_DBG_CALIBRATE
,
676 "noise floor failed detected; "
677 "detected %d, threshold %d\n",
679 chan
->channelFlags
|= CHANNEL_CW_INT
;
685 ath9k_hw_update_nfcal_hist_buffer(h
, nfarray
);
686 chan
->rawNoiseFloor
= h
[0].privNF
;
688 return chan
->rawNoiseFloor
;
691 void ath9k_init_nfcal_hist_buffer(struct ath_hw
*ah
)
696 if (AR_SREV_9280(ah
))
697 noise_floor
= AR_PHY_CCA_MAX_AR9280_GOOD_VALUE
;
698 else if (AR_SREV_9285(ah
))
699 noise_floor
= AR_PHY_CCA_MAX_AR9285_GOOD_VALUE
;
701 noise_floor
= AR_PHY_CCA_MAX_AR5416_GOOD_VALUE
;
703 for (i
= 0; i
< NUM_NF_READINGS
; i
++) {
704 ah
->nfCalHist
[i
].currIndex
= 0;
705 ah
->nfCalHist
[i
].privNF
= noise_floor
;
706 ah
->nfCalHist
[i
].invalidNFcount
=
707 AR_PHY_CCA_FILTERWINDOW_LENGTH
;
708 for (j
= 0; j
< ATH9K_NF_CAL_HIST_MAX
; j
++) {
709 ah
->nfCalHist
[i
].nfCalBuffer
[j
] = noise_floor
;
714 s16
ath9k_hw_getchan_noise(struct ath_hw
*ah
, struct ath9k_channel
*chan
)
718 if (chan
->rawNoiseFloor
== 0)
721 nf
= chan
->rawNoiseFloor
;
723 if (!ath9k_hw_nf_in_range(ah
, nf
))
724 nf
= ATH_DEFAULT_NOISE_FLOOR
;
729 static void ath9k_olc_temp_compensation(struct ath_hw
*ah
)
732 int delta
, currPDADC
, regval
;
734 rddata
= REG_READ(ah
, AR_PHY_TX_PWRCTRL4
);
736 currPDADC
= MS(rddata
, AR_PHY_TX_PWRCTRL_PD_AVG_OUT
);
738 if (ah
->eep_ops
->get_eeprom(ah
, EEP_DAC_HPWR_5G
))
739 delta
= (currPDADC
- ah
->initPDADC
+ 4) / 8;
741 delta
= (currPDADC
- ah
->initPDADC
+ 5) / 10;
743 if (delta
!= ah
->PDADCdelta
) {
744 ah
->PDADCdelta
= delta
;
745 for (i
= 1; i
< AR9280_TX_GAIN_TABLE_SIZE
; i
++) {
746 regval
= ah
->originalGain
[i
] - delta
;
750 REG_RMW_FIELD(ah
, AR_PHY_TX_GAIN_TBL1
+ i
* 4,
751 AR_PHY_TX_GAIN
, regval
);
756 static inline void ath9k_hw_9285_pa_cal(struct ath_hw
*ah
)
760 int i
, offset
, offs_6_1
, offs_0
;
761 u32 ccomp_org
, reg_field
;
772 if (AR_SREV_9285_11(ah
)) {
773 REG_WRITE(ah
, AR9285_AN_TOP4
, (AR9285_AN_TOP4_DEFAULT
| 0x14));
777 for (i
= 0; i
< ARRAY_SIZE(regList
); i
++)
778 regList
[i
][1] = REG_READ(ah
, regList
[i
][0]);
780 regVal
= REG_READ(ah
, 0x7834);
782 REG_WRITE(ah
, 0x7834, regVal
);
783 regVal
= REG_READ(ah
, 0x9808);
784 regVal
|= (0x1 << 27);
785 REG_WRITE(ah
, 0x9808, regVal
);
787 REG_RMW_FIELD(ah
, AR9285_AN_TOP3
, AR9285_AN_TOP3_PWDDAC
, 1);
788 REG_RMW_FIELD(ah
, AR9285_AN_RXTXBB1
, AR9285_AN_RXTXBB1_PDRXTXBB1
, 1);
789 REG_RMW_FIELD(ah
, AR9285_AN_RXTXBB1
, AR9285_AN_RXTXBB1_PDV2I
, 1);
790 REG_RMW_FIELD(ah
, AR9285_AN_RXTXBB1
, AR9285_AN_RXTXBB1_PDDACIF
, 1);
791 REG_RMW_FIELD(ah
, AR9285_AN_RF2G2
, AR9285_AN_RF2G2_OFFCAL
, 0);
792 REG_RMW_FIELD(ah
, AR9285_AN_RF2G7
, AR9285_AN_RF2G7_PWDDB
, 0);
793 REG_RMW_FIELD(ah
, AR9285_AN_RF2G1
, AR9285_AN_RF2G1_ENPACAL
, 0);
794 REG_RMW_FIELD(ah
, AR9285_AN_RF2G1
, AR9285_AN_RF2G1_PDPADRV1
, 1);
795 REG_RMW_FIELD(ah
, AR9285_AN_RF2G1
, AR9285_AN_RF2G1_PDPADRV2
, 0);
796 REG_RMW_FIELD(ah
, AR9285_AN_RF2G1
, AR9285_AN_RF2G1_PDPAOUT
, 0);
797 REG_RMW_FIELD(ah
, AR9285_AN_RF2G8
, AR9285_AN_RF2G8_PADRVGN2TAB0
, 7);
798 REG_RMW_FIELD(ah
, AR9285_AN_RF2G7
, AR9285_AN_RF2G7_PADRVGN2TAB0
, 0);
799 ccomp_org
= MS(REG_READ(ah
, AR9285_AN_RF2G6
), AR9285_AN_RF2G6_CCOMP
);
800 REG_RMW_FIELD(ah
, AR9285_AN_RF2G6
, AR9285_AN_RF2G6_CCOMP
, 7);
802 REG_WRITE(ah
, AR9285_AN_TOP2
, 0xca0358a0);
804 REG_RMW_FIELD(ah
, AR9285_AN_RF2G6
, AR9285_AN_RF2G6_OFFS
, 0);
805 REG_RMW_FIELD(ah
, AR9285_AN_RF2G3
, AR9285_AN_RF2G3_PDVCCOMP
, 0);
807 for (i
= 6; i
> 0; i
--) {
808 regVal
= REG_READ(ah
, 0x7834);
809 regVal
|= (1 << (19 + i
));
810 REG_WRITE(ah
, 0x7834, regVal
);
812 regVal
= REG_READ(ah
, 0x7834);
813 regVal
&= (~(0x1 << (19 + i
)));
814 reg_field
= MS(REG_READ(ah
, 0x7840), AR9285_AN_RXTXBB1_SPARE9
);
815 regVal
|= (reg_field
<< (19 + i
));
816 REG_WRITE(ah
, 0x7834, regVal
);
819 REG_RMW_FIELD(ah
, AR9285_AN_RF2G3
, AR9285_AN_RF2G3_PDVCCOMP
, 1);
821 reg_field
= MS(REG_READ(ah
, AR9285_AN_RF2G9
), AR9285_AN_RXTXBB1_SPARE9
);
822 REG_RMW_FIELD(ah
, AR9285_AN_RF2G3
, AR9285_AN_RF2G3_PDVCCOMP
, reg_field
);
823 offs_6_1
= MS(REG_READ(ah
, AR9285_AN_RF2G6
), AR9285_AN_RF2G6_OFFS
);
824 offs_0
= MS(REG_READ(ah
, AR9285_AN_RF2G3
), AR9285_AN_RF2G3_PDVCCOMP
);
826 offset
= (offs_6_1
<<1) | offs_0
;
828 offs_6_1
= offset
>>1;
831 REG_RMW_FIELD(ah
, AR9285_AN_RF2G6
, AR9285_AN_RF2G6_OFFS
, offs_6_1
);
832 REG_RMW_FIELD(ah
, AR9285_AN_RF2G3
, AR9285_AN_RF2G3_PDVCCOMP
, offs_0
);
834 regVal
= REG_READ(ah
, 0x7834);
836 REG_WRITE(ah
, 0x7834, regVal
);
837 regVal
= REG_READ(ah
, 0x9808);
838 regVal
&= (~(0x1 << 27));
839 REG_WRITE(ah
, 0x9808, regVal
);
841 for (i
= 0; i
< ARRAY_SIZE(regList
); i
++)
842 REG_WRITE(ah
, regList
[i
][0], regList
[i
][1]);
844 REG_RMW_FIELD(ah
, AR9285_AN_RF2G6
, AR9285_AN_RF2G6_CCOMP
, ccomp_org
);
846 if (AR_SREV_9285_11(ah
))
847 REG_WRITE(ah
, AR9285_AN_TOP4
, AR9285_AN_TOP4_DEFAULT
);
851 bool ath9k_hw_calibrate(struct ath_hw
*ah
, struct ath9k_channel
*chan
,
852 u8 rxchainmask
, bool longcal
)
854 bool iscaldone
= true;
855 struct ath9k_cal_list
*currCal
= ah
->cal_list_curr
;
858 (currCal
->calState
== CAL_RUNNING
||
859 currCal
->calState
== CAL_WAITING
)) {
860 iscaldone
= ath9k_hw_per_calibration(ah
, chan
,
861 rxchainmask
, currCal
);
863 ah
->cal_list_curr
= currCal
= currCal
->calNext
;
865 if (currCal
->calState
== CAL_WAITING
) {
867 ath9k_hw_reset_calibration(ah
, currCal
);
873 if (AR_SREV_9285_11_OR_LATER(ah
))
874 ath9k_hw_9285_pa_cal(ah
);
876 if (OLC_FOR_AR9280_20_LATER
|| OLC_FOR_AR9287_10_LATER
)
877 ath9k_olc_temp_compensation(ah
);
878 ath9k_hw_getnf(ah
, chan
);
879 ath9k_hw_loadnf(ah
, ah
->curchan
);
880 ath9k_hw_start_nfcal(ah
);
886 static bool ar9285_clc(struct ath_hw
*ah
, struct ath9k_channel
*chan
)
888 REG_SET_BIT(ah
, AR_PHY_CL_CAL_CTL
, AR_PHY_CL_CAL_ENABLE
);
889 if (IS_CHAN_HT20(chan
)) {
890 REG_SET_BIT(ah
, AR_PHY_CL_CAL_CTL
, AR_PHY_PARALLEL_CAL_ENABLE
);
891 REG_SET_BIT(ah
, AR_PHY_TURBO
, AR_PHY_FC_DYN2040_EN
);
892 REG_CLR_BIT(ah
, AR_PHY_AGC_CONTROL
,
893 AR_PHY_AGC_CONTROL_FLTR_CAL
);
894 REG_CLR_BIT(ah
, AR_PHY_TPCRG1
, AR_PHY_TPCRG1_PD_CAL_ENABLE
);
895 REG_SET_BIT(ah
, AR_PHY_AGC_CONTROL
, AR_PHY_AGC_CONTROL_CAL
);
896 if (!ath9k_hw_wait(ah
, AR_PHY_AGC_CONTROL
,
897 AR_PHY_AGC_CONTROL_CAL
, 0, AH_WAIT_TIMEOUT
)) {
898 DPRINTF(ah
->ah_sc
, ATH_DBG_CALIBRATE
, "offset "
899 "calibration failed to complete in "
903 REG_CLR_BIT(ah
, AR_PHY_TURBO
, AR_PHY_FC_DYN2040_EN
);
904 REG_CLR_BIT(ah
, AR_PHY_CL_CAL_CTL
, AR_PHY_PARALLEL_CAL_ENABLE
);
905 REG_CLR_BIT(ah
, AR_PHY_CL_CAL_CTL
, AR_PHY_CL_CAL_ENABLE
);
907 REG_CLR_BIT(ah
, AR_PHY_ADC_CTL
, AR_PHY_ADC_CTL_OFF_PWDADC
);
908 REG_SET_BIT(ah
, AR_PHY_AGC_CONTROL
, AR_PHY_AGC_CONTROL_FLTR_CAL
);
909 REG_SET_BIT(ah
, AR_PHY_TPCRG1
, AR_PHY_TPCRG1_PD_CAL_ENABLE
);
910 REG_SET_BIT(ah
, AR_PHY_AGC_CONTROL
, AR_PHY_AGC_CONTROL_CAL
);
911 if (!ath9k_hw_wait(ah
, AR_PHY_AGC_CONTROL
, AR_PHY_AGC_CONTROL_CAL
,
912 0, AH_WAIT_TIMEOUT
)) {
913 DPRINTF(ah
->ah_sc
, ATH_DBG_CALIBRATE
, "offset calibration "
914 "failed to complete in 1ms; noisy ??\n");
918 REG_SET_BIT(ah
, AR_PHY_ADC_CTL
, AR_PHY_ADC_CTL_OFF_PWDADC
);
919 REG_CLR_BIT(ah
, AR_PHY_CL_CAL_CTL
, AR_PHY_CL_CAL_ENABLE
);
920 REG_CLR_BIT(ah
, AR_PHY_AGC_CONTROL
, AR_PHY_AGC_CONTROL_FLTR_CAL
);
925 bool ath9k_hw_init_cal(struct ath_hw
*ah
, struct ath9k_channel
*chan
)
927 if (AR_SREV_9285_12_OR_LATER(ah
)) {
928 if (!ar9285_clc(ah
, chan
))
931 if (AR_SREV_9280_10_OR_LATER(ah
)) {
932 if (!AR_SREV_9287_10_OR_LATER(ah
))
933 REG_CLR_BIT(ah
, AR_PHY_ADC_CTL
,
934 AR_PHY_ADC_CTL_OFF_PWDADC
);
935 REG_SET_BIT(ah
, AR_PHY_AGC_CONTROL
,
936 AR_PHY_AGC_CONTROL_FLTR_CAL
);
939 /* Calibrate the AGC */
940 REG_WRITE(ah
, AR_PHY_AGC_CONTROL
,
941 REG_READ(ah
, AR_PHY_AGC_CONTROL
) |
942 AR_PHY_AGC_CONTROL_CAL
);
944 /* Poll for offset calibration complete */
945 if (!ath9k_hw_wait(ah
, AR_PHY_AGC_CONTROL
, AR_PHY_AGC_CONTROL_CAL
,
946 0, AH_WAIT_TIMEOUT
)) {
947 DPRINTF(ah
->ah_sc
, ATH_DBG_CALIBRATE
,
948 "offset calibration failed to complete in 1ms; "
949 "noisy environment?\n");
953 if (AR_SREV_9280_10_OR_LATER(ah
)) {
954 if (!AR_SREV_9287_10_OR_LATER(ah
))
955 REG_SET_BIT(ah
, AR_PHY_ADC_CTL
,
956 AR_PHY_ADC_CTL_OFF_PWDADC
);
957 REG_CLR_BIT(ah
, AR_PHY_AGC_CONTROL
,
958 AR_PHY_AGC_CONTROL_FLTR_CAL
);
962 /* Do PA Calibration */
963 if (AR_SREV_9285_11_OR_LATER(ah
))
964 ath9k_hw_9285_pa_cal(ah
);
966 /* Do NF Calibration after DC offset and other calibrations */
967 REG_WRITE(ah
, AR_PHY_AGC_CONTROL
,
968 REG_READ(ah
, AR_PHY_AGC_CONTROL
) | AR_PHY_AGC_CONTROL_NF
);
970 ah
->cal_list
= ah
->cal_list_last
= ah
->cal_list_curr
= NULL
;
972 /* Enable IQ, ADC Gain and ADC DC offset CALs */
973 if (AR_SREV_9100(ah
) || AR_SREV_9160_10_OR_LATER(ah
)) {
974 if (ath9k_hw_iscal_supported(ah
, ADC_GAIN_CAL
)) {
975 INIT_CAL(&ah
->adcgain_caldata
);
976 INSERT_CAL(ah
, &ah
->adcgain_caldata
);
977 DPRINTF(ah
->ah_sc
, ATH_DBG_CALIBRATE
,
978 "enabling ADC Gain Calibration.\n");
980 if (ath9k_hw_iscal_supported(ah
, ADC_DC_CAL
)) {
981 INIT_CAL(&ah
->adcdc_caldata
);
982 INSERT_CAL(ah
, &ah
->adcdc_caldata
);
983 DPRINTF(ah
->ah_sc
, ATH_DBG_CALIBRATE
,
984 "enabling ADC DC Calibration.\n");
986 if (ath9k_hw_iscal_supported(ah
, IQ_MISMATCH_CAL
)) {
987 INIT_CAL(&ah
->iq_caldata
);
988 INSERT_CAL(ah
, &ah
->iq_caldata
);
989 DPRINTF(ah
->ah_sc
, ATH_DBG_CALIBRATE
,
990 "enabling IQ Calibration.\n");
993 ah
->cal_list_curr
= ah
->cal_list
;
995 if (ah
->cal_list_curr
)
996 ath9k_hw_reset_calibration(ah
, ah
->cal_list_curr
);
1004 const struct ath9k_percal_data iq_cal_multi_sample
= {
1008 ath9k_hw_iqcal_collect
,
1009 ath9k_hw_iqcalibrate
1011 const struct ath9k_percal_data iq_cal_single_sample
= {
1015 ath9k_hw_iqcal_collect
,
1016 ath9k_hw_iqcalibrate
1018 const struct ath9k_percal_data adc_gain_cal_multi_sample
= {
1022 ath9k_hw_adc_gaincal_collect
,
1023 ath9k_hw_adc_gaincal_calibrate
1025 const struct ath9k_percal_data adc_gain_cal_single_sample
= {
1029 ath9k_hw_adc_gaincal_collect
,
1030 ath9k_hw_adc_gaincal_calibrate
1032 const struct ath9k_percal_data adc_dc_cal_multi_sample
= {
1036 ath9k_hw_adc_dccal_collect
,
1037 ath9k_hw_adc_dccal_calibrate
1039 const struct ath9k_percal_data adc_dc_cal_single_sample
= {
1043 ath9k_hw_adc_dccal_collect
,
1044 ath9k_hw_adc_dccal_calibrate
1046 const struct ath9k_percal_data adc_init_dc_cal
= {
1050 ath9k_hw_adc_dccal_collect
,
1051 ath9k_hw_adc_dccal_calibrate