drivers/net/wireless/ath/ath9k/debug.h

   1 /*
   2  * Copyright (c) 2008-2011 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #ifndef DEBUG_H
  18 #define DEBUG_H
  19
  20 #include "hw.h"
  21 #include "rc.h"
  22 #include "dfs_debug.h"
  23
  24 struct ath_txq;
  25 struct ath_buf;
  26
  27 #ifdef CONFIG_ATH9K_DEBUGFS
  28 #define TX_STAT_INC(q, c) sc->debug.stats.txstats[q].c++
  29 #define RESET_STAT_INC(sc, type) sc->debug.stats.reset[type]++
  30 #else
  31 #define TX_STAT_INC(q, c) do { } while (0)
  32 #define RESET_STAT_INC(sc, type) do { } while (0)
  33 #endif
  34
  35 #ifdef CONFIG_ATH9K_DEBUGFS
  36
  37 /**
  38  * struct ath_interrupt_stats - Contains statistics about interrupts
  39  * @total: Total no. of interrupts generated so far
  40  * @rxok: RX with no errors
  41  * @rxlp: RX with low priority RX
  42  * @rxhp: RX with high priority, uapsd only
  43  * @rxeol: RX with no more RXDESC available
  44  * @rxorn: RX FIFO overrun
  45  * @txok: TX completed at the requested rate
  46  * @txurn: TX FIFO underrun
  47  * @mib: MIB regs reaching its threshold
  48  * @rxphyerr: RX with phy errors
  49  * @rx_keycache_miss: RX with key cache misses
  50  * @swba: Software Beacon Alert
  51  * @bmiss: Beacon Miss
  52  * @bnr: Beacon Not Ready
  53  * @cst: Carrier Sense TImeout
  54  * @gtt: Global TX Timeout
  55  * @tim: RX beacon TIM occurrence
  56  * @cabend: RX End of CAB traffic
  57  * @dtimsync: DTIM sync lossage
  58  * @dtim: RX Beacon with DTIM
  59  * @bb_watchdog: Baseband watchdog
  60  * @tsfoor: TSF out of range, indicates that the corrected TSF received
  61  * from a beacon differs from the PCU's internal TSF by more than a
  62  * (programmable) threshold
  63  * @local_timeout: Internal bus timeout.
  64  */
  65 struct ath_interrupt_stats {
  66         u32 total;
  67         u32 rxok;
  68         u32 rxlp;
  69         u32 rxhp;
  70         u32 rxeol;
  71         u32 rxorn;
  72         u32 txok;
  73         u32 txeol;
  74         u32 txurn;
  75         u32 mib;
  76         u32 rxphyerr;
  77         u32 rx_keycache_miss;
  78         u32 swba;
  79         u32 bmiss;
  80         u32 bnr;
  81         u32 cst;
  82         u32 gtt;
  83         u32 tim;
  84         u32 cabend;
  85         u32 dtimsync;
  86         u32 dtim;
  87         u32 bb_watchdog;
  88         u32 tsfoor;
  89
  90         /* Sync-cause stats */
  91         u32 sync_cause_all;
  92         u32 sync_rtc_irq;
  93         u32 sync_mac_irq;
  94         u32 eeprom_illegal_access;
  95         u32 apb_timeout;
  96         u32 pci_mode_conflict;
  97         u32 host1_fatal;
  98         u32 host1_perr;
  99         u32 trcv_fifo_perr;
 100         u32 radm_cpl_ep;
 101         u32 radm_cpl_dllp_abort;
 102         u32 radm_cpl_tlp_abort;
 103         u32 radm_cpl_ecrc_err;
 104         u32 radm_cpl_timeout;
 105         u32 local_timeout;
 106         u32 pm_access;
 107         u32 mac_awake;
 108         u32 mac_asleep;
 109         u32 mac_sleep_access;
 110 };
 111
 112
 113 /**
 114  * struct ath_tx_stats - Statistics about TX
 115  * @tx_pkts_all:  No. of total frames transmitted, including ones that
 116         may have had errors.
 117  * @tx_bytes_all:  No. of total bytes transmitted, including ones that
 118         may have had errors.
 119  * @queued: Total MPDUs (non-aggr) queued
 120  * @completed: Total MPDUs (non-aggr) completed
 121  * @a_aggr: Total no. of aggregates queued
 122  * @a_queued_hw: Total AMPDUs queued to hardware
 123  * @a_queued_sw: Total AMPDUs queued to software queues
 124  * @a_completed: Total AMPDUs completed
 125  * @a_retries: No. of AMPDUs retried (SW)
 126  * @a_xretries: No. of AMPDUs dropped due to xretries
 127  * @fifo_underrun: FIFO underrun occurrences
 128         Valid only for:
 129                 - non-aggregate condition.
 130                 - first packet of aggregate.
 131  * @xtxop: No. of frames filtered because of TXOP limit
 132  * @timer_exp: Transmit timer expiry
 133  * @desc_cfg_err: Descriptor configuration errors
 134  * @data_urn: TX data underrun errors
 135  * @delim_urn: TX delimiter underrun errors
 136  * @puttxbuf: Number of times hardware was given txbuf to write.
 137  * @txstart:  Number of times hardware was told to start tx.
 138  * @txprocdesc:  Number of times tx descriptor was processed
 139  * @txfailed:  Out-of-memory or other errors in xmit path.
 140  */
 141 struct ath_tx_stats {
 142         u32 tx_pkts_all;
 143         u32 tx_bytes_all;
 144         u32 queued;
 145         u32 completed;
 146         u32 xretries;
 147         u32 a_aggr;
 148         u32 a_queued_hw;
 149         u32 a_queued_sw;
 150         u32 a_completed;
 151         u32 a_retries;
 152         u32 a_xretries;
 153         u32 fifo_underrun;
 154         u32 xtxop;
 155         u32 timer_exp;
 156         u32 desc_cfg_err;
 157         u32 data_underrun;
 158         u32 delim_underrun;
 159         u32 puttxbuf;
 160         u32 txstart;
 161         u32 txprocdesc;
 162         u32 txfailed;
 163 };
 164
 165 #define RX_STAT_INC(c) (sc->debug.stats.rxstats.c++)
 166
 167 /**
 168  * struct ath_rx_stats - RX Statistics
 169  * @rx_pkts_all:  No. of total frames received, including ones that
 170         may have had errors.
 171  * @rx_bytes_all:  No. of total bytes received, including ones that
 172         may have had errors.
 173  * @crc_err: No. of frames with incorrect CRC value
 174  * @decrypt_crc_err: No. of frames whose CRC check failed after
 175         decryption process completed
 176  * @phy_err: No. of frames whose reception failed because the PHY
 177         encountered an error
 178  * @mic_err: No. of frames with incorrect TKIP MIC verification failure
 179  * @pre_delim_crc_err: Pre-Frame delimiter CRC error detections
 180  * @post_delim_crc_err: Post-Frame delimiter CRC error detections
 181  * @decrypt_busy_err: Decryption interruptions counter
 182  * @phy_err_stats: Individual PHY error statistics
 183  * @rx_len_err:  No. of frames discarded due to bad length.
 184  * @rx_oom_err:  No. of frames dropped due to OOM issues.
 185  * @rx_rate_err:  No. of frames dropped due to rate errors.
 186  * @rx_too_many_frags_err:  Frames dropped due to too-many-frags received.
 187  * @rx_drop_rxflush: No. of frames dropped due to RX-FLUSH.
 188  * @rx_beacons:  No. of beacons received.
 189  * @rx_frags:  No. of rx-fragements received.
 190  */
 191 struct ath_rx_stats {
 192         u32 rx_pkts_all;
 193         u32 rx_bytes_all;
 194         u32 crc_err;
 195         u32 decrypt_crc_err;
 196         u32 phy_err;
 197         u32 mic_err;
 198         u32 pre_delim_crc_err;
 199         u32 post_delim_crc_err;
 200         u32 decrypt_busy_err;
 201         u32 phy_err_stats[ATH9K_PHYERR_MAX];
 202         u32 rx_len_err;
 203         u32 rx_oom_err;
 204         u32 rx_rate_err;
 205         u32 rx_too_many_frags_err;
 206         u32 rx_drop_rxflush;
 207         u32 rx_beacons;
 208         u32 rx_frags;
 209 };
 210
 211 enum ath_reset_type {
 212         RESET_TYPE_BB_HANG,
 213         RESET_TYPE_BB_WATCHDOG,
 214         RESET_TYPE_FATAL_INT,
 215         RESET_TYPE_TX_ERROR,
 216         RESET_TYPE_TX_HANG,
 217         RESET_TYPE_PLL_HANG,
 218         RESET_TYPE_MAC_HANG,
 219         __RESET_TYPE_MAX
 220 };
 221
 222 struct ath_stats {
 223         struct ath_interrupt_stats istats;
 224         struct ath_tx_stats txstats[ATH9K_NUM_TX_QUEUES];
 225         struct ath_rx_stats rxstats;
 226         struct ath_dfs_stats dfs_stats;
 227         u32 reset[__RESET_TYPE_MAX];
 228 };
 229
 230 #define ATH_DBG_MAX_SAMPLES     10
 231 struct ath_dbg_bb_mac_samp {
 232         u32 dma_dbg_reg_vals[ATH9K_NUM_DMA_DEBUG_REGS];
 233         u32 pcu_obs, pcu_cr, noise;
 234         struct {
 235                 u64 jiffies;
 236                 int8_t rssi_ctl0;
 237                 int8_t rssi_ctl1;
 238                 int8_t rssi_ctl2;
 239                 int8_t rssi_ext0;
 240                 int8_t rssi_ext1;
 241                 int8_t rssi_ext2;
 242                 int8_t rssi;
 243                 bool isok;
 244                 u8 rts_fail_cnt;
 245                 u8 data_fail_cnt;
 246                 u8 rateindex;
 247                 u8 qid;
 248                 u8 tid;
 249                 u32 ba_low;
 250                 u32 ba_high;
 251         } ts[ATH_DBG_MAX_SAMPLES];
 252         struct {
 253                 u64 jiffies;
 254                 int8_t rssi_ctl0;
 255                 int8_t rssi_ctl1;
 256                 int8_t rssi_ctl2;
 257                 int8_t rssi_ext0;
 258                 int8_t rssi_ext1;
 259                 int8_t rssi_ext2;
 260                 int8_t rssi;
 261                 bool is_mybeacon;
 262                 u8 antenna;
 263                 u8 rate;
 264         } rs[ATH_DBG_MAX_SAMPLES];
 265         struct ath_cycle_counters cc;
 266         struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
 267 };
 268
 269 struct ath9k_debug {
 270         struct dentry *debugfs_phy;
 271         u32 regidx;
 272         struct ath_stats stats;
 273 #ifdef CONFIG_ATH9K_MAC_DEBUG
 274         spinlock_t samp_lock;
 275         struct ath_dbg_bb_mac_samp bb_mac_samp[ATH_DBG_MAX_SAMPLES];
 276         u8 sampidx;
 277         u8 tsidx;
 278         u8 rsidx;
 279 #endif
 280 };
 281
 282 int ath9k_init_debug(struct ath_hw *ah);
 283
 284 void ath_debug_stat_interrupt(struct ath_softc *sc, enum ath9k_int status);
 285 void ath_debug_stat_tx(struct ath_softc *sc, struct ath_buf *bf,
 286                        struct ath_tx_status *ts, struct ath_txq *txq,
 287                        unsigned int flags);
 288 void ath_debug_stat_rx(struct ath_softc *sc, struct ath_rx_status *rs);
 289
 290 #else
 291
 292 #define RX_STAT_INC(c) /* NOP */
 293
 294 static inline int ath9k_init_debug(struct ath_hw *ah)
 295 {
 296         return 0;
 297 }
 298
 299 static inline void ath_debug_stat_interrupt(struct ath_softc *sc,
 300                                             enum ath9k_int status)
 301 {
 302 }
 303
 304 static inline void ath_debug_stat_tx(struct ath_softc *sc,
 305                                      struct ath_buf *bf,
 306                                      struct ath_tx_status *ts,
 307                                      struct ath_txq *txq,
 308                                      unsigned int flags)
 309 {
 310 }
 311
 312 static inline void ath_debug_stat_rx(struct ath_softc *sc,
 313                                      struct ath_rx_status *rs)
 314 {
 315 }
 316
 317 #endif /* CONFIG_ATH9K_DEBUGFS */
 318
 319 #ifdef CONFIG_ATH9K_MAC_DEBUG
 320
 321 void ath9k_debug_samp_bb_mac(struct ath_softc *sc);
 322
 323 #else
 324
 325 static inline void ath9k_debug_samp_bb_mac(struct ath_softc *sc)
 326 {
 327 }
 328
 329 #endif
 330
 331
 332 #endif /* DEBUG_H */