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ath9k: Add QCA956x HW support
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / hw.c
1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/io.h>
18 #include <linux/slab.h>
19 #include <linux/module.h>
20 #include <linux/time.h>
21 #include <linux/bitops.h>
22 #include <linux/etherdevice.h>
23 #include <asm/unaligned.h>
24
25 #include "hw.h"
26 #include "hw-ops.h"
27 #include "ar9003_mac.h"
28 #include "ar9003_mci.h"
29 #include "ar9003_phy.h"
30 #include "ath9k.h"
31
32 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
33
34 MODULE_AUTHOR("Atheros Communications");
35 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
36 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
37 MODULE_LICENSE("Dual BSD/GPL");
38
39 static void ath9k_hw_set_clockrate(struct ath_hw *ah)
40 {
41 struct ath_common *common = ath9k_hw_common(ah);
42 struct ath9k_channel *chan = ah->curchan;
43 unsigned int clockrate;
44
45 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */
46 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah))
47 clockrate = 117;
48 else if (!chan) /* should really check for CCK instead */
49 clockrate = ATH9K_CLOCK_RATE_CCK;
50 else if (IS_CHAN_2GHZ(chan))
51 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
52 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
53 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
54 else
55 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
56
57 if (chan) {
58 if (IS_CHAN_HT40(chan))
59 clockrate *= 2;
60 if (IS_CHAN_HALF_RATE(chan))
61 clockrate /= 2;
62 if (IS_CHAN_QUARTER_RATE(chan))
63 clockrate /= 4;
64 }
65
66 common->clockrate = clockrate;
67 }
68
69 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
70 {
71 struct ath_common *common = ath9k_hw_common(ah);
72
73 return usecs * common->clockrate;
74 }
75
76 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
77 {
78 int i;
79
80 BUG_ON(timeout < AH_TIME_QUANTUM);
81
82 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
83 if ((REG_READ(ah, reg) & mask) == val)
84 return true;
85
86 udelay(AH_TIME_QUANTUM);
87 }
88
89 ath_dbg(ath9k_hw_common(ah), ANY,
90 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
91 timeout, reg, REG_READ(ah, reg), mask, val);
92
93 return false;
94 }
95 EXPORT_SYMBOL(ath9k_hw_wait);
96
97 void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan,
98 int hw_delay)
99 {
100 hw_delay /= 10;
101
102 if (IS_CHAN_HALF_RATE(chan))
103 hw_delay *= 2;
104 else if (IS_CHAN_QUARTER_RATE(chan))
105 hw_delay *= 4;
106
107 udelay(hw_delay + BASE_ACTIVATE_DELAY);
108 }
109
110 void ath9k_hw_write_array(struct ath_hw *ah, const struct ar5416IniArray *array,
111 int column, unsigned int *writecnt)
112 {
113 int r;
114
115 ENABLE_REGWRITE_BUFFER(ah);
116 for (r = 0; r < array->ia_rows; r++) {
117 REG_WRITE(ah, INI_RA(array, r, 0),
118 INI_RA(array, r, column));
119 DO_DELAY(*writecnt);
120 }
121 REGWRITE_BUFFER_FLUSH(ah);
122 }
123
124 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
125 {
126 u32 retval;
127 int i;
128
129 for (i = 0, retval = 0; i < n; i++) {
130 retval = (retval << 1) | (val & 1);
131 val >>= 1;
132 }
133 return retval;
134 }
135
136 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
137 u8 phy, int kbps,
138 u32 frameLen, u16 rateix,
139 bool shortPreamble)
140 {
141 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
142
143 if (kbps == 0)
144 return 0;
145
146 switch (phy) {
147 case WLAN_RC_PHY_CCK:
148 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
149 if (shortPreamble)
150 phyTime >>= 1;
151 numBits = frameLen << 3;
152 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
153 break;
154 case WLAN_RC_PHY_OFDM:
155 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
156 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
157 numBits = OFDM_PLCP_BITS + (frameLen << 3);
158 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
159 txTime = OFDM_SIFS_TIME_QUARTER
160 + OFDM_PREAMBLE_TIME_QUARTER
161 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
162 } else if (ah->curchan &&
163 IS_CHAN_HALF_RATE(ah->curchan)) {
164 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
165 numBits = OFDM_PLCP_BITS + (frameLen << 3);
166 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
167 txTime = OFDM_SIFS_TIME_HALF +
168 OFDM_PREAMBLE_TIME_HALF
169 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
170 } else {
171 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
172 numBits = OFDM_PLCP_BITS + (frameLen << 3);
173 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
174 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
175 + (numSymbols * OFDM_SYMBOL_TIME);
176 }
177 break;
178 default:
179 ath_err(ath9k_hw_common(ah),
180 "Unknown phy %u (rate ix %u)\n", phy, rateix);
181 txTime = 0;
182 break;
183 }
184
185 return txTime;
186 }
187 EXPORT_SYMBOL(ath9k_hw_computetxtime);
188
189 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
190 struct ath9k_channel *chan,
191 struct chan_centers *centers)
192 {
193 int8_t extoff;
194
195 if (!IS_CHAN_HT40(chan)) {
196 centers->ctl_center = centers->ext_center =
197 centers->synth_center = chan->channel;
198 return;
199 }
200
201 if (IS_CHAN_HT40PLUS(chan)) {
202 centers->synth_center =
203 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
204 extoff = 1;
205 } else {
206 centers->synth_center =
207 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
208 extoff = -1;
209 }
210
211 centers->ctl_center =
212 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
213 /* 25 MHz spacing is supported by hw but not on upper layers */
214 centers->ext_center =
215 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
216 }
217
218 /******************/
219 /* Chip Revisions */
220 /******************/
221
222 static void ath9k_hw_read_revisions(struct ath_hw *ah)
223 {
224 u32 val;
225
226 if (ah->get_mac_revision)
227 ah->hw_version.macRev = ah->get_mac_revision();
228
229 switch (ah->hw_version.devid) {
230 case AR5416_AR9100_DEVID:
231 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
232 break;
233 case AR9300_DEVID_AR9330:
234 ah->hw_version.macVersion = AR_SREV_VERSION_9330;
235 if (!ah->get_mac_revision) {
236 val = REG_READ(ah, AR_SREV);
237 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
238 }
239 return;
240 case AR9300_DEVID_AR9340:
241 ah->hw_version.macVersion = AR_SREV_VERSION_9340;
242 return;
243 case AR9300_DEVID_QCA955X:
244 ah->hw_version.macVersion = AR_SREV_VERSION_9550;
245 return;
246 case AR9300_DEVID_AR953X:
247 ah->hw_version.macVersion = AR_SREV_VERSION_9531;
248 return;
249 case AR9300_DEVID_QCA956X:
250 ah->hw_version.macVersion = AR_SREV_VERSION_9561;
251 }
252
253 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
254
255 if (val == 0xFF) {
256 val = REG_READ(ah, AR_SREV);
257 ah->hw_version.macVersion =
258 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
259 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
260
261 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
262 ah->is_pciexpress = true;
263 else
264 ah->is_pciexpress = (val &
265 AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
266 } else {
267 if (!AR_SREV_9100(ah))
268 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
269
270 ah->hw_version.macRev = val & AR_SREV_REVISION;
271
272 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
273 ah->is_pciexpress = true;
274 }
275 }
276
277 /************************************/
278 /* HW Attach, Detach, Init Routines */
279 /************************************/
280
281 static void ath9k_hw_disablepcie(struct ath_hw *ah)
282 {
283 if (!AR_SREV_5416(ah))
284 return;
285
286 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
287 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
288 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
289 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
290 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
291 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
292 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
293 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
294 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
295
296 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
297 }
298
299 /* This should work for all families including legacy */
300 static bool ath9k_hw_chip_test(struct ath_hw *ah)
301 {
302 struct ath_common *common = ath9k_hw_common(ah);
303 u32 regAddr[2] = { AR_STA_ID0 };
304 u32 regHold[2];
305 static const u32 patternData[4] = {
306 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
307 };
308 int i, j, loop_max;
309
310 if (!AR_SREV_9300_20_OR_LATER(ah)) {
311 loop_max = 2;
312 regAddr[1] = AR_PHY_BASE + (8 << 2);
313 } else
314 loop_max = 1;
315
316 for (i = 0; i < loop_max; i++) {
317 u32 addr = regAddr[i];
318 u32 wrData, rdData;
319
320 regHold[i] = REG_READ(ah, addr);
321 for (j = 0; j < 0x100; j++) {
322 wrData = (j << 16) | j;
323 REG_WRITE(ah, addr, wrData);
324 rdData = REG_READ(ah, addr);
325 if (rdData != wrData) {
326 ath_err(common,
327 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
328 addr, wrData, rdData);
329 return false;
330 }
331 }
332 for (j = 0; j < 4; j++) {
333 wrData = patternData[j];
334 REG_WRITE(ah, addr, wrData);
335 rdData = REG_READ(ah, addr);
336 if (wrData != rdData) {
337 ath_err(common,
338 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
339 addr, wrData, rdData);
340 return false;
341 }
342 }
343 REG_WRITE(ah, regAddr[i], regHold[i]);
344 }
345 udelay(100);
346
347 return true;
348 }
349
350 static void ath9k_hw_init_config(struct ath_hw *ah)
351 {
352 struct ath_common *common = ath9k_hw_common(ah);
353
354 ah->config.dma_beacon_response_time = 1;
355 ah->config.sw_beacon_response_time = 6;
356 ah->config.cwm_ignore_extcca = 0;
357 ah->config.analog_shiftreg = 1;
358
359 ah->config.rx_intr_mitigation = true;
360
361 if (AR_SREV_9300_20_OR_LATER(ah)) {
362 ah->config.rimt_last = 500;
363 ah->config.rimt_first = 2000;
364 } else {
365 ah->config.rimt_last = 250;
366 ah->config.rimt_first = 700;
367 }
368
369 /*
370 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
371 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
372 * This means we use it for all AR5416 devices, and the few
373 * minor PCI AR9280 devices out there.
374 *
375 * Serialization is required because these devices do not handle
376 * well the case of two concurrent reads/writes due to the latency
377 * involved. During one read/write another read/write can be issued
378 * on another CPU while the previous read/write may still be working
379 * on our hardware, if we hit this case the hardware poops in a loop.
380 * We prevent this by serializing reads and writes.
381 *
382 * This issue is not present on PCI-Express devices or pre-AR5416
383 * devices (legacy, 802.11abg).
384 */
385 if (num_possible_cpus() > 1)
386 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
387
388 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
389 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
390 ((AR_SREV_9160(ah) || AR_SREV_9280(ah) || AR_SREV_9287(ah)) &&
391 !ah->is_pciexpress)) {
392 ah->config.serialize_regmode = SER_REG_MODE_ON;
393 } else {
394 ah->config.serialize_regmode = SER_REG_MODE_OFF;
395 }
396 }
397
398 ath_dbg(common, RESET, "serialize_regmode is %d\n",
399 ah->config.serialize_regmode);
400
401 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
402 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
403 else
404 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
405 }
406
407 static void ath9k_hw_init_defaults(struct ath_hw *ah)
408 {
409 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
410
411 regulatory->country_code = CTRY_DEFAULT;
412 regulatory->power_limit = MAX_RATE_POWER;
413
414 ah->hw_version.magic = AR5416_MAGIC;
415 ah->hw_version.subvendorid = 0;
416
417 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE |
418 AR_STA_ID1_MCAST_KSRCH;
419 if (AR_SREV_9100(ah))
420 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX;
421
422 ah->slottime = ATH9K_SLOT_TIME_9;
423 ah->globaltxtimeout = (u32) -1;
424 ah->power_mode = ATH9K_PM_UNDEFINED;
425 ah->htc_reset_init = true;
426
427 /* ar9002 does not support TPC for the moment */
428 ah->tpc_enabled = !!AR_SREV_9300_20_OR_LATER(ah);
429
430 ah->ani_function = ATH9K_ANI_ALL;
431 if (!AR_SREV_9300_20_OR_LATER(ah))
432 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
433
434 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
435 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
436 else
437 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
438 }
439
440 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
441 {
442 struct ath_common *common = ath9k_hw_common(ah);
443 u32 sum;
444 int i;
445 u16 eeval;
446 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
447
448 sum = 0;
449 for (i = 0; i < 3; i++) {
450 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
451 sum += eeval;
452 common->macaddr[2 * i] = eeval >> 8;
453 common->macaddr[2 * i + 1] = eeval & 0xff;
454 }
455 if (!is_valid_ether_addr(common->macaddr)) {
456 ath_err(common,
457 "eeprom contains invalid mac address: %pM\n",
458 common->macaddr);
459
460 random_ether_addr(common->macaddr);
461 ath_err(common,
462 "random mac address will be used: %pM\n",
463 common->macaddr);
464 }
465
466 return 0;
467 }
468
469 static int ath9k_hw_post_init(struct ath_hw *ah)
470 {
471 struct ath_common *common = ath9k_hw_common(ah);
472 int ecode;
473
474 if (common->bus_ops->ath_bus_type != ATH_USB) {
475 if (!ath9k_hw_chip_test(ah))
476 return -ENODEV;
477 }
478
479 if (!AR_SREV_9300_20_OR_LATER(ah)) {
480 ecode = ar9002_hw_rf_claim(ah);
481 if (ecode != 0)
482 return ecode;
483 }
484
485 ecode = ath9k_hw_eeprom_init(ah);
486 if (ecode != 0)
487 return ecode;
488
489 ath_dbg(ath9k_hw_common(ah), CONFIG, "Eeprom VER: %d, REV: %d\n",
490 ah->eep_ops->get_eeprom_ver(ah),
491 ah->eep_ops->get_eeprom_rev(ah));
492
493 ath9k_hw_ani_init(ah);
494
495 /*
496 * EEPROM needs to be initialized before we do this.
497 * This is required for regulatory compliance.
498 */
499 if (AR_SREV_9300_20_OR_LATER(ah)) {
500 u16 regdmn = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
501 if ((regdmn & 0xF0) == CTL_FCC) {
502 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_2GHZ;
503 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_5GHZ;
504 }
505 }
506
507 return 0;
508 }
509
510 static int ath9k_hw_attach_ops(struct ath_hw *ah)
511 {
512 if (!AR_SREV_9300_20_OR_LATER(ah))
513 return ar9002_hw_attach_ops(ah);
514
515 ar9003_hw_attach_ops(ah);
516 return 0;
517 }
518
519 /* Called for all hardware families */
520 static int __ath9k_hw_init(struct ath_hw *ah)
521 {
522 struct ath_common *common = ath9k_hw_common(ah);
523 int r = 0;
524
525 ath9k_hw_read_revisions(ah);
526
527 switch (ah->hw_version.macVersion) {
528 case AR_SREV_VERSION_5416_PCI:
529 case AR_SREV_VERSION_5416_PCIE:
530 case AR_SREV_VERSION_9160:
531 case AR_SREV_VERSION_9100:
532 case AR_SREV_VERSION_9280:
533 case AR_SREV_VERSION_9285:
534 case AR_SREV_VERSION_9287:
535 case AR_SREV_VERSION_9271:
536 case AR_SREV_VERSION_9300:
537 case AR_SREV_VERSION_9330:
538 case AR_SREV_VERSION_9485:
539 case AR_SREV_VERSION_9340:
540 case AR_SREV_VERSION_9462:
541 case AR_SREV_VERSION_9550:
542 case AR_SREV_VERSION_9565:
543 case AR_SREV_VERSION_9531:
544 case AR_SREV_VERSION_9561:
545 break;
546 default:
547 ath_err(common,
548 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
549 ah->hw_version.macVersion, ah->hw_version.macRev);
550 return -EOPNOTSUPP;
551 }
552
553 /*
554 * Read back AR_WA into a permanent copy and set bits 14 and 17.
555 * We need to do this to avoid RMW of this register. We cannot
556 * read the reg when chip is asleep.
557 */
558 if (AR_SREV_9300_20_OR_LATER(ah)) {
559 ah->WARegVal = REG_READ(ah, AR_WA);
560 ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
561 AR_WA_ASPM_TIMER_BASED_DISABLE);
562 }
563
564 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
565 ath_err(common, "Couldn't reset chip\n");
566 return -EIO;
567 }
568
569 if (AR_SREV_9565(ah)) {
570 ah->WARegVal |= AR_WA_BIT22;
571 REG_WRITE(ah, AR_WA, ah->WARegVal);
572 }
573
574 ath9k_hw_init_defaults(ah);
575 ath9k_hw_init_config(ah);
576
577 r = ath9k_hw_attach_ops(ah);
578 if (r)
579 return r;
580
581 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
582 ath_err(common, "Couldn't wakeup chip\n");
583 return -EIO;
584 }
585
586 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) ||
587 AR_SREV_9330(ah) || AR_SREV_9550(ah))
588 ah->is_pciexpress = false;
589
590 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
591 ath9k_hw_init_cal_settings(ah);
592
593 if (!ah->is_pciexpress)
594 ath9k_hw_disablepcie(ah);
595
596 r = ath9k_hw_post_init(ah);
597 if (r)
598 return r;
599
600 ath9k_hw_init_mode_gain_regs(ah);
601 r = ath9k_hw_fill_cap_info(ah);
602 if (r)
603 return r;
604
605 r = ath9k_hw_init_macaddr(ah);
606 if (r) {
607 ath_err(common, "Failed to initialize MAC address\n");
608 return r;
609 }
610
611 ath9k_hw_init_hang_checks(ah);
612
613 common->state = ATH_HW_INITIALIZED;
614
615 return 0;
616 }
617
618 int ath9k_hw_init(struct ath_hw *ah)
619 {
620 int ret;
621 struct ath_common *common = ath9k_hw_common(ah);
622
623 /* These are all the AR5008/AR9001/AR9002/AR9003 hardware family of chipsets */
624 switch (ah->hw_version.devid) {
625 case AR5416_DEVID_PCI:
626 case AR5416_DEVID_PCIE:
627 case AR5416_AR9100_DEVID:
628 case AR9160_DEVID_PCI:
629 case AR9280_DEVID_PCI:
630 case AR9280_DEVID_PCIE:
631 case AR9285_DEVID_PCIE:
632 case AR9287_DEVID_PCI:
633 case AR9287_DEVID_PCIE:
634 case AR2427_DEVID_PCIE:
635 case AR9300_DEVID_PCIE:
636 case AR9300_DEVID_AR9485_PCIE:
637 case AR9300_DEVID_AR9330:
638 case AR9300_DEVID_AR9340:
639 case AR9300_DEVID_QCA955X:
640 case AR9300_DEVID_AR9580:
641 case AR9300_DEVID_AR9462:
642 case AR9485_DEVID_AR1111:
643 case AR9300_DEVID_AR9565:
644 case AR9300_DEVID_AR953X:
645 case AR9300_DEVID_QCA956X:
646 break;
647 default:
648 if (common->bus_ops->ath_bus_type == ATH_USB)
649 break;
650 ath_err(common, "Hardware device ID 0x%04x not supported\n",
651 ah->hw_version.devid);
652 return -EOPNOTSUPP;
653 }
654
655 ret = __ath9k_hw_init(ah);
656 if (ret) {
657 ath_err(common,
658 "Unable to initialize hardware; initialization status: %d\n",
659 ret);
660 return ret;
661 }
662
663 ath_dynack_init(ah);
664
665 return 0;
666 }
667 EXPORT_SYMBOL(ath9k_hw_init);
668
669 static void ath9k_hw_init_qos(struct ath_hw *ah)
670 {
671 ENABLE_REGWRITE_BUFFER(ah);
672
673 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
674 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
675
676 REG_WRITE(ah, AR_QOS_NO_ACK,
677 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
678 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
679 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
680
681 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
682 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
683 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
684 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
685 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
686
687 REGWRITE_BUFFER_FLUSH(ah);
688 }
689
690 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
691 {
692 struct ath_common *common = ath9k_hw_common(ah);
693 int i = 0;
694
695 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
696 udelay(100);
697 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
698
699 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) {
700
701 udelay(100);
702
703 if (WARN_ON_ONCE(i >= 100)) {
704 ath_err(common, "PLL4 meaurement not done\n");
705 break;
706 }
707
708 i++;
709 }
710
711 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
712 }
713 EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc);
714
715 static void ath9k_hw_init_pll(struct ath_hw *ah,
716 struct ath9k_channel *chan)
717 {
718 u32 pll;
719
720 pll = ath9k_hw_compute_pll_control(ah, chan);
721
722 if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
723 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */
724 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
725 AR_CH0_BB_DPLL2_PLL_PWD, 0x1);
726 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
727 AR_CH0_DPLL2_KD, 0x40);
728 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
729 AR_CH0_DPLL2_KI, 0x4);
730
731 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
732 AR_CH0_BB_DPLL1_REFDIV, 0x5);
733 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
734 AR_CH0_BB_DPLL1_NINI, 0x58);
735 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
736 AR_CH0_BB_DPLL1_NFRAC, 0x0);
737
738 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
739 AR_CH0_BB_DPLL2_OUTDIV, 0x1);
740 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
741 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1);
742 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
743 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1);
744
745 /* program BB PLL phase_shift to 0x6 */
746 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
747 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6);
748
749 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
750 AR_CH0_BB_DPLL2_PLL_PWD, 0x0);
751 udelay(1000);
752 } else if (AR_SREV_9330(ah)) {
753 u32 ddr_dpll2, pll_control2, kd;
754
755 if (ah->is_clk_25mhz) {
756 ddr_dpll2 = 0x18e82f01;
757 pll_control2 = 0xe04a3d;
758 kd = 0x1d;
759 } else {
760 ddr_dpll2 = 0x19e82f01;
761 pll_control2 = 0x886666;
762 kd = 0x3d;
763 }
764
765 /* program DDR PLL ki and kd value */
766 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2);
767
768 /* program DDR PLL phase_shift */
769 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3,
770 AR_CH0_DPLL3_PHASE_SHIFT, 0x1);
771
772 REG_WRITE(ah, AR_RTC_PLL_CONTROL,
773 pll | AR_RTC_9300_PLL_BYPASS);
774 udelay(1000);
775
776 /* program refdiv, nint, frac to RTC register */
777 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2);
778
779 /* program BB PLL kd and ki value */
780 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd);
781 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06);
782
783 /* program BB PLL phase_shift */
784 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
785 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1);
786 } else if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah) ||
787 AR_SREV_9561(ah)) {
788 u32 regval, pll2_divint, pll2_divfrac, refdiv;
789
790 REG_WRITE(ah, AR_RTC_PLL_CONTROL,
791 pll | AR_RTC_9300_SOC_PLL_BYPASS);
792 udelay(1000);
793
794 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16);
795 udelay(100);
796
797 if (ah->is_clk_25mhz) {
798 if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) {
799 pll2_divint = 0x1c;
800 pll2_divfrac = 0xa3d2;
801 refdiv = 1;
802 } else {
803 pll2_divint = 0x54;
804 pll2_divfrac = 0x1eb85;
805 refdiv = 3;
806 }
807 } else {
808 if (AR_SREV_9340(ah)) {
809 pll2_divint = 88;
810 pll2_divfrac = 0;
811 refdiv = 5;
812 } else {
813 pll2_divint = 0x11;
814 pll2_divfrac = (AR_SREV_9531(ah) ||
815 AR_SREV_9561(ah)) ?
816 0x26665 : 0x26666;
817 refdiv = 1;
818 }
819 }
820
821 regval = REG_READ(ah, AR_PHY_PLL_MODE);
822 if (AR_SREV_9531(ah) || AR_SREV_9561(ah))
823 regval |= (0x1 << 22);
824 else
825 regval |= (0x1 << 16);
826 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
827 udelay(100);
828
829 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) |
830 (pll2_divint << 18) | pll2_divfrac);
831 udelay(100);
832
833 regval = REG_READ(ah, AR_PHY_PLL_MODE);
834 if (AR_SREV_9340(ah))
835 regval = (regval & 0x80071fff) |
836 (0x1 << 30) |
837 (0x1 << 13) |
838 (0x4 << 26) |
839 (0x18 << 19);
840 else if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) {
841 regval = (regval & 0x01c00fff) |
842 (0x1 << 31) |
843 (0x2 << 29) |
844 (0xa << 25) |
845 (0x1 << 19);
846
847 if (AR_SREV_9531(ah))
848 regval |= (0x6 << 12);
849 } else
850 regval = (regval & 0x80071fff) |
851 (0x3 << 30) |
852 (0x1 << 13) |
853 (0x4 << 26) |
854 (0x60 << 19);
855 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
856
857 if (AR_SREV_9531(ah) || AR_SREV_9561(ah))
858 REG_WRITE(ah, AR_PHY_PLL_MODE,
859 REG_READ(ah, AR_PHY_PLL_MODE) & 0xffbfffff);
860 else
861 REG_WRITE(ah, AR_PHY_PLL_MODE,
862 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff);
863
864 udelay(1000);
865 }
866
867 if (AR_SREV_9565(ah))
868 pll |= 0x40000;
869 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
870
871 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
872 AR_SREV_9550(ah))
873 udelay(1000);
874
875 /* Switch the core clock for ar9271 to 117Mhz */
876 if (AR_SREV_9271(ah)) {
877 udelay(500);
878 REG_WRITE(ah, 0x50040, 0x304);
879 }
880
881 udelay(RTC_PLL_SETTLE_DELAY);
882
883 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
884 }
885
886 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
887 enum nl80211_iftype opmode)
888 {
889 u32 sync_default = AR_INTR_SYNC_DEFAULT;
890 u32 imr_reg = AR_IMR_TXERR |
891 AR_IMR_TXURN |
892 AR_IMR_RXERR |
893 AR_IMR_RXORN |
894 AR_IMR_BCNMISC;
895
896 if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah) ||
897 AR_SREV_9561(ah))
898 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
899
900 if (AR_SREV_9300_20_OR_LATER(ah)) {
901 imr_reg |= AR_IMR_RXOK_HP;
902 if (ah->config.rx_intr_mitigation)
903 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
904 else
905 imr_reg |= AR_IMR_RXOK_LP;
906
907 } else {
908 if (ah->config.rx_intr_mitigation)
909 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
910 else
911 imr_reg |= AR_IMR_RXOK;
912 }
913
914 if (ah->config.tx_intr_mitigation)
915 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
916 else
917 imr_reg |= AR_IMR_TXOK;
918
919 ENABLE_REGWRITE_BUFFER(ah);
920
921 REG_WRITE(ah, AR_IMR, imr_reg);
922 ah->imrs2_reg |= AR_IMR_S2_GTT;
923 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
924
925 if (!AR_SREV_9100(ah)) {
926 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
927 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
928 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
929 }
930
931 REGWRITE_BUFFER_FLUSH(ah);
932
933 if (AR_SREV_9300_20_OR_LATER(ah)) {
934 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
935 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
936 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
937 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
938 }
939 }
940
941 static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us)
942 {
943 u32 val = ath9k_hw_mac_to_clks(ah, us - 2);
944 val = min(val, (u32) 0xFFFF);
945 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val);
946 }
947
948 void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
949 {
950 u32 val = ath9k_hw_mac_to_clks(ah, us);
951 val = min(val, (u32) 0xFFFF);
952 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
953 }
954
955 void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
956 {
957 u32 val = ath9k_hw_mac_to_clks(ah, us);
958 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
959 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
960 }
961
962 void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
963 {
964 u32 val = ath9k_hw_mac_to_clks(ah, us);
965 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
966 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
967 }
968
969 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
970 {
971 if (tu > 0xFFFF) {
972 ath_dbg(ath9k_hw_common(ah), XMIT, "bad global tx timeout %u\n",
973 tu);
974 ah->globaltxtimeout = (u32) -1;
975 return false;
976 } else {
977 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
978 ah->globaltxtimeout = tu;
979 return true;
980 }
981 }
982
983 void ath9k_hw_init_global_settings(struct ath_hw *ah)
984 {
985 struct ath_common *common = ath9k_hw_common(ah);
986 const struct ath9k_channel *chan = ah->curchan;
987 int acktimeout, ctstimeout, ack_offset = 0;
988 int slottime;
989 int sifstime;
990 int rx_lat = 0, tx_lat = 0, eifs = 0;
991 u32 reg;
992
993 ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n",
994 ah->misc_mode);
995
996 if (!chan)
997 return;
998
999 if (ah->misc_mode != 0)
1000 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode);
1001
1002 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1003 rx_lat = 41;
1004 else
1005 rx_lat = 37;
1006 tx_lat = 54;
1007
1008 if (IS_CHAN_5GHZ(chan))
1009 sifstime = 16;
1010 else
1011 sifstime = 10;
1012
1013 if (IS_CHAN_HALF_RATE(chan)) {
1014 eifs = 175;
1015 rx_lat *= 2;
1016 tx_lat *= 2;
1017 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1018 tx_lat += 11;
1019
1020 sifstime = 32;
1021 ack_offset = 16;
1022 slottime = 13;
1023 } else if (IS_CHAN_QUARTER_RATE(chan)) {
1024 eifs = 340;
1025 rx_lat = (rx_lat * 4) - 1;
1026 tx_lat *= 4;
1027 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1028 tx_lat += 22;
1029
1030 sifstime = 64;
1031 ack_offset = 32;
1032 slottime = 21;
1033 } else {
1034 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1035 eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO;
1036 reg = AR_USEC_ASYNC_FIFO;
1037 } else {
1038 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/
1039 common->clockrate;
1040 reg = REG_READ(ah, AR_USEC);
1041 }
1042 rx_lat = MS(reg, AR_USEC_RX_LAT);
1043 tx_lat = MS(reg, AR_USEC_TX_LAT);
1044
1045 slottime = ah->slottime;
1046 }
1047
1048 /* As defined by IEEE 802.11-2007 17.3.8.6 */
1049 slottime += 3 * ah->coverage_class;
1050 acktimeout = slottime + sifstime + ack_offset;
1051 ctstimeout = acktimeout;
1052
1053 /*
1054 * Workaround for early ACK timeouts, add an offset to match the
1055 * initval's 64us ack timeout value. Use 48us for the CTS timeout.
1056 * This was initially only meant to work around an issue with delayed
1057 * BA frames in some implementations, but it has been found to fix ACK
1058 * timeout issues in other cases as well.
1059 */
1060 if (IS_CHAN_2GHZ(chan) &&
1061 !IS_CHAN_HALF_RATE(chan) && !IS_CHAN_QUARTER_RATE(chan)) {
1062 acktimeout += 64 - sifstime - ah->slottime;
1063 ctstimeout += 48 - sifstime - ah->slottime;
1064 }
1065
1066 if (ah->dynack.enabled) {
1067 acktimeout = ah->dynack.ackto;
1068 ctstimeout = acktimeout;
1069 slottime = (acktimeout - 3) / 2;
1070 } else {
1071 ah->dynack.ackto = acktimeout;
1072 }
1073
1074 ath9k_hw_set_sifs_time(ah, sifstime);
1075 ath9k_hw_setslottime(ah, slottime);
1076 ath9k_hw_set_ack_timeout(ah, acktimeout);
1077 ath9k_hw_set_cts_timeout(ah, ctstimeout);
1078 if (ah->globaltxtimeout != (u32) -1)
1079 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1080
1081 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs));
1082 REG_RMW(ah, AR_USEC,
1083 (common->clockrate - 1) |
1084 SM(rx_lat, AR_USEC_RX_LAT) |
1085 SM(tx_lat, AR_USEC_TX_LAT),
1086 AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC);
1087
1088 }
1089 EXPORT_SYMBOL(ath9k_hw_init_global_settings);
1090
1091 void ath9k_hw_deinit(struct ath_hw *ah)
1092 {
1093 struct ath_common *common = ath9k_hw_common(ah);
1094
1095 if (common->state < ATH_HW_INITIALIZED)
1096 return;
1097
1098 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1099 }
1100 EXPORT_SYMBOL(ath9k_hw_deinit);
1101
1102 /*******/
1103 /* INI */
1104 /*******/
1105
1106 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
1107 {
1108 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1109
1110 if (IS_CHAN_2GHZ(chan))
1111 ctl |= CTL_11G;
1112 else
1113 ctl |= CTL_11A;
1114
1115 return ctl;
1116 }
1117
1118 /****************************************/
1119 /* Reset and Channel Switching Routines */
1120 /****************************************/
1121
1122 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1123 {
1124 struct ath_common *common = ath9k_hw_common(ah);
1125 int txbuf_size;
1126
1127 ENABLE_REGWRITE_BUFFER(ah);
1128
1129 /*
1130 * set AHB_MODE not to do cacheline prefetches
1131 */
1132 if (!AR_SREV_9300_20_OR_LATER(ah))
1133 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
1134
1135 /*
1136 * let mac dma reads be in 128 byte chunks
1137 */
1138 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK);
1139
1140 REGWRITE_BUFFER_FLUSH(ah);
1141
1142 /*
1143 * Restore TX Trigger Level to its pre-reset value.
1144 * The initial value depends on whether aggregation is enabled, and is
1145 * adjusted whenever underruns are detected.
1146 */
1147 if (!AR_SREV_9300_20_OR_LATER(ah))
1148 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1149
1150 ENABLE_REGWRITE_BUFFER(ah);
1151
1152 /*
1153 * let mac dma writes be in 128 byte chunks
1154 */
1155 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK);
1156
1157 /*
1158 * Setup receive FIFO threshold to hold off TX activities
1159 */
1160 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1161
1162 if (AR_SREV_9300_20_OR_LATER(ah)) {
1163 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
1164 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
1165
1166 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
1167 ah->caps.rx_status_len);
1168 }
1169
1170 /*
1171 * reduce the number of usable entries in PCU TXBUF to avoid
1172 * wrap around issues.
1173 */
1174 if (AR_SREV_9285(ah)) {
1175 /* For AR9285 the number of Fifos are reduced to half.
1176 * So set the usable tx buf size also to half to
1177 * avoid data/delimiter underruns
1178 */
1179 txbuf_size = AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE;
1180 } else if (AR_SREV_9340_13_OR_LATER(ah)) {
1181 /* Uses fewer entries for AR934x v1.3+ to prevent rx overruns */
1182 txbuf_size = AR_9340_PCU_TXBUF_CTRL_USABLE_SIZE;
1183 } else {
1184 txbuf_size = AR_PCU_TXBUF_CTRL_USABLE_SIZE;
1185 }
1186
1187 if (!AR_SREV_9271(ah))
1188 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, txbuf_size);
1189
1190 REGWRITE_BUFFER_FLUSH(ah);
1191
1192 if (AR_SREV_9300_20_OR_LATER(ah))
1193 ath9k_hw_reset_txstatus_ring(ah);
1194 }
1195
1196 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1197 {
1198 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC;
1199 u32 set = AR_STA_ID1_KSRCH_MODE;
1200
1201 switch (opmode) {
1202 case NL80211_IFTYPE_ADHOC:
1203 if (!AR_SREV_9340_13(ah)) {
1204 set |= AR_STA_ID1_ADHOC;
1205 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1206 break;
1207 }
1208 /* fall through */
1209 case NL80211_IFTYPE_MESH_POINT:
1210 case NL80211_IFTYPE_AP:
1211 set |= AR_STA_ID1_STA_AP;
1212 /* fall through */
1213 case NL80211_IFTYPE_STATION:
1214 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1215 break;
1216 default:
1217 if (!ah->is_monitoring)
1218 set = 0;
1219 break;
1220 }
1221 REG_RMW(ah, AR_STA_ID1, set, mask);
1222 }
1223
1224 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1225 u32 *coef_mantissa, u32 *coef_exponent)
1226 {
1227 u32 coef_exp, coef_man;
1228
1229 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1230 if ((coef_scaled >> coef_exp) & 0x1)
1231 break;
1232
1233 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1234
1235 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1236
1237 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1238 *coef_exponent = coef_exp - 16;
1239 }
1240
1241 /* AR9330 WAR:
1242 * call external reset function to reset WMAC if:
1243 * - doing a cold reset
1244 * - we have pending frames in the TX queues.
1245 */
1246 static bool ath9k_hw_ar9330_reset_war(struct ath_hw *ah, int type)
1247 {
1248 int i, npend = 0;
1249
1250 for (i = 0; i < AR_NUM_QCU; i++) {
1251 npend = ath9k_hw_numtxpending(ah, i);
1252 if (npend)
1253 break;
1254 }
1255
1256 if (ah->external_reset &&
1257 (npend || type == ATH9K_RESET_COLD)) {
1258 int reset_err = 0;
1259
1260 ath_dbg(ath9k_hw_common(ah), RESET,
1261 "reset MAC via external reset\n");
1262
1263 reset_err = ah->external_reset();
1264 if (reset_err) {
1265 ath_err(ath9k_hw_common(ah),
1266 "External reset failed, err=%d\n",
1267 reset_err);
1268 return false;
1269 }
1270
1271 REG_WRITE(ah, AR_RTC_RESET, 1);
1272 }
1273
1274 return true;
1275 }
1276
1277 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1278 {
1279 u32 rst_flags;
1280 u32 tmpReg;
1281
1282 if (AR_SREV_9100(ah)) {
1283 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK,
1284 AR_RTC_DERIVED_CLK_PERIOD, 1);
1285 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1286 }
1287
1288 ENABLE_REGWRITE_BUFFER(ah);
1289
1290 if (AR_SREV_9300_20_OR_LATER(ah)) {
1291 REG_WRITE(ah, AR_WA, ah->WARegVal);
1292 udelay(10);
1293 }
1294
1295 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1296 AR_RTC_FORCE_WAKE_ON_INT);
1297
1298 if (AR_SREV_9100(ah)) {
1299 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1300 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1301 } else {
1302 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1303 if (AR_SREV_9340(ah))
1304 tmpReg &= AR9340_INTR_SYNC_LOCAL_TIMEOUT;
1305 else
1306 tmpReg &= AR_INTR_SYNC_LOCAL_TIMEOUT |
1307 AR_INTR_SYNC_RADM_CPL_TIMEOUT;
1308
1309 if (tmpReg) {
1310 u32 val;
1311 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1312
1313 val = AR_RC_HOSTIF;
1314 if (!AR_SREV_9300_20_OR_LATER(ah))
1315 val |= AR_RC_AHB;
1316 REG_WRITE(ah, AR_RC, val);
1317
1318 } else if (!AR_SREV_9300_20_OR_LATER(ah))
1319 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1320
1321 rst_flags = AR_RTC_RC_MAC_WARM;
1322 if (type == ATH9K_RESET_COLD)
1323 rst_flags |= AR_RTC_RC_MAC_COLD;
1324 }
1325
1326 if (AR_SREV_9330(ah)) {
1327 if (!ath9k_hw_ar9330_reset_war(ah, type))
1328 return false;
1329 }
1330
1331 if (ath9k_hw_mci_is_enabled(ah))
1332 ar9003_mci_check_gpm_offset(ah);
1333
1334 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1335
1336 REGWRITE_BUFFER_FLUSH(ah);
1337
1338 if (AR_SREV_9300_20_OR_LATER(ah))
1339 udelay(50);
1340 else if (AR_SREV_9100(ah))
1341 mdelay(10);
1342 else
1343 udelay(100);
1344
1345 REG_WRITE(ah, AR_RTC_RC, 0);
1346 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1347 ath_dbg(ath9k_hw_common(ah), RESET, "RTC stuck in MAC reset\n");
1348 return false;
1349 }
1350
1351 if (!AR_SREV_9100(ah))
1352 REG_WRITE(ah, AR_RC, 0);
1353
1354 if (AR_SREV_9100(ah))
1355 udelay(50);
1356
1357 return true;
1358 }
1359
1360 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1361 {
1362 ENABLE_REGWRITE_BUFFER(ah);
1363
1364 if (AR_SREV_9300_20_OR_LATER(ah)) {
1365 REG_WRITE(ah, AR_WA, ah->WARegVal);
1366 udelay(10);
1367 }
1368
1369 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1370 AR_RTC_FORCE_WAKE_ON_INT);
1371
1372 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1373 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1374
1375 REG_WRITE(ah, AR_RTC_RESET, 0);
1376
1377 REGWRITE_BUFFER_FLUSH(ah);
1378
1379 udelay(2);
1380
1381 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1382 REG_WRITE(ah, AR_RC, 0);
1383
1384 REG_WRITE(ah, AR_RTC_RESET, 1);
1385
1386 if (!ath9k_hw_wait(ah,
1387 AR_RTC_STATUS,
1388 AR_RTC_STATUS_M,
1389 AR_RTC_STATUS_ON,
1390 AH_WAIT_TIMEOUT)) {
1391 ath_dbg(ath9k_hw_common(ah), RESET, "RTC not waking up\n");
1392 return false;
1393 }
1394
1395 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1396 }
1397
1398 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1399 {
1400 bool ret = false;
1401
1402 if (AR_SREV_9300_20_OR_LATER(ah)) {
1403 REG_WRITE(ah, AR_WA, ah->WARegVal);
1404 udelay(10);
1405 }
1406
1407 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1408 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1409
1410 if (!ah->reset_power_on)
1411 type = ATH9K_RESET_POWER_ON;
1412
1413 switch (type) {
1414 case ATH9K_RESET_POWER_ON:
1415 ret = ath9k_hw_set_reset_power_on(ah);
1416 if (ret)
1417 ah->reset_power_on = true;
1418 break;
1419 case ATH9K_RESET_WARM:
1420 case ATH9K_RESET_COLD:
1421 ret = ath9k_hw_set_reset(ah, type);
1422 break;
1423 default:
1424 break;
1425 }
1426
1427 return ret;
1428 }
1429
1430 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1431 struct ath9k_channel *chan)
1432 {
1433 int reset_type = ATH9K_RESET_WARM;
1434
1435 if (AR_SREV_9280(ah)) {
1436 if (ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1437 reset_type = ATH9K_RESET_POWER_ON;
1438 else
1439 reset_type = ATH9K_RESET_COLD;
1440 } else if (ah->chip_fullsleep || REG_READ(ah, AR_Q_TXE) ||
1441 (REG_READ(ah, AR_CR) & AR_CR_RXE))
1442 reset_type = ATH9K_RESET_COLD;
1443
1444 if (!ath9k_hw_set_reset_reg(ah, reset_type))
1445 return false;
1446
1447 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1448 return false;
1449
1450 ah->chip_fullsleep = false;
1451
1452 if (AR_SREV_9330(ah))
1453 ar9003_hw_internal_regulator_apply(ah);
1454 ath9k_hw_init_pll(ah, chan);
1455
1456 return true;
1457 }
1458
1459 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1460 struct ath9k_channel *chan)
1461 {
1462 struct ath_common *common = ath9k_hw_common(ah);
1463 struct ath9k_hw_capabilities *pCap = &ah->caps;
1464 bool band_switch = false, mode_diff = false;
1465 u8 ini_reloaded = 0;
1466 u32 qnum;
1467 int r;
1468
1469 if (pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) {
1470 u32 flags_diff = chan->channelFlags ^ ah->curchan->channelFlags;
1471 band_switch = !!(flags_diff & CHANNEL_5GHZ);
1472 mode_diff = !!(flags_diff & ~CHANNEL_HT);
1473 }
1474
1475 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1476 if (ath9k_hw_numtxpending(ah, qnum)) {
1477 ath_dbg(common, QUEUE,
1478 "Transmit frames pending on queue %d\n", qnum);
1479 return false;
1480 }
1481 }
1482
1483 if (!ath9k_hw_rfbus_req(ah)) {
1484 ath_err(common, "Could not kill baseband RX\n");
1485 return false;
1486 }
1487
1488 if (band_switch || mode_diff) {
1489 ath9k_hw_mark_phy_inactive(ah);
1490 udelay(5);
1491
1492 if (band_switch)
1493 ath9k_hw_init_pll(ah, chan);
1494
1495 if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) {
1496 ath_err(common, "Failed to do fast channel change\n");
1497 return false;
1498 }
1499 }
1500
1501 ath9k_hw_set_channel_regs(ah, chan);
1502
1503 r = ath9k_hw_rf_set_freq(ah, chan);
1504 if (r) {
1505 ath_err(common, "Failed to set channel\n");
1506 return false;
1507 }
1508 ath9k_hw_set_clockrate(ah);
1509 ath9k_hw_apply_txpower(ah, chan, false);
1510
1511 ath9k_hw_set_delta_slope(ah, chan);
1512 ath9k_hw_spur_mitigate_freq(ah, chan);
1513
1514 if (band_switch || ini_reloaded)
1515 ah->eep_ops->set_board_values(ah, chan);
1516
1517 ath9k_hw_init_bb(ah, chan);
1518 ath9k_hw_rfbus_done(ah);
1519
1520 if (band_switch || ini_reloaded) {
1521 ah->ah_flags |= AH_FASTCC;
1522 ath9k_hw_init_cal(ah, chan);
1523 ah->ah_flags &= ~AH_FASTCC;
1524 }
1525
1526 return true;
1527 }
1528
1529 static void ath9k_hw_apply_gpio_override(struct ath_hw *ah)
1530 {
1531 u32 gpio_mask = ah->gpio_mask;
1532 int i;
1533
1534 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) {
1535 if (!(gpio_mask & 1))
1536 continue;
1537
1538 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1539 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i)));
1540 }
1541 }
1542
1543 void ath9k_hw_check_nav(struct ath_hw *ah)
1544 {
1545 struct ath_common *common = ath9k_hw_common(ah);
1546 u32 val;
1547
1548 val = REG_READ(ah, AR_NAV);
1549 if (val != 0xdeadbeef && val > 0x7fff) {
1550 ath_dbg(common, BSTUCK, "Abnormal NAV: 0x%x\n", val);
1551 REG_WRITE(ah, AR_NAV, 0);
1552 }
1553 }
1554 EXPORT_SYMBOL(ath9k_hw_check_nav);
1555
1556 bool ath9k_hw_check_alive(struct ath_hw *ah)
1557 {
1558 int count = 50;
1559 u32 reg, last_val;
1560
1561 if (AR_SREV_9300(ah))
1562 return !ath9k_hw_detect_mac_hang(ah);
1563
1564 if (AR_SREV_9285_12_OR_LATER(ah))
1565 return true;
1566
1567 last_val = REG_READ(ah, AR_OBS_BUS_1);
1568 do {
1569 reg = REG_READ(ah, AR_OBS_BUS_1);
1570 if (reg != last_val)
1571 return true;
1572
1573 udelay(1);
1574 last_val = reg;
1575 if ((reg & 0x7E7FFFEF) == 0x00702400)
1576 continue;
1577
1578 switch (reg & 0x7E000B00) {
1579 case 0x1E000000:
1580 case 0x52000B00:
1581 case 0x18000B00:
1582 continue;
1583 default:
1584 return true;
1585 }
1586 } while (count-- > 0);
1587
1588 return false;
1589 }
1590 EXPORT_SYMBOL(ath9k_hw_check_alive);
1591
1592 static void ath9k_hw_init_mfp(struct ath_hw *ah)
1593 {
1594 /* Setup MFP options for CCMP */
1595 if (AR_SREV_9280_20_OR_LATER(ah)) {
1596 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1597 * frames when constructing CCMP AAD. */
1598 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1599 0xc7ff);
1600 if (AR_SREV_9271(ah) || AR_DEVID_7010(ah))
1601 ah->sw_mgmt_crypto_tx = true;
1602 else
1603 ah->sw_mgmt_crypto_tx = false;
1604 ah->sw_mgmt_crypto_rx = false;
1605 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1606 /* Disable hardware crypto for management frames */
1607 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1608 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1609 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1610 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1611 ah->sw_mgmt_crypto_tx = true;
1612 ah->sw_mgmt_crypto_rx = true;
1613 } else {
1614 ah->sw_mgmt_crypto_tx = true;
1615 ah->sw_mgmt_crypto_rx = true;
1616 }
1617 }
1618
1619 static void ath9k_hw_reset_opmode(struct ath_hw *ah,
1620 u32 macStaId1, u32 saveDefAntenna)
1621 {
1622 struct ath_common *common = ath9k_hw_common(ah);
1623
1624 ENABLE_REGWRITE_BUFFER(ah);
1625
1626 REG_RMW(ah, AR_STA_ID1, macStaId1
1627 | AR_STA_ID1_RTS_USE_DEF
1628 | ah->sta_id1_defaults,
1629 ~AR_STA_ID1_SADH_MASK);
1630 ath_hw_setbssidmask(common);
1631 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1632 ath9k_hw_write_associd(ah);
1633 REG_WRITE(ah, AR_ISR, ~0);
1634 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1635
1636 REGWRITE_BUFFER_FLUSH(ah);
1637
1638 ath9k_hw_set_operating_mode(ah, ah->opmode);
1639 }
1640
1641 static void ath9k_hw_init_queues(struct ath_hw *ah)
1642 {
1643 int i;
1644
1645 ENABLE_REGWRITE_BUFFER(ah);
1646
1647 for (i = 0; i < AR_NUM_DCU; i++)
1648 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1649
1650 REGWRITE_BUFFER_FLUSH(ah);
1651
1652 ah->intr_txqs = 0;
1653 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1654 ath9k_hw_resettxqueue(ah, i);
1655 }
1656
1657 /*
1658 * For big endian systems turn on swapping for descriptors
1659 */
1660 static void ath9k_hw_init_desc(struct ath_hw *ah)
1661 {
1662 struct ath_common *common = ath9k_hw_common(ah);
1663
1664 if (AR_SREV_9100(ah)) {
1665 u32 mask;
1666 mask = REG_READ(ah, AR_CFG);
1667 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1668 ath_dbg(common, RESET, "CFG Byte Swap Set 0x%x\n",
1669 mask);
1670 } else {
1671 mask = INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1672 REG_WRITE(ah, AR_CFG, mask);
1673 ath_dbg(common, RESET, "Setting CFG 0x%x\n",
1674 REG_READ(ah, AR_CFG));
1675 }
1676 } else {
1677 if (common->bus_ops->ath_bus_type == ATH_USB) {
1678 /* Configure AR9271 target WLAN */
1679 if (AR_SREV_9271(ah))
1680 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1681 else
1682 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1683 }
1684 #ifdef __BIG_ENDIAN
1685 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah) ||
1686 AR_SREV_9550(ah) || AR_SREV_9531(ah) ||
1687 AR_SREV_9561(ah))
1688 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0);
1689 else
1690 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1691 #endif
1692 }
1693 }
1694
1695 /*
1696 * Fast channel change:
1697 * (Change synthesizer based on channel freq without resetting chip)
1698 */
1699 static int ath9k_hw_do_fastcc(struct ath_hw *ah, struct ath9k_channel *chan)
1700 {
1701 struct ath_common *common = ath9k_hw_common(ah);
1702 struct ath9k_hw_capabilities *pCap = &ah->caps;
1703 int ret;
1704
1705 if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI)
1706 goto fail;
1707
1708 if (ah->chip_fullsleep)
1709 goto fail;
1710
1711 if (!ah->curchan)
1712 goto fail;
1713
1714 if (chan->channel == ah->curchan->channel)
1715 goto fail;
1716
1717 if ((ah->curchan->channelFlags | chan->channelFlags) &
1718 (CHANNEL_HALF | CHANNEL_QUARTER))
1719 goto fail;
1720
1721 /*
1722 * If cross-band fcc is not supoprted, bail out if channelFlags differ.
1723 */
1724 if (!(pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) &&
1725 ((chan->channelFlags ^ ah->curchan->channelFlags) & ~CHANNEL_HT))
1726 goto fail;
1727
1728 if (!ath9k_hw_check_alive(ah))
1729 goto fail;
1730
1731 /*
1732 * For AR9462, make sure that calibration data for
1733 * re-using are present.
1734 */
1735 if (AR_SREV_9462(ah) && (ah->caldata &&
1736 (!test_bit(TXIQCAL_DONE, &ah->caldata->cal_flags) ||
1737 !test_bit(TXCLCAL_DONE, &ah->caldata->cal_flags) ||
1738 !test_bit(RTT_DONE, &ah->caldata->cal_flags))))
1739 goto fail;
1740
1741 ath_dbg(common, RESET, "FastChannelChange for %d -> %d\n",
1742 ah->curchan->channel, chan->channel);
1743
1744 ret = ath9k_hw_channel_change(ah, chan);
1745 if (!ret)
1746 goto fail;
1747
1748 if (ath9k_hw_mci_is_enabled(ah))
1749 ar9003_mci_2g5g_switch(ah, false);
1750
1751 ath9k_hw_loadnf(ah, ah->curchan);
1752 ath9k_hw_start_nfcal(ah, true);
1753
1754 if (AR_SREV_9271(ah))
1755 ar9002_hw_load_ani_reg(ah, chan);
1756
1757 return 0;
1758 fail:
1759 return -EINVAL;
1760 }
1761
1762 u32 ath9k_hw_get_tsf_offset(struct timespec *last, struct timespec *cur)
1763 {
1764 struct timespec ts;
1765 s64 usec;
1766
1767 if (!cur) {
1768 getrawmonotonic(&ts);
1769 cur = &ts;
1770 }
1771
1772 usec = cur->tv_sec * 1000000ULL + cur->tv_nsec / 1000;
1773 usec -= last->tv_sec * 1000000ULL + last->tv_nsec / 1000;
1774
1775 return (u32) usec;
1776 }
1777 EXPORT_SYMBOL(ath9k_hw_get_tsf_offset);
1778
1779 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1780 struct ath9k_hw_cal_data *caldata, bool fastcc)
1781 {
1782 struct ath_common *common = ath9k_hw_common(ah);
1783 u32 saveLedState;
1784 u32 saveDefAntenna;
1785 u32 macStaId1;
1786 u64 tsf = 0;
1787 s64 usec = 0;
1788 int r;
1789 bool start_mci_reset = false;
1790 bool save_fullsleep = ah->chip_fullsleep;
1791
1792 if (ath9k_hw_mci_is_enabled(ah)) {
1793 start_mci_reset = ar9003_mci_start_reset(ah, chan);
1794 if (start_mci_reset)
1795 return 0;
1796 }
1797
1798 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1799 return -EIO;
1800
1801 if (ah->curchan && !ah->chip_fullsleep)
1802 ath9k_hw_getnf(ah, ah->curchan);
1803
1804 ah->caldata = caldata;
1805 if (caldata && (chan->channel != caldata->channel ||
1806 chan->channelFlags != caldata->channelFlags)) {
1807 /* Operating channel changed, reset channel calibration data */
1808 memset(caldata, 0, sizeof(*caldata));
1809 ath9k_init_nfcal_hist_buffer(ah, chan);
1810 } else if (caldata) {
1811 clear_bit(PAPRD_PACKET_SENT, &caldata->cal_flags);
1812 }
1813 ah->noise = ath9k_hw_getchan_noise(ah, chan, chan->noisefloor);
1814
1815 if (fastcc) {
1816 r = ath9k_hw_do_fastcc(ah, chan);
1817 if (!r)
1818 return r;
1819 }
1820
1821 if (ath9k_hw_mci_is_enabled(ah))
1822 ar9003_mci_stop_bt(ah, save_fullsleep);
1823
1824 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1825 if (saveDefAntenna == 0)
1826 saveDefAntenna = 1;
1827
1828 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1829
1830 /* Save TSF before chip reset, a cold reset clears it */
1831 tsf = ath9k_hw_gettsf64(ah);
1832 usec = ktime_to_us(ktime_get_raw());
1833
1834 saveLedState = REG_READ(ah, AR_CFG_LED) &
1835 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1836 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1837
1838 ath9k_hw_mark_phy_inactive(ah);
1839
1840 ah->paprd_table_write_done = false;
1841
1842 /* Only required on the first reset */
1843 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1844 REG_WRITE(ah,
1845 AR9271_RESET_POWER_DOWN_CONTROL,
1846 AR9271_RADIO_RF_RST);
1847 udelay(50);
1848 }
1849
1850 if (!ath9k_hw_chip_reset(ah, chan)) {
1851 ath_err(common, "Chip reset failed\n");
1852 return -EINVAL;
1853 }
1854
1855 /* Only required on the first reset */
1856 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1857 ah->htc_reset_init = false;
1858 REG_WRITE(ah,
1859 AR9271_RESET_POWER_DOWN_CONTROL,
1860 AR9271_GATE_MAC_CTL);
1861 udelay(50);
1862 }
1863
1864 /* Restore TSF */
1865 usec = ktime_to_us(ktime_get_raw()) - usec;
1866 ath9k_hw_settsf64(ah, tsf + usec);
1867
1868 if (AR_SREV_9280_20_OR_LATER(ah))
1869 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1870
1871 if (!AR_SREV_9300_20_OR_LATER(ah))
1872 ar9002_hw_enable_async_fifo(ah);
1873
1874 r = ath9k_hw_process_ini(ah, chan);
1875 if (r)
1876 return r;
1877
1878 ath9k_hw_set_rfmode(ah, chan);
1879
1880 if (ath9k_hw_mci_is_enabled(ah))
1881 ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep);
1882
1883 /*
1884 * Some AR91xx SoC devices frequently fail to accept TSF writes
1885 * right after the chip reset. When that happens, write a new
1886 * value after the initvals have been applied, with an offset
1887 * based on measured time difference
1888 */
1889 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
1890 tsf += 1500;
1891 ath9k_hw_settsf64(ah, tsf);
1892 }
1893
1894 ath9k_hw_init_mfp(ah);
1895
1896 ath9k_hw_set_delta_slope(ah, chan);
1897 ath9k_hw_spur_mitigate_freq(ah, chan);
1898 ah->eep_ops->set_board_values(ah, chan);
1899
1900 ath9k_hw_reset_opmode(ah, macStaId1, saveDefAntenna);
1901
1902 r = ath9k_hw_rf_set_freq(ah, chan);
1903 if (r)
1904 return r;
1905
1906 ath9k_hw_set_clockrate(ah);
1907
1908 ath9k_hw_init_queues(ah);
1909 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
1910 ath9k_hw_ani_cache_ini_regs(ah);
1911 ath9k_hw_init_qos(ah);
1912
1913 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1914 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
1915
1916 ath9k_hw_init_global_settings(ah);
1917
1918 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1919 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
1920 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
1921 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
1922 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
1923 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1924 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
1925 }
1926
1927 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
1928
1929 ath9k_hw_set_dma(ah);
1930
1931 if (!ath9k_hw_mci_is_enabled(ah))
1932 REG_WRITE(ah, AR_OBS, 8);
1933
1934 if (ah->config.rx_intr_mitigation) {
1935 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, ah->config.rimt_last);
1936 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, ah->config.rimt_first);
1937 }
1938
1939 if (ah->config.tx_intr_mitigation) {
1940 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1941 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1942 }
1943
1944 ath9k_hw_init_bb(ah, chan);
1945
1946 if (caldata) {
1947 clear_bit(TXIQCAL_DONE, &caldata->cal_flags);
1948 clear_bit(TXCLCAL_DONE, &caldata->cal_flags);
1949 }
1950 if (!ath9k_hw_init_cal(ah, chan))
1951 return -EIO;
1952
1953 if (ath9k_hw_mci_is_enabled(ah) && ar9003_mci_end_reset(ah, chan, caldata))
1954 return -EIO;
1955
1956 ENABLE_REGWRITE_BUFFER(ah);
1957
1958 ath9k_hw_restore_chainmask(ah);
1959 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1960
1961 REGWRITE_BUFFER_FLUSH(ah);
1962
1963 ath9k_hw_gen_timer_start_tsf2(ah);
1964
1965 ath9k_hw_init_desc(ah);
1966
1967 if (ath9k_hw_btcoex_is_enabled(ah))
1968 ath9k_hw_btcoex_enable(ah);
1969
1970 if (ath9k_hw_mci_is_enabled(ah))
1971 ar9003_mci_check_bt(ah);
1972
1973 if (AR_SREV_9300_20_OR_LATER(ah)) {
1974 ath9k_hw_loadnf(ah, chan);
1975 ath9k_hw_start_nfcal(ah, true);
1976 }
1977
1978 if (AR_SREV_9300_20_OR_LATER(ah))
1979 ar9003_hw_bb_watchdog_config(ah);
1980
1981 if (ah->config.hw_hang_checks & HW_PHYRESTART_CLC_WAR)
1982 ar9003_hw_disable_phy_restart(ah);
1983
1984 ath9k_hw_apply_gpio_override(ah);
1985
1986 if (AR_SREV_9565(ah) && common->bt_ant_diversity)
1987 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, AR_BTCOEX_WL_LNADIV_FORCE_ON);
1988
1989 if (ah->hw->conf.radar_enabled) {
1990 /* set HW specific DFS configuration */
1991 ah->radar_conf.ext_channel = IS_CHAN_HT40(chan);
1992 ath9k_hw_set_radar_params(ah);
1993 }
1994
1995 return 0;
1996 }
1997 EXPORT_SYMBOL(ath9k_hw_reset);
1998
1999 /******************************/
2000 /* Power Management (Chipset) */
2001 /******************************/
2002
2003 /*
2004 * Notify Power Mgt is disabled in self-generated frames.
2005 * If requested, force chip to sleep.
2006 */
2007 static void ath9k_set_power_sleep(struct ath_hw *ah)
2008 {
2009 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2010
2011 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
2012 REG_CLR_BIT(ah, AR_TIMER_MODE, 0xff);
2013 REG_CLR_BIT(ah, AR_NDP2_TIMER_MODE, 0xff);
2014 REG_CLR_BIT(ah, AR_SLP32_INC, 0xfffff);
2015 /* xxx Required for WLAN only case ? */
2016 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0);
2017 udelay(100);
2018 }
2019
2020 /*
2021 * Clear the RTC force wake bit to allow the
2022 * mac to go to sleep.
2023 */
2024 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
2025
2026 if (ath9k_hw_mci_is_enabled(ah))
2027 udelay(100);
2028
2029 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
2030 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2031
2032 /* Shutdown chip. Active low */
2033 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) {
2034 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN);
2035 udelay(2);
2036 }
2037
2038 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
2039 if (AR_SREV_9300_20_OR_LATER(ah))
2040 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
2041 }
2042
2043 /*
2044 * Notify Power Management is enabled in self-generating
2045 * frames. If request, set power mode of chip to
2046 * auto/normal. Duration in units of 128us (1/8 TU).
2047 */
2048 static void ath9k_set_power_network_sleep(struct ath_hw *ah)
2049 {
2050 struct ath9k_hw_capabilities *pCap = &ah->caps;
2051
2052 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2053
2054 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2055 /* Set WakeOnInterrupt bit; clear ForceWake bit */
2056 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2057 AR_RTC_FORCE_WAKE_ON_INT);
2058 } else {
2059
2060 /* When chip goes into network sleep, it could be waken
2061 * up by MCI_INT interrupt caused by BT's HW messages
2062 * (LNA_xxx, CONT_xxx) which chould be in a very fast
2063 * rate (~100us). This will cause chip to leave and
2064 * re-enter network sleep mode frequently, which in
2065 * consequence will have WLAN MCI HW to generate lots of
2066 * SYS_WAKING and SYS_SLEEPING messages which will make
2067 * BT CPU to busy to process.
2068 */
2069 if (ath9k_hw_mci_is_enabled(ah))
2070 REG_CLR_BIT(ah, AR_MCI_INTERRUPT_RX_MSG_EN,
2071 AR_MCI_INTERRUPT_RX_HW_MSG_MASK);
2072 /*
2073 * Clear the RTC force wake bit to allow the
2074 * mac to go to sleep.
2075 */
2076 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
2077
2078 if (ath9k_hw_mci_is_enabled(ah))
2079 udelay(30);
2080 }
2081
2082 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
2083 if (AR_SREV_9300_20_OR_LATER(ah))
2084 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
2085 }
2086
2087 static bool ath9k_hw_set_power_awake(struct ath_hw *ah)
2088 {
2089 u32 val;
2090 int i;
2091
2092 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */
2093 if (AR_SREV_9300_20_OR_LATER(ah)) {
2094 REG_WRITE(ah, AR_WA, ah->WARegVal);
2095 udelay(10);
2096 }
2097
2098 if ((REG_READ(ah, AR_RTC_STATUS) &
2099 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2100 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
2101 return false;
2102 }
2103 if (!AR_SREV_9300_20_OR_LATER(ah))
2104 ath9k_hw_init_pll(ah, NULL);
2105 }
2106 if (AR_SREV_9100(ah))
2107 REG_SET_BIT(ah, AR_RTC_RESET,
2108 AR_RTC_RESET_EN);
2109
2110 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2111 AR_RTC_FORCE_WAKE_EN);
2112 if (AR_SREV_9100(ah))
2113 mdelay(10);
2114 else
2115 udelay(50);
2116
2117 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2118 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2119 if (val == AR_RTC_STATUS_ON)
2120 break;
2121 udelay(50);
2122 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2123 AR_RTC_FORCE_WAKE_EN);
2124 }
2125 if (i == 0) {
2126 ath_err(ath9k_hw_common(ah),
2127 "Failed to wakeup in %uus\n",
2128 POWER_UP_TIME / 20);
2129 return false;
2130 }
2131
2132 if (ath9k_hw_mci_is_enabled(ah))
2133 ar9003_mci_set_power_awake(ah);
2134
2135 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2136
2137 return true;
2138 }
2139
2140 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2141 {
2142 struct ath_common *common = ath9k_hw_common(ah);
2143 int status = true;
2144 static const char *modes[] = {
2145 "AWAKE",
2146 "FULL-SLEEP",
2147 "NETWORK SLEEP",
2148 "UNDEFINED"
2149 };
2150
2151 if (ah->power_mode == mode)
2152 return status;
2153
2154 ath_dbg(common, RESET, "%s -> %s\n",
2155 modes[ah->power_mode], modes[mode]);
2156
2157 switch (mode) {
2158 case ATH9K_PM_AWAKE:
2159 status = ath9k_hw_set_power_awake(ah);
2160 break;
2161 case ATH9K_PM_FULL_SLEEP:
2162 if (ath9k_hw_mci_is_enabled(ah))
2163 ar9003_mci_set_full_sleep(ah);
2164
2165 ath9k_set_power_sleep(ah);
2166 ah->chip_fullsleep = true;
2167 break;
2168 case ATH9K_PM_NETWORK_SLEEP:
2169 ath9k_set_power_network_sleep(ah);
2170 break;
2171 default:
2172 ath_err(common, "Unknown power mode %u\n", mode);
2173 return false;
2174 }
2175 ah->power_mode = mode;
2176
2177 /*
2178 * XXX: If this warning never comes up after a while then
2179 * simply keep the ATH_DBG_WARN_ON_ONCE() but make
2180 * ath9k_hw_setpower() return type void.
2181 */
2182
2183 if (!(ah->ah_flags & AH_UNPLUGGED))
2184 ATH_DBG_WARN_ON_ONCE(!status);
2185
2186 return status;
2187 }
2188 EXPORT_SYMBOL(ath9k_hw_setpower);
2189
2190 /*******************/
2191 /* Beacon Handling */
2192 /*******************/
2193
2194 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
2195 {
2196 int flags = 0;
2197
2198 ENABLE_REGWRITE_BUFFER(ah);
2199
2200 switch (ah->opmode) {
2201 case NL80211_IFTYPE_ADHOC:
2202 REG_SET_BIT(ah, AR_TXCFG,
2203 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
2204 case NL80211_IFTYPE_MESH_POINT:
2205 case NL80211_IFTYPE_AP:
2206 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon);
2207 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon -
2208 TU_TO_USEC(ah->config.dma_beacon_response_time));
2209 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon -
2210 TU_TO_USEC(ah->config.sw_beacon_response_time));
2211 flags |=
2212 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
2213 break;
2214 default:
2215 ath_dbg(ath9k_hw_common(ah), BEACON,
2216 "%s: unsupported opmode: %d\n", __func__, ah->opmode);
2217 return;
2218 break;
2219 }
2220
2221 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period);
2222 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period);
2223 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period);
2224
2225 REGWRITE_BUFFER_FLUSH(ah);
2226
2227 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
2228 }
2229 EXPORT_SYMBOL(ath9k_hw_beaconinit);
2230
2231 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
2232 const struct ath9k_beacon_state *bs)
2233 {
2234 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
2235 struct ath9k_hw_capabilities *pCap = &ah->caps;
2236 struct ath_common *common = ath9k_hw_common(ah);
2237
2238 ENABLE_REGWRITE_BUFFER(ah);
2239
2240 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, bs->bs_nexttbtt);
2241 REG_WRITE(ah, AR_BEACON_PERIOD, bs->bs_intval);
2242 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, bs->bs_intval);
2243
2244 REGWRITE_BUFFER_FLUSH(ah);
2245
2246 REG_RMW_FIELD(ah, AR_RSSI_THR,
2247 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
2248
2249 beaconintval = bs->bs_intval;
2250
2251 if (bs->bs_sleepduration > beaconintval)
2252 beaconintval = bs->bs_sleepduration;
2253
2254 dtimperiod = bs->bs_dtimperiod;
2255 if (bs->bs_sleepduration > dtimperiod)
2256 dtimperiod = bs->bs_sleepduration;
2257
2258 if (beaconintval == dtimperiod)
2259 nextTbtt = bs->bs_nextdtim;
2260 else
2261 nextTbtt = bs->bs_nexttbtt;
2262
2263 ath_dbg(common, BEACON, "next DTIM %d\n", bs->bs_nextdtim);
2264 ath_dbg(common, BEACON, "next beacon %d\n", nextTbtt);
2265 ath_dbg(common, BEACON, "beacon period %d\n", beaconintval);
2266 ath_dbg(common, BEACON, "DTIM period %d\n", dtimperiod);
2267
2268 ENABLE_REGWRITE_BUFFER(ah);
2269
2270 REG_WRITE(ah, AR_NEXT_DTIM, bs->bs_nextdtim - SLEEP_SLOP);
2271 REG_WRITE(ah, AR_NEXT_TIM, nextTbtt - SLEEP_SLOP);
2272
2273 REG_WRITE(ah, AR_SLEEP1,
2274 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
2275 | AR_SLEEP1_ASSUME_DTIM);
2276
2277 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
2278 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
2279 else
2280 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
2281
2282 REG_WRITE(ah, AR_SLEEP2,
2283 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
2284
2285 REG_WRITE(ah, AR_TIM_PERIOD, beaconintval);
2286 REG_WRITE(ah, AR_DTIM_PERIOD, dtimperiod);
2287
2288 REGWRITE_BUFFER_FLUSH(ah);
2289
2290 REG_SET_BIT(ah, AR_TIMER_MODE,
2291 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
2292 AR_DTIM_TIMER_EN);
2293
2294 /* TSF Out of Range Threshold */
2295 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
2296 }
2297 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
2298
2299 /*******************/
2300 /* HW Capabilities */
2301 /*******************/
2302
2303 static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask)
2304 {
2305 eeprom_chainmask &= chip_chainmask;
2306 if (eeprom_chainmask)
2307 return eeprom_chainmask;
2308 else
2309 return chip_chainmask;
2310 }
2311
2312 /**
2313 * ath9k_hw_dfs_tested - checks if DFS has been tested with used chipset
2314 * @ah: the atheros hardware data structure
2315 *
2316 * We enable DFS support upstream on chipsets which have passed a series
2317 * of tests. The testing requirements are going to be documented. Desired
2318 * test requirements are documented at:
2319 *
2320 * http://wireless.kernel.org/en/users/Drivers/ath9k/dfs
2321 *
2322 * Once a new chipset gets properly tested an individual commit can be used
2323 * to document the testing for DFS for that chipset.
2324 */
2325 static bool ath9k_hw_dfs_tested(struct ath_hw *ah)
2326 {
2327
2328 switch (ah->hw_version.macVersion) {
2329 /* for temporary testing DFS with 9280 */
2330 case AR_SREV_VERSION_9280:
2331 /* AR9580 will likely be our first target to get testing on */
2332 case AR_SREV_VERSION_9580:
2333 return true;
2334 default:
2335 return false;
2336 }
2337 }
2338
2339 int ath9k_hw_fill_cap_info(struct ath_hw *ah)
2340 {
2341 struct ath9k_hw_capabilities *pCap = &ah->caps;
2342 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2343 struct ath_common *common = ath9k_hw_common(ah);
2344
2345 u16 eeval;
2346 u8 ant_div_ctl1, tx_chainmask, rx_chainmask;
2347
2348 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
2349 regulatory->current_rd = eeval;
2350
2351 if (ah->opmode != NL80211_IFTYPE_AP &&
2352 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
2353 if (regulatory->current_rd == 0x64 ||
2354 regulatory->current_rd == 0x65)
2355 regulatory->current_rd += 5;
2356 else if (regulatory->current_rd == 0x41)
2357 regulatory->current_rd = 0x43;
2358 ath_dbg(common, REGULATORY, "regdomain mapped to 0x%x\n",
2359 regulatory->current_rd);
2360 }
2361
2362 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
2363
2364 if (eeval & AR5416_OPFLAGS_11A) {
2365 if (ah->disable_5ghz)
2366 ath_warn(common, "disabling 5GHz band\n");
2367 else
2368 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
2369 }
2370
2371 if (eeval & AR5416_OPFLAGS_11G) {
2372 if (ah->disable_2ghz)
2373 ath_warn(common, "disabling 2GHz band\n");
2374 else
2375 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
2376 }
2377
2378 if ((pCap->hw_caps & (ATH9K_HW_CAP_2GHZ | ATH9K_HW_CAP_5GHZ)) == 0) {
2379 ath_err(common, "both bands are disabled\n");
2380 return -EINVAL;
2381 }
2382
2383 if (AR_SREV_9485(ah) ||
2384 AR_SREV_9285(ah) ||
2385 AR_SREV_9330(ah) ||
2386 AR_SREV_9565(ah))
2387 pCap->chip_chainmask = 1;
2388 else if (!AR_SREV_9280_20_OR_LATER(ah))
2389 pCap->chip_chainmask = 7;
2390 else if (!AR_SREV_9300_20_OR_LATER(ah) ||
2391 AR_SREV_9340(ah) ||
2392 AR_SREV_9462(ah) ||
2393 AR_SREV_9531(ah))
2394 pCap->chip_chainmask = 3;
2395 else
2396 pCap->chip_chainmask = 7;
2397
2398 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
2399 /*
2400 * For AR9271 we will temporarilly uses the rx chainmax as read from
2401 * the EEPROM.
2402 */
2403 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
2404 !(eeval & AR5416_OPFLAGS_11A) &&
2405 !(AR_SREV_9271(ah)))
2406 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
2407 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
2408 else if (AR_SREV_9100(ah))
2409 pCap->rx_chainmask = 0x7;
2410 else
2411 /* Use rx_chainmask from EEPROM. */
2412 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
2413
2414 pCap->tx_chainmask = fixup_chainmask(pCap->chip_chainmask, pCap->tx_chainmask);
2415 pCap->rx_chainmask = fixup_chainmask(pCap->chip_chainmask, pCap->rx_chainmask);
2416 ah->txchainmask = pCap->tx_chainmask;
2417 ah->rxchainmask = pCap->rx_chainmask;
2418
2419 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
2420
2421 /* enable key search for every frame in an aggregate */
2422 if (AR_SREV_9300_20_OR_LATER(ah))
2423 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
2424
2425 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
2426
2427 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
2428 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2429 else
2430 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
2431
2432 if (AR_SREV_9271(ah))
2433 pCap->num_gpio_pins = AR9271_NUM_GPIO;
2434 else if (AR_DEVID_7010(ah))
2435 pCap->num_gpio_pins = AR7010_NUM_GPIO;
2436 else if (AR_SREV_9300_20_OR_LATER(ah))
2437 pCap->num_gpio_pins = AR9300_NUM_GPIO;
2438 else if (AR_SREV_9287_11_OR_LATER(ah))
2439 pCap->num_gpio_pins = AR9287_NUM_GPIO;
2440 else if (AR_SREV_9285_12_OR_LATER(ah))
2441 pCap->num_gpio_pins = AR9285_NUM_GPIO;
2442 else if (AR_SREV_9280_20_OR_LATER(ah))
2443 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2444 else
2445 pCap->num_gpio_pins = AR_NUM_GPIO;
2446
2447 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah))
2448 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
2449 else
2450 pCap->rts_aggr_limit = (8 * 1024);
2451
2452 #ifdef CONFIG_ATH9K_RFKILL
2453 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2454 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2455 ah->rfkill_gpio =
2456 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2457 ah->rfkill_polarity =
2458 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
2459
2460 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
2461 }
2462 #endif
2463 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
2464 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2465 else
2466 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
2467
2468 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
2469 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2470 else
2471 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
2472
2473 if (AR_SREV_9300_20_OR_LATER(ah)) {
2474 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
2475 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah) &&
2476 !AR_SREV_9561(ah) && !AR_SREV_9565(ah))
2477 pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
2478
2479 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2480 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2481 pCap->rx_status_len = sizeof(struct ar9003_rxs);
2482 pCap->tx_desc_len = sizeof(struct ar9003_txc);
2483 pCap->txs_len = sizeof(struct ar9003_txs);
2484 } else {
2485 pCap->tx_desc_len = sizeof(struct ath_desc);
2486 if (AR_SREV_9280_20(ah))
2487 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
2488 }
2489
2490 if (AR_SREV_9300_20_OR_LATER(ah))
2491 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2492
2493 if (AR_SREV_9561(ah))
2494 ah->ent_mode = 0x3BDA000;
2495 else if (AR_SREV_9300_20_OR_LATER(ah))
2496 ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
2497
2498 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
2499 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
2500
2501 if (AR_SREV_9285(ah)) {
2502 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
2503 ant_div_ctl1 =
2504 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2505 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1)) {
2506 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2507 ath_info(common, "Enable LNA combining\n");
2508 }
2509 }
2510 }
2511
2512 if (AR_SREV_9300_20_OR_LATER(ah)) {
2513 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
2514 pCap->hw_caps |= ATH9K_HW_CAP_APM;
2515 }
2516
2517 if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
2518 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2519 if ((ant_div_ctl1 >> 0x6) == 0x3) {
2520 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2521 ath_info(common, "Enable LNA combining\n");
2522 }
2523 }
2524
2525 if (ath9k_hw_dfs_tested(ah))
2526 pCap->hw_caps |= ATH9K_HW_CAP_DFS;
2527
2528 tx_chainmask = pCap->tx_chainmask;
2529 rx_chainmask = pCap->rx_chainmask;
2530 while (tx_chainmask || rx_chainmask) {
2531 if (tx_chainmask & BIT(0))
2532 pCap->max_txchains++;
2533 if (rx_chainmask & BIT(0))
2534 pCap->max_rxchains++;
2535
2536 tx_chainmask >>= 1;
2537 rx_chainmask >>= 1;
2538 }
2539
2540 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
2541 if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE))
2542 pCap->hw_caps |= ATH9K_HW_CAP_MCI;
2543
2544 if (AR_SREV_9462_20_OR_LATER(ah))
2545 pCap->hw_caps |= ATH9K_HW_CAP_RTT;
2546 }
2547
2548 if (AR_SREV_9462(ah))
2549 pCap->hw_caps |= ATH9K_HW_WOW_DEVICE_CAPABLE;
2550
2551 if (AR_SREV_9300_20_OR_LATER(ah) &&
2552 ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
2553 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
2554
2555 return 0;
2556 }
2557
2558 /****************************/
2559 /* GPIO / RFKILL / Antennae */
2560 /****************************/
2561
2562 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
2563 u32 gpio, u32 type)
2564 {
2565 int addr;
2566 u32 gpio_shift, tmp;
2567
2568 if (gpio > 11)
2569 addr = AR_GPIO_OUTPUT_MUX3;
2570 else if (gpio > 5)
2571 addr = AR_GPIO_OUTPUT_MUX2;
2572 else
2573 addr = AR_GPIO_OUTPUT_MUX1;
2574
2575 gpio_shift = (gpio % 6) * 5;
2576
2577 if (AR_SREV_9280_20_OR_LATER(ah)
2578 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2579 REG_RMW(ah, addr, (type << gpio_shift),
2580 (0x1f << gpio_shift));
2581 } else {
2582 tmp = REG_READ(ah, addr);
2583 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2584 tmp &= ~(0x1f << gpio_shift);
2585 tmp |= (type << gpio_shift);
2586 REG_WRITE(ah, addr, tmp);
2587 }
2588 }
2589
2590 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
2591 {
2592 u32 gpio_shift;
2593
2594 BUG_ON(gpio >= ah->caps.num_gpio_pins);
2595
2596 if (AR_DEVID_7010(ah)) {
2597 gpio_shift = gpio;
2598 REG_RMW(ah, AR7010_GPIO_OE,
2599 (AR7010_GPIO_OE_AS_INPUT << gpio_shift),
2600 (AR7010_GPIO_OE_MASK << gpio_shift));
2601 return;
2602 }
2603
2604 gpio_shift = gpio << 1;
2605 REG_RMW(ah,
2606 AR_GPIO_OE_OUT,
2607 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2608 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2609 }
2610 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
2611
2612 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
2613 {
2614 #define MS_REG_READ(x, y) \
2615 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2616
2617 if (gpio >= ah->caps.num_gpio_pins)
2618 return 0xffffffff;
2619
2620 if (AR_DEVID_7010(ah)) {
2621 u32 val;
2622 val = REG_READ(ah, AR7010_GPIO_IN);
2623 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0;
2624 } else if (AR_SREV_9300_20_OR_LATER(ah))
2625 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) &
2626 AR_GPIO_BIT(gpio)) != 0;
2627 else if (AR_SREV_9271(ah))
2628 return MS_REG_READ(AR9271, gpio) != 0;
2629 else if (AR_SREV_9287_11_OR_LATER(ah))
2630 return MS_REG_READ(AR9287, gpio) != 0;
2631 else if (AR_SREV_9285_12_OR_LATER(ah))
2632 return MS_REG_READ(AR9285, gpio) != 0;
2633 else if (AR_SREV_9280_20_OR_LATER(ah))
2634 return MS_REG_READ(AR928X, gpio) != 0;
2635 else
2636 return MS_REG_READ(AR, gpio) != 0;
2637 }
2638 EXPORT_SYMBOL(ath9k_hw_gpio_get);
2639
2640 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
2641 u32 ah_signal_type)
2642 {
2643 u32 gpio_shift;
2644
2645 if (AR_DEVID_7010(ah)) {
2646 gpio_shift = gpio;
2647 REG_RMW(ah, AR7010_GPIO_OE,
2648 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift),
2649 (AR7010_GPIO_OE_MASK << gpio_shift));
2650 return;
2651 }
2652
2653 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
2654 gpio_shift = 2 * gpio;
2655 REG_RMW(ah,
2656 AR_GPIO_OE_OUT,
2657 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2658 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2659 }
2660 EXPORT_SYMBOL(ath9k_hw_cfg_output);
2661
2662 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
2663 {
2664 if (AR_DEVID_7010(ah)) {
2665 val = val ? 0 : 1;
2666 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio),
2667 AR_GPIO_BIT(gpio));
2668 return;
2669 }
2670
2671 if (AR_SREV_9271(ah))
2672 val = ~val;
2673
2674 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2675 AR_GPIO_BIT(gpio));
2676 }
2677 EXPORT_SYMBOL(ath9k_hw_set_gpio);
2678
2679 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
2680 {
2681 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
2682 }
2683 EXPORT_SYMBOL(ath9k_hw_setantenna);
2684
2685 /*********************/
2686 /* General Operation */
2687 /*********************/
2688
2689 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
2690 {
2691 u32 bits = REG_READ(ah, AR_RX_FILTER);
2692 u32 phybits = REG_READ(ah, AR_PHY_ERR);
2693
2694 if (phybits & AR_PHY_ERR_RADAR)
2695 bits |= ATH9K_RX_FILTER_PHYRADAR;
2696 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2697 bits |= ATH9K_RX_FILTER_PHYERR;
2698
2699 return bits;
2700 }
2701 EXPORT_SYMBOL(ath9k_hw_getrxfilter);
2702
2703 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
2704 {
2705 u32 phybits;
2706
2707 ENABLE_REGWRITE_BUFFER(ah);
2708
2709 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
2710 bits |= ATH9K_RX_FILTER_CONTROL_WRAPPER;
2711
2712 REG_WRITE(ah, AR_RX_FILTER, bits);
2713
2714 phybits = 0;
2715 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2716 phybits |= AR_PHY_ERR_RADAR;
2717 if (bits & ATH9K_RX_FILTER_PHYERR)
2718 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2719 REG_WRITE(ah, AR_PHY_ERR, phybits);
2720
2721 if (phybits)
2722 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
2723 else
2724 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
2725
2726 REGWRITE_BUFFER_FLUSH(ah);
2727 }
2728 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
2729
2730 bool ath9k_hw_phy_disable(struct ath_hw *ah)
2731 {
2732 if (ath9k_hw_mci_is_enabled(ah))
2733 ar9003_mci_bt_gain_ctrl(ah);
2734
2735 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2736 return false;
2737
2738 ath9k_hw_init_pll(ah, NULL);
2739 ah->htc_reset_init = true;
2740 return true;
2741 }
2742 EXPORT_SYMBOL(ath9k_hw_phy_disable);
2743
2744 bool ath9k_hw_disable(struct ath_hw *ah)
2745 {
2746 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2747 return false;
2748
2749 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2750 return false;
2751
2752 ath9k_hw_init_pll(ah, NULL);
2753 return true;
2754 }
2755 EXPORT_SYMBOL(ath9k_hw_disable);
2756
2757 static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan)
2758 {
2759 enum eeprom_param gain_param;
2760
2761 if (IS_CHAN_2GHZ(chan))
2762 gain_param = EEP_ANTENNA_GAIN_2G;
2763 else
2764 gain_param = EEP_ANTENNA_GAIN_5G;
2765
2766 return ah->eep_ops->get_eeprom(ah, gain_param);
2767 }
2768
2769 void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan,
2770 bool test)
2771 {
2772 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2773 struct ieee80211_channel *channel;
2774 int chan_pwr, new_pwr, max_gain;
2775 int ant_gain, ant_reduction = 0;
2776
2777 if (!chan)
2778 return;
2779
2780 channel = chan->chan;
2781 chan_pwr = min_t(int, channel->max_power * 2, MAX_RATE_POWER);
2782 new_pwr = min_t(int, chan_pwr, reg->power_limit);
2783 max_gain = chan_pwr - new_pwr + channel->max_antenna_gain * 2;
2784
2785 ant_gain = get_antenna_gain(ah, chan);
2786 if (ant_gain > max_gain)
2787 ant_reduction = ant_gain - max_gain;
2788
2789 ah->eep_ops->set_txpower(ah, chan,
2790 ath9k_regd_get_ctl(reg, chan),
2791 ant_reduction, new_pwr, test);
2792 }
2793
2794 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
2795 {
2796 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2797 struct ath9k_channel *chan = ah->curchan;
2798 struct ieee80211_channel *channel = chan->chan;
2799
2800 reg->power_limit = min_t(u32, limit, MAX_RATE_POWER);
2801 if (test)
2802 channel->max_power = MAX_RATE_POWER / 2;
2803
2804 ath9k_hw_apply_txpower(ah, chan, test);
2805
2806 if (test)
2807 channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2);
2808 }
2809 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
2810
2811 void ath9k_hw_setopmode(struct ath_hw *ah)
2812 {
2813 ath9k_hw_set_operating_mode(ah, ah->opmode);
2814 }
2815 EXPORT_SYMBOL(ath9k_hw_setopmode);
2816
2817 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
2818 {
2819 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2820 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
2821 }
2822 EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
2823
2824 void ath9k_hw_write_associd(struct ath_hw *ah)
2825 {
2826 struct ath_common *common = ath9k_hw_common(ah);
2827
2828 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2829 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2830 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2831 }
2832 EXPORT_SYMBOL(ath9k_hw_write_associd);
2833
2834 #define ATH9K_MAX_TSF_READ 10
2835
2836 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
2837 {
2838 u32 tsf_lower, tsf_upper1, tsf_upper2;
2839 int i;
2840
2841 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2842 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2843 tsf_lower = REG_READ(ah, AR_TSF_L32);
2844 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2845 if (tsf_upper2 == tsf_upper1)
2846 break;
2847 tsf_upper1 = tsf_upper2;
2848 }
2849
2850 WARN_ON( i == ATH9K_MAX_TSF_READ );
2851
2852 return (((u64)tsf_upper1 << 32) | tsf_lower);
2853 }
2854 EXPORT_SYMBOL(ath9k_hw_gettsf64);
2855
2856 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
2857 {
2858 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
2859 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
2860 }
2861 EXPORT_SYMBOL(ath9k_hw_settsf64);
2862
2863 void ath9k_hw_reset_tsf(struct ath_hw *ah)
2864 {
2865 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2866 AH_TSF_WRITE_TIMEOUT))
2867 ath_dbg(ath9k_hw_common(ah), RESET,
2868 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
2869
2870 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2871 }
2872 EXPORT_SYMBOL(ath9k_hw_reset_tsf);
2873
2874 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set)
2875 {
2876 if (set)
2877 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
2878 else
2879 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
2880 }
2881 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
2882
2883 void ath9k_hw_set11nmac2040(struct ath_hw *ah, struct ath9k_channel *chan)
2884 {
2885 u32 macmode;
2886
2887 if (IS_CHAN_HT40(chan) && !ah->config.cwm_ignore_extcca)
2888 macmode = AR_2040_JOINED_RX_CLEAR;
2889 else
2890 macmode = 0;
2891
2892 REG_WRITE(ah, AR_2040_MODE, macmode);
2893 }
2894
2895 /* HW Generic timers configuration */
2896
2897 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2898 {
2899 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2900 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2901 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2902 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2903 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2904 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2905 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2906 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2907 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2908 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2909 AR_NDP2_TIMER_MODE, 0x0002},
2910 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2911 AR_NDP2_TIMER_MODE, 0x0004},
2912 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2913 AR_NDP2_TIMER_MODE, 0x0008},
2914 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2915 AR_NDP2_TIMER_MODE, 0x0010},
2916 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2917 AR_NDP2_TIMER_MODE, 0x0020},
2918 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2919 AR_NDP2_TIMER_MODE, 0x0040},
2920 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2921 AR_NDP2_TIMER_MODE, 0x0080}
2922 };
2923
2924 /* HW generic timer primitives */
2925
2926 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
2927 {
2928 return REG_READ(ah, AR_TSF_L32);
2929 }
2930 EXPORT_SYMBOL(ath9k_hw_gettsf32);
2931
2932 void ath9k_hw_gen_timer_start_tsf2(struct ath_hw *ah)
2933 {
2934 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2935
2936 if (timer_table->tsf2_enabled) {
2937 REG_SET_BIT(ah, AR_DIRECT_CONNECT, AR_DC_AP_STA_EN);
2938 REG_SET_BIT(ah, AR_RESET_TSF, AR_RESET_TSF2_ONCE);
2939 }
2940 }
2941
2942 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2943 void (*trigger)(void *),
2944 void (*overflow)(void *),
2945 void *arg,
2946 u8 timer_index)
2947 {
2948 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2949 struct ath_gen_timer *timer;
2950
2951 if ((timer_index < AR_FIRST_NDP_TIMER) ||
2952 (timer_index >= ATH_MAX_GEN_TIMER))
2953 return NULL;
2954
2955 if ((timer_index > AR_FIRST_NDP_TIMER) &&
2956 !AR_SREV_9300_20_OR_LATER(ah))
2957 return NULL;
2958
2959 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
2960 if (timer == NULL)
2961 return NULL;
2962
2963 /* allocate a hardware generic timer slot */
2964 timer_table->timers[timer_index] = timer;
2965 timer->index = timer_index;
2966 timer->trigger = trigger;
2967 timer->overflow = overflow;
2968 timer->arg = arg;
2969
2970 if ((timer_index > AR_FIRST_NDP_TIMER) && !timer_table->tsf2_enabled) {
2971 timer_table->tsf2_enabled = true;
2972 ath9k_hw_gen_timer_start_tsf2(ah);
2973 }
2974
2975 return timer;
2976 }
2977 EXPORT_SYMBOL(ath_gen_timer_alloc);
2978
2979 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2980 struct ath_gen_timer *timer,
2981 u32 timer_next,
2982 u32 timer_period)
2983 {
2984 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2985 u32 mask = 0;
2986
2987 timer_table->timer_mask |= BIT(timer->index);
2988
2989 /*
2990 * Program generic timer registers
2991 */
2992 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
2993 timer_next);
2994 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
2995 timer_period);
2996 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2997 gen_tmr_configuration[timer->index].mode_mask);
2998
2999 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
3000 /*
3001 * Starting from AR9462, each generic timer can select which tsf
3002 * to use. But we still follow the old rule, 0 - 7 use tsf and
3003 * 8 - 15 use tsf2.
3004 */
3005 if ((timer->index < AR_GEN_TIMER_BANK_1_LEN))
3006 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3007 (1 << timer->index));
3008 else
3009 REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3010 (1 << timer->index));
3011 }
3012
3013 if (timer->trigger)
3014 mask |= SM(AR_GENTMR_BIT(timer->index),
3015 AR_IMR_S5_GENTIMER_TRIG);
3016 if (timer->overflow)
3017 mask |= SM(AR_GENTMR_BIT(timer->index),
3018 AR_IMR_S5_GENTIMER_THRESH);
3019
3020 REG_SET_BIT(ah, AR_IMR_S5, mask);
3021
3022 if ((ah->imask & ATH9K_INT_GENTIMER) == 0) {
3023 ah->imask |= ATH9K_INT_GENTIMER;
3024 ath9k_hw_set_interrupts(ah);
3025 }
3026 }
3027 EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
3028
3029 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
3030 {
3031 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3032
3033 /* Clear generic timer enable bits. */
3034 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3035 gen_tmr_configuration[timer->index].mode_mask);
3036
3037 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
3038 /*
3039 * Need to switch back to TSF if it was using TSF2.
3040 */
3041 if ((timer->index >= AR_GEN_TIMER_BANK_1_LEN)) {
3042 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3043 (1 << timer->index));
3044 }
3045 }
3046
3047 /* Disable both trigger and thresh interrupt masks */
3048 REG_CLR_BIT(ah, AR_IMR_S5,
3049 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3050 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3051
3052 timer_table->timer_mask &= ~BIT(timer->index);
3053
3054 if (timer_table->timer_mask == 0) {
3055 ah->imask &= ~ATH9K_INT_GENTIMER;
3056 ath9k_hw_set_interrupts(ah);
3057 }
3058 }
3059 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
3060
3061 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
3062 {
3063 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3064
3065 /* free the hardware generic timer slot */
3066 timer_table->timers[timer->index] = NULL;
3067 kfree(timer);
3068 }
3069 EXPORT_SYMBOL(ath_gen_timer_free);
3070
3071 /*
3072 * Generic Timer Interrupts handling
3073 */
3074 void ath_gen_timer_isr(struct ath_hw *ah)
3075 {
3076 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3077 struct ath_gen_timer *timer;
3078 unsigned long trigger_mask, thresh_mask;
3079 unsigned int index;
3080
3081 /* get hardware generic timer interrupt status */
3082 trigger_mask = ah->intr_gen_timer_trigger;
3083 thresh_mask = ah->intr_gen_timer_thresh;
3084 trigger_mask &= timer_table->timer_mask;
3085 thresh_mask &= timer_table->timer_mask;
3086
3087 for_each_set_bit(index, &thresh_mask, ARRAY_SIZE(timer_table->timers)) {
3088 timer = timer_table->timers[index];
3089 if (!timer)
3090 continue;
3091 if (!timer->overflow)
3092 continue;
3093
3094 trigger_mask &= ~BIT(index);
3095 timer->overflow(timer->arg);
3096 }
3097
3098 for_each_set_bit(index, &trigger_mask, ARRAY_SIZE(timer_table->timers)) {
3099 timer = timer_table->timers[index];
3100 if (!timer)
3101 continue;
3102 if (!timer->trigger)
3103 continue;
3104 timer->trigger(timer->arg);
3105 }
3106 }
3107 EXPORT_SYMBOL(ath_gen_timer_isr);
3108
3109 /********/
3110 /* HTC */
3111 /********/
3112
3113 static struct {
3114 u32 version;
3115 const char * name;
3116 } ath_mac_bb_names[] = {
3117 /* Devices with external radios */
3118 { AR_SREV_VERSION_5416_PCI, "5416" },
3119 { AR_SREV_VERSION_5416_PCIE, "5418" },
3120 { AR_SREV_VERSION_9100, "9100" },
3121 { AR_SREV_VERSION_9160, "9160" },
3122 /* Single-chip solutions */
3123 { AR_SREV_VERSION_9280, "9280" },
3124 { AR_SREV_VERSION_9285, "9285" },
3125 { AR_SREV_VERSION_9287, "9287" },
3126 { AR_SREV_VERSION_9271, "9271" },
3127 { AR_SREV_VERSION_9300, "9300" },
3128 { AR_SREV_VERSION_9330, "9330" },
3129 { AR_SREV_VERSION_9340, "9340" },
3130 { AR_SREV_VERSION_9485, "9485" },
3131 { AR_SREV_VERSION_9462, "9462" },
3132 { AR_SREV_VERSION_9550, "9550" },
3133 { AR_SREV_VERSION_9565, "9565" },
3134 { AR_SREV_VERSION_9531, "9531" },
3135 };
3136
3137 /* For devices with external radios */
3138 static struct {
3139 u16 version;
3140 const char * name;
3141 } ath_rf_names[] = {
3142 { 0, "5133" },
3143 { AR_RAD5133_SREV_MAJOR, "5133" },
3144 { AR_RAD5122_SREV_MAJOR, "5122" },
3145 { AR_RAD2133_SREV_MAJOR, "2133" },
3146 { AR_RAD2122_SREV_MAJOR, "2122" }
3147 };
3148
3149 /*
3150 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3151 */
3152 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
3153 {
3154 int i;
3155
3156 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3157 if (ath_mac_bb_names[i].version == mac_bb_version) {
3158 return ath_mac_bb_names[i].name;
3159 }
3160 }
3161
3162 return "????";
3163 }
3164
3165 /*
3166 * Return the RF name. "????" is returned if the RF is unknown.
3167 * Used for devices with external radios.
3168 */
3169 static const char *ath9k_hw_rf_name(u16 rf_version)
3170 {
3171 int i;
3172
3173 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3174 if (ath_rf_names[i].version == rf_version) {
3175 return ath_rf_names[i].name;
3176 }
3177 }
3178
3179 return "????";
3180 }
3181
3182 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
3183 {
3184 int used;
3185
3186 /* chipsets >= AR9280 are single-chip */
3187 if (AR_SREV_9280_20_OR_LATER(ah)) {
3188 used = scnprintf(hw_name, len,
3189 "Atheros AR%s Rev:%x",
3190 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3191 ah->hw_version.macRev);
3192 }
3193 else {
3194 used = scnprintf(hw_name, len,
3195 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3196 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3197 ah->hw_version.macRev,
3198 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev
3199 & AR_RADIO_SREV_MAJOR)),
3200 ah->hw_version.phyRev);
3201 }
3202
3203 hw_name[used] = '\0';
3204 }
3205 EXPORT_SYMBOL(ath9k_hw_name);
Linux kernel - Deliverables
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