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ath9k_hw: add DFS testing check
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / hw.c
1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/io.h>
18 #include <linux/slab.h>
19 #include <linux/module.h>
20 #include <asm/unaligned.h>
21
22 #include "hw.h"
23 #include "hw-ops.h"
24 #include "rc.h"
25 #include "ar9003_mac.h"
26
27 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
28
29 MODULE_AUTHOR("Atheros Communications");
30 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
31 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
32 MODULE_LICENSE("Dual BSD/GPL");
33
34 static int __init ath9k_init(void)
35 {
36 return 0;
37 }
38 module_init(ath9k_init);
39
40 static void __exit ath9k_exit(void)
41 {
42 return;
43 }
44 module_exit(ath9k_exit);
45
46 /* Private hardware callbacks */
47
48 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
49 {
50 ath9k_hw_private_ops(ah)->init_cal_settings(ah);
51 }
52
53 static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
54 {
55 ath9k_hw_private_ops(ah)->init_mode_regs(ah);
56 }
57
58 static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
59 struct ath9k_channel *chan)
60 {
61 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
62 }
63
64 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
65 {
66 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
67 return;
68
69 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
70 }
71
72 static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah)
73 {
74 /* You will not have this callback if using the old ANI */
75 if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs)
76 return;
77
78 ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah);
79 }
80
81 /********************/
82 /* Helper Functions */
83 /********************/
84
85 static void ath9k_hw_set_clockrate(struct ath_hw *ah)
86 {
87 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
88 struct ath_common *common = ath9k_hw_common(ah);
89 unsigned int clockrate;
90
91 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */
92 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah))
93 clockrate = 117;
94 else if (!ah->curchan) /* should really check for CCK instead */
95 clockrate = ATH9K_CLOCK_RATE_CCK;
96 else if (conf->channel->band == IEEE80211_BAND_2GHZ)
97 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
98 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
99 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
100 else
101 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
102
103 if (conf_is_ht40(conf))
104 clockrate *= 2;
105
106 if (ah->curchan) {
107 if (IS_CHAN_HALF_RATE(ah->curchan))
108 clockrate /= 2;
109 if (IS_CHAN_QUARTER_RATE(ah->curchan))
110 clockrate /= 4;
111 }
112
113 common->clockrate = clockrate;
114 }
115
116 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
117 {
118 struct ath_common *common = ath9k_hw_common(ah);
119
120 return usecs * common->clockrate;
121 }
122
123 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
124 {
125 int i;
126
127 BUG_ON(timeout < AH_TIME_QUANTUM);
128
129 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
130 if ((REG_READ(ah, reg) & mask) == val)
131 return true;
132
133 udelay(AH_TIME_QUANTUM);
134 }
135
136 ath_dbg(ath9k_hw_common(ah), ATH_DBG_ANY,
137 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
138 timeout, reg, REG_READ(ah, reg), mask, val);
139
140 return false;
141 }
142 EXPORT_SYMBOL(ath9k_hw_wait);
143
144 void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array,
145 int column, unsigned int *writecnt)
146 {
147 int r;
148
149 ENABLE_REGWRITE_BUFFER(ah);
150 for (r = 0; r < array->ia_rows; r++) {
151 REG_WRITE(ah, INI_RA(array, r, 0),
152 INI_RA(array, r, column));
153 DO_DELAY(*writecnt);
154 }
155 REGWRITE_BUFFER_FLUSH(ah);
156 }
157
158 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
159 {
160 u32 retval;
161 int i;
162
163 for (i = 0, retval = 0; i < n; i++) {
164 retval = (retval << 1) | (val & 1);
165 val >>= 1;
166 }
167 return retval;
168 }
169
170 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
171 u8 phy, int kbps,
172 u32 frameLen, u16 rateix,
173 bool shortPreamble)
174 {
175 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
176
177 if (kbps == 0)
178 return 0;
179
180 switch (phy) {
181 case WLAN_RC_PHY_CCK:
182 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
183 if (shortPreamble)
184 phyTime >>= 1;
185 numBits = frameLen << 3;
186 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
187 break;
188 case WLAN_RC_PHY_OFDM:
189 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
190 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
191 numBits = OFDM_PLCP_BITS + (frameLen << 3);
192 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
193 txTime = OFDM_SIFS_TIME_QUARTER
194 + OFDM_PREAMBLE_TIME_QUARTER
195 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
196 } else if (ah->curchan &&
197 IS_CHAN_HALF_RATE(ah->curchan)) {
198 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
199 numBits = OFDM_PLCP_BITS + (frameLen << 3);
200 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
201 txTime = OFDM_SIFS_TIME_HALF +
202 OFDM_PREAMBLE_TIME_HALF
203 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
204 } else {
205 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
206 numBits = OFDM_PLCP_BITS + (frameLen << 3);
207 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
208 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
209 + (numSymbols * OFDM_SYMBOL_TIME);
210 }
211 break;
212 default:
213 ath_err(ath9k_hw_common(ah),
214 "Unknown phy %u (rate ix %u)\n", phy, rateix);
215 txTime = 0;
216 break;
217 }
218
219 return txTime;
220 }
221 EXPORT_SYMBOL(ath9k_hw_computetxtime);
222
223 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
224 struct ath9k_channel *chan,
225 struct chan_centers *centers)
226 {
227 int8_t extoff;
228
229 if (!IS_CHAN_HT40(chan)) {
230 centers->ctl_center = centers->ext_center =
231 centers->synth_center = chan->channel;
232 return;
233 }
234
235 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
236 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
237 centers->synth_center =
238 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
239 extoff = 1;
240 } else {
241 centers->synth_center =
242 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
243 extoff = -1;
244 }
245
246 centers->ctl_center =
247 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
248 /* 25 MHz spacing is supported by hw but not on upper layers */
249 centers->ext_center =
250 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
251 }
252
253 /******************/
254 /* Chip Revisions */
255 /******************/
256
257 static void ath9k_hw_read_revisions(struct ath_hw *ah)
258 {
259 u32 val;
260
261 switch (ah->hw_version.devid) {
262 case AR5416_AR9100_DEVID:
263 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
264 break;
265 case AR9300_DEVID_AR9330:
266 ah->hw_version.macVersion = AR_SREV_VERSION_9330;
267 if (ah->get_mac_revision) {
268 ah->hw_version.macRev = ah->get_mac_revision();
269 } else {
270 val = REG_READ(ah, AR_SREV);
271 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
272 }
273 return;
274 case AR9300_DEVID_AR9340:
275 ah->hw_version.macVersion = AR_SREV_VERSION_9340;
276 val = REG_READ(ah, AR_SREV);
277 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
278 return;
279 }
280
281 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
282
283 if (val == 0xFF) {
284 val = REG_READ(ah, AR_SREV);
285 ah->hw_version.macVersion =
286 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
287 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
288
289 if (AR_SREV_9462(ah))
290 ah->is_pciexpress = true;
291 else
292 ah->is_pciexpress = (val &
293 AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
294 } else {
295 if (!AR_SREV_9100(ah))
296 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
297
298 ah->hw_version.macRev = val & AR_SREV_REVISION;
299
300 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
301 ah->is_pciexpress = true;
302 }
303 }
304
305 /************************************/
306 /* HW Attach, Detach, Init Routines */
307 /************************************/
308
309 static void ath9k_hw_disablepcie(struct ath_hw *ah)
310 {
311 if (!AR_SREV_5416(ah))
312 return;
313
314 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
315 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
316 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
317 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
318 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
319 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
320 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
321 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
322 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
323
324 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
325 }
326
327 static void ath9k_hw_aspm_init(struct ath_hw *ah)
328 {
329 struct ath_common *common = ath9k_hw_common(ah);
330
331 if (common->bus_ops->aspm_init)
332 common->bus_ops->aspm_init(common);
333 }
334
335 /* This should work for all families including legacy */
336 static bool ath9k_hw_chip_test(struct ath_hw *ah)
337 {
338 struct ath_common *common = ath9k_hw_common(ah);
339 u32 regAddr[2] = { AR_STA_ID0 };
340 u32 regHold[2];
341 static const u32 patternData[4] = {
342 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
343 };
344 int i, j, loop_max;
345
346 if (!AR_SREV_9300_20_OR_LATER(ah)) {
347 loop_max = 2;
348 regAddr[1] = AR_PHY_BASE + (8 << 2);
349 } else
350 loop_max = 1;
351
352 for (i = 0; i < loop_max; i++) {
353 u32 addr = regAddr[i];
354 u32 wrData, rdData;
355
356 regHold[i] = REG_READ(ah, addr);
357 for (j = 0; j < 0x100; j++) {
358 wrData = (j << 16) | j;
359 REG_WRITE(ah, addr, wrData);
360 rdData = REG_READ(ah, addr);
361 if (rdData != wrData) {
362 ath_err(common,
363 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
364 addr, wrData, rdData);
365 return false;
366 }
367 }
368 for (j = 0; j < 4; j++) {
369 wrData = patternData[j];
370 REG_WRITE(ah, addr, wrData);
371 rdData = REG_READ(ah, addr);
372 if (wrData != rdData) {
373 ath_err(common,
374 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
375 addr, wrData, rdData);
376 return false;
377 }
378 }
379 REG_WRITE(ah, regAddr[i], regHold[i]);
380 }
381 udelay(100);
382
383 return true;
384 }
385
386 static void ath9k_hw_init_config(struct ath_hw *ah)
387 {
388 int i;
389
390 ah->config.dma_beacon_response_time = 2;
391 ah->config.sw_beacon_response_time = 10;
392 ah->config.additional_swba_backoff = 0;
393 ah->config.ack_6mb = 0x0;
394 ah->config.cwm_ignore_extcca = 0;
395 ah->config.pcie_clock_req = 0;
396 ah->config.pcie_waen = 0;
397 ah->config.analog_shiftreg = 1;
398 ah->config.enable_ani = true;
399
400 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
401 ah->config.spurchans[i][0] = AR_NO_SPUR;
402 ah->config.spurchans[i][1] = AR_NO_SPUR;
403 }
404
405 /* PAPRD needs some more work to be enabled */
406 ah->config.paprd_disable = 1;
407
408 ah->config.rx_intr_mitigation = true;
409 ah->config.pcieSerDesWrite = true;
410
411 /*
412 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
413 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
414 * This means we use it for all AR5416 devices, and the few
415 * minor PCI AR9280 devices out there.
416 *
417 * Serialization is required because these devices do not handle
418 * well the case of two concurrent reads/writes due to the latency
419 * involved. During one read/write another read/write can be issued
420 * on another CPU while the previous read/write may still be working
421 * on our hardware, if we hit this case the hardware poops in a loop.
422 * We prevent this by serializing reads and writes.
423 *
424 * This issue is not present on PCI-Express devices or pre-AR5416
425 * devices (legacy, 802.11abg).
426 */
427 if (num_possible_cpus() > 1)
428 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
429 }
430
431 static void ath9k_hw_init_defaults(struct ath_hw *ah)
432 {
433 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
434
435 regulatory->country_code = CTRY_DEFAULT;
436 regulatory->power_limit = MAX_RATE_POWER;
437
438 ah->hw_version.magic = AR5416_MAGIC;
439 ah->hw_version.subvendorid = 0;
440
441 ah->atim_window = 0;
442 ah->sta_id1_defaults =
443 AR_STA_ID1_CRPT_MIC_ENABLE |
444 AR_STA_ID1_MCAST_KSRCH;
445 if (AR_SREV_9100(ah))
446 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX;
447 ah->enable_32kHz_clock = DONT_USE_32KHZ;
448 ah->slottime = ATH9K_SLOT_TIME_9;
449 ah->globaltxtimeout = (u32) -1;
450 ah->power_mode = ATH9K_PM_UNDEFINED;
451 }
452
453 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
454 {
455 struct ath_common *common = ath9k_hw_common(ah);
456 u32 sum;
457 int i;
458 u16 eeval;
459 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
460
461 sum = 0;
462 for (i = 0; i < 3; i++) {
463 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
464 sum += eeval;
465 common->macaddr[2 * i] = eeval >> 8;
466 common->macaddr[2 * i + 1] = eeval & 0xff;
467 }
468 if (sum == 0 || sum == 0xffff * 3)
469 return -EADDRNOTAVAIL;
470
471 return 0;
472 }
473
474 static int ath9k_hw_post_init(struct ath_hw *ah)
475 {
476 struct ath_common *common = ath9k_hw_common(ah);
477 int ecode;
478
479 if (common->bus_ops->ath_bus_type != ATH_USB) {
480 if (!ath9k_hw_chip_test(ah))
481 return -ENODEV;
482 }
483
484 if (!AR_SREV_9300_20_OR_LATER(ah)) {
485 ecode = ar9002_hw_rf_claim(ah);
486 if (ecode != 0)
487 return ecode;
488 }
489
490 ecode = ath9k_hw_eeprom_init(ah);
491 if (ecode != 0)
492 return ecode;
493
494 ath_dbg(ath9k_hw_common(ah), ATH_DBG_CONFIG,
495 "Eeprom VER: %d, REV: %d\n",
496 ah->eep_ops->get_eeprom_ver(ah),
497 ah->eep_ops->get_eeprom_rev(ah));
498
499 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
500 if (ecode) {
501 ath_err(ath9k_hw_common(ah),
502 "Failed allocating banks for external radio\n");
503 ath9k_hw_rf_free_ext_banks(ah);
504 return ecode;
505 }
506
507 if (ah->config.enable_ani) {
508 ath9k_hw_ani_setup(ah);
509 ath9k_hw_ani_init(ah);
510 }
511
512 return 0;
513 }
514
515 static void ath9k_hw_attach_ops(struct ath_hw *ah)
516 {
517 if (AR_SREV_9300_20_OR_LATER(ah))
518 ar9003_hw_attach_ops(ah);
519 else
520 ar9002_hw_attach_ops(ah);
521 }
522
523 /* Called for all hardware families */
524 static int __ath9k_hw_init(struct ath_hw *ah)
525 {
526 struct ath_common *common = ath9k_hw_common(ah);
527 int r = 0;
528
529 ath9k_hw_read_revisions(ah);
530
531 /*
532 * Read back AR_WA into a permanent copy and set bits 14 and 17.
533 * We need to do this to avoid RMW of this register. We cannot
534 * read the reg when chip is asleep.
535 */
536 ah->WARegVal = REG_READ(ah, AR_WA);
537 ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
538 AR_WA_ASPM_TIMER_BASED_DISABLE);
539
540 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
541 ath_err(common, "Couldn't reset chip\n");
542 return -EIO;
543 }
544
545 if (AR_SREV_9462(ah))
546 ah->WARegVal &= ~AR_WA_D3_L1_DISABLE;
547
548 ath9k_hw_init_defaults(ah);
549 ath9k_hw_init_config(ah);
550
551 ath9k_hw_attach_ops(ah);
552
553 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
554 ath_err(common, "Couldn't wakeup chip\n");
555 return -EIO;
556 }
557
558 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
559 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
560 ((AR_SREV_9160(ah) || AR_SREV_9280(ah)) &&
561 !ah->is_pciexpress)) {
562 ah->config.serialize_regmode =
563 SER_REG_MODE_ON;
564 } else {
565 ah->config.serialize_regmode =
566 SER_REG_MODE_OFF;
567 }
568 }
569
570 ath_dbg(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
571 ah->config.serialize_regmode);
572
573 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
574 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
575 else
576 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
577
578 switch (ah->hw_version.macVersion) {
579 case AR_SREV_VERSION_5416_PCI:
580 case AR_SREV_VERSION_5416_PCIE:
581 case AR_SREV_VERSION_9160:
582 case AR_SREV_VERSION_9100:
583 case AR_SREV_VERSION_9280:
584 case AR_SREV_VERSION_9285:
585 case AR_SREV_VERSION_9287:
586 case AR_SREV_VERSION_9271:
587 case AR_SREV_VERSION_9300:
588 case AR_SREV_VERSION_9330:
589 case AR_SREV_VERSION_9485:
590 case AR_SREV_VERSION_9340:
591 case AR_SREV_VERSION_9462:
592 break;
593 default:
594 ath_err(common,
595 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
596 ah->hw_version.macVersion, ah->hw_version.macRev);
597 return -EOPNOTSUPP;
598 }
599
600 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) ||
601 AR_SREV_9330(ah))
602 ah->is_pciexpress = false;
603
604 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
605 ath9k_hw_init_cal_settings(ah);
606
607 ah->ani_function = ATH9K_ANI_ALL;
608 if (AR_SREV_9280_20_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
609 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
610 if (!AR_SREV_9300_20_OR_LATER(ah))
611 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
612
613 /* disable ANI for 9340 */
614 if (AR_SREV_9340(ah))
615 ah->config.enable_ani = false;
616
617 ath9k_hw_init_mode_regs(ah);
618
619 if (!ah->is_pciexpress)
620 ath9k_hw_disablepcie(ah);
621
622 if (!AR_SREV_9300_20_OR_LATER(ah))
623 ar9002_hw_cck_chan14_spread(ah);
624
625 r = ath9k_hw_post_init(ah);
626 if (r)
627 return r;
628
629 ath9k_hw_init_mode_gain_regs(ah);
630 r = ath9k_hw_fill_cap_info(ah);
631 if (r)
632 return r;
633
634 if (ah->is_pciexpress)
635 ath9k_hw_aspm_init(ah);
636
637 r = ath9k_hw_init_macaddr(ah);
638 if (r) {
639 ath_err(common, "Failed to initialize MAC address\n");
640 return r;
641 }
642
643 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
644 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
645 else
646 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
647
648 if (AR_SREV_9330(ah))
649 ah->bb_watchdog_timeout_ms = 85;
650 else
651 ah->bb_watchdog_timeout_ms = 25;
652
653 common->state = ATH_HW_INITIALIZED;
654
655 return 0;
656 }
657
658 int ath9k_hw_init(struct ath_hw *ah)
659 {
660 int ret;
661 struct ath_common *common = ath9k_hw_common(ah);
662
663 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
664 switch (ah->hw_version.devid) {
665 case AR5416_DEVID_PCI:
666 case AR5416_DEVID_PCIE:
667 case AR5416_AR9100_DEVID:
668 case AR9160_DEVID_PCI:
669 case AR9280_DEVID_PCI:
670 case AR9280_DEVID_PCIE:
671 case AR9285_DEVID_PCIE:
672 case AR9287_DEVID_PCI:
673 case AR9287_DEVID_PCIE:
674 case AR2427_DEVID_PCIE:
675 case AR9300_DEVID_PCIE:
676 case AR9300_DEVID_AR9485_PCIE:
677 case AR9300_DEVID_AR9330:
678 case AR9300_DEVID_AR9340:
679 case AR9300_DEVID_AR9580:
680 case AR9300_DEVID_AR9462:
681 break;
682 default:
683 if (common->bus_ops->ath_bus_type == ATH_USB)
684 break;
685 ath_err(common, "Hardware device ID 0x%04x not supported\n",
686 ah->hw_version.devid);
687 return -EOPNOTSUPP;
688 }
689
690 ret = __ath9k_hw_init(ah);
691 if (ret) {
692 ath_err(common,
693 "Unable to initialize hardware; initialization status: %d\n",
694 ret);
695 return ret;
696 }
697
698 return 0;
699 }
700 EXPORT_SYMBOL(ath9k_hw_init);
701
702 static void ath9k_hw_init_qos(struct ath_hw *ah)
703 {
704 ENABLE_REGWRITE_BUFFER(ah);
705
706 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
707 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
708
709 REG_WRITE(ah, AR_QOS_NO_ACK,
710 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
711 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
712 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
713
714 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
715 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
716 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
717 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
718 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
719
720 REGWRITE_BUFFER_FLUSH(ah);
721 }
722
723 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
724 {
725 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
726 udelay(100);
727 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
728
729 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0)
730 udelay(100);
731
732 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
733 }
734 EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc);
735
736 static void ath9k_hw_init_pll(struct ath_hw *ah,
737 struct ath9k_channel *chan)
738 {
739 u32 pll;
740
741 if (AR_SREV_9485(ah)) {
742
743 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */
744 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
745 AR_CH0_BB_DPLL2_PLL_PWD, 0x1);
746 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
747 AR_CH0_DPLL2_KD, 0x40);
748 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
749 AR_CH0_DPLL2_KI, 0x4);
750
751 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
752 AR_CH0_BB_DPLL1_REFDIV, 0x5);
753 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
754 AR_CH0_BB_DPLL1_NINI, 0x58);
755 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
756 AR_CH0_BB_DPLL1_NFRAC, 0x0);
757
758 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
759 AR_CH0_BB_DPLL2_OUTDIV, 0x1);
760 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
761 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1);
762 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
763 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1);
764
765 /* program BB PLL phase_shift to 0x6 */
766 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
767 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6);
768
769 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
770 AR_CH0_BB_DPLL2_PLL_PWD, 0x0);
771 udelay(1000);
772 } else if (AR_SREV_9330(ah)) {
773 u32 ddr_dpll2, pll_control2, kd;
774
775 if (ah->is_clk_25mhz) {
776 ddr_dpll2 = 0x18e82f01;
777 pll_control2 = 0xe04a3d;
778 kd = 0x1d;
779 } else {
780 ddr_dpll2 = 0x19e82f01;
781 pll_control2 = 0x886666;
782 kd = 0x3d;
783 }
784
785 /* program DDR PLL ki and kd value */
786 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2);
787
788 /* program DDR PLL phase_shift */
789 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3,
790 AR_CH0_DPLL3_PHASE_SHIFT, 0x1);
791
792 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
793 udelay(1000);
794
795 /* program refdiv, nint, frac to RTC register */
796 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2);
797
798 /* program BB PLL kd and ki value */
799 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd);
800 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06);
801
802 /* program BB PLL phase_shift */
803 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
804 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1);
805 } else if (AR_SREV_9340(ah)) {
806 u32 regval, pll2_divint, pll2_divfrac, refdiv;
807
808 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
809 udelay(1000);
810
811 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16);
812 udelay(100);
813
814 if (ah->is_clk_25mhz) {
815 pll2_divint = 0x54;
816 pll2_divfrac = 0x1eb85;
817 refdiv = 3;
818 } else {
819 pll2_divint = 88;
820 pll2_divfrac = 0;
821 refdiv = 5;
822 }
823
824 regval = REG_READ(ah, AR_PHY_PLL_MODE);
825 regval |= (0x1 << 16);
826 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
827 udelay(100);
828
829 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) |
830 (pll2_divint << 18) | pll2_divfrac);
831 udelay(100);
832
833 regval = REG_READ(ah, AR_PHY_PLL_MODE);
834 regval = (regval & 0x80071fff) | (0x1 << 30) | (0x1 << 13) |
835 (0x4 << 26) | (0x18 << 19);
836 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
837 REG_WRITE(ah, AR_PHY_PLL_MODE,
838 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff);
839 udelay(1000);
840 }
841
842 pll = ath9k_hw_compute_pll_control(ah, chan);
843
844 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
845
846 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah))
847 udelay(1000);
848
849 /* Switch the core clock for ar9271 to 117Mhz */
850 if (AR_SREV_9271(ah)) {
851 udelay(500);
852 REG_WRITE(ah, 0x50040, 0x304);
853 }
854
855 udelay(RTC_PLL_SETTLE_DELAY);
856
857 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
858
859 if (AR_SREV_9340(ah)) {
860 if (ah->is_clk_25mhz) {
861 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1);
862 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);
863 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae);
864 } else {
865 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1);
866 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400);
867 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800);
868 }
869 udelay(100);
870 }
871 }
872
873 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
874 enum nl80211_iftype opmode)
875 {
876 u32 sync_default = AR_INTR_SYNC_DEFAULT;
877 u32 imr_reg = AR_IMR_TXERR |
878 AR_IMR_TXURN |
879 AR_IMR_RXERR |
880 AR_IMR_RXORN |
881 AR_IMR_BCNMISC;
882
883 if (AR_SREV_9340(ah))
884 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
885
886 if (AR_SREV_9300_20_OR_LATER(ah)) {
887 imr_reg |= AR_IMR_RXOK_HP;
888 if (ah->config.rx_intr_mitigation)
889 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
890 else
891 imr_reg |= AR_IMR_RXOK_LP;
892
893 } else {
894 if (ah->config.rx_intr_mitigation)
895 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
896 else
897 imr_reg |= AR_IMR_RXOK;
898 }
899
900 if (ah->config.tx_intr_mitigation)
901 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
902 else
903 imr_reg |= AR_IMR_TXOK;
904
905 if (opmode == NL80211_IFTYPE_AP)
906 imr_reg |= AR_IMR_MIB;
907
908 ENABLE_REGWRITE_BUFFER(ah);
909
910 REG_WRITE(ah, AR_IMR, imr_reg);
911 ah->imrs2_reg |= AR_IMR_S2_GTT;
912 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
913
914 if (!AR_SREV_9100(ah)) {
915 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
916 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
917 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
918 }
919
920 REGWRITE_BUFFER_FLUSH(ah);
921
922 if (AR_SREV_9300_20_OR_LATER(ah)) {
923 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
924 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
925 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
926 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
927 }
928 }
929
930 static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us)
931 {
932 u32 val = ath9k_hw_mac_to_clks(ah, us - 2);
933 val = min(val, (u32) 0xFFFF);
934 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val);
935 }
936
937 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
938 {
939 u32 val = ath9k_hw_mac_to_clks(ah, us);
940 val = min(val, (u32) 0xFFFF);
941 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
942 }
943
944 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
945 {
946 u32 val = ath9k_hw_mac_to_clks(ah, us);
947 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
948 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
949 }
950
951 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
952 {
953 u32 val = ath9k_hw_mac_to_clks(ah, us);
954 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
955 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
956 }
957
958 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
959 {
960 if (tu > 0xFFFF) {
961 ath_dbg(ath9k_hw_common(ah), ATH_DBG_XMIT,
962 "bad global tx timeout %u\n", tu);
963 ah->globaltxtimeout = (u32) -1;
964 return false;
965 } else {
966 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
967 ah->globaltxtimeout = tu;
968 return true;
969 }
970 }
971
972 void ath9k_hw_init_global_settings(struct ath_hw *ah)
973 {
974 struct ath_common *common = ath9k_hw_common(ah);
975 struct ieee80211_conf *conf = &common->hw->conf;
976 const struct ath9k_channel *chan = ah->curchan;
977 int acktimeout, ctstimeout;
978 int slottime;
979 int sifstime;
980 int rx_lat = 0, tx_lat = 0, eifs = 0;
981 u32 reg;
982
983 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
984 ah->misc_mode);
985
986 if (!chan)
987 return;
988
989 if (ah->misc_mode != 0)
990 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode);
991
992 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
993 rx_lat = 41;
994 else
995 rx_lat = 37;
996 tx_lat = 54;
997
998 if (IS_CHAN_HALF_RATE(chan)) {
999 eifs = 175;
1000 rx_lat *= 2;
1001 tx_lat *= 2;
1002 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1003 tx_lat += 11;
1004
1005 slottime = 13;
1006 sifstime = 32;
1007 } else if (IS_CHAN_QUARTER_RATE(chan)) {
1008 eifs = 340;
1009 rx_lat = (rx_lat * 4) - 1;
1010 tx_lat *= 4;
1011 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1012 tx_lat += 22;
1013
1014 slottime = 21;
1015 sifstime = 64;
1016 } else {
1017 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1018 eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO;
1019 reg = AR_USEC_ASYNC_FIFO;
1020 } else {
1021 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/
1022 common->clockrate;
1023 reg = REG_READ(ah, AR_USEC);
1024 }
1025 rx_lat = MS(reg, AR_USEC_RX_LAT);
1026 tx_lat = MS(reg, AR_USEC_TX_LAT);
1027
1028 slottime = ah->slottime;
1029 if (IS_CHAN_5GHZ(chan))
1030 sifstime = 16;
1031 else
1032 sifstime = 10;
1033 }
1034
1035 /* As defined by IEEE 802.11-2007 17.3.8.6 */
1036 acktimeout = slottime + sifstime + 3 * ah->coverage_class;
1037 ctstimeout = acktimeout;
1038
1039 /*
1040 * Workaround for early ACK timeouts, add an offset to match the
1041 * initval's 64us ack timeout value.
1042 * This was initially only meant to work around an issue with delayed
1043 * BA frames in some implementations, but it has been found to fix ACK
1044 * timeout issues in other cases as well.
1045 */
1046 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
1047 acktimeout += 64 - sifstime - ah->slottime;
1048
1049 ath9k_hw_set_sifs_time(ah, sifstime);
1050 ath9k_hw_setslottime(ah, slottime);
1051 ath9k_hw_set_ack_timeout(ah, acktimeout);
1052 ath9k_hw_set_cts_timeout(ah, ctstimeout);
1053 if (ah->globaltxtimeout != (u32) -1)
1054 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1055
1056 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs));
1057 REG_RMW(ah, AR_USEC,
1058 (common->clockrate - 1) |
1059 SM(rx_lat, AR_USEC_RX_LAT) |
1060 SM(tx_lat, AR_USEC_TX_LAT),
1061 AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC);
1062
1063 }
1064 EXPORT_SYMBOL(ath9k_hw_init_global_settings);
1065
1066 void ath9k_hw_deinit(struct ath_hw *ah)
1067 {
1068 struct ath_common *common = ath9k_hw_common(ah);
1069
1070 if (common->state < ATH_HW_INITIALIZED)
1071 goto free_hw;
1072
1073 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1074
1075 free_hw:
1076 ath9k_hw_rf_free_ext_banks(ah);
1077 }
1078 EXPORT_SYMBOL(ath9k_hw_deinit);
1079
1080 /*******/
1081 /* INI */
1082 /*******/
1083
1084 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
1085 {
1086 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1087
1088 if (IS_CHAN_B(chan))
1089 ctl |= CTL_11B;
1090 else if (IS_CHAN_G(chan))
1091 ctl |= CTL_11G;
1092 else
1093 ctl |= CTL_11A;
1094
1095 return ctl;
1096 }
1097
1098 /****************************************/
1099 /* Reset and Channel Switching Routines */
1100 /****************************************/
1101
1102 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1103 {
1104 struct ath_common *common = ath9k_hw_common(ah);
1105
1106 ENABLE_REGWRITE_BUFFER(ah);
1107
1108 /*
1109 * set AHB_MODE not to do cacheline prefetches
1110 */
1111 if (!AR_SREV_9300_20_OR_LATER(ah))
1112 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
1113
1114 /*
1115 * let mac dma reads be in 128 byte chunks
1116 */
1117 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK);
1118
1119 REGWRITE_BUFFER_FLUSH(ah);
1120
1121 /*
1122 * Restore TX Trigger Level to its pre-reset value.
1123 * The initial value depends on whether aggregation is enabled, and is
1124 * adjusted whenever underruns are detected.
1125 */
1126 if (!AR_SREV_9300_20_OR_LATER(ah))
1127 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1128
1129 ENABLE_REGWRITE_BUFFER(ah);
1130
1131 /*
1132 * let mac dma writes be in 128 byte chunks
1133 */
1134 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK);
1135
1136 /*
1137 * Setup receive FIFO threshold to hold off TX activities
1138 */
1139 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1140
1141 if (AR_SREV_9300_20_OR_LATER(ah)) {
1142 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
1143 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
1144
1145 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
1146 ah->caps.rx_status_len);
1147 }
1148
1149 /*
1150 * reduce the number of usable entries in PCU TXBUF to avoid
1151 * wrap around issues.
1152 */
1153 if (AR_SREV_9285(ah)) {
1154 /* For AR9285 the number of Fifos are reduced to half.
1155 * So set the usable tx buf size also to half to
1156 * avoid data/delimiter underruns
1157 */
1158 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1159 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1160 } else if (!AR_SREV_9271(ah)) {
1161 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1162 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1163 }
1164
1165 REGWRITE_BUFFER_FLUSH(ah);
1166
1167 if (AR_SREV_9300_20_OR_LATER(ah))
1168 ath9k_hw_reset_txstatus_ring(ah);
1169 }
1170
1171 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1172 {
1173 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC;
1174 u32 set = AR_STA_ID1_KSRCH_MODE;
1175
1176 switch (opmode) {
1177 case NL80211_IFTYPE_ADHOC:
1178 case NL80211_IFTYPE_MESH_POINT:
1179 set |= AR_STA_ID1_ADHOC;
1180 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1181 break;
1182 case NL80211_IFTYPE_AP:
1183 set |= AR_STA_ID1_STA_AP;
1184 /* fall through */
1185 case NL80211_IFTYPE_STATION:
1186 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1187 break;
1188 default:
1189 if (!ah->is_monitoring)
1190 set = 0;
1191 break;
1192 }
1193 REG_RMW(ah, AR_STA_ID1, set, mask);
1194 }
1195
1196 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1197 u32 *coef_mantissa, u32 *coef_exponent)
1198 {
1199 u32 coef_exp, coef_man;
1200
1201 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1202 if ((coef_scaled >> coef_exp) & 0x1)
1203 break;
1204
1205 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1206
1207 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1208
1209 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1210 *coef_exponent = coef_exp - 16;
1211 }
1212
1213 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1214 {
1215 u32 rst_flags;
1216 u32 tmpReg;
1217
1218 if (AR_SREV_9100(ah)) {
1219 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK,
1220 AR_RTC_DERIVED_CLK_PERIOD, 1);
1221 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1222 }
1223
1224 ENABLE_REGWRITE_BUFFER(ah);
1225
1226 if (AR_SREV_9300_20_OR_LATER(ah)) {
1227 REG_WRITE(ah, AR_WA, ah->WARegVal);
1228 udelay(10);
1229 }
1230
1231 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1232 AR_RTC_FORCE_WAKE_ON_INT);
1233
1234 if (AR_SREV_9100(ah)) {
1235 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1236 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1237 } else {
1238 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1239 if (tmpReg &
1240 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1241 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1242 u32 val;
1243 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1244
1245 val = AR_RC_HOSTIF;
1246 if (!AR_SREV_9300_20_OR_LATER(ah))
1247 val |= AR_RC_AHB;
1248 REG_WRITE(ah, AR_RC, val);
1249
1250 } else if (!AR_SREV_9300_20_OR_LATER(ah))
1251 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1252
1253 rst_flags = AR_RTC_RC_MAC_WARM;
1254 if (type == ATH9K_RESET_COLD)
1255 rst_flags |= AR_RTC_RC_MAC_COLD;
1256 }
1257
1258 if (AR_SREV_9330(ah)) {
1259 int npend = 0;
1260 int i;
1261
1262 /* AR9330 WAR:
1263 * call external reset function to reset WMAC if:
1264 * - doing a cold reset
1265 * - we have pending frames in the TX queues
1266 */
1267
1268 for (i = 0; i < AR_NUM_QCU; i++) {
1269 npend = ath9k_hw_numtxpending(ah, i);
1270 if (npend)
1271 break;
1272 }
1273
1274 if (ah->external_reset &&
1275 (npend || type == ATH9K_RESET_COLD)) {
1276 int reset_err = 0;
1277
1278 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
1279 "reset MAC via external reset\n");
1280
1281 reset_err = ah->external_reset();
1282 if (reset_err) {
1283 ath_err(ath9k_hw_common(ah),
1284 "External reset failed, err=%d\n",
1285 reset_err);
1286 return false;
1287 }
1288
1289 REG_WRITE(ah, AR_RTC_RESET, 1);
1290 }
1291 }
1292
1293 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1294
1295 REGWRITE_BUFFER_FLUSH(ah);
1296
1297 udelay(50);
1298
1299 REG_WRITE(ah, AR_RTC_RC, 0);
1300 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1301 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
1302 "RTC stuck in MAC reset\n");
1303 return false;
1304 }
1305
1306 if (!AR_SREV_9100(ah))
1307 REG_WRITE(ah, AR_RC, 0);
1308
1309 if (AR_SREV_9100(ah))
1310 udelay(50);
1311
1312 return true;
1313 }
1314
1315 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1316 {
1317 ENABLE_REGWRITE_BUFFER(ah);
1318
1319 if (AR_SREV_9300_20_OR_LATER(ah)) {
1320 REG_WRITE(ah, AR_WA, ah->WARegVal);
1321 udelay(10);
1322 }
1323
1324 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1325 AR_RTC_FORCE_WAKE_ON_INT);
1326
1327 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1328 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1329
1330 REG_WRITE(ah, AR_RTC_RESET, 0);
1331
1332 REGWRITE_BUFFER_FLUSH(ah);
1333
1334 if (!AR_SREV_9300_20_OR_LATER(ah))
1335 udelay(2);
1336
1337 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1338 REG_WRITE(ah, AR_RC, 0);
1339
1340 REG_WRITE(ah, AR_RTC_RESET, 1);
1341
1342 if (!ath9k_hw_wait(ah,
1343 AR_RTC_STATUS,
1344 AR_RTC_STATUS_M,
1345 AR_RTC_STATUS_ON,
1346 AH_WAIT_TIMEOUT)) {
1347 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
1348 "RTC not waking up\n");
1349 return false;
1350 }
1351
1352 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1353 }
1354
1355 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1356 {
1357 bool ret = false;
1358
1359 if (AR_SREV_9300_20_OR_LATER(ah)) {
1360 REG_WRITE(ah, AR_WA, ah->WARegVal);
1361 udelay(10);
1362 }
1363
1364 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1365 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1366
1367 switch (type) {
1368 case ATH9K_RESET_POWER_ON:
1369 ret = ath9k_hw_set_reset_power_on(ah);
1370 break;
1371 case ATH9K_RESET_WARM:
1372 case ATH9K_RESET_COLD:
1373 ret = ath9k_hw_set_reset(ah, type);
1374 break;
1375 default:
1376 break;
1377 }
1378
1379 if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI)
1380 REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2);
1381
1382 return ret;
1383 }
1384
1385 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1386 struct ath9k_channel *chan)
1387 {
1388 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
1389 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1390 return false;
1391 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1392 return false;
1393
1394 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1395 return false;
1396
1397 ah->chip_fullsleep = false;
1398 ath9k_hw_init_pll(ah, chan);
1399 ath9k_hw_set_rfmode(ah, chan);
1400
1401 return true;
1402 }
1403
1404 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1405 struct ath9k_channel *chan)
1406 {
1407 struct ath_common *common = ath9k_hw_common(ah);
1408 u32 qnum;
1409 int r;
1410 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1411 bool band_switch, mode_diff;
1412 u8 ini_reloaded;
1413
1414 band_switch = (chan->channelFlags & (CHANNEL_2GHZ | CHANNEL_5GHZ)) !=
1415 (ah->curchan->channelFlags & (CHANNEL_2GHZ |
1416 CHANNEL_5GHZ));
1417 mode_diff = (chan->chanmode != ah->curchan->chanmode);
1418
1419 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1420 if (ath9k_hw_numtxpending(ah, qnum)) {
1421 ath_dbg(common, ATH_DBG_QUEUE,
1422 "Transmit frames pending on queue %d\n", qnum);
1423 return false;
1424 }
1425 }
1426
1427 if (!ath9k_hw_rfbus_req(ah)) {
1428 ath_err(common, "Could not kill baseband RX\n");
1429 return false;
1430 }
1431
1432 if (edma && (band_switch || mode_diff)) {
1433 ath9k_hw_mark_phy_inactive(ah);
1434 udelay(5);
1435
1436 ath9k_hw_init_pll(ah, NULL);
1437
1438 if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) {
1439 ath_err(common, "Failed to do fast channel change\n");
1440 return false;
1441 }
1442 }
1443
1444 ath9k_hw_set_channel_regs(ah, chan);
1445
1446 r = ath9k_hw_rf_set_freq(ah, chan);
1447 if (r) {
1448 ath_err(common, "Failed to set channel\n");
1449 return false;
1450 }
1451 ath9k_hw_set_clockrate(ah);
1452 ath9k_hw_apply_txpower(ah, chan);
1453 ath9k_hw_rfbus_done(ah);
1454
1455 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1456 ath9k_hw_set_delta_slope(ah, chan);
1457
1458 ath9k_hw_spur_mitigate_freq(ah, chan);
1459
1460 if (edma && (band_switch || mode_diff)) {
1461 ah->ah_flags |= AH_FASTCC;
1462 if (band_switch || ini_reloaded)
1463 ah->eep_ops->set_board_values(ah, chan);
1464
1465 ath9k_hw_init_bb(ah, chan);
1466
1467 if (band_switch || ini_reloaded)
1468 ath9k_hw_init_cal(ah, chan);
1469 ah->ah_flags &= ~AH_FASTCC;
1470 }
1471
1472 return true;
1473 }
1474
1475 static void ath9k_hw_apply_gpio_override(struct ath_hw *ah)
1476 {
1477 u32 gpio_mask = ah->gpio_mask;
1478 int i;
1479
1480 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) {
1481 if (!(gpio_mask & 1))
1482 continue;
1483
1484 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1485 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i)));
1486 }
1487 }
1488
1489 bool ath9k_hw_check_alive(struct ath_hw *ah)
1490 {
1491 int count = 50;
1492 u32 reg;
1493
1494 if (AR_SREV_9285_12_OR_LATER(ah))
1495 return true;
1496
1497 do {
1498 reg = REG_READ(ah, AR_OBS_BUS_1);
1499
1500 if ((reg & 0x7E7FFFEF) == 0x00702400)
1501 continue;
1502
1503 switch (reg & 0x7E000B00) {
1504 case 0x1E000000:
1505 case 0x52000B00:
1506 case 0x18000B00:
1507 continue;
1508 default:
1509 return true;
1510 }
1511 } while (count-- > 0);
1512
1513 return false;
1514 }
1515 EXPORT_SYMBOL(ath9k_hw_check_alive);
1516
1517 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1518 struct ath9k_hw_cal_data *caldata, bool bChannelChange)
1519 {
1520 struct ath_common *common = ath9k_hw_common(ah);
1521 struct ath9k_hw_mci *mci_hw = &ah->btcoex_hw.mci;
1522 u32 saveLedState;
1523 struct ath9k_channel *curchan = ah->curchan;
1524 u32 saveDefAntenna;
1525 u32 macStaId1;
1526 u64 tsf = 0;
1527 int i, r;
1528 bool allow_fbs = false;
1529 bool mci = !!(ah->caps.hw_caps & ATH9K_HW_CAP_MCI);
1530 bool save_fullsleep = ah->chip_fullsleep;
1531
1532 if (mci) {
1533
1534 ar9003_mci_2g5g_changed(ah, IS_CHAN_2GHZ(chan));
1535
1536 if (mci_hw->bt_state == MCI_BT_CAL_START) {
1537 u32 payload[4] = {0, 0, 0, 0};
1538
1539 ath_dbg(common, ATH_DBG_MCI, "MCI stop rx for BT CAL");
1540
1541 mci_hw->bt_state = MCI_BT_CAL;
1542
1543 /*
1544 * MCI FIX: disable mci interrupt here. This is to avoid
1545 * SW_MSG_DONE or RX_MSG bits to trigger MCI_INT and
1546 * lead to mci_intr reentry.
1547 */
1548
1549 ar9003_mci_disable_interrupt(ah);
1550
1551 ath_dbg(common, ATH_DBG_MCI, "send WLAN_CAL_GRANT");
1552 MCI_GPM_SET_CAL_TYPE(payload, MCI_GPM_WLAN_CAL_GRANT);
1553 ar9003_mci_send_message(ah, MCI_GPM, 0, payload,
1554 16, true, false);
1555
1556 ath_dbg(common, ATH_DBG_MCI, "\nMCI BT is calibrating");
1557
1558 /* Wait BT calibration to be completed for 25ms */
1559
1560 if (ar9003_mci_wait_for_gpm(ah, MCI_GPM_BT_CAL_DONE,
1561 0, 25000))
1562 ath_dbg(common, ATH_DBG_MCI,
1563 "MCI got BT_CAL_DONE\n");
1564 else
1565 ath_dbg(common, ATH_DBG_MCI,
1566 "MCI ### BT cal takes to long, force"
1567 "bt_state to be bt_awake\n");
1568 mci_hw->bt_state = MCI_BT_AWAKE;
1569 /* MCI FIX: enable mci interrupt here */
1570 ar9003_mci_enable_interrupt(ah);
1571
1572 return true;
1573 }
1574 }
1575
1576
1577 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1578 return -EIO;
1579
1580 if (curchan && !ah->chip_fullsleep)
1581 ath9k_hw_getnf(ah, curchan);
1582
1583 ah->caldata = caldata;
1584 if (caldata &&
1585 (chan->channel != caldata->channel ||
1586 (chan->channelFlags & ~CHANNEL_CW_INT) !=
1587 (caldata->channelFlags & ~CHANNEL_CW_INT))) {
1588 /* Operating channel changed, reset channel calibration data */
1589 memset(caldata, 0, sizeof(*caldata));
1590 ath9k_init_nfcal_hist_buffer(ah, chan);
1591 }
1592 ah->noise = ath9k_hw_getchan_noise(ah, chan);
1593
1594 if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI)
1595 bChannelChange = false;
1596
1597 if (caldata &&
1598 caldata->done_txiqcal_once &&
1599 caldata->done_txclcal_once &&
1600 caldata->rtt_hist.num_readings)
1601 allow_fbs = true;
1602
1603 if (bChannelChange &&
1604 (ah->chip_fullsleep != true) &&
1605 (ah->curchan != NULL) &&
1606 (chan->channel != ah->curchan->channel) &&
1607 (allow_fbs ||
1608 ((chan->channelFlags & CHANNEL_ALL) ==
1609 (ah->curchan->channelFlags & CHANNEL_ALL)))) {
1610 if (ath9k_hw_channel_change(ah, chan)) {
1611 ath9k_hw_loadnf(ah, ah->curchan);
1612 ath9k_hw_start_nfcal(ah, true);
1613 if (mci && mci_hw->ready)
1614 ar9003_mci_2g5g_switch(ah, true);
1615
1616 if (AR_SREV_9271(ah))
1617 ar9002_hw_load_ani_reg(ah, chan);
1618 return 0;
1619 }
1620 }
1621
1622 if (mci) {
1623 ar9003_mci_disable_interrupt(ah);
1624
1625 if (mci_hw->ready && !save_fullsleep) {
1626 ar9003_mci_mute_bt(ah);
1627 udelay(20);
1628 REG_WRITE(ah, AR_BTCOEX_CTRL, 0);
1629 }
1630
1631 mci_hw->bt_state = MCI_BT_SLEEP;
1632 mci_hw->ready = false;
1633 }
1634
1635
1636 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1637 if (saveDefAntenna == 0)
1638 saveDefAntenna = 1;
1639
1640 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1641
1642 /* For chips on which RTC reset is done, save TSF before it gets cleared */
1643 if (AR_SREV_9100(ah) ||
1644 (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)))
1645 tsf = ath9k_hw_gettsf64(ah);
1646
1647 saveLedState = REG_READ(ah, AR_CFG_LED) &
1648 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1649 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1650
1651 ath9k_hw_mark_phy_inactive(ah);
1652
1653 ah->paprd_table_write_done = false;
1654
1655 /* Only required on the first reset */
1656 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1657 REG_WRITE(ah,
1658 AR9271_RESET_POWER_DOWN_CONTROL,
1659 AR9271_RADIO_RF_RST);
1660 udelay(50);
1661 }
1662
1663 if (!ath9k_hw_chip_reset(ah, chan)) {
1664 ath_err(common, "Chip reset failed\n");
1665 return -EINVAL;
1666 }
1667
1668 /* Only required on the first reset */
1669 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1670 ah->htc_reset_init = false;
1671 REG_WRITE(ah,
1672 AR9271_RESET_POWER_DOWN_CONTROL,
1673 AR9271_GATE_MAC_CTL);
1674 udelay(50);
1675 }
1676
1677 /* Restore TSF */
1678 if (tsf)
1679 ath9k_hw_settsf64(ah, tsf);
1680
1681 if (AR_SREV_9280_20_OR_LATER(ah))
1682 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1683
1684 if (!AR_SREV_9300_20_OR_LATER(ah))
1685 ar9002_hw_enable_async_fifo(ah);
1686
1687 r = ath9k_hw_process_ini(ah, chan);
1688 if (r)
1689 return r;
1690
1691 if (mci)
1692 ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep);
1693
1694 /*
1695 * Some AR91xx SoC devices frequently fail to accept TSF writes
1696 * right after the chip reset. When that happens, write a new
1697 * value after the initvals have been applied, with an offset
1698 * based on measured time difference
1699 */
1700 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
1701 tsf += 1500;
1702 ath9k_hw_settsf64(ah, tsf);
1703 }
1704
1705 /* Setup MFP options for CCMP */
1706 if (AR_SREV_9280_20_OR_LATER(ah)) {
1707 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1708 * frames when constructing CCMP AAD. */
1709 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1710 0xc7ff);
1711 ah->sw_mgmt_crypto = false;
1712 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1713 /* Disable hardware crypto for management frames */
1714 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1715 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1716 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1717 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1718 ah->sw_mgmt_crypto = true;
1719 } else
1720 ah->sw_mgmt_crypto = true;
1721
1722 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1723 ath9k_hw_set_delta_slope(ah, chan);
1724
1725 ath9k_hw_spur_mitigate_freq(ah, chan);
1726 ah->eep_ops->set_board_values(ah, chan);
1727
1728 ENABLE_REGWRITE_BUFFER(ah);
1729
1730 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
1731 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
1732 | macStaId1
1733 | AR_STA_ID1_RTS_USE_DEF
1734 | (ah->config.
1735 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
1736 | ah->sta_id1_defaults);
1737 ath_hw_setbssidmask(common);
1738 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1739 ath9k_hw_write_associd(ah);
1740 REG_WRITE(ah, AR_ISR, ~0);
1741 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1742
1743 REGWRITE_BUFFER_FLUSH(ah);
1744
1745 ath9k_hw_set_operating_mode(ah, ah->opmode);
1746
1747 r = ath9k_hw_rf_set_freq(ah, chan);
1748 if (r)
1749 return r;
1750
1751 ath9k_hw_set_clockrate(ah);
1752
1753 ENABLE_REGWRITE_BUFFER(ah);
1754
1755 for (i = 0; i < AR_NUM_DCU; i++)
1756 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1757
1758 REGWRITE_BUFFER_FLUSH(ah);
1759
1760 ah->intr_txqs = 0;
1761 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1762 ath9k_hw_resettxqueue(ah, i);
1763
1764 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
1765 ath9k_hw_ani_cache_ini_regs(ah);
1766 ath9k_hw_init_qos(ah);
1767
1768 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1769 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
1770
1771 ath9k_hw_init_global_settings(ah);
1772
1773 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1774 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
1775 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
1776 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
1777 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
1778 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1779 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
1780 }
1781
1782 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
1783
1784 ath9k_hw_set_dma(ah);
1785
1786 REG_WRITE(ah, AR_OBS, 8);
1787
1788 if (ah->config.rx_intr_mitigation) {
1789 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
1790 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
1791 }
1792
1793 if (ah->config.tx_intr_mitigation) {
1794 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1795 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1796 }
1797
1798 ath9k_hw_init_bb(ah, chan);
1799
1800 if (caldata) {
1801 caldata->done_txiqcal_once = false;
1802 caldata->done_txclcal_once = false;
1803 caldata->rtt_hist.num_readings = 0;
1804 }
1805 if (!ath9k_hw_init_cal(ah, chan))
1806 return -EIO;
1807
1808 ath9k_hw_loadnf(ah, chan);
1809 ath9k_hw_start_nfcal(ah, true);
1810
1811 if (mci && mci_hw->ready) {
1812
1813 if (IS_CHAN_2GHZ(chan) &&
1814 (mci_hw->bt_state == MCI_BT_SLEEP)) {
1815
1816 if (ar9003_mci_check_int(ah,
1817 AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET) ||
1818 ar9003_mci_check_int(ah,
1819 AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE)) {
1820
1821 /*
1822 * BT is sleeping. Check if BT wakes up during
1823 * WLAN calibration. If BT wakes up during
1824 * WLAN calibration, need to go through all
1825 * message exchanges again and recal.
1826 */
1827
1828 ath_dbg(common, ATH_DBG_MCI, "MCI BT wakes up"
1829 "during WLAN calibration\n");
1830
1831 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW,
1832 AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET |
1833 AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE);
1834 ath_dbg(common, ATH_DBG_MCI, "MCI send"
1835 "REMOTE_RESET\n");
1836 ar9003_mci_remote_reset(ah, true);
1837 ar9003_mci_send_sys_waking(ah, true);
1838 udelay(1);
1839 if (IS_CHAN_2GHZ(chan))
1840 ar9003_mci_send_lna_transfer(ah, true);
1841
1842 mci_hw->bt_state = MCI_BT_AWAKE;
1843
1844 ath_dbg(common, ATH_DBG_MCI, "MCI re-cal\n");
1845
1846 if (caldata) {
1847 caldata->done_txiqcal_once = false;
1848 caldata->done_txclcal_once = false;
1849 caldata->rtt_hist.num_readings = 0;
1850 }
1851
1852 if (!ath9k_hw_init_cal(ah, chan))
1853 return -EIO;
1854
1855 }
1856 }
1857 ar9003_mci_enable_interrupt(ah);
1858 }
1859
1860 ENABLE_REGWRITE_BUFFER(ah);
1861
1862 ath9k_hw_restore_chainmask(ah);
1863 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1864
1865 REGWRITE_BUFFER_FLUSH(ah);
1866
1867 /*
1868 * For big endian systems turn on swapping for descriptors
1869 */
1870 if (AR_SREV_9100(ah)) {
1871 u32 mask;
1872 mask = REG_READ(ah, AR_CFG);
1873 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1874 ath_dbg(common, ATH_DBG_RESET,
1875 "CFG Byte Swap Set 0x%x\n", mask);
1876 } else {
1877 mask =
1878 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1879 REG_WRITE(ah, AR_CFG, mask);
1880 ath_dbg(common, ATH_DBG_RESET,
1881 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
1882 }
1883 } else {
1884 if (common->bus_ops->ath_bus_type == ATH_USB) {
1885 /* Configure AR9271 target WLAN */
1886 if (AR_SREV_9271(ah))
1887 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1888 else
1889 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1890 }
1891 #ifdef __BIG_ENDIAN
1892 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah))
1893 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0);
1894 else
1895 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1896 #endif
1897 }
1898
1899 if (ah->btcoex_hw.enabled)
1900 ath9k_hw_btcoex_enable(ah);
1901
1902 if (mci && mci_hw->ready) {
1903 /*
1904 * check BT state again to make
1905 * sure it's not changed.
1906 */
1907
1908 ar9003_mci_sync_bt_state(ah);
1909 ar9003_mci_2g5g_switch(ah, true);
1910
1911 if ((mci_hw->bt_state == MCI_BT_AWAKE) &&
1912 (mci_hw->query_bt == true)) {
1913 mci_hw->need_flush_btinfo = true;
1914 }
1915 }
1916
1917 if (AR_SREV_9300_20_OR_LATER(ah)) {
1918 ar9003_hw_bb_watchdog_config(ah);
1919
1920 ar9003_hw_disable_phy_restart(ah);
1921 }
1922
1923 ath9k_hw_apply_gpio_override(ah);
1924
1925 return 0;
1926 }
1927 EXPORT_SYMBOL(ath9k_hw_reset);
1928
1929 /******************************/
1930 /* Power Management (Chipset) */
1931 /******************************/
1932
1933 /*
1934 * Notify Power Mgt is disabled in self-generated frames.
1935 * If requested, force chip to sleep.
1936 */
1937 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
1938 {
1939 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1940 if (setChip) {
1941 if (AR_SREV_9462(ah)) {
1942 REG_WRITE(ah, AR_TIMER_MODE,
1943 REG_READ(ah, AR_TIMER_MODE) & 0xFFFFFF00);
1944 REG_WRITE(ah, AR_NDP2_TIMER_MODE, REG_READ(ah,
1945 AR_NDP2_TIMER_MODE) & 0xFFFFFF00);
1946 REG_WRITE(ah, AR_SLP32_INC,
1947 REG_READ(ah, AR_SLP32_INC) & 0xFFF00000);
1948 /* xxx Required for WLAN only case ? */
1949 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0);
1950 udelay(100);
1951 }
1952
1953 /*
1954 * Clear the RTC force wake bit to allow the
1955 * mac to go to sleep.
1956 */
1957 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
1958
1959 if (AR_SREV_9462(ah))
1960 udelay(100);
1961
1962 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1963 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1964
1965 /* Shutdown chip. Active low */
1966 if (!AR_SREV_5416(ah) &&
1967 !AR_SREV_9271(ah) && !AR_SREV_9462_10(ah)) {
1968 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN);
1969 udelay(2);
1970 }
1971 }
1972
1973 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
1974 if (AR_SREV_9300_20_OR_LATER(ah))
1975 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
1976 }
1977
1978 /*
1979 * Notify Power Management is enabled in self-generating
1980 * frames. If request, set power mode of chip to
1981 * auto/normal. Duration in units of 128us (1/8 TU).
1982 */
1983 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
1984 {
1985 u32 val;
1986
1987 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1988 if (setChip) {
1989 struct ath9k_hw_capabilities *pCap = &ah->caps;
1990
1991 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1992 /* Set WakeOnInterrupt bit; clear ForceWake bit */
1993 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1994 AR_RTC_FORCE_WAKE_ON_INT);
1995 } else {
1996
1997 /* When chip goes into network sleep, it could be waken
1998 * up by MCI_INT interrupt caused by BT's HW messages
1999 * (LNA_xxx, CONT_xxx) which chould be in a very fast
2000 * rate (~100us). This will cause chip to leave and
2001 * re-enter network sleep mode frequently, which in
2002 * consequence will have WLAN MCI HW to generate lots of
2003 * SYS_WAKING and SYS_SLEEPING messages which will make
2004 * BT CPU to busy to process.
2005 */
2006 if (AR_SREV_9462(ah)) {
2007 val = REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_EN) &
2008 ~AR_MCI_INTERRUPT_RX_HW_MSG_MASK;
2009 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, val);
2010 }
2011 /*
2012 * Clear the RTC force wake bit to allow the
2013 * mac to go to sleep.
2014 */
2015 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2016 AR_RTC_FORCE_WAKE_EN);
2017
2018 if (AR_SREV_9462(ah))
2019 udelay(30);
2020 }
2021 }
2022
2023 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
2024 if (AR_SREV_9300_20_OR_LATER(ah))
2025 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
2026 }
2027
2028 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2029 {
2030 u32 val;
2031 int i;
2032
2033 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */
2034 if (AR_SREV_9300_20_OR_LATER(ah)) {
2035 REG_WRITE(ah, AR_WA, ah->WARegVal);
2036 udelay(10);
2037 }
2038
2039 if (setChip) {
2040 if ((REG_READ(ah, AR_RTC_STATUS) &
2041 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2042 if (ath9k_hw_set_reset_reg(ah,
2043 ATH9K_RESET_POWER_ON) != true) {
2044 return false;
2045 }
2046 if (!AR_SREV_9300_20_OR_LATER(ah))
2047 ath9k_hw_init_pll(ah, NULL);
2048 }
2049 if (AR_SREV_9100(ah))
2050 REG_SET_BIT(ah, AR_RTC_RESET,
2051 AR_RTC_RESET_EN);
2052
2053 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2054 AR_RTC_FORCE_WAKE_EN);
2055 udelay(50);
2056
2057 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2058 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2059 if (val == AR_RTC_STATUS_ON)
2060 break;
2061 udelay(50);
2062 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2063 AR_RTC_FORCE_WAKE_EN);
2064 }
2065 if (i == 0) {
2066 ath_err(ath9k_hw_common(ah),
2067 "Failed to wakeup in %uus\n",
2068 POWER_UP_TIME / 20);
2069 return false;
2070 }
2071 }
2072
2073 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2074
2075 return true;
2076 }
2077
2078 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2079 {
2080 struct ath_common *common = ath9k_hw_common(ah);
2081 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
2082 int status = true, setChip = true;
2083 static const char *modes[] = {
2084 "AWAKE",
2085 "FULL-SLEEP",
2086 "NETWORK SLEEP",
2087 "UNDEFINED"
2088 };
2089
2090 if (ah->power_mode == mode)
2091 return status;
2092
2093 ath_dbg(common, ATH_DBG_RESET, "%s -> %s\n",
2094 modes[ah->power_mode], modes[mode]);
2095
2096 switch (mode) {
2097 case ATH9K_PM_AWAKE:
2098 status = ath9k_hw_set_power_awake(ah, setChip);
2099
2100 if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI)
2101 REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2);
2102
2103 break;
2104 case ATH9K_PM_FULL_SLEEP:
2105
2106 if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI) {
2107 if (ar9003_mci_state(ah, MCI_STATE_ENABLE, NULL) &&
2108 (mci->bt_state != MCI_BT_SLEEP) &&
2109 !mci->halted_bt_gpm) {
2110 ath_dbg(common, ATH_DBG_MCI, "MCI halt BT GPM"
2111 "(full_sleep)");
2112 ar9003_mci_send_coex_halt_bt_gpm(ah,
2113 true, true);
2114 }
2115
2116 mci->ready = false;
2117 REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2);
2118 }
2119
2120 ath9k_set_power_sleep(ah, setChip);
2121 ah->chip_fullsleep = true;
2122 break;
2123 case ATH9K_PM_NETWORK_SLEEP:
2124
2125 if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI)
2126 REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2);
2127
2128 ath9k_set_power_network_sleep(ah, setChip);
2129 break;
2130 default:
2131 ath_err(common, "Unknown power mode %u\n", mode);
2132 return false;
2133 }
2134 ah->power_mode = mode;
2135
2136 /*
2137 * XXX: If this warning never comes up after a while then
2138 * simply keep the ATH_DBG_WARN_ON_ONCE() but make
2139 * ath9k_hw_setpower() return type void.
2140 */
2141
2142 if (!(ah->ah_flags & AH_UNPLUGGED))
2143 ATH_DBG_WARN_ON_ONCE(!status);
2144
2145 return status;
2146 }
2147 EXPORT_SYMBOL(ath9k_hw_setpower);
2148
2149 /*******************/
2150 /* Beacon Handling */
2151 /*******************/
2152
2153 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
2154 {
2155 int flags = 0;
2156
2157 ENABLE_REGWRITE_BUFFER(ah);
2158
2159 switch (ah->opmode) {
2160 case NL80211_IFTYPE_ADHOC:
2161 case NL80211_IFTYPE_MESH_POINT:
2162 REG_SET_BIT(ah, AR_TXCFG,
2163 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
2164 REG_WRITE(ah, AR_NEXT_NDP_TIMER, next_beacon +
2165 TU_TO_USEC(ah->atim_window ? ah->atim_window : 1));
2166 flags |= AR_NDP_TIMER_EN;
2167 case NL80211_IFTYPE_AP:
2168 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon);
2169 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon -
2170 TU_TO_USEC(ah->config.dma_beacon_response_time));
2171 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon -
2172 TU_TO_USEC(ah->config.sw_beacon_response_time));
2173 flags |=
2174 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
2175 break;
2176 default:
2177 ath_dbg(ath9k_hw_common(ah), ATH_DBG_BEACON,
2178 "%s: unsupported opmode: %d\n",
2179 __func__, ah->opmode);
2180 return;
2181 break;
2182 }
2183
2184 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period);
2185 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period);
2186 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period);
2187 REG_WRITE(ah, AR_NDP_PERIOD, beacon_period);
2188
2189 REGWRITE_BUFFER_FLUSH(ah);
2190
2191 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
2192 }
2193 EXPORT_SYMBOL(ath9k_hw_beaconinit);
2194
2195 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
2196 const struct ath9k_beacon_state *bs)
2197 {
2198 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
2199 struct ath9k_hw_capabilities *pCap = &ah->caps;
2200 struct ath_common *common = ath9k_hw_common(ah);
2201
2202 ENABLE_REGWRITE_BUFFER(ah);
2203
2204 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
2205
2206 REG_WRITE(ah, AR_BEACON_PERIOD,
2207 TU_TO_USEC(bs->bs_intval));
2208 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
2209 TU_TO_USEC(bs->bs_intval));
2210
2211 REGWRITE_BUFFER_FLUSH(ah);
2212
2213 REG_RMW_FIELD(ah, AR_RSSI_THR,
2214 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
2215
2216 beaconintval = bs->bs_intval;
2217
2218 if (bs->bs_sleepduration > beaconintval)
2219 beaconintval = bs->bs_sleepduration;
2220
2221 dtimperiod = bs->bs_dtimperiod;
2222 if (bs->bs_sleepduration > dtimperiod)
2223 dtimperiod = bs->bs_sleepduration;
2224
2225 if (beaconintval == dtimperiod)
2226 nextTbtt = bs->bs_nextdtim;
2227 else
2228 nextTbtt = bs->bs_nexttbtt;
2229
2230 ath_dbg(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
2231 ath_dbg(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
2232 ath_dbg(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
2233 ath_dbg(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
2234
2235 ENABLE_REGWRITE_BUFFER(ah);
2236
2237 REG_WRITE(ah, AR_NEXT_DTIM,
2238 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
2239 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
2240
2241 REG_WRITE(ah, AR_SLEEP1,
2242 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
2243 | AR_SLEEP1_ASSUME_DTIM);
2244
2245 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
2246 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
2247 else
2248 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
2249
2250 REG_WRITE(ah, AR_SLEEP2,
2251 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
2252
2253 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
2254 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
2255
2256 REGWRITE_BUFFER_FLUSH(ah);
2257
2258 REG_SET_BIT(ah, AR_TIMER_MODE,
2259 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
2260 AR_DTIM_TIMER_EN);
2261
2262 /* TSF Out of Range Threshold */
2263 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
2264 }
2265 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
2266
2267 /*******************/
2268 /* HW Capabilities */
2269 /*******************/
2270
2271 static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask)
2272 {
2273 eeprom_chainmask &= chip_chainmask;
2274 if (eeprom_chainmask)
2275 return eeprom_chainmask;
2276 else
2277 return chip_chainmask;
2278 }
2279
2280 /**
2281 * ath9k_hw_dfs_tested - checks if DFS has been tested with used chipset
2282 * @ah: the atheros hardware data structure
2283 *
2284 * We enable DFS support upstream on chipsets which have passed a series
2285 * of tests. The testing requirements are going to be documented. Desired
2286 * test requirements are documented at:
2287 *
2288 * http://wireless.kernel.org/en/users/Drivers/ath9k/dfs
2289 *
2290 * Once a new chipset gets properly tested an individual commit can be used
2291 * to document the testing for DFS for that chipset.
2292 */
2293 static bool ath9k_hw_dfs_tested(struct ath_hw *ah)
2294 {
2295
2296 switch (ah->hw_version.macVersion) {
2297 /* AR9580 will likely be our first target to get testing on */
2298 case AR_SREV_VERSION_9580:
2299 default:
2300 return false;
2301 }
2302 }
2303
2304 int ath9k_hw_fill_cap_info(struct ath_hw *ah)
2305 {
2306 struct ath9k_hw_capabilities *pCap = &ah->caps;
2307 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2308 struct ath_common *common = ath9k_hw_common(ah);
2309 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
2310 unsigned int chip_chainmask;
2311
2312 u16 eeval;
2313 u8 ant_div_ctl1, tx_chainmask, rx_chainmask;
2314
2315 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
2316 regulatory->current_rd = eeval;
2317
2318 if (ah->opmode != NL80211_IFTYPE_AP &&
2319 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
2320 if (regulatory->current_rd == 0x64 ||
2321 regulatory->current_rd == 0x65)
2322 regulatory->current_rd += 5;
2323 else if (regulatory->current_rd == 0x41)
2324 regulatory->current_rd = 0x43;
2325 ath_dbg(common, ATH_DBG_REGULATORY,
2326 "regdomain mapped to 0x%x\n", regulatory->current_rd);
2327 }
2328
2329 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
2330 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
2331 ath_err(common,
2332 "no band has been marked as supported in EEPROM\n");
2333 return -EINVAL;
2334 }
2335
2336 if (eeval & AR5416_OPFLAGS_11A)
2337 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
2338
2339 if (eeval & AR5416_OPFLAGS_11G)
2340 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
2341
2342 if (AR_SREV_9485(ah) || AR_SREV_9285(ah) || AR_SREV_9330(ah))
2343 chip_chainmask = 1;
2344 else if (AR_SREV_9462(ah))
2345 chip_chainmask = 3;
2346 else if (!AR_SREV_9280_20_OR_LATER(ah))
2347 chip_chainmask = 7;
2348 else if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9340(ah))
2349 chip_chainmask = 3;
2350 else
2351 chip_chainmask = 7;
2352
2353 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
2354 /*
2355 * For AR9271 we will temporarilly uses the rx chainmax as read from
2356 * the EEPROM.
2357 */
2358 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
2359 !(eeval & AR5416_OPFLAGS_11A) &&
2360 !(AR_SREV_9271(ah)))
2361 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
2362 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
2363 else if (AR_SREV_9100(ah))
2364 pCap->rx_chainmask = 0x7;
2365 else
2366 /* Use rx_chainmask from EEPROM. */
2367 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
2368
2369 pCap->tx_chainmask = fixup_chainmask(chip_chainmask, pCap->tx_chainmask);
2370 pCap->rx_chainmask = fixup_chainmask(chip_chainmask, pCap->rx_chainmask);
2371 ah->txchainmask = pCap->tx_chainmask;
2372 ah->rxchainmask = pCap->rx_chainmask;
2373
2374 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
2375
2376 /* enable key search for every frame in an aggregate */
2377 if (AR_SREV_9300_20_OR_LATER(ah))
2378 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
2379
2380 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
2381
2382 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
2383 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2384 else
2385 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
2386
2387 if (AR_SREV_9271(ah))
2388 pCap->num_gpio_pins = AR9271_NUM_GPIO;
2389 else if (AR_DEVID_7010(ah))
2390 pCap->num_gpio_pins = AR7010_NUM_GPIO;
2391 else if (AR_SREV_9300_20_OR_LATER(ah))
2392 pCap->num_gpio_pins = AR9300_NUM_GPIO;
2393 else if (AR_SREV_9287_11_OR_LATER(ah))
2394 pCap->num_gpio_pins = AR9287_NUM_GPIO;
2395 else if (AR_SREV_9285_12_OR_LATER(ah))
2396 pCap->num_gpio_pins = AR9285_NUM_GPIO;
2397 else if (AR_SREV_9280_20_OR_LATER(ah))
2398 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2399 else
2400 pCap->num_gpio_pins = AR_NUM_GPIO;
2401
2402 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
2403 pCap->hw_caps |= ATH9K_HW_CAP_CST;
2404 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
2405 } else {
2406 pCap->rts_aggr_limit = (8 * 1024);
2407 }
2408
2409 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2410 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2411 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2412 ah->rfkill_gpio =
2413 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2414 ah->rfkill_polarity =
2415 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
2416
2417 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
2418 }
2419 #endif
2420 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
2421 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2422 else
2423 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
2424
2425 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
2426 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2427 else
2428 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
2429
2430 if (common->btcoex_enabled) {
2431 if (AR_SREV_9462(ah))
2432 btcoex_hw->scheme = ATH_BTCOEX_CFG_MCI;
2433 else if (AR_SREV_9300_20_OR_LATER(ah)) {
2434 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
2435 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO_9300;
2436 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO_9300;
2437 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO_9300;
2438 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
2439 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO_9280;
2440 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO_9280;
2441
2442 if (AR_SREV_9285(ah)) {
2443 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
2444 btcoex_hw->btpriority_gpio =
2445 ATH_BTPRIORITY_GPIO_9285;
2446 } else {
2447 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
2448 }
2449 }
2450 } else {
2451 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
2452 }
2453
2454 if (AR_SREV_9300_20_OR_LATER(ah)) {
2455 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
2456 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah))
2457 pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
2458
2459 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2460 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2461 pCap->rx_status_len = sizeof(struct ar9003_rxs);
2462 pCap->tx_desc_len = sizeof(struct ar9003_txc);
2463 pCap->txs_len = sizeof(struct ar9003_txs);
2464 if (!ah->config.paprd_disable &&
2465 ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
2466 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
2467 } else {
2468 pCap->tx_desc_len = sizeof(struct ath_desc);
2469 if (AR_SREV_9280_20(ah))
2470 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
2471 }
2472
2473 if (AR_SREV_9300_20_OR_LATER(ah))
2474 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2475
2476 if (AR_SREV_9300_20_OR_LATER(ah))
2477 ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
2478
2479 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
2480 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
2481
2482 if (AR_SREV_9285(ah))
2483 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
2484 ant_div_ctl1 =
2485 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2486 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1))
2487 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2488 }
2489 if (AR_SREV_9300_20_OR_LATER(ah)) {
2490 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
2491 pCap->hw_caps |= ATH9K_HW_CAP_APM;
2492 }
2493
2494
2495 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
2496 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2497 /*
2498 * enable the diversity-combining algorithm only when
2499 * both enable_lna_div and enable_fast_div are set
2500 * Table for Diversity
2501 * ant_div_alt_lnaconf bit 0-1
2502 * ant_div_main_lnaconf bit 2-3
2503 * ant_div_alt_gaintb bit 4
2504 * ant_div_main_gaintb bit 5
2505 * enable_ant_div_lnadiv bit 6
2506 * enable_ant_fast_div bit 7
2507 */
2508 if ((ant_div_ctl1 >> 0x6) == 0x3)
2509 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2510 }
2511
2512 if (AR_SREV_9485_10(ah)) {
2513 pCap->pcie_lcr_extsync_en = true;
2514 pCap->pcie_lcr_offset = 0x80;
2515 }
2516
2517 if (ath9k_hw_dfs_tested(ah))
2518 pCap->hw_caps |= ATH9K_HW_CAP_DFS;
2519
2520 tx_chainmask = pCap->tx_chainmask;
2521 rx_chainmask = pCap->rx_chainmask;
2522 while (tx_chainmask || rx_chainmask) {
2523 if (tx_chainmask & BIT(0))
2524 pCap->max_txchains++;
2525 if (rx_chainmask & BIT(0))
2526 pCap->max_rxchains++;
2527
2528 tx_chainmask >>= 1;
2529 rx_chainmask >>= 1;
2530 }
2531
2532 if (AR_SREV_9300_20_OR_LATER(ah)) {
2533 ah->enabled_cals |= TX_IQ_CAL;
2534 if (AR_SREV_9485_OR_LATER(ah))
2535 ah->enabled_cals |= TX_IQ_ON_AGC_CAL;
2536 }
2537 if (AR_SREV_9462(ah))
2538 pCap->hw_caps |= ATH9K_HW_CAP_RTT | ATH9K_HW_CAP_MCI;
2539
2540 return 0;
2541 }
2542
2543 /****************************/
2544 /* GPIO / RFKILL / Antennae */
2545 /****************************/
2546
2547 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
2548 u32 gpio, u32 type)
2549 {
2550 int addr;
2551 u32 gpio_shift, tmp;
2552
2553 if (gpio > 11)
2554 addr = AR_GPIO_OUTPUT_MUX3;
2555 else if (gpio > 5)
2556 addr = AR_GPIO_OUTPUT_MUX2;
2557 else
2558 addr = AR_GPIO_OUTPUT_MUX1;
2559
2560 gpio_shift = (gpio % 6) * 5;
2561
2562 if (AR_SREV_9280_20_OR_LATER(ah)
2563 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2564 REG_RMW(ah, addr, (type << gpio_shift),
2565 (0x1f << gpio_shift));
2566 } else {
2567 tmp = REG_READ(ah, addr);
2568 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2569 tmp &= ~(0x1f << gpio_shift);
2570 tmp |= (type << gpio_shift);
2571 REG_WRITE(ah, addr, tmp);
2572 }
2573 }
2574
2575 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
2576 {
2577 u32 gpio_shift;
2578
2579 BUG_ON(gpio >= ah->caps.num_gpio_pins);
2580
2581 if (AR_DEVID_7010(ah)) {
2582 gpio_shift = gpio;
2583 REG_RMW(ah, AR7010_GPIO_OE,
2584 (AR7010_GPIO_OE_AS_INPUT << gpio_shift),
2585 (AR7010_GPIO_OE_MASK << gpio_shift));
2586 return;
2587 }
2588
2589 gpio_shift = gpio << 1;
2590 REG_RMW(ah,
2591 AR_GPIO_OE_OUT,
2592 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2593 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2594 }
2595 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
2596
2597 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
2598 {
2599 #define MS_REG_READ(x, y) \
2600 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2601
2602 if (gpio >= ah->caps.num_gpio_pins)
2603 return 0xffffffff;
2604
2605 if (AR_DEVID_7010(ah)) {
2606 u32 val;
2607 val = REG_READ(ah, AR7010_GPIO_IN);
2608 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0;
2609 } else if (AR_SREV_9300_20_OR_LATER(ah))
2610 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) &
2611 AR_GPIO_BIT(gpio)) != 0;
2612 else if (AR_SREV_9271(ah))
2613 return MS_REG_READ(AR9271, gpio) != 0;
2614 else if (AR_SREV_9287_11_OR_LATER(ah))
2615 return MS_REG_READ(AR9287, gpio) != 0;
2616 else if (AR_SREV_9285_12_OR_LATER(ah))
2617 return MS_REG_READ(AR9285, gpio) != 0;
2618 else if (AR_SREV_9280_20_OR_LATER(ah))
2619 return MS_REG_READ(AR928X, gpio) != 0;
2620 else
2621 return MS_REG_READ(AR, gpio) != 0;
2622 }
2623 EXPORT_SYMBOL(ath9k_hw_gpio_get);
2624
2625 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
2626 u32 ah_signal_type)
2627 {
2628 u32 gpio_shift;
2629
2630 if (AR_DEVID_7010(ah)) {
2631 gpio_shift = gpio;
2632 REG_RMW(ah, AR7010_GPIO_OE,
2633 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift),
2634 (AR7010_GPIO_OE_MASK << gpio_shift));
2635 return;
2636 }
2637
2638 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
2639 gpio_shift = 2 * gpio;
2640 REG_RMW(ah,
2641 AR_GPIO_OE_OUT,
2642 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2643 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2644 }
2645 EXPORT_SYMBOL(ath9k_hw_cfg_output);
2646
2647 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
2648 {
2649 if (AR_DEVID_7010(ah)) {
2650 val = val ? 0 : 1;
2651 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio),
2652 AR_GPIO_BIT(gpio));
2653 return;
2654 }
2655
2656 if (AR_SREV_9271(ah))
2657 val = ~val;
2658
2659 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2660 AR_GPIO_BIT(gpio));
2661 }
2662 EXPORT_SYMBOL(ath9k_hw_set_gpio);
2663
2664 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
2665 {
2666 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
2667 }
2668 EXPORT_SYMBOL(ath9k_hw_getdefantenna);
2669
2670 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
2671 {
2672 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
2673 }
2674 EXPORT_SYMBOL(ath9k_hw_setantenna);
2675
2676 /*********************/
2677 /* General Operation */
2678 /*********************/
2679
2680 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
2681 {
2682 u32 bits = REG_READ(ah, AR_RX_FILTER);
2683 u32 phybits = REG_READ(ah, AR_PHY_ERR);
2684
2685 if (phybits & AR_PHY_ERR_RADAR)
2686 bits |= ATH9K_RX_FILTER_PHYRADAR;
2687 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2688 bits |= ATH9K_RX_FILTER_PHYERR;
2689
2690 return bits;
2691 }
2692 EXPORT_SYMBOL(ath9k_hw_getrxfilter);
2693
2694 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
2695 {
2696 u32 phybits;
2697
2698 ENABLE_REGWRITE_BUFFER(ah);
2699
2700 if (AR_SREV_9462(ah))
2701 bits |= ATH9K_RX_FILTER_CONTROL_WRAPPER;
2702
2703 REG_WRITE(ah, AR_RX_FILTER, bits);
2704
2705 phybits = 0;
2706 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2707 phybits |= AR_PHY_ERR_RADAR;
2708 if (bits & ATH9K_RX_FILTER_PHYERR)
2709 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2710 REG_WRITE(ah, AR_PHY_ERR, phybits);
2711
2712 if (phybits)
2713 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
2714 else
2715 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
2716
2717 REGWRITE_BUFFER_FLUSH(ah);
2718 }
2719 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
2720
2721 bool ath9k_hw_phy_disable(struct ath_hw *ah)
2722 {
2723 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2724 return false;
2725
2726 ath9k_hw_init_pll(ah, NULL);
2727 return true;
2728 }
2729 EXPORT_SYMBOL(ath9k_hw_phy_disable);
2730
2731 bool ath9k_hw_disable(struct ath_hw *ah)
2732 {
2733 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2734 return false;
2735
2736 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2737 return false;
2738
2739 ath9k_hw_init_pll(ah, NULL);
2740 return true;
2741 }
2742 EXPORT_SYMBOL(ath9k_hw_disable);
2743
2744 static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan)
2745 {
2746 enum eeprom_param gain_param;
2747
2748 if (IS_CHAN_2GHZ(chan))
2749 gain_param = EEP_ANTENNA_GAIN_2G;
2750 else
2751 gain_param = EEP_ANTENNA_GAIN_5G;
2752
2753 return ah->eep_ops->get_eeprom(ah, gain_param);
2754 }
2755
2756 void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan)
2757 {
2758 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2759 struct ieee80211_channel *channel;
2760 int chan_pwr, new_pwr, max_gain;
2761 int ant_gain, ant_reduction = 0;
2762
2763 if (!chan)
2764 return;
2765
2766 channel = chan->chan;
2767 chan_pwr = min_t(int, channel->max_power * 2, MAX_RATE_POWER);
2768 new_pwr = min_t(int, chan_pwr, reg->power_limit);
2769 max_gain = chan_pwr - new_pwr + channel->max_antenna_gain * 2;
2770
2771 ant_gain = get_antenna_gain(ah, chan);
2772 if (ant_gain > max_gain)
2773 ant_reduction = ant_gain - max_gain;
2774
2775 ah->eep_ops->set_txpower(ah, chan,
2776 ath9k_regd_get_ctl(reg, chan),
2777 ant_reduction, new_pwr, false);
2778 }
2779
2780 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
2781 {
2782 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2783 struct ath9k_channel *chan = ah->curchan;
2784 struct ieee80211_channel *channel = chan->chan;
2785
2786 reg->power_limit = min_t(u32, limit, MAX_RATE_POWER);
2787 if (test)
2788 channel->max_power = MAX_RATE_POWER / 2;
2789
2790 ath9k_hw_apply_txpower(ah, chan);
2791
2792 if (test)
2793 channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2);
2794 }
2795 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
2796
2797 void ath9k_hw_setopmode(struct ath_hw *ah)
2798 {
2799 ath9k_hw_set_operating_mode(ah, ah->opmode);
2800 }
2801 EXPORT_SYMBOL(ath9k_hw_setopmode);
2802
2803 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
2804 {
2805 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2806 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
2807 }
2808 EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
2809
2810 void ath9k_hw_write_associd(struct ath_hw *ah)
2811 {
2812 struct ath_common *common = ath9k_hw_common(ah);
2813
2814 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2815 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2816 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2817 }
2818 EXPORT_SYMBOL(ath9k_hw_write_associd);
2819
2820 #define ATH9K_MAX_TSF_READ 10
2821
2822 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
2823 {
2824 u32 tsf_lower, tsf_upper1, tsf_upper2;
2825 int i;
2826
2827 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2828 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2829 tsf_lower = REG_READ(ah, AR_TSF_L32);
2830 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2831 if (tsf_upper2 == tsf_upper1)
2832 break;
2833 tsf_upper1 = tsf_upper2;
2834 }
2835
2836 WARN_ON( i == ATH9K_MAX_TSF_READ );
2837
2838 return (((u64)tsf_upper1 << 32) | tsf_lower);
2839 }
2840 EXPORT_SYMBOL(ath9k_hw_gettsf64);
2841
2842 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
2843 {
2844 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
2845 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
2846 }
2847 EXPORT_SYMBOL(ath9k_hw_settsf64);
2848
2849 void ath9k_hw_reset_tsf(struct ath_hw *ah)
2850 {
2851 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2852 AH_TSF_WRITE_TIMEOUT))
2853 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
2854 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
2855
2856 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2857 }
2858 EXPORT_SYMBOL(ath9k_hw_reset_tsf);
2859
2860 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
2861 {
2862 if (setting)
2863 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
2864 else
2865 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
2866 }
2867 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
2868
2869 void ath9k_hw_set11nmac2040(struct ath_hw *ah)
2870 {
2871 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
2872 u32 macmode;
2873
2874 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
2875 macmode = AR_2040_JOINED_RX_CLEAR;
2876 else
2877 macmode = 0;
2878
2879 REG_WRITE(ah, AR_2040_MODE, macmode);
2880 }
2881
2882 /* HW Generic timers configuration */
2883
2884 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2885 {
2886 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2887 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2888 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2889 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2890 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2891 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2892 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2893 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2894 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2895 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2896 AR_NDP2_TIMER_MODE, 0x0002},
2897 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2898 AR_NDP2_TIMER_MODE, 0x0004},
2899 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2900 AR_NDP2_TIMER_MODE, 0x0008},
2901 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2902 AR_NDP2_TIMER_MODE, 0x0010},
2903 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2904 AR_NDP2_TIMER_MODE, 0x0020},
2905 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2906 AR_NDP2_TIMER_MODE, 0x0040},
2907 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2908 AR_NDP2_TIMER_MODE, 0x0080}
2909 };
2910
2911 /* HW generic timer primitives */
2912
2913 /* compute and clear index of rightmost 1 */
2914 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
2915 {
2916 u32 b;
2917
2918 b = *mask;
2919 b &= (0-b);
2920 *mask &= ~b;
2921 b *= debruijn32;
2922 b >>= 27;
2923
2924 return timer_table->gen_timer_index[b];
2925 }
2926
2927 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
2928 {
2929 return REG_READ(ah, AR_TSF_L32);
2930 }
2931 EXPORT_SYMBOL(ath9k_hw_gettsf32);
2932
2933 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2934 void (*trigger)(void *),
2935 void (*overflow)(void *),
2936 void *arg,
2937 u8 timer_index)
2938 {
2939 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2940 struct ath_gen_timer *timer;
2941
2942 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
2943
2944 if (timer == NULL) {
2945 ath_err(ath9k_hw_common(ah),
2946 "Failed to allocate memory for hw timer[%d]\n",
2947 timer_index);
2948 return NULL;
2949 }
2950
2951 /* allocate a hardware generic timer slot */
2952 timer_table->timers[timer_index] = timer;
2953 timer->index = timer_index;
2954 timer->trigger = trigger;
2955 timer->overflow = overflow;
2956 timer->arg = arg;
2957
2958 return timer;
2959 }
2960 EXPORT_SYMBOL(ath_gen_timer_alloc);
2961
2962 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2963 struct ath_gen_timer *timer,
2964 u32 trig_timeout,
2965 u32 timer_period)
2966 {
2967 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2968 u32 tsf, timer_next;
2969
2970 BUG_ON(!timer_period);
2971
2972 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
2973
2974 tsf = ath9k_hw_gettsf32(ah);
2975
2976 timer_next = tsf + trig_timeout;
2977
2978 ath_dbg(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
2979 "current tsf %x period %x timer_next %x\n",
2980 tsf, timer_period, timer_next);
2981
2982 /*
2983 * Program generic timer registers
2984 */
2985 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
2986 timer_next);
2987 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
2988 timer_period);
2989 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2990 gen_tmr_configuration[timer->index].mode_mask);
2991
2992 if (AR_SREV_9462(ah)) {
2993 /*
2994 * Starting from AR9462, each generic timer can select which tsf
2995 * to use. But we still follow the old rule, 0 - 7 use tsf and
2996 * 8 - 15 use tsf2.
2997 */
2998 if ((timer->index < AR_GEN_TIMER_BANK_1_LEN))
2999 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3000 (1 << timer->index));
3001 else
3002 REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3003 (1 << timer->index));
3004 }
3005
3006 /* Enable both trigger and thresh interrupt masks */
3007 REG_SET_BIT(ah, AR_IMR_S5,
3008 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3009 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3010 }
3011 EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
3012
3013 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
3014 {
3015 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3016
3017 if ((timer->index < AR_FIRST_NDP_TIMER) ||
3018 (timer->index >= ATH_MAX_GEN_TIMER)) {
3019 return;
3020 }
3021
3022 /* Clear generic timer enable bits. */
3023 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3024 gen_tmr_configuration[timer->index].mode_mask);
3025
3026 /* Disable both trigger and thresh interrupt masks */
3027 REG_CLR_BIT(ah, AR_IMR_S5,
3028 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3029 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3030
3031 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
3032 }
3033 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
3034
3035 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
3036 {
3037 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3038
3039 /* free the hardware generic timer slot */
3040 timer_table->timers[timer->index] = NULL;
3041 kfree(timer);
3042 }
3043 EXPORT_SYMBOL(ath_gen_timer_free);
3044
3045 /*
3046 * Generic Timer Interrupts handling
3047 */
3048 void ath_gen_timer_isr(struct ath_hw *ah)
3049 {
3050 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3051 struct ath_gen_timer *timer;
3052 struct ath_common *common = ath9k_hw_common(ah);
3053 u32 trigger_mask, thresh_mask, index;
3054
3055 /* get hardware generic timer interrupt status */
3056 trigger_mask = ah->intr_gen_timer_trigger;
3057 thresh_mask = ah->intr_gen_timer_thresh;
3058 trigger_mask &= timer_table->timer_mask.val;
3059 thresh_mask &= timer_table->timer_mask.val;
3060
3061 trigger_mask &= ~thresh_mask;
3062
3063 while (thresh_mask) {
3064 index = rightmost_index(timer_table, &thresh_mask);
3065 timer = timer_table->timers[index];
3066 BUG_ON(!timer);
3067 ath_dbg(common, ATH_DBG_HWTIMER,
3068 "TSF overflow for Gen timer %d\n", index);
3069 timer->overflow(timer->arg);
3070 }
3071
3072 while (trigger_mask) {
3073 index = rightmost_index(timer_table, &trigger_mask);
3074 timer = timer_table->timers[index];
3075 BUG_ON(!timer);
3076 ath_dbg(common, ATH_DBG_HWTIMER,
3077 "Gen timer[%d] trigger\n", index);
3078 timer->trigger(timer->arg);
3079 }
3080 }
3081 EXPORT_SYMBOL(ath_gen_timer_isr);
3082
3083 /********/
3084 /* HTC */
3085 /********/
3086
3087 void ath9k_hw_htc_resetinit(struct ath_hw *ah)
3088 {
3089 ah->htc_reset_init = true;
3090 }
3091 EXPORT_SYMBOL(ath9k_hw_htc_resetinit);
3092
3093 static struct {
3094 u32 version;
3095 const char * name;
3096 } ath_mac_bb_names[] = {
3097 /* Devices with external radios */
3098 { AR_SREV_VERSION_5416_PCI, "5416" },
3099 { AR_SREV_VERSION_5416_PCIE, "5418" },
3100 { AR_SREV_VERSION_9100, "9100" },
3101 { AR_SREV_VERSION_9160, "9160" },
3102 /* Single-chip solutions */
3103 { AR_SREV_VERSION_9280, "9280" },
3104 { AR_SREV_VERSION_9285, "9285" },
3105 { AR_SREV_VERSION_9287, "9287" },
3106 { AR_SREV_VERSION_9271, "9271" },
3107 { AR_SREV_VERSION_9300, "9300" },
3108 { AR_SREV_VERSION_9330, "9330" },
3109 { AR_SREV_VERSION_9340, "9340" },
3110 { AR_SREV_VERSION_9485, "9485" },
3111 { AR_SREV_VERSION_9462, "9462" },
3112 };
3113
3114 /* For devices with external radios */
3115 static struct {
3116 u16 version;
3117 const char * name;
3118 } ath_rf_names[] = {
3119 { 0, "5133" },
3120 { AR_RAD5133_SREV_MAJOR, "5133" },
3121 { AR_RAD5122_SREV_MAJOR, "5122" },
3122 { AR_RAD2133_SREV_MAJOR, "2133" },
3123 { AR_RAD2122_SREV_MAJOR, "2122" }
3124 };
3125
3126 /*
3127 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3128 */
3129 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
3130 {
3131 int i;
3132
3133 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3134 if (ath_mac_bb_names[i].version == mac_bb_version) {
3135 return ath_mac_bb_names[i].name;
3136 }
3137 }
3138
3139 return "????";
3140 }
3141
3142 /*
3143 * Return the RF name. "????" is returned if the RF is unknown.
3144 * Used for devices with external radios.
3145 */
3146 static const char *ath9k_hw_rf_name(u16 rf_version)
3147 {
3148 int i;
3149
3150 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3151 if (ath_rf_names[i].version == rf_version) {
3152 return ath_rf_names[i].name;
3153 }
3154 }
3155
3156 return "????";
3157 }
3158
3159 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
3160 {
3161 int used;
3162
3163 /* chipsets >= AR9280 are single-chip */
3164 if (AR_SREV_9280_20_OR_LATER(ah)) {
3165 used = snprintf(hw_name, len,
3166 "Atheros AR%s Rev:%x",
3167 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3168 ah->hw_version.macRev);
3169 }
3170 else {
3171 used = snprintf(hw_name, len,
3172 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3173 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3174 ah->hw_version.macRev,
3175 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
3176 AR_RADIO_SREV_MAJOR)),
3177 ah->hw_version.phyRev);
3178 }
3179
3180 hw_name[used] = '\0';
3181 }
3182 EXPORT_SYMBOL(ath9k_hw_name);
Linux kernel - Deliverables
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