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ath9k: Initialize and configure tx status for EDMA
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / hw.c
1 /*
2 * Copyright (c) 2008-2010 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/io.h>
18 #include <asm/unaligned.h>
19
20 #include "hw.h"
21 #include "hw-ops.h"
22 #include "rc.h"
23 #include "ar9003_mac.h"
24
25 #define ATH9K_CLOCK_RATE_CCK 22
26 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
27 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
28
29 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
30
31 MODULE_AUTHOR("Atheros Communications");
32 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
33 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
34 MODULE_LICENSE("Dual BSD/GPL");
35
36 static int __init ath9k_init(void)
37 {
38 return 0;
39 }
40 module_init(ath9k_init);
41
42 static void __exit ath9k_exit(void)
43 {
44 return;
45 }
46 module_exit(ath9k_exit);
47
48 /* Private hardware callbacks */
49
50 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
51 {
52 ath9k_hw_private_ops(ah)->init_cal_settings(ah);
53 }
54
55 static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
56 {
57 ath9k_hw_private_ops(ah)->init_mode_regs(ah);
58 }
59
60 static bool ath9k_hw_macversion_supported(struct ath_hw *ah)
61 {
62 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
63
64 return priv_ops->macversion_supported(ah->hw_version.macVersion);
65 }
66
67 static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
68 struct ath9k_channel *chan)
69 {
70 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
71 }
72
73 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
74 {
75 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
76 return;
77
78 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
79 }
80
81 /********************/
82 /* Helper Functions */
83 /********************/
84
85 static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
86 {
87 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
88
89 if (!ah->curchan) /* should really check for CCK instead */
90 return usecs *ATH9K_CLOCK_RATE_CCK;
91 if (conf->channel->band == IEEE80211_BAND_2GHZ)
92 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
93 return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
94 }
95
96 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
97 {
98 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
99
100 if (conf_is_ht40(conf))
101 return ath9k_hw_mac_clks(ah, usecs) * 2;
102 else
103 return ath9k_hw_mac_clks(ah, usecs);
104 }
105
106 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
107 {
108 int i;
109
110 BUG_ON(timeout < AH_TIME_QUANTUM);
111
112 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
113 if ((REG_READ(ah, reg) & mask) == val)
114 return true;
115
116 udelay(AH_TIME_QUANTUM);
117 }
118
119 ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
120 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
121 timeout, reg, REG_READ(ah, reg), mask, val);
122
123 return false;
124 }
125 EXPORT_SYMBOL(ath9k_hw_wait);
126
127 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
128 {
129 u32 retval;
130 int i;
131
132 for (i = 0, retval = 0; i < n; i++) {
133 retval = (retval << 1) | (val & 1);
134 val >>= 1;
135 }
136 return retval;
137 }
138
139 bool ath9k_get_channel_edges(struct ath_hw *ah,
140 u16 flags, u16 *low,
141 u16 *high)
142 {
143 struct ath9k_hw_capabilities *pCap = &ah->caps;
144
145 if (flags & CHANNEL_5GHZ) {
146 *low = pCap->low_5ghz_chan;
147 *high = pCap->high_5ghz_chan;
148 return true;
149 }
150 if ((flags & CHANNEL_2GHZ)) {
151 *low = pCap->low_2ghz_chan;
152 *high = pCap->high_2ghz_chan;
153 return true;
154 }
155 return false;
156 }
157
158 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
159 u8 phy, int kbps,
160 u32 frameLen, u16 rateix,
161 bool shortPreamble)
162 {
163 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
164
165 if (kbps == 0)
166 return 0;
167
168 switch (phy) {
169 case WLAN_RC_PHY_CCK:
170 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
171 if (shortPreamble)
172 phyTime >>= 1;
173 numBits = frameLen << 3;
174 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
175 break;
176 case WLAN_RC_PHY_OFDM:
177 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
178 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
179 numBits = OFDM_PLCP_BITS + (frameLen << 3);
180 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
181 txTime = OFDM_SIFS_TIME_QUARTER
182 + OFDM_PREAMBLE_TIME_QUARTER
183 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
184 } else if (ah->curchan &&
185 IS_CHAN_HALF_RATE(ah->curchan)) {
186 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
187 numBits = OFDM_PLCP_BITS + (frameLen << 3);
188 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
189 txTime = OFDM_SIFS_TIME_HALF +
190 OFDM_PREAMBLE_TIME_HALF
191 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
192 } else {
193 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
194 numBits = OFDM_PLCP_BITS + (frameLen << 3);
195 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
196 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
197 + (numSymbols * OFDM_SYMBOL_TIME);
198 }
199 break;
200 default:
201 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
202 "Unknown phy %u (rate ix %u)\n", phy, rateix);
203 txTime = 0;
204 break;
205 }
206
207 return txTime;
208 }
209 EXPORT_SYMBOL(ath9k_hw_computetxtime);
210
211 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
212 struct ath9k_channel *chan,
213 struct chan_centers *centers)
214 {
215 int8_t extoff;
216
217 if (!IS_CHAN_HT40(chan)) {
218 centers->ctl_center = centers->ext_center =
219 centers->synth_center = chan->channel;
220 return;
221 }
222
223 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
224 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
225 centers->synth_center =
226 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
227 extoff = 1;
228 } else {
229 centers->synth_center =
230 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
231 extoff = -1;
232 }
233
234 centers->ctl_center =
235 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
236 /* 25 MHz spacing is supported by hw but not on upper layers */
237 centers->ext_center =
238 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
239 }
240
241 /******************/
242 /* Chip Revisions */
243 /******************/
244
245 static void ath9k_hw_read_revisions(struct ath_hw *ah)
246 {
247 u32 val;
248
249 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
250
251 if (val == 0xFF) {
252 val = REG_READ(ah, AR_SREV);
253 ah->hw_version.macVersion =
254 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
255 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
256 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
257 } else {
258 if (!AR_SREV_9100(ah))
259 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
260
261 ah->hw_version.macRev = val & AR_SREV_REVISION;
262
263 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
264 ah->is_pciexpress = true;
265 }
266 }
267
268 /************************************/
269 /* HW Attach, Detach, Init Routines */
270 /************************************/
271
272 static void ath9k_hw_disablepcie(struct ath_hw *ah)
273 {
274 if (AR_SREV_9100(ah))
275 return;
276
277 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
278 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
279 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
280 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
281 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
282 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
283 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
284 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
285 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
286
287 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
288 }
289
290 /* This should work for all families including legacy */
291 static bool ath9k_hw_chip_test(struct ath_hw *ah)
292 {
293 struct ath_common *common = ath9k_hw_common(ah);
294 u32 regAddr[2] = { AR_STA_ID0 };
295 u32 regHold[2];
296 u32 patternData[4] = { 0x55555555,
297 0xaaaaaaaa,
298 0x66666666,
299 0x99999999 };
300 int i, j, loop_max;
301
302 if (!AR_SREV_9300_20_OR_LATER(ah)) {
303 loop_max = 2;
304 regAddr[1] = AR_PHY_BASE + (8 << 2);
305 } else
306 loop_max = 1;
307
308 for (i = 0; i < loop_max; i++) {
309 u32 addr = regAddr[i];
310 u32 wrData, rdData;
311
312 regHold[i] = REG_READ(ah, addr);
313 for (j = 0; j < 0x100; j++) {
314 wrData = (j << 16) | j;
315 REG_WRITE(ah, addr, wrData);
316 rdData = REG_READ(ah, addr);
317 if (rdData != wrData) {
318 ath_print(common, ATH_DBG_FATAL,
319 "address test failed "
320 "addr: 0x%08x - wr:0x%08x != "
321 "rd:0x%08x\n",
322 addr, wrData, rdData);
323 return false;
324 }
325 }
326 for (j = 0; j < 4; j++) {
327 wrData = patternData[j];
328 REG_WRITE(ah, addr, wrData);
329 rdData = REG_READ(ah, addr);
330 if (wrData != rdData) {
331 ath_print(common, ATH_DBG_FATAL,
332 "address test failed "
333 "addr: 0x%08x - wr:0x%08x != "
334 "rd:0x%08x\n",
335 addr, wrData, rdData);
336 return false;
337 }
338 }
339 REG_WRITE(ah, regAddr[i], regHold[i]);
340 }
341 udelay(100);
342
343 return true;
344 }
345
346 static void ath9k_hw_init_config(struct ath_hw *ah)
347 {
348 int i;
349
350 ah->config.dma_beacon_response_time = 2;
351 ah->config.sw_beacon_response_time = 10;
352 ah->config.additional_swba_backoff = 0;
353 ah->config.ack_6mb = 0x0;
354 ah->config.cwm_ignore_extcca = 0;
355 ah->config.pcie_powersave_enable = 0;
356 ah->config.pcie_clock_req = 0;
357 ah->config.pcie_waen = 0;
358 ah->config.analog_shiftreg = 1;
359 ah->config.ofdm_trig_low = 200;
360 ah->config.ofdm_trig_high = 500;
361 ah->config.cck_trig_high = 200;
362 ah->config.cck_trig_low = 100;
363
364 /*
365 * For now ANI is disabled for AR9003, it is still
366 * being tested.
367 */
368 if (!AR_SREV_9300_20_OR_LATER(ah))
369 ah->config.enable_ani = 1;
370
371 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
372 ah->config.spurchans[i][0] = AR_NO_SPUR;
373 ah->config.spurchans[i][1] = AR_NO_SPUR;
374 }
375
376 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
377 ah->config.ht_enable = 1;
378 else
379 ah->config.ht_enable = 0;
380
381 ah->config.rx_intr_mitigation = true;
382
383 /*
384 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
385 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
386 * This means we use it for all AR5416 devices, and the few
387 * minor PCI AR9280 devices out there.
388 *
389 * Serialization is required because these devices do not handle
390 * well the case of two concurrent reads/writes due to the latency
391 * involved. During one read/write another read/write can be issued
392 * on another CPU while the previous read/write may still be working
393 * on our hardware, if we hit this case the hardware poops in a loop.
394 * We prevent this by serializing reads and writes.
395 *
396 * This issue is not present on PCI-Express devices or pre-AR5416
397 * devices (legacy, 802.11abg).
398 */
399 if (num_possible_cpus() > 1)
400 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
401 }
402
403 static void ath9k_hw_init_defaults(struct ath_hw *ah)
404 {
405 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
406
407 regulatory->country_code = CTRY_DEFAULT;
408 regulatory->power_limit = MAX_RATE_POWER;
409 regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
410
411 ah->hw_version.magic = AR5416_MAGIC;
412 ah->hw_version.subvendorid = 0;
413
414 ah->ah_flags = 0;
415 if (!AR_SREV_9100(ah))
416 ah->ah_flags = AH_USE_EEPROM;
417
418 ah->atim_window = 0;
419 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
420 ah->beacon_interval = 100;
421 ah->enable_32kHz_clock = DONT_USE_32KHZ;
422 ah->slottime = (u32) -1;
423 ah->globaltxtimeout = (u32) -1;
424 ah->power_mode = ATH9K_PM_UNDEFINED;
425 }
426
427 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
428 {
429 struct ath_common *common = ath9k_hw_common(ah);
430 u32 sum;
431 int i;
432 u16 eeval;
433 u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
434
435 sum = 0;
436 for (i = 0; i < 3; i++) {
437 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
438 sum += eeval;
439 common->macaddr[2 * i] = eeval >> 8;
440 common->macaddr[2 * i + 1] = eeval & 0xff;
441 }
442 if (sum == 0 || sum == 0xffff * 3)
443 return -EADDRNOTAVAIL;
444
445 return 0;
446 }
447
448 static int ath9k_hw_post_init(struct ath_hw *ah)
449 {
450 int ecode;
451
452 if (!AR_SREV_9271(ah)) {
453 if (!ath9k_hw_chip_test(ah))
454 return -ENODEV;
455 }
456
457 if (!AR_SREV_9300_20_OR_LATER(ah)) {
458 ecode = ar9002_hw_rf_claim(ah);
459 if (ecode != 0)
460 return ecode;
461 }
462
463 ecode = ath9k_hw_eeprom_init(ah);
464 if (ecode != 0)
465 return ecode;
466
467 ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
468 "Eeprom VER: %d, REV: %d\n",
469 ah->eep_ops->get_eeprom_ver(ah),
470 ah->eep_ops->get_eeprom_rev(ah));
471
472 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
473 if (ecode) {
474 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
475 "Failed allocating banks for "
476 "external radio\n");
477 return ecode;
478 }
479
480 if (!AR_SREV_9100(ah)) {
481 ath9k_hw_ani_setup(ah);
482 ath9k_hw_ani_init(ah);
483 }
484
485 return 0;
486 }
487
488 static void ath9k_hw_attach_ops(struct ath_hw *ah)
489 {
490 if (AR_SREV_9300_20_OR_LATER(ah))
491 ar9003_hw_attach_ops(ah);
492 else
493 ar9002_hw_attach_ops(ah);
494 }
495
496 /* Called for all hardware families */
497 static int __ath9k_hw_init(struct ath_hw *ah)
498 {
499 struct ath_common *common = ath9k_hw_common(ah);
500 int r = 0;
501
502 if (ah->hw_version.devid == AR5416_AR9100_DEVID)
503 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
504
505 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
506 ath_print(common, ATH_DBG_FATAL,
507 "Couldn't reset chip\n");
508 return -EIO;
509 }
510
511 ath9k_hw_init_defaults(ah);
512 ath9k_hw_init_config(ah);
513
514 ath9k_hw_attach_ops(ah);
515
516 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
517 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
518 return -EIO;
519 }
520
521 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
522 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
523 (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
524 ah->config.serialize_regmode =
525 SER_REG_MODE_ON;
526 } else {
527 ah->config.serialize_regmode =
528 SER_REG_MODE_OFF;
529 }
530 }
531
532 ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
533 ah->config.serialize_regmode);
534
535 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
536 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
537 else
538 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
539
540 if (!ath9k_hw_macversion_supported(ah)) {
541 ath_print(common, ATH_DBG_FATAL,
542 "Mac Chip Rev 0x%02x.%x is not supported by "
543 "this driver\n", ah->hw_version.macVersion,
544 ah->hw_version.macRev);
545 return -EOPNOTSUPP;
546 }
547
548 if (AR_SREV_9271(ah) || AR_SREV_9100(ah))
549 ah->is_pciexpress = false;
550
551 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
552 ath9k_hw_init_cal_settings(ah);
553
554 ah->ani_function = ATH9K_ANI_ALL;
555 if (AR_SREV_9280_10_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
556 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
557
558 ath9k_hw_init_mode_regs(ah);
559
560 if (ah->is_pciexpress)
561 ath9k_hw_configpcipowersave(ah, 0, 0);
562 else
563 ath9k_hw_disablepcie(ah);
564
565 if (!AR_SREV_9300_20_OR_LATER(ah))
566 ar9002_hw_cck_chan14_spread(ah);
567
568 r = ath9k_hw_post_init(ah);
569 if (r)
570 return r;
571
572 ath9k_hw_init_mode_gain_regs(ah);
573 r = ath9k_hw_fill_cap_info(ah);
574 if (r)
575 return r;
576
577 r = ath9k_hw_init_macaddr(ah);
578 if (r) {
579 ath_print(common, ATH_DBG_FATAL,
580 "Failed to initialize MAC address\n");
581 return r;
582 }
583
584 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
585 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
586 else
587 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
588
589 if (AR_SREV_9300_20_OR_LATER(ah))
590 ar9003_hw_set_nf_limits(ah);
591
592 ath9k_init_nfcal_hist_buffer(ah);
593
594 common->state = ATH_HW_INITIALIZED;
595
596 return 0;
597 }
598
599 int ath9k_hw_init(struct ath_hw *ah)
600 {
601 int ret;
602 struct ath_common *common = ath9k_hw_common(ah);
603
604 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
605 switch (ah->hw_version.devid) {
606 case AR5416_DEVID_PCI:
607 case AR5416_DEVID_PCIE:
608 case AR5416_AR9100_DEVID:
609 case AR9160_DEVID_PCI:
610 case AR9280_DEVID_PCI:
611 case AR9280_DEVID_PCIE:
612 case AR9285_DEVID_PCIE:
613 case AR9287_DEVID_PCI:
614 case AR9287_DEVID_PCIE:
615 case AR2427_DEVID_PCIE:
616 case AR9300_DEVID_PCIE:
617 break;
618 default:
619 if (common->bus_ops->ath_bus_type == ATH_USB)
620 break;
621 ath_print(common, ATH_DBG_FATAL,
622 "Hardware device ID 0x%04x not supported\n",
623 ah->hw_version.devid);
624 return -EOPNOTSUPP;
625 }
626
627 ret = __ath9k_hw_init(ah);
628 if (ret) {
629 ath_print(common, ATH_DBG_FATAL,
630 "Unable to initialize hardware; "
631 "initialization status: %d\n", ret);
632 return ret;
633 }
634
635 return 0;
636 }
637 EXPORT_SYMBOL(ath9k_hw_init);
638
639 static void ath9k_hw_init_qos(struct ath_hw *ah)
640 {
641 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
642 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
643
644 REG_WRITE(ah, AR_QOS_NO_ACK,
645 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
646 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
647 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
648
649 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
650 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
651 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
652 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
653 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
654 }
655
656 static void ath9k_hw_init_pll(struct ath_hw *ah,
657 struct ath9k_channel *chan)
658 {
659 u32 pll = ath9k_hw_compute_pll_control(ah, chan);
660
661 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
662
663 /* Switch the core clock for ar9271 to 117Mhz */
664 if (AR_SREV_9271(ah)) {
665 udelay(500);
666 REG_WRITE(ah, 0x50040, 0x304);
667 }
668
669 udelay(RTC_PLL_SETTLE_DELAY);
670
671 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
672 }
673
674 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
675 enum nl80211_iftype opmode)
676 {
677 u32 imr_reg = AR_IMR_TXERR |
678 AR_IMR_TXURN |
679 AR_IMR_RXERR |
680 AR_IMR_RXORN |
681 AR_IMR_BCNMISC;
682
683 if (AR_SREV_9300_20_OR_LATER(ah)) {
684 imr_reg |= AR_IMR_RXOK_HP;
685 if (ah->config.rx_intr_mitigation)
686 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
687 else
688 imr_reg |= AR_IMR_RXOK_LP;
689
690 } else {
691 if (ah->config.rx_intr_mitigation)
692 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
693 else
694 imr_reg |= AR_IMR_RXOK;
695 }
696
697 if (ah->config.tx_intr_mitigation)
698 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
699 else
700 imr_reg |= AR_IMR_TXOK;
701
702 if (opmode == NL80211_IFTYPE_AP)
703 imr_reg |= AR_IMR_MIB;
704
705 REG_WRITE(ah, AR_IMR, imr_reg);
706 ah->imrs2_reg |= AR_IMR_S2_GTT;
707 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
708
709 if (!AR_SREV_9100(ah)) {
710 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
711 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
712 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
713 }
714
715 if (AR_SREV_9300_20_OR_LATER(ah)) {
716 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
717 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
718 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
719 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
720 }
721 }
722
723 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
724 {
725 u32 val = ath9k_hw_mac_to_clks(ah, us);
726 val = min(val, (u32) 0xFFFF);
727 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
728 }
729
730 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
731 {
732 u32 val = ath9k_hw_mac_to_clks(ah, us);
733 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
734 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
735 }
736
737 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
738 {
739 u32 val = ath9k_hw_mac_to_clks(ah, us);
740 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
741 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
742 }
743
744 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
745 {
746 if (tu > 0xFFFF) {
747 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
748 "bad global tx timeout %u\n", tu);
749 ah->globaltxtimeout = (u32) -1;
750 return false;
751 } else {
752 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
753 ah->globaltxtimeout = tu;
754 return true;
755 }
756 }
757
758 void ath9k_hw_init_global_settings(struct ath_hw *ah)
759 {
760 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
761 int acktimeout;
762 int slottime;
763 int sifstime;
764
765 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
766 ah->misc_mode);
767
768 if (ah->misc_mode != 0)
769 REG_WRITE(ah, AR_PCU_MISC,
770 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
771
772 if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
773 sifstime = 16;
774 else
775 sifstime = 10;
776
777 /* As defined by IEEE 802.11-2007 17.3.8.6 */
778 slottime = ah->slottime + 3 * ah->coverage_class;
779 acktimeout = slottime + sifstime;
780
781 /*
782 * Workaround for early ACK timeouts, add an offset to match the
783 * initval's 64us ack timeout value.
784 * This was initially only meant to work around an issue with delayed
785 * BA frames in some implementations, but it has been found to fix ACK
786 * timeout issues in other cases as well.
787 */
788 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
789 acktimeout += 64 - sifstime - ah->slottime;
790
791 ath9k_hw_setslottime(ah, slottime);
792 ath9k_hw_set_ack_timeout(ah, acktimeout);
793 ath9k_hw_set_cts_timeout(ah, acktimeout);
794 if (ah->globaltxtimeout != (u32) -1)
795 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
796 }
797 EXPORT_SYMBOL(ath9k_hw_init_global_settings);
798
799 void ath9k_hw_deinit(struct ath_hw *ah)
800 {
801 struct ath_common *common = ath9k_hw_common(ah);
802
803 if (common->state < ATH_HW_INITIALIZED)
804 goto free_hw;
805
806 if (!AR_SREV_9100(ah))
807 ath9k_hw_ani_disable(ah);
808
809 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
810
811 free_hw:
812 ath9k_hw_rf_free_ext_banks(ah);
813 }
814 EXPORT_SYMBOL(ath9k_hw_deinit);
815
816 /*******/
817 /* INI */
818 /*******/
819
820 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
821 {
822 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
823
824 if (IS_CHAN_B(chan))
825 ctl |= CTL_11B;
826 else if (IS_CHAN_G(chan))
827 ctl |= CTL_11G;
828 else
829 ctl |= CTL_11A;
830
831 return ctl;
832 }
833
834 /****************************************/
835 /* Reset and Channel Switching Routines */
836 /****************************************/
837
838 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
839 {
840 struct ath_common *common = ath9k_hw_common(ah);
841 u32 regval;
842
843 /*
844 * set AHB_MODE not to do cacheline prefetches
845 */
846 if (!AR_SREV_9300_20_OR_LATER(ah)) {
847 regval = REG_READ(ah, AR_AHB_MODE);
848 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
849 }
850
851 /*
852 * let mac dma reads be in 128 byte chunks
853 */
854 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
855 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
856
857 /*
858 * Restore TX Trigger Level to its pre-reset value.
859 * The initial value depends on whether aggregation is enabled, and is
860 * adjusted whenever underruns are detected.
861 */
862 if (!AR_SREV_9300_20_OR_LATER(ah))
863 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
864
865 /*
866 * let mac dma writes be in 128 byte chunks
867 */
868 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
869 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
870
871 /*
872 * Setup receive FIFO threshold to hold off TX activities
873 */
874 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
875
876 if (AR_SREV_9300_20_OR_LATER(ah)) {
877 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
878 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
879
880 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
881 ah->caps.rx_status_len);
882 }
883
884 /*
885 * reduce the number of usable entries in PCU TXBUF to avoid
886 * wrap around issues.
887 */
888 if (AR_SREV_9285(ah)) {
889 /* For AR9285 the number of Fifos are reduced to half.
890 * So set the usable tx buf size also to half to
891 * avoid data/delimiter underruns
892 */
893 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
894 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
895 } else if (!AR_SREV_9271(ah)) {
896 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
897 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
898 }
899
900 if (AR_SREV_9300_20_OR_LATER(ah))
901 ath9k_hw_reset_txstatus_ring(ah);
902 }
903
904 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
905 {
906 u32 val;
907
908 val = REG_READ(ah, AR_STA_ID1);
909 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
910 switch (opmode) {
911 case NL80211_IFTYPE_AP:
912 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
913 | AR_STA_ID1_KSRCH_MODE);
914 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
915 break;
916 case NL80211_IFTYPE_ADHOC:
917 case NL80211_IFTYPE_MESH_POINT:
918 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
919 | AR_STA_ID1_KSRCH_MODE);
920 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
921 break;
922 case NL80211_IFTYPE_STATION:
923 case NL80211_IFTYPE_MONITOR:
924 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
925 break;
926 }
927 }
928
929 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
930 u32 *coef_mantissa, u32 *coef_exponent)
931 {
932 u32 coef_exp, coef_man;
933
934 for (coef_exp = 31; coef_exp > 0; coef_exp--)
935 if ((coef_scaled >> coef_exp) & 0x1)
936 break;
937
938 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
939
940 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
941
942 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
943 *coef_exponent = coef_exp - 16;
944 }
945
946 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
947 {
948 u32 rst_flags;
949 u32 tmpReg;
950
951 if (AR_SREV_9100(ah)) {
952 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
953 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
954 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
955 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
956 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
957 }
958
959 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
960 AR_RTC_FORCE_WAKE_ON_INT);
961
962 if (AR_SREV_9100(ah)) {
963 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
964 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
965 } else {
966 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
967 if (tmpReg &
968 (AR_INTR_SYNC_LOCAL_TIMEOUT |
969 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
970 u32 val;
971 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
972
973 val = AR_RC_HOSTIF;
974 if (!AR_SREV_9300_20_OR_LATER(ah))
975 val |= AR_RC_AHB;
976 REG_WRITE(ah, AR_RC, val);
977
978 } else if (!AR_SREV_9300_20_OR_LATER(ah))
979 REG_WRITE(ah, AR_RC, AR_RC_AHB);
980
981 rst_flags = AR_RTC_RC_MAC_WARM;
982 if (type == ATH9K_RESET_COLD)
983 rst_flags |= AR_RTC_RC_MAC_COLD;
984 }
985
986 REG_WRITE(ah, AR_RTC_RC, rst_flags);
987 udelay(50);
988
989 REG_WRITE(ah, AR_RTC_RC, 0);
990 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
991 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
992 "RTC stuck in MAC reset\n");
993 return false;
994 }
995
996 if (!AR_SREV_9100(ah))
997 REG_WRITE(ah, AR_RC, 0);
998
999 if (AR_SREV_9100(ah))
1000 udelay(50);
1001
1002 return true;
1003 }
1004
1005 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1006 {
1007 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1008 AR_RTC_FORCE_WAKE_ON_INT);
1009
1010 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1011 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1012
1013 REG_WRITE(ah, AR_RTC_RESET, 0);
1014
1015 if (!AR_SREV_9300_20_OR_LATER(ah))
1016 udelay(2);
1017
1018 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1019 REG_WRITE(ah, AR_RC, 0);
1020
1021 REG_WRITE(ah, AR_RTC_RESET, 1);
1022
1023 if (!ath9k_hw_wait(ah,
1024 AR_RTC_STATUS,
1025 AR_RTC_STATUS_M,
1026 AR_RTC_STATUS_ON,
1027 AH_WAIT_TIMEOUT)) {
1028 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1029 "RTC not waking up\n");
1030 return false;
1031 }
1032
1033 ath9k_hw_read_revisions(ah);
1034
1035 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1036 }
1037
1038 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1039 {
1040 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1041 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1042
1043 switch (type) {
1044 case ATH9K_RESET_POWER_ON:
1045 return ath9k_hw_set_reset_power_on(ah);
1046 case ATH9K_RESET_WARM:
1047 case ATH9K_RESET_COLD:
1048 return ath9k_hw_set_reset(ah, type);
1049 default:
1050 return false;
1051 }
1052 }
1053
1054 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1055 struct ath9k_channel *chan)
1056 {
1057 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
1058 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1059 return false;
1060 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1061 return false;
1062
1063 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1064 return false;
1065
1066 ah->chip_fullsleep = false;
1067 ath9k_hw_init_pll(ah, chan);
1068 ath9k_hw_set_rfmode(ah, chan);
1069
1070 return true;
1071 }
1072
1073 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1074 struct ath9k_channel *chan)
1075 {
1076 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1077 struct ath_common *common = ath9k_hw_common(ah);
1078 struct ieee80211_channel *channel = chan->chan;
1079 u32 qnum;
1080 int r;
1081
1082 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1083 if (ath9k_hw_numtxpending(ah, qnum)) {
1084 ath_print(common, ATH_DBG_QUEUE,
1085 "Transmit frames pending on "
1086 "queue %d\n", qnum);
1087 return false;
1088 }
1089 }
1090
1091 if (!ath9k_hw_rfbus_req(ah)) {
1092 ath_print(common, ATH_DBG_FATAL,
1093 "Could not kill baseband RX\n");
1094 return false;
1095 }
1096
1097 ath9k_hw_set_channel_regs(ah, chan);
1098
1099 r = ath9k_hw_rf_set_freq(ah, chan);
1100 if (r) {
1101 ath_print(common, ATH_DBG_FATAL,
1102 "Failed to set channel\n");
1103 return false;
1104 }
1105
1106 ah->eep_ops->set_txpower(ah, chan,
1107 ath9k_regd_get_ctl(regulatory, chan),
1108 channel->max_antenna_gain * 2,
1109 channel->max_power * 2,
1110 min((u32) MAX_RATE_POWER,
1111 (u32) regulatory->power_limit));
1112
1113 ath9k_hw_rfbus_done(ah);
1114
1115 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1116 ath9k_hw_set_delta_slope(ah, chan);
1117
1118 ath9k_hw_spur_mitigate_freq(ah, chan);
1119
1120 if (!chan->oneTimeCalsDone)
1121 chan->oneTimeCalsDone = true;
1122
1123 return true;
1124 }
1125
1126 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1127 bool bChannelChange)
1128 {
1129 struct ath_common *common = ath9k_hw_common(ah);
1130 u32 saveLedState;
1131 struct ath9k_channel *curchan = ah->curchan;
1132 u32 saveDefAntenna;
1133 u32 macStaId1;
1134 u64 tsf = 0;
1135 int i, r;
1136
1137 ah->txchainmask = common->tx_chainmask;
1138 ah->rxchainmask = common->rx_chainmask;
1139
1140 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1141 return -EIO;
1142
1143 if (curchan && !ah->chip_fullsleep)
1144 ath9k_hw_getnf(ah, curchan);
1145
1146 if (bChannelChange &&
1147 (ah->chip_fullsleep != true) &&
1148 (ah->curchan != NULL) &&
1149 (chan->channel != ah->curchan->channel) &&
1150 ((chan->channelFlags & CHANNEL_ALL) ==
1151 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
1152 !(AR_SREV_9280(ah) || IS_CHAN_A_5MHZ_SPACED(chan) ||
1153 IS_CHAN_A_5MHZ_SPACED(ah->curchan))) {
1154
1155 if (ath9k_hw_channel_change(ah, chan)) {
1156 ath9k_hw_loadnf(ah, ah->curchan);
1157 ath9k_hw_start_nfcal(ah);
1158 return 0;
1159 }
1160 }
1161
1162 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1163 if (saveDefAntenna == 0)
1164 saveDefAntenna = 1;
1165
1166 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1167
1168 /* For chips on which RTC reset is done, save TSF before it gets cleared */
1169 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1170 tsf = ath9k_hw_gettsf64(ah);
1171
1172 saveLedState = REG_READ(ah, AR_CFG_LED) &
1173 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1174 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1175
1176 ath9k_hw_mark_phy_inactive(ah);
1177
1178 /* Only required on the first reset */
1179 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1180 REG_WRITE(ah,
1181 AR9271_RESET_POWER_DOWN_CONTROL,
1182 AR9271_RADIO_RF_RST);
1183 udelay(50);
1184 }
1185
1186 if (!ath9k_hw_chip_reset(ah, chan)) {
1187 ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n");
1188 return -EINVAL;
1189 }
1190
1191 /* Only required on the first reset */
1192 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1193 ah->htc_reset_init = false;
1194 REG_WRITE(ah,
1195 AR9271_RESET_POWER_DOWN_CONTROL,
1196 AR9271_GATE_MAC_CTL);
1197 udelay(50);
1198 }
1199
1200 /* Restore TSF */
1201 if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1202 ath9k_hw_settsf64(ah, tsf);
1203
1204 if (AR_SREV_9280_10_OR_LATER(ah))
1205 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1206
1207 r = ath9k_hw_process_ini(ah, chan);
1208 if (r)
1209 return r;
1210
1211 /* Setup MFP options for CCMP */
1212 if (AR_SREV_9280_20_OR_LATER(ah)) {
1213 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1214 * frames when constructing CCMP AAD. */
1215 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1216 0xc7ff);
1217 ah->sw_mgmt_crypto = false;
1218 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1219 /* Disable hardware crypto for management frames */
1220 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1221 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1222 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1223 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1224 ah->sw_mgmt_crypto = true;
1225 } else
1226 ah->sw_mgmt_crypto = true;
1227
1228 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1229 ath9k_hw_set_delta_slope(ah, chan);
1230
1231 ath9k_hw_spur_mitigate_freq(ah, chan);
1232 ah->eep_ops->set_board_values(ah, chan);
1233
1234 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
1235 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
1236 | macStaId1
1237 | AR_STA_ID1_RTS_USE_DEF
1238 | (ah->config.
1239 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
1240 | ah->sta_id1_defaults);
1241 ath9k_hw_set_operating_mode(ah, ah->opmode);
1242
1243 ath_hw_setbssidmask(common);
1244
1245 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1246
1247 ath9k_hw_write_associd(ah);
1248
1249 REG_WRITE(ah, AR_ISR, ~0);
1250
1251 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1252
1253 r = ath9k_hw_rf_set_freq(ah, chan);
1254 if (r)
1255 return r;
1256
1257 for (i = 0; i < AR_NUM_DCU; i++)
1258 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1259
1260 ah->intr_txqs = 0;
1261 for (i = 0; i < ah->caps.total_queues; i++)
1262 ath9k_hw_resettxqueue(ah, i);
1263
1264 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
1265 ath9k_hw_init_qos(ah);
1266
1267 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1268 ath9k_enable_rfkill(ah);
1269
1270 ath9k_hw_init_global_settings(ah);
1271
1272 if (!AR_SREV_9300_20_OR_LATER(ah)) {
1273 ar9002_hw_enable_async_fifo(ah);
1274 ar9002_hw_enable_wep_aggregation(ah);
1275 }
1276
1277 REG_WRITE(ah, AR_STA_ID1,
1278 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
1279
1280 ath9k_hw_set_dma(ah);
1281
1282 REG_WRITE(ah, AR_OBS, 8);
1283
1284 if (ah->config.rx_intr_mitigation) {
1285 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
1286 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
1287 }
1288
1289 if (ah->config.tx_intr_mitigation) {
1290 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1291 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1292 }
1293
1294 ath9k_hw_init_bb(ah, chan);
1295
1296 if (!ath9k_hw_init_cal(ah, chan))
1297 return -EIO;
1298
1299 ath9k_hw_restore_chainmask(ah);
1300 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1301
1302 /*
1303 * For big endian systems turn on swapping for descriptors
1304 */
1305 if (AR_SREV_9100(ah)) {
1306 u32 mask;
1307 mask = REG_READ(ah, AR_CFG);
1308 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1309 ath_print(common, ATH_DBG_RESET,
1310 "CFG Byte Swap Set 0x%x\n", mask);
1311 } else {
1312 mask =
1313 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1314 REG_WRITE(ah, AR_CFG, mask);
1315 ath_print(common, ATH_DBG_RESET,
1316 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
1317 }
1318 } else {
1319 /* Configure AR9271 target WLAN */
1320 if (AR_SREV_9271(ah))
1321 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1322 #ifdef __BIG_ENDIAN
1323 else
1324 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1325 #endif
1326 }
1327
1328 if (ah->btcoex_hw.enabled)
1329 ath9k_hw_btcoex_enable(ah);
1330
1331 if (AR_SREV_9300_20_OR_LATER(ah)) {
1332 ath9k_hw_loadnf(ah, curchan);
1333 ath9k_hw_start_nfcal(ah);
1334 }
1335
1336 return 0;
1337 }
1338 EXPORT_SYMBOL(ath9k_hw_reset);
1339
1340 /************************/
1341 /* Key Cache Management */
1342 /************************/
1343
1344 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
1345 {
1346 u32 keyType;
1347
1348 if (entry >= ah->caps.keycache_size) {
1349 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1350 "keychache entry %u out of range\n", entry);
1351 return false;
1352 }
1353
1354 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
1355
1356 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
1357 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
1358 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
1359 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
1360 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
1361 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
1362 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
1363 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
1364
1365 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
1366 u16 micentry = entry + 64;
1367
1368 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
1369 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
1370 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
1371 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
1372
1373 }
1374
1375 return true;
1376 }
1377 EXPORT_SYMBOL(ath9k_hw_keyreset);
1378
1379 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
1380 {
1381 u32 macHi, macLo;
1382
1383 if (entry >= ah->caps.keycache_size) {
1384 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1385 "keychache entry %u out of range\n", entry);
1386 return false;
1387 }
1388
1389 if (mac != NULL) {
1390 macHi = (mac[5] << 8) | mac[4];
1391 macLo = (mac[3] << 24) |
1392 (mac[2] << 16) |
1393 (mac[1] << 8) |
1394 mac[0];
1395 macLo >>= 1;
1396 macLo |= (macHi & 1) << 31;
1397 macHi >>= 1;
1398 } else {
1399 macLo = macHi = 0;
1400 }
1401 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
1402 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
1403
1404 return true;
1405 }
1406 EXPORT_SYMBOL(ath9k_hw_keysetmac);
1407
1408 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
1409 const struct ath9k_keyval *k,
1410 const u8 *mac)
1411 {
1412 const struct ath9k_hw_capabilities *pCap = &ah->caps;
1413 struct ath_common *common = ath9k_hw_common(ah);
1414 u32 key0, key1, key2, key3, key4;
1415 u32 keyType;
1416
1417 if (entry >= pCap->keycache_size) {
1418 ath_print(common, ATH_DBG_FATAL,
1419 "keycache entry %u out of range\n", entry);
1420 return false;
1421 }
1422
1423 switch (k->kv_type) {
1424 case ATH9K_CIPHER_AES_OCB:
1425 keyType = AR_KEYTABLE_TYPE_AES;
1426 break;
1427 case ATH9K_CIPHER_AES_CCM:
1428 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
1429 ath_print(common, ATH_DBG_ANY,
1430 "AES-CCM not supported by mac rev 0x%x\n",
1431 ah->hw_version.macRev);
1432 return false;
1433 }
1434 keyType = AR_KEYTABLE_TYPE_CCM;
1435 break;
1436 case ATH9K_CIPHER_TKIP:
1437 keyType = AR_KEYTABLE_TYPE_TKIP;
1438 if (ATH9K_IS_MIC_ENABLED(ah)
1439 && entry + 64 >= pCap->keycache_size) {
1440 ath_print(common, ATH_DBG_ANY,
1441 "entry %u inappropriate for TKIP\n", entry);
1442 return false;
1443 }
1444 break;
1445 case ATH9K_CIPHER_WEP:
1446 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
1447 ath_print(common, ATH_DBG_ANY,
1448 "WEP key length %u too small\n", k->kv_len);
1449 return false;
1450 }
1451 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
1452 keyType = AR_KEYTABLE_TYPE_40;
1453 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
1454 keyType = AR_KEYTABLE_TYPE_104;
1455 else
1456 keyType = AR_KEYTABLE_TYPE_128;
1457 break;
1458 case ATH9K_CIPHER_CLR:
1459 keyType = AR_KEYTABLE_TYPE_CLR;
1460 break;
1461 default:
1462 ath_print(common, ATH_DBG_FATAL,
1463 "cipher %u not supported\n", k->kv_type);
1464 return false;
1465 }
1466
1467 key0 = get_unaligned_le32(k->kv_val + 0);
1468 key1 = get_unaligned_le16(k->kv_val + 4);
1469 key2 = get_unaligned_le32(k->kv_val + 6);
1470 key3 = get_unaligned_le16(k->kv_val + 10);
1471 key4 = get_unaligned_le32(k->kv_val + 12);
1472 if (k->kv_len <= WLAN_KEY_LEN_WEP104)
1473 key4 &= 0xff;
1474
1475 /*
1476 * Note: Key cache registers access special memory area that requires
1477 * two 32-bit writes to actually update the values in the internal
1478 * memory. Consequently, the exact order and pairs used here must be
1479 * maintained.
1480 */
1481
1482 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
1483 u16 micentry = entry + 64;
1484
1485 /*
1486 * Write inverted key[47:0] first to avoid Michael MIC errors
1487 * on frames that could be sent or received at the same time.
1488 * The correct key will be written in the end once everything
1489 * else is ready.
1490 */
1491 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
1492 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
1493
1494 /* Write key[95:48] */
1495 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
1496 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
1497
1498 /* Write key[127:96] and key type */
1499 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
1500 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
1501
1502 /* Write MAC address for the entry */
1503 (void) ath9k_hw_keysetmac(ah, entry, mac);
1504
1505 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
1506 /*
1507 * TKIP uses two key cache entries:
1508 * Michael MIC TX/RX keys in the same key cache entry
1509 * (idx = main index + 64):
1510 * key0 [31:0] = RX key [31:0]
1511 * key1 [15:0] = TX key [31:16]
1512 * key1 [31:16] = reserved
1513 * key2 [31:0] = RX key [63:32]
1514 * key3 [15:0] = TX key [15:0]
1515 * key3 [31:16] = reserved
1516 * key4 [31:0] = TX key [63:32]
1517 */
1518 u32 mic0, mic1, mic2, mic3, mic4;
1519
1520 mic0 = get_unaligned_le32(k->kv_mic + 0);
1521 mic2 = get_unaligned_le32(k->kv_mic + 4);
1522 mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
1523 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
1524 mic4 = get_unaligned_le32(k->kv_txmic + 4);
1525
1526 /* Write RX[31:0] and TX[31:16] */
1527 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
1528 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
1529
1530 /* Write RX[63:32] and TX[15:0] */
1531 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
1532 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
1533
1534 /* Write TX[63:32] and keyType(reserved) */
1535 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
1536 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
1537 AR_KEYTABLE_TYPE_CLR);
1538
1539 } else {
1540 /*
1541 * TKIP uses four key cache entries (two for group
1542 * keys):
1543 * Michael MIC TX/RX keys are in different key cache
1544 * entries (idx = main index + 64 for TX and
1545 * main index + 32 + 96 for RX):
1546 * key0 [31:0] = TX/RX MIC key [31:0]
1547 * key1 [31:0] = reserved
1548 * key2 [31:0] = TX/RX MIC key [63:32]
1549 * key3 [31:0] = reserved
1550 * key4 [31:0] = reserved
1551 *
1552 * Upper layer code will call this function separately
1553 * for TX and RX keys when these registers offsets are
1554 * used.
1555 */
1556 u32 mic0, mic2;
1557
1558 mic0 = get_unaligned_le32(k->kv_mic + 0);
1559 mic2 = get_unaligned_le32(k->kv_mic + 4);
1560
1561 /* Write MIC key[31:0] */
1562 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
1563 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
1564
1565 /* Write MIC key[63:32] */
1566 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
1567 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
1568
1569 /* Write TX[63:32] and keyType(reserved) */
1570 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
1571 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
1572 AR_KEYTABLE_TYPE_CLR);
1573 }
1574
1575 /* MAC address registers are reserved for the MIC entry */
1576 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
1577 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
1578
1579 /*
1580 * Write the correct (un-inverted) key[47:0] last to enable
1581 * TKIP now that all other registers are set with correct
1582 * values.
1583 */
1584 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
1585 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
1586 } else {
1587 /* Write key[47:0] */
1588 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
1589 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
1590
1591 /* Write key[95:48] */
1592 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
1593 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
1594
1595 /* Write key[127:96] and key type */
1596 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
1597 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
1598
1599 /* Write MAC address for the entry */
1600 (void) ath9k_hw_keysetmac(ah, entry, mac);
1601 }
1602
1603 return true;
1604 }
1605 EXPORT_SYMBOL(ath9k_hw_set_keycache_entry);
1606
1607 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
1608 {
1609 if (entry < ah->caps.keycache_size) {
1610 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
1611 if (val & AR_KEYTABLE_VALID)
1612 return true;
1613 }
1614 return false;
1615 }
1616 EXPORT_SYMBOL(ath9k_hw_keyisvalid);
1617
1618 /******************************/
1619 /* Power Management (Chipset) */
1620 /******************************/
1621
1622 /*
1623 * Notify Power Mgt is disabled in self-generated frames.
1624 * If requested, force chip to sleep.
1625 */
1626 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
1627 {
1628 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1629 if (setChip) {
1630 /*
1631 * Clear the RTC force wake bit to allow the
1632 * mac to go to sleep.
1633 */
1634 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1635 AR_RTC_FORCE_WAKE_EN);
1636 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1637 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1638
1639 /* Shutdown chip. Active low */
1640 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah))
1641 REG_CLR_BIT(ah, (AR_RTC_RESET),
1642 AR_RTC_RESET_EN);
1643 }
1644 }
1645
1646 /*
1647 * Notify Power Management is enabled in self-generating
1648 * frames. If request, set power mode of chip to
1649 * auto/normal. Duration in units of 128us (1/8 TU).
1650 */
1651 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
1652 {
1653 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1654 if (setChip) {
1655 struct ath9k_hw_capabilities *pCap = &ah->caps;
1656
1657 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1658 /* Set WakeOnInterrupt bit; clear ForceWake bit */
1659 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1660 AR_RTC_FORCE_WAKE_ON_INT);
1661 } else {
1662 /*
1663 * Clear the RTC force wake bit to allow the
1664 * mac to go to sleep.
1665 */
1666 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1667 AR_RTC_FORCE_WAKE_EN);
1668 }
1669 }
1670 }
1671
1672 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
1673 {
1674 u32 val;
1675 int i;
1676
1677 if (setChip) {
1678 if ((REG_READ(ah, AR_RTC_STATUS) &
1679 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
1680 if (ath9k_hw_set_reset_reg(ah,
1681 ATH9K_RESET_POWER_ON) != true) {
1682 return false;
1683 }
1684 if (!AR_SREV_9300_20_OR_LATER(ah))
1685 ath9k_hw_init_pll(ah, NULL);
1686 }
1687 if (AR_SREV_9100(ah))
1688 REG_SET_BIT(ah, AR_RTC_RESET,
1689 AR_RTC_RESET_EN);
1690
1691 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1692 AR_RTC_FORCE_WAKE_EN);
1693 udelay(50);
1694
1695 for (i = POWER_UP_TIME / 50; i > 0; i--) {
1696 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
1697 if (val == AR_RTC_STATUS_ON)
1698 break;
1699 udelay(50);
1700 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1701 AR_RTC_FORCE_WAKE_EN);
1702 }
1703 if (i == 0) {
1704 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1705 "Failed to wakeup in %uus\n",
1706 POWER_UP_TIME / 20);
1707 return false;
1708 }
1709 }
1710
1711 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1712
1713 return true;
1714 }
1715
1716 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
1717 {
1718 struct ath_common *common = ath9k_hw_common(ah);
1719 int status = true, setChip = true;
1720 static const char *modes[] = {
1721 "AWAKE",
1722 "FULL-SLEEP",
1723 "NETWORK SLEEP",
1724 "UNDEFINED"
1725 };
1726
1727 if (ah->power_mode == mode)
1728 return status;
1729
1730 ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
1731 modes[ah->power_mode], modes[mode]);
1732
1733 switch (mode) {
1734 case ATH9K_PM_AWAKE:
1735 status = ath9k_hw_set_power_awake(ah, setChip);
1736 break;
1737 case ATH9K_PM_FULL_SLEEP:
1738 ath9k_set_power_sleep(ah, setChip);
1739 ah->chip_fullsleep = true;
1740 break;
1741 case ATH9K_PM_NETWORK_SLEEP:
1742 ath9k_set_power_network_sleep(ah, setChip);
1743 break;
1744 default:
1745 ath_print(common, ATH_DBG_FATAL,
1746 "Unknown power mode %u\n", mode);
1747 return false;
1748 }
1749 ah->power_mode = mode;
1750
1751 return status;
1752 }
1753 EXPORT_SYMBOL(ath9k_hw_setpower);
1754
1755 /*******************/
1756 /* Beacon Handling */
1757 /*******************/
1758
1759 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
1760 {
1761 int flags = 0;
1762
1763 ah->beacon_interval = beacon_period;
1764
1765 switch (ah->opmode) {
1766 case NL80211_IFTYPE_STATION:
1767 case NL80211_IFTYPE_MONITOR:
1768 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
1769 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
1770 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
1771 flags |= AR_TBTT_TIMER_EN;
1772 break;
1773 case NL80211_IFTYPE_ADHOC:
1774 case NL80211_IFTYPE_MESH_POINT:
1775 REG_SET_BIT(ah, AR_TXCFG,
1776 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
1777 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
1778 TU_TO_USEC(next_beacon +
1779 (ah->atim_window ? ah->
1780 atim_window : 1)));
1781 flags |= AR_NDP_TIMER_EN;
1782 case NL80211_IFTYPE_AP:
1783 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
1784 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
1785 TU_TO_USEC(next_beacon -
1786 ah->config.
1787 dma_beacon_response_time));
1788 REG_WRITE(ah, AR_NEXT_SWBA,
1789 TU_TO_USEC(next_beacon -
1790 ah->config.
1791 sw_beacon_response_time));
1792 flags |=
1793 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
1794 break;
1795 default:
1796 ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
1797 "%s: unsupported opmode: %d\n",
1798 __func__, ah->opmode);
1799 return;
1800 break;
1801 }
1802
1803 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
1804 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
1805 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
1806 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
1807
1808 beacon_period &= ~ATH9K_BEACON_ENA;
1809 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
1810 ath9k_hw_reset_tsf(ah);
1811 }
1812
1813 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
1814 }
1815 EXPORT_SYMBOL(ath9k_hw_beaconinit);
1816
1817 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
1818 const struct ath9k_beacon_state *bs)
1819 {
1820 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
1821 struct ath9k_hw_capabilities *pCap = &ah->caps;
1822 struct ath_common *common = ath9k_hw_common(ah);
1823
1824 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
1825
1826 REG_WRITE(ah, AR_BEACON_PERIOD,
1827 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1828 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
1829 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1830
1831 REG_RMW_FIELD(ah, AR_RSSI_THR,
1832 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
1833
1834 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
1835
1836 if (bs->bs_sleepduration > beaconintval)
1837 beaconintval = bs->bs_sleepduration;
1838
1839 dtimperiod = bs->bs_dtimperiod;
1840 if (bs->bs_sleepduration > dtimperiod)
1841 dtimperiod = bs->bs_sleepduration;
1842
1843 if (beaconintval == dtimperiod)
1844 nextTbtt = bs->bs_nextdtim;
1845 else
1846 nextTbtt = bs->bs_nexttbtt;
1847
1848 ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
1849 ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
1850 ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
1851 ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
1852
1853 REG_WRITE(ah, AR_NEXT_DTIM,
1854 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
1855 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
1856
1857 REG_WRITE(ah, AR_SLEEP1,
1858 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
1859 | AR_SLEEP1_ASSUME_DTIM);
1860
1861 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
1862 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
1863 else
1864 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
1865
1866 REG_WRITE(ah, AR_SLEEP2,
1867 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
1868
1869 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
1870 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
1871
1872 REG_SET_BIT(ah, AR_TIMER_MODE,
1873 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
1874 AR_DTIM_TIMER_EN);
1875
1876 /* TSF Out of Range Threshold */
1877 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
1878 }
1879 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
1880
1881 /*******************/
1882 /* HW Capabilities */
1883 /*******************/
1884
1885 int ath9k_hw_fill_cap_info(struct ath_hw *ah)
1886 {
1887 struct ath9k_hw_capabilities *pCap = &ah->caps;
1888 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1889 struct ath_common *common = ath9k_hw_common(ah);
1890 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
1891
1892 u16 capField = 0, eeval;
1893
1894 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
1895 regulatory->current_rd = eeval;
1896
1897 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
1898 if (AR_SREV_9285_10_OR_LATER(ah))
1899 eeval |= AR9285_RDEXT_DEFAULT;
1900 regulatory->current_rd_ext = eeval;
1901
1902 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
1903
1904 if (ah->opmode != NL80211_IFTYPE_AP &&
1905 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
1906 if (regulatory->current_rd == 0x64 ||
1907 regulatory->current_rd == 0x65)
1908 regulatory->current_rd += 5;
1909 else if (regulatory->current_rd == 0x41)
1910 regulatory->current_rd = 0x43;
1911 ath_print(common, ATH_DBG_REGULATORY,
1912 "regdomain mapped to 0x%x\n", regulatory->current_rd);
1913 }
1914
1915 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
1916 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
1917 ath_print(common, ATH_DBG_FATAL,
1918 "no band has been marked as supported in EEPROM.\n");
1919 return -EINVAL;
1920 }
1921
1922 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
1923
1924 if (eeval & AR5416_OPFLAGS_11A) {
1925 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
1926 if (ah->config.ht_enable) {
1927 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
1928 set_bit(ATH9K_MODE_11NA_HT20,
1929 pCap->wireless_modes);
1930 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
1931 set_bit(ATH9K_MODE_11NA_HT40PLUS,
1932 pCap->wireless_modes);
1933 set_bit(ATH9K_MODE_11NA_HT40MINUS,
1934 pCap->wireless_modes);
1935 }
1936 }
1937 }
1938
1939 if (eeval & AR5416_OPFLAGS_11G) {
1940 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
1941 if (ah->config.ht_enable) {
1942 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
1943 set_bit(ATH9K_MODE_11NG_HT20,
1944 pCap->wireless_modes);
1945 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
1946 set_bit(ATH9K_MODE_11NG_HT40PLUS,
1947 pCap->wireless_modes);
1948 set_bit(ATH9K_MODE_11NG_HT40MINUS,
1949 pCap->wireless_modes);
1950 }
1951 }
1952 }
1953
1954 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
1955 /*
1956 * For AR9271 we will temporarilly uses the rx chainmax as read from
1957 * the EEPROM.
1958 */
1959 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
1960 !(eeval & AR5416_OPFLAGS_11A) &&
1961 !(AR_SREV_9271(ah)))
1962 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
1963 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
1964 else
1965 /* Use rx_chainmask from EEPROM. */
1966 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
1967
1968 if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
1969 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
1970
1971 pCap->low_2ghz_chan = 2312;
1972 pCap->high_2ghz_chan = 2732;
1973
1974 pCap->low_5ghz_chan = 4920;
1975 pCap->high_5ghz_chan = 6100;
1976
1977 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
1978 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
1979 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
1980
1981 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
1982 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
1983 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
1984
1985 if (ah->config.ht_enable)
1986 pCap->hw_caps |= ATH9K_HW_CAP_HT;
1987 else
1988 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
1989
1990 pCap->hw_caps |= ATH9K_HW_CAP_GTT;
1991 pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
1992 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
1993 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
1994
1995 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
1996 pCap->total_queues =
1997 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
1998 else
1999 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
2000
2001 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
2002 pCap->keycache_size =
2003 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
2004 else
2005 pCap->keycache_size = AR_KEYTABLE_SIZE;
2006
2007 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
2008
2009 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
2010 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1;
2011 else
2012 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
2013
2014 if (AR_SREV_9271(ah))
2015 pCap->num_gpio_pins = AR9271_NUM_GPIO;
2016 else if (AR_SREV_9285_10_OR_LATER(ah))
2017 pCap->num_gpio_pins = AR9285_NUM_GPIO;
2018 else if (AR_SREV_9280_10_OR_LATER(ah))
2019 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2020 else
2021 pCap->num_gpio_pins = AR_NUM_GPIO;
2022
2023 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
2024 pCap->hw_caps |= ATH9K_HW_CAP_CST;
2025 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
2026 } else {
2027 pCap->rts_aggr_limit = (8 * 1024);
2028 }
2029
2030 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
2031
2032 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2033 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2034 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2035 ah->rfkill_gpio =
2036 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2037 ah->rfkill_polarity =
2038 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
2039
2040 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
2041 }
2042 #endif
2043 if (AR_SREV_9271(ah))
2044 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2045 else
2046 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
2047
2048 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
2049 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2050 else
2051 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
2052
2053 if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
2054 pCap->reg_cap =
2055 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
2056 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
2057 AR_EEPROM_EEREGCAP_EN_KK_U2 |
2058 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
2059 } else {
2060 pCap->reg_cap =
2061 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
2062 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
2063 }
2064
2065 /* Advertise midband for AR5416 with FCC midband set in eeprom */
2066 if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
2067 AR_SREV_5416(ah))
2068 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
2069
2070 pCap->num_antcfg_5ghz =
2071 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
2072 pCap->num_antcfg_2ghz =
2073 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
2074
2075 if (AR_SREV_9280_10_OR_LATER(ah) &&
2076 ath9k_hw_btcoex_supported(ah)) {
2077 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
2078 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
2079
2080 if (AR_SREV_9285(ah)) {
2081 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
2082 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
2083 } else {
2084 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
2085 }
2086 } else {
2087 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
2088 }
2089
2090 if (AR_SREV_9300_20_OR_LATER(ah)) {
2091 pCap->hw_caps |= ATH9K_HW_CAP_EDMA;
2092 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2093 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2094 pCap->rx_status_len = sizeof(struct ar9003_rxs);
2095 pCap->tx_desc_len = sizeof(struct ar9003_txc);
2096 pCap->txs_len = sizeof(struct ar9003_txs);
2097 } else {
2098 pCap->tx_desc_len = sizeof(struct ath_desc);
2099 }
2100
2101 if (AR_SREV_9300_20_OR_LATER(ah))
2102 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2103
2104 return 0;
2105 }
2106
2107 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
2108 u32 capability, u32 *result)
2109 {
2110 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2111 switch (type) {
2112 case ATH9K_CAP_CIPHER:
2113 switch (capability) {
2114 case ATH9K_CIPHER_AES_CCM:
2115 case ATH9K_CIPHER_AES_OCB:
2116 case ATH9K_CIPHER_TKIP:
2117 case ATH9K_CIPHER_WEP:
2118 case ATH9K_CIPHER_MIC:
2119 case ATH9K_CIPHER_CLR:
2120 return true;
2121 default:
2122 return false;
2123 }
2124 case ATH9K_CAP_TKIP_MIC:
2125 switch (capability) {
2126 case 0:
2127 return true;
2128 case 1:
2129 return (ah->sta_id1_defaults &
2130 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
2131 false;
2132 }
2133 case ATH9K_CAP_TKIP_SPLIT:
2134 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
2135 false : true;
2136 case ATH9K_CAP_MCAST_KEYSRCH:
2137 switch (capability) {
2138 case 0:
2139 return true;
2140 case 1:
2141 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
2142 return false;
2143 } else {
2144 return (ah->sta_id1_defaults &
2145 AR_STA_ID1_MCAST_KSRCH) ? true :
2146 false;
2147 }
2148 }
2149 return false;
2150 case ATH9K_CAP_TXPOW:
2151 switch (capability) {
2152 case 0:
2153 return 0;
2154 case 1:
2155 *result = regulatory->power_limit;
2156 return 0;
2157 case 2:
2158 *result = regulatory->max_power_level;
2159 return 0;
2160 case 3:
2161 *result = regulatory->tp_scale;
2162 return 0;
2163 }
2164 return false;
2165 case ATH9K_CAP_DS:
2166 return (AR_SREV_9280_20_OR_LATER(ah) &&
2167 (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
2168 ? false : true;
2169 default:
2170 return false;
2171 }
2172 }
2173 EXPORT_SYMBOL(ath9k_hw_getcapability);
2174
2175 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
2176 u32 capability, u32 setting, int *status)
2177 {
2178 switch (type) {
2179 case ATH9K_CAP_TKIP_MIC:
2180 if (setting)
2181 ah->sta_id1_defaults |=
2182 AR_STA_ID1_CRPT_MIC_ENABLE;
2183 else
2184 ah->sta_id1_defaults &=
2185 ~AR_STA_ID1_CRPT_MIC_ENABLE;
2186 return true;
2187 case ATH9K_CAP_MCAST_KEYSRCH:
2188 if (setting)
2189 ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
2190 else
2191 ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
2192 return true;
2193 default:
2194 return false;
2195 }
2196 }
2197 EXPORT_SYMBOL(ath9k_hw_setcapability);
2198
2199 /****************************/
2200 /* GPIO / RFKILL / Antennae */
2201 /****************************/
2202
2203 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
2204 u32 gpio, u32 type)
2205 {
2206 int addr;
2207 u32 gpio_shift, tmp;
2208
2209 if (gpio > 11)
2210 addr = AR_GPIO_OUTPUT_MUX3;
2211 else if (gpio > 5)
2212 addr = AR_GPIO_OUTPUT_MUX2;
2213 else
2214 addr = AR_GPIO_OUTPUT_MUX1;
2215
2216 gpio_shift = (gpio % 6) * 5;
2217
2218 if (AR_SREV_9280_20_OR_LATER(ah)
2219 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2220 REG_RMW(ah, addr, (type << gpio_shift),
2221 (0x1f << gpio_shift));
2222 } else {
2223 tmp = REG_READ(ah, addr);
2224 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2225 tmp &= ~(0x1f << gpio_shift);
2226 tmp |= (type << gpio_shift);
2227 REG_WRITE(ah, addr, tmp);
2228 }
2229 }
2230
2231 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
2232 {
2233 u32 gpio_shift;
2234
2235 BUG_ON(gpio >= ah->caps.num_gpio_pins);
2236
2237 gpio_shift = gpio << 1;
2238
2239 REG_RMW(ah,
2240 AR_GPIO_OE_OUT,
2241 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2242 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2243 }
2244 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
2245
2246 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
2247 {
2248 #define MS_REG_READ(x, y) \
2249 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2250
2251 if (gpio >= ah->caps.num_gpio_pins)
2252 return 0xffffffff;
2253
2254 if (AR_SREV_9300_20_OR_LATER(ah))
2255 return MS_REG_READ(AR9300, gpio) != 0;
2256 else if (AR_SREV_9271(ah))
2257 return MS_REG_READ(AR9271, gpio) != 0;
2258 else if (AR_SREV_9287_10_OR_LATER(ah))
2259 return MS_REG_READ(AR9287, gpio) != 0;
2260 else if (AR_SREV_9285_10_OR_LATER(ah))
2261 return MS_REG_READ(AR9285, gpio) != 0;
2262 else if (AR_SREV_9280_10_OR_LATER(ah))
2263 return MS_REG_READ(AR928X, gpio) != 0;
2264 else
2265 return MS_REG_READ(AR, gpio) != 0;
2266 }
2267 EXPORT_SYMBOL(ath9k_hw_gpio_get);
2268
2269 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
2270 u32 ah_signal_type)
2271 {
2272 u32 gpio_shift;
2273
2274 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
2275
2276 gpio_shift = 2 * gpio;
2277
2278 REG_RMW(ah,
2279 AR_GPIO_OE_OUT,
2280 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2281 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2282 }
2283 EXPORT_SYMBOL(ath9k_hw_cfg_output);
2284
2285 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
2286 {
2287 if (AR_SREV_9271(ah))
2288 val = ~val;
2289
2290 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2291 AR_GPIO_BIT(gpio));
2292 }
2293 EXPORT_SYMBOL(ath9k_hw_set_gpio);
2294
2295 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
2296 {
2297 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
2298 }
2299 EXPORT_SYMBOL(ath9k_hw_getdefantenna);
2300
2301 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
2302 {
2303 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
2304 }
2305 EXPORT_SYMBOL(ath9k_hw_setantenna);
2306
2307 /*********************/
2308 /* General Operation */
2309 /*********************/
2310
2311 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
2312 {
2313 u32 bits = REG_READ(ah, AR_RX_FILTER);
2314 u32 phybits = REG_READ(ah, AR_PHY_ERR);
2315
2316 if (phybits & AR_PHY_ERR_RADAR)
2317 bits |= ATH9K_RX_FILTER_PHYRADAR;
2318 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2319 bits |= ATH9K_RX_FILTER_PHYERR;
2320
2321 return bits;
2322 }
2323 EXPORT_SYMBOL(ath9k_hw_getrxfilter);
2324
2325 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
2326 {
2327 u32 phybits;
2328
2329 REG_WRITE(ah, AR_RX_FILTER, bits);
2330
2331 phybits = 0;
2332 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2333 phybits |= AR_PHY_ERR_RADAR;
2334 if (bits & ATH9K_RX_FILTER_PHYERR)
2335 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2336 REG_WRITE(ah, AR_PHY_ERR, phybits);
2337
2338 if (phybits)
2339 REG_WRITE(ah, AR_RXCFG,
2340 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
2341 else
2342 REG_WRITE(ah, AR_RXCFG,
2343 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
2344 }
2345 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
2346
2347 bool ath9k_hw_phy_disable(struct ath_hw *ah)
2348 {
2349 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2350 return false;
2351
2352 ath9k_hw_init_pll(ah, NULL);
2353 return true;
2354 }
2355 EXPORT_SYMBOL(ath9k_hw_phy_disable);
2356
2357 bool ath9k_hw_disable(struct ath_hw *ah)
2358 {
2359 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2360 return false;
2361
2362 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2363 return false;
2364
2365 ath9k_hw_init_pll(ah, NULL);
2366 return true;
2367 }
2368 EXPORT_SYMBOL(ath9k_hw_disable);
2369
2370 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
2371 {
2372 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2373 struct ath9k_channel *chan = ah->curchan;
2374 struct ieee80211_channel *channel = chan->chan;
2375
2376 regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
2377
2378 ah->eep_ops->set_txpower(ah, chan,
2379 ath9k_regd_get_ctl(regulatory, chan),
2380 channel->max_antenna_gain * 2,
2381 channel->max_power * 2,
2382 min((u32) MAX_RATE_POWER,
2383 (u32) regulatory->power_limit));
2384 }
2385 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
2386
2387 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
2388 {
2389 memcpy(ath9k_hw_common(ah)->macaddr, mac, ETH_ALEN);
2390 }
2391 EXPORT_SYMBOL(ath9k_hw_setmac);
2392
2393 void ath9k_hw_setopmode(struct ath_hw *ah)
2394 {
2395 ath9k_hw_set_operating_mode(ah, ah->opmode);
2396 }
2397 EXPORT_SYMBOL(ath9k_hw_setopmode);
2398
2399 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
2400 {
2401 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2402 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
2403 }
2404 EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
2405
2406 void ath9k_hw_write_associd(struct ath_hw *ah)
2407 {
2408 struct ath_common *common = ath9k_hw_common(ah);
2409
2410 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2411 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2412 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2413 }
2414 EXPORT_SYMBOL(ath9k_hw_write_associd);
2415
2416 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
2417 {
2418 u64 tsf;
2419
2420 tsf = REG_READ(ah, AR_TSF_U32);
2421 tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
2422
2423 return tsf;
2424 }
2425 EXPORT_SYMBOL(ath9k_hw_gettsf64);
2426
2427 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
2428 {
2429 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
2430 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
2431 }
2432 EXPORT_SYMBOL(ath9k_hw_settsf64);
2433
2434 void ath9k_hw_reset_tsf(struct ath_hw *ah)
2435 {
2436 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2437 AH_TSF_WRITE_TIMEOUT))
2438 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
2439 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
2440
2441 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2442 }
2443 EXPORT_SYMBOL(ath9k_hw_reset_tsf);
2444
2445 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
2446 {
2447 if (setting)
2448 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
2449 else
2450 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
2451 }
2452 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
2453
2454 /*
2455 * Extend 15-bit time stamp from rx descriptor to
2456 * a full 64-bit TSF using the current h/w TSF.
2457 */
2458 u64 ath9k_hw_extend_tsf(struct ath_hw *ah, u32 rstamp)
2459 {
2460 u64 tsf;
2461
2462 tsf = ath9k_hw_gettsf64(ah);
2463 if ((tsf & 0x7fff) < rstamp)
2464 tsf -= 0x8000;
2465 return (tsf & ~0x7fff) | rstamp;
2466 }
2467 EXPORT_SYMBOL(ath9k_hw_extend_tsf);
2468
2469 void ath9k_hw_set11nmac2040(struct ath_hw *ah)
2470 {
2471 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
2472 u32 macmode;
2473
2474 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
2475 macmode = AR_2040_JOINED_RX_CLEAR;
2476 else
2477 macmode = 0;
2478
2479 REG_WRITE(ah, AR_2040_MODE, macmode);
2480 }
2481
2482 /* HW Generic timers configuration */
2483
2484 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2485 {
2486 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2487 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2488 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2489 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2490 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2491 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2492 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2493 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2494 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2495 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2496 AR_NDP2_TIMER_MODE, 0x0002},
2497 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2498 AR_NDP2_TIMER_MODE, 0x0004},
2499 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2500 AR_NDP2_TIMER_MODE, 0x0008},
2501 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2502 AR_NDP2_TIMER_MODE, 0x0010},
2503 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2504 AR_NDP2_TIMER_MODE, 0x0020},
2505 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2506 AR_NDP2_TIMER_MODE, 0x0040},
2507 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2508 AR_NDP2_TIMER_MODE, 0x0080}
2509 };
2510
2511 /* HW generic timer primitives */
2512
2513 /* compute and clear index of rightmost 1 */
2514 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
2515 {
2516 u32 b;
2517
2518 b = *mask;
2519 b &= (0-b);
2520 *mask &= ~b;
2521 b *= debruijn32;
2522 b >>= 27;
2523
2524 return timer_table->gen_timer_index[b];
2525 }
2526
2527 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
2528 {
2529 return REG_READ(ah, AR_TSF_L32);
2530 }
2531 EXPORT_SYMBOL(ath9k_hw_gettsf32);
2532
2533 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2534 void (*trigger)(void *),
2535 void (*overflow)(void *),
2536 void *arg,
2537 u8 timer_index)
2538 {
2539 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2540 struct ath_gen_timer *timer;
2541
2542 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
2543
2544 if (timer == NULL) {
2545 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2546 "Failed to allocate memory"
2547 "for hw timer[%d]\n", timer_index);
2548 return NULL;
2549 }
2550
2551 /* allocate a hardware generic timer slot */
2552 timer_table->timers[timer_index] = timer;
2553 timer->index = timer_index;
2554 timer->trigger = trigger;
2555 timer->overflow = overflow;
2556 timer->arg = arg;
2557
2558 return timer;
2559 }
2560 EXPORT_SYMBOL(ath_gen_timer_alloc);
2561
2562 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2563 struct ath_gen_timer *timer,
2564 u32 timer_next,
2565 u32 timer_period)
2566 {
2567 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2568 u32 tsf;
2569
2570 BUG_ON(!timer_period);
2571
2572 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
2573
2574 tsf = ath9k_hw_gettsf32(ah);
2575
2576 ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
2577 "curent tsf %x period %x"
2578 "timer_next %x\n", tsf, timer_period, timer_next);
2579
2580 /*
2581 * Pull timer_next forward if the current TSF already passed it
2582 * because of software latency
2583 */
2584 if (timer_next < tsf)
2585 timer_next = tsf + timer_period;
2586
2587 /*
2588 * Program generic timer registers
2589 */
2590 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
2591 timer_next);
2592 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
2593 timer_period);
2594 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2595 gen_tmr_configuration[timer->index].mode_mask);
2596
2597 /* Enable both trigger and thresh interrupt masks */
2598 REG_SET_BIT(ah, AR_IMR_S5,
2599 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2600 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2601 }
2602 EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
2603
2604 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
2605 {
2606 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2607
2608 if ((timer->index < AR_FIRST_NDP_TIMER) ||
2609 (timer->index >= ATH_MAX_GEN_TIMER)) {
2610 return;
2611 }
2612
2613 /* Clear generic timer enable bits. */
2614 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2615 gen_tmr_configuration[timer->index].mode_mask);
2616
2617 /* Disable both trigger and thresh interrupt masks */
2618 REG_CLR_BIT(ah, AR_IMR_S5,
2619 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2620 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2621
2622 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
2623 }
2624 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
2625
2626 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
2627 {
2628 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2629
2630 /* free the hardware generic timer slot */
2631 timer_table->timers[timer->index] = NULL;
2632 kfree(timer);
2633 }
2634 EXPORT_SYMBOL(ath_gen_timer_free);
2635
2636 /*
2637 * Generic Timer Interrupts handling
2638 */
2639 void ath_gen_timer_isr(struct ath_hw *ah)
2640 {
2641 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2642 struct ath_gen_timer *timer;
2643 struct ath_common *common = ath9k_hw_common(ah);
2644 u32 trigger_mask, thresh_mask, index;
2645
2646 /* get hardware generic timer interrupt status */
2647 trigger_mask = ah->intr_gen_timer_trigger;
2648 thresh_mask = ah->intr_gen_timer_thresh;
2649 trigger_mask &= timer_table->timer_mask.val;
2650 thresh_mask &= timer_table->timer_mask.val;
2651
2652 trigger_mask &= ~thresh_mask;
2653
2654 while (thresh_mask) {
2655 index = rightmost_index(timer_table, &thresh_mask);
2656 timer = timer_table->timers[index];
2657 BUG_ON(!timer);
2658 ath_print(common, ATH_DBG_HWTIMER,
2659 "TSF overflow for Gen timer %d\n", index);
2660 timer->overflow(timer->arg);
2661 }
2662
2663 while (trigger_mask) {
2664 index = rightmost_index(timer_table, &trigger_mask);
2665 timer = timer_table->timers[index];
2666 BUG_ON(!timer);
2667 ath_print(common, ATH_DBG_HWTIMER,
2668 "Gen timer[%d] trigger\n", index);
2669 timer->trigger(timer->arg);
2670 }
2671 }
2672 EXPORT_SYMBOL(ath_gen_timer_isr);
2673
2674 /********/
2675 /* HTC */
2676 /********/
2677
2678 void ath9k_hw_htc_resetinit(struct ath_hw *ah)
2679 {
2680 ah->htc_reset_init = true;
2681 }
2682 EXPORT_SYMBOL(ath9k_hw_htc_resetinit);
2683
2684 static struct {
2685 u32 version;
2686 const char * name;
2687 } ath_mac_bb_names[] = {
2688 /* Devices with external radios */
2689 { AR_SREV_VERSION_5416_PCI, "5416" },
2690 { AR_SREV_VERSION_5416_PCIE, "5418" },
2691 { AR_SREV_VERSION_9100, "9100" },
2692 { AR_SREV_VERSION_9160, "9160" },
2693 /* Single-chip solutions */
2694 { AR_SREV_VERSION_9280, "9280" },
2695 { AR_SREV_VERSION_9285, "9285" },
2696 { AR_SREV_VERSION_9287, "9287" },
2697 { AR_SREV_VERSION_9271, "9271" },
2698 { AR_SREV_VERSION_9300, "9300" },
2699 };
2700
2701 /* For devices with external radios */
2702 static struct {
2703 u16 version;
2704 const char * name;
2705 } ath_rf_names[] = {
2706 { 0, "5133" },
2707 { AR_RAD5133_SREV_MAJOR, "5133" },
2708 { AR_RAD5122_SREV_MAJOR, "5122" },
2709 { AR_RAD2133_SREV_MAJOR, "2133" },
2710 { AR_RAD2122_SREV_MAJOR, "2122" }
2711 };
2712
2713 /*
2714 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2715 */
2716 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
2717 {
2718 int i;
2719
2720 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2721 if (ath_mac_bb_names[i].version == mac_bb_version) {
2722 return ath_mac_bb_names[i].name;
2723 }
2724 }
2725
2726 return "????";
2727 }
2728
2729 /*
2730 * Return the RF name. "????" is returned if the RF is unknown.
2731 * Used for devices with external radios.
2732 */
2733 static const char *ath9k_hw_rf_name(u16 rf_version)
2734 {
2735 int i;
2736
2737 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2738 if (ath_rf_names[i].version == rf_version) {
2739 return ath_rf_names[i].name;
2740 }
2741 }
2742
2743 return "????";
2744 }
2745
2746 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
2747 {
2748 int used;
2749
2750 /* chipsets >= AR9280 are single-chip */
2751 if (AR_SREV_9280_10_OR_LATER(ah)) {
2752 used = snprintf(hw_name, len,
2753 "Atheros AR%s Rev:%x",
2754 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2755 ah->hw_version.macRev);
2756 }
2757 else {
2758 used = snprintf(hw_name, len,
2759 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
2760 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2761 ah->hw_version.macRev,
2762 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
2763 AR_RADIO_SREV_MAJOR)),
2764 ah->hw_version.phyRev);
2765 }
2766
2767 hw_name[used] = '\0';
2768 }
2769 EXPORT_SYMBOL(ath9k_hw_name);
Linux kernel - Deliverables
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