2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include <asm/unaligned.h>
23 static int btcoex_enable
;
24 module_param(btcoex_enable
, bool, 0);
25 MODULE_PARM_DESC(btcoex_enable
, "Enable Bluetooth coexistence support");
27 #define ATH9K_CLOCK_RATE_CCK 22
28 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
29 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
31 static bool ath9k_hw_set_reset_reg(struct ath_hw
*ah
, u32 type
);
32 static void ath9k_hw_set_regs(struct ath_hw
*ah
, struct ath9k_channel
*chan
,
33 enum ath9k_ht_macmode macmode
);
34 static u32
ath9k_hw_ini_fixup(struct ath_hw
*ah
,
35 struct ar5416_eeprom_def
*pEepData
,
37 static void ath9k_hw_9280_spur_mitigate(struct ath_hw
*ah
, struct ath9k_channel
*chan
);
38 static void ath9k_hw_spur_mitigate(struct ath_hw
*ah
, struct ath9k_channel
*chan
);
40 /********************/
41 /* Helper Functions */
42 /********************/
44 static u32
ath9k_hw_mac_usec(struct ath_hw
*ah
, u32 clks
)
46 struct ieee80211_conf
*conf
= &ah
->ah_sc
->hw
->conf
;
48 if (!ah
->curchan
) /* should really check for CCK instead */
49 return clks
/ ATH9K_CLOCK_RATE_CCK
;
50 if (conf
->channel
->band
== IEEE80211_BAND_2GHZ
)
51 return clks
/ ATH9K_CLOCK_RATE_2GHZ_OFDM
;
53 return clks
/ ATH9K_CLOCK_RATE_5GHZ_OFDM
;
56 static u32
ath9k_hw_mac_to_usec(struct ath_hw
*ah
, u32 clks
)
58 struct ieee80211_conf
*conf
= &ah
->ah_sc
->hw
->conf
;
60 if (conf_is_ht40(conf
))
61 return ath9k_hw_mac_usec(ah
, clks
) / 2;
63 return ath9k_hw_mac_usec(ah
, clks
);
66 static u32
ath9k_hw_mac_clks(struct ath_hw
*ah
, u32 usecs
)
68 struct ieee80211_conf
*conf
= &ah
->ah_sc
->hw
->conf
;
70 if (!ah
->curchan
) /* should really check for CCK instead */
71 return usecs
*ATH9K_CLOCK_RATE_CCK
;
72 if (conf
->channel
->band
== IEEE80211_BAND_2GHZ
)
73 return usecs
*ATH9K_CLOCK_RATE_2GHZ_OFDM
;
74 return usecs
*ATH9K_CLOCK_RATE_5GHZ_OFDM
;
77 static u32
ath9k_hw_mac_to_clks(struct ath_hw
*ah
, u32 usecs
)
79 struct ieee80211_conf
*conf
= &ah
->ah_sc
->hw
->conf
;
81 if (conf_is_ht40(conf
))
82 return ath9k_hw_mac_clks(ah
, usecs
) * 2;
84 return ath9k_hw_mac_clks(ah
, usecs
);
88 * Read and write, they both share the same lock. We do this to serialize
89 * reads and writes on Atheros 802.11n PCI devices only. This is required
90 * as the FIFO on these devices can only accept sanely 2 requests. After
91 * that the device goes bananas. Serializing the reads/writes prevents this
95 void ath9k_iowrite32(struct ath_hw
*ah
, u32 reg_offset
, u32 val
)
97 if (ah
->config
.serialize_regmode
== SER_REG_MODE_ON
) {
99 spin_lock_irqsave(&ah
->ah_sc
->sc_serial_rw
, flags
);
100 iowrite32(val
, ah
->ah_sc
->mem
+ reg_offset
);
101 spin_unlock_irqrestore(&ah
->ah_sc
->sc_serial_rw
, flags
);
103 iowrite32(val
, ah
->ah_sc
->mem
+ reg_offset
);
106 unsigned int ath9k_ioread32(struct ath_hw
*ah
, u32 reg_offset
)
109 if (ah
->config
.serialize_regmode
== SER_REG_MODE_ON
) {
111 spin_lock_irqsave(&ah
->ah_sc
->sc_serial_rw
, flags
);
112 val
= ioread32(ah
->ah_sc
->mem
+ reg_offset
);
113 spin_unlock_irqrestore(&ah
->ah_sc
->sc_serial_rw
, flags
);
115 val
= ioread32(ah
->ah_sc
->mem
+ reg_offset
);
119 bool ath9k_hw_wait(struct ath_hw
*ah
, u32 reg
, u32 mask
, u32 val
, u32 timeout
)
123 BUG_ON(timeout
< AH_TIME_QUANTUM
);
125 for (i
= 0; i
< (timeout
/ AH_TIME_QUANTUM
); i
++) {
126 if ((REG_READ(ah
, reg
) & mask
) == val
)
129 udelay(AH_TIME_QUANTUM
);
132 DPRINTF(ah
->ah_sc
, ATH_DBG_ANY
,
133 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
134 timeout
, reg
, REG_READ(ah
, reg
), mask
, val
);
139 u32
ath9k_hw_reverse_bits(u32 val
, u32 n
)
144 for (i
= 0, retval
= 0; i
< n
; i
++) {
145 retval
= (retval
<< 1) | (val
& 1);
151 bool ath9k_get_channel_edges(struct ath_hw
*ah
,
155 struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
157 if (flags
& CHANNEL_5GHZ
) {
158 *low
= pCap
->low_5ghz_chan
;
159 *high
= pCap
->high_5ghz_chan
;
162 if ((flags
& CHANNEL_2GHZ
)) {
163 *low
= pCap
->low_2ghz_chan
;
164 *high
= pCap
->high_2ghz_chan
;
170 u16
ath9k_hw_computetxtime(struct ath_hw
*ah
,
171 const struct ath_rate_table
*rates
,
172 u32 frameLen
, u16 rateix
,
175 u32 bitsPerSymbol
, numBits
, numSymbols
, phyTime
, txTime
;
178 kbps
= rates
->info
[rateix
].ratekbps
;
183 switch (rates
->info
[rateix
].phy
) {
184 case WLAN_RC_PHY_CCK
:
185 phyTime
= CCK_PREAMBLE_BITS
+ CCK_PLCP_BITS
;
186 if (shortPreamble
&& rates
->info
[rateix
].short_preamble
)
188 numBits
= frameLen
<< 3;
189 txTime
= CCK_SIFS_TIME
+ phyTime
+ ((numBits
* 1000) / kbps
);
191 case WLAN_RC_PHY_OFDM
:
192 if (ah
->curchan
&& IS_CHAN_QUARTER_RATE(ah
->curchan
)) {
193 bitsPerSymbol
= (kbps
* OFDM_SYMBOL_TIME_QUARTER
) / 1000;
194 numBits
= OFDM_PLCP_BITS
+ (frameLen
<< 3);
195 numSymbols
= DIV_ROUND_UP(numBits
, bitsPerSymbol
);
196 txTime
= OFDM_SIFS_TIME_QUARTER
197 + OFDM_PREAMBLE_TIME_QUARTER
198 + (numSymbols
* OFDM_SYMBOL_TIME_QUARTER
);
199 } else if (ah
->curchan
&&
200 IS_CHAN_HALF_RATE(ah
->curchan
)) {
201 bitsPerSymbol
= (kbps
* OFDM_SYMBOL_TIME_HALF
) / 1000;
202 numBits
= OFDM_PLCP_BITS
+ (frameLen
<< 3);
203 numSymbols
= DIV_ROUND_UP(numBits
, bitsPerSymbol
);
204 txTime
= OFDM_SIFS_TIME_HALF
+
205 OFDM_PREAMBLE_TIME_HALF
206 + (numSymbols
* OFDM_SYMBOL_TIME_HALF
);
208 bitsPerSymbol
= (kbps
* OFDM_SYMBOL_TIME
) / 1000;
209 numBits
= OFDM_PLCP_BITS
+ (frameLen
<< 3);
210 numSymbols
= DIV_ROUND_UP(numBits
, bitsPerSymbol
);
211 txTime
= OFDM_SIFS_TIME
+ OFDM_PREAMBLE_TIME
212 + (numSymbols
* OFDM_SYMBOL_TIME
);
216 DPRINTF(ah
->ah_sc
, ATH_DBG_FATAL
,
217 "Unknown phy %u (rate ix %u)\n",
218 rates
->info
[rateix
].phy
, rateix
);
226 void ath9k_hw_get_channel_centers(struct ath_hw
*ah
,
227 struct ath9k_channel
*chan
,
228 struct chan_centers
*centers
)
232 if (!IS_CHAN_HT40(chan
)) {
233 centers
->ctl_center
= centers
->ext_center
=
234 centers
->synth_center
= chan
->channel
;
238 if ((chan
->chanmode
== CHANNEL_A_HT40PLUS
) ||
239 (chan
->chanmode
== CHANNEL_G_HT40PLUS
)) {
240 centers
->synth_center
=
241 chan
->channel
+ HT40_CHANNEL_CENTER_SHIFT
;
244 centers
->synth_center
=
245 chan
->channel
- HT40_CHANNEL_CENTER_SHIFT
;
249 centers
->ctl_center
=
250 centers
->synth_center
- (extoff
* HT40_CHANNEL_CENTER_SHIFT
);
251 centers
->ext_center
=
252 centers
->synth_center
+ (extoff
*
253 ((ah
->extprotspacing
== ATH9K_HT_EXTPROTSPACING_20
) ?
254 HT40_CHANNEL_CENTER_SHIFT
: 15));
261 static void ath9k_hw_read_revisions(struct ath_hw
*ah
)
265 val
= REG_READ(ah
, AR_SREV
) & AR_SREV_ID
;
268 val
= REG_READ(ah
, AR_SREV
);
269 ah
->hw_version
.macVersion
=
270 (val
& AR_SREV_VERSION2
) >> AR_SREV_TYPE2_S
;
271 ah
->hw_version
.macRev
= MS(val
, AR_SREV_REVISION2
);
272 ah
->is_pciexpress
= (val
& AR_SREV_TYPE2_HOST_MODE
) ? 0 : 1;
274 if (!AR_SREV_9100(ah
))
275 ah
->hw_version
.macVersion
= MS(val
, AR_SREV_VERSION
);
277 ah
->hw_version
.macRev
= val
& AR_SREV_REVISION
;
279 if (ah
->hw_version
.macVersion
== AR_SREV_VERSION_5416_PCIE
)
280 ah
->is_pciexpress
= true;
284 static int ath9k_hw_get_radiorev(struct ath_hw
*ah
)
289 REG_WRITE(ah
, AR_PHY(0x36), 0x00007058);
291 for (i
= 0; i
< 8; i
++)
292 REG_WRITE(ah
, AR_PHY(0x20), 0x00010000);
293 val
= (REG_READ(ah
, AR_PHY(256)) >> 24) & 0xff;
294 val
= ((val
& 0xf0) >> 4) | ((val
& 0x0f) << 4);
296 return ath9k_hw_reverse_bits(val
, 8);
299 /************************************/
300 /* HW Attach, Detach, Init Routines */
301 /************************************/
303 static void ath9k_hw_disablepcie(struct ath_hw
*ah
)
305 if (AR_SREV_9100(ah
))
308 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x9248fc00);
309 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x24924924);
310 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x28000029);
311 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x57160824);
312 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x25980579);
313 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x00000000);
314 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x1aaabe40);
315 REG_WRITE(ah
, AR_PCIE_SERDES
, 0xbe105554);
316 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x000e1007);
318 REG_WRITE(ah
, AR_PCIE_SERDES2
, 0x00000000);
321 static bool ath9k_hw_chip_test(struct ath_hw
*ah
)
323 u32 regAddr
[2] = { AR_STA_ID0
, AR_PHY_BASE
+ (8 << 2) };
325 u32 patternData
[4] = { 0x55555555,
331 for (i
= 0; i
< 2; i
++) {
332 u32 addr
= regAddr
[i
];
335 regHold
[i
] = REG_READ(ah
, addr
);
336 for (j
= 0; j
< 0x100; j
++) {
337 wrData
= (j
<< 16) | j
;
338 REG_WRITE(ah
, addr
, wrData
);
339 rdData
= REG_READ(ah
, addr
);
340 if (rdData
!= wrData
) {
341 DPRINTF(ah
->ah_sc
, ATH_DBG_FATAL
,
342 "address test failed "
343 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
344 addr
, wrData
, rdData
);
348 for (j
= 0; j
< 4; j
++) {
349 wrData
= patternData
[j
];
350 REG_WRITE(ah
, addr
, wrData
);
351 rdData
= REG_READ(ah
, addr
);
352 if (wrData
!= rdData
) {
353 DPRINTF(ah
->ah_sc
, ATH_DBG_FATAL
,
354 "address test failed "
355 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
356 addr
, wrData
, rdData
);
360 REG_WRITE(ah
, regAddr
[i
], regHold
[i
]);
367 static const char *ath9k_hw_devname(u16 devid
)
370 case AR5416_DEVID_PCI
:
371 return "Atheros 5416";
372 case AR5416_DEVID_PCIE
:
373 return "Atheros 5418";
374 case AR9160_DEVID_PCI
:
375 return "Atheros 9160";
376 case AR5416_AR9100_DEVID
:
377 return "Atheros 9100";
378 case AR9280_DEVID_PCI
:
379 case AR9280_DEVID_PCIE
:
380 return "Atheros 9280";
381 case AR9285_DEVID_PCIE
:
382 return "Atheros 9285";
383 case AR5416_DEVID_AR9287_PCI
:
384 case AR5416_DEVID_AR9287_PCIE
:
385 return "Atheros 9287";
391 static void ath9k_hw_init_config(struct ath_hw
*ah
)
395 ah
->config
.dma_beacon_response_time
= 2;
396 ah
->config
.sw_beacon_response_time
= 10;
397 ah
->config
.additional_swba_backoff
= 0;
398 ah
->config
.ack_6mb
= 0x0;
399 ah
->config
.cwm_ignore_extcca
= 0;
400 ah
->config
.pcie_powersave_enable
= 0;
401 ah
->config
.pcie_clock_req
= 0;
402 ah
->config
.pcie_waen
= 0;
403 ah
->config
.analog_shiftreg
= 1;
404 ah
->config
.ht_enable
= 1;
405 ah
->config
.ofdm_trig_low
= 200;
406 ah
->config
.ofdm_trig_high
= 500;
407 ah
->config
.cck_trig_high
= 200;
408 ah
->config
.cck_trig_low
= 100;
409 ah
->config
.enable_ani
= 1;
410 ah
->config
.diversity_control
= 0;
411 ah
->config
.antenna_switch_swap
= 0;
413 for (i
= 0; i
< AR_EEPROM_MODAL_SPURS
; i
++) {
414 ah
->config
.spurchans
[i
][0] = AR_NO_SPUR
;
415 ah
->config
.spurchans
[i
][1] = AR_NO_SPUR
;
418 ah
->config
.intr_mitigation
= true;
421 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
422 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
423 * This means we use it for all AR5416 devices, and the few
424 * minor PCI AR9280 devices out there.
426 * Serialization is required because these devices do not handle
427 * well the case of two concurrent reads/writes due to the latency
428 * involved. During one read/write another read/write can be issued
429 * on another CPU while the previous read/write may still be working
430 * on our hardware, if we hit this case the hardware poops in a loop.
431 * We prevent this by serializing reads and writes.
433 * This issue is not present on PCI-Express devices or pre-AR5416
434 * devices (legacy, 802.11abg).
436 if (num_possible_cpus() > 1)
437 ah
->config
.serialize_regmode
= SER_REG_MODE_AUTO
;
440 static void ath9k_hw_init_defaults(struct ath_hw
*ah
)
442 ah
->hw_version
.magic
= AR5416_MAGIC
;
443 ah
->regulatory
.country_code
= CTRY_DEFAULT
;
444 ah
->hw_version
.subvendorid
= 0;
447 if (ah
->hw_version
.devid
== AR5416_AR9100_DEVID
)
448 ah
->hw_version
.macVersion
= AR_SREV_VERSION_9100
;
449 if (!AR_SREV_9100(ah
))
450 ah
->ah_flags
= AH_USE_EEPROM
;
452 ah
->regulatory
.power_limit
= MAX_RATE_POWER
;
453 ah
->regulatory
.tp_scale
= ATH9K_TP_SCALE_MAX
;
455 ah
->diversity_control
= ah
->config
.diversity_control
;
456 ah
->antenna_switch_swap
=
457 ah
->config
.antenna_switch_swap
;
458 ah
->sta_id1_defaults
= AR_STA_ID1_CRPT_MIC_ENABLE
;
459 ah
->beacon_interval
= 100;
460 ah
->enable_32kHz_clock
= DONT_USE_32KHZ
;
461 ah
->slottime
= (u32
) -1;
462 ah
->acktimeout
= (u32
) -1;
463 ah
->ctstimeout
= (u32
) -1;
464 ah
->globaltxtimeout
= (u32
) -1;
466 ah
->gbeacon_rate
= 0;
468 ah
->power_mode
= ATH9K_PM_UNDEFINED
;
471 static int ath9k_hw_rfattach(struct ath_hw
*ah
)
473 bool rfStatus
= false;
476 rfStatus
= ath9k_hw_init_rf(ah
, &ecode
);
478 DPRINTF(ah
->ah_sc
, ATH_DBG_FATAL
,
479 "RF setup failed, status: %u\n", ecode
);
486 static int ath9k_hw_rf_claim(struct ath_hw
*ah
)
490 REG_WRITE(ah
, AR_PHY(0), 0x00000007);
492 val
= ath9k_hw_get_radiorev(ah
);
493 switch (val
& AR_RADIO_SREV_MAJOR
) {
495 val
= AR_RAD5133_SREV_MAJOR
;
497 case AR_RAD5133_SREV_MAJOR
:
498 case AR_RAD5122_SREV_MAJOR
:
499 case AR_RAD2133_SREV_MAJOR
:
500 case AR_RAD2122_SREV_MAJOR
:
503 DPRINTF(ah
->ah_sc
, ATH_DBG_FATAL
,
504 "Radio Chip Rev 0x%02X not supported\n",
505 val
& AR_RADIO_SREV_MAJOR
);
509 ah
->hw_version
.analog5GhzRev
= val
;
514 static int ath9k_hw_init_macaddr(struct ath_hw
*ah
)
521 for (i
= 0; i
< 3; i
++) {
522 eeval
= ah
->eep_ops
->get_eeprom(ah
, AR_EEPROM_MAC(i
));
524 ah
->macaddr
[2 * i
] = eeval
>> 8;
525 ah
->macaddr
[2 * i
+ 1] = eeval
& 0xff;
527 if (sum
== 0 || sum
== 0xffff * 3)
528 return -EADDRNOTAVAIL
;
533 static void ath9k_hw_init_rxgain_ini(struct ath_hw
*ah
)
537 if (ah
->eep_ops
->get_eeprom(ah
, EEP_MINOR_REV
) >= AR5416_EEP_MINOR_VER_17
) {
538 rxgain_type
= ah
->eep_ops
->get_eeprom(ah
, EEP_RXGAIN_TYPE
);
540 if (rxgain_type
== AR5416_EEP_RXGAIN_13DB_BACKOFF
)
541 INIT_INI_ARRAY(&ah
->iniModesRxGain
,
542 ar9280Modes_backoff_13db_rxgain_9280_2
,
543 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2
), 6);
544 else if (rxgain_type
== AR5416_EEP_RXGAIN_23DB_BACKOFF
)
545 INIT_INI_ARRAY(&ah
->iniModesRxGain
,
546 ar9280Modes_backoff_23db_rxgain_9280_2
,
547 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2
), 6);
549 INIT_INI_ARRAY(&ah
->iniModesRxGain
,
550 ar9280Modes_original_rxgain_9280_2
,
551 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2
), 6);
553 INIT_INI_ARRAY(&ah
->iniModesRxGain
,
554 ar9280Modes_original_rxgain_9280_2
,
555 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2
), 6);
559 static void ath9k_hw_init_txgain_ini(struct ath_hw
*ah
)
563 if (ah
->eep_ops
->get_eeprom(ah
, EEP_MINOR_REV
) >= AR5416_EEP_MINOR_VER_19
) {
564 txgain_type
= ah
->eep_ops
->get_eeprom(ah
, EEP_TXGAIN_TYPE
);
566 if (txgain_type
== AR5416_EEP_TXGAIN_HIGH_POWER
)
567 INIT_INI_ARRAY(&ah
->iniModesTxGain
,
568 ar9280Modes_high_power_tx_gain_9280_2
,
569 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2
), 6);
571 INIT_INI_ARRAY(&ah
->iniModesTxGain
,
572 ar9280Modes_original_tx_gain_9280_2
,
573 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2
), 6);
575 INIT_INI_ARRAY(&ah
->iniModesTxGain
,
576 ar9280Modes_original_tx_gain_9280_2
,
577 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2
), 6);
581 static int ath9k_hw_post_init(struct ath_hw
*ah
)
585 if (!ath9k_hw_chip_test(ah
))
588 ecode
= ath9k_hw_rf_claim(ah
);
592 ecode
= ath9k_hw_eeprom_init(ah
);
596 DPRINTF(ah
->ah_sc
, ATH_DBG_CONFIG
, "Eeprom VER: %d, REV: %d\n",
597 ah
->eep_ops
->get_eeprom_ver(ah
), ah
->eep_ops
->get_eeprom_rev(ah
));
599 ecode
= ath9k_hw_rfattach(ah
);
603 if (!AR_SREV_9100(ah
)) {
604 ath9k_hw_ani_setup(ah
);
605 ath9k_hw_ani_init(ah
);
611 static bool ath9k_hw_devid_supported(u16 devid
)
614 case AR5416_DEVID_PCI
:
615 case AR5416_DEVID_PCIE
:
616 case AR5416_AR9100_DEVID
:
617 case AR9160_DEVID_PCI
:
618 case AR9280_DEVID_PCI
:
619 case AR9280_DEVID_PCIE
:
620 case AR9285_DEVID_PCIE
:
621 case AR5416_DEVID_AR9287_PCI
:
622 case AR5416_DEVID_AR9287_PCIE
:
630 static bool ath9k_hw_macversion_supported(u32 macversion
)
632 switch (macversion
) {
633 case AR_SREV_VERSION_5416_PCI
:
634 case AR_SREV_VERSION_5416_PCIE
:
635 case AR_SREV_VERSION_9160
:
636 case AR_SREV_VERSION_9100
:
637 case AR_SREV_VERSION_9280
:
638 case AR_SREV_VERSION_9285
:
639 case AR_SREV_VERSION_9287
:
647 static void ath9k_hw_init_cal_settings(struct ath_hw
*ah
)
649 if (AR_SREV_9160_10_OR_LATER(ah
)) {
650 if (AR_SREV_9280_10_OR_LATER(ah
)) {
651 ah
->iq_caldata
.calData
= &iq_cal_single_sample
;
652 ah
->adcgain_caldata
.calData
=
653 &adc_gain_cal_single_sample
;
654 ah
->adcdc_caldata
.calData
=
655 &adc_dc_cal_single_sample
;
656 ah
->adcdc_calinitdata
.calData
=
659 ah
->iq_caldata
.calData
= &iq_cal_multi_sample
;
660 ah
->adcgain_caldata
.calData
=
661 &adc_gain_cal_multi_sample
;
662 ah
->adcdc_caldata
.calData
=
663 &adc_dc_cal_multi_sample
;
664 ah
->adcdc_calinitdata
.calData
=
667 ah
->supp_cals
= ADC_GAIN_CAL
| ADC_DC_CAL
| IQ_MISMATCH_CAL
;
671 static void ath9k_hw_init_mode_regs(struct ath_hw
*ah
)
673 if (AR_SREV_9287_11_OR_LATER(ah
)) {
674 INIT_INI_ARRAY(&ah
->iniModes
, ar9287Modes_9287_1_1
,
675 ARRAY_SIZE(ar9287Modes_9287_1_1
), 6);
676 INIT_INI_ARRAY(&ah
->iniCommon
, ar9287Common_9287_1_1
,
677 ARRAY_SIZE(ar9287Common_9287_1_1
), 2);
678 if (ah
->config
.pcie_clock_req
)
679 INIT_INI_ARRAY(&ah
->iniPcieSerdes
,
680 ar9287PciePhy_clkreq_off_L1_9287_1_1
,
681 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1
), 2);
683 INIT_INI_ARRAY(&ah
->iniPcieSerdes
,
684 ar9287PciePhy_clkreq_always_on_L1_9287_1_1
,
685 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1
),
687 } else if (AR_SREV_9287_10_OR_LATER(ah
)) {
688 INIT_INI_ARRAY(&ah
->iniModes
, ar9287Modes_9287_1_0
,
689 ARRAY_SIZE(ar9287Modes_9287_1_0
), 6);
690 INIT_INI_ARRAY(&ah
->iniCommon
, ar9287Common_9287_1_0
,
691 ARRAY_SIZE(ar9287Common_9287_1_0
), 2);
693 if (ah
->config
.pcie_clock_req
)
694 INIT_INI_ARRAY(&ah
->iniPcieSerdes
,
695 ar9287PciePhy_clkreq_off_L1_9287_1_0
,
696 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0
), 2);
698 INIT_INI_ARRAY(&ah
->iniPcieSerdes
,
699 ar9287PciePhy_clkreq_always_on_L1_9287_1_0
,
700 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0
),
702 } else if (AR_SREV_9285_12_OR_LATER(ah
)) {
705 INIT_INI_ARRAY(&ah
->iniModes
, ar9285Modes_9285_1_2
,
706 ARRAY_SIZE(ar9285Modes_9285_1_2
), 6);
707 INIT_INI_ARRAY(&ah
->iniCommon
, ar9285Common_9285_1_2
,
708 ARRAY_SIZE(ar9285Common_9285_1_2
), 2);
710 if (ah
->config
.pcie_clock_req
) {
711 INIT_INI_ARRAY(&ah
->iniPcieSerdes
,
712 ar9285PciePhy_clkreq_off_L1_9285_1_2
,
713 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2
), 2);
715 INIT_INI_ARRAY(&ah
->iniPcieSerdes
,
716 ar9285PciePhy_clkreq_always_on_L1_9285_1_2
,
717 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2
),
720 } else if (AR_SREV_9285_10_OR_LATER(ah
)) {
721 INIT_INI_ARRAY(&ah
->iniModes
, ar9285Modes_9285
,
722 ARRAY_SIZE(ar9285Modes_9285
), 6);
723 INIT_INI_ARRAY(&ah
->iniCommon
, ar9285Common_9285
,
724 ARRAY_SIZE(ar9285Common_9285
), 2);
726 if (ah
->config
.pcie_clock_req
) {
727 INIT_INI_ARRAY(&ah
->iniPcieSerdes
,
728 ar9285PciePhy_clkreq_off_L1_9285
,
729 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285
), 2);
731 INIT_INI_ARRAY(&ah
->iniPcieSerdes
,
732 ar9285PciePhy_clkreq_always_on_L1_9285
,
733 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285
), 2);
735 } else if (AR_SREV_9280_20_OR_LATER(ah
)) {
736 INIT_INI_ARRAY(&ah
->iniModes
, ar9280Modes_9280_2
,
737 ARRAY_SIZE(ar9280Modes_9280_2
), 6);
738 INIT_INI_ARRAY(&ah
->iniCommon
, ar9280Common_9280_2
,
739 ARRAY_SIZE(ar9280Common_9280_2
), 2);
741 if (ah
->config
.pcie_clock_req
) {
742 INIT_INI_ARRAY(&ah
->iniPcieSerdes
,
743 ar9280PciePhy_clkreq_off_L1_9280
,
744 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280
),2);
746 INIT_INI_ARRAY(&ah
->iniPcieSerdes
,
747 ar9280PciePhy_clkreq_always_on_L1_9280
,
748 ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280
), 2);
750 INIT_INI_ARRAY(&ah
->iniModesAdditional
,
751 ar9280Modes_fast_clock_9280_2
,
752 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2
), 3);
753 } else if (AR_SREV_9280_10_OR_LATER(ah
)) {
754 INIT_INI_ARRAY(&ah
->iniModes
, ar9280Modes_9280
,
755 ARRAY_SIZE(ar9280Modes_9280
), 6);
756 INIT_INI_ARRAY(&ah
->iniCommon
, ar9280Common_9280
,
757 ARRAY_SIZE(ar9280Common_9280
), 2);
758 } else if (AR_SREV_9160_10_OR_LATER(ah
)) {
759 INIT_INI_ARRAY(&ah
->iniModes
, ar5416Modes_9160
,
760 ARRAY_SIZE(ar5416Modes_9160
), 6);
761 INIT_INI_ARRAY(&ah
->iniCommon
, ar5416Common_9160
,
762 ARRAY_SIZE(ar5416Common_9160
), 2);
763 INIT_INI_ARRAY(&ah
->iniBank0
, ar5416Bank0_9160
,
764 ARRAY_SIZE(ar5416Bank0_9160
), 2);
765 INIT_INI_ARRAY(&ah
->iniBB_RfGain
, ar5416BB_RfGain_9160
,
766 ARRAY_SIZE(ar5416BB_RfGain_9160
), 3);
767 INIT_INI_ARRAY(&ah
->iniBank1
, ar5416Bank1_9160
,
768 ARRAY_SIZE(ar5416Bank1_9160
), 2);
769 INIT_INI_ARRAY(&ah
->iniBank2
, ar5416Bank2_9160
,
770 ARRAY_SIZE(ar5416Bank2_9160
), 2);
771 INIT_INI_ARRAY(&ah
->iniBank3
, ar5416Bank3_9160
,
772 ARRAY_SIZE(ar5416Bank3_9160
), 3);
773 INIT_INI_ARRAY(&ah
->iniBank6
, ar5416Bank6_9160
,
774 ARRAY_SIZE(ar5416Bank6_9160
), 3);
775 INIT_INI_ARRAY(&ah
->iniBank6TPC
, ar5416Bank6TPC_9160
,
776 ARRAY_SIZE(ar5416Bank6TPC_9160
), 3);
777 INIT_INI_ARRAY(&ah
->iniBank7
, ar5416Bank7_9160
,
778 ARRAY_SIZE(ar5416Bank7_9160
), 2);
779 if (AR_SREV_9160_11(ah
)) {
780 INIT_INI_ARRAY(&ah
->iniAddac
,
782 ARRAY_SIZE(ar5416Addac_91601_1
), 2);
784 INIT_INI_ARRAY(&ah
->iniAddac
, ar5416Addac_9160
,
785 ARRAY_SIZE(ar5416Addac_9160
), 2);
787 } else if (AR_SREV_9100_OR_LATER(ah
)) {
788 INIT_INI_ARRAY(&ah
->iniModes
, ar5416Modes_9100
,
789 ARRAY_SIZE(ar5416Modes_9100
), 6);
790 INIT_INI_ARRAY(&ah
->iniCommon
, ar5416Common_9100
,
791 ARRAY_SIZE(ar5416Common_9100
), 2);
792 INIT_INI_ARRAY(&ah
->iniBank0
, ar5416Bank0_9100
,
793 ARRAY_SIZE(ar5416Bank0_9100
), 2);
794 INIT_INI_ARRAY(&ah
->iniBB_RfGain
, ar5416BB_RfGain_9100
,
795 ARRAY_SIZE(ar5416BB_RfGain_9100
), 3);
796 INIT_INI_ARRAY(&ah
->iniBank1
, ar5416Bank1_9100
,
797 ARRAY_SIZE(ar5416Bank1_9100
), 2);
798 INIT_INI_ARRAY(&ah
->iniBank2
, ar5416Bank2_9100
,
799 ARRAY_SIZE(ar5416Bank2_9100
), 2);
800 INIT_INI_ARRAY(&ah
->iniBank3
, ar5416Bank3_9100
,
801 ARRAY_SIZE(ar5416Bank3_9100
), 3);
802 INIT_INI_ARRAY(&ah
->iniBank6
, ar5416Bank6_9100
,
803 ARRAY_SIZE(ar5416Bank6_9100
), 3);
804 INIT_INI_ARRAY(&ah
->iniBank6TPC
, ar5416Bank6TPC_9100
,
805 ARRAY_SIZE(ar5416Bank6TPC_9100
), 3);
806 INIT_INI_ARRAY(&ah
->iniBank7
, ar5416Bank7_9100
,
807 ARRAY_SIZE(ar5416Bank7_9100
), 2);
808 INIT_INI_ARRAY(&ah
->iniAddac
, ar5416Addac_9100
,
809 ARRAY_SIZE(ar5416Addac_9100
), 2);
811 INIT_INI_ARRAY(&ah
->iniModes
, ar5416Modes
,
812 ARRAY_SIZE(ar5416Modes
), 6);
813 INIT_INI_ARRAY(&ah
->iniCommon
, ar5416Common
,
814 ARRAY_SIZE(ar5416Common
), 2);
815 INIT_INI_ARRAY(&ah
->iniBank0
, ar5416Bank0
,
816 ARRAY_SIZE(ar5416Bank0
), 2);
817 INIT_INI_ARRAY(&ah
->iniBB_RfGain
, ar5416BB_RfGain
,
818 ARRAY_SIZE(ar5416BB_RfGain
), 3);
819 INIT_INI_ARRAY(&ah
->iniBank1
, ar5416Bank1
,
820 ARRAY_SIZE(ar5416Bank1
), 2);
821 INIT_INI_ARRAY(&ah
->iniBank2
, ar5416Bank2
,
822 ARRAY_SIZE(ar5416Bank2
), 2);
823 INIT_INI_ARRAY(&ah
->iniBank3
, ar5416Bank3
,
824 ARRAY_SIZE(ar5416Bank3
), 3);
825 INIT_INI_ARRAY(&ah
->iniBank6
, ar5416Bank6
,
826 ARRAY_SIZE(ar5416Bank6
), 3);
827 INIT_INI_ARRAY(&ah
->iniBank6TPC
, ar5416Bank6TPC
,
828 ARRAY_SIZE(ar5416Bank6TPC
), 3);
829 INIT_INI_ARRAY(&ah
->iniBank7
, ar5416Bank7
,
830 ARRAY_SIZE(ar5416Bank7
), 2);
831 INIT_INI_ARRAY(&ah
->iniAddac
, ar5416Addac
,
832 ARRAY_SIZE(ar5416Addac
), 2);
836 static void ath9k_hw_init_mode_gain_regs(struct ath_hw
*ah
)
838 if (AR_SREV_9287_11(ah
))
839 INIT_INI_ARRAY(&ah
->iniModesRxGain
,
840 ar9287Modes_rx_gain_9287_1_1
,
841 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1
), 6);
842 else if (AR_SREV_9287_10(ah
))
843 INIT_INI_ARRAY(&ah
->iniModesRxGain
,
844 ar9287Modes_rx_gain_9287_1_0
,
845 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0
), 6);
846 else if (AR_SREV_9280_20(ah
))
847 ath9k_hw_init_rxgain_ini(ah
);
849 if (AR_SREV_9287_11(ah
)) {
850 INIT_INI_ARRAY(&ah
->iniModesTxGain
,
851 ar9287Modes_tx_gain_9287_1_1
,
852 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1
), 6);
853 } else if (AR_SREV_9287_10(ah
)) {
854 INIT_INI_ARRAY(&ah
->iniModesTxGain
,
855 ar9287Modes_tx_gain_9287_1_0
,
856 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0
), 6);
857 } else if (AR_SREV_9280_20(ah
)) {
858 ath9k_hw_init_txgain_ini(ah
);
859 } else if (AR_SREV_9285_12_OR_LATER(ah
)) {
860 u32 txgain_type
= ah
->eep_ops
->get_eeprom(ah
, EEP_TXGAIN_TYPE
);
863 if (txgain_type
== AR5416_EEP_TXGAIN_HIGH_POWER
) {
864 INIT_INI_ARRAY(&ah
->iniModesTxGain
,
865 ar9285Modes_high_power_tx_gain_9285_1_2
,
866 ARRAY_SIZE(ar9285Modes_high_power_tx_gain_9285_1_2
), 6);
868 INIT_INI_ARRAY(&ah
->iniModesTxGain
,
869 ar9285Modes_original_tx_gain_9285_1_2
,
870 ARRAY_SIZE(ar9285Modes_original_tx_gain_9285_1_2
), 6);
876 static void ath9k_hw_init_11a_eeprom_fix(struct ath_hw
*ah
)
880 if ((ah
->hw_version
.devid
== AR9280_DEVID_PCI
) &&
881 test_bit(ATH9K_MODE_11A
, ah
->caps
.wireless_modes
)) {
884 for (i
= 0; i
< ah
->iniModes
.ia_rows
; i
++) {
885 u32 reg
= INI_RA(&ah
->iniModes
, i
, 0);
887 for (j
= 1; j
< ah
->iniModes
.ia_columns
; j
++) {
888 u32 val
= INI_RA(&ah
->iniModes
, i
, j
);
890 INI_RA(&ah
->iniModes
, i
, j
) =
891 ath9k_hw_ini_fixup(ah
,
899 int ath9k_hw_init(struct ath_hw
*ah
)
903 if (!ath9k_hw_devid_supported(ah
->hw_version
.devid
)) {
908 ath9k_hw_init_defaults(ah
);
909 ath9k_hw_init_config(ah
);
911 if (!ath9k_hw_set_reset_reg(ah
, ATH9K_RESET_POWER_ON
)) {
912 DPRINTF(ah
->ah_sc
, ATH_DBG_FATAL
, "Couldn't reset chip\n");
917 if (!ath9k_hw_setpower(ah
, ATH9K_PM_AWAKE
)) {
918 DPRINTF(ah
->ah_sc
, ATH_DBG_FATAL
, "Couldn't wakeup chip\n");
923 if (ah
->config
.serialize_regmode
== SER_REG_MODE_AUTO
) {
924 if (ah
->hw_version
.macVersion
== AR_SREV_VERSION_5416_PCI
||
925 (AR_SREV_9280(ah
) && !ah
->is_pciexpress
)) {
926 ah
->config
.serialize_regmode
=
929 ah
->config
.serialize_regmode
=
934 DPRINTF(ah
->ah_sc
, ATH_DBG_RESET
, "serialize_regmode is %d\n",
935 ah
->config
.serialize_regmode
);
937 if (!ath9k_hw_macversion_supported(ah
->hw_version
.macVersion
)) {
938 DPRINTF(ah
->ah_sc
, ATH_DBG_FATAL
,
939 "Mac Chip Rev 0x%02x.%x is not supported by "
940 "this driver\n", ah
->hw_version
.macVersion
,
941 ah
->hw_version
.macRev
);
946 if (AR_SREV_9100(ah
)) {
947 ah
->iq_caldata
.calData
= &iq_cal_multi_sample
;
948 ah
->supp_cals
= IQ_MISMATCH_CAL
;
949 ah
->is_pciexpress
= false;
951 ah
->hw_version
.phyRev
= REG_READ(ah
, AR_PHY_CHIP_ID
);
953 ath9k_hw_init_cal_settings(ah
);
955 ah
->ani_function
= ATH9K_ANI_ALL
;
956 if (AR_SREV_9280_10_OR_LATER(ah
))
957 ah
->ani_function
&= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL
;
959 ath9k_hw_init_mode_regs(ah
);
961 if (ah
->is_pciexpress
)
962 ath9k_hw_configpcipowersave(ah
, 0);
964 ath9k_hw_disablepcie(ah
);
966 r
= ath9k_hw_post_init(ah
);
970 ath9k_hw_init_mode_gain_regs(ah
);
971 ath9k_hw_fill_cap_info(ah
);
972 ath9k_hw_init_11a_eeprom_fix(ah
);
974 r
= ath9k_hw_init_macaddr(ah
);
976 DPRINTF(ah
->ah_sc
, ATH_DBG_FATAL
,
977 "Failed to initialize MAC address\n");
981 if (AR_SREV_9285(ah
))
982 ah
->tx_trig_level
= (AR_FTRIG_256B
>> AR_FTRIG_S
);
984 ah
->tx_trig_level
= (AR_FTRIG_512B
>> AR_FTRIG_S
);
986 ath9k_init_nfcal_hist_buffer(ah
);
994 static void ath9k_hw_init_bb(struct ath_hw
*ah
,
995 struct ath9k_channel
*chan
)
999 synthDelay
= REG_READ(ah
, AR_PHY_RX_DELAY
) & AR_PHY_RX_DELAY_DELAY
;
1000 if (IS_CHAN_B(chan
))
1001 synthDelay
= (4 * synthDelay
) / 22;
1005 REG_WRITE(ah
, AR_PHY_ACTIVE
, AR_PHY_ACTIVE_EN
);
1007 udelay(synthDelay
+ BASE_ACTIVATE_DELAY
);
1010 static void ath9k_hw_init_qos(struct ath_hw
*ah
)
1012 REG_WRITE(ah
, AR_MIC_QOS_CONTROL
, 0x100aa);
1013 REG_WRITE(ah
, AR_MIC_QOS_SELECT
, 0x3210);
1015 REG_WRITE(ah
, AR_QOS_NO_ACK
,
1016 SM(2, AR_QOS_NO_ACK_TWO_BIT
) |
1017 SM(5, AR_QOS_NO_ACK_BIT_OFF
) |
1018 SM(0, AR_QOS_NO_ACK_BYTE_OFF
));
1020 REG_WRITE(ah
, AR_TXOP_X
, AR_TXOP_X_VAL
);
1021 REG_WRITE(ah
, AR_TXOP_0_3
, 0xFFFFFFFF);
1022 REG_WRITE(ah
, AR_TXOP_4_7
, 0xFFFFFFFF);
1023 REG_WRITE(ah
, AR_TXOP_8_11
, 0xFFFFFFFF);
1024 REG_WRITE(ah
, AR_TXOP_12_15
, 0xFFFFFFFF);
1027 static void ath9k_hw_init_pll(struct ath_hw
*ah
,
1028 struct ath9k_channel
*chan
)
1032 if (AR_SREV_9100(ah
)) {
1033 if (chan
&& IS_CHAN_5GHZ(chan
))
1038 if (AR_SREV_9280_10_OR_LATER(ah
)) {
1039 pll
= SM(0x5, AR_RTC_9160_PLL_REFDIV
);
1041 if (chan
&& IS_CHAN_HALF_RATE(chan
))
1042 pll
|= SM(0x1, AR_RTC_9160_PLL_CLKSEL
);
1043 else if (chan
&& IS_CHAN_QUARTER_RATE(chan
))
1044 pll
|= SM(0x2, AR_RTC_9160_PLL_CLKSEL
);
1046 if (chan
&& IS_CHAN_5GHZ(chan
)) {
1047 pll
|= SM(0x28, AR_RTC_9160_PLL_DIV
);
1050 if (AR_SREV_9280_20(ah
)) {
1051 if (((chan
->channel
% 20) == 0)
1052 || ((chan
->channel
% 10) == 0))
1058 pll
|= SM(0x2c, AR_RTC_9160_PLL_DIV
);
1061 } else if (AR_SREV_9160_10_OR_LATER(ah
)) {
1063 pll
= SM(0x5, AR_RTC_9160_PLL_REFDIV
);
1065 if (chan
&& IS_CHAN_HALF_RATE(chan
))
1066 pll
|= SM(0x1, AR_RTC_9160_PLL_CLKSEL
);
1067 else if (chan
&& IS_CHAN_QUARTER_RATE(chan
))
1068 pll
|= SM(0x2, AR_RTC_9160_PLL_CLKSEL
);
1070 if (chan
&& IS_CHAN_5GHZ(chan
))
1071 pll
|= SM(0x50, AR_RTC_9160_PLL_DIV
);
1073 pll
|= SM(0x58, AR_RTC_9160_PLL_DIV
);
1075 pll
= AR_RTC_PLL_REFDIV_5
| AR_RTC_PLL_DIV2
;
1077 if (chan
&& IS_CHAN_HALF_RATE(chan
))
1078 pll
|= SM(0x1, AR_RTC_PLL_CLKSEL
);
1079 else if (chan
&& IS_CHAN_QUARTER_RATE(chan
))
1080 pll
|= SM(0x2, AR_RTC_PLL_CLKSEL
);
1082 if (chan
&& IS_CHAN_5GHZ(chan
))
1083 pll
|= SM(0xa, AR_RTC_PLL_DIV
);
1085 pll
|= SM(0xb, AR_RTC_PLL_DIV
);
1088 REG_WRITE(ah
, AR_RTC_PLL_CONTROL
, pll
);
1090 udelay(RTC_PLL_SETTLE_DELAY
);
1092 REG_WRITE(ah
, AR_RTC_SLEEP_CLK
, AR_RTC_FORCE_DERIVED_CLK
);
1095 static void ath9k_hw_init_chain_masks(struct ath_hw
*ah
)
1097 int rx_chainmask
, tx_chainmask
;
1099 rx_chainmask
= ah
->rxchainmask
;
1100 tx_chainmask
= ah
->txchainmask
;
1102 switch (rx_chainmask
) {
1104 REG_SET_BIT(ah
, AR_PHY_ANALOG_SWAP
,
1105 AR_PHY_SWAP_ALT_CHAIN
);
1107 if (((ah
)->hw_version
.macVersion
<= AR_SREV_VERSION_9160
)) {
1108 REG_WRITE(ah
, AR_PHY_RX_CHAINMASK
, 0x7);
1109 REG_WRITE(ah
, AR_PHY_CAL_CHAINMASK
, 0x7);
1115 REG_WRITE(ah
, AR_PHY_RX_CHAINMASK
, rx_chainmask
);
1116 REG_WRITE(ah
, AR_PHY_CAL_CHAINMASK
, rx_chainmask
);
1122 REG_WRITE(ah
, AR_SELFGEN_MASK
, tx_chainmask
);
1123 if (tx_chainmask
== 0x5) {
1124 REG_SET_BIT(ah
, AR_PHY_ANALOG_SWAP
,
1125 AR_PHY_SWAP_ALT_CHAIN
);
1127 if (AR_SREV_9100(ah
))
1128 REG_WRITE(ah
, AR_PHY_ANALOG_SWAP
,
1129 REG_READ(ah
, AR_PHY_ANALOG_SWAP
) | 0x00000001);
1132 static void ath9k_hw_init_interrupt_masks(struct ath_hw
*ah
,
1133 enum nl80211_iftype opmode
)
1135 ah
->mask_reg
= AR_IMR_TXERR
|
1141 if (ah
->config
.intr_mitigation
)
1142 ah
->mask_reg
|= AR_IMR_RXINTM
| AR_IMR_RXMINTR
;
1144 ah
->mask_reg
|= AR_IMR_RXOK
;
1146 ah
->mask_reg
|= AR_IMR_TXOK
;
1148 if (opmode
== NL80211_IFTYPE_AP
)
1149 ah
->mask_reg
|= AR_IMR_MIB
;
1151 REG_WRITE(ah
, AR_IMR
, ah
->mask_reg
);
1152 REG_WRITE(ah
, AR_IMR_S2
, REG_READ(ah
, AR_IMR_S2
) | AR_IMR_S2_GTT
);
1154 if (!AR_SREV_9100(ah
)) {
1155 REG_WRITE(ah
, AR_INTR_SYNC_CAUSE
, 0xFFFFFFFF);
1156 REG_WRITE(ah
, AR_INTR_SYNC_ENABLE
, AR_INTR_SYNC_DEFAULT
);
1157 REG_WRITE(ah
, AR_INTR_SYNC_MASK
, 0);
1161 static bool ath9k_hw_set_ack_timeout(struct ath_hw
*ah
, u32 us
)
1163 if (us
> ath9k_hw_mac_to_usec(ah
, MS(0xffffffff, AR_TIME_OUT_ACK
))) {
1164 DPRINTF(ah
->ah_sc
, ATH_DBG_RESET
, "bad ack timeout %u\n", us
);
1165 ah
->acktimeout
= (u32
) -1;
1168 REG_RMW_FIELD(ah
, AR_TIME_OUT
,
1169 AR_TIME_OUT_ACK
, ath9k_hw_mac_to_clks(ah
, us
));
1170 ah
->acktimeout
= us
;
1175 static bool ath9k_hw_set_cts_timeout(struct ath_hw
*ah
, u32 us
)
1177 if (us
> ath9k_hw_mac_to_usec(ah
, MS(0xffffffff, AR_TIME_OUT_CTS
))) {
1178 DPRINTF(ah
->ah_sc
, ATH_DBG_RESET
, "bad cts timeout %u\n", us
);
1179 ah
->ctstimeout
= (u32
) -1;
1182 REG_RMW_FIELD(ah
, AR_TIME_OUT
,
1183 AR_TIME_OUT_CTS
, ath9k_hw_mac_to_clks(ah
, us
));
1184 ah
->ctstimeout
= us
;
1189 static bool ath9k_hw_set_global_txtimeout(struct ath_hw
*ah
, u32 tu
)
1192 DPRINTF(ah
->ah_sc
, ATH_DBG_XMIT
,
1193 "bad global tx timeout %u\n", tu
);
1194 ah
->globaltxtimeout
= (u32
) -1;
1197 REG_RMW_FIELD(ah
, AR_GTXTO
, AR_GTXTO_TIMEOUT_LIMIT
, tu
);
1198 ah
->globaltxtimeout
= tu
;
1203 static void ath9k_hw_init_user_settings(struct ath_hw
*ah
)
1205 DPRINTF(ah
->ah_sc
, ATH_DBG_RESET
, "ah->misc_mode 0x%x\n",
1208 if (ah
->misc_mode
!= 0)
1209 REG_WRITE(ah
, AR_PCU_MISC
,
1210 REG_READ(ah
, AR_PCU_MISC
) | ah
->misc_mode
);
1211 if (ah
->slottime
!= (u32
) -1)
1212 ath9k_hw_setslottime(ah
, ah
->slottime
);
1213 if (ah
->acktimeout
!= (u32
) -1)
1214 ath9k_hw_set_ack_timeout(ah
, ah
->acktimeout
);
1215 if (ah
->ctstimeout
!= (u32
) -1)
1216 ath9k_hw_set_cts_timeout(ah
, ah
->ctstimeout
);
1217 if (ah
->globaltxtimeout
!= (u32
) -1)
1218 ath9k_hw_set_global_txtimeout(ah
, ah
->globaltxtimeout
);
1221 const char *ath9k_hw_probe(u16 vendorid
, u16 devid
)
1223 return vendorid
== ATHEROS_VENDOR_ID
?
1224 ath9k_hw_devname(devid
) : NULL
;
1227 void ath9k_hw_detach(struct ath_hw
*ah
)
1229 if (!AR_SREV_9100(ah
))
1230 ath9k_hw_ani_detach(ah
);
1232 ath9k_hw_rfdetach(ah
);
1233 ath9k_hw_setpower(ah
, ATH9K_PM_FULL_SLEEP
);
1241 static void ath9k_hw_override_ini(struct ath_hw
*ah
,
1242 struct ath9k_channel
*chan
)
1245 * Set the RX_ABORT and RX_DIS and clear if off only after
1246 * RXE is set for MAC. This prevents frames with corrupted
1247 * descriptor status.
1249 REG_SET_BIT(ah
, AR_DIAG_SW
, (AR_DIAG_RX_DIS
| AR_DIAG_RX_ABORT
));
1252 if (!AR_SREV_5416_20_OR_LATER(ah
) ||
1253 AR_SREV_9280_10_OR_LATER(ah
))
1256 REG_WRITE(ah
, 0x9800 + (651 << 2), 0x11);
1259 static u32
ath9k_hw_def_ini_fixup(struct ath_hw
*ah
,
1260 struct ar5416_eeprom_def
*pEepData
,
1263 struct base_eep_header
*pBase
= &(pEepData
->baseEepHeader
);
1265 switch (ah
->hw_version
.devid
) {
1266 case AR9280_DEVID_PCI
:
1267 if (reg
== 0x7894) {
1268 DPRINTF(ah
->ah_sc
, ATH_DBG_EEPROM
,
1269 "ini VAL: %x EEPROM: %x\n", value
,
1270 (pBase
->version
& 0xff));
1272 if ((pBase
->version
& 0xff) > 0x0a) {
1273 DPRINTF(ah
->ah_sc
, ATH_DBG_EEPROM
,
1276 value
&= ~AR_AN_TOP2_PWDCLKIND
;
1277 value
|= AR_AN_TOP2_PWDCLKIND
&
1278 (pBase
->pwdclkind
<< AR_AN_TOP2_PWDCLKIND_S
);
1280 DPRINTF(ah
->ah_sc
, ATH_DBG_EEPROM
,
1281 "PWDCLKIND Earlier Rev\n");
1284 DPRINTF(ah
->ah_sc
, ATH_DBG_EEPROM
,
1285 "final ini VAL: %x\n", value
);
1293 static u32
ath9k_hw_ini_fixup(struct ath_hw
*ah
,
1294 struct ar5416_eeprom_def
*pEepData
,
1297 if (ah
->eep_map
== EEP_MAP_4KBITS
)
1300 return ath9k_hw_def_ini_fixup(ah
, pEepData
, reg
, value
);
1303 static void ath9k_olc_init(struct ath_hw
*ah
)
1307 for (i
= 0; i
< AR9280_TX_GAIN_TABLE_SIZE
; i
++)
1308 ah
->originalGain
[i
] =
1309 MS(REG_READ(ah
, AR_PHY_TX_GAIN_TBL1
+ i
* 4),
1314 static u32
ath9k_regd_get_ctl(struct ath_regulatory
*reg
,
1315 struct ath9k_channel
*chan
)
1317 u32 ctl
= ath_regd_get_band_ctl(reg
, chan
->chan
->band
);
1319 if (IS_CHAN_B(chan
))
1321 else if (IS_CHAN_G(chan
))
1329 static int ath9k_hw_process_ini(struct ath_hw
*ah
,
1330 struct ath9k_channel
*chan
,
1331 enum ath9k_ht_macmode macmode
)
1333 int i
, regWrites
= 0;
1334 struct ieee80211_channel
*channel
= chan
->chan
;
1335 u32 modesIndex
, freqIndex
;
1337 switch (chan
->chanmode
) {
1339 case CHANNEL_A_HT20
:
1343 case CHANNEL_A_HT40PLUS
:
1344 case CHANNEL_A_HT40MINUS
:
1349 case CHANNEL_G_HT20
:
1354 case CHANNEL_G_HT40PLUS
:
1355 case CHANNEL_G_HT40MINUS
:
1364 REG_WRITE(ah
, AR_PHY(0), 0x00000007);
1365 REG_WRITE(ah
, AR_PHY_ADC_SERIAL_CTL
, AR_PHY_SEL_EXTERNAL_RADIO
);
1366 ah
->eep_ops
->set_addac(ah
, chan
);
1368 if (AR_SREV_5416_22_OR_LATER(ah
)) {
1369 REG_WRITE_ARRAY(&ah
->iniAddac
, 1, regWrites
);
1371 struct ar5416IniArray temp
;
1373 sizeof(u32
) * ah
->iniAddac
.ia_rows
*
1374 ah
->iniAddac
.ia_columns
;
1376 memcpy(ah
->addac5416_21
,
1377 ah
->iniAddac
.ia_array
, addacSize
);
1379 (ah
->addac5416_21
)[31 * ah
->iniAddac
.ia_columns
+ 1] = 0;
1381 temp
.ia_array
= ah
->addac5416_21
;
1382 temp
.ia_columns
= ah
->iniAddac
.ia_columns
;
1383 temp
.ia_rows
= ah
->iniAddac
.ia_rows
;
1384 REG_WRITE_ARRAY(&temp
, 1, regWrites
);
1387 REG_WRITE(ah
, AR_PHY_ADC_SERIAL_CTL
, AR_PHY_SEL_INTERNAL_ADDAC
);
1389 for (i
= 0; i
< ah
->iniModes
.ia_rows
; i
++) {
1390 u32 reg
= INI_RA(&ah
->iniModes
, i
, 0);
1391 u32 val
= INI_RA(&ah
->iniModes
, i
, modesIndex
);
1393 REG_WRITE(ah
, reg
, val
);
1395 if (reg
>= 0x7800 && reg
< 0x78a0
1396 && ah
->config
.analog_shiftreg
) {
1400 DO_DELAY(regWrites
);
1403 if (AR_SREV_9280(ah
) || AR_SREV_9287_10_OR_LATER(ah
))
1404 REG_WRITE_ARRAY(&ah
->iniModesRxGain
, modesIndex
, regWrites
);
1406 if (AR_SREV_9280(ah
) || AR_SREV_9285_12_OR_LATER(ah
) ||
1407 AR_SREV_9287_10_OR_LATER(ah
))
1408 REG_WRITE_ARRAY(&ah
->iniModesTxGain
, modesIndex
, regWrites
);
1410 for (i
= 0; i
< ah
->iniCommon
.ia_rows
; i
++) {
1411 u32 reg
= INI_RA(&ah
->iniCommon
, i
, 0);
1412 u32 val
= INI_RA(&ah
->iniCommon
, i
, 1);
1414 REG_WRITE(ah
, reg
, val
);
1416 if (reg
>= 0x7800 && reg
< 0x78a0
1417 && ah
->config
.analog_shiftreg
) {
1421 DO_DELAY(regWrites
);
1424 ath9k_hw_write_regs(ah
, modesIndex
, freqIndex
, regWrites
);
1426 if (AR_SREV_9280_20(ah
) && IS_CHAN_A_5MHZ_SPACED(chan
)) {
1427 REG_WRITE_ARRAY(&ah
->iniModesAdditional
, modesIndex
,
1431 ath9k_hw_override_ini(ah
, chan
);
1432 ath9k_hw_set_regs(ah
, chan
, macmode
);
1433 ath9k_hw_init_chain_masks(ah
);
1435 if (OLC_FOR_AR9280_20_LATER
)
1438 ah
->eep_ops
->set_txpower(ah
, chan
,
1439 ath9k_regd_get_ctl(&ah
->regulatory
, chan
),
1440 channel
->max_antenna_gain
* 2,
1441 channel
->max_power
* 2,
1442 min((u32
) MAX_RATE_POWER
,
1443 (u32
) ah
->regulatory
.power_limit
));
1445 if (!ath9k_hw_set_rf_regs(ah
, chan
, freqIndex
)) {
1446 DPRINTF(ah
->ah_sc
, ATH_DBG_FATAL
,
1447 "ar5416SetRfRegs failed\n");
1454 /****************************************/
1455 /* Reset and Channel Switching Routines */
1456 /****************************************/
1458 static void ath9k_hw_set_rfmode(struct ath_hw
*ah
, struct ath9k_channel
*chan
)
1465 rfMode
|= (IS_CHAN_B(chan
) || IS_CHAN_G(chan
))
1466 ? AR_PHY_MODE_DYNAMIC
: AR_PHY_MODE_OFDM
;
1468 if (!AR_SREV_9280_10_OR_LATER(ah
))
1469 rfMode
|= (IS_CHAN_5GHZ(chan
)) ?
1470 AR_PHY_MODE_RF5GHZ
: AR_PHY_MODE_RF2GHZ
;
1472 if (AR_SREV_9280_20(ah
) && IS_CHAN_A_5MHZ_SPACED(chan
))
1473 rfMode
|= (AR_PHY_MODE_DYNAMIC
| AR_PHY_MODE_DYN_CCK_DISABLE
);
1475 REG_WRITE(ah
, AR_PHY_MODE
, rfMode
);
1478 static void ath9k_hw_mark_phy_inactive(struct ath_hw
*ah
)
1480 REG_WRITE(ah
, AR_PHY_ACTIVE
, AR_PHY_ACTIVE_DIS
);
1483 static inline void ath9k_hw_set_dma(struct ath_hw
*ah
)
1487 regval
= REG_READ(ah
, AR_AHB_MODE
);
1488 REG_WRITE(ah
, AR_AHB_MODE
, regval
| AR_AHB_PREFETCH_RD_EN
);
1490 regval
= REG_READ(ah
, AR_TXCFG
) & ~AR_TXCFG_DMASZ_MASK
;
1491 REG_WRITE(ah
, AR_TXCFG
, regval
| AR_TXCFG_DMASZ_128B
);
1493 REG_RMW_FIELD(ah
, AR_TXCFG
, AR_FTRIG
, ah
->tx_trig_level
);
1495 regval
= REG_READ(ah
, AR_RXCFG
) & ~AR_RXCFG_DMASZ_MASK
;
1496 REG_WRITE(ah
, AR_RXCFG
, regval
| AR_RXCFG_DMASZ_128B
);
1498 REG_WRITE(ah
, AR_RXFIFO_CFG
, 0x200);
1500 if (AR_SREV_9285(ah
)) {
1501 REG_WRITE(ah
, AR_PCU_TXBUF_CTRL
,
1502 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE
);
1504 REG_WRITE(ah
, AR_PCU_TXBUF_CTRL
,
1505 AR_PCU_TXBUF_CTRL_USABLE_SIZE
);
1509 static void ath9k_hw_set_operating_mode(struct ath_hw
*ah
, int opmode
)
1513 val
= REG_READ(ah
, AR_STA_ID1
);
1514 val
&= ~(AR_STA_ID1_STA_AP
| AR_STA_ID1_ADHOC
);
1516 case NL80211_IFTYPE_AP
:
1517 REG_WRITE(ah
, AR_STA_ID1
, val
| AR_STA_ID1_STA_AP
1518 | AR_STA_ID1_KSRCH_MODE
);
1519 REG_CLR_BIT(ah
, AR_CFG
, AR_CFG_AP_ADHOC_INDICATION
);
1521 case NL80211_IFTYPE_ADHOC
:
1522 case NL80211_IFTYPE_MESH_POINT
:
1523 REG_WRITE(ah
, AR_STA_ID1
, val
| AR_STA_ID1_ADHOC
1524 | AR_STA_ID1_KSRCH_MODE
);
1525 REG_SET_BIT(ah
, AR_CFG
, AR_CFG_AP_ADHOC_INDICATION
);
1527 case NL80211_IFTYPE_STATION
:
1528 case NL80211_IFTYPE_MONITOR
:
1529 REG_WRITE(ah
, AR_STA_ID1
, val
| AR_STA_ID1_KSRCH_MODE
);
1534 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw
*ah
,
1539 u32 coef_exp
, coef_man
;
1541 for (coef_exp
= 31; coef_exp
> 0; coef_exp
--)
1542 if ((coef_scaled
>> coef_exp
) & 0x1)
1545 coef_exp
= 14 - (coef_exp
- COEF_SCALE_S
);
1547 coef_man
= coef_scaled
+ (1 << (COEF_SCALE_S
- coef_exp
- 1));
1549 *coef_mantissa
= coef_man
>> (COEF_SCALE_S
- coef_exp
);
1550 *coef_exponent
= coef_exp
- 16;
1553 static void ath9k_hw_set_delta_slope(struct ath_hw
*ah
,
1554 struct ath9k_channel
*chan
)
1556 u32 coef_scaled
, ds_coef_exp
, ds_coef_man
;
1557 u32 clockMhzScaled
= 0x64000000;
1558 struct chan_centers centers
;
1560 if (IS_CHAN_HALF_RATE(chan
))
1561 clockMhzScaled
= clockMhzScaled
>> 1;
1562 else if (IS_CHAN_QUARTER_RATE(chan
))
1563 clockMhzScaled
= clockMhzScaled
>> 2;
1565 ath9k_hw_get_channel_centers(ah
, chan
, ¢ers
);
1566 coef_scaled
= clockMhzScaled
/ centers
.synth_center
;
1568 ath9k_hw_get_delta_slope_vals(ah
, coef_scaled
, &ds_coef_man
,
1571 REG_RMW_FIELD(ah
, AR_PHY_TIMING3
,
1572 AR_PHY_TIMING3_DSC_MAN
, ds_coef_man
);
1573 REG_RMW_FIELD(ah
, AR_PHY_TIMING3
,
1574 AR_PHY_TIMING3_DSC_EXP
, ds_coef_exp
);
1576 coef_scaled
= (9 * coef_scaled
) / 10;
1578 ath9k_hw_get_delta_slope_vals(ah
, coef_scaled
, &ds_coef_man
,
1581 REG_RMW_FIELD(ah
, AR_PHY_HALFGI
,
1582 AR_PHY_HALFGI_DSC_MAN
, ds_coef_man
);
1583 REG_RMW_FIELD(ah
, AR_PHY_HALFGI
,
1584 AR_PHY_HALFGI_DSC_EXP
, ds_coef_exp
);
1587 static bool ath9k_hw_set_reset(struct ath_hw
*ah
, int type
)
1592 if (AR_SREV_9100(ah
)) {
1593 u32 val
= REG_READ(ah
, AR_RTC_DERIVED_CLK
);
1594 val
&= ~AR_RTC_DERIVED_CLK_PERIOD
;
1595 val
|= SM(1, AR_RTC_DERIVED_CLK_PERIOD
);
1596 REG_WRITE(ah
, AR_RTC_DERIVED_CLK
, val
);
1597 (void)REG_READ(ah
, AR_RTC_DERIVED_CLK
);
1600 REG_WRITE(ah
, AR_RTC_FORCE_WAKE
, AR_RTC_FORCE_WAKE_EN
|
1601 AR_RTC_FORCE_WAKE_ON_INT
);
1603 if (AR_SREV_9100(ah
)) {
1604 rst_flags
= AR_RTC_RC_MAC_WARM
| AR_RTC_RC_MAC_COLD
|
1605 AR_RTC_RC_COLD_RESET
| AR_RTC_RC_WARM_RESET
;
1607 tmpReg
= REG_READ(ah
, AR_INTR_SYNC_CAUSE
);
1609 (AR_INTR_SYNC_LOCAL_TIMEOUT
|
1610 AR_INTR_SYNC_RADM_CPL_TIMEOUT
)) {
1611 REG_WRITE(ah
, AR_INTR_SYNC_ENABLE
, 0);
1612 REG_WRITE(ah
, AR_RC
, AR_RC_AHB
| AR_RC_HOSTIF
);
1614 REG_WRITE(ah
, AR_RC
, AR_RC_AHB
);
1617 rst_flags
= AR_RTC_RC_MAC_WARM
;
1618 if (type
== ATH9K_RESET_COLD
)
1619 rst_flags
|= AR_RTC_RC_MAC_COLD
;
1622 REG_WRITE(ah
, AR_RTC_RC
, rst_flags
);
1625 REG_WRITE(ah
, AR_RTC_RC
, 0);
1626 if (!ath9k_hw_wait(ah
, AR_RTC_RC
, AR_RTC_RC_M
, 0, AH_WAIT_TIMEOUT
)) {
1627 DPRINTF(ah
->ah_sc
, ATH_DBG_RESET
,
1628 "RTC stuck in MAC reset\n");
1632 if (!AR_SREV_9100(ah
))
1633 REG_WRITE(ah
, AR_RC
, 0);
1635 ath9k_hw_init_pll(ah
, NULL
);
1637 if (AR_SREV_9100(ah
))
1643 static bool ath9k_hw_set_reset_power_on(struct ath_hw
*ah
)
1645 REG_WRITE(ah
, AR_RTC_FORCE_WAKE
, AR_RTC_FORCE_WAKE_EN
|
1646 AR_RTC_FORCE_WAKE_ON_INT
);
1648 REG_WRITE(ah
, AR_RTC_RESET
, 0);
1650 REG_WRITE(ah
, AR_RTC_RESET
, 1);
1652 if (!ath9k_hw_wait(ah
,
1657 DPRINTF(ah
->ah_sc
, ATH_DBG_RESET
, "RTC not waking up\n");
1661 ath9k_hw_read_revisions(ah
);
1663 return ath9k_hw_set_reset(ah
, ATH9K_RESET_WARM
);
1666 static bool ath9k_hw_set_reset_reg(struct ath_hw
*ah
, u32 type
)
1668 REG_WRITE(ah
, AR_RTC_FORCE_WAKE
,
1669 AR_RTC_FORCE_WAKE_EN
| AR_RTC_FORCE_WAKE_ON_INT
);
1672 case ATH9K_RESET_POWER_ON
:
1673 return ath9k_hw_set_reset_power_on(ah
);
1674 case ATH9K_RESET_WARM
:
1675 case ATH9K_RESET_COLD
:
1676 return ath9k_hw_set_reset(ah
, type
);
1682 static void ath9k_hw_set_regs(struct ath_hw
*ah
, struct ath9k_channel
*chan
,
1683 enum ath9k_ht_macmode macmode
)
1686 u32 enableDacFifo
= 0;
1688 if (AR_SREV_9285_10_OR_LATER(ah
))
1689 enableDacFifo
= (REG_READ(ah
, AR_PHY_TURBO
) &
1690 AR_PHY_FC_ENABLE_DAC_FIFO
);
1692 phymode
= AR_PHY_FC_HT_EN
| AR_PHY_FC_SHORT_GI_40
1693 | AR_PHY_FC_SINGLE_HT_LTF1
| AR_PHY_FC_WALSH
| enableDacFifo
;
1695 if (IS_CHAN_HT40(chan
)) {
1696 phymode
|= AR_PHY_FC_DYN2040_EN
;
1698 if ((chan
->chanmode
== CHANNEL_A_HT40PLUS
) ||
1699 (chan
->chanmode
== CHANNEL_G_HT40PLUS
))
1700 phymode
|= AR_PHY_FC_DYN2040_PRI_CH
;
1702 if (ah
->extprotspacing
== ATH9K_HT_EXTPROTSPACING_25
)
1703 phymode
|= AR_PHY_FC_DYN2040_EXT_CH
;
1705 REG_WRITE(ah
, AR_PHY_TURBO
, phymode
);
1707 ath9k_hw_set11nmac2040(ah
, macmode
);
1709 REG_WRITE(ah
, AR_GTXTO
, 25 << AR_GTXTO_TIMEOUT_LIMIT_S
);
1710 REG_WRITE(ah
, AR_CST
, 0xF << AR_CST_TIMEOUT_LIMIT_S
);
1713 static bool ath9k_hw_chip_reset(struct ath_hw
*ah
,
1714 struct ath9k_channel
*chan
)
1716 if (OLC_FOR_AR9280_20_LATER
) {
1717 if (!ath9k_hw_set_reset_reg(ah
, ATH9K_RESET_POWER_ON
))
1719 } else if (!ath9k_hw_set_reset_reg(ah
, ATH9K_RESET_WARM
))
1722 if (!ath9k_hw_setpower(ah
, ATH9K_PM_AWAKE
))
1725 ah
->chip_fullsleep
= false;
1726 ath9k_hw_init_pll(ah
, chan
);
1727 ath9k_hw_set_rfmode(ah
, chan
);
1732 static bool ath9k_hw_channel_change(struct ath_hw
*ah
,
1733 struct ath9k_channel
*chan
,
1734 enum ath9k_ht_macmode macmode
)
1736 struct ieee80211_channel
*channel
= chan
->chan
;
1737 u32 synthDelay
, qnum
;
1739 for (qnum
= 0; qnum
< AR_NUM_QCU
; qnum
++) {
1740 if (ath9k_hw_numtxpending(ah
, qnum
)) {
1741 DPRINTF(ah
->ah_sc
, ATH_DBG_QUEUE
,
1742 "Transmit frames pending on queue %d\n", qnum
);
1747 REG_WRITE(ah
, AR_PHY_RFBUS_REQ
, AR_PHY_RFBUS_REQ_EN
);
1748 if (!ath9k_hw_wait(ah
, AR_PHY_RFBUS_GRANT
, AR_PHY_RFBUS_GRANT_EN
,
1749 AR_PHY_RFBUS_GRANT_EN
, AH_WAIT_TIMEOUT
)) {
1750 DPRINTF(ah
->ah_sc
, ATH_DBG_FATAL
,
1751 "Could not kill baseband RX\n");
1755 ath9k_hw_set_regs(ah
, chan
, macmode
);
1757 if (AR_SREV_9280_10_OR_LATER(ah
)) {
1758 ath9k_hw_ar9280_set_channel(ah
, chan
);
1760 if (!(ath9k_hw_set_channel(ah
, chan
))) {
1761 DPRINTF(ah
->ah_sc
, ATH_DBG_FATAL
,
1762 "Failed to set channel\n");
1767 ah
->eep_ops
->set_txpower(ah
, chan
,
1768 ath9k_regd_get_ctl(&ah
->regulatory
, chan
),
1769 channel
->max_antenna_gain
* 2,
1770 channel
->max_power
* 2,
1771 min((u32
) MAX_RATE_POWER
,
1772 (u32
) ah
->regulatory
.power_limit
));
1774 synthDelay
= REG_READ(ah
, AR_PHY_RX_DELAY
) & AR_PHY_RX_DELAY_DELAY
;
1775 if (IS_CHAN_B(chan
))
1776 synthDelay
= (4 * synthDelay
) / 22;
1780 udelay(synthDelay
+ BASE_ACTIVATE_DELAY
);
1782 REG_WRITE(ah
, AR_PHY_RFBUS_REQ
, 0);
1784 if (IS_CHAN_OFDM(chan
) || IS_CHAN_HT(chan
))
1785 ath9k_hw_set_delta_slope(ah
, chan
);
1787 if (AR_SREV_9280_10_OR_LATER(ah
))
1788 ath9k_hw_9280_spur_mitigate(ah
, chan
);
1790 ath9k_hw_spur_mitigate(ah
, chan
);
1792 if (!chan
->oneTimeCalsDone
)
1793 chan
->oneTimeCalsDone
= true;
1798 static void ath9k_hw_9280_spur_mitigate(struct ath_hw
*ah
, struct ath9k_channel
*chan
)
1800 int bb_spur
= AR_NO_SPUR
;
1803 int bb_spur_off
, spur_subchannel_sd
;
1805 int spur_delta_phase
;
1807 int upper
, lower
, cur_vit_mask
;
1810 int pilot_mask_reg
[4] = { AR_PHY_TIMING7
, AR_PHY_TIMING8
,
1811 AR_PHY_PILOT_MASK_01_30
, AR_PHY_PILOT_MASK_31_60
1813 int chan_mask_reg
[4] = { AR_PHY_TIMING9
, AR_PHY_TIMING10
,
1814 AR_PHY_CHANNEL_MASK_01_30
, AR_PHY_CHANNEL_MASK_31_60
1816 int inc
[4] = { 0, 100, 0, 0 };
1817 struct chan_centers centers
;
1824 bool is2GHz
= IS_CHAN_2GHZ(chan
);
1826 memset(&mask_m
, 0, sizeof(int8_t) * 123);
1827 memset(&mask_p
, 0, sizeof(int8_t) * 123);
1829 ath9k_hw_get_channel_centers(ah
, chan
, ¢ers
);
1830 freq
= centers
.synth_center
;
1832 ah
->config
.spurmode
= SPUR_ENABLE_EEPROM
;
1833 for (i
= 0; i
< AR_EEPROM_MODAL_SPURS
; i
++) {
1834 cur_bb_spur
= ah
->eep_ops
->get_spur_channel(ah
, i
, is2GHz
);
1837 cur_bb_spur
= (cur_bb_spur
/ 10) + AR_BASE_FREQ_2GHZ
;
1839 cur_bb_spur
= (cur_bb_spur
/ 10) + AR_BASE_FREQ_5GHZ
;
1841 if (AR_NO_SPUR
== cur_bb_spur
)
1843 cur_bb_spur
= cur_bb_spur
- freq
;
1845 if (IS_CHAN_HT40(chan
)) {
1846 if ((cur_bb_spur
> -AR_SPUR_FEEQ_BOUND_HT40
) &&
1847 (cur_bb_spur
< AR_SPUR_FEEQ_BOUND_HT40
)) {
1848 bb_spur
= cur_bb_spur
;
1851 } else if ((cur_bb_spur
> -AR_SPUR_FEEQ_BOUND_HT20
) &&
1852 (cur_bb_spur
< AR_SPUR_FEEQ_BOUND_HT20
)) {
1853 bb_spur
= cur_bb_spur
;
1858 if (AR_NO_SPUR
== bb_spur
) {
1859 REG_CLR_BIT(ah
, AR_PHY_FORCE_CLKEN_CCK
,
1860 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX
);
1863 REG_CLR_BIT(ah
, AR_PHY_FORCE_CLKEN_CCK
,
1864 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX
);
1867 bin
= bb_spur
* 320;
1869 tmp
= REG_READ(ah
, AR_PHY_TIMING_CTRL4(0));
1871 newVal
= tmp
| (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI
|
1872 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER
|
1873 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK
|
1874 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK
);
1875 REG_WRITE(ah
, AR_PHY_TIMING_CTRL4(0), newVal
);
1877 newVal
= (AR_PHY_SPUR_REG_MASK_RATE_CNTL
|
1878 AR_PHY_SPUR_REG_ENABLE_MASK_PPM
|
1879 AR_PHY_SPUR_REG_MASK_RATE_SELECT
|
1880 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI
|
1881 SM(SPUR_RSSI_THRESH
, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH
));
1882 REG_WRITE(ah
, AR_PHY_SPUR_REG
, newVal
);
1884 if (IS_CHAN_HT40(chan
)) {
1886 spur_subchannel_sd
= 1;
1887 bb_spur_off
= bb_spur
+ 10;
1889 spur_subchannel_sd
= 0;
1890 bb_spur_off
= bb_spur
- 10;
1893 spur_subchannel_sd
= 0;
1894 bb_spur_off
= bb_spur
;
1897 if (IS_CHAN_HT40(chan
))
1899 ((bb_spur
* 262144) /
1900 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE
;
1903 ((bb_spur
* 524288) /
1904 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE
;
1906 denominator
= IS_CHAN_2GHZ(chan
) ? 44 : 40;
1907 spur_freq_sd
= ((bb_spur_off
* 2048) / denominator
) & 0x3ff;
1909 newVal
= (AR_PHY_TIMING11_USE_SPUR_IN_AGC
|
1910 SM(spur_freq_sd
, AR_PHY_TIMING11_SPUR_FREQ_SD
) |
1911 SM(spur_delta_phase
, AR_PHY_TIMING11_SPUR_DELTA_PHASE
));
1912 REG_WRITE(ah
, AR_PHY_TIMING11
, newVal
);
1914 newVal
= spur_subchannel_sd
<< AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S
;
1915 REG_WRITE(ah
, AR_PHY_SFCORR_EXT
, newVal
);
1921 for (i
= 0; i
< 4; i
++) {
1925 for (bp
= 0; bp
< 30; bp
++) {
1926 if ((cur_bin
> lower
) && (cur_bin
< upper
)) {
1927 pilot_mask
= pilot_mask
| 0x1 << bp
;
1928 chan_mask
= chan_mask
| 0x1 << bp
;
1933 REG_WRITE(ah
, pilot_mask_reg
[i
], pilot_mask
);
1934 REG_WRITE(ah
, chan_mask_reg
[i
], chan_mask
);
1937 cur_vit_mask
= 6100;
1941 for (i
= 0; i
< 123; i
++) {
1942 if ((cur_vit_mask
> lower
) && (cur_vit_mask
< upper
)) {
1944 /* workaround for gcc bug #37014 */
1945 volatile int tmp_v
= abs(cur_vit_mask
- bin
);
1951 if (cur_vit_mask
< 0)
1952 mask_m
[abs(cur_vit_mask
/ 100)] = mask_amt
;
1954 mask_p
[cur_vit_mask
/ 100] = mask_amt
;
1956 cur_vit_mask
-= 100;
1959 tmp_mask
= (mask_m
[46] << 30) | (mask_m
[47] << 28)
1960 | (mask_m
[48] << 26) | (mask_m
[49] << 24)
1961 | (mask_m
[50] << 22) | (mask_m
[51] << 20)
1962 | (mask_m
[52] << 18) | (mask_m
[53] << 16)
1963 | (mask_m
[54] << 14) | (mask_m
[55] << 12)
1964 | (mask_m
[56] << 10) | (mask_m
[57] << 8)
1965 | (mask_m
[58] << 6) | (mask_m
[59] << 4)
1966 | (mask_m
[60] << 2) | (mask_m
[61] << 0);
1967 REG_WRITE(ah
, AR_PHY_BIN_MASK_1
, tmp_mask
);
1968 REG_WRITE(ah
, AR_PHY_VIT_MASK2_M_46_61
, tmp_mask
);
1970 tmp_mask
= (mask_m
[31] << 28)
1971 | (mask_m
[32] << 26) | (mask_m
[33] << 24)
1972 | (mask_m
[34] << 22) | (mask_m
[35] << 20)
1973 | (mask_m
[36] << 18) | (mask_m
[37] << 16)
1974 | (mask_m
[48] << 14) | (mask_m
[39] << 12)
1975 | (mask_m
[40] << 10) | (mask_m
[41] << 8)
1976 | (mask_m
[42] << 6) | (mask_m
[43] << 4)
1977 | (mask_m
[44] << 2) | (mask_m
[45] << 0);
1978 REG_WRITE(ah
, AR_PHY_BIN_MASK_2
, tmp_mask
);
1979 REG_WRITE(ah
, AR_PHY_MASK2_M_31_45
, tmp_mask
);
1981 tmp_mask
= (mask_m
[16] << 30) | (mask_m
[16] << 28)
1982 | (mask_m
[18] << 26) | (mask_m
[18] << 24)
1983 | (mask_m
[20] << 22) | (mask_m
[20] << 20)
1984 | (mask_m
[22] << 18) | (mask_m
[22] << 16)
1985 | (mask_m
[24] << 14) | (mask_m
[24] << 12)
1986 | (mask_m
[25] << 10) | (mask_m
[26] << 8)
1987 | (mask_m
[27] << 6) | (mask_m
[28] << 4)
1988 | (mask_m
[29] << 2) | (mask_m
[30] << 0);
1989 REG_WRITE(ah
, AR_PHY_BIN_MASK_3
, tmp_mask
);
1990 REG_WRITE(ah
, AR_PHY_MASK2_M_16_30
, tmp_mask
);
1992 tmp_mask
= (mask_m
[0] << 30) | (mask_m
[1] << 28)
1993 | (mask_m
[2] << 26) | (mask_m
[3] << 24)
1994 | (mask_m
[4] << 22) | (mask_m
[5] << 20)
1995 | (mask_m
[6] << 18) | (mask_m
[7] << 16)
1996 | (mask_m
[8] << 14) | (mask_m
[9] << 12)
1997 | (mask_m
[10] << 10) | (mask_m
[11] << 8)
1998 | (mask_m
[12] << 6) | (mask_m
[13] << 4)
1999 | (mask_m
[14] << 2) | (mask_m
[15] << 0);
2000 REG_WRITE(ah
, AR_PHY_MASK_CTL
, tmp_mask
);
2001 REG_WRITE(ah
, AR_PHY_MASK2_M_00_15
, tmp_mask
);
2003 tmp_mask
= (mask_p
[15] << 28)
2004 | (mask_p
[14] << 26) | (mask_p
[13] << 24)
2005 | (mask_p
[12] << 22) | (mask_p
[11] << 20)
2006 | (mask_p
[10] << 18) | (mask_p
[9] << 16)
2007 | (mask_p
[8] << 14) | (mask_p
[7] << 12)
2008 | (mask_p
[6] << 10) | (mask_p
[5] << 8)
2009 | (mask_p
[4] << 6) | (mask_p
[3] << 4)
2010 | (mask_p
[2] << 2) | (mask_p
[1] << 0);
2011 REG_WRITE(ah
, AR_PHY_BIN_MASK2_1
, tmp_mask
);
2012 REG_WRITE(ah
, AR_PHY_MASK2_P_15_01
, tmp_mask
);
2014 tmp_mask
= (mask_p
[30] << 28)
2015 | (mask_p
[29] << 26) | (mask_p
[28] << 24)
2016 | (mask_p
[27] << 22) | (mask_p
[26] << 20)
2017 | (mask_p
[25] << 18) | (mask_p
[24] << 16)
2018 | (mask_p
[23] << 14) | (mask_p
[22] << 12)
2019 | (mask_p
[21] << 10) | (mask_p
[20] << 8)
2020 | (mask_p
[19] << 6) | (mask_p
[18] << 4)
2021 | (mask_p
[17] << 2) | (mask_p
[16] << 0);
2022 REG_WRITE(ah
, AR_PHY_BIN_MASK2_2
, tmp_mask
);
2023 REG_WRITE(ah
, AR_PHY_MASK2_P_30_16
, tmp_mask
);
2025 tmp_mask
= (mask_p
[45] << 28)
2026 | (mask_p
[44] << 26) | (mask_p
[43] << 24)
2027 | (mask_p
[42] << 22) | (mask_p
[41] << 20)
2028 | (mask_p
[40] << 18) | (mask_p
[39] << 16)
2029 | (mask_p
[38] << 14) | (mask_p
[37] << 12)
2030 | (mask_p
[36] << 10) | (mask_p
[35] << 8)
2031 | (mask_p
[34] << 6) | (mask_p
[33] << 4)
2032 | (mask_p
[32] << 2) | (mask_p
[31] << 0);
2033 REG_WRITE(ah
, AR_PHY_BIN_MASK2_3
, tmp_mask
);
2034 REG_WRITE(ah
, AR_PHY_MASK2_P_45_31
, tmp_mask
);
2036 tmp_mask
= (mask_p
[61] << 30) | (mask_p
[60] << 28)
2037 | (mask_p
[59] << 26) | (mask_p
[58] << 24)
2038 | (mask_p
[57] << 22) | (mask_p
[56] << 20)
2039 | (mask_p
[55] << 18) | (mask_p
[54] << 16)
2040 | (mask_p
[53] << 14) | (mask_p
[52] << 12)
2041 | (mask_p
[51] << 10) | (mask_p
[50] << 8)
2042 | (mask_p
[49] << 6) | (mask_p
[48] << 4)
2043 | (mask_p
[47] << 2) | (mask_p
[46] << 0);
2044 REG_WRITE(ah
, AR_PHY_BIN_MASK2_4
, tmp_mask
);
2045 REG_WRITE(ah
, AR_PHY_MASK2_P_61_45
, tmp_mask
);
2048 static void ath9k_hw_spur_mitigate(struct ath_hw
*ah
, struct ath9k_channel
*chan
)
2050 int bb_spur
= AR_NO_SPUR
;
2053 int spur_delta_phase
;
2055 int upper
, lower
, cur_vit_mask
;
2058 int pilot_mask_reg
[4] = { AR_PHY_TIMING7
, AR_PHY_TIMING8
,
2059 AR_PHY_PILOT_MASK_01_30
, AR_PHY_PILOT_MASK_31_60
2061 int chan_mask_reg
[4] = { AR_PHY_TIMING9
, AR_PHY_TIMING10
,
2062 AR_PHY_CHANNEL_MASK_01_30
, AR_PHY_CHANNEL_MASK_31_60
2064 int inc
[4] = { 0, 100, 0, 0 };
2071 bool is2GHz
= IS_CHAN_2GHZ(chan
);
2073 memset(&mask_m
, 0, sizeof(int8_t) * 123);
2074 memset(&mask_p
, 0, sizeof(int8_t) * 123);
2076 for (i
= 0; i
< AR_EEPROM_MODAL_SPURS
; i
++) {
2077 cur_bb_spur
= ah
->eep_ops
->get_spur_channel(ah
, i
, is2GHz
);
2078 if (AR_NO_SPUR
== cur_bb_spur
)
2080 cur_bb_spur
= cur_bb_spur
- (chan
->channel
* 10);
2081 if ((cur_bb_spur
> -95) && (cur_bb_spur
< 95)) {
2082 bb_spur
= cur_bb_spur
;
2087 if (AR_NO_SPUR
== bb_spur
)
2092 tmp
= REG_READ(ah
, AR_PHY_TIMING_CTRL4(0));
2093 new = tmp
| (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI
|
2094 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER
|
2095 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK
|
2096 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK
);
2098 REG_WRITE(ah
, AR_PHY_TIMING_CTRL4(0), new);
2100 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL
|
2101 AR_PHY_SPUR_REG_ENABLE_MASK_PPM
|
2102 AR_PHY_SPUR_REG_MASK_RATE_SELECT
|
2103 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI
|
2104 SM(SPUR_RSSI_THRESH
, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH
));
2105 REG_WRITE(ah
, AR_PHY_SPUR_REG
, new);
2107 spur_delta_phase
= ((bb_spur
* 524288) / 100) &
2108 AR_PHY_TIMING11_SPUR_DELTA_PHASE
;
2110 denominator
= IS_CHAN_2GHZ(chan
) ? 440 : 400;
2111 spur_freq_sd
= ((bb_spur
* 2048) / denominator
) & 0x3ff;
2113 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC
|
2114 SM(spur_freq_sd
, AR_PHY_TIMING11_SPUR_FREQ_SD
) |
2115 SM(spur_delta_phase
, AR_PHY_TIMING11_SPUR_DELTA_PHASE
));
2116 REG_WRITE(ah
, AR_PHY_TIMING11
, new);
2122 for (i
= 0; i
< 4; i
++) {
2126 for (bp
= 0; bp
< 30; bp
++) {
2127 if ((cur_bin
> lower
) && (cur_bin
< upper
)) {
2128 pilot_mask
= pilot_mask
| 0x1 << bp
;
2129 chan_mask
= chan_mask
| 0x1 << bp
;
2134 REG_WRITE(ah
, pilot_mask_reg
[i
], pilot_mask
);
2135 REG_WRITE(ah
, chan_mask_reg
[i
], chan_mask
);
2138 cur_vit_mask
= 6100;
2142 for (i
= 0; i
< 123; i
++) {
2143 if ((cur_vit_mask
> lower
) && (cur_vit_mask
< upper
)) {
2145 /* workaround for gcc bug #37014 */
2146 volatile int tmp_v
= abs(cur_vit_mask
- bin
);
2152 if (cur_vit_mask
< 0)
2153 mask_m
[abs(cur_vit_mask
/ 100)] = mask_amt
;
2155 mask_p
[cur_vit_mask
/ 100] = mask_amt
;
2157 cur_vit_mask
-= 100;
2160 tmp_mask
= (mask_m
[46] << 30) | (mask_m
[47] << 28)
2161 | (mask_m
[48] << 26) | (mask_m
[49] << 24)
2162 | (mask_m
[50] << 22) | (mask_m
[51] << 20)
2163 | (mask_m
[52] << 18) | (mask_m
[53] << 16)
2164 | (mask_m
[54] << 14) | (mask_m
[55] << 12)
2165 | (mask_m
[56] << 10) | (mask_m
[57] << 8)
2166 | (mask_m
[58] << 6) | (mask_m
[59] << 4)
2167 | (mask_m
[60] << 2) | (mask_m
[61] << 0);
2168 REG_WRITE(ah
, AR_PHY_BIN_MASK_1
, tmp_mask
);
2169 REG_WRITE(ah
, AR_PHY_VIT_MASK2_M_46_61
, tmp_mask
);
2171 tmp_mask
= (mask_m
[31] << 28)
2172 | (mask_m
[32] << 26) | (mask_m
[33] << 24)
2173 | (mask_m
[34] << 22) | (mask_m
[35] << 20)
2174 | (mask_m
[36] << 18) | (mask_m
[37] << 16)
2175 | (mask_m
[48] << 14) | (mask_m
[39] << 12)
2176 | (mask_m
[40] << 10) | (mask_m
[41] << 8)
2177 | (mask_m
[42] << 6) | (mask_m
[43] << 4)
2178 | (mask_m
[44] << 2) | (mask_m
[45] << 0);
2179 REG_WRITE(ah
, AR_PHY_BIN_MASK_2
, tmp_mask
);
2180 REG_WRITE(ah
, AR_PHY_MASK2_M_31_45
, tmp_mask
);
2182 tmp_mask
= (mask_m
[16] << 30) | (mask_m
[16] << 28)
2183 | (mask_m
[18] << 26) | (mask_m
[18] << 24)
2184 | (mask_m
[20] << 22) | (mask_m
[20] << 20)
2185 | (mask_m
[22] << 18) | (mask_m
[22] << 16)
2186 | (mask_m
[24] << 14) | (mask_m
[24] << 12)
2187 | (mask_m
[25] << 10) | (mask_m
[26] << 8)
2188 | (mask_m
[27] << 6) | (mask_m
[28] << 4)
2189 | (mask_m
[29] << 2) | (mask_m
[30] << 0);
2190 REG_WRITE(ah
, AR_PHY_BIN_MASK_3
, tmp_mask
);
2191 REG_WRITE(ah
, AR_PHY_MASK2_M_16_30
, tmp_mask
);
2193 tmp_mask
= (mask_m
[0] << 30) | (mask_m
[1] << 28)
2194 | (mask_m
[2] << 26) | (mask_m
[3] << 24)
2195 | (mask_m
[4] << 22) | (mask_m
[5] << 20)
2196 | (mask_m
[6] << 18) | (mask_m
[7] << 16)
2197 | (mask_m
[8] << 14) | (mask_m
[9] << 12)
2198 | (mask_m
[10] << 10) | (mask_m
[11] << 8)
2199 | (mask_m
[12] << 6) | (mask_m
[13] << 4)
2200 | (mask_m
[14] << 2) | (mask_m
[15] << 0);
2201 REG_WRITE(ah
, AR_PHY_MASK_CTL
, tmp_mask
);
2202 REG_WRITE(ah
, AR_PHY_MASK2_M_00_15
, tmp_mask
);
2204 tmp_mask
= (mask_p
[15] << 28)
2205 | (mask_p
[14] << 26) | (mask_p
[13] << 24)
2206 | (mask_p
[12] << 22) | (mask_p
[11] << 20)
2207 | (mask_p
[10] << 18) | (mask_p
[9] << 16)
2208 | (mask_p
[8] << 14) | (mask_p
[7] << 12)
2209 | (mask_p
[6] << 10) | (mask_p
[5] << 8)
2210 | (mask_p
[4] << 6) | (mask_p
[3] << 4)
2211 | (mask_p
[2] << 2) | (mask_p
[1] << 0);
2212 REG_WRITE(ah
, AR_PHY_BIN_MASK2_1
, tmp_mask
);
2213 REG_WRITE(ah
, AR_PHY_MASK2_P_15_01
, tmp_mask
);
2215 tmp_mask
= (mask_p
[30] << 28)
2216 | (mask_p
[29] << 26) | (mask_p
[28] << 24)
2217 | (mask_p
[27] << 22) | (mask_p
[26] << 20)
2218 | (mask_p
[25] << 18) | (mask_p
[24] << 16)
2219 | (mask_p
[23] << 14) | (mask_p
[22] << 12)
2220 | (mask_p
[21] << 10) | (mask_p
[20] << 8)
2221 | (mask_p
[19] << 6) | (mask_p
[18] << 4)
2222 | (mask_p
[17] << 2) | (mask_p
[16] << 0);
2223 REG_WRITE(ah
, AR_PHY_BIN_MASK2_2
, tmp_mask
);
2224 REG_WRITE(ah
, AR_PHY_MASK2_P_30_16
, tmp_mask
);
2226 tmp_mask
= (mask_p
[45] << 28)
2227 | (mask_p
[44] << 26) | (mask_p
[43] << 24)
2228 | (mask_p
[42] << 22) | (mask_p
[41] << 20)
2229 | (mask_p
[40] << 18) | (mask_p
[39] << 16)
2230 | (mask_p
[38] << 14) | (mask_p
[37] << 12)
2231 | (mask_p
[36] << 10) | (mask_p
[35] << 8)
2232 | (mask_p
[34] << 6) | (mask_p
[33] << 4)
2233 | (mask_p
[32] << 2) | (mask_p
[31] << 0);
2234 REG_WRITE(ah
, AR_PHY_BIN_MASK2_3
, tmp_mask
);
2235 REG_WRITE(ah
, AR_PHY_MASK2_P_45_31
, tmp_mask
);
2237 tmp_mask
= (mask_p
[61] << 30) | (mask_p
[60] << 28)
2238 | (mask_p
[59] << 26) | (mask_p
[58] << 24)
2239 | (mask_p
[57] << 22) | (mask_p
[56] << 20)
2240 | (mask_p
[55] << 18) | (mask_p
[54] << 16)
2241 | (mask_p
[53] << 14) | (mask_p
[52] << 12)
2242 | (mask_p
[51] << 10) | (mask_p
[50] << 8)
2243 | (mask_p
[49] << 6) | (mask_p
[48] << 4)
2244 | (mask_p
[47] << 2) | (mask_p
[46] << 0);
2245 REG_WRITE(ah
, AR_PHY_BIN_MASK2_4
, tmp_mask
);
2246 REG_WRITE(ah
, AR_PHY_MASK2_P_61_45
, tmp_mask
);
2249 static void ath9k_enable_rfkill(struct ath_hw
*ah
)
2251 REG_SET_BIT(ah
, AR_GPIO_INPUT_EN_VAL
,
2252 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB
);
2254 REG_CLR_BIT(ah
, AR_GPIO_INPUT_MUX2
,
2255 AR_GPIO_INPUT_MUX2_RFSILENT
);
2257 ath9k_hw_cfg_gpio_input(ah
, ah
->rfkill_gpio
);
2258 REG_SET_BIT(ah
, AR_PHY_TEST
, RFSILENT_BB
);
2261 int ath9k_hw_reset(struct ath_hw
*ah
, struct ath9k_channel
*chan
,
2262 bool bChannelChange
)
2265 struct ath_softc
*sc
= ah
->ah_sc
;
2266 struct ath9k_channel
*curchan
= ah
->curchan
;
2269 int i
, rx_chainmask
, r
;
2271 ah
->extprotspacing
= sc
->ht_extprotspacing
;
2272 ah
->txchainmask
= sc
->tx_chainmask
;
2273 ah
->rxchainmask
= sc
->rx_chainmask
;
2275 if (!ath9k_hw_setpower(ah
, ATH9K_PM_AWAKE
))
2279 ath9k_hw_getnf(ah
, curchan
);
2281 if (bChannelChange
&&
2282 (ah
->chip_fullsleep
!= true) &&
2283 (ah
->curchan
!= NULL
) &&
2284 (chan
->channel
!= ah
->curchan
->channel
) &&
2285 ((chan
->channelFlags
& CHANNEL_ALL
) ==
2286 (ah
->curchan
->channelFlags
& CHANNEL_ALL
)) &&
2287 (!AR_SREV_9280(ah
) || (!IS_CHAN_A_5MHZ_SPACED(chan
) &&
2288 !IS_CHAN_A_5MHZ_SPACED(ah
->curchan
)))) {
2290 if (ath9k_hw_channel_change(ah
, chan
, sc
->tx_chan_width
)) {
2291 ath9k_hw_loadnf(ah
, ah
->curchan
);
2292 ath9k_hw_start_nfcal(ah
);
2297 saveDefAntenna
= REG_READ(ah
, AR_DEF_ANTENNA
);
2298 if (saveDefAntenna
== 0)
2301 macStaId1
= REG_READ(ah
, AR_STA_ID1
) & AR_STA_ID1_BASE_RATE_11B
;
2303 saveLedState
= REG_READ(ah
, AR_CFG_LED
) &
2304 (AR_CFG_LED_ASSOC_CTL
| AR_CFG_LED_MODE_SEL
|
2305 AR_CFG_LED_BLINK_THRESH_SEL
| AR_CFG_LED_BLINK_SLOW
);
2307 ath9k_hw_mark_phy_inactive(ah
);
2309 if (!ath9k_hw_chip_reset(ah
, chan
)) {
2310 DPRINTF(ah
->ah_sc
, ATH_DBG_FATAL
, "Chip reset failed\n");
2314 if (AR_SREV_9280_10_OR_LATER(ah
))
2315 REG_SET_BIT(ah
, AR_GPIO_INPUT_EN_VAL
, AR_GPIO_JTAG_DISABLE
);
2317 if (AR_SREV_9287_10_OR_LATER(ah
)) {
2318 /* Enable ASYNC FIFO */
2319 REG_SET_BIT(ah
, AR_MAC_PCU_ASYNC_FIFO_REG3
,
2320 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL
);
2321 REG_SET_BIT(ah
, AR_PHY_MODE
, AR_PHY_MODE_ASYNCFIFO
);
2322 REG_CLR_BIT(ah
, AR_MAC_PCU_ASYNC_FIFO_REG3
,
2323 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET
);
2324 REG_SET_BIT(ah
, AR_MAC_PCU_ASYNC_FIFO_REG3
,
2325 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET
);
2327 r
= ath9k_hw_process_ini(ah
, chan
, sc
->tx_chan_width
);
2331 /* Setup MFP options for CCMP */
2332 if (AR_SREV_9280_20_OR_LATER(ah
)) {
2333 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
2334 * frames when constructing CCMP AAD. */
2335 REG_RMW_FIELD(ah
, AR_AES_MUTE_MASK1
, AR_AES_MUTE_MASK1_FC_MGMT
,
2337 ah
->sw_mgmt_crypto
= false;
2338 } else if (AR_SREV_9160_10_OR_LATER(ah
)) {
2339 /* Disable hardware crypto for management frames */
2340 REG_CLR_BIT(ah
, AR_PCU_MISC_MODE2
,
2341 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE
);
2342 REG_SET_BIT(ah
, AR_PCU_MISC_MODE2
,
2343 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT
);
2344 ah
->sw_mgmt_crypto
= true;
2346 ah
->sw_mgmt_crypto
= true;
2348 if (IS_CHAN_OFDM(chan
) || IS_CHAN_HT(chan
))
2349 ath9k_hw_set_delta_slope(ah
, chan
);
2351 if (AR_SREV_9280_10_OR_LATER(ah
))
2352 ath9k_hw_9280_spur_mitigate(ah
, chan
);
2354 ath9k_hw_spur_mitigate(ah
, chan
);
2356 ah
->eep_ops
->set_board_values(ah
, chan
);
2358 ath9k_hw_decrease_chain_power(ah
, chan
);
2360 REG_WRITE(ah
, AR_STA_ID0
, get_unaligned_le32(ah
->macaddr
));
2361 REG_WRITE(ah
, AR_STA_ID1
, get_unaligned_le16(ah
->macaddr
+ 4)
2363 | AR_STA_ID1_RTS_USE_DEF
2365 ack_6mb
? AR_STA_ID1_ACKCTS_6MB
: 0)
2366 | ah
->sta_id1_defaults
);
2367 ath9k_hw_set_operating_mode(ah
, ah
->opmode
);
2369 REG_WRITE(ah
, AR_BSSMSKL
, get_unaligned_le32(sc
->bssidmask
));
2370 REG_WRITE(ah
, AR_BSSMSKU
, get_unaligned_le16(sc
->bssidmask
+ 4));
2372 REG_WRITE(ah
, AR_DEF_ANTENNA
, saveDefAntenna
);
2374 REG_WRITE(ah
, AR_BSS_ID0
, get_unaligned_le32(sc
->curbssid
));
2375 REG_WRITE(ah
, AR_BSS_ID1
, get_unaligned_le16(sc
->curbssid
+ 4) |
2376 ((sc
->curaid
& 0x3fff) << AR_BSS_ID1_AID_S
));
2378 REG_WRITE(ah
, AR_ISR
, ~0);
2380 REG_WRITE(ah
, AR_RSSI_THR
, INIT_RSSI_THR
);
2382 if (AR_SREV_9280_10_OR_LATER(ah
))
2383 ath9k_hw_ar9280_set_channel(ah
, chan
);
2385 if (!(ath9k_hw_set_channel(ah
, chan
)))
2388 for (i
= 0; i
< AR_NUM_DCU
; i
++)
2389 REG_WRITE(ah
, AR_DQCUMASK(i
), 1 << i
);
2392 for (i
= 0; i
< ah
->caps
.total_queues
; i
++)
2393 ath9k_hw_resettxqueue(ah
, i
);
2395 ath9k_hw_init_interrupt_masks(ah
, ah
->opmode
);
2396 ath9k_hw_init_qos(ah
);
2398 if (ah
->caps
.hw_caps
& ATH9K_HW_CAP_RFSILENT
)
2399 ath9k_enable_rfkill(ah
);
2401 ath9k_hw_init_user_settings(ah
);
2403 if (AR_SREV_9287_10_OR_LATER(ah
)) {
2404 REG_WRITE(ah
, AR_D_GBL_IFS_SIFS
,
2405 AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR
);
2406 REG_WRITE(ah
, AR_D_GBL_IFS_SLOT
,
2407 AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR
);
2408 REG_WRITE(ah
, AR_D_GBL_IFS_EIFS
,
2409 AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR
);
2411 REG_WRITE(ah
, AR_TIME_OUT
, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR
);
2412 REG_WRITE(ah
, AR_USEC
, AR_USEC_ASYNC_FIFO_DUR
);
2414 REG_SET_BIT(ah
, AR_MAC_PCU_LOGIC_ANALYZER
,
2415 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768
);
2416 REG_RMW_FIELD(ah
, AR_AHB_MODE
, AR_AHB_CUSTOM_BURST_EN
,
2417 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL
);
2419 if (AR_SREV_9287_10_OR_LATER(ah
)) {
2420 REG_SET_BIT(ah
, AR_PCU_MISC_MODE2
,
2421 AR_PCU_MISC_MODE2_ENABLE_AGGWEP
);
2424 REG_WRITE(ah
, AR_STA_ID1
,
2425 REG_READ(ah
, AR_STA_ID1
) | AR_STA_ID1_PRESERVE_SEQNUM
);
2427 ath9k_hw_set_dma(ah
);
2429 REG_WRITE(ah
, AR_OBS
, 8);
2431 if (ah
->config
.intr_mitigation
) {
2432 REG_RMW_FIELD(ah
, AR_RIMT
, AR_RIMT_LAST
, 500);
2433 REG_RMW_FIELD(ah
, AR_RIMT
, AR_RIMT_FIRST
, 2000);
2436 ath9k_hw_init_bb(ah
, chan
);
2438 if (!ath9k_hw_init_cal(ah
, chan
))
2441 rx_chainmask
= ah
->rxchainmask
;
2442 if ((rx_chainmask
== 0x5) || (rx_chainmask
== 0x3)) {
2443 REG_WRITE(ah
, AR_PHY_RX_CHAINMASK
, rx_chainmask
);
2444 REG_WRITE(ah
, AR_PHY_CAL_CHAINMASK
, rx_chainmask
);
2447 REG_WRITE(ah
, AR_CFG_LED
, saveLedState
| AR_CFG_SCLK_32KHZ
);
2449 if (AR_SREV_9100(ah
)) {
2451 mask
= REG_READ(ah
, AR_CFG
);
2452 if (mask
& (AR_CFG_SWRB
| AR_CFG_SWTB
| AR_CFG_SWRG
)) {
2453 DPRINTF(ah
->ah_sc
, ATH_DBG_RESET
,
2454 "CFG Byte Swap Set 0x%x\n", mask
);
2457 INIT_CONFIG_STATUS
| AR_CFG_SWRB
| AR_CFG_SWTB
;
2458 REG_WRITE(ah
, AR_CFG
, mask
);
2459 DPRINTF(ah
->ah_sc
, ATH_DBG_RESET
,
2460 "Setting CFG 0x%x\n", REG_READ(ah
, AR_CFG
));
2464 REG_WRITE(ah
, AR_CFG
, AR_CFG_SWTD
| AR_CFG_SWRD
);
2471 /************************/
2472 /* Key Cache Management */
2473 /************************/
2475 bool ath9k_hw_keyreset(struct ath_hw
*ah
, u16 entry
)
2479 if (entry
>= ah
->caps
.keycache_size
) {
2480 DPRINTF(ah
->ah_sc
, ATH_DBG_FATAL
,
2481 "keychache entry %u out of range\n", entry
);
2485 keyType
= REG_READ(ah
, AR_KEYTABLE_TYPE(entry
));
2487 REG_WRITE(ah
, AR_KEYTABLE_KEY0(entry
), 0);
2488 REG_WRITE(ah
, AR_KEYTABLE_KEY1(entry
), 0);
2489 REG_WRITE(ah
, AR_KEYTABLE_KEY2(entry
), 0);
2490 REG_WRITE(ah
, AR_KEYTABLE_KEY3(entry
), 0);
2491 REG_WRITE(ah
, AR_KEYTABLE_KEY4(entry
), 0);
2492 REG_WRITE(ah
, AR_KEYTABLE_TYPE(entry
), AR_KEYTABLE_TYPE_CLR
);
2493 REG_WRITE(ah
, AR_KEYTABLE_MAC0(entry
), 0);
2494 REG_WRITE(ah
, AR_KEYTABLE_MAC1(entry
), 0);
2496 if (keyType
== AR_KEYTABLE_TYPE_TKIP
&& ATH9K_IS_MIC_ENABLED(ah
)) {
2497 u16 micentry
= entry
+ 64;
2499 REG_WRITE(ah
, AR_KEYTABLE_KEY0(micentry
), 0);
2500 REG_WRITE(ah
, AR_KEYTABLE_KEY1(micentry
), 0);
2501 REG_WRITE(ah
, AR_KEYTABLE_KEY2(micentry
), 0);
2502 REG_WRITE(ah
, AR_KEYTABLE_KEY3(micentry
), 0);
2506 if (ah
->curchan
== NULL
)
2512 bool ath9k_hw_keysetmac(struct ath_hw
*ah
, u16 entry
, const u8
*mac
)
2516 if (entry
>= ah
->caps
.keycache_size
) {
2517 DPRINTF(ah
->ah_sc
, ATH_DBG_FATAL
,
2518 "keychache entry %u out of range\n", entry
);
2523 macHi
= (mac
[5] << 8) | mac
[4];
2524 macLo
= (mac
[3] << 24) |
2529 macLo
|= (macHi
& 1) << 31;
2534 REG_WRITE(ah
, AR_KEYTABLE_MAC0(entry
), macLo
);
2535 REG_WRITE(ah
, AR_KEYTABLE_MAC1(entry
), macHi
| AR_KEYTABLE_VALID
);
2540 bool ath9k_hw_set_keycache_entry(struct ath_hw
*ah
, u16 entry
,
2541 const struct ath9k_keyval
*k
,
2544 const struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
2545 u32 key0
, key1
, key2
, key3
, key4
;
2548 if (entry
>= pCap
->keycache_size
) {
2549 DPRINTF(ah
->ah_sc
, ATH_DBG_FATAL
,
2550 "keycache entry %u out of range\n", entry
);
2554 switch (k
->kv_type
) {
2555 case ATH9K_CIPHER_AES_OCB
:
2556 keyType
= AR_KEYTABLE_TYPE_AES
;
2558 case ATH9K_CIPHER_AES_CCM
:
2559 if (!(pCap
->hw_caps
& ATH9K_HW_CAP_CIPHER_AESCCM
)) {
2560 DPRINTF(ah
->ah_sc
, ATH_DBG_ANY
,
2561 "AES-CCM not supported by mac rev 0x%x\n",
2562 ah
->hw_version
.macRev
);
2565 keyType
= AR_KEYTABLE_TYPE_CCM
;
2567 case ATH9K_CIPHER_TKIP
:
2568 keyType
= AR_KEYTABLE_TYPE_TKIP
;
2569 if (ATH9K_IS_MIC_ENABLED(ah
)
2570 && entry
+ 64 >= pCap
->keycache_size
) {
2571 DPRINTF(ah
->ah_sc
, ATH_DBG_ANY
,
2572 "entry %u inappropriate for TKIP\n", entry
);
2576 case ATH9K_CIPHER_WEP
:
2577 if (k
->kv_len
< WLAN_KEY_LEN_WEP40
) {
2578 DPRINTF(ah
->ah_sc
, ATH_DBG_ANY
,
2579 "WEP key length %u too small\n", k
->kv_len
);
2582 if (k
->kv_len
<= WLAN_KEY_LEN_WEP40
)
2583 keyType
= AR_KEYTABLE_TYPE_40
;
2584 else if (k
->kv_len
<= WLAN_KEY_LEN_WEP104
)
2585 keyType
= AR_KEYTABLE_TYPE_104
;
2587 keyType
= AR_KEYTABLE_TYPE_128
;
2589 case ATH9K_CIPHER_CLR
:
2590 keyType
= AR_KEYTABLE_TYPE_CLR
;
2593 DPRINTF(ah
->ah_sc
, ATH_DBG_FATAL
,
2594 "cipher %u not supported\n", k
->kv_type
);
2598 key0
= get_unaligned_le32(k
->kv_val
+ 0);
2599 key1
= get_unaligned_le16(k
->kv_val
+ 4);
2600 key2
= get_unaligned_le32(k
->kv_val
+ 6);
2601 key3
= get_unaligned_le16(k
->kv_val
+ 10);
2602 key4
= get_unaligned_le32(k
->kv_val
+ 12);
2603 if (k
->kv_len
<= WLAN_KEY_LEN_WEP104
)
2607 * Note: Key cache registers access special memory area that requires
2608 * two 32-bit writes to actually update the values in the internal
2609 * memory. Consequently, the exact order and pairs used here must be
2613 if (keyType
== AR_KEYTABLE_TYPE_TKIP
&& ATH9K_IS_MIC_ENABLED(ah
)) {
2614 u16 micentry
= entry
+ 64;
2617 * Write inverted key[47:0] first to avoid Michael MIC errors
2618 * on frames that could be sent or received at the same time.
2619 * The correct key will be written in the end once everything
2622 REG_WRITE(ah
, AR_KEYTABLE_KEY0(entry
), ~key0
);
2623 REG_WRITE(ah
, AR_KEYTABLE_KEY1(entry
), ~key1
);
2625 /* Write key[95:48] */
2626 REG_WRITE(ah
, AR_KEYTABLE_KEY2(entry
), key2
);
2627 REG_WRITE(ah
, AR_KEYTABLE_KEY3(entry
), key3
);
2629 /* Write key[127:96] and key type */
2630 REG_WRITE(ah
, AR_KEYTABLE_KEY4(entry
), key4
);
2631 REG_WRITE(ah
, AR_KEYTABLE_TYPE(entry
), keyType
);
2633 /* Write MAC address for the entry */
2634 (void) ath9k_hw_keysetmac(ah
, entry
, mac
);
2636 if (ah
->misc_mode
& AR_PCU_MIC_NEW_LOC_ENA
) {
2638 * TKIP uses two key cache entries:
2639 * Michael MIC TX/RX keys in the same key cache entry
2640 * (idx = main index + 64):
2641 * key0 [31:0] = RX key [31:0]
2642 * key1 [15:0] = TX key [31:16]
2643 * key1 [31:16] = reserved
2644 * key2 [31:0] = RX key [63:32]
2645 * key3 [15:0] = TX key [15:0]
2646 * key3 [31:16] = reserved
2647 * key4 [31:0] = TX key [63:32]
2649 u32 mic0
, mic1
, mic2
, mic3
, mic4
;
2651 mic0
= get_unaligned_le32(k
->kv_mic
+ 0);
2652 mic2
= get_unaligned_le32(k
->kv_mic
+ 4);
2653 mic1
= get_unaligned_le16(k
->kv_txmic
+ 2) & 0xffff;
2654 mic3
= get_unaligned_le16(k
->kv_txmic
+ 0) & 0xffff;
2655 mic4
= get_unaligned_le32(k
->kv_txmic
+ 4);
2657 /* Write RX[31:0] and TX[31:16] */
2658 REG_WRITE(ah
, AR_KEYTABLE_KEY0(micentry
), mic0
);
2659 REG_WRITE(ah
, AR_KEYTABLE_KEY1(micentry
), mic1
);
2661 /* Write RX[63:32] and TX[15:0] */
2662 REG_WRITE(ah
, AR_KEYTABLE_KEY2(micentry
), mic2
);
2663 REG_WRITE(ah
, AR_KEYTABLE_KEY3(micentry
), mic3
);
2665 /* Write TX[63:32] and keyType(reserved) */
2666 REG_WRITE(ah
, AR_KEYTABLE_KEY4(micentry
), mic4
);
2667 REG_WRITE(ah
, AR_KEYTABLE_TYPE(micentry
),
2668 AR_KEYTABLE_TYPE_CLR
);
2672 * TKIP uses four key cache entries (two for group
2674 * Michael MIC TX/RX keys are in different key cache
2675 * entries (idx = main index + 64 for TX and
2676 * main index + 32 + 96 for RX):
2677 * key0 [31:0] = TX/RX MIC key [31:0]
2678 * key1 [31:0] = reserved
2679 * key2 [31:0] = TX/RX MIC key [63:32]
2680 * key3 [31:0] = reserved
2681 * key4 [31:0] = reserved
2683 * Upper layer code will call this function separately
2684 * for TX and RX keys when these registers offsets are
2689 mic0
= get_unaligned_le32(k
->kv_mic
+ 0);
2690 mic2
= get_unaligned_le32(k
->kv_mic
+ 4);
2692 /* Write MIC key[31:0] */
2693 REG_WRITE(ah
, AR_KEYTABLE_KEY0(micentry
), mic0
);
2694 REG_WRITE(ah
, AR_KEYTABLE_KEY1(micentry
), 0);
2696 /* Write MIC key[63:32] */
2697 REG_WRITE(ah
, AR_KEYTABLE_KEY2(micentry
), mic2
);
2698 REG_WRITE(ah
, AR_KEYTABLE_KEY3(micentry
), 0);
2700 /* Write TX[63:32] and keyType(reserved) */
2701 REG_WRITE(ah
, AR_KEYTABLE_KEY4(micentry
), 0);
2702 REG_WRITE(ah
, AR_KEYTABLE_TYPE(micentry
),
2703 AR_KEYTABLE_TYPE_CLR
);
2706 /* MAC address registers are reserved for the MIC entry */
2707 REG_WRITE(ah
, AR_KEYTABLE_MAC0(micentry
), 0);
2708 REG_WRITE(ah
, AR_KEYTABLE_MAC1(micentry
), 0);
2711 * Write the correct (un-inverted) key[47:0] last to enable
2712 * TKIP now that all other registers are set with correct
2715 REG_WRITE(ah
, AR_KEYTABLE_KEY0(entry
), key0
);
2716 REG_WRITE(ah
, AR_KEYTABLE_KEY1(entry
), key1
);
2718 /* Write key[47:0] */
2719 REG_WRITE(ah
, AR_KEYTABLE_KEY0(entry
), key0
);
2720 REG_WRITE(ah
, AR_KEYTABLE_KEY1(entry
), key1
);
2722 /* Write key[95:48] */
2723 REG_WRITE(ah
, AR_KEYTABLE_KEY2(entry
), key2
);
2724 REG_WRITE(ah
, AR_KEYTABLE_KEY3(entry
), key3
);
2726 /* Write key[127:96] and key type */
2727 REG_WRITE(ah
, AR_KEYTABLE_KEY4(entry
), key4
);
2728 REG_WRITE(ah
, AR_KEYTABLE_TYPE(entry
), keyType
);
2730 /* Write MAC address for the entry */
2731 (void) ath9k_hw_keysetmac(ah
, entry
, mac
);
2737 bool ath9k_hw_keyisvalid(struct ath_hw
*ah
, u16 entry
)
2739 if (entry
< ah
->caps
.keycache_size
) {
2740 u32 val
= REG_READ(ah
, AR_KEYTABLE_MAC1(entry
));
2741 if (val
& AR_KEYTABLE_VALID
)
2747 /******************************/
2748 /* Power Management (Chipset) */
2749 /******************************/
2751 static void ath9k_set_power_sleep(struct ath_hw
*ah
, int setChip
)
2753 REG_SET_BIT(ah
, AR_STA_ID1
, AR_STA_ID1_PWR_SAV
);
2755 REG_CLR_BIT(ah
, AR_RTC_FORCE_WAKE
,
2756 AR_RTC_FORCE_WAKE_EN
);
2757 if (!AR_SREV_9100(ah
))
2758 REG_WRITE(ah
, AR_RC
, AR_RC_AHB
| AR_RC_HOSTIF
);
2760 REG_CLR_BIT(ah
, (AR_RTC_RESET
),
2765 static void ath9k_set_power_network_sleep(struct ath_hw
*ah
, int setChip
)
2767 REG_SET_BIT(ah
, AR_STA_ID1
, AR_STA_ID1_PWR_SAV
);
2769 struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
2771 if (!(pCap
->hw_caps
& ATH9K_HW_CAP_AUTOSLEEP
)) {
2772 REG_WRITE(ah
, AR_RTC_FORCE_WAKE
,
2773 AR_RTC_FORCE_WAKE_ON_INT
);
2775 REG_CLR_BIT(ah
, AR_RTC_FORCE_WAKE
,
2776 AR_RTC_FORCE_WAKE_EN
);
2781 static bool ath9k_hw_set_power_awake(struct ath_hw
*ah
, int setChip
)
2787 if ((REG_READ(ah
, AR_RTC_STATUS
) &
2788 AR_RTC_STATUS_M
) == AR_RTC_STATUS_SHUTDOWN
) {
2789 if (ath9k_hw_set_reset_reg(ah
,
2790 ATH9K_RESET_POWER_ON
) != true) {
2794 if (AR_SREV_9100(ah
))
2795 REG_SET_BIT(ah
, AR_RTC_RESET
,
2798 REG_SET_BIT(ah
, AR_RTC_FORCE_WAKE
,
2799 AR_RTC_FORCE_WAKE_EN
);
2802 for (i
= POWER_UP_TIME
/ 50; i
> 0; i
--) {
2803 val
= REG_READ(ah
, AR_RTC_STATUS
) & AR_RTC_STATUS_M
;
2804 if (val
== AR_RTC_STATUS_ON
)
2807 REG_SET_BIT(ah
, AR_RTC_FORCE_WAKE
,
2808 AR_RTC_FORCE_WAKE_EN
);
2811 DPRINTF(ah
->ah_sc
, ATH_DBG_FATAL
,
2812 "Failed to wakeup in %uus\n", POWER_UP_TIME
/ 20);
2817 REG_CLR_BIT(ah
, AR_STA_ID1
, AR_STA_ID1_PWR_SAV
);
2822 static bool ath9k_hw_setpower_nolock(struct ath_hw
*ah
,
2823 enum ath9k_power_mode mode
)
2825 int status
= true, setChip
= true;
2826 static const char *modes
[] = {
2833 if (ah
->power_mode
== mode
)
2836 DPRINTF(ah
->ah_sc
, ATH_DBG_RESET
, "%s -> %s\n",
2837 modes
[ah
->power_mode
], modes
[mode
]);
2840 case ATH9K_PM_AWAKE
:
2841 status
= ath9k_hw_set_power_awake(ah
, setChip
);
2843 case ATH9K_PM_FULL_SLEEP
:
2844 ath9k_set_power_sleep(ah
, setChip
);
2845 ah
->chip_fullsleep
= true;
2847 case ATH9K_PM_NETWORK_SLEEP
:
2848 ath9k_set_power_network_sleep(ah
, setChip
);
2851 DPRINTF(ah
->ah_sc
, ATH_DBG_FATAL
,
2852 "Unknown power mode %u\n", mode
);
2855 ah
->power_mode
= mode
;
2860 bool ath9k_hw_setpower(struct ath_hw
*ah
, enum ath9k_power_mode mode
)
2862 unsigned long flags
;
2865 spin_lock_irqsave(&ah
->ah_sc
->sc_pm_lock
, flags
);
2866 ret
= ath9k_hw_setpower_nolock(ah
, mode
);
2867 spin_unlock_irqrestore(&ah
->ah_sc
->sc_pm_lock
, flags
);
2872 void ath9k_ps_wakeup(struct ath_softc
*sc
)
2874 unsigned long flags
;
2876 spin_lock_irqsave(&sc
->sc_pm_lock
, flags
);
2877 if (++sc
->ps_usecount
!= 1)
2880 ath9k_hw_setpower_nolock(sc
->sc_ah
, ATH9K_PM_AWAKE
);
2883 spin_unlock_irqrestore(&sc
->sc_pm_lock
, flags
);
2886 void ath9k_ps_restore(struct ath_softc
*sc
)
2888 unsigned long flags
;
2890 spin_lock_irqsave(&sc
->sc_pm_lock
, flags
);
2891 if (--sc
->ps_usecount
!= 0)
2894 if (sc
->ps_enabled
&&
2895 !(sc
->sc_flags
& (SC_OP_WAIT_FOR_BEACON
|
2896 SC_OP_WAIT_FOR_CAB
|
2897 SC_OP_WAIT_FOR_PSPOLL_DATA
|
2898 SC_OP_WAIT_FOR_TX_ACK
)))
2899 ath9k_hw_setpower_nolock(sc
->sc_ah
, ATH9K_PM_NETWORK_SLEEP
);
2902 spin_unlock_irqrestore(&sc
->sc_pm_lock
, flags
);
2906 * Helper for ASPM support.
2908 * Disable PLL when in L0s as well as receiver clock when in L1.
2909 * This power saving option must be enabled through the SerDes.
2911 * Programming the SerDes must go through the same 288 bit serial shift
2912 * register as the other analog registers. Hence the 9 writes.
2914 void ath9k_hw_configpcipowersave(struct ath_hw
*ah
, int restore
)
2918 if (ah
->is_pciexpress
!= true)
2921 /* Do not touch SerDes registers */
2922 if (ah
->config
.pcie_powersave_enable
== 2)
2925 /* Nothing to do on restore for 11N */
2929 if (AR_SREV_9280_20_OR_LATER(ah
)) {
2931 * AR9280 2.0 or later chips use SerDes values from the
2932 * initvals.h initialized depending on chipset during
2935 for (i
= 0; i
< ah
->iniPcieSerdes
.ia_rows
; i
++) {
2936 REG_WRITE(ah
, INI_RA(&ah
->iniPcieSerdes
, i
, 0),
2937 INI_RA(&ah
->iniPcieSerdes
, i
, 1));
2939 } else if (AR_SREV_9280(ah
) &&
2940 (ah
->hw_version
.macRev
== AR_SREV_REVISION_9280_10
)) {
2941 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x9248fd00);
2942 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x24924924);
2944 /* RX shut off when elecidle is asserted */
2945 REG_WRITE(ah
, AR_PCIE_SERDES
, 0xa8000019);
2946 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x13160820);
2947 REG_WRITE(ah
, AR_PCIE_SERDES
, 0xe5980560);
2949 /* Shut off CLKREQ active in L1 */
2950 if (ah
->config
.pcie_clock_req
)
2951 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x401deffc);
2953 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x401deffd);
2955 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x1aaabe40);
2956 REG_WRITE(ah
, AR_PCIE_SERDES
, 0xbe105554);
2957 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x00043007);
2959 /* Load the new settings */
2960 REG_WRITE(ah
, AR_PCIE_SERDES2
, 0x00000000);
2963 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x9248fc00);
2964 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x24924924);
2966 /* RX shut off when elecidle is asserted */
2967 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x28000039);
2968 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x53160824);
2969 REG_WRITE(ah
, AR_PCIE_SERDES
, 0xe5980579);
2972 * Ignore ah->ah_config.pcie_clock_req setting for
2975 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x001defff);
2977 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x1aaabe40);
2978 REG_WRITE(ah
, AR_PCIE_SERDES
, 0xbe105554);
2979 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x000e3007);
2981 /* Load the new settings */
2982 REG_WRITE(ah
, AR_PCIE_SERDES2
, 0x00000000);
2987 /* set bit 19 to allow forcing of pcie core into L1 state */
2988 REG_SET_BIT(ah
, AR_PCIE_PM_CTRL
, AR_PCIE_PM_CTRL_ENA
);
2990 /* Several PCIe massages to ensure proper behaviour */
2991 if (ah
->config
.pcie_waen
) {
2992 REG_WRITE(ah
, AR_WA
, ah
->config
.pcie_waen
);
2994 if (AR_SREV_9285(ah
))
2995 REG_WRITE(ah
, AR_WA
, AR9285_WA_DEFAULT
);
2997 * On AR9280 chips bit 22 of 0x4004 needs to be set to
2998 * otherwise card may disappear.
3000 else if (AR_SREV_9280(ah
))
3001 REG_WRITE(ah
, AR_WA
, AR9280_WA_DEFAULT
);
3003 REG_WRITE(ah
, AR_WA
, AR_WA_DEFAULT
);
3007 /**********************/
3008 /* Interrupt Handling */
3009 /**********************/
3011 bool ath9k_hw_intrpend(struct ath_hw
*ah
)
3015 if (AR_SREV_9100(ah
))
3018 host_isr
= REG_READ(ah
, AR_INTR_ASYNC_CAUSE
);
3019 if ((host_isr
& AR_INTR_MAC_IRQ
) && (host_isr
!= AR_INTR_SPURIOUS
))
3022 host_isr
= REG_READ(ah
, AR_INTR_SYNC_CAUSE
);
3023 if ((host_isr
& AR_INTR_SYNC_DEFAULT
)
3024 && (host_isr
!= AR_INTR_SPURIOUS
))
3030 bool ath9k_hw_getisr(struct ath_hw
*ah
, enum ath9k_int
*masked
)
3034 struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
3036 bool fatal_int
= false;
3038 if (!AR_SREV_9100(ah
)) {
3039 if (REG_READ(ah
, AR_INTR_ASYNC_CAUSE
) & AR_INTR_MAC_IRQ
) {
3040 if ((REG_READ(ah
, AR_RTC_STATUS
) & AR_RTC_STATUS_M
)
3041 == AR_RTC_STATUS_ON
) {
3042 isr
= REG_READ(ah
, AR_ISR
);
3046 sync_cause
= REG_READ(ah
, AR_INTR_SYNC_CAUSE
) &
3047 AR_INTR_SYNC_DEFAULT
;
3051 if (!isr
&& !sync_cause
)
3055 isr
= REG_READ(ah
, AR_ISR
);
3059 if (isr
& AR_ISR_BCNMISC
) {
3061 isr2
= REG_READ(ah
, AR_ISR_S2
);
3062 if (isr2
& AR_ISR_S2_TIM
)
3063 mask2
|= ATH9K_INT_TIM
;
3064 if (isr2
& AR_ISR_S2_DTIM
)
3065 mask2
|= ATH9K_INT_DTIM
;
3066 if (isr2
& AR_ISR_S2_DTIMSYNC
)
3067 mask2
|= ATH9K_INT_DTIMSYNC
;
3068 if (isr2
& (AR_ISR_S2_CABEND
))
3069 mask2
|= ATH9K_INT_CABEND
;
3070 if (isr2
& AR_ISR_S2_GTT
)
3071 mask2
|= ATH9K_INT_GTT
;
3072 if (isr2
& AR_ISR_S2_CST
)
3073 mask2
|= ATH9K_INT_CST
;
3074 if (isr2
& AR_ISR_S2_TSFOOR
)
3075 mask2
|= ATH9K_INT_TSFOOR
;
3078 isr
= REG_READ(ah
, AR_ISR_RAC
);
3079 if (isr
== 0xffffffff) {
3084 *masked
= isr
& ATH9K_INT_COMMON
;
3086 if (ah
->config
.intr_mitigation
) {
3087 if (isr
& (AR_ISR_RXMINTR
| AR_ISR_RXINTM
))
3088 *masked
|= ATH9K_INT_RX
;
3091 if (isr
& (AR_ISR_RXOK
| AR_ISR_RXERR
))
3092 *masked
|= ATH9K_INT_RX
;
3094 (AR_ISR_TXOK
| AR_ISR_TXDESC
| AR_ISR_TXERR
|
3098 *masked
|= ATH9K_INT_TX
;
3100 s0_s
= REG_READ(ah
, AR_ISR_S0_S
);
3101 ah
->intr_txqs
|= MS(s0_s
, AR_ISR_S0_QCU_TXOK
);
3102 ah
->intr_txqs
|= MS(s0_s
, AR_ISR_S0_QCU_TXDESC
);
3104 s1_s
= REG_READ(ah
, AR_ISR_S1_S
);
3105 ah
->intr_txqs
|= MS(s1_s
, AR_ISR_S1_QCU_TXERR
);
3106 ah
->intr_txqs
|= MS(s1_s
, AR_ISR_S1_QCU_TXEOL
);
3109 if (isr
& AR_ISR_RXORN
) {
3110 DPRINTF(ah
->ah_sc
, ATH_DBG_INTERRUPT
,
3111 "receive FIFO overrun interrupt\n");
3114 if (!AR_SREV_9100(ah
)) {
3115 if (!(pCap
->hw_caps
& ATH9K_HW_CAP_AUTOSLEEP
)) {
3116 u32 isr5
= REG_READ(ah
, AR_ISR_S5_S
);
3117 if (isr5
& AR_ISR_S5_TIM_TIMER
)
3118 *masked
|= ATH9K_INT_TIM_TIMER
;
3125 if (AR_SREV_9100(ah
))
3131 (AR_INTR_SYNC_HOST1_FATAL
| AR_INTR_SYNC_HOST1_PERR
))
3135 if (sync_cause
& AR_INTR_SYNC_HOST1_FATAL
) {
3136 DPRINTF(ah
->ah_sc
, ATH_DBG_ANY
,
3137 "received PCI FATAL interrupt\n");
3139 if (sync_cause
& AR_INTR_SYNC_HOST1_PERR
) {
3140 DPRINTF(ah
->ah_sc
, ATH_DBG_ANY
,
3141 "received PCI PERR interrupt\n");
3143 *masked
|= ATH9K_INT_FATAL
;
3145 if (sync_cause
& AR_INTR_SYNC_RADM_CPL_TIMEOUT
) {
3146 DPRINTF(ah
->ah_sc
, ATH_DBG_INTERRUPT
,
3147 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
3148 REG_WRITE(ah
, AR_RC
, AR_RC_HOSTIF
);
3149 REG_WRITE(ah
, AR_RC
, 0);
3150 *masked
|= ATH9K_INT_FATAL
;
3152 if (sync_cause
& AR_INTR_SYNC_LOCAL_TIMEOUT
) {
3153 DPRINTF(ah
->ah_sc
, ATH_DBG_INTERRUPT
,
3154 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
3157 REG_WRITE(ah
, AR_INTR_SYNC_CAUSE_CLR
, sync_cause
);
3158 (void) REG_READ(ah
, AR_INTR_SYNC_CAUSE_CLR
);
3164 enum ath9k_int
ath9k_hw_set_interrupts(struct ath_hw
*ah
, enum ath9k_int ints
)
3166 u32 omask
= ah
->mask_reg
;
3168 struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
3170 DPRINTF(ah
->ah_sc
, ATH_DBG_INTERRUPT
, "0x%x => 0x%x\n", omask
, ints
);
3172 if (omask
& ATH9K_INT_GLOBAL
) {
3173 DPRINTF(ah
->ah_sc
, ATH_DBG_INTERRUPT
, "disable IER\n");
3174 REG_WRITE(ah
, AR_IER
, AR_IER_DISABLE
);
3175 (void) REG_READ(ah
, AR_IER
);
3176 if (!AR_SREV_9100(ah
)) {
3177 REG_WRITE(ah
, AR_INTR_ASYNC_ENABLE
, 0);
3178 (void) REG_READ(ah
, AR_INTR_ASYNC_ENABLE
);
3180 REG_WRITE(ah
, AR_INTR_SYNC_ENABLE
, 0);
3181 (void) REG_READ(ah
, AR_INTR_SYNC_ENABLE
);
3185 mask
= ints
& ATH9K_INT_COMMON
;
3188 if (ints
& ATH9K_INT_TX
) {
3189 if (ah
->txok_interrupt_mask
)
3190 mask
|= AR_IMR_TXOK
;
3191 if (ah
->txdesc_interrupt_mask
)
3192 mask
|= AR_IMR_TXDESC
;
3193 if (ah
->txerr_interrupt_mask
)
3194 mask
|= AR_IMR_TXERR
;
3195 if (ah
->txeol_interrupt_mask
)
3196 mask
|= AR_IMR_TXEOL
;
3198 if (ints
& ATH9K_INT_RX
) {
3199 mask
|= AR_IMR_RXERR
;
3200 if (ah
->config
.intr_mitigation
)
3201 mask
|= AR_IMR_RXMINTR
| AR_IMR_RXINTM
;
3203 mask
|= AR_IMR_RXOK
| AR_IMR_RXDESC
;
3204 if (!(pCap
->hw_caps
& ATH9K_HW_CAP_AUTOSLEEP
))
3205 mask
|= AR_IMR_GENTMR
;
3208 if (ints
& (ATH9K_INT_BMISC
)) {
3209 mask
|= AR_IMR_BCNMISC
;
3210 if (ints
& ATH9K_INT_TIM
)
3211 mask2
|= AR_IMR_S2_TIM
;
3212 if (ints
& ATH9K_INT_DTIM
)
3213 mask2
|= AR_IMR_S2_DTIM
;
3214 if (ints
& ATH9K_INT_DTIMSYNC
)
3215 mask2
|= AR_IMR_S2_DTIMSYNC
;
3216 if (ints
& ATH9K_INT_CABEND
)
3217 mask2
|= AR_IMR_S2_CABEND
;
3218 if (ints
& ATH9K_INT_TSFOOR
)
3219 mask2
|= AR_IMR_S2_TSFOOR
;
3222 if (ints
& (ATH9K_INT_GTT
| ATH9K_INT_CST
)) {
3223 mask
|= AR_IMR_BCNMISC
;
3224 if (ints
& ATH9K_INT_GTT
)
3225 mask2
|= AR_IMR_S2_GTT
;
3226 if (ints
& ATH9K_INT_CST
)
3227 mask2
|= AR_IMR_S2_CST
;
3230 DPRINTF(ah
->ah_sc
, ATH_DBG_INTERRUPT
, "new IMR 0x%x\n", mask
);
3231 REG_WRITE(ah
, AR_IMR
, mask
);
3232 mask
= REG_READ(ah
, AR_IMR_S2
) & ~(AR_IMR_S2_TIM
|
3234 AR_IMR_S2_DTIMSYNC
|
3238 AR_IMR_S2_GTT
| AR_IMR_S2_CST
);
3239 REG_WRITE(ah
, AR_IMR_S2
, mask
| mask2
);
3240 ah
->mask_reg
= ints
;
3242 if (!(pCap
->hw_caps
& ATH9K_HW_CAP_AUTOSLEEP
)) {
3243 if (ints
& ATH9K_INT_TIM_TIMER
)
3244 REG_SET_BIT(ah
, AR_IMR_S5
, AR_IMR_S5_TIM_TIMER
);
3246 REG_CLR_BIT(ah
, AR_IMR_S5
, AR_IMR_S5_TIM_TIMER
);
3249 if (ints
& ATH9K_INT_GLOBAL
) {
3250 DPRINTF(ah
->ah_sc
, ATH_DBG_INTERRUPT
, "enable IER\n");
3251 REG_WRITE(ah
, AR_IER
, AR_IER_ENABLE
);
3252 if (!AR_SREV_9100(ah
)) {
3253 REG_WRITE(ah
, AR_INTR_ASYNC_ENABLE
,
3255 REG_WRITE(ah
, AR_INTR_ASYNC_MASK
, AR_INTR_MAC_IRQ
);
3258 REG_WRITE(ah
, AR_INTR_SYNC_ENABLE
,
3259 AR_INTR_SYNC_DEFAULT
);
3260 REG_WRITE(ah
, AR_INTR_SYNC_MASK
,
3261 AR_INTR_SYNC_DEFAULT
);
3263 DPRINTF(ah
->ah_sc
, ATH_DBG_INTERRUPT
, "AR_IMR 0x%x IER 0x%x\n",
3264 REG_READ(ah
, AR_IMR
), REG_READ(ah
, AR_IER
));
3270 /*******************/
3271 /* Beacon Handling */
3272 /*******************/
3274 void ath9k_hw_beaconinit(struct ath_hw
*ah
, u32 next_beacon
, u32 beacon_period
)
3278 ah
->beacon_interval
= beacon_period
;
3280 switch (ah
->opmode
) {
3281 case NL80211_IFTYPE_STATION
:
3282 case NL80211_IFTYPE_MONITOR
:
3283 REG_WRITE(ah
, AR_NEXT_TBTT_TIMER
, TU_TO_USEC(next_beacon
));
3284 REG_WRITE(ah
, AR_NEXT_DMA_BEACON_ALERT
, 0xffff);
3285 REG_WRITE(ah
, AR_NEXT_SWBA
, 0x7ffff);
3286 flags
|= AR_TBTT_TIMER_EN
;
3288 case NL80211_IFTYPE_ADHOC
:
3289 case NL80211_IFTYPE_MESH_POINT
:
3290 REG_SET_BIT(ah
, AR_TXCFG
,
3291 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY
);
3292 REG_WRITE(ah
, AR_NEXT_NDP_TIMER
,
3293 TU_TO_USEC(next_beacon
+
3294 (ah
->atim_window
? ah
->
3296 flags
|= AR_NDP_TIMER_EN
;
3297 case NL80211_IFTYPE_AP
:
3298 REG_WRITE(ah
, AR_NEXT_TBTT_TIMER
, TU_TO_USEC(next_beacon
));
3299 REG_WRITE(ah
, AR_NEXT_DMA_BEACON_ALERT
,
3300 TU_TO_USEC(next_beacon
-
3302 dma_beacon_response_time
));
3303 REG_WRITE(ah
, AR_NEXT_SWBA
,
3304 TU_TO_USEC(next_beacon
-
3306 sw_beacon_response_time
));
3308 AR_TBTT_TIMER_EN
| AR_DBA_TIMER_EN
| AR_SWBA_TIMER_EN
;
3311 DPRINTF(ah
->ah_sc
, ATH_DBG_BEACON
,
3312 "%s: unsupported opmode: %d\n",
3313 __func__
, ah
->opmode
);
3318 REG_WRITE(ah
, AR_BEACON_PERIOD
, TU_TO_USEC(beacon_period
));
3319 REG_WRITE(ah
, AR_DMA_BEACON_PERIOD
, TU_TO_USEC(beacon_period
));
3320 REG_WRITE(ah
, AR_SWBA_PERIOD
, TU_TO_USEC(beacon_period
));
3321 REG_WRITE(ah
, AR_NDP_PERIOD
, TU_TO_USEC(beacon_period
));
3323 beacon_period
&= ~ATH9K_BEACON_ENA
;
3324 if (beacon_period
& ATH9K_BEACON_RESET_TSF
) {
3325 beacon_period
&= ~ATH9K_BEACON_RESET_TSF
;
3326 ath9k_hw_reset_tsf(ah
);
3329 REG_SET_BIT(ah
, AR_TIMER_MODE
, flags
);
3332 void ath9k_hw_set_sta_beacon_timers(struct ath_hw
*ah
,
3333 const struct ath9k_beacon_state
*bs
)
3335 u32 nextTbtt
, beaconintval
, dtimperiod
, beacontimeout
;
3336 struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
3338 REG_WRITE(ah
, AR_NEXT_TBTT_TIMER
, TU_TO_USEC(bs
->bs_nexttbtt
));
3340 REG_WRITE(ah
, AR_BEACON_PERIOD
,
3341 TU_TO_USEC(bs
->bs_intval
& ATH9K_BEACON_PERIOD
));
3342 REG_WRITE(ah
, AR_DMA_BEACON_PERIOD
,
3343 TU_TO_USEC(bs
->bs_intval
& ATH9K_BEACON_PERIOD
));
3345 REG_RMW_FIELD(ah
, AR_RSSI_THR
,
3346 AR_RSSI_THR_BM_THR
, bs
->bs_bmissthreshold
);
3348 beaconintval
= bs
->bs_intval
& ATH9K_BEACON_PERIOD
;
3350 if (bs
->bs_sleepduration
> beaconintval
)
3351 beaconintval
= bs
->bs_sleepduration
;
3353 dtimperiod
= bs
->bs_dtimperiod
;
3354 if (bs
->bs_sleepduration
> dtimperiod
)
3355 dtimperiod
= bs
->bs_sleepduration
;
3357 if (beaconintval
== dtimperiod
)
3358 nextTbtt
= bs
->bs_nextdtim
;
3360 nextTbtt
= bs
->bs_nexttbtt
;
3362 DPRINTF(ah
->ah_sc
, ATH_DBG_BEACON
, "next DTIM %d\n", bs
->bs_nextdtim
);
3363 DPRINTF(ah
->ah_sc
, ATH_DBG_BEACON
, "next beacon %d\n", nextTbtt
);
3364 DPRINTF(ah
->ah_sc
, ATH_DBG_BEACON
, "beacon period %d\n", beaconintval
);
3365 DPRINTF(ah
->ah_sc
, ATH_DBG_BEACON
, "DTIM period %d\n", dtimperiod
);
3367 REG_WRITE(ah
, AR_NEXT_DTIM
,
3368 TU_TO_USEC(bs
->bs_nextdtim
- SLEEP_SLOP
));
3369 REG_WRITE(ah
, AR_NEXT_TIM
, TU_TO_USEC(nextTbtt
- SLEEP_SLOP
));
3371 REG_WRITE(ah
, AR_SLEEP1
,
3372 SM((CAB_TIMEOUT_VAL
<< 3), AR_SLEEP1_CAB_TIMEOUT
)
3373 | AR_SLEEP1_ASSUME_DTIM
);
3375 if (pCap
->hw_caps
& ATH9K_HW_CAP_AUTOSLEEP
)
3376 beacontimeout
= (BEACON_TIMEOUT_VAL
<< 3);
3378 beacontimeout
= MIN_BEACON_TIMEOUT_VAL
;
3380 REG_WRITE(ah
, AR_SLEEP2
,
3381 SM(beacontimeout
, AR_SLEEP2_BEACON_TIMEOUT
));
3383 REG_WRITE(ah
, AR_TIM_PERIOD
, TU_TO_USEC(beaconintval
));
3384 REG_WRITE(ah
, AR_DTIM_PERIOD
, TU_TO_USEC(dtimperiod
));
3386 REG_SET_BIT(ah
, AR_TIMER_MODE
,
3387 AR_TBTT_TIMER_EN
| AR_TIM_TIMER_EN
|
3390 /* TSF Out of Range Threshold */
3391 REG_WRITE(ah
, AR_TSFOOR_THRESHOLD
, bs
->bs_tsfoor_threshold
);
3394 /*******************/
3395 /* HW Capabilities */
3396 /*******************/
3398 void ath9k_hw_fill_cap_info(struct ath_hw
*ah
)
3400 struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
3401 u16 capField
= 0, eeval
;
3403 eeval
= ah
->eep_ops
->get_eeprom(ah
, EEP_REG_0
);
3404 ah
->regulatory
.current_rd
= eeval
;
3406 eeval
= ah
->eep_ops
->get_eeprom(ah
, EEP_REG_1
);
3407 if (AR_SREV_9285_10_OR_LATER(ah
))
3408 eeval
|= AR9285_RDEXT_DEFAULT
;
3409 ah
->regulatory
.current_rd_ext
= eeval
;
3411 capField
= ah
->eep_ops
->get_eeprom(ah
, EEP_OP_CAP
);
3413 if (ah
->opmode
!= NL80211_IFTYPE_AP
&&
3414 ah
->hw_version
.subvendorid
== AR_SUBVENDOR_ID_NEW_A
) {
3415 if (ah
->regulatory
.current_rd
== 0x64 ||
3416 ah
->regulatory
.current_rd
== 0x65)
3417 ah
->regulatory
.current_rd
+= 5;
3418 else if (ah
->regulatory
.current_rd
== 0x41)
3419 ah
->regulatory
.current_rd
= 0x43;
3420 DPRINTF(ah
->ah_sc
, ATH_DBG_REGULATORY
,
3421 "regdomain mapped to 0x%x\n", ah
->regulatory
.current_rd
);
3424 eeval
= ah
->eep_ops
->get_eeprom(ah
, EEP_OP_MODE
);
3425 bitmap_zero(pCap
->wireless_modes
, ATH9K_MODE_MAX
);
3427 if (eeval
& AR5416_OPFLAGS_11A
) {
3428 set_bit(ATH9K_MODE_11A
, pCap
->wireless_modes
);
3429 if (ah
->config
.ht_enable
) {
3430 if (!(eeval
& AR5416_OPFLAGS_N_5G_HT20
))
3431 set_bit(ATH9K_MODE_11NA_HT20
,
3432 pCap
->wireless_modes
);
3433 if (!(eeval
& AR5416_OPFLAGS_N_5G_HT40
)) {
3434 set_bit(ATH9K_MODE_11NA_HT40PLUS
,
3435 pCap
->wireless_modes
);
3436 set_bit(ATH9K_MODE_11NA_HT40MINUS
,
3437 pCap
->wireless_modes
);
3442 if (eeval
& AR5416_OPFLAGS_11G
) {
3443 set_bit(ATH9K_MODE_11G
, pCap
->wireless_modes
);
3444 if (ah
->config
.ht_enable
) {
3445 if (!(eeval
& AR5416_OPFLAGS_N_2G_HT20
))
3446 set_bit(ATH9K_MODE_11NG_HT20
,
3447 pCap
->wireless_modes
);
3448 if (!(eeval
& AR5416_OPFLAGS_N_2G_HT40
)) {
3449 set_bit(ATH9K_MODE_11NG_HT40PLUS
,
3450 pCap
->wireless_modes
);
3451 set_bit(ATH9K_MODE_11NG_HT40MINUS
,
3452 pCap
->wireless_modes
);
3457 pCap
->tx_chainmask
= ah
->eep_ops
->get_eeprom(ah
, EEP_TX_MASK
);
3458 if ((ah
->hw_version
.devid
== AR5416_DEVID_PCI
) &&
3459 !(eeval
& AR5416_OPFLAGS_11A
))
3460 pCap
->rx_chainmask
= ath9k_hw_gpio_get(ah
, 0) ? 0x5 : 0x7;
3462 pCap
->rx_chainmask
= ah
->eep_ops
->get_eeprom(ah
, EEP_RX_MASK
);
3464 if (!(AR_SREV_9280(ah
) && (ah
->hw_version
.macRev
== 0)))
3465 ah
->misc_mode
|= AR_PCU_MIC_NEW_LOC_ENA
;
3467 pCap
->low_2ghz_chan
= 2312;
3468 pCap
->high_2ghz_chan
= 2732;
3470 pCap
->low_5ghz_chan
= 4920;
3471 pCap
->high_5ghz_chan
= 6100;
3473 pCap
->hw_caps
&= ~ATH9K_HW_CAP_CIPHER_CKIP
;
3474 pCap
->hw_caps
|= ATH9K_HW_CAP_CIPHER_TKIP
;
3475 pCap
->hw_caps
|= ATH9K_HW_CAP_CIPHER_AESCCM
;
3477 pCap
->hw_caps
&= ~ATH9K_HW_CAP_MIC_CKIP
;
3478 pCap
->hw_caps
|= ATH9K_HW_CAP_MIC_TKIP
;
3479 pCap
->hw_caps
|= ATH9K_HW_CAP_MIC_AESCCM
;
3481 if (ah
->config
.ht_enable
)
3482 pCap
->hw_caps
|= ATH9K_HW_CAP_HT
;
3484 pCap
->hw_caps
&= ~ATH9K_HW_CAP_HT
;
3486 pCap
->hw_caps
|= ATH9K_HW_CAP_GTT
;
3487 pCap
->hw_caps
|= ATH9K_HW_CAP_VEOL
;
3488 pCap
->hw_caps
|= ATH9K_HW_CAP_BSSIDMASK
;
3489 pCap
->hw_caps
&= ~ATH9K_HW_CAP_MCAST_KEYSEARCH
;
3491 if (capField
& AR_EEPROM_EEPCAP_MAXQCU
)
3492 pCap
->total_queues
=
3493 MS(capField
, AR_EEPROM_EEPCAP_MAXQCU
);
3495 pCap
->total_queues
= ATH9K_NUM_TX_QUEUES
;
3497 if (capField
& AR_EEPROM_EEPCAP_KC_ENTRIES
)
3498 pCap
->keycache_size
=
3499 1 << MS(capField
, AR_EEPROM_EEPCAP_KC_ENTRIES
);
3501 pCap
->keycache_size
= AR_KEYTABLE_SIZE
;
3503 pCap
->hw_caps
|= ATH9K_HW_CAP_FASTCC
;
3504 pCap
->tx_triglevel_max
= MAX_TX_FIFO_THRESHOLD
;
3506 if (AR_SREV_9285_10_OR_LATER(ah
))
3507 pCap
->num_gpio_pins
= AR9285_NUM_GPIO
;
3508 else if (AR_SREV_9280_10_OR_LATER(ah
))
3509 pCap
->num_gpio_pins
= AR928X_NUM_GPIO
;
3511 pCap
->num_gpio_pins
= AR_NUM_GPIO
;
3513 if (AR_SREV_9160_10_OR_LATER(ah
) || AR_SREV_9100(ah
)) {
3514 pCap
->hw_caps
|= ATH9K_HW_CAP_CST
;
3515 pCap
->rts_aggr_limit
= ATH_AMPDU_LIMIT_MAX
;
3517 pCap
->rts_aggr_limit
= (8 * 1024);
3520 pCap
->hw_caps
|= ATH9K_HW_CAP_ENHANCEDPM
;
3522 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3523 ah
->rfsilent
= ah
->eep_ops
->get_eeprom(ah
, EEP_RF_SILENT
);
3524 if (ah
->rfsilent
& EEP_RFSILENT_ENABLED
) {
3526 MS(ah
->rfsilent
, EEP_RFSILENT_GPIO_SEL
);
3527 ah
->rfkill_polarity
=
3528 MS(ah
->rfsilent
, EEP_RFSILENT_POLARITY
);
3530 pCap
->hw_caps
|= ATH9K_HW_CAP_RFSILENT
;
3534 if ((ah
->hw_version
.macVersion
== AR_SREV_VERSION_5416_PCI
) ||
3535 (ah
->hw_version
.macVersion
== AR_SREV_VERSION_5416_PCIE
) ||
3536 (ah
->hw_version
.macVersion
== AR_SREV_VERSION_9160
) ||
3537 (ah
->hw_version
.macVersion
== AR_SREV_VERSION_9100
) ||
3538 (ah
->hw_version
.macVersion
== AR_SREV_VERSION_9280
) ||
3539 (ah
->hw_version
.macVersion
== AR_SREV_VERSION_9285
))
3540 pCap
->hw_caps
&= ~ATH9K_HW_CAP_AUTOSLEEP
;
3542 pCap
->hw_caps
|= ATH9K_HW_CAP_AUTOSLEEP
;
3544 if (AR_SREV_9280(ah
) || AR_SREV_9285(ah
))
3545 pCap
->hw_caps
&= ~ATH9K_HW_CAP_4KB_SPLITTRANS
;
3547 pCap
->hw_caps
|= ATH9K_HW_CAP_4KB_SPLITTRANS
;
3549 if (ah
->regulatory
.current_rd_ext
& (1 << REG_EXT_JAPAN_MIDBAND
)) {
3551 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A
|
3552 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN
|
3553 AR_EEPROM_EEREGCAP_EN_KK_U2
|
3554 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND
;
3557 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A
|
3558 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN
;
3561 pCap
->reg_cap
|= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND
;
3563 pCap
->num_antcfg_5ghz
=
3564 ah
->eep_ops
->get_num_ant_config(ah
, ATH9K_HAL_FREQ_BAND_5GHZ
);
3565 pCap
->num_antcfg_2ghz
=
3566 ah
->eep_ops
->get_num_ant_config(ah
, ATH9K_HAL_FREQ_BAND_2GHZ
);
3568 if (AR_SREV_9280_10_OR_LATER(ah
) && btcoex_enable
) {
3569 pCap
->hw_caps
|= ATH9K_HW_CAP_BT_COEX
;
3570 ah
->btactive_gpio
= 6;
3571 ah
->wlanactive_gpio
= 5;
3575 bool ath9k_hw_getcapability(struct ath_hw
*ah
, enum ath9k_capability_type type
,
3576 u32 capability
, u32
*result
)
3579 case ATH9K_CAP_CIPHER
:
3580 switch (capability
) {
3581 case ATH9K_CIPHER_AES_CCM
:
3582 case ATH9K_CIPHER_AES_OCB
:
3583 case ATH9K_CIPHER_TKIP
:
3584 case ATH9K_CIPHER_WEP
:
3585 case ATH9K_CIPHER_MIC
:
3586 case ATH9K_CIPHER_CLR
:
3591 case ATH9K_CAP_TKIP_MIC
:
3592 switch (capability
) {
3596 return (ah
->sta_id1_defaults
&
3597 AR_STA_ID1_CRPT_MIC_ENABLE
) ? true :
3600 case ATH9K_CAP_TKIP_SPLIT
:
3601 return (ah
->misc_mode
& AR_PCU_MIC_NEW_LOC_ENA
) ?
3603 case ATH9K_CAP_DIVERSITY
:
3604 return (REG_READ(ah
, AR_PHY_CCK_DETECT
) &
3605 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV
) ?
3607 case ATH9K_CAP_MCAST_KEYSRCH
:
3608 switch (capability
) {
3612 if (REG_READ(ah
, AR_STA_ID1
) & AR_STA_ID1_ADHOC
) {
3615 return (ah
->sta_id1_defaults
&
3616 AR_STA_ID1_MCAST_KSRCH
) ? true :
3621 case ATH9K_CAP_TXPOW
:
3622 switch (capability
) {
3626 *result
= ah
->regulatory
.power_limit
;
3629 *result
= ah
->regulatory
.max_power_level
;
3632 *result
= ah
->regulatory
.tp_scale
;
3637 return (AR_SREV_9280_20_OR_LATER(ah
) &&
3638 (ah
->eep_ops
->get_eeprom(ah
, EEP_RC_CHAIN_MASK
) == 1))
3645 bool ath9k_hw_setcapability(struct ath_hw
*ah
, enum ath9k_capability_type type
,
3646 u32 capability
, u32 setting
, int *status
)
3651 case ATH9K_CAP_TKIP_MIC
:
3653 ah
->sta_id1_defaults
|=
3654 AR_STA_ID1_CRPT_MIC_ENABLE
;
3656 ah
->sta_id1_defaults
&=
3657 ~AR_STA_ID1_CRPT_MIC_ENABLE
;
3659 case ATH9K_CAP_DIVERSITY
:
3660 v
= REG_READ(ah
, AR_PHY_CCK_DETECT
);
3662 v
|= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV
;
3664 v
&= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV
;
3665 REG_WRITE(ah
, AR_PHY_CCK_DETECT
, v
);
3667 case ATH9K_CAP_MCAST_KEYSRCH
:
3669 ah
->sta_id1_defaults
|= AR_STA_ID1_MCAST_KSRCH
;
3671 ah
->sta_id1_defaults
&= ~AR_STA_ID1_MCAST_KSRCH
;
3678 /****************************/
3679 /* GPIO / RFKILL / Antennae */
3680 /****************************/
3682 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw
*ah
,
3686 u32 gpio_shift
, tmp
;
3689 addr
= AR_GPIO_OUTPUT_MUX3
;
3691 addr
= AR_GPIO_OUTPUT_MUX2
;
3693 addr
= AR_GPIO_OUTPUT_MUX1
;
3695 gpio_shift
= (gpio
% 6) * 5;
3697 if (AR_SREV_9280_20_OR_LATER(ah
)
3698 || (addr
!= AR_GPIO_OUTPUT_MUX1
)) {
3699 REG_RMW(ah
, addr
, (type
<< gpio_shift
),
3700 (0x1f << gpio_shift
));
3702 tmp
= REG_READ(ah
, addr
);
3703 tmp
= ((tmp
& 0x1F0) << 1) | (tmp
& ~0x1F0);
3704 tmp
&= ~(0x1f << gpio_shift
);
3705 tmp
|= (type
<< gpio_shift
);
3706 REG_WRITE(ah
, addr
, tmp
);
3710 void ath9k_hw_cfg_gpio_input(struct ath_hw
*ah
, u32 gpio
)
3714 ASSERT(gpio
< ah
->caps
.num_gpio_pins
);
3716 gpio_shift
= gpio
<< 1;
3720 (AR_GPIO_OE_OUT_DRV_NO
<< gpio_shift
),
3721 (AR_GPIO_OE_OUT_DRV
<< gpio_shift
));
3724 u32
ath9k_hw_gpio_get(struct ath_hw
*ah
, u32 gpio
)
3726 #define MS_REG_READ(x, y) \
3727 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3729 if (gpio
>= ah
->caps
.num_gpio_pins
)
3732 if (AR_SREV_9287_10_OR_LATER(ah
))
3733 return MS_REG_READ(AR9287
, gpio
) != 0;
3734 else if (AR_SREV_9285_10_OR_LATER(ah
))
3735 return MS_REG_READ(AR9285
, gpio
) != 0;
3736 else if (AR_SREV_9280_10_OR_LATER(ah
))
3737 return MS_REG_READ(AR928X
, gpio
) != 0;
3739 return MS_REG_READ(AR
, gpio
) != 0;
3742 void ath9k_hw_cfg_output(struct ath_hw
*ah
, u32 gpio
,
3747 ath9k_hw_gpio_cfg_output_mux(ah
, gpio
, ah_signal_type
);
3749 gpio_shift
= 2 * gpio
;
3753 (AR_GPIO_OE_OUT_DRV_ALL
<< gpio_shift
),
3754 (AR_GPIO_OE_OUT_DRV
<< gpio_shift
));
3757 void ath9k_hw_set_gpio(struct ath_hw
*ah
, u32 gpio
, u32 val
)
3759 REG_RMW(ah
, AR_GPIO_IN_OUT
, ((val
& 1) << gpio
),
3763 u32
ath9k_hw_getdefantenna(struct ath_hw
*ah
)
3765 return REG_READ(ah
, AR_DEF_ANTENNA
) & 0x7;
3768 void ath9k_hw_setantenna(struct ath_hw
*ah
, u32 antenna
)
3770 REG_WRITE(ah
, AR_DEF_ANTENNA
, (antenna
& 0x7));
3773 bool ath9k_hw_setantennaswitch(struct ath_hw
*ah
,
3774 enum ath9k_ant_setting settings
,
3775 struct ath9k_channel
*chan
,
3780 static u8 tx_chainmask_cfg
, rx_chainmask_cfg
;
3782 if (AR_SREV_9280(ah
)) {
3783 if (!tx_chainmask_cfg
) {
3785 tx_chainmask_cfg
= *tx_chainmask
;
3786 rx_chainmask_cfg
= *rx_chainmask
;
3790 case ATH9K_ANT_FIXED_A
:
3791 *tx_chainmask
= ATH9K_ANTENNA0_CHAINMASK
;
3792 *rx_chainmask
= ATH9K_ANTENNA0_CHAINMASK
;
3793 *antenna_cfgd
= true;
3795 case ATH9K_ANT_FIXED_B
:
3796 if (ah
->caps
.tx_chainmask
>
3797 ATH9K_ANTENNA1_CHAINMASK
) {
3798 *tx_chainmask
= ATH9K_ANTENNA1_CHAINMASK
;
3800 *rx_chainmask
= ATH9K_ANTENNA1_CHAINMASK
;
3801 *antenna_cfgd
= true;
3803 case ATH9K_ANT_VARIABLE
:
3804 *tx_chainmask
= tx_chainmask_cfg
;
3805 *rx_chainmask
= rx_chainmask_cfg
;
3806 *antenna_cfgd
= true;
3812 ah
->diversity_control
= settings
;
3818 /*********************/
3819 /* General Operation */
3820 /*********************/
3822 u32
ath9k_hw_getrxfilter(struct ath_hw
*ah
)
3824 u32 bits
= REG_READ(ah
, AR_RX_FILTER
);
3825 u32 phybits
= REG_READ(ah
, AR_PHY_ERR
);
3827 if (phybits
& AR_PHY_ERR_RADAR
)
3828 bits
|= ATH9K_RX_FILTER_PHYRADAR
;
3829 if (phybits
& (AR_PHY_ERR_OFDM_TIMING
| AR_PHY_ERR_CCK_TIMING
))
3830 bits
|= ATH9K_RX_FILTER_PHYERR
;
3835 void ath9k_hw_setrxfilter(struct ath_hw
*ah
, u32 bits
)
3839 REG_WRITE(ah
, AR_RX_FILTER
, (bits
& 0xffff) | AR_RX_COMPR_BAR
);
3841 if (bits
& ATH9K_RX_FILTER_PHYRADAR
)
3842 phybits
|= AR_PHY_ERR_RADAR
;
3843 if (bits
& ATH9K_RX_FILTER_PHYERR
)
3844 phybits
|= AR_PHY_ERR_OFDM_TIMING
| AR_PHY_ERR_CCK_TIMING
;
3845 REG_WRITE(ah
, AR_PHY_ERR
, phybits
);
3848 REG_WRITE(ah
, AR_RXCFG
,
3849 REG_READ(ah
, AR_RXCFG
) | AR_RXCFG_ZLFDMA
);
3851 REG_WRITE(ah
, AR_RXCFG
,
3852 REG_READ(ah
, AR_RXCFG
) & ~AR_RXCFG_ZLFDMA
);
3855 bool ath9k_hw_phy_disable(struct ath_hw
*ah
)
3857 return ath9k_hw_set_reset_reg(ah
, ATH9K_RESET_WARM
);
3860 bool ath9k_hw_disable(struct ath_hw
*ah
)
3862 if (!ath9k_hw_setpower(ah
, ATH9K_PM_AWAKE
))
3865 return ath9k_hw_set_reset_reg(ah
, ATH9K_RESET_COLD
);
3868 void ath9k_hw_set_txpowerlimit(struct ath_hw
*ah
, u32 limit
)
3870 struct ath9k_channel
*chan
= ah
->curchan
;
3871 struct ieee80211_channel
*channel
= chan
->chan
;
3873 ah
->regulatory
.power_limit
= min(limit
, (u32
) MAX_RATE_POWER
);
3875 ah
->eep_ops
->set_txpower(ah
, chan
,
3876 ath9k_regd_get_ctl(&ah
->regulatory
, chan
),
3877 channel
->max_antenna_gain
* 2,
3878 channel
->max_power
* 2,
3879 min((u32
) MAX_RATE_POWER
,
3880 (u32
) ah
->regulatory
.power_limit
));
3883 void ath9k_hw_setmac(struct ath_hw
*ah
, const u8
*mac
)
3885 memcpy(ah
->macaddr
, mac
, ETH_ALEN
);
3888 void ath9k_hw_setopmode(struct ath_hw
*ah
)
3890 ath9k_hw_set_operating_mode(ah
, ah
->opmode
);
3893 void ath9k_hw_setmcastfilter(struct ath_hw
*ah
, u32 filter0
, u32 filter1
)
3895 REG_WRITE(ah
, AR_MCAST_FIL0
, filter0
);
3896 REG_WRITE(ah
, AR_MCAST_FIL1
, filter1
);
3899 void ath9k_hw_setbssidmask(struct ath_softc
*sc
)
3901 REG_WRITE(sc
->sc_ah
, AR_BSSMSKL
, get_unaligned_le32(sc
->bssidmask
));
3902 REG_WRITE(sc
->sc_ah
, AR_BSSMSKU
, get_unaligned_le16(sc
->bssidmask
+ 4));
3905 void ath9k_hw_write_associd(struct ath_softc
*sc
)
3907 REG_WRITE(sc
->sc_ah
, AR_BSS_ID0
, get_unaligned_le32(sc
->curbssid
));
3908 REG_WRITE(sc
->sc_ah
, AR_BSS_ID1
, get_unaligned_le16(sc
->curbssid
+ 4) |
3909 ((sc
->curaid
& 0x3fff) << AR_BSS_ID1_AID_S
));
3912 u64
ath9k_hw_gettsf64(struct ath_hw
*ah
)
3916 tsf
= REG_READ(ah
, AR_TSF_U32
);
3917 tsf
= (tsf
<< 32) | REG_READ(ah
, AR_TSF_L32
);
3922 void ath9k_hw_settsf64(struct ath_hw
*ah
, u64 tsf64
)
3924 REG_WRITE(ah
, AR_TSF_L32
, tsf64
& 0xffffffff);
3925 REG_WRITE(ah
, AR_TSF_U32
, (tsf64
>> 32) & 0xffffffff);
3928 void ath9k_hw_reset_tsf(struct ath_hw
*ah
)
3930 ath9k_ps_wakeup(ah
->ah_sc
);
3931 if (!ath9k_hw_wait(ah
, AR_SLP32_MODE
, AR_SLP32_TSF_WRITE_STATUS
, 0,
3932 AH_TSF_WRITE_TIMEOUT
))
3933 DPRINTF(ah
->ah_sc
, ATH_DBG_RESET
,
3934 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
3936 REG_WRITE(ah
, AR_RESET_TSF
, AR_RESET_TSF_ONCE
);
3937 ath9k_ps_restore(ah
->ah_sc
);
3940 bool ath9k_hw_set_tsfadjust(struct ath_hw
*ah
, u32 setting
)
3943 ah
->misc_mode
|= AR_PCU_TX_ADD_TSF
;
3945 ah
->misc_mode
&= ~AR_PCU_TX_ADD_TSF
;
3950 bool ath9k_hw_setslottime(struct ath_hw
*ah
, u32 us
)
3952 if (us
< ATH9K_SLOT_TIME_9
|| us
> ath9k_hw_mac_to_usec(ah
, 0xffff)) {
3953 DPRINTF(ah
->ah_sc
, ATH_DBG_RESET
, "bad slot time %u\n", us
);
3954 ah
->slottime
= (u32
) -1;
3957 REG_WRITE(ah
, AR_D_GBL_IFS_SLOT
, ath9k_hw_mac_to_clks(ah
, us
));
3963 void ath9k_hw_set11nmac2040(struct ath_hw
*ah
, enum ath9k_ht_macmode mode
)
3967 if (mode
== ATH9K_HT_MACMODE_2040
&&
3968 !ah
->config
.cwm_ignore_extcca
)
3969 macmode
= AR_2040_JOINED_RX_CLEAR
;
3973 REG_WRITE(ah
, AR_2040_MODE
, macmode
);
3976 /***************************/
3977 /* Bluetooth Coexistence */
3978 /***************************/
3980 void ath9k_hw_btcoex_enable(struct ath_hw
*ah
)
3982 /* connect bt_active to baseband */
3983 REG_CLR_BIT(ah
, AR_GPIO_INPUT_EN_VAL
,
3984 (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF
|
3985 AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF
));
3987 REG_SET_BIT(ah
, AR_GPIO_INPUT_EN_VAL
,
3988 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB
);
3990 /* Set input mux for bt_active to gpio pin */
3991 REG_RMW_FIELD(ah
, AR_GPIO_INPUT_MUX1
,
3992 AR_GPIO_INPUT_MUX1_BT_ACTIVE
,
3995 /* Configure the desired gpio port for input */
3996 ath9k_hw_cfg_gpio_input(ah
, ah
->btactive_gpio
);
3998 /* Configure the desired GPIO port for TX_FRAME output */
3999 ath9k_hw_cfg_output(ah
, ah
->wlanactive_gpio
,
4000 AR_GPIO_OUTPUT_MUX_AS_TX_FRAME
);