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x86: Move call to print_modules() out of show_regs()
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / hw.c
1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/io.h>
18 #include <linux/slab.h>
19 #include <linux/module.h>
20 #include <asm/unaligned.h>
21
22 #include "hw.h"
23 #include "hw-ops.h"
24 #include "rc.h"
25 #include "ar9003_mac.h"
26 #include "ar9003_mci.h"
27 #include "debug.h"
28 #include "ath9k.h"
29
30 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
31
32 MODULE_AUTHOR("Atheros Communications");
33 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
34 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
35 MODULE_LICENSE("Dual BSD/GPL");
36
37 static int __init ath9k_init(void)
38 {
39 return 0;
40 }
41 module_init(ath9k_init);
42
43 static void __exit ath9k_exit(void)
44 {
45 return;
46 }
47 module_exit(ath9k_exit);
48
49 /* Private hardware callbacks */
50
51 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
52 {
53 ath9k_hw_private_ops(ah)->init_cal_settings(ah);
54 }
55
56 static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
57 {
58 ath9k_hw_private_ops(ah)->init_mode_regs(ah);
59 }
60
61 static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
62 struct ath9k_channel *chan)
63 {
64 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
65 }
66
67 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
68 {
69 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
70 return;
71
72 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
73 }
74
75 static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah)
76 {
77 /* You will not have this callback if using the old ANI */
78 if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs)
79 return;
80
81 ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah);
82 }
83
84 /********************/
85 /* Helper Functions */
86 /********************/
87
88 #ifdef CONFIG_ATH9K_DEBUGFS
89
90 void ath9k_debug_sync_cause(struct ath_common *common, u32 sync_cause)
91 {
92 struct ath_softc *sc = common->priv;
93 if (sync_cause)
94 sc->debug.stats.istats.sync_cause_all++;
95 if (sync_cause & AR_INTR_SYNC_RTC_IRQ)
96 sc->debug.stats.istats.sync_rtc_irq++;
97 if (sync_cause & AR_INTR_SYNC_MAC_IRQ)
98 sc->debug.stats.istats.sync_mac_irq++;
99 if (sync_cause & AR_INTR_SYNC_EEPROM_ILLEGAL_ACCESS)
100 sc->debug.stats.istats.eeprom_illegal_access++;
101 if (sync_cause & AR_INTR_SYNC_APB_TIMEOUT)
102 sc->debug.stats.istats.apb_timeout++;
103 if (sync_cause & AR_INTR_SYNC_PCI_MODE_CONFLICT)
104 sc->debug.stats.istats.pci_mode_conflict++;
105 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL)
106 sc->debug.stats.istats.host1_fatal++;
107 if (sync_cause & AR_INTR_SYNC_HOST1_PERR)
108 sc->debug.stats.istats.host1_perr++;
109 if (sync_cause & AR_INTR_SYNC_TRCV_FIFO_PERR)
110 sc->debug.stats.istats.trcv_fifo_perr++;
111 if (sync_cause & AR_INTR_SYNC_RADM_CPL_EP)
112 sc->debug.stats.istats.radm_cpl_ep++;
113 if (sync_cause & AR_INTR_SYNC_RADM_CPL_DLLP_ABORT)
114 sc->debug.stats.istats.radm_cpl_dllp_abort++;
115 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TLP_ABORT)
116 sc->debug.stats.istats.radm_cpl_tlp_abort++;
117 if (sync_cause & AR_INTR_SYNC_RADM_CPL_ECRC_ERR)
118 sc->debug.stats.istats.radm_cpl_ecrc_err++;
119 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT)
120 sc->debug.stats.istats.radm_cpl_timeout++;
121 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT)
122 sc->debug.stats.istats.local_timeout++;
123 if (sync_cause & AR_INTR_SYNC_PM_ACCESS)
124 sc->debug.stats.istats.pm_access++;
125 if (sync_cause & AR_INTR_SYNC_MAC_AWAKE)
126 sc->debug.stats.istats.mac_awake++;
127 if (sync_cause & AR_INTR_SYNC_MAC_ASLEEP)
128 sc->debug.stats.istats.mac_asleep++;
129 if (sync_cause & AR_INTR_SYNC_MAC_SLEEP_ACCESS)
130 sc->debug.stats.istats.mac_sleep_access++;
131 }
132 #endif
133
134
135 static void ath9k_hw_set_clockrate(struct ath_hw *ah)
136 {
137 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
138 struct ath_common *common = ath9k_hw_common(ah);
139 unsigned int clockrate;
140
141 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */
142 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah))
143 clockrate = 117;
144 else if (!ah->curchan) /* should really check for CCK instead */
145 clockrate = ATH9K_CLOCK_RATE_CCK;
146 else if (conf->channel->band == IEEE80211_BAND_2GHZ)
147 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
148 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
149 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
150 else
151 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
152
153 if (conf_is_ht40(conf))
154 clockrate *= 2;
155
156 if (ah->curchan) {
157 if (IS_CHAN_HALF_RATE(ah->curchan))
158 clockrate /= 2;
159 if (IS_CHAN_QUARTER_RATE(ah->curchan))
160 clockrate /= 4;
161 }
162
163 common->clockrate = clockrate;
164 }
165
166 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
167 {
168 struct ath_common *common = ath9k_hw_common(ah);
169
170 return usecs * common->clockrate;
171 }
172
173 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
174 {
175 int i;
176
177 BUG_ON(timeout < AH_TIME_QUANTUM);
178
179 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
180 if ((REG_READ(ah, reg) & mask) == val)
181 return true;
182
183 udelay(AH_TIME_QUANTUM);
184 }
185
186 ath_dbg(ath9k_hw_common(ah), ANY,
187 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
188 timeout, reg, REG_READ(ah, reg), mask, val);
189
190 return false;
191 }
192 EXPORT_SYMBOL(ath9k_hw_wait);
193
194 void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan,
195 int hw_delay)
196 {
197 if (IS_CHAN_B(chan))
198 hw_delay = (4 * hw_delay) / 22;
199 else
200 hw_delay /= 10;
201
202 if (IS_CHAN_HALF_RATE(chan))
203 hw_delay *= 2;
204 else if (IS_CHAN_QUARTER_RATE(chan))
205 hw_delay *= 4;
206
207 udelay(hw_delay + BASE_ACTIVATE_DELAY);
208 }
209
210 void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array,
211 int column, unsigned int *writecnt)
212 {
213 int r;
214
215 ENABLE_REGWRITE_BUFFER(ah);
216 for (r = 0; r < array->ia_rows; r++) {
217 REG_WRITE(ah, INI_RA(array, r, 0),
218 INI_RA(array, r, column));
219 DO_DELAY(*writecnt);
220 }
221 REGWRITE_BUFFER_FLUSH(ah);
222 }
223
224 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
225 {
226 u32 retval;
227 int i;
228
229 for (i = 0, retval = 0; i < n; i++) {
230 retval = (retval << 1) | (val & 1);
231 val >>= 1;
232 }
233 return retval;
234 }
235
236 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
237 u8 phy, int kbps,
238 u32 frameLen, u16 rateix,
239 bool shortPreamble)
240 {
241 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
242
243 if (kbps == 0)
244 return 0;
245
246 switch (phy) {
247 case WLAN_RC_PHY_CCK:
248 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
249 if (shortPreamble)
250 phyTime >>= 1;
251 numBits = frameLen << 3;
252 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
253 break;
254 case WLAN_RC_PHY_OFDM:
255 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
256 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
257 numBits = OFDM_PLCP_BITS + (frameLen << 3);
258 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
259 txTime = OFDM_SIFS_TIME_QUARTER
260 + OFDM_PREAMBLE_TIME_QUARTER
261 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
262 } else if (ah->curchan &&
263 IS_CHAN_HALF_RATE(ah->curchan)) {
264 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
265 numBits = OFDM_PLCP_BITS + (frameLen << 3);
266 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
267 txTime = OFDM_SIFS_TIME_HALF +
268 OFDM_PREAMBLE_TIME_HALF
269 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
270 } else {
271 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
272 numBits = OFDM_PLCP_BITS + (frameLen << 3);
273 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
274 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
275 + (numSymbols * OFDM_SYMBOL_TIME);
276 }
277 break;
278 default:
279 ath_err(ath9k_hw_common(ah),
280 "Unknown phy %u (rate ix %u)\n", phy, rateix);
281 txTime = 0;
282 break;
283 }
284
285 return txTime;
286 }
287 EXPORT_SYMBOL(ath9k_hw_computetxtime);
288
289 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
290 struct ath9k_channel *chan,
291 struct chan_centers *centers)
292 {
293 int8_t extoff;
294
295 if (!IS_CHAN_HT40(chan)) {
296 centers->ctl_center = centers->ext_center =
297 centers->synth_center = chan->channel;
298 return;
299 }
300
301 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
302 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
303 centers->synth_center =
304 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
305 extoff = 1;
306 } else {
307 centers->synth_center =
308 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
309 extoff = -1;
310 }
311
312 centers->ctl_center =
313 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
314 /* 25 MHz spacing is supported by hw but not on upper layers */
315 centers->ext_center =
316 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
317 }
318
319 /******************/
320 /* Chip Revisions */
321 /******************/
322
323 static void ath9k_hw_read_revisions(struct ath_hw *ah)
324 {
325 u32 val;
326
327 switch (ah->hw_version.devid) {
328 case AR5416_AR9100_DEVID:
329 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
330 break;
331 case AR9300_DEVID_AR9330:
332 ah->hw_version.macVersion = AR_SREV_VERSION_9330;
333 if (ah->get_mac_revision) {
334 ah->hw_version.macRev = ah->get_mac_revision();
335 } else {
336 val = REG_READ(ah, AR_SREV);
337 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
338 }
339 return;
340 case AR9300_DEVID_AR9340:
341 ah->hw_version.macVersion = AR_SREV_VERSION_9340;
342 val = REG_READ(ah, AR_SREV);
343 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
344 return;
345 }
346
347 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
348
349 if (val == 0xFF) {
350 val = REG_READ(ah, AR_SREV);
351 ah->hw_version.macVersion =
352 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
353 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
354
355 if (AR_SREV_9462(ah))
356 ah->is_pciexpress = true;
357 else
358 ah->is_pciexpress = (val &
359 AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
360 } else {
361 if (!AR_SREV_9100(ah))
362 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
363
364 ah->hw_version.macRev = val & AR_SREV_REVISION;
365
366 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
367 ah->is_pciexpress = true;
368 }
369 }
370
371 /************************************/
372 /* HW Attach, Detach, Init Routines */
373 /************************************/
374
375 static void ath9k_hw_disablepcie(struct ath_hw *ah)
376 {
377 if (!AR_SREV_5416(ah))
378 return;
379
380 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
381 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
382 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
383 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
384 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
385 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
386 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
387 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
388 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
389
390 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
391 }
392
393 static void ath9k_hw_aspm_init(struct ath_hw *ah)
394 {
395 struct ath_common *common = ath9k_hw_common(ah);
396
397 if (common->bus_ops->aspm_init)
398 common->bus_ops->aspm_init(common);
399 }
400
401 /* This should work for all families including legacy */
402 static bool ath9k_hw_chip_test(struct ath_hw *ah)
403 {
404 struct ath_common *common = ath9k_hw_common(ah);
405 u32 regAddr[2] = { AR_STA_ID0 };
406 u32 regHold[2];
407 static const u32 patternData[4] = {
408 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
409 };
410 int i, j, loop_max;
411
412 if (!AR_SREV_9300_20_OR_LATER(ah)) {
413 loop_max = 2;
414 regAddr[1] = AR_PHY_BASE + (8 << 2);
415 } else
416 loop_max = 1;
417
418 for (i = 0; i < loop_max; i++) {
419 u32 addr = regAddr[i];
420 u32 wrData, rdData;
421
422 regHold[i] = REG_READ(ah, addr);
423 for (j = 0; j < 0x100; j++) {
424 wrData = (j << 16) | j;
425 REG_WRITE(ah, addr, wrData);
426 rdData = REG_READ(ah, addr);
427 if (rdData != wrData) {
428 ath_err(common,
429 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
430 addr, wrData, rdData);
431 return false;
432 }
433 }
434 for (j = 0; j < 4; j++) {
435 wrData = patternData[j];
436 REG_WRITE(ah, addr, wrData);
437 rdData = REG_READ(ah, addr);
438 if (wrData != rdData) {
439 ath_err(common,
440 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
441 addr, wrData, rdData);
442 return false;
443 }
444 }
445 REG_WRITE(ah, regAddr[i], regHold[i]);
446 }
447 udelay(100);
448
449 return true;
450 }
451
452 static void ath9k_hw_init_config(struct ath_hw *ah)
453 {
454 int i;
455
456 ah->config.dma_beacon_response_time = 1;
457 ah->config.sw_beacon_response_time = 6;
458 ah->config.additional_swba_backoff = 0;
459 ah->config.ack_6mb = 0x0;
460 ah->config.cwm_ignore_extcca = 0;
461 ah->config.pcie_clock_req = 0;
462 ah->config.pcie_waen = 0;
463 ah->config.analog_shiftreg = 1;
464 ah->config.enable_ani = true;
465
466 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
467 ah->config.spurchans[i][0] = AR_NO_SPUR;
468 ah->config.spurchans[i][1] = AR_NO_SPUR;
469 }
470
471 /* PAPRD needs some more work to be enabled */
472 ah->config.paprd_disable = 1;
473
474 ah->config.rx_intr_mitigation = true;
475 ah->config.pcieSerDesWrite = true;
476
477 /*
478 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
479 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
480 * This means we use it for all AR5416 devices, and the few
481 * minor PCI AR9280 devices out there.
482 *
483 * Serialization is required because these devices do not handle
484 * well the case of two concurrent reads/writes due to the latency
485 * involved. During one read/write another read/write can be issued
486 * on another CPU while the previous read/write may still be working
487 * on our hardware, if we hit this case the hardware poops in a loop.
488 * We prevent this by serializing reads and writes.
489 *
490 * This issue is not present on PCI-Express devices or pre-AR5416
491 * devices (legacy, 802.11abg).
492 */
493 if (num_possible_cpus() > 1)
494 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
495 }
496
497 static void ath9k_hw_init_defaults(struct ath_hw *ah)
498 {
499 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
500
501 regulatory->country_code = CTRY_DEFAULT;
502 regulatory->power_limit = MAX_RATE_POWER;
503
504 ah->hw_version.magic = AR5416_MAGIC;
505 ah->hw_version.subvendorid = 0;
506
507 ah->atim_window = 0;
508 ah->sta_id1_defaults =
509 AR_STA_ID1_CRPT_MIC_ENABLE |
510 AR_STA_ID1_MCAST_KSRCH;
511 if (AR_SREV_9100(ah))
512 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX;
513 ah->slottime = ATH9K_SLOT_TIME_9;
514 ah->globaltxtimeout = (u32) -1;
515 ah->power_mode = ATH9K_PM_UNDEFINED;
516 ah->htc_reset_init = true;
517 }
518
519 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
520 {
521 struct ath_common *common = ath9k_hw_common(ah);
522 u32 sum;
523 int i;
524 u16 eeval;
525 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
526
527 sum = 0;
528 for (i = 0; i < 3; i++) {
529 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
530 sum += eeval;
531 common->macaddr[2 * i] = eeval >> 8;
532 common->macaddr[2 * i + 1] = eeval & 0xff;
533 }
534 if (sum == 0 || sum == 0xffff * 3)
535 return -EADDRNOTAVAIL;
536
537 return 0;
538 }
539
540 static int ath9k_hw_post_init(struct ath_hw *ah)
541 {
542 struct ath_common *common = ath9k_hw_common(ah);
543 int ecode;
544
545 if (common->bus_ops->ath_bus_type != ATH_USB) {
546 if (!ath9k_hw_chip_test(ah))
547 return -ENODEV;
548 }
549
550 if (!AR_SREV_9300_20_OR_LATER(ah)) {
551 ecode = ar9002_hw_rf_claim(ah);
552 if (ecode != 0)
553 return ecode;
554 }
555
556 ecode = ath9k_hw_eeprom_init(ah);
557 if (ecode != 0)
558 return ecode;
559
560 ath_dbg(ath9k_hw_common(ah), CONFIG, "Eeprom VER: %d, REV: %d\n",
561 ah->eep_ops->get_eeprom_ver(ah),
562 ah->eep_ops->get_eeprom_rev(ah));
563
564 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
565 if (ecode) {
566 ath_err(ath9k_hw_common(ah),
567 "Failed allocating banks for external radio\n");
568 ath9k_hw_rf_free_ext_banks(ah);
569 return ecode;
570 }
571
572 if (ah->config.enable_ani) {
573 ath9k_hw_ani_setup(ah);
574 ath9k_hw_ani_init(ah);
575 }
576
577 return 0;
578 }
579
580 static void ath9k_hw_attach_ops(struct ath_hw *ah)
581 {
582 if (AR_SREV_9300_20_OR_LATER(ah))
583 ar9003_hw_attach_ops(ah);
584 else
585 ar9002_hw_attach_ops(ah);
586 }
587
588 /* Called for all hardware families */
589 static int __ath9k_hw_init(struct ath_hw *ah)
590 {
591 struct ath_common *common = ath9k_hw_common(ah);
592 int r = 0;
593
594 ath9k_hw_read_revisions(ah);
595
596 /*
597 * Read back AR_WA into a permanent copy and set bits 14 and 17.
598 * We need to do this to avoid RMW of this register. We cannot
599 * read the reg when chip is asleep.
600 */
601 ah->WARegVal = REG_READ(ah, AR_WA);
602 ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
603 AR_WA_ASPM_TIMER_BASED_DISABLE);
604
605 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
606 ath_err(common, "Couldn't reset chip\n");
607 return -EIO;
608 }
609
610 if (AR_SREV_9462(ah))
611 ah->WARegVal &= ~AR_WA_D3_L1_DISABLE;
612
613 ath9k_hw_init_defaults(ah);
614 ath9k_hw_init_config(ah);
615
616 ath9k_hw_attach_ops(ah);
617
618 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
619 ath_err(common, "Couldn't wakeup chip\n");
620 return -EIO;
621 }
622
623 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
624 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
625 ((AR_SREV_9160(ah) || AR_SREV_9280(ah)) &&
626 !ah->is_pciexpress)) {
627 ah->config.serialize_regmode =
628 SER_REG_MODE_ON;
629 } else {
630 ah->config.serialize_regmode =
631 SER_REG_MODE_OFF;
632 }
633 }
634
635 ath_dbg(common, RESET, "serialize_regmode is %d\n",
636 ah->config.serialize_regmode);
637
638 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
639 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
640 else
641 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
642
643 switch (ah->hw_version.macVersion) {
644 case AR_SREV_VERSION_5416_PCI:
645 case AR_SREV_VERSION_5416_PCIE:
646 case AR_SREV_VERSION_9160:
647 case AR_SREV_VERSION_9100:
648 case AR_SREV_VERSION_9280:
649 case AR_SREV_VERSION_9285:
650 case AR_SREV_VERSION_9287:
651 case AR_SREV_VERSION_9271:
652 case AR_SREV_VERSION_9300:
653 case AR_SREV_VERSION_9330:
654 case AR_SREV_VERSION_9485:
655 case AR_SREV_VERSION_9340:
656 case AR_SREV_VERSION_9462:
657 break;
658 default:
659 ath_err(common,
660 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
661 ah->hw_version.macVersion, ah->hw_version.macRev);
662 return -EOPNOTSUPP;
663 }
664
665 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) ||
666 AR_SREV_9330(ah))
667 ah->is_pciexpress = false;
668
669 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
670 ath9k_hw_init_cal_settings(ah);
671
672 ah->ani_function = ATH9K_ANI_ALL;
673 if (AR_SREV_9280_20_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
674 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
675 if (!AR_SREV_9300_20_OR_LATER(ah))
676 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
677
678 /* disable ANI for 9340 */
679 if (AR_SREV_9340(ah))
680 ah->config.enable_ani = false;
681
682 ath9k_hw_init_mode_regs(ah);
683
684 if (!ah->is_pciexpress)
685 ath9k_hw_disablepcie(ah);
686
687 r = ath9k_hw_post_init(ah);
688 if (r)
689 return r;
690
691 ath9k_hw_init_mode_gain_regs(ah);
692 r = ath9k_hw_fill_cap_info(ah);
693 if (r)
694 return r;
695
696 if (ah->is_pciexpress)
697 ath9k_hw_aspm_init(ah);
698
699 r = ath9k_hw_init_macaddr(ah);
700 if (r) {
701 ath_err(common, "Failed to initialize MAC address\n");
702 return r;
703 }
704
705 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
706 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
707 else
708 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
709
710 if (AR_SREV_9330(ah))
711 ah->bb_watchdog_timeout_ms = 85;
712 else
713 ah->bb_watchdog_timeout_ms = 25;
714
715 common->state = ATH_HW_INITIALIZED;
716
717 return 0;
718 }
719
720 int ath9k_hw_init(struct ath_hw *ah)
721 {
722 int ret;
723 struct ath_common *common = ath9k_hw_common(ah);
724
725 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
726 switch (ah->hw_version.devid) {
727 case AR5416_DEVID_PCI:
728 case AR5416_DEVID_PCIE:
729 case AR5416_AR9100_DEVID:
730 case AR9160_DEVID_PCI:
731 case AR9280_DEVID_PCI:
732 case AR9280_DEVID_PCIE:
733 case AR9285_DEVID_PCIE:
734 case AR9287_DEVID_PCI:
735 case AR9287_DEVID_PCIE:
736 case AR2427_DEVID_PCIE:
737 case AR9300_DEVID_PCIE:
738 case AR9300_DEVID_AR9485_PCIE:
739 case AR9300_DEVID_AR9330:
740 case AR9300_DEVID_AR9340:
741 case AR9300_DEVID_AR9580:
742 case AR9300_DEVID_AR9462:
743 break;
744 default:
745 if (common->bus_ops->ath_bus_type == ATH_USB)
746 break;
747 ath_err(common, "Hardware device ID 0x%04x not supported\n",
748 ah->hw_version.devid);
749 return -EOPNOTSUPP;
750 }
751
752 ret = __ath9k_hw_init(ah);
753 if (ret) {
754 ath_err(common,
755 "Unable to initialize hardware; initialization status: %d\n",
756 ret);
757 return ret;
758 }
759
760 return 0;
761 }
762 EXPORT_SYMBOL(ath9k_hw_init);
763
764 static void ath9k_hw_init_qos(struct ath_hw *ah)
765 {
766 ENABLE_REGWRITE_BUFFER(ah);
767
768 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
769 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
770
771 REG_WRITE(ah, AR_QOS_NO_ACK,
772 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
773 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
774 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
775
776 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
777 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
778 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
779 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
780 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
781
782 REGWRITE_BUFFER_FLUSH(ah);
783 }
784
785 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
786 {
787 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
788 udelay(100);
789 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
790
791 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0)
792 udelay(100);
793
794 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
795 }
796 EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc);
797
798 static void ath9k_hw_init_pll(struct ath_hw *ah,
799 struct ath9k_channel *chan)
800 {
801 u32 pll;
802
803 if (AR_SREV_9485(ah)) {
804
805 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */
806 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
807 AR_CH0_BB_DPLL2_PLL_PWD, 0x1);
808 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
809 AR_CH0_DPLL2_KD, 0x40);
810 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
811 AR_CH0_DPLL2_KI, 0x4);
812
813 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
814 AR_CH0_BB_DPLL1_REFDIV, 0x5);
815 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
816 AR_CH0_BB_DPLL1_NINI, 0x58);
817 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
818 AR_CH0_BB_DPLL1_NFRAC, 0x0);
819
820 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
821 AR_CH0_BB_DPLL2_OUTDIV, 0x1);
822 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
823 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1);
824 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
825 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1);
826
827 /* program BB PLL phase_shift to 0x6 */
828 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
829 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6);
830
831 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
832 AR_CH0_BB_DPLL2_PLL_PWD, 0x0);
833 udelay(1000);
834 } else if (AR_SREV_9330(ah)) {
835 u32 ddr_dpll2, pll_control2, kd;
836
837 if (ah->is_clk_25mhz) {
838 ddr_dpll2 = 0x18e82f01;
839 pll_control2 = 0xe04a3d;
840 kd = 0x1d;
841 } else {
842 ddr_dpll2 = 0x19e82f01;
843 pll_control2 = 0x886666;
844 kd = 0x3d;
845 }
846
847 /* program DDR PLL ki and kd value */
848 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2);
849
850 /* program DDR PLL phase_shift */
851 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3,
852 AR_CH0_DPLL3_PHASE_SHIFT, 0x1);
853
854 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
855 udelay(1000);
856
857 /* program refdiv, nint, frac to RTC register */
858 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2);
859
860 /* program BB PLL kd and ki value */
861 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd);
862 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06);
863
864 /* program BB PLL phase_shift */
865 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
866 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1);
867 } else if (AR_SREV_9340(ah)) {
868 u32 regval, pll2_divint, pll2_divfrac, refdiv;
869
870 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
871 udelay(1000);
872
873 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16);
874 udelay(100);
875
876 if (ah->is_clk_25mhz) {
877 pll2_divint = 0x54;
878 pll2_divfrac = 0x1eb85;
879 refdiv = 3;
880 } else {
881 pll2_divint = 88;
882 pll2_divfrac = 0;
883 refdiv = 5;
884 }
885
886 regval = REG_READ(ah, AR_PHY_PLL_MODE);
887 regval |= (0x1 << 16);
888 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
889 udelay(100);
890
891 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) |
892 (pll2_divint << 18) | pll2_divfrac);
893 udelay(100);
894
895 regval = REG_READ(ah, AR_PHY_PLL_MODE);
896 regval = (regval & 0x80071fff) | (0x1 << 30) | (0x1 << 13) |
897 (0x4 << 26) | (0x18 << 19);
898 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
899 REG_WRITE(ah, AR_PHY_PLL_MODE,
900 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff);
901 udelay(1000);
902 }
903
904 pll = ath9k_hw_compute_pll_control(ah, chan);
905
906 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
907
908 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah))
909 udelay(1000);
910
911 /* Switch the core clock for ar9271 to 117Mhz */
912 if (AR_SREV_9271(ah)) {
913 udelay(500);
914 REG_WRITE(ah, 0x50040, 0x304);
915 }
916
917 udelay(RTC_PLL_SETTLE_DELAY);
918
919 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
920
921 if (AR_SREV_9340(ah)) {
922 if (ah->is_clk_25mhz) {
923 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1);
924 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);
925 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae);
926 } else {
927 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1);
928 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400);
929 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800);
930 }
931 udelay(100);
932 }
933 }
934
935 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
936 enum nl80211_iftype opmode)
937 {
938 u32 sync_default = AR_INTR_SYNC_DEFAULT;
939 u32 imr_reg = AR_IMR_TXERR |
940 AR_IMR_TXURN |
941 AR_IMR_RXERR |
942 AR_IMR_RXORN |
943 AR_IMR_BCNMISC;
944
945 if (AR_SREV_9340(ah))
946 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
947
948 if (AR_SREV_9300_20_OR_LATER(ah)) {
949 imr_reg |= AR_IMR_RXOK_HP;
950 if (ah->config.rx_intr_mitigation)
951 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
952 else
953 imr_reg |= AR_IMR_RXOK_LP;
954
955 } else {
956 if (ah->config.rx_intr_mitigation)
957 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
958 else
959 imr_reg |= AR_IMR_RXOK;
960 }
961
962 if (ah->config.tx_intr_mitigation)
963 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
964 else
965 imr_reg |= AR_IMR_TXOK;
966
967 if (opmode == NL80211_IFTYPE_AP)
968 imr_reg |= AR_IMR_MIB;
969
970 ENABLE_REGWRITE_BUFFER(ah);
971
972 REG_WRITE(ah, AR_IMR, imr_reg);
973 ah->imrs2_reg |= AR_IMR_S2_GTT;
974 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
975
976 if (!AR_SREV_9100(ah)) {
977 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
978 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
979 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
980 }
981
982 REGWRITE_BUFFER_FLUSH(ah);
983
984 if (AR_SREV_9300_20_OR_LATER(ah)) {
985 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
986 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
987 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
988 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
989 }
990 }
991
992 static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us)
993 {
994 u32 val = ath9k_hw_mac_to_clks(ah, us - 2);
995 val = min(val, (u32) 0xFFFF);
996 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val);
997 }
998
999 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
1000 {
1001 u32 val = ath9k_hw_mac_to_clks(ah, us);
1002 val = min(val, (u32) 0xFFFF);
1003 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
1004 }
1005
1006 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1007 {
1008 u32 val = ath9k_hw_mac_to_clks(ah, us);
1009 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
1010 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
1011 }
1012
1013 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1014 {
1015 u32 val = ath9k_hw_mac_to_clks(ah, us);
1016 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
1017 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
1018 }
1019
1020 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1021 {
1022 if (tu > 0xFFFF) {
1023 ath_dbg(ath9k_hw_common(ah), XMIT, "bad global tx timeout %u\n",
1024 tu);
1025 ah->globaltxtimeout = (u32) -1;
1026 return false;
1027 } else {
1028 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1029 ah->globaltxtimeout = tu;
1030 return true;
1031 }
1032 }
1033
1034 void ath9k_hw_init_global_settings(struct ath_hw *ah)
1035 {
1036 struct ath_common *common = ath9k_hw_common(ah);
1037 struct ieee80211_conf *conf = &common->hw->conf;
1038 const struct ath9k_channel *chan = ah->curchan;
1039 int acktimeout, ctstimeout, ack_offset = 0;
1040 int slottime;
1041 int sifstime;
1042 int rx_lat = 0, tx_lat = 0, eifs = 0;
1043 u32 reg;
1044
1045 ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n",
1046 ah->misc_mode);
1047
1048 if (!chan)
1049 return;
1050
1051 if (ah->misc_mode != 0)
1052 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode);
1053
1054 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1055 rx_lat = 41;
1056 else
1057 rx_lat = 37;
1058 tx_lat = 54;
1059
1060 if (IS_CHAN_5GHZ(chan))
1061 sifstime = 16;
1062 else
1063 sifstime = 10;
1064
1065 if (IS_CHAN_HALF_RATE(chan)) {
1066 eifs = 175;
1067 rx_lat *= 2;
1068 tx_lat *= 2;
1069 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1070 tx_lat += 11;
1071
1072 sifstime *= 2;
1073 ack_offset = 16;
1074 slottime = 13;
1075 } else if (IS_CHAN_QUARTER_RATE(chan)) {
1076 eifs = 340;
1077 rx_lat = (rx_lat * 4) - 1;
1078 tx_lat *= 4;
1079 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1080 tx_lat += 22;
1081
1082 sifstime *= 4;
1083 ack_offset = 32;
1084 slottime = 21;
1085 } else {
1086 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1087 eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO;
1088 reg = AR_USEC_ASYNC_FIFO;
1089 } else {
1090 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/
1091 common->clockrate;
1092 reg = REG_READ(ah, AR_USEC);
1093 }
1094 rx_lat = MS(reg, AR_USEC_RX_LAT);
1095 tx_lat = MS(reg, AR_USEC_TX_LAT);
1096
1097 slottime = ah->slottime;
1098 }
1099
1100 /* As defined by IEEE 802.11-2007 17.3.8.6 */
1101 acktimeout = slottime + sifstime + 3 * ah->coverage_class + ack_offset;
1102 ctstimeout = acktimeout;
1103
1104 /*
1105 * Workaround for early ACK timeouts, add an offset to match the
1106 * initval's 64us ack timeout value. Use 48us for the CTS timeout.
1107 * This was initially only meant to work around an issue with delayed
1108 * BA frames in some implementations, but it has been found to fix ACK
1109 * timeout issues in other cases as well.
1110 */
1111 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ &&
1112 !IS_CHAN_HALF_RATE(chan) && !IS_CHAN_QUARTER_RATE(chan)) {
1113 acktimeout += 64 - sifstime - ah->slottime;
1114 ctstimeout += 48 - sifstime - ah->slottime;
1115 }
1116
1117
1118 ath9k_hw_set_sifs_time(ah, sifstime);
1119 ath9k_hw_setslottime(ah, slottime);
1120 ath9k_hw_set_ack_timeout(ah, acktimeout);
1121 ath9k_hw_set_cts_timeout(ah, ctstimeout);
1122 if (ah->globaltxtimeout != (u32) -1)
1123 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1124
1125 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs));
1126 REG_RMW(ah, AR_USEC,
1127 (common->clockrate - 1) |
1128 SM(rx_lat, AR_USEC_RX_LAT) |
1129 SM(tx_lat, AR_USEC_TX_LAT),
1130 AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC);
1131
1132 }
1133 EXPORT_SYMBOL(ath9k_hw_init_global_settings);
1134
1135 void ath9k_hw_deinit(struct ath_hw *ah)
1136 {
1137 struct ath_common *common = ath9k_hw_common(ah);
1138
1139 if (common->state < ATH_HW_INITIALIZED)
1140 goto free_hw;
1141
1142 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1143
1144 free_hw:
1145 ath9k_hw_rf_free_ext_banks(ah);
1146 }
1147 EXPORT_SYMBOL(ath9k_hw_deinit);
1148
1149 /*******/
1150 /* INI */
1151 /*******/
1152
1153 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
1154 {
1155 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1156
1157 if (IS_CHAN_B(chan))
1158 ctl |= CTL_11B;
1159 else if (IS_CHAN_G(chan))
1160 ctl |= CTL_11G;
1161 else
1162 ctl |= CTL_11A;
1163
1164 return ctl;
1165 }
1166
1167 /****************************************/
1168 /* Reset and Channel Switching Routines */
1169 /****************************************/
1170
1171 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1172 {
1173 struct ath_common *common = ath9k_hw_common(ah);
1174
1175 ENABLE_REGWRITE_BUFFER(ah);
1176
1177 /*
1178 * set AHB_MODE not to do cacheline prefetches
1179 */
1180 if (!AR_SREV_9300_20_OR_LATER(ah))
1181 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
1182
1183 /*
1184 * let mac dma reads be in 128 byte chunks
1185 */
1186 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK);
1187
1188 REGWRITE_BUFFER_FLUSH(ah);
1189
1190 /*
1191 * Restore TX Trigger Level to its pre-reset value.
1192 * The initial value depends on whether aggregation is enabled, and is
1193 * adjusted whenever underruns are detected.
1194 */
1195 if (!AR_SREV_9300_20_OR_LATER(ah))
1196 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1197
1198 ENABLE_REGWRITE_BUFFER(ah);
1199
1200 /*
1201 * let mac dma writes be in 128 byte chunks
1202 */
1203 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK);
1204
1205 /*
1206 * Setup receive FIFO threshold to hold off TX activities
1207 */
1208 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1209
1210 if (AR_SREV_9300_20_OR_LATER(ah)) {
1211 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
1212 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
1213
1214 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
1215 ah->caps.rx_status_len);
1216 }
1217
1218 /*
1219 * reduce the number of usable entries in PCU TXBUF to avoid
1220 * wrap around issues.
1221 */
1222 if (AR_SREV_9285(ah)) {
1223 /* For AR9285 the number of Fifos are reduced to half.
1224 * So set the usable tx buf size also to half to
1225 * avoid data/delimiter underruns
1226 */
1227 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1228 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1229 } else if (!AR_SREV_9271(ah)) {
1230 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1231 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1232 }
1233
1234 REGWRITE_BUFFER_FLUSH(ah);
1235
1236 if (AR_SREV_9300_20_OR_LATER(ah))
1237 ath9k_hw_reset_txstatus_ring(ah);
1238 }
1239
1240 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1241 {
1242 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC;
1243 u32 set = AR_STA_ID1_KSRCH_MODE;
1244
1245 switch (opmode) {
1246 case NL80211_IFTYPE_ADHOC:
1247 case NL80211_IFTYPE_MESH_POINT:
1248 set |= AR_STA_ID1_ADHOC;
1249 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1250 break;
1251 case NL80211_IFTYPE_AP:
1252 set |= AR_STA_ID1_STA_AP;
1253 /* fall through */
1254 case NL80211_IFTYPE_STATION:
1255 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1256 break;
1257 default:
1258 if (!ah->is_monitoring)
1259 set = 0;
1260 break;
1261 }
1262 REG_RMW(ah, AR_STA_ID1, set, mask);
1263 }
1264
1265 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1266 u32 *coef_mantissa, u32 *coef_exponent)
1267 {
1268 u32 coef_exp, coef_man;
1269
1270 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1271 if ((coef_scaled >> coef_exp) & 0x1)
1272 break;
1273
1274 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1275
1276 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1277
1278 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1279 *coef_exponent = coef_exp - 16;
1280 }
1281
1282 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1283 {
1284 u32 rst_flags;
1285 u32 tmpReg;
1286
1287 if (AR_SREV_9100(ah)) {
1288 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK,
1289 AR_RTC_DERIVED_CLK_PERIOD, 1);
1290 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1291 }
1292
1293 ENABLE_REGWRITE_BUFFER(ah);
1294
1295 if (AR_SREV_9300_20_OR_LATER(ah)) {
1296 REG_WRITE(ah, AR_WA, ah->WARegVal);
1297 udelay(10);
1298 }
1299
1300 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1301 AR_RTC_FORCE_WAKE_ON_INT);
1302
1303 if (AR_SREV_9100(ah)) {
1304 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1305 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1306 } else {
1307 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1308 if (tmpReg &
1309 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1310 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1311 u32 val;
1312 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1313
1314 val = AR_RC_HOSTIF;
1315 if (!AR_SREV_9300_20_OR_LATER(ah))
1316 val |= AR_RC_AHB;
1317 REG_WRITE(ah, AR_RC, val);
1318
1319 } else if (!AR_SREV_9300_20_OR_LATER(ah))
1320 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1321
1322 rst_flags = AR_RTC_RC_MAC_WARM;
1323 if (type == ATH9K_RESET_COLD)
1324 rst_flags |= AR_RTC_RC_MAC_COLD;
1325 }
1326
1327 if (AR_SREV_9330(ah)) {
1328 int npend = 0;
1329 int i;
1330
1331 /* AR9330 WAR:
1332 * call external reset function to reset WMAC if:
1333 * - doing a cold reset
1334 * - we have pending frames in the TX queues
1335 */
1336
1337 for (i = 0; i < AR_NUM_QCU; i++) {
1338 npend = ath9k_hw_numtxpending(ah, i);
1339 if (npend)
1340 break;
1341 }
1342
1343 if (ah->external_reset &&
1344 (npend || type == ATH9K_RESET_COLD)) {
1345 int reset_err = 0;
1346
1347 ath_dbg(ath9k_hw_common(ah), RESET,
1348 "reset MAC via external reset\n");
1349
1350 reset_err = ah->external_reset();
1351 if (reset_err) {
1352 ath_err(ath9k_hw_common(ah),
1353 "External reset failed, err=%d\n",
1354 reset_err);
1355 return false;
1356 }
1357
1358 REG_WRITE(ah, AR_RTC_RESET, 1);
1359 }
1360 }
1361
1362 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1363
1364 REGWRITE_BUFFER_FLUSH(ah);
1365
1366 udelay(50);
1367
1368 REG_WRITE(ah, AR_RTC_RC, 0);
1369 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1370 ath_dbg(ath9k_hw_common(ah), RESET, "RTC stuck in MAC reset\n");
1371 return false;
1372 }
1373
1374 if (!AR_SREV_9100(ah))
1375 REG_WRITE(ah, AR_RC, 0);
1376
1377 if (AR_SREV_9100(ah))
1378 udelay(50);
1379
1380 return true;
1381 }
1382
1383 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1384 {
1385 ENABLE_REGWRITE_BUFFER(ah);
1386
1387 if (AR_SREV_9300_20_OR_LATER(ah)) {
1388 REG_WRITE(ah, AR_WA, ah->WARegVal);
1389 udelay(10);
1390 }
1391
1392 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1393 AR_RTC_FORCE_WAKE_ON_INT);
1394
1395 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1396 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1397
1398 REG_WRITE(ah, AR_RTC_RESET, 0);
1399
1400 REGWRITE_BUFFER_FLUSH(ah);
1401
1402 if (!AR_SREV_9300_20_OR_LATER(ah))
1403 udelay(2);
1404
1405 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1406 REG_WRITE(ah, AR_RC, 0);
1407
1408 REG_WRITE(ah, AR_RTC_RESET, 1);
1409
1410 if (!ath9k_hw_wait(ah,
1411 AR_RTC_STATUS,
1412 AR_RTC_STATUS_M,
1413 AR_RTC_STATUS_ON,
1414 AH_WAIT_TIMEOUT)) {
1415 ath_dbg(ath9k_hw_common(ah), RESET, "RTC not waking up\n");
1416 return false;
1417 }
1418
1419 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1420 }
1421
1422 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1423 {
1424 bool ret = false;
1425
1426 if (AR_SREV_9300_20_OR_LATER(ah)) {
1427 REG_WRITE(ah, AR_WA, ah->WARegVal);
1428 udelay(10);
1429 }
1430
1431 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1432 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1433
1434 switch (type) {
1435 case ATH9K_RESET_POWER_ON:
1436 ret = ath9k_hw_set_reset_power_on(ah);
1437 break;
1438 case ATH9K_RESET_WARM:
1439 case ATH9K_RESET_COLD:
1440 ret = ath9k_hw_set_reset(ah, type);
1441 break;
1442 default:
1443 break;
1444 }
1445
1446 if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI)
1447 REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2);
1448
1449 return ret;
1450 }
1451
1452 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1453 struct ath9k_channel *chan)
1454 {
1455 int reset_type = ATH9K_RESET_WARM;
1456
1457 if (AR_SREV_9280(ah)) {
1458 if (ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1459 reset_type = ATH9K_RESET_POWER_ON;
1460 else
1461 reset_type = ATH9K_RESET_COLD;
1462 }
1463
1464 if (!ath9k_hw_set_reset_reg(ah, reset_type))
1465 return false;
1466
1467 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1468 return false;
1469
1470 ah->chip_fullsleep = false;
1471
1472 if (AR_SREV_9330(ah))
1473 ar9003_hw_internal_regulator_apply(ah);
1474 ath9k_hw_init_pll(ah, chan);
1475 ath9k_hw_set_rfmode(ah, chan);
1476
1477 return true;
1478 }
1479
1480 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1481 struct ath9k_channel *chan)
1482 {
1483 struct ath_common *common = ath9k_hw_common(ah);
1484 u32 qnum;
1485 int r;
1486 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1487 bool band_switch, mode_diff;
1488 u8 ini_reloaded;
1489
1490 band_switch = (chan->channelFlags & (CHANNEL_2GHZ | CHANNEL_5GHZ)) !=
1491 (ah->curchan->channelFlags & (CHANNEL_2GHZ |
1492 CHANNEL_5GHZ));
1493 mode_diff = (chan->chanmode != ah->curchan->chanmode);
1494
1495 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1496 if (ath9k_hw_numtxpending(ah, qnum)) {
1497 ath_dbg(common, QUEUE,
1498 "Transmit frames pending on queue %d\n", qnum);
1499 return false;
1500 }
1501 }
1502
1503 if (!ath9k_hw_rfbus_req(ah)) {
1504 ath_err(common, "Could not kill baseband RX\n");
1505 return false;
1506 }
1507
1508 if (edma && (band_switch || mode_diff)) {
1509 ath9k_hw_mark_phy_inactive(ah);
1510 udelay(5);
1511
1512 ath9k_hw_init_pll(ah, NULL);
1513
1514 if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) {
1515 ath_err(common, "Failed to do fast channel change\n");
1516 return false;
1517 }
1518 }
1519
1520 ath9k_hw_set_channel_regs(ah, chan);
1521
1522 r = ath9k_hw_rf_set_freq(ah, chan);
1523 if (r) {
1524 ath_err(common, "Failed to set channel\n");
1525 return false;
1526 }
1527 ath9k_hw_set_clockrate(ah);
1528 ath9k_hw_apply_txpower(ah, chan, false);
1529 ath9k_hw_rfbus_done(ah);
1530
1531 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1532 ath9k_hw_set_delta_slope(ah, chan);
1533
1534 ath9k_hw_spur_mitigate_freq(ah, chan);
1535
1536 if (edma && (band_switch || mode_diff)) {
1537 ah->ah_flags |= AH_FASTCC;
1538 if (band_switch || ini_reloaded)
1539 ah->eep_ops->set_board_values(ah, chan);
1540
1541 ath9k_hw_init_bb(ah, chan);
1542
1543 if (band_switch || ini_reloaded)
1544 ath9k_hw_init_cal(ah, chan);
1545 ah->ah_flags &= ~AH_FASTCC;
1546 }
1547
1548 return true;
1549 }
1550
1551 static void ath9k_hw_apply_gpio_override(struct ath_hw *ah)
1552 {
1553 u32 gpio_mask = ah->gpio_mask;
1554 int i;
1555
1556 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) {
1557 if (!(gpio_mask & 1))
1558 continue;
1559
1560 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1561 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i)));
1562 }
1563 }
1564
1565 static bool ath9k_hw_check_dcs(u32 dma_dbg, u32 num_dcu_states,
1566 int *hang_state, int *hang_pos)
1567 {
1568 static u32 dcu_chain_state[] = {5, 6, 9}; /* DCU chain stuck states */
1569 u32 chain_state, dcs_pos, i;
1570
1571 for (dcs_pos = 0; dcs_pos < num_dcu_states; dcs_pos++) {
1572 chain_state = (dma_dbg >> (5 * dcs_pos)) & 0x1f;
1573 for (i = 0; i < 3; i++) {
1574 if (chain_state == dcu_chain_state[i]) {
1575 *hang_state = chain_state;
1576 *hang_pos = dcs_pos;
1577 return true;
1578 }
1579 }
1580 }
1581 return false;
1582 }
1583
1584 #define DCU_COMPLETE_STATE 1
1585 #define DCU_COMPLETE_STATE_MASK 0x3
1586 #define NUM_STATUS_READS 50
1587 static bool ath9k_hw_detect_mac_hang(struct ath_hw *ah)
1588 {
1589 u32 chain_state, comp_state, dcs_reg = AR_DMADBG_4;
1590 u32 i, hang_pos, hang_state, num_state = 6;
1591
1592 comp_state = REG_READ(ah, AR_DMADBG_6);
1593
1594 if ((comp_state & DCU_COMPLETE_STATE_MASK) != DCU_COMPLETE_STATE) {
1595 ath_dbg(ath9k_hw_common(ah), RESET,
1596 "MAC Hang signature not found at DCU complete\n");
1597 return false;
1598 }
1599
1600 chain_state = REG_READ(ah, dcs_reg);
1601 if (ath9k_hw_check_dcs(chain_state, num_state, &hang_state, &hang_pos))
1602 goto hang_check_iter;
1603
1604 dcs_reg = AR_DMADBG_5;
1605 num_state = 4;
1606 chain_state = REG_READ(ah, dcs_reg);
1607 if (ath9k_hw_check_dcs(chain_state, num_state, &hang_state, &hang_pos))
1608 goto hang_check_iter;
1609
1610 ath_dbg(ath9k_hw_common(ah), RESET,
1611 "MAC Hang signature 1 not found\n");
1612 return false;
1613
1614 hang_check_iter:
1615 ath_dbg(ath9k_hw_common(ah), RESET,
1616 "DCU registers: chain %08x complete %08x Hang: state %d pos %d\n",
1617 chain_state, comp_state, hang_state, hang_pos);
1618
1619 for (i = 0; i < NUM_STATUS_READS; i++) {
1620 chain_state = REG_READ(ah, dcs_reg);
1621 chain_state = (chain_state >> (5 * hang_pos)) & 0x1f;
1622 comp_state = REG_READ(ah, AR_DMADBG_6);
1623
1624 if (((comp_state & DCU_COMPLETE_STATE_MASK) !=
1625 DCU_COMPLETE_STATE) ||
1626 (chain_state != hang_state))
1627 return false;
1628 }
1629
1630 ath_dbg(ath9k_hw_common(ah), RESET, "MAC Hang signature 1 found\n");
1631
1632 return true;
1633 }
1634
1635 bool ath9k_hw_check_alive(struct ath_hw *ah)
1636 {
1637 int count = 50;
1638 u32 reg;
1639
1640 if (AR_SREV_9300(ah))
1641 return !ath9k_hw_detect_mac_hang(ah);
1642
1643 if (AR_SREV_9285_12_OR_LATER(ah))
1644 return true;
1645
1646 do {
1647 reg = REG_READ(ah, AR_OBS_BUS_1);
1648
1649 if ((reg & 0x7E7FFFEF) == 0x00702400)
1650 continue;
1651
1652 switch (reg & 0x7E000B00) {
1653 case 0x1E000000:
1654 case 0x52000B00:
1655 case 0x18000B00:
1656 continue;
1657 default:
1658 return true;
1659 }
1660 } while (count-- > 0);
1661
1662 return false;
1663 }
1664 EXPORT_SYMBOL(ath9k_hw_check_alive);
1665
1666 /*
1667 * Fast channel change:
1668 * (Change synthesizer based on channel freq without resetting chip)
1669 *
1670 * Don't do FCC when
1671 * - Flag is not set
1672 * - Chip is just coming out of full sleep
1673 * - Channel to be set is same as current channel
1674 * - Channel flags are different, (eg.,moving from 2GHz to 5GHz channel)
1675 */
1676 static int ath9k_hw_do_fastcc(struct ath_hw *ah, struct ath9k_channel *chan)
1677 {
1678 struct ath_common *common = ath9k_hw_common(ah);
1679 int ret;
1680
1681 if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI)
1682 goto fail;
1683
1684 if (ah->chip_fullsleep)
1685 goto fail;
1686
1687 if (!ah->curchan)
1688 goto fail;
1689
1690 if (chan->channel == ah->curchan->channel)
1691 goto fail;
1692
1693 if ((ah->curchan->channelFlags | chan->channelFlags) &
1694 (CHANNEL_HALF | CHANNEL_QUARTER))
1695 goto fail;
1696
1697 if ((chan->channelFlags & CHANNEL_ALL) !=
1698 (ah->curchan->channelFlags & CHANNEL_ALL))
1699 goto fail;
1700
1701 if (!ath9k_hw_check_alive(ah))
1702 goto fail;
1703
1704 /*
1705 * For AR9462, make sure that calibration data for
1706 * re-using are present.
1707 */
1708 if (AR_SREV_9462(ah) && (ah->caldata &&
1709 (!ah->caldata->done_txiqcal_once ||
1710 !ah->caldata->done_txclcal_once ||
1711 !ah->caldata->rtt_done)))
1712 goto fail;
1713
1714 ath_dbg(common, RESET, "FastChannelChange for %d -> %d\n",
1715 ah->curchan->channel, chan->channel);
1716
1717 ret = ath9k_hw_channel_change(ah, chan);
1718 if (!ret)
1719 goto fail;
1720
1721 ath9k_hw_loadnf(ah, ah->curchan);
1722 ath9k_hw_start_nfcal(ah, true);
1723
1724 if ((ah->caps.hw_caps & ATH9K_HW_CAP_MCI) && ar9003_mci_is_ready(ah))
1725 ar9003_mci_2g5g_switch(ah, true);
1726
1727 if (AR_SREV_9271(ah))
1728 ar9002_hw_load_ani_reg(ah, chan);
1729
1730 return 0;
1731 fail:
1732 return -EINVAL;
1733 }
1734
1735 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1736 struct ath9k_hw_cal_data *caldata, bool fastcc)
1737 {
1738 struct ath_common *common = ath9k_hw_common(ah);
1739 u32 saveLedState;
1740 u32 saveDefAntenna;
1741 u32 macStaId1;
1742 u64 tsf = 0;
1743 int i, r;
1744 bool start_mci_reset = false;
1745 bool mci = !!(ah->caps.hw_caps & ATH9K_HW_CAP_MCI);
1746 bool save_fullsleep = ah->chip_fullsleep;
1747
1748 if (mci) {
1749 start_mci_reset = ar9003_mci_start_reset(ah, chan);
1750 if (start_mci_reset)
1751 return 0;
1752 }
1753
1754 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1755 return -EIO;
1756
1757 if (ah->curchan && !ah->chip_fullsleep)
1758 ath9k_hw_getnf(ah, ah->curchan);
1759
1760 ah->caldata = caldata;
1761 if (caldata &&
1762 (chan->channel != caldata->channel ||
1763 (chan->channelFlags & ~CHANNEL_CW_INT) !=
1764 (caldata->channelFlags & ~CHANNEL_CW_INT))) {
1765 /* Operating channel changed, reset channel calibration data */
1766 memset(caldata, 0, sizeof(*caldata));
1767 ath9k_init_nfcal_hist_buffer(ah, chan);
1768 }
1769 ah->noise = ath9k_hw_getchan_noise(ah, chan);
1770
1771 if (fastcc) {
1772 r = ath9k_hw_do_fastcc(ah, chan);
1773 if (!r)
1774 return r;
1775 }
1776
1777 if (mci)
1778 ar9003_mci_stop_bt(ah, save_fullsleep);
1779
1780 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1781 if (saveDefAntenna == 0)
1782 saveDefAntenna = 1;
1783
1784 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1785
1786 /* For chips on which RTC reset is done, save TSF before it gets cleared */
1787 if (AR_SREV_9100(ah) ||
1788 (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)))
1789 tsf = ath9k_hw_gettsf64(ah);
1790
1791 saveLedState = REG_READ(ah, AR_CFG_LED) &
1792 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1793 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1794
1795 ath9k_hw_mark_phy_inactive(ah);
1796
1797 ah->paprd_table_write_done = false;
1798
1799 /* Only required on the first reset */
1800 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1801 REG_WRITE(ah,
1802 AR9271_RESET_POWER_DOWN_CONTROL,
1803 AR9271_RADIO_RF_RST);
1804 udelay(50);
1805 }
1806
1807 if (!ath9k_hw_chip_reset(ah, chan)) {
1808 ath_err(common, "Chip reset failed\n");
1809 return -EINVAL;
1810 }
1811
1812 /* Only required on the first reset */
1813 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1814 ah->htc_reset_init = false;
1815 REG_WRITE(ah,
1816 AR9271_RESET_POWER_DOWN_CONTROL,
1817 AR9271_GATE_MAC_CTL);
1818 udelay(50);
1819 }
1820
1821 /* Restore TSF */
1822 if (tsf)
1823 ath9k_hw_settsf64(ah, tsf);
1824
1825 if (AR_SREV_9280_20_OR_LATER(ah))
1826 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1827
1828 if (!AR_SREV_9300_20_OR_LATER(ah))
1829 ar9002_hw_enable_async_fifo(ah);
1830
1831 r = ath9k_hw_process_ini(ah, chan);
1832 if (r)
1833 return r;
1834
1835 if (mci)
1836 ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep);
1837
1838 /*
1839 * Some AR91xx SoC devices frequently fail to accept TSF writes
1840 * right after the chip reset. When that happens, write a new
1841 * value after the initvals have been applied, with an offset
1842 * based on measured time difference
1843 */
1844 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
1845 tsf += 1500;
1846 ath9k_hw_settsf64(ah, tsf);
1847 }
1848
1849 /* Setup MFP options for CCMP */
1850 if (AR_SREV_9280_20_OR_LATER(ah)) {
1851 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1852 * frames when constructing CCMP AAD. */
1853 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1854 0xc7ff);
1855 ah->sw_mgmt_crypto = false;
1856 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1857 /* Disable hardware crypto for management frames */
1858 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1859 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1860 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1861 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1862 ah->sw_mgmt_crypto = true;
1863 } else
1864 ah->sw_mgmt_crypto = true;
1865
1866 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1867 ath9k_hw_set_delta_slope(ah, chan);
1868
1869 ath9k_hw_spur_mitigate_freq(ah, chan);
1870 ah->eep_ops->set_board_values(ah, chan);
1871
1872 ENABLE_REGWRITE_BUFFER(ah);
1873
1874 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
1875 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
1876 | macStaId1
1877 | AR_STA_ID1_RTS_USE_DEF
1878 | (ah->config.
1879 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
1880 | ah->sta_id1_defaults);
1881 ath_hw_setbssidmask(common);
1882 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1883 ath9k_hw_write_associd(ah);
1884 REG_WRITE(ah, AR_ISR, ~0);
1885 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1886
1887 REGWRITE_BUFFER_FLUSH(ah);
1888
1889 ath9k_hw_set_operating_mode(ah, ah->opmode);
1890
1891 r = ath9k_hw_rf_set_freq(ah, chan);
1892 if (r)
1893 return r;
1894
1895 ath9k_hw_set_clockrate(ah);
1896
1897 ENABLE_REGWRITE_BUFFER(ah);
1898
1899 for (i = 0; i < AR_NUM_DCU; i++)
1900 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1901
1902 REGWRITE_BUFFER_FLUSH(ah);
1903
1904 ah->intr_txqs = 0;
1905 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1906 ath9k_hw_resettxqueue(ah, i);
1907
1908 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
1909 ath9k_hw_ani_cache_ini_regs(ah);
1910 ath9k_hw_init_qos(ah);
1911
1912 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1913 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
1914
1915 ath9k_hw_init_global_settings(ah);
1916
1917 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1918 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
1919 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
1920 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
1921 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
1922 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1923 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
1924 }
1925
1926 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
1927
1928 ath9k_hw_set_dma(ah);
1929
1930 REG_WRITE(ah, AR_OBS, 8);
1931
1932 if (ah->config.rx_intr_mitigation) {
1933 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
1934 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
1935 }
1936
1937 if (ah->config.tx_intr_mitigation) {
1938 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1939 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1940 }
1941
1942 ath9k_hw_init_bb(ah, chan);
1943
1944 if (caldata) {
1945 caldata->done_txiqcal_once = false;
1946 caldata->done_txclcal_once = false;
1947 }
1948 if (!ath9k_hw_init_cal(ah, chan))
1949 return -EIO;
1950
1951 ath9k_hw_loadnf(ah, chan);
1952 ath9k_hw_start_nfcal(ah, true);
1953
1954 if (mci && ar9003_mci_end_reset(ah, chan, caldata))
1955 return -EIO;
1956
1957 ENABLE_REGWRITE_BUFFER(ah);
1958
1959 ath9k_hw_restore_chainmask(ah);
1960 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1961
1962 REGWRITE_BUFFER_FLUSH(ah);
1963
1964 /*
1965 * For big endian systems turn on swapping for descriptors
1966 */
1967 if (AR_SREV_9100(ah)) {
1968 u32 mask;
1969 mask = REG_READ(ah, AR_CFG);
1970 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1971 ath_dbg(common, RESET, "CFG Byte Swap Set 0x%x\n",
1972 mask);
1973 } else {
1974 mask =
1975 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1976 REG_WRITE(ah, AR_CFG, mask);
1977 ath_dbg(common, RESET, "Setting CFG 0x%x\n",
1978 REG_READ(ah, AR_CFG));
1979 }
1980 } else {
1981 if (common->bus_ops->ath_bus_type == ATH_USB) {
1982 /* Configure AR9271 target WLAN */
1983 if (AR_SREV_9271(ah))
1984 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1985 else
1986 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1987 }
1988 #ifdef __BIG_ENDIAN
1989 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah))
1990 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0);
1991 else
1992 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1993 #endif
1994 }
1995
1996 if (ath9k_hw_btcoex_is_enabled(ah))
1997 ath9k_hw_btcoex_enable(ah);
1998
1999 if (mci)
2000 ar9003_mci_check_bt(ah);
2001
2002 if (AR_SREV_9300_20_OR_LATER(ah)) {
2003 ar9003_hw_bb_watchdog_config(ah);
2004
2005 ar9003_hw_disable_phy_restart(ah);
2006 }
2007
2008 ath9k_hw_apply_gpio_override(ah);
2009
2010 return 0;
2011 }
2012 EXPORT_SYMBOL(ath9k_hw_reset);
2013
2014 /******************************/
2015 /* Power Management (Chipset) */
2016 /******************************/
2017
2018 /*
2019 * Notify Power Mgt is disabled in self-generated frames.
2020 * If requested, force chip to sleep.
2021 */
2022 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
2023 {
2024 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2025 if (setChip) {
2026 if (AR_SREV_9462(ah)) {
2027 REG_WRITE(ah, AR_TIMER_MODE,
2028 REG_READ(ah, AR_TIMER_MODE) & 0xFFFFFF00);
2029 REG_WRITE(ah, AR_NDP2_TIMER_MODE, REG_READ(ah,
2030 AR_NDP2_TIMER_MODE) & 0xFFFFFF00);
2031 REG_WRITE(ah, AR_SLP32_INC,
2032 REG_READ(ah, AR_SLP32_INC) & 0xFFF00000);
2033 /* xxx Required for WLAN only case ? */
2034 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0);
2035 udelay(100);
2036 }
2037
2038 /*
2039 * Clear the RTC force wake bit to allow the
2040 * mac to go to sleep.
2041 */
2042 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
2043
2044 if (AR_SREV_9462(ah))
2045 udelay(100);
2046
2047 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
2048 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2049
2050 /* Shutdown chip. Active low */
2051 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) {
2052 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN);
2053 udelay(2);
2054 }
2055 }
2056
2057 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
2058 if (AR_SREV_9300_20_OR_LATER(ah))
2059 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
2060 }
2061
2062 /*
2063 * Notify Power Management is enabled in self-generating
2064 * frames. If request, set power mode of chip to
2065 * auto/normal. Duration in units of 128us (1/8 TU).
2066 */
2067 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
2068 {
2069 u32 val;
2070
2071 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2072 if (setChip) {
2073 struct ath9k_hw_capabilities *pCap = &ah->caps;
2074
2075 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2076 /* Set WakeOnInterrupt bit; clear ForceWake bit */
2077 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2078 AR_RTC_FORCE_WAKE_ON_INT);
2079 } else {
2080
2081 /* When chip goes into network sleep, it could be waken
2082 * up by MCI_INT interrupt caused by BT's HW messages
2083 * (LNA_xxx, CONT_xxx) which chould be in a very fast
2084 * rate (~100us). This will cause chip to leave and
2085 * re-enter network sleep mode frequently, which in
2086 * consequence will have WLAN MCI HW to generate lots of
2087 * SYS_WAKING and SYS_SLEEPING messages which will make
2088 * BT CPU to busy to process.
2089 */
2090 if (AR_SREV_9462(ah)) {
2091 val = REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_EN) &
2092 ~AR_MCI_INTERRUPT_RX_HW_MSG_MASK;
2093 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, val);
2094 }
2095 /*
2096 * Clear the RTC force wake bit to allow the
2097 * mac to go to sleep.
2098 */
2099 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2100 AR_RTC_FORCE_WAKE_EN);
2101
2102 if (AR_SREV_9462(ah))
2103 udelay(30);
2104 }
2105 }
2106
2107 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
2108 if (AR_SREV_9300_20_OR_LATER(ah))
2109 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
2110 }
2111
2112 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2113 {
2114 u32 val;
2115 int i;
2116
2117 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */
2118 if (AR_SREV_9300_20_OR_LATER(ah)) {
2119 REG_WRITE(ah, AR_WA, ah->WARegVal);
2120 udelay(10);
2121 }
2122
2123 if (setChip) {
2124 if ((REG_READ(ah, AR_RTC_STATUS) &
2125 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2126 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
2127 return false;
2128 }
2129 if (!AR_SREV_9300_20_OR_LATER(ah))
2130 ath9k_hw_init_pll(ah, NULL);
2131 }
2132 if (AR_SREV_9100(ah))
2133 REG_SET_BIT(ah, AR_RTC_RESET,
2134 AR_RTC_RESET_EN);
2135
2136 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2137 AR_RTC_FORCE_WAKE_EN);
2138 udelay(50);
2139
2140 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2141 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2142 if (val == AR_RTC_STATUS_ON)
2143 break;
2144 udelay(50);
2145 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2146 AR_RTC_FORCE_WAKE_EN);
2147 }
2148 if (i == 0) {
2149 ath_err(ath9k_hw_common(ah),
2150 "Failed to wakeup in %uus\n",
2151 POWER_UP_TIME / 20);
2152 return false;
2153 }
2154 }
2155
2156 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2157
2158 return true;
2159 }
2160
2161 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2162 {
2163 struct ath_common *common = ath9k_hw_common(ah);
2164 int status = true, setChip = true;
2165 static const char *modes[] = {
2166 "AWAKE",
2167 "FULL-SLEEP",
2168 "NETWORK SLEEP",
2169 "UNDEFINED"
2170 };
2171
2172 if (ah->power_mode == mode)
2173 return status;
2174
2175 ath_dbg(common, RESET, "%s -> %s\n",
2176 modes[ah->power_mode], modes[mode]);
2177
2178 switch (mode) {
2179 case ATH9K_PM_AWAKE:
2180 status = ath9k_hw_set_power_awake(ah, setChip);
2181
2182 if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI)
2183 REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2);
2184
2185 break;
2186 case ATH9K_PM_FULL_SLEEP:
2187 if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI)
2188 ar9003_mci_set_full_sleep(ah);
2189
2190 ath9k_set_power_sleep(ah, setChip);
2191 ah->chip_fullsleep = true;
2192 break;
2193 case ATH9K_PM_NETWORK_SLEEP:
2194
2195 if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI)
2196 REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2);
2197
2198 ath9k_set_power_network_sleep(ah, setChip);
2199 break;
2200 default:
2201 ath_err(common, "Unknown power mode %u\n", mode);
2202 return false;
2203 }
2204 ah->power_mode = mode;
2205
2206 /*
2207 * XXX: If this warning never comes up after a while then
2208 * simply keep the ATH_DBG_WARN_ON_ONCE() but make
2209 * ath9k_hw_setpower() return type void.
2210 */
2211
2212 if (!(ah->ah_flags & AH_UNPLUGGED))
2213 ATH_DBG_WARN_ON_ONCE(!status);
2214
2215 return status;
2216 }
2217 EXPORT_SYMBOL(ath9k_hw_setpower);
2218
2219 /*******************/
2220 /* Beacon Handling */
2221 /*******************/
2222
2223 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
2224 {
2225 int flags = 0;
2226
2227 ENABLE_REGWRITE_BUFFER(ah);
2228
2229 switch (ah->opmode) {
2230 case NL80211_IFTYPE_ADHOC:
2231 case NL80211_IFTYPE_MESH_POINT:
2232 REG_SET_BIT(ah, AR_TXCFG,
2233 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
2234 REG_WRITE(ah, AR_NEXT_NDP_TIMER, next_beacon +
2235 TU_TO_USEC(ah->atim_window ? ah->atim_window : 1));
2236 flags |= AR_NDP_TIMER_EN;
2237 case NL80211_IFTYPE_AP:
2238 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon);
2239 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon -
2240 TU_TO_USEC(ah->config.dma_beacon_response_time));
2241 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon -
2242 TU_TO_USEC(ah->config.sw_beacon_response_time));
2243 flags |=
2244 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
2245 break;
2246 default:
2247 ath_dbg(ath9k_hw_common(ah), BEACON,
2248 "%s: unsupported opmode: %d\n", __func__, ah->opmode);
2249 return;
2250 break;
2251 }
2252
2253 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period);
2254 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period);
2255 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period);
2256 REG_WRITE(ah, AR_NDP_PERIOD, beacon_period);
2257
2258 REGWRITE_BUFFER_FLUSH(ah);
2259
2260 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
2261 }
2262 EXPORT_SYMBOL(ath9k_hw_beaconinit);
2263
2264 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
2265 const struct ath9k_beacon_state *bs)
2266 {
2267 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
2268 struct ath9k_hw_capabilities *pCap = &ah->caps;
2269 struct ath_common *common = ath9k_hw_common(ah);
2270
2271 ENABLE_REGWRITE_BUFFER(ah);
2272
2273 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
2274
2275 REG_WRITE(ah, AR_BEACON_PERIOD,
2276 TU_TO_USEC(bs->bs_intval));
2277 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
2278 TU_TO_USEC(bs->bs_intval));
2279
2280 REGWRITE_BUFFER_FLUSH(ah);
2281
2282 REG_RMW_FIELD(ah, AR_RSSI_THR,
2283 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
2284
2285 beaconintval = bs->bs_intval;
2286
2287 if (bs->bs_sleepduration > beaconintval)
2288 beaconintval = bs->bs_sleepduration;
2289
2290 dtimperiod = bs->bs_dtimperiod;
2291 if (bs->bs_sleepduration > dtimperiod)
2292 dtimperiod = bs->bs_sleepduration;
2293
2294 if (beaconintval == dtimperiod)
2295 nextTbtt = bs->bs_nextdtim;
2296 else
2297 nextTbtt = bs->bs_nexttbtt;
2298
2299 ath_dbg(common, BEACON, "next DTIM %d\n", bs->bs_nextdtim);
2300 ath_dbg(common, BEACON, "next beacon %d\n", nextTbtt);
2301 ath_dbg(common, BEACON, "beacon period %d\n", beaconintval);
2302 ath_dbg(common, BEACON, "DTIM period %d\n", dtimperiod);
2303
2304 ENABLE_REGWRITE_BUFFER(ah);
2305
2306 REG_WRITE(ah, AR_NEXT_DTIM,
2307 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
2308 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
2309
2310 REG_WRITE(ah, AR_SLEEP1,
2311 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
2312 | AR_SLEEP1_ASSUME_DTIM);
2313
2314 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
2315 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
2316 else
2317 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
2318
2319 REG_WRITE(ah, AR_SLEEP2,
2320 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
2321
2322 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
2323 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
2324
2325 REGWRITE_BUFFER_FLUSH(ah);
2326
2327 REG_SET_BIT(ah, AR_TIMER_MODE,
2328 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
2329 AR_DTIM_TIMER_EN);
2330
2331 /* TSF Out of Range Threshold */
2332 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
2333 }
2334 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
2335
2336 /*******************/
2337 /* HW Capabilities */
2338 /*******************/
2339
2340 static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask)
2341 {
2342 eeprom_chainmask &= chip_chainmask;
2343 if (eeprom_chainmask)
2344 return eeprom_chainmask;
2345 else
2346 return chip_chainmask;
2347 }
2348
2349 /**
2350 * ath9k_hw_dfs_tested - checks if DFS has been tested with used chipset
2351 * @ah: the atheros hardware data structure
2352 *
2353 * We enable DFS support upstream on chipsets which have passed a series
2354 * of tests. The testing requirements are going to be documented. Desired
2355 * test requirements are documented at:
2356 *
2357 * http://wireless.kernel.org/en/users/Drivers/ath9k/dfs
2358 *
2359 * Once a new chipset gets properly tested an individual commit can be used
2360 * to document the testing for DFS for that chipset.
2361 */
2362 static bool ath9k_hw_dfs_tested(struct ath_hw *ah)
2363 {
2364
2365 switch (ah->hw_version.macVersion) {
2366 /* AR9580 will likely be our first target to get testing on */
2367 case AR_SREV_VERSION_9580:
2368 default:
2369 return false;
2370 }
2371 }
2372
2373 int ath9k_hw_fill_cap_info(struct ath_hw *ah)
2374 {
2375 struct ath9k_hw_capabilities *pCap = &ah->caps;
2376 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2377 struct ath_common *common = ath9k_hw_common(ah);
2378 unsigned int chip_chainmask;
2379
2380 u16 eeval;
2381 u8 ant_div_ctl1, tx_chainmask, rx_chainmask;
2382
2383 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
2384 regulatory->current_rd = eeval;
2385
2386 if (ah->opmode != NL80211_IFTYPE_AP &&
2387 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
2388 if (regulatory->current_rd == 0x64 ||
2389 regulatory->current_rd == 0x65)
2390 regulatory->current_rd += 5;
2391 else if (regulatory->current_rd == 0x41)
2392 regulatory->current_rd = 0x43;
2393 ath_dbg(common, REGULATORY, "regdomain mapped to 0x%x\n",
2394 regulatory->current_rd);
2395 }
2396
2397 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
2398 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
2399 ath_err(common,
2400 "no band has been marked as supported in EEPROM\n");
2401 return -EINVAL;
2402 }
2403
2404 if (eeval & AR5416_OPFLAGS_11A)
2405 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
2406
2407 if (eeval & AR5416_OPFLAGS_11G)
2408 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
2409
2410 if (AR_SREV_9485(ah) || AR_SREV_9285(ah) || AR_SREV_9330(ah))
2411 chip_chainmask = 1;
2412 else if (AR_SREV_9462(ah))
2413 chip_chainmask = 3;
2414 else if (!AR_SREV_9280_20_OR_LATER(ah))
2415 chip_chainmask = 7;
2416 else if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9340(ah))
2417 chip_chainmask = 3;
2418 else
2419 chip_chainmask = 7;
2420
2421 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
2422 /*
2423 * For AR9271 we will temporarilly uses the rx chainmax as read from
2424 * the EEPROM.
2425 */
2426 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
2427 !(eeval & AR5416_OPFLAGS_11A) &&
2428 !(AR_SREV_9271(ah)))
2429 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
2430 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
2431 else if (AR_SREV_9100(ah))
2432 pCap->rx_chainmask = 0x7;
2433 else
2434 /* Use rx_chainmask from EEPROM. */
2435 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
2436
2437 pCap->tx_chainmask = fixup_chainmask(chip_chainmask, pCap->tx_chainmask);
2438 pCap->rx_chainmask = fixup_chainmask(chip_chainmask, pCap->rx_chainmask);
2439 ah->txchainmask = pCap->tx_chainmask;
2440 ah->rxchainmask = pCap->rx_chainmask;
2441
2442 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
2443
2444 /* enable key search for every frame in an aggregate */
2445 if (AR_SREV_9300_20_OR_LATER(ah))
2446 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
2447
2448 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
2449
2450 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
2451 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2452 else
2453 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
2454
2455 if (AR_SREV_9271(ah))
2456 pCap->num_gpio_pins = AR9271_NUM_GPIO;
2457 else if (AR_DEVID_7010(ah))
2458 pCap->num_gpio_pins = AR7010_NUM_GPIO;
2459 else if (AR_SREV_9300_20_OR_LATER(ah))
2460 pCap->num_gpio_pins = AR9300_NUM_GPIO;
2461 else if (AR_SREV_9287_11_OR_LATER(ah))
2462 pCap->num_gpio_pins = AR9287_NUM_GPIO;
2463 else if (AR_SREV_9285_12_OR_LATER(ah))
2464 pCap->num_gpio_pins = AR9285_NUM_GPIO;
2465 else if (AR_SREV_9280_20_OR_LATER(ah))
2466 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2467 else
2468 pCap->num_gpio_pins = AR_NUM_GPIO;
2469
2470 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah))
2471 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
2472 else
2473 pCap->rts_aggr_limit = (8 * 1024);
2474
2475 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2476 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2477 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2478 ah->rfkill_gpio =
2479 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2480 ah->rfkill_polarity =
2481 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
2482
2483 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
2484 }
2485 #endif
2486 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
2487 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2488 else
2489 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
2490
2491 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
2492 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2493 else
2494 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
2495
2496 if (AR_SREV_9300_20_OR_LATER(ah)) {
2497 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
2498 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah))
2499 pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
2500
2501 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2502 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2503 pCap->rx_status_len = sizeof(struct ar9003_rxs);
2504 pCap->tx_desc_len = sizeof(struct ar9003_txc);
2505 pCap->txs_len = sizeof(struct ar9003_txs);
2506 if (!ah->config.paprd_disable &&
2507 ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
2508 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
2509 } else {
2510 pCap->tx_desc_len = sizeof(struct ath_desc);
2511 if (AR_SREV_9280_20(ah))
2512 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
2513 }
2514
2515 if (AR_SREV_9300_20_OR_LATER(ah))
2516 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2517
2518 if (AR_SREV_9300_20_OR_LATER(ah))
2519 ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
2520
2521 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
2522 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
2523
2524 if (AR_SREV_9285(ah))
2525 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
2526 ant_div_ctl1 =
2527 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2528 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1))
2529 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2530 }
2531 if (AR_SREV_9300_20_OR_LATER(ah)) {
2532 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
2533 pCap->hw_caps |= ATH9K_HW_CAP_APM;
2534 }
2535
2536
2537 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
2538 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2539 /*
2540 * enable the diversity-combining algorithm only when
2541 * both enable_lna_div and enable_fast_div are set
2542 * Table for Diversity
2543 * ant_div_alt_lnaconf bit 0-1
2544 * ant_div_main_lnaconf bit 2-3
2545 * ant_div_alt_gaintb bit 4
2546 * ant_div_main_gaintb bit 5
2547 * enable_ant_div_lnadiv bit 6
2548 * enable_ant_fast_div bit 7
2549 */
2550 if ((ant_div_ctl1 >> 0x6) == 0x3)
2551 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2552 }
2553
2554 if (AR_SREV_9485_10(ah)) {
2555 pCap->pcie_lcr_extsync_en = true;
2556 pCap->pcie_lcr_offset = 0x80;
2557 }
2558
2559 if (ath9k_hw_dfs_tested(ah))
2560 pCap->hw_caps |= ATH9K_HW_CAP_DFS;
2561
2562 tx_chainmask = pCap->tx_chainmask;
2563 rx_chainmask = pCap->rx_chainmask;
2564 while (tx_chainmask || rx_chainmask) {
2565 if (tx_chainmask & BIT(0))
2566 pCap->max_txchains++;
2567 if (rx_chainmask & BIT(0))
2568 pCap->max_rxchains++;
2569
2570 tx_chainmask >>= 1;
2571 rx_chainmask >>= 1;
2572 }
2573
2574 if (AR_SREV_9300_20_OR_LATER(ah)) {
2575 ah->enabled_cals |= TX_IQ_CAL;
2576 if (AR_SREV_9485_OR_LATER(ah))
2577 ah->enabled_cals |= TX_IQ_ON_AGC_CAL;
2578 }
2579
2580 if (AR_SREV_9462(ah)) {
2581
2582 if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE))
2583 pCap->hw_caps |= ATH9K_HW_CAP_MCI;
2584
2585 if (AR_SREV_9462_20(ah))
2586 pCap->hw_caps |= ATH9K_HW_CAP_RTT;
2587
2588 }
2589
2590
2591 return 0;
2592 }
2593
2594 /****************************/
2595 /* GPIO / RFKILL / Antennae */
2596 /****************************/
2597
2598 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
2599 u32 gpio, u32 type)
2600 {
2601 int addr;
2602 u32 gpio_shift, tmp;
2603
2604 if (gpio > 11)
2605 addr = AR_GPIO_OUTPUT_MUX3;
2606 else if (gpio > 5)
2607 addr = AR_GPIO_OUTPUT_MUX2;
2608 else
2609 addr = AR_GPIO_OUTPUT_MUX1;
2610
2611 gpio_shift = (gpio % 6) * 5;
2612
2613 if (AR_SREV_9280_20_OR_LATER(ah)
2614 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2615 REG_RMW(ah, addr, (type << gpio_shift),
2616 (0x1f << gpio_shift));
2617 } else {
2618 tmp = REG_READ(ah, addr);
2619 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2620 tmp &= ~(0x1f << gpio_shift);
2621 tmp |= (type << gpio_shift);
2622 REG_WRITE(ah, addr, tmp);
2623 }
2624 }
2625
2626 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
2627 {
2628 u32 gpio_shift;
2629
2630 BUG_ON(gpio >= ah->caps.num_gpio_pins);
2631
2632 if (AR_DEVID_7010(ah)) {
2633 gpio_shift = gpio;
2634 REG_RMW(ah, AR7010_GPIO_OE,
2635 (AR7010_GPIO_OE_AS_INPUT << gpio_shift),
2636 (AR7010_GPIO_OE_MASK << gpio_shift));
2637 return;
2638 }
2639
2640 gpio_shift = gpio << 1;
2641 REG_RMW(ah,
2642 AR_GPIO_OE_OUT,
2643 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2644 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2645 }
2646 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
2647
2648 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
2649 {
2650 #define MS_REG_READ(x, y) \
2651 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2652
2653 if (gpio >= ah->caps.num_gpio_pins)
2654 return 0xffffffff;
2655
2656 if (AR_DEVID_7010(ah)) {
2657 u32 val;
2658 val = REG_READ(ah, AR7010_GPIO_IN);
2659 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0;
2660 } else if (AR_SREV_9300_20_OR_LATER(ah))
2661 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) &
2662 AR_GPIO_BIT(gpio)) != 0;
2663 else if (AR_SREV_9271(ah))
2664 return MS_REG_READ(AR9271, gpio) != 0;
2665 else if (AR_SREV_9287_11_OR_LATER(ah))
2666 return MS_REG_READ(AR9287, gpio) != 0;
2667 else if (AR_SREV_9285_12_OR_LATER(ah))
2668 return MS_REG_READ(AR9285, gpio) != 0;
2669 else if (AR_SREV_9280_20_OR_LATER(ah))
2670 return MS_REG_READ(AR928X, gpio) != 0;
2671 else
2672 return MS_REG_READ(AR, gpio) != 0;
2673 }
2674 EXPORT_SYMBOL(ath9k_hw_gpio_get);
2675
2676 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
2677 u32 ah_signal_type)
2678 {
2679 u32 gpio_shift;
2680
2681 if (AR_DEVID_7010(ah)) {
2682 gpio_shift = gpio;
2683 REG_RMW(ah, AR7010_GPIO_OE,
2684 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift),
2685 (AR7010_GPIO_OE_MASK << gpio_shift));
2686 return;
2687 }
2688
2689 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
2690 gpio_shift = 2 * gpio;
2691 REG_RMW(ah,
2692 AR_GPIO_OE_OUT,
2693 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2694 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2695 }
2696 EXPORT_SYMBOL(ath9k_hw_cfg_output);
2697
2698 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
2699 {
2700 if (AR_DEVID_7010(ah)) {
2701 val = val ? 0 : 1;
2702 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio),
2703 AR_GPIO_BIT(gpio));
2704 return;
2705 }
2706
2707 if (AR_SREV_9271(ah))
2708 val = ~val;
2709
2710 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2711 AR_GPIO_BIT(gpio));
2712 }
2713 EXPORT_SYMBOL(ath9k_hw_set_gpio);
2714
2715 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
2716 {
2717 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
2718 }
2719 EXPORT_SYMBOL(ath9k_hw_setantenna);
2720
2721 /*********************/
2722 /* General Operation */
2723 /*********************/
2724
2725 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
2726 {
2727 u32 bits = REG_READ(ah, AR_RX_FILTER);
2728 u32 phybits = REG_READ(ah, AR_PHY_ERR);
2729
2730 if (phybits & AR_PHY_ERR_RADAR)
2731 bits |= ATH9K_RX_FILTER_PHYRADAR;
2732 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2733 bits |= ATH9K_RX_FILTER_PHYERR;
2734
2735 return bits;
2736 }
2737 EXPORT_SYMBOL(ath9k_hw_getrxfilter);
2738
2739 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
2740 {
2741 u32 phybits;
2742
2743 ENABLE_REGWRITE_BUFFER(ah);
2744
2745 if (AR_SREV_9462(ah))
2746 bits |= ATH9K_RX_FILTER_CONTROL_WRAPPER;
2747
2748 REG_WRITE(ah, AR_RX_FILTER, bits);
2749
2750 phybits = 0;
2751 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2752 phybits |= AR_PHY_ERR_RADAR;
2753 if (bits & ATH9K_RX_FILTER_PHYERR)
2754 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2755 REG_WRITE(ah, AR_PHY_ERR, phybits);
2756
2757 if (phybits)
2758 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
2759 else
2760 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
2761
2762 REGWRITE_BUFFER_FLUSH(ah);
2763 }
2764 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
2765
2766 bool ath9k_hw_phy_disable(struct ath_hw *ah)
2767 {
2768 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2769 return false;
2770
2771 ath9k_hw_init_pll(ah, NULL);
2772 ah->htc_reset_init = true;
2773 return true;
2774 }
2775 EXPORT_SYMBOL(ath9k_hw_phy_disable);
2776
2777 bool ath9k_hw_disable(struct ath_hw *ah)
2778 {
2779 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2780 return false;
2781
2782 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2783 return false;
2784
2785 ath9k_hw_init_pll(ah, NULL);
2786 return true;
2787 }
2788 EXPORT_SYMBOL(ath9k_hw_disable);
2789
2790 static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan)
2791 {
2792 enum eeprom_param gain_param;
2793
2794 if (IS_CHAN_2GHZ(chan))
2795 gain_param = EEP_ANTENNA_GAIN_2G;
2796 else
2797 gain_param = EEP_ANTENNA_GAIN_5G;
2798
2799 return ah->eep_ops->get_eeprom(ah, gain_param);
2800 }
2801
2802 void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan,
2803 bool test)
2804 {
2805 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2806 struct ieee80211_channel *channel;
2807 int chan_pwr, new_pwr, max_gain;
2808 int ant_gain, ant_reduction = 0;
2809
2810 if (!chan)
2811 return;
2812
2813 channel = chan->chan;
2814 chan_pwr = min_t(int, channel->max_power * 2, MAX_RATE_POWER);
2815 new_pwr = min_t(int, chan_pwr, reg->power_limit);
2816 max_gain = chan_pwr - new_pwr + channel->max_antenna_gain * 2;
2817
2818 ant_gain = get_antenna_gain(ah, chan);
2819 if (ant_gain > max_gain)
2820 ant_reduction = ant_gain - max_gain;
2821
2822 ah->eep_ops->set_txpower(ah, chan,
2823 ath9k_regd_get_ctl(reg, chan),
2824 ant_reduction, new_pwr, test);
2825 }
2826
2827 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
2828 {
2829 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2830 struct ath9k_channel *chan = ah->curchan;
2831 struct ieee80211_channel *channel = chan->chan;
2832
2833 reg->power_limit = min_t(u32, limit, MAX_RATE_POWER);
2834 if (test)
2835 channel->max_power = MAX_RATE_POWER / 2;
2836
2837 ath9k_hw_apply_txpower(ah, chan, test);
2838
2839 if (test)
2840 channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2);
2841 }
2842 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
2843
2844 void ath9k_hw_setopmode(struct ath_hw *ah)
2845 {
2846 ath9k_hw_set_operating_mode(ah, ah->opmode);
2847 }
2848 EXPORT_SYMBOL(ath9k_hw_setopmode);
2849
2850 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
2851 {
2852 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2853 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
2854 }
2855 EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
2856
2857 void ath9k_hw_write_associd(struct ath_hw *ah)
2858 {
2859 struct ath_common *common = ath9k_hw_common(ah);
2860
2861 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2862 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2863 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2864 }
2865 EXPORT_SYMBOL(ath9k_hw_write_associd);
2866
2867 #define ATH9K_MAX_TSF_READ 10
2868
2869 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
2870 {
2871 u32 tsf_lower, tsf_upper1, tsf_upper2;
2872 int i;
2873
2874 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2875 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2876 tsf_lower = REG_READ(ah, AR_TSF_L32);
2877 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2878 if (tsf_upper2 == tsf_upper1)
2879 break;
2880 tsf_upper1 = tsf_upper2;
2881 }
2882
2883 WARN_ON( i == ATH9K_MAX_TSF_READ );
2884
2885 return (((u64)tsf_upper1 << 32) | tsf_lower);
2886 }
2887 EXPORT_SYMBOL(ath9k_hw_gettsf64);
2888
2889 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
2890 {
2891 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
2892 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
2893 }
2894 EXPORT_SYMBOL(ath9k_hw_settsf64);
2895
2896 void ath9k_hw_reset_tsf(struct ath_hw *ah)
2897 {
2898 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2899 AH_TSF_WRITE_TIMEOUT))
2900 ath_dbg(ath9k_hw_common(ah), RESET,
2901 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
2902
2903 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2904 }
2905 EXPORT_SYMBOL(ath9k_hw_reset_tsf);
2906
2907 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
2908 {
2909 if (setting)
2910 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
2911 else
2912 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
2913 }
2914 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
2915
2916 void ath9k_hw_set11nmac2040(struct ath_hw *ah)
2917 {
2918 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
2919 u32 macmode;
2920
2921 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
2922 macmode = AR_2040_JOINED_RX_CLEAR;
2923 else
2924 macmode = 0;
2925
2926 REG_WRITE(ah, AR_2040_MODE, macmode);
2927 }
2928
2929 /* HW Generic timers configuration */
2930
2931 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2932 {
2933 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2934 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2935 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2936 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2937 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2938 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2939 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2940 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2941 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2942 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2943 AR_NDP2_TIMER_MODE, 0x0002},
2944 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2945 AR_NDP2_TIMER_MODE, 0x0004},
2946 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2947 AR_NDP2_TIMER_MODE, 0x0008},
2948 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2949 AR_NDP2_TIMER_MODE, 0x0010},
2950 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2951 AR_NDP2_TIMER_MODE, 0x0020},
2952 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2953 AR_NDP2_TIMER_MODE, 0x0040},
2954 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2955 AR_NDP2_TIMER_MODE, 0x0080}
2956 };
2957
2958 /* HW generic timer primitives */
2959
2960 /* compute and clear index of rightmost 1 */
2961 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
2962 {
2963 u32 b;
2964
2965 b = *mask;
2966 b &= (0-b);
2967 *mask &= ~b;
2968 b *= debruijn32;
2969 b >>= 27;
2970
2971 return timer_table->gen_timer_index[b];
2972 }
2973
2974 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
2975 {
2976 return REG_READ(ah, AR_TSF_L32);
2977 }
2978 EXPORT_SYMBOL(ath9k_hw_gettsf32);
2979
2980 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2981 void (*trigger)(void *),
2982 void (*overflow)(void *),
2983 void *arg,
2984 u8 timer_index)
2985 {
2986 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2987 struct ath_gen_timer *timer;
2988
2989 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
2990
2991 if (timer == NULL) {
2992 ath_err(ath9k_hw_common(ah),
2993 "Failed to allocate memory for hw timer[%d]\n",
2994 timer_index);
2995 return NULL;
2996 }
2997
2998 /* allocate a hardware generic timer slot */
2999 timer_table->timers[timer_index] = timer;
3000 timer->index = timer_index;
3001 timer->trigger = trigger;
3002 timer->overflow = overflow;
3003 timer->arg = arg;
3004
3005 return timer;
3006 }
3007 EXPORT_SYMBOL(ath_gen_timer_alloc);
3008
3009 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
3010 struct ath_gen_timer *timer,
3011 u32 trig_timeout,
3012 u32 timer_period)
3013 {
3014 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3015 u32 tsf, timer_next;
3016
3017 BUG_ON(!timer_period);
3018
3019 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
3020
3021 tsf = ath9k_hw_gettsf32(ah);
3022
3023 timer_next = tsf + trig_timeout;
3024
3025 ath_dbg(ath9k_hw_common(ah), HWTIMER,
3026 "current tsf %x period %x timer_next %x\n",
3027 tsf, timer_period, timer_next);
3028
3029 /*
3030 * Program generic timer registers
3031 */
3032 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
3033 timer_next);
3034 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
3035 timer_period);
3036 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3037 gen_tmr_configuration[timer->index].mode_mask);
3038
3039 if (AR_SREV_9462(ah)) {
3040 /*
3041 * Starting from AR9462, each generic timer can select which tsf
3042 * to use. But we still follow the old rule, 0 - 7 use tsf and
3043 * 8 - 15 use tsf2.
3044 */
3045 if ((timer->index < AR_GEN_TIMER_BANK_1_LEN))
3046 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3047 (1 << timer->index));
3048 else
3049 REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3050 (1 << timer->index));
3051 }
3052
3053 /* Enable both trigger and thresh interrupt masks */
3054 REG_SET_BIT(ah, AR_IMR_S5,
3055 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3056 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3057 }
3058 EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
3059
3060 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
3061 {
3062 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3063
3064 if ((timer->index < AR_FIRST_NDP_TIMER) ||
3065 (timer->index >= ATH_MAX_GEN_TIMER)) {
3066 return;
3067 }
3068
3069 /* Clear generic timer enable bits. */
3070 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3071 gen_tmr_configuration[timer->index].mode_mask);
3072
3073 /* Disable both trigger and thresh interrupt masks */
3074 REG_CLR_BIT(ah, AR_IMR_S5,
3075 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3076 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3077
3078 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
3079 }
3080 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
3081
3082 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
3083 {
3084 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3085
3086 /* free the hardware generic timer slot */
3087 timer_table->timers[timer->index] = NULL;
3088 kfree(timer);
3089 }
3090 EXPORT_SYMBOL(ath_gen_timer_free);
3091
3092 /*
3093 * Generic Timer Interrupts handling
3094 */
3095 void ath_gen_timer_isr(struct ath_hw *ah)
3096 {
3097 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3098 struct ath_gen_timer *timer;
3099 struct ath_common *common = ath9k_hw_common(ah);
3100 u32 trigger_mask, thresh_mask, index;
3101
3102 /* get hardware generic timer interrupt status */
3103 trigger_mask = ah->intr_gen_timer_trigger;
3104 thresh_mask = ah->intr_gen_timer_thresh;
3105 trigger_mask &= timer_table->timer_mask.val;
3106 thresh_mask &= timer_table->timer_mask.val;
3107
3108 trigger_mask &= ~thresh_mask;
3109
3110 while (thresh_mask) {
3111 index = rightmost_index(timer_table, &thresh_mask);
3112 timer = timer_table->timers[index];
3113 BUG_ON(!timer);
3114 ath_dbg(common, HWTIMER, "TSF overflow for Gen timer %d\n",
3115 index);
3116 timer->overflow(timer->arg);
3117 }
3118
3119 while (trigger_mask) {
3120 index = rightmost_index(timer_table, &trigger_mask);
3121 timer = timer_table->timers[index];
3122 BUG_ON(!timer);
3123 ath_dbg(common, HWTIMER,
3124 "Gen timer[%d] trigger\n", index);
3125 timer->trigger(timer->arg);
3126 }
3127 }
3128 EXPORT_SYMBOL(ath_gen_timer_isr);
3129
3130 /********/
3131 /* HTC */
3132 /********/
3133
3134 static struct {
3135 u32 version;
3136 const char * name;
3137 } ath_mac_bb_names[] = {
3138 /* Devices with external radios */
3139 { AR_SREV_VERSION_5416_PCI, "5416" },
3140 { AR_SREV_VERSION_5416_PCIE, "5418" },
3141 { AR_SREV_VERSION_9100, "9100" },
3142 { AR_SREV_VERSION_9160, "9160" },
3143 /* Single-chip solutions */
3144 { AR_SREV_VERSION_9280, "9280" },
3145 { AR_SREV_VERSION_9285, "9285" },
3146 { AR_SREV_VERSION_9287, "9287" },
3147 { AR_SREV_VERSION_9271, "9271" },
3148 { AR_SREV_VERSION_9300, "9300" },
3149 { AR_SREV_VERSION_9330, "9330" },
3150 { AR_SREV_VERSION_9340, "9340" },
3151 { AR_SREV_VERSION_9485, "9485" },
3152 { AR_SREV_VERSION_9462, "9462" },
3153 };
3154
3155 /* For devices with external radios */
3156 static struct {
3157 u16 version;
3158 const char * name;
3159 } ath_rf_names[] = {
3160 { 0, "5133" },
3161 { AR_RAD5133_SREV_MAJOR, "5133" },
3162 { AR_RAD5122_SREV_MAJOR, "5122" },
3163 { AR_RAD2133_SREV_MAJOR, "2133" },
3164 { AR_RAD2122_SREV_MAJOR, "2122" }
3165 };
3166
3167 /*
3168 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3169 */
3170 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
3171 {
3172 int i;
3173
3174 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3175 if (ath_mac_bb_names[i].version == mac_bb_version) {
3176 return ath_mac_bb_names[i].name;
3177 }
3178 }
3179
3180 return "????";
3181 }
3182
3183 /*
3184 * Return the RF name. "????" is returned if the RF is unknown.
3185 * Used for devices with external radios.
3186 */
3187 static const char *ath9k_hw_rf_name(u16 rf_version)
3188 {
3189 int i;
3190
3191 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3192 if (ath_rf_names[i].version == rf_version) {
3193 return ath_rf_names[i].name;
3194 }
3195 }
3196
3197 return "????";
3198 }
3199
3200 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
3201 {
3202 int used;
3203
3204 /* chipsets >= AR9280 are single-chip */
3205 if (AR_SREV_9280_20_OR_LATER(ah)) {
3206 used = snprintf(hw_name, len,
3207 "Atheros AR%s Rev:%x",
3208 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3209 ah->hw_version.macRev);
3210 }
3211 else {
3212 used = snprintf(hw_name, len,
3213 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3214 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3215 ah->hw_version.macRev,
3216 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
3217 AR_RADIO_SREV_MAJOR)),
3218 ah->hw_version.phyRev);
3219 }
3220
3221 hw_name[used] = '\0';
3222 }
3223 EXPORT_SYMBOL(ath9k_hw_name);
Linux kernel - Deliverables
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