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Merge branch 'for-john' of git://git.kernel.org/pub/scm/linux/kernel/git/jberg/mac802...
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / hw.c
1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/io.h>
18 #include <linux/slab.h>
19 #include <linux/module.h>
20 #include <asm/unaligned.h>
21
22 #include "hw.h"
23 #include "hw-ops.h"
24 #include "rc.h"
25 #include "ar9003_mac.h"
26 #include "ar9003_mci.h"
27 #include "ar9003_phy.h"
28 #include "debug.h"
29 #include "ath9k.h"
30
31 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
32
33 MODULE_AUTHOR("Atheros Communications");
34 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
35 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
36 MODULE_LICENSE("Dual BSD/GPL");
37
38 static int __init ath9k_init(void)
39 {
40 return 0;
41 }
42 module_init(ath9k_init);
43
44 static void __exit ath9k_exit(void)
45 {
46 return;
47 }
48 module_exit(ath9k_exit);
49
50 /* Private hardware callbacks */
51
52 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
53 {
54 ath9k_hw_private_ops(ah)->init_cal_settings(ah);
55 }
56
57 static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
58 struct ath9k_channel *chan)
59 {
60 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
61 }
62
63 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
64 {
65 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
66 return;
67
68 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
69 }
70
71 static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah)
72 {
73 /* You will not have this callback if using the old ANI */
74 if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs)
75 return;
76
77 ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah);
78 }
79
80 /********************/
81 /* Helper Functions */
82 /********************/
83
84 #ifdef CONFIG_ATH9K_DEBUGFS
85
86 void ath9k_debug_sync_cause(struct ath_common *common, u32 sync_cause)
87 {
88 struct ath_softc *sc = common->priv;
89 if (sync_cause)
90 sc->debug.stats.istats.sync_cause_all++;
91 if (sync_cause & AR_INTR_SYNC_RTC_IRQ)
92 sc->debug.stats.istats.sync_rtc_irq++;
93 if (sync_cause & AR_INTR_SYNC_MAC_IRQ)
94 sc->debug.stats.istats.sync_mac_irq++;
95 if (sync_cause & AR_INTR_SYNC_EEPROM_ILLEGAL_ACCESS)
96 sc->debug.stats.istats.eeprom_illegal_access++;
97 if (sync_cause & AR_INTR_SYNC_APB_TIMEOUT)
98 sc->debug.stats.istats.apb_timeout++;
99 if (sync_cause & AR_INTR_SYNC_PCI_MODE_CONFLICT)
100 sc->debug.stats.istats.pci_mode_conflict++;
101 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL)
102 sc->debug.stats.istats.host1_fatal++;
103 if (sync_cause & AR_INTR_SYNC_HOST1_PERR)
104 sc->debug.stats.istats.host1_perr++;
105 if (sync_cause & AR_INTR_SYNC_TRCV_FIFO_PERR)
106 sc->debug.stats.istats.trcv_fifo_perr++;
107 if (sync_cause & AR_INTR_SYNC_RADM_CPL_EP)
108 sc->debug.stats.istats.radm_cpl_ep++;
109 if (sync_cause & AR_INTR_SYNC_RADM_CPL_DLLP_ABORT)
110 sc->debug.stats.istats.radm_cpl_dllp_abort++;
111 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TLP_ABORT)
112 sc->debug.stats.istats.radm_cpl_tlp_abort++;
113 if (sync_cause & AR_INTR_SYNC_RADM_CPL_ECRC_ERR)
114 sc->debug.stats.istats.radm_cpl_ecrc_err++;
115 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT)
116 sc->debug.stats.istats.radm_cpl_timeout++;
117 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT)
118 sc->debug.stats.istats.local_timeout++;
119 if (sync_cause & AR_INTR_SYNC_PM_ACCESS)
120 sc->debug.stats.istats.pm_access++;
121 if (sync_cause & AR_INTR_SYNC_MAC_AWAKE)
122 sc->debug.stats.istats.mac_awake++;
123 if (sync_cause & AR_INTR_SYNC_MAC_ASLEEP)
124 sc->debug.stats.istats.mac_asleep++;
125 if (sync_cause & AR_INTR_SYNC_MAC_SLEEP_ACCESS)
126 sc->debug.stats.istats.mac_sleep_access++;
127 }
128 #endif
129
130
131 static void ath9k_hw_set_clockrate(struct ath_hw *ah)
132 {
133 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
134 struct ath_common *common = ath9k_hw_common(ah);
135 unsigned int clockrate;
136
137 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */
138 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah))
139 clockrate = 117;
140 else if (!ah->curchan) /* should really check for CCK instead */
141 clockrate = ATH9K_CLOCK_RATE_CCK;
142 else if (conf->chandef.chan->band == IEEE80211_BAND_2GHZ)
143 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
144 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
145 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
146 else
147 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
148
149 if (conf_is_ht40(conf))
150 clockrate *= 2;
151
152 if (ah->curchan) {
153 if (IS_CHAN_HALF_RATE(ah->curchan))
154 clockrate /= 2;
155 if (IS_CHAN_QUARTER_RATE(ah->curchan))
156 clockrate /= 4;
157 }
158
159 common->clockrate = clockrate;
160 }
161
162 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
163 {
164 struct ath_common *common = ath9k_hw_common(ah);
165
166 return usecs * common->clockrate;
167 }
168
169 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
170 {
171 int i;
172
173 BUG_ON(timeout < AH_TIME_QUANTUM);
174
175 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
176 if ((REG_READ(ah, reg) & mask) == val)
177 return true;
178
179 udelay(AH_TIME_QUANTUM);
180 }
181
182 ath_dbg(ath9k_hw_common(ah), ANY,
183 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
184 timeout, reg, REG_READ(ah, reg), mask, val);
185
186 return false;
187 }
188 EXPORT_SYMBOL(ath9k_hw_wait);
189
190 void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan,
191 int hw_delay)
192 {
193 if (IS_CHAN_B(chan))
194 hw_delay = (4 * hw_delay) / 22;
195 else
196 hw_delay /= 10;
197
198 if (IS_CHAN_HALF_RATE(chan))
199 hw_delay *= 2;
200 else if (IS_CHAN_QUARTER_RATE(chan))
201 hw_delay *= 4;
202
203 udelay(hw_delay + BASE_ACTIVATE_DELAY);
204 }
205
206 void ath9k_hw_write_array(struct ath_hw *ah, const struct ar5416IniArray *array,
207 int column, unsigned int *writecnt)
208 {
209 int r;
210
211 ENABLE_REGWRITE_BUFFER(ah);
212 for (r = 0; r < array->ia_rows; r++) {
213 REG_WRITE(ah, INI_RA(array, r, 0),
214 INI_RA(array, r, column));
215 DO_DELAY(*writecnt);
216 }
217 REGWRITE_BUFFER_FLUSH(ah);
218 }
219
220 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
221 {
222 u32 retval;
223 int i;
224
225 for (i = 0, retval = 0; i < n; i++) {
226 retval = (retval << 1) | (val & 1);
227 val >>= 1;
228 }
229 return retval;
230 }
231
232 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
233 u8 phy, int kbps,
234 u32 frameLen, u16 rateix,
235 bool shortPreamble)
236 {
237 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
238
239 if (kbps == 0)
240 return 0;
241
242 switch (phy) {
243 case WLAN_RC_PHY_CCK:
244 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
245 if (shortPreamble)
246 phyTime >>= 1;
247 numBits = frameLen << 3;
248 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
249 break;
250 case WLAN_RC_PHY_OFDM:
251 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
252 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
253 numBits = OFDM_PLCP_BITS + (frameLen << 3);
254 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
255 txTime = OFDM_SIFS_TIME_QUARTER
256 + OFDM_PREAMBLE_TIME_QUARTER
257 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
258 } else if (ah->curchan &&
259 IS_CHAN_HALF_RATE(ah->curchan)) {
260 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
261 numBits = OFDM_PLCP_BITS + (frameLen << 3);
262 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
263 txTime = OFDM_SIFS_TIME_HALF +
264 OFDM_PREAMBLE_TIME_HALF
265 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
266 } else {
267 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
268 numBits = OFDM_PLCP_BITS + (frameLen << 3);
269 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
270 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
271 + (numSymbols * OFDM_SYMBOL_TIME);
272 }
273 break;
274 default:
275 ath_err(ath9k_hw_common(ah),
276 "Unknown phy %u (rate ix %u)\n", phy, rateix);
277 txTime = 0;
278 break;
279 }
280
281 return txTime;
282 }
283 EXPORT_SYMBOL(ath9k_hw_computetxtime);
284
285 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
286 struct ath9k_channel *chan,
287 struct chan_centers *centers)
288 {
289 int8_t extoff;
290
291 if (!IS_CHAN_HT40(chan)) {
292 centers->ctl_center = centers->ext_center =
293 centers->synth_center = chan->channel;
294 return;
295 }
296
297 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
298 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
299 centers->synth_center =
300 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
301 extoff = 1;
302 } else {
303 centers->synth_center =
304 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
305 extoff = -1;
306 }
307
308 centers->ctl_center =
309 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
310 /* 25 MHz spacing is supported by hw but not on upper layers */
311 centers->ext_center =
312 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
313 }
314
315 /******************/
316 /* Chip Revisions */
317 /******************/
318
319 static void ath9k_hw_read_revisions(struct ath_hw *ah)
320 {
321 u32 val;
322
323 switch (ah->hw_version.devid) {
324 case AR5416_AR9100_DEVID:
325 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
326 break;
327 case AR9300_DEVID_AR9330:
328 ah->hw_version.macVersion = AR_SREV_VERSION_9330;
329 if (ah->get_mac_revision) {
330 ah->hw_version.macRev = ah->get_mac_revision();
331 } else {
332 val = REG_READ(ah, AR_SREV);
333 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
334 }
335 return;
336 case AR9300_DEVID_AR9340:
337 ah->hw_version.macVersion = AR_SREV_VERSION_9340;
338 val = REG_READ(ah, AR_SREV);
339 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
340 return;
341 case AR9300_DEVID_QCA955X:
342 ah->hw_version.macVersion = AR_SREV_VERSION_9550;
343 return;
344 }
345
346 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
347
348 if (val == 0xFF) {
349 val = REG_READ(ah, AR_SREV);
350 ah->hw_version.macVersion =
351 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
352 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
353
354 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
355 ah->is_pciexpress = true;
356 else
357 ah->is_pciexpress = (val &
358 AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
359 } else {
360 if (!AR_SREV_9100(ah))
361 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
362
363 ah->hw_version.macRev = val & AR_SREV_REVISION;
364
365 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
366 ah->is_pciexpress = true;
367 }
368 }
369
370 /************************************/
371 /* HW Attach, Detach, Init Routines */
372 /************************************/
373
374 static void ath9k_hw_disablepcie(struct ath_hw *ah)
375 {
376 if (!AR_SREV_5416(ah))
377 return;
378
379 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
380 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
381 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
382 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
383 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
384 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
385 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
386 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
387 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
388
389 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
390 }
391
392 /* This should work for all families including legacy */
393 static bool ath9k_hw_chip_test(struct ath_hw *ah)
394 {
395 struct ath_common *common = ath9k_hw_common(ah);
396 u32 regAddr[2] = { AR_STA_ID0 };
397 u32 regHold[2];
398 static const u32 patternData[4] = {
399 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
400 };
401 int i, j, loop_max;
402
403 if (!AR_SREV_9300_20_OR_LATER(ah)) {
404 loop_max = 2;
405 regAddr[1] = AR_PHY_BASE + (8 << 2);
406 } else
407 loop_max = 1;
408
409 for (i = 0; i < loop_max; i++) {
410 u32 addr = regAddr[i];
411 u32 wrData, rdData;
412
413 regHold[i] = REG_READ(ah, addr);
414 for (j = 0; j < 0x100; j++) {
415 wrData = (j << 16) | j;
416 REG_WRITE(ah, addr, wrData);
417 rdData = REG_READ(ah, addr);
418 if (rdData != wrData) {
419 ath_err(common,
420 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
421 addr, wrData, rdData);
422 return false;
423 }
424 }
425 for (j = 0; j < 4; j++) {
426 wrData = patternData[j];
427 REG_WRITE(ah, addr, wrData);
428 rdData = REG_READ(ah, addr);
429 if (wrData != rdData) {
430 ath_err(common,
431 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
432 addr, wrData, rdData);
433 return false;
434 }
435 }
436 REG_WRITE(ah, regAddr[i], regHold[i]);
437 }
438 udelay(100);
439
440 return true;
441 }
442
443 static void ath9k_hw_init_config(struct ath_hw *ah)
444 {
445 int i;
446
447 ah->config.dma_beacon_response_time = 1;
448 ah->config.sw_beacon_response_time = 6;
449 ah->config.additional_swba_backoff = 0;
450 ah->config.ack_6mb = 0x0;
451 ah->config.cwm_ignore_extcca = 0;
452 ah->config.pcie_clock_req = 0;
453 ah->config.pcie_waen = 0;
454 ah->config.analog_shiftreg = 1;
455 ah->config.enable_ani = true;
456
457 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
458 ah->config.spurchans[i][0] = AR_NO_SPUR;
459 ah->config.spurchans[i][1] = AR_NO_SPUR;
460 }
461
462 ah->config.rx_intr_mitigation = true;
463 ah->config.pcieSerDesWrite = true;
464
465 /*
466 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
467 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
468 * This means we use it for all AR5416 devices, and the few
469 * minor PCI AR9280 devices out there.
470 *
471 * Serialization is required because these devices do not handle
472 * well the case of two concurrent reads/writes due to the latency
473 * involved. During one read/write another read/write can be issued
474 * on another CPU while the previous read/write may still be working
475 * on our hardware, if we hit this case the hardware poops in a loop.
476 * We prevent this by serializing reads and writes.
477 *
478 * This issue is not present on PCI-Express devices or pre-AR5416
479 * devices (legacy, 802.11abg).
480 */
481 if (num_possible_cpus() > 1)
482 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
483 }
484
485 static void ath9k_hw_init_defaults(struct ath_hw *ah)
486 {
487 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
488
489 regulatory->country_code = CTRY_DEFAULT;
490 regulatory->power_limit = MAX_RATE_POWER;
491
492 ah->hw_version.magic = AR5416_MAGIC;
493 ah->hw_version.subvendorid = 0;
494
495 ah->atim_window = 0;
496 ah->sta_id1_defaults =
497 AR_STA_ID1_CRPT_MIC_ENABLE |
498 AR_STA_ID1_MCAST_KSRCH;
499 if (AR_SREV_9100(ah))
500 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX;
501 ah->slottime = ATH9K_SLOT_TIME_9;
502 ah->globaltxtimeout = (u32) -1;
503 ah->power_mode = ATH9K_PM_UNDEFINED;
504 ah->htc_reset_init = true;
505 }
506
507 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
508 {
509 struct ath_common *common = ath9k_hw_common(ah);
510 u32 sum;
511 int i;
512 u16 eeval;
513 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
514
515 sum = 0;
516 for (i = 0; i < 3; i++) {
517 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
518 sum += eeval;
519 common->macaddr[2 * i] = eeval >> 8;
520 common->macaddr[2 * i + 1] = eeval & 0xff;
521 }
522 if (sum == 0 || sum == 0xffff * 3)
523 return -EADDRNOTAVAIL;
524
525 return 0;
526 }
527
528 static int ath9k_hw_post_init(struct ath_hw *ah)
529 {
530 struct ath_common *common = ath9k_hw_common(ah);
531 int ecode;
532
533 if (common->bus_ops->ath_bus_type != ATH_USB) {
534 if (!ath9k_hw_chip_test(ah))
535 return -ENODEV;
536 }
537
538 if (!AR_SREV_9300_20_OR_LATER(ah)) {
539 ecode = ar9002_hw_rf_claim(ah);
540 if (ecode != 0)
541 return ecode;
542 }
543
544 ecode = ath9k_hw_eeprom_init(ah);
545 if (ecode != 0)
546 return ecode;
547
548 ath_dbg(ath9k_hw_common(ah), CONFIG, "Eeprom VER: %d, REV: %d\n",
549 ah->eep_ops->get_eeprom_ver(ah),
550 ah->eep_ops->get_eeprom_rev(ah));
551
552 if (ah->config.enable_ani)
553 ath9k_hw_ani_init(ah);
554
555 return 0;
556 }
557
558 static int ath9k_hw_attach_ops(struct ath_hw *ah)
559 {
560 if (!AR_SREV_9300_20_OR_LATER(ah))
561 return ar9002_hw_attach_ops(ah);
562
563 ar9003_hw_attach_ops(ah);
564 return 0;
565 }
566
567 /* Called for all hardware families */
568 static int __ath9k_hw_init(struct ath_hw *ah)
569 {
570 struct ath_common *common = ath9k_hw_common(ah);
571 int r = 0;
572
573 ath9k_hw_read_revisions(ah);
574
575 /*
576 * Read back AR_WA into a permanent copy and set bits 14 and 17.
577 * We need to do this to avoid RMW of this register. We cannot
578 * read the reg when chip is asleep.
579 */
580 ah->WARegVal = REG_READ(ah, AR_WA);
581 ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
582 AR_WA_ASPM_TIMER_BASED_DISABLE);
583
584 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
585 ath_err(common, "Couldn't reset chip\n");
586 return -EIO;
587 }
588
589 if (AR_SREV_9462(ah))
590 ah->WARegVal &= ~AR_WA_D3_L1_DISABLE;
591
592 if (AR_SREV_9565(ah)) {
593 ah->WARegVal |= AR_WA_BIT22;
594 REG_WRITE(ah, AR_WA, ah->WARegVal);
595 }
596
597 ath9k_hw_init_defaults(ah);
598 ath9k_hw_init_config(ah);
599
600 r = ath9k_hw_attach_ops(ah);
601 if (r)
602 return r;
603
604 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
605 ath_err(common, "Couldn't wakeup chip\n");
606 return -EIO;
607 }
608
609 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
610 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
611 ((AR_SREV_9160(ah) || AR_SREV_9280(ah) || AR_SREV_9287(ah)) &&
612 !ah->is_pciexpress)) {
613 ah->config.serialize_regmode =
614 SER_REG_MODE_ON;
615 } else {
616 ah->config.serialize_regmode =
617 SER_REG_MODE_OFF;
618 }
619 }
620
621 ath_dbg(common, RESET, "serialize_regmode is %d\n",
622 ah->config.serialize_regmode);
623
624 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
625 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
626 else
627 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
628
629 switch (ah->hw_version.macVersion) {
630 case AR_SREV_VERSION_5416_PCI:
631 case AR_SREV_VERSION_5416_PCIE:
632 case AR_SREV_VERSION_9160:
633 case AR_SREV_VERSION_9100:
634 case AR_SREV_VERSION_9280:
635 case AR_SREV_VERSION_9285:
636 case AR_SREV_VERSION_9287:
637 case AR_SREV_VERSION_9271:
638 case AR_SREV_VERSION_9300:
639 case AR_SREV_VERSION_9330:
640 case AR_SREV_VERSION_9485:
641 case AR_SREV_VERSION_9340:
642 case AR_SREV_VERSION_9462:
643 case AR_SREV_VERSION_9550:
644 case AR_SREV_VERSION_9565:
645 break;
646 default:
647 ath_err(common,
648 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
649 ah->hw_version.macVersion, ah->hw_version.macRev);
650 return -EOPNOTSUPP;
651 }
652
653 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) ||
654 AR_SREV_9330(ah) || AR_SREV_9550(ah))
655 ah->is_pciexpress = false;
656
657 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
658 ath9k_hw_init_cal_settings(ah);
659
660 ah->ani_function = ATH9K_ANI_ALL;
661 if (AR_SREV_9280_20_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
662 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
663 if (!AR_SREV_9300_20_OR_LATER(ah))
664 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
665
666 if (!ah->is_pciexpress)
667 ath9k_hw_disablepcie(ah);
668
669 r = ath9k_hw_post_init(ah);
670 if (r)
671 return r;
672
673 ath9k_hw_init_mode_gain_regs(ah);
674 r = ath9k_hw_fill_cap_info(ah);
675 if (r)
676 return r;
677
678 r = ath9k_hw_init_macaddr(ah);
679 if (r) {
680 ath_err(common, "Failed to initialize MAC address\n");
681 return r;
682 }
683
684 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
685 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
686 else
687 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
688
689 if (AR_SREV_9330(ah))
690 ah->bb_watchdog_timeout_ms = 85;
691 else
692 ah->bb_watchdog_timeout_ms = 25;
693
694 common->state = ATH_HW_INITIALIZED;
695
696 return 0;
697 }
698
699 int ath9k_hw_init(struct ath_hw *ah)
700 {
701 int ret;
702 struct ath_common *common = ath9k_hw_common(ah);
703
704 /* These are all the AR5008/AR9001/AR9002/AR9003 hardware family of chipsets */
705 switch (ah->hw_version.devid) {
706 case AR5416_DEVID_PCI:
707 case AR5416_DEVID_PCIE:
708 case AR5416_AR9100_DEVID:
709 case AR9160_DEVID_PCI:
710 case AR9280_DEVID_PCI:
711 case AR9280_DEVID_PCIE:
712 case AR9285_DEVID_PCIE:
713 case AR9287_DEVID_PCI:
714 case AR9287_DEVID_PCIE:
715 case AR2427_DEVID_PCIE:
716 case AR9300_DEVID_PCIE:
717 case AR9300_DEVID_AR9485_PCIE:
718 case AR9300_DEVID_AR9330:
719 case AR9300_DEVID_AR9340:
720 case AR9300_DEVID_QCA955X:
721 case AR9300_DEVID_AR9580:
722 case AR9300_DEVID_AR9462:
723 case AR9485_DEVID_AR1111:
724 case AR9300_DEVID_AR9565:
725 break;
726 default:
727 if (common->bus_ops->ath_bus_type == ATH_USB)
728 break;
729 ath_err(common, "Hardware device ID 0x%04x not supported\n",
730 ah->hw_version.devid);
731 return -EOPNOTSUPP;
732 }
733
734 ret = __ath9k_hw_init(ah);
735 if (ret) {
736 ath_err(common,
737 "Unable to initialize hardware; initialization status: %d\n",
738 ret);
739 return ret;
740 }
741
742 return 0;
743 }
744 EXPORT_SYMBOL(ath9k_hw_init);
745
746 static void ath9k_hw_init_qos(struct ath_hw *ah)
747 {
748 ENABLE_REGWRITE_BUFFER(ah);
749
750 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
751 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
752
753 REG_WRITE(ah, AR_QOS_NO_ACK,
754 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
755 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
756 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
757
758 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
759 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
760 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
761 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
762 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
763
764 REGWRITE_BUFFER_FLUSH(ah);
765 }
766
767 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
768 {
769 struct ath_common *common = ath9k_hw_common(ah);
770 int i = 0;
771
772 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
773 udelay(100);
774 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
775
776 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) {
777
778 udelay(100);
779
780 if (WARN_ON_ONCE(i >= 100)) {
781 ath_err(common, "PLL4 meaurement not done\n");
782 break;
783 }
784
785 i++;
786 }
787
788 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
789 }
790 EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc);
791
792 static void ath9k_hw_init_pll(struct ath_hw *ah,
793 struct ath9k_channel *chan)
794 {
795 u32 pll;
796
797 if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
798 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */
799 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
800 AR_CH0_BB_DPLL2_PLL_PWD, 0x1);
801 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
802 AR_CH0_DPLL2_KD, 0x40);
803 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
804 AR_CH0_DPLL2_KI, 0x4);
805
806 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
807 AR_CH0_BB_DPLL1_REFDIV, 0x5);
808 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
809 AR_CH0_BB_DPLL1_NINI, 0x58);
810 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
811 AR_CH0_BB_DPLL1_NFRAC, 0x0);
812
813 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
814 AR_CH0_BB_DPLL2_OUTDIV, 0x1);
815 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
816 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1);
817 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
818 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1);
819
820 /* program BB PLL phase_shift to 0x6 */
821 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
822 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6);
823
824 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
825 AR_CH0_BB_DPLL2_PLL_PWD, 0x0);
826 udelay(1000);
827 } else if (AR_SREV_9330(ah)) {
828 u32 ddr_dpll2, pll_control2, kd;
829
830 if (ah->is_clk_25mhz) {
831 ddr_dpll2 = 0x18e82f01;
832 pll_control2 = 0xe04a3d;
833 kd = 0x1d;
834 } else {
835 ddr_dpll2 = 0x19e82f01;
836 pll_control2 = 0x886666;
837 kd = 0x3d;
838 }
839
840 /* program DDR PLL ki and kd value */
841 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2);
842
843 /* program DDR PLL phase_shift */
844 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3,
845 AR_CH0_DPLL3_PHASE_SHIFT, 0x1);
846
847 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
848 udelay(1000);
849
850 /* program refdiv, nint, frac to RTC register */
851 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2);
852
853 /* program BB PLL kd and ki value */
854 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd);
855 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06);
856
857 /* program BB PLL phase_shift */
858 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
859 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1);
860 } else if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) {
861 u32 regval, pll2_divint, pll2_divfrac, refdiv;
862
863 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
864 udelay(1000);
865
866 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16);
867 udelay(100);
868
869 if (ah->is_clk_25mhz) {
870 pll2_divint = 0x54;
871 pll2_divfrac = 0x1eb85;
872 refdiv = 3;
873 } else {
874 if (AR_SREV_9340(ah)) {
875 pll2_divint = 88;
876 pll2_divfrac = 0;
877 refdiv = 5;
878 } else {
879 pll2_divint = 0x11;
880 pll2_divfrac = 0x26666;
881 refdiv = 1;
882 }
883 }
884
885 regval = REG_READ(ah, AR_PHY_PLL_MODE);
886 regval |= (0x1 << 16);
887 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
888 udelay(100);
889
890 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) |
891 (pll2_divint << 18) | pll2_divfrac);
892 udelay(100);
893
894 regval = REG_READ(ah, AR_PHY_PLL_MODE);
895 if (AR_SREV_9340(ah))
896 regval = (regval & 0x80071fff) | (0x1 << 30) |
897 (0x1 << 13) | (0x4 << 26) | (0x18 << 19);
898 else
899 regval = (regval & 0x80071fff) | (0x3 << 30) |
900 (0x1 << 13) | (0x4 << 26) | (0x60 << 19);
901 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
902 REG_WRITE(ah, AR_PHY_PLL_MODE,
903 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff);
904 udelay(1000);
905 }
906
907 pll = ath9k_hw_compute_pll_control(ah, chan);
908 if (AR_SREV_9565(ah))
909 pll |= 0x40000;
910 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
911
912 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
913 AR_SREV_9550(ah))
914 udelay(1000);
915
916 /* Switch the core clock for ar9271 to 117Mhz */
917 if (AR_SREV_9271(ah)) {
918 udelay(500);
919 REG_WRITE(ah, 0x50040, 0x304);
920 }
921
922 udelay(RTC_PLL_SETTLE_DELAY);
923
924 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
925
926 if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) {
927 if (ah->is_clk_25mhz) {
928 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1);
929 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);
930 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae);
931 } else {
932 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1);
933 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400);
934 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800);
935 }
936 udelay(100);
937 }
938 }
939
940 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
941 enum nl80211_iftype opmode)
942 {
943 u32 sync_default = AR_INTR_SYNC_DEFAULT;
944 u32 imr_reg = AR_IMR_TXERR |
945 AR_IMR_TXURN |
946 AR_IMR_RXERR |
947 AR_IMR_RXORN |
948 AR_IMR_BCNMISC;
949
950 if (AR_SREV_9340(ah) || AR_SREV_9550(ah))
951 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
952
953 if (AR_SREV_9300_20_OR_LATER(ah)) {
954 imr_reg |= AR_IMR_RXOK_HP;
955 if (ah->config.rx_intr_mitigation)
956 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
957 else
958 imr_reg |= AR_IMR_RXOK_LP;
959
960 } else {
961 if (ah->config.rx_intr_mitigation)
962 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
963 else
964 imr_reg |= AR_IMR_RXOK;
965 }
966
967 if (ah->config.tx_intr_mitigation)
968 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
969 else
970 imr_reg |= AR_IMR_TXOK;
971
972 ENABLE_REGWRITE_BUFFER(ah);
973
974 REG_WRITE(ah, AR_IMR, imr_reg);
975 ah->imrs2_reg |= AR_IMR_S2_GTT;
976 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
977
978 if (!AR_SREV_9100(ah)) {
979 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
980 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
981 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
982 }
983
984 REGWRITE_BUFFER_FLUSH(ah);
985
986 if (AR_SREV_9300_20_OR_LATER(ah)) {
987 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
988 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
989 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
990 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
991 }
992 }
993
994 static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us)
995 {
996 u32 val = ath9k_hw_mac_to_clks(ah, us - 2);
997 val = min(val, (u32) 0xFFFF);
998 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val);
999 }
1000
1001 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
1002 {
1003 u32 val = ath9k_hw_mac_to_clks(ah, us);
1004 val = min(val, (u32) 0xFFFF);
1005 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
1006 }
1007
1008 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1009 {
1010 u32 val = ath9k_hw_mac_to_clks(ah, us);
1011 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
1012 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
1013 }
1014
1015 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1016 {
1017 u32 val = ath9k_hw_mac_to_clks(ah, us);
1018 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
1019 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
1020 }
1021
1022 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1023 {
1024 if (tu > 0xFFFF) {
1025 ath_dbg(ath9k_hw_common(ah), XMIT, "bad global tx timeout %u\n",
1026 tu);
1027 ah->globaltxtimeout = (u32) -1;
1028 return false;
1029 } else {
1030 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1031 ah->globaltxtimeout = tu;
1032 return true;
1033 }
1034 }
1035
1036 void ath9k_hw_init_global_settings(struct ath_hw *ah)
1037 {
1038 struct ath_common *common = ath9k_hw_common(ah);
1039 struct ieee80211_conf *conf = &common->hw->conf;
1040 const struct ath9k_channel *chan = ah->curchan;
1041 int acktimeout, ctstimeout, ack_offset = 0;
1042 int slottime;
1043 int sifstime;
1044 int rx_lat = 0, tx_lat = 0, eifs = 0;
1045 u32 reg;
1046
1047 ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n",
1048 ah->misc_mode);
1049
1050 if (!chan)
1051 return;
1052
1053 if (ah->misc_mode != 0)
1054 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode);
1055
1056 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1057 rx_lat = 41;
1058 else
1059 rx_lat = 37;
1060 tx_lat = 54;
1061
1062 if (IS_CHAN_5GHZ(chan))
1063 sifstime = 16;
1064 else
1065 sifstime = 10;
1066
1067 if (IS_CHAN_HALF_RATE(chan)) {
1068 eifs = 175;
1069 rx_lat *= 2;
1070 tx_lat *= 2;
1071 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1072 tx_lat += 11;
1073
1074 sifstime *= 2;
1075 ack_offset = 16;
1076 slottime = 13;
1077 } else if (IS_CHAN_QUARTER_RATE(chan)) {
1078 eifs = 340;
1079 rx_lat = (rx_lat * 4) - 1;
1080 tx_lat *= 4;
1081 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1082 tx_lat += 22;
1083
1084 sifstime *= 4;
1085 ack_offset = 32;
1086 slottime = 21;
1087 } else {
1088 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1089 eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO;
1090 reg = AR_USEC_ASYNC_FIFO;
1091 } else {
1092 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/
1093 common->clockrate;
1094 reg = REG_READ(ah, AR_USEC);
1095 }
1096 rx_lat = MS(reg, AR_USEC_RX_LAT);
1097 tx_lat = MS(reg, AR_USEC_TX_LAT);
1098
1099 slottime = ah->slottime;
1100 }
1101
1102 /* As defined by IEEE 802.11-2007 17.3.8.6 */
1103 acktimeout = slottime + sifstime + 3 * ah->coverage_class + ack_offset;
1104 ctstimeout = acktimeout;
1105
1106 /*
1107 * Workaround for early ACK timeouts, add an offset to match the
1108 * initval's 64us ack timeout value. Use 48us for the CTS timeout.
1109 * This was initially only meant to work around an issue with delayed
1110 * BA frames in some implementations, but it has been found to fix ACK
1111 * timeout issues in other cases as well.
1112 */
1113 if (conf->chandef.chan &&
1114 conf->chandef.chan->band == IEEE80211_BAND_2GHZ &&
1115 !IS_CHAN_HALF_RATE(chan) && !IS_CHAN_QUARTER_RATE(chan)) {
1116 acktimeout += 64 - sifstime - ah->slottime;
1117 ctstimeout += 48 - sifstime - ah->slottime;
1118 }
1119
1120
1121 ath9k_hw_set_sifs_time(ah, sifstime);
1122 ath9k_hw_setslottime(ah, slottime);
1123 ath9k_hw_set_ack_timeout(ah, acktimeout);
1124 ath9k_hw_set_cts_timeout(ah, ctstimeout);
1125 if (ah->globaltxtimeout != (u32) -1)
1126 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1127
1128 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs));
1129 REG_RMW(ah, AR_USEC,
1130 (common->clockrate - 1) |
1131 SM(rx_lat, AR_USEC_RX_LAT) |
1132 SM(tx_lat, AR_USEC_TX_LAT),
1133 AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC);
1134
1135 }
1136 EXPORT_SYMBOL(ath9k_hw_init_global_settings);
1137
1138 void ath9k_hw_deinit(struct ath_hw *ah)
1139 {
1140 struct ath_common *common = ath9k_hw_common(ah);
1141
1142 if (common->state < ATH_HW_INITIALIZED)
1143 return;
1144
1145 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1146 }
1147 EXPORT_SYMBOL(ath9k_hw_deinit);
1148
1149 /*******/
1150 /* INI */
1151 /*******/
1152
1153 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
1154 {
1155 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1156
1157 if (IS_CHAN_B(chan))
1158 ctl |= CTL_11B;
1159 else if (IS_CHAN_G(chan))
1160 ctl |= CTL_11G;
1161 else
1162 ctl |= CTL_11A;
1163
1164 return ctl;
1165 }
1166
1167 /****************************************/
1168 /* Reset and Channel Switching Routines */
1169 /****************************************/
1170
1171 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1172 {
1173 struct ath_common *common = ath9k_hw_common(ah);
1174
1175 ENABLE_REGWRITE_BUFFER(ah);
1176
1177 /*
1178 * set AHB_MODE not to do cacheline prefetches
1179 */
1180 if (!AR_SREV_9300_20_OR_LATER(ah))
1181 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
1182
1183 /*
1184 * let mac dma reads be in 128 byte chunks
1185 */
1186 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK);
1187
1188 REGWRITE_BUFFER_FLUSH(ah);
1189
1190 /*
1191 * Restore TX Trigger Level to its pre-reset value.
1192 * The initial value depends on whether aggregation is enabled, and is
1193 * adjusted whenever underruns are detected.
1194 */
1195 if (!AR_SREV_9300_20_OR_LATER(ah))
1196 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1197
1198 ENABLE_REGWRITE_BUFFER(ah);
1199
1200 /*
1201 * let mac dma writes be in 128 byte chunks
1202 */
1203 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK);
1204
1205 /*
1206 * Setup receive FIFO threshold to hold off TX activities
1207 */
1208 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1209
1210 if (AR_SREV_9300_20_OR_LATER(ah)) {
1211 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
1212 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
1213
1214 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
1215 ah->caps.rx_status_len);
1216 }
1217
1218 /*
1219 * reduce the number of usable entries in PCU TXBUF to avoid
1220 * wrap around issues.
1221 */
1222 if (AR_SREV_9285(ah)) {
1223 /* For AR9285 the number of Fifos are reduced to half.
1224 * So set the usable tx buf size also to half to
1225 * avoid data/delimiter underruns
1226 */
1227 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1228 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1229 } else if (!AR_SREV_9271(ah)) {
1230 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1231 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1232 }
1233
1234 REGWRITE_BUFFER_FLUSH(ah);
1235
1236 if (AR_SREV_9300_20_OR_LATER(ah))
1237 ath9k_hw_reset_txstatus_ring(ah);
1238 }
1239
1240 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1241 {
1242 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC;
1243 u32 set = AR_STA_ID1_KSRCH_MODE;
1244
1245 switch (opmode) {
1246 case NL80211_IFTYPE_ADHOC:
1247 case NL80211_IFTYPE_MESH_POINT:
1248 set |= AR_STA_ID1_ADHOC;
1249 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1250 break;
1251 case NL80211_IFTYPE_AP:
1252 set |= AR_STA_ID1_STA_AP;
1253 /* fall through */
1254 case NL80211_IFTYPE_STATION:
1255 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1256 break;
1257 default:
1258 if (!ah->is_monitoring)
1259 set = 0;
1260 break;
1261 }
1262 REG_RMW(ah, AR_STA_ID1, set, mask);
1263 }
1264
1265 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1266 u32 *coef_mantissa, u32 *coef_exponent)
1267 {
1268 u32 coef_exp, coef_man;
1269
1270 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1271 if ((coef_scaled >> coef_exp) & 0x1)
1272 break;
1273
1274 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1275
1276 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1277
1278 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1279 *coef_exponent = coef_exp - 16;
1280 }
1281
1282 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1283 {
1284 u32 rst_flags;
1285 u32 tmpReg;
1286
1287 if (AR_SREV_9100(ah)) {
1288 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK,
1289 AR_RTC_DERIVED_CLK_PERIOD, 1);
1290 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1291 }
1292
1293 ENABLE_REGWRITE_BUFFER(ah);
1294
1295 if (AR_SREV_9300_20_OR_LATER(ah)) {
1296 REG_WRITE(ah, AR_WA, ah->WARegVal);
1297 udelay(10);
1298 }
1299
1300 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1301 AR_RTC_FORCE_WAKE_ON_INT);
1302
1303 if (AR_SREV_9100(ah)) {
1304 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1305 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1306 } else {
1307 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1308 if (tmpReg &
1309 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1310 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1311 u32 val;
1312 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1313
1314 val = AR_RC_HOSTIF;
1315 if (!AR_SREV_9300_20_OR_LATER(ah))
1316 val |= AR_RC_AHB;
1317 REG_WRITE(ah, AR_RC, val);
1318
1319 } else if (!AR_SREV_9300_20_OR_LATER(ah))
1320 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1321
1322 rst_flags = AR_RTC_RC_MAC_WARM;
1323 if (type == ATH9K_RESET_COLD)
1324 rst_flags |= AR_RTC_RC_MAC_COLD;
1325 }
1326
1327 if (AR_SREV_9330(ah)) {
1328 int npend = 0;
1329 int i;
1330
1331 /* AR9330 WAR:
1332 * call external reset function to reset WMAC if:
1333 * - doing a cold reset
1334 * - we have pending frames in the TX queues
1335 */
1336
1337 for (i = 0; i < AR_NUM_QCU; i++) {
1338 npend = ath9k_hw_numtxpending(ah, i);
1339 if (npend)
1340 break;
1341 }
1342
1343 if (ah->external_reset &&
1344 (npend || type == ATH9K_RESET_COLD)) {
1345 int reset_err = 0;
1346
1347 ath_dbg(ath9k_hw_common(ah), RESET,
1348 "reset MAC via external reset\n");
1349
1350 reset_err = ah->external_reset();
1351 if (reset_err) {
1352 ath_err(ath9k_hw_common(ah),
1353 "External reset failed, err=%d\n",
1354 reset_err);
1355 return false;
1356 }
1357
1358 REG_WRITE(ah, AR_RTC_RESET, 1);
1359 }
1360 }
1361
1362 if (ath9k_hw_mci_is_enabled(ah))
1363 ar9003_mci_check_gpm_offset(ah);
1364
1365 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1366
1367 REGWRITE_BUFFER_FLUSH(ah);
1368
1369 udelay(50);
1370
1371 REG_WRITE(ah, AR_RTC_RC, 0);
1372 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1373 ath_dbg(ath9k_hw_common(ah), RESET, "RTC stuck in MAC reset\n");
1374 return false;
1375 }
1376
1377 if (!AR_SREV_9100(ah))
1378 REG_WRITE(ah, AR_RC, 0);
1379
1380 if (AR_SREV_9100(ah))
1381 udelay(50);
1382
1383 return true;
1384 }
1385
1386 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1387 {
1388 ENABLE_REGWRITE_BUFFER(ah);
1389
1390 if (AR_SREV_9300_20_OR_LATER(ah)) {
1391 REG_WRITE(ah, AR_WA, ah->WARegVal);
1392 udelay(10);
1393 }
1394
1395 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1396 AR_RTC_FORCE_WAKE_ON_INT);
1397
1398 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1399 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1400
1401 REG_WRITE(ah, AR_RTC_RESET, 0);
1402
1403 REGWRITE_BUFFER_FLUSH(ah);
1404
1405 if (!AR_SREV_9300_20_OR_LATER(ah))
1406 udelay(2);
1407
1408 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1409 REG_WRITE(ah, AR_RC, 0);
1410
1411 REG_WRITE(ah, AR_RTC_RESET, 1);
1412
1413 if (!ath9k_hw_wait(ah,
1414 AR_RTC_STATUS,
1415 AR_RTC_STATUS_M,
1416 AR_RTC_STATUS_ON,
1417 AH_WAIT_TIMEOUT)) {
1418 ath_dbg(ath9k_hw_common(ah), RESET, "RTC not waking up\n");
1419 return false;
1420 }
1421
1422 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1423 }
1424
1425 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1426 {
1427 bool ret = false;
1428
1429 if (AR_SREV_9300_20_OR_LATER(ah)) {
1430 REG_WRITE(ah, AR_WA, ah->WARegVal);
1431 udelay(10);
1432 }
1433
1434 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1435 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1436
1437 if (!ah->reset_power_on)
1438 type = ATH9K_RESET_POWER_ON;
1439
1440 switch (type) {
1441 case ATH9K_RESET_POWER_ON:
1442 ret = ath9k_hw_set_reset_power_on(ah);
1443 if (ret)
1444 ah->reset_power_on = true;
1445 break;
1446 case ATH9K_RESET_WARM:
1447 case ATH9K_RESET_COLD:
1448 ret = ath9k_hw_set_reset(ah, type);
1449 break;
1450 default:
1451 break;
1452 }
1453
1454 return ret;
1455 }
1456
1457 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1458 struct ath9k_channel *chan)
1459 {
1460 int reset_type = ATH9K_RESET_WARM;
1461
1462 if (AR_SREV_9280(ah)) {
1463 if (ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1464 reset_type = ATH9K_RESET_POWER_ON;
1465 else
1466 reset_type = ATH9K_RESET_COLD;
1467 } else if (ah->chip_fullsleep || REG_READ(ah, AR_Q_TXE) ||
1468 (REG_READ(ah, AR_CR) & AR_CR_RXE))
1469 reset_type = ATH9K_RESET_COLD;
1470
1471 if (!ath9k_hw_set_reset_reg(ah, reset_type))
1472 return false;
1473
1474 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1475 return false;
1476
1477 ah->chip_fullsleep = false;
1478
1479 if (AR_SREV_9330(ah))
1480 ar9003_hw_internal_regulator_apply(ah);
1481 ath9k_hw_init_pll(ah, chan);
1482 ath9k_hw_set_rfmode(ah, chan);
1483
1484 return true;
1485 }
1486
1487 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1488 struct ath9k_channel *chan)
1489 {
1490 struct ath_common *common = ath9k_hw_common(ah);
1491 u32 qnum;
1492 int r;
1493 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1494 bool band_switch, mode_diff;
1495 u8 ini_reloaded;
1496
1497 band_switch = (chan->channelFlags & (CHANNEL_2GHZ | CHANNEL_5GHZ)) !=
1498 (ah->curchan->channelFlags & (CHANNEL_2GHZ |
1499 CHANNEL_5GHZ));
1500 mode_diff = (chan->chanmode != ah->curchan->chanmode);
1501
1502 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1503 if (ath9k_hw_numtxpending(ah, qnum)) {
1504 ath_dbg(common, QUEUE,
1505 "Transmit frames pending on queue %d\n", qnum);
1506 return false;
1507 }
1508 }
1509
1510 if (!ath9k_hw_rfbus_req(ah)) {
1511 ath_err(common, "Could not kill baseband RX\n");
1512 return false;
1513 }
1514
1515 if (edma && (band_switch || mode_diff)) {
1516 ath9k_hw_mark_phy_inactive(ah);
1517 udelay(5);
1518
1519 ath9k_hw_init_pll(ah, NULL);
1520
1521 if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) {
1522 ath_err(common, "Failed to do fast channel change\n");
1523 return false;
1524 }
1525 }
1526
1527 ath9k_hw_set_channel_regs(ah, chan);
1528
1529 r = ath9k_hw_rf_set_freq(ah, chan);
1530 if (r) {
1531 ath_err(common, "Failed to set channel\n");
1532 return false;
1533 }
1534 ath9k_hw_set_clockrate(ah);
1535 ath9k_hw_apply_txpower(ah, chan, false);
1536 ath9k_hw_rfbus_done(ah);
1537
1538 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1539 ath9k_hw_set_delta_slope(ah, chan);
1540
1541 ath9k_hw_spur_mitigate_freq(ah, chan);
1542
1543 if (edma && (band_switch || mode_diff)) {
1544 ah->ah_flags |= AH_FASTCC;
1545 if (band_switch || ini_reloaded)
1546 ah->eep_ops->set_board_values(ah, chan);
1547
1548 ath9k_hw_init_bb(ah, chan);
1549
1550 if (band_switch || ini_reloaded)
1551 ath9k_hw_init_cal(ah, chan);
1552 ah->ah_flags &= ~AH_FASTCC;
1553 }
1554
1555 return true;
1556 }
1557
1558 static void ath9k_hw_apply_gpio_override(struct ath_hw *ah)
1559 {
1560 u32 gpio_mask = ah->gpio_mask;
1561 int i;
1562
1563 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) {
1564 if (!(gpio_mask & 1))
1565 continue;
1566
1567 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1568 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i)));
1569 }
1570 }
1571
1572 static bool ath9k_hw_check_dcs(u32 dma_dbg, u32 num_dcu_states,
1573 int *hang_state, int *hang_pos)
1574 {
1575 static u32 dcu_chain_state[] = {5, 6, 9}; /* DCU chain stuck states */
1576 u32 chain_state, dcs_pos, i;
1577
1578 for (dcs_pos = 0; dcs_pos < num_dcu_states; dcs_pos++) {
1579 chain_state = (dma_dbg >> (5 * dcs_pos)) & 0x1f;
1580 for (i = 0; i < 3; i++) {
1581 if (chain_state == dcu_chain_state[i]) {
1582 *hang_state = chain_state;
1583 *hang_pos = dcs_pos;
1584 return true;
1585 }
1586 }
1587 }
1588 return false;
1589 }
1590
1591 #define DCU_COMPLETE_STATE 1
1592 #define DCU_COMPLETE_STATE_MASK 0x3
1593 #define NUM_STATUS_READS 50
1594 static bool ath9k_hw_detect_mac_hang(struct ath_hw *ah)
1595 {
1596 u32 chain_state, comp_state, dcs_reg = AR_DMADBG_4;
1597 u32 i, hang_pos, hang_state, num_state = 6;
1598
1599 comp_state = REG_READ(ah, AR_DMADBG_6);
1600
1601 if ((comp_state & DCU_COMPLETE_STATE_MASK) != DCU_COMPLETE_STATE) {
1602 ath_dbg(ath9k_hw_common(ah), RESET,
1603 "MAC Hang signature not found at DCU complete\n");
1604 return false;
1605 }
1606
1607 chain_state = REG_READ(ah, dcs_reg);
1608 if (ath9k_hw_check_dcs(chain_state, num_state, &hang_state, &hang_pos))
1609 goto hang_check_iter;
1610
1611 dcs_reg = AR_DMADBG_5;
1612 num_state = 4;
1613 chain_state = REG_READ(ah, dcs_reg);
1614 if (ath9k_hw_check_dcs(chain_state, num_state, &hang_state, &hang_pos))
1615 goto hang_check_iter;
1616
1617 ath_dbg(ath9k_hw_common(ah), RESET,
1618 "MAC Hang signature 1 not found\n");
1619 return false;
1620
1621 hang_check_iter:
1622 ath_dbg(ath9k_hw_common(ah), RESET,
1623 "DCU registers: chain %08x complete %08x Hang: state %d pos %d\n",
1624 chain_state, comp_state, hang_state, hang_pos);
1625
1626 for (i = 0; i < NUM_STATUS_READS; i++) {
1627 chain_state = REG_READ(ah, dcs_reg);
1628 chain_state = (chain_state >> (5 * hang_pos)) & 0x1f;
1629 comp_state = REG_READ(ah, AR_DMADBG_6);
1630
1631 if (((comp_state & DCU_COMPLETE_STATE_MASK) !=
1632 DCU_COMPLETE_STATE) ||
1633 (chain_state != hang_state))
1634 return false;
1635 }
1636
1637 ath_dbg(ath9k_hw_common(ah), RESET, "MAC Hang signature 1 found\n");
1638
1639 return true;
1640 }
1641
1642 bool ath9k_hw_check_alive(struct ath_hw *ah)
1643 {
1644 int count = 50;
1645 u32 reg;
1646
1647 if (AR_SREV_9300(ah))
1648 return !ath9k_hw_detect_mac_hang(ah);
1649
1650 if (AR_SREV_9285_12_OR_LATER(ah))
1651 return true;
1652
1653 do {
1654 reg = REG_READ(ah, AR_OBS_BUS_1);
1655
1656 if ((reg & 0x7E7FFFEF) == 0x00702400)
1657 continue;
1658
1659 switch (reg & 0x7E000B00) {
1660 case 0x1E000000:
1661 case 0x52000B00:
1662 case 0x18000B00:
1663 continue;
1664 default:
1665 return true;
1666 }
1667 } while (count-- > 0);
1668
1669 return false;
1670 }
1671 EXPORT_SYMBOL(ath9k_hw_check_alive);
1672
1673 static void ath9k_hw_init_mfp(struct ath_hw *ah)
1674 {
1675 /* Setup MFP options for CCMP */
1676 if (AR_SREV_9280_20_OR_LATER(ah)) {
1677 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1678 * frames when constructing CCMP AAD. */
1679 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1680 0xc7ff);
1681 ah->sw_mgmt_crypto = false;
1682 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1683 /* Disable hardware crypto for management frames */
1684 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1685 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1686 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1687 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1688 ah->sw_mgmt_crypto = true;
1689 } else {
1690 ah->sw_mgmt_crypto = true;
1691 }
1692 }
1693
1694 static void ath9k_hw_reset_opmode(struct ath_hw *ah,
1695 u32 macStaId1, u32 saveDefAntenna)
1696 {
1697 struct ath_common *common = ath9k_hw_common(ah);
1698
1699 ENABLE_REGWRITE_BUFFER(ah);
1700
1701 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
1702 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
1703 | macStaId1
1704 | AR_STA_ID1_RTS_USE_DEF
1705 | (ah->config.ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
1706 | ah->sta_id1_defaults);
1707 ath_hw_setbssidmask(common);
1708 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1709 ath9k_hw_write_associd(ah);
1710 REG_WRITE(ah, AR_ISR, ~0);
1711 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1712
1713 REGWRITE_BUFFER_FLUSH(ah);
1714
1715 ath9k_hw_set_operating_mode(ah, ah->opmode);
1716 }
1717
1718 static void ath9k_hw_init_queues(struct ath_hw *ah)
1719 {
1720 int i;
1721
1722 ENABLE_REGWRITE_BUFFER(ah);
1723
1724 for (i = 0; i < AR_NUM_DCU; i++)
1725 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1726
1727 REGWRITE_BUFFER_FLUSH(ah);
1728
1729 ah->intr_txqs = 0;
1730 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1731 ath9k_hw_resettxqueue(ah, i);
1732 }
1733
1734 /*
1735 * For big endian systems turn on swapping for descriptors
1736 */
1737 static void ath9k_hw_init_desc(struct ath_hw *ah)
1738 {
1739 struct ath_common *common = ath9k_hw_common(ah);
1740
1741 if (AR_SREV_9100(ah)) {
1742 u32 mask;
1743 mask = REG_READ(ah, AR_CFG);
1744 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1745 ath_dbg(common, RESET, "CFG Byte Swap Set 0x%x\n",
1746 mask);
1747 } else {
1748 mask = INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1749 REG_WRITE(ah, AR_CFG, mask);
1750 ath_dbg(common, RESET, "Setting CFG 0x%x\n",
1751 REG_READ(ah, AR_CFG));
1752 }
1753 } else {
1754 if (common->bus_ops->ath_bus_type == ATH_USB) {
1755 /* Configure AR9271 target WLAN */
1756 if (AR_SREV_9271(ah))
1757 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1758 else
1759 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1760 }
1761 #ifdef __BIG_ENDIAN
1762 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah) ||
1763 AR_SREV_9550(ah))
1764 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0);
1765 else
1766 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1767 #endif
1768 }
1769 }
1770
1771 /*
1772 * Fast channel change:
1773 * (Change synthesizer based on channel freq without resetting chip)
1774 *
1775 * Don't do FCC when
1776 * - Flag is not set
1777 * - Chip is just coming out of full sleep
1778 * - Channel to be set is same as current channel
1779 * - Channel flags are different, (eg.,moving from 2GHz to 5GHz channel)
1780 */
1781 static int ath9k_hw_do_fastcc(struct ath_hw *ah, struct ath9k_channel *chan)
1782 {
1783 struct ath_common *common = ath9k_hw_common(ah);
1784 int ret;
1785
1786 if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI)
1787 goto fail;
1788
1789 if (ah->chip_fullsleep)
1790 goto fail;
1791
1792 if (!ah->curchan)
1793 goto fail;
1794
1795 if (chan->channel == ah->curchan->channel)
1796 goto fail;
1797
1798 if ((ah->curchan->channelFlags | chan->channelFlags) &
1799 (CHANNEL_HALF | CHANNEL_QUARTER))
1800 goto fail;
1801
1802 if ((chan->channelFlags & CHANNEL_ALL) !=
1803 (ah->curchan->channelFlags & CHANNEL_ALL))
1804 goto fail;
1805
1806 if (!ath9k_hw_check_alive(ah))
1807 goto fail;
1808
1809 /*
1810 * For AR9462, make sure that calibration data for
1811 * re-using are present.
1812 */
1813 if (AR_SREV_9462(ah) && (ah->caldata &&
1814 (!ah->caldata->done_txiqcal_once ||
1815 !ah->caldata->done_txclcal_once ||
1816 !ah->caldata->rtt_done)))
1817 goto fail;
1818
1819 ath_dbg(common, RESET, "FastChannelChange for %d -> %d\n",
1820 ah->curchan->channel, chan->channel);
1821
1822 ret = ath9k_hw_channel_change(ah, chan);
1823 if (!ret)
1824 goto fail;
1825
1826 if (ath9k_hw_mci_is_enabled(ah))
1827 ar9003_mci_2g5g_switch(ah, false);
1828
1829 ath9k_hw_loadnf(ah, ah->curchan);
1830 ath9k_hw_start_nfcal(ah, true);
1831
1832 if (AR_SREV_9271(ah))
1833 ar9002_hw_load_ani_reg(ah, chan);
1834
1835 return 0;
1836 fail:
1837 return -EINVAL;
1838 }
1839
1840 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1841 struct ath9k_hw_cal_data *caldata, bool fastcc)
1842 {
1843 struct ath_common *common = ath9k_hw_common(ah);
1844 u32 saveLedState;
1845 u32 saveDefAntenna;
1846 u32 macStaId1;
1847 u64 tsf = 0;
1848 int r;
1849 bool start_mci_reset = false;
1850 bool save_fullsleep = ah->chip_fullsleep;
1851
1852 if (ath9k_hw_mci_is_enabled(ah)) {
1853 start_mci_reset = ar9003_mci_start_reset(ah, chan);
1854 if (start_mci_reset)
1855 return 0;
1856 }
1857
1858 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1859 return -EIO;
1860
1861 if (ah->curchan && !ah->chip_fullsleep)
1862 ath9k_hw_getnf(ah, ah->curchan);
1863
1864 ah->caldata = caldata;
1865 if (caldata && (chan->channel != caldata->channel ||
1866 chan->channelFlags != caldata->channelFlags)) {
1867 /* Operating channel changed, reset channel calibration data */
1868 memset(caldata, 0, sizeof(*caldata));
1869 ath9k_init_nfcal_hist_buffer(ah, chan);
1870 } else if (caldata) {
1871 caldata->paprd_packet_sent = false;
1872 }
1873 ah->noise = ath9k_hw_getchan_noise(ah, chan);
1874
1875 if (fastcc) {
1876 r = ath9k_hw_do_fastcc(ah, chan);
1877 if (!r)
1878 return r;
1879 }
1880
1881 if (ath9k_hw_mci_is_enabled(ah))
1882 ar9003_mci_stop_bt(ah, save_fullsleep);
1883
1884 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1885 if (saveDefAntenna == 0)
1886 saveDefAntenna = 1;
1887
1888 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1889
1890 /* For chips on which RTC reset is done, save TSF before it gets cleared */
1891 if (AR_SREV_9100(ah) ||
1892 (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)))
1893 tsf = ath9k_hw_gettsf64(ah);
1894
1895 saveLedState = REG_READ(ah, AR_CFG_LED) &
1896 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1897 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1898
1899 ath9k_hw_mark_phy_inactive(ah);
1900
1901 ah->paprd_table_write_done = false;
1902
1903 /* Only required on the first reset */
1904 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1905 REG_WRITE(ah,
1906 AR9271_RESET_POWER_DOWN_CONTROL,
1907 AR9271_RADIO_RF_RST);
1908 udelay(50);
1909 }
1910
1911 if (!ath9k_hw_chip_reset(ah, chan)) {
1912 ath_err(common, "Chip reset failed\n");
1913 return -EINVAL;
1914 }
1915
1916 /* Only required on the first reset */
1917 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1918 ah->htc_reset_init = false;
1919 REG_WRITE(ah,
1920 AR9271_RESET_POWER_DOWN_CONTROL,
1921 AR9271_GATE_MAC_CTL);
1922 udelay(50);
1923 }
1924
1925 /* Restore TSF */
1926 if (tsf)
1927 ath9k_hw_settsf64(ah, tsf);
1928
1929 if (AR_SREV_9280_20_OR_LATER(ah))
1930 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1931
1932 if (!AR_SREV_9300_20_OR_LATER(ah))
1933 ar9002_hw_enable_async_fifo(ah);
1934
1935 r = ath9k_hw_process_ini(ah, chan);
1936 if (r)
1937 return r;
1938
1939 if (ath9k_hw_mci_is_enabled(ah))
1940 ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep);
1941
1942 /*
1943 * Some AR91xx SoC devices frequently fail to accept TSF writes
1944 * right after the chip reset. When that happens, write a new
1945 * value after the initvals have been applied, with an offset
1946 * based on measured time difference
1947 */
1948 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
1949 tsf += 1500;
1950 ath9k_hw_settsf64(ah, tsf);
1951 }
1952
1953 ath9k_hw_init_mfp(ah);
1954
1955 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1956 ath9k_hw_set_delta_slope(ah, chan);
1957
1958 ath9k_hw_spur_mitigate_freq(ah, chan);
1959 ah->eep_ops->set_board_values(ah, chan);
1960
1961 ath9k_hw_reset_opmode(ah, macStaId1, saveDefAntenna);
1962
1963 r = ath9k_hw_rf_set_freq(ah, chan);
1964 if (r)
1965 return r;
1966
1967 ath9k_hw_set_clockrate(ah);
1968
1969 ath9k_hw_init_queues(ah);
1970 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
1971 ath9k_hw_ani_cache_ini_regs(ah);
1972 ath9k_hw_init_qos(ah);
1973
1974 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1975 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
1976
1977 ath9k_hw_init_global_settings(ah);
1978
1979 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1980 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
1981 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
1982 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
1983 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
1984 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1985 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
1986 }
1987
1988 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
1989
1990 ath9k_hw_set_dma(ah);
1991
1992 if (!ath9k_hw_mci_is_enabled(ah))
1993 REG_WRITE(ah, AR_OBS, 8);
1994
1995 if (ah->config.rx_intr_mitigation) {
1996 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
1997 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
1998 }
1999
2000 if (ah->config.tx_intr_mitigation) {
2001 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
2002 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
2003 }
2004
2005 ath9k_hw_init_bb(ah, chan);
2006
2007 if (caldata) {
2008 caldata->done_txiqcal_once = false;
2009 caldata->done_txclcal_once = false;
2010 }
2011 if (!ath9k_hw_init_cal(ah, chan))
2012 return -EIO;
2013
2014 if (ath9k_hw_mci_is_enabled(ah) && ar9003_mci_end_reset(ah, chan, caldata))
2015 return -EIO;
2016
2017 ENABLE_REGWRITE_BUFFER(ah);
2018
2019 ath9k_hw_restore_chainmask(ah);
2020 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2021
2022 REGWRITE_BUFFER_FLUSH(ah);
2023
2024 ath9k_hw_init_desc(ah);
2025
2026 if (ath9k_hw_btcoex_is_enabled(ah))
2027 ath9k_hw_btcoex_enable(ah);
2028
2029 if (ath9k_hw_mci_is_enabled(ah))
2030 ar9003_mci_check_bt(ah);
2031
2032 ath9k_hw_loadnf(ah, chan);
2033 ath9k_hw_start_nfcal(ah, true);
2034
2035 if (AR_SREV_9300_20_OR_LATER(ah)) {
2036 ar9003_hw_bb_watchdog_config(ah);
2037 ar9003_hw_disable_phy_restart(ah);
2038 }
2039
2040 ath9k_hw_apply_gpio_override(ah);
2041
2042 if (AR_SREV_9565(ah) && ah->shared_chain_lnadiv)
2043 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, AR_BTCOEX_WL_LNADIV_FORCE_ON);
2044
2045 return 0;
2046 }
2047 EXPORT_SYMBOL(ath9k_hw_reset);
2048
2049 /******************************/
2050 /* Power Management (Chipset) */
2051 /******************************/
2052
2053 /*
2054 * Notify Power Mgt is disabled in self-generated frames.
2055 * If requested, force chip to sleep.
2056 */
2057 static void ath9k_set_power_sleep(struct ath_hw *ah)
2058 {
2059 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2060
2061 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
2062 REG_CLR_BIT(ah, AR_TIMER_MODE, 0xff);
2063 REG_CLR_BIT(ah, AR_NDP2_TIMER_MODE, 0xff);
2064 REG_CLR_BIT(ah, AR_SLP32_INC, 0xfffff);
2065 /* xxx Required for WLAN only case ? */
2066 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0);
2067 udelay(100);
2068 }
2069
2070 /*
2071 * Clear the RTC force wake bit to allow the
2072 * mac to go to sleep.
2073 */
2074 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
2075
2076 if (ath9k_hw_mci_is_enabled(ah))
2077 udelay(100);
2078
2079 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
2080 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2081
2082 /* Shutdown chip. Active low */
2083 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) {
2084 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN);
2085 udelay(2);
2086 }
2087
2088 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
2089 if (AR_SREV_9300_20_OR_LATER(ah))
2090 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
2091 }
2092
2093 /*
2094 * Notify Power Management is enabled in self-generating
2095 * frames. If request, set power mode of chip to
2096 * auto/normal. Duration in units of 128us (1/8 TU).
2097 */
2098 static void ath9k_set_power_network_sleep(struct ath_hw *ah)
2099 {
2100 struct ath9k_hw_capabilities *pCap = &ah->caps;
2101
2102 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2103
2104 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2105 /* Set WakeOnInterrupt bit; clear ForceWake bit */
2106 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2107 AR_RTC_FORCE_WAKE_ON_INT);
2108 } else {
2109
2110 /* When chip goes into network sleep, it could be waken
2111 * up by MCI_INT interrupt caused by BT's HW messages
2112 * (LNA_xxx, CONT_xxx) which chould be in a very fast
2113 * rate (~100us). This will cause chip to leave and
2114 * re-enter network sleep mode frequently, which in
2115 * consequence will have WLAN MCI HW to generate lots of
2116 * SYS_WAKING and SYS_SLEEPING messages which will make
2117 * BT CPU to busy to process.
2118 */
2119 if (ath9k_hw_mci_is_enabled(ah))
2120 REG_CLR_BIT(ah, AR_MCI_INTERRUPT_RX_MSG_EN,
2121 AR_MCI_INTERRUPT_RX_HW_MSG_MASK);
2122 /*
2123 * Clear the RTC force wake bit to allow the
2124 * mac to go to sleep.
2125 */
2126 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
2127
2128 if (ath9k_hw_mci_is_enabled(ah))
2129 udelay(30);
2130 }
2131
2132 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
2133 if (AR_SREV_9300_20_OR_LATER(ah))
2134 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
2135 }
2136
2137 static bool ath9k_hw_set_power_awake(struct ath_hw *ah)
2138 {
2139 u32 val;
2140 int i;
2141
2142 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */
2143 if (AR_SREV_9300_20_OR_LATER(ah)) {
2144 REG_WRITE(ah, AR_WA, ah->WARegVal);
2145 udelay(10);
2146 }
2147
2148 if ((REG_READ(ah, AR_RTC_STATUS) &
2149 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2150 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
2151 return false;
2152 }
2153 if (!AR_SREV_9300_20_OR_LATER(ah))
2154 ath9k_hw_init_pll(ah, NULL);
2155 }
2156 if (AR_SREV_9100(ah))
2157 REG_SET_BIT(ah, AR_RTC_RESET,
2158 AR_RTC_RESET_EN);
2159
2160 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2161 AR_RTC_FORCE_WAKE_EN);
2162 udelay(50);
2163
2164 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2165 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2166 if (val == AR_RTC_STATUS_ON)
2167 break;
2168 udelay(50);
2169 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2170 AR_RTC_FORCE_WAKE_EN);
2171 }
2172 if (i == 0) {
2173 ath_err(ath9k_hw_common(ah),
2174 "Failed to wakeup in %uus\n",
2175 POWER_UP_TIME / 20);
2176 return false;
2177 }
2178
2179 if (ath9k_hw_mci_is_enabled(ah))
2180 ar9003_mci_set_power_awake(ah);
2181
2182 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2183
2184 return true;
2185 }
2186
2187 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2188 {
2189 struct ath_common *common = ath9k_hw_common(ah);
2190 int status = true;
2191 static const char *modes[] = {
2192 "AWAKE",
2193 "FULL-SLEEP",
2194 "NETWORK SLEEP",
2195 "UNDEFINED"
2196 };
2197
2198 if (ah->power_mode == mode)
2199 return status;
2200
2201 ath_dbg(common, RESET, "%s -> %s\n",
2202 modes[ah->power_mode], modes[mode]);
2203
2204 switch (mode) {
2205 case ATH9K_PM_AWAKE:
2206 status = ath9k_hw_set_power_awake(ah);
2207 break;
2208 case ATH9K_PM_FULL_SLEEP:
2209 if (ath9k_hw_mci_is_enabled(ah))
2210 ar9003_mci_set_full_sleep(ah);
2211
2212 ath9k_set_power_sleep(ah);
2213 ah->chip_fullsleep = true;
2214 break;
2215 case ATH9K_PM_NETWORK_SLEEP:
2216 ath9k_set_power_network_sleep(ah);
2217 break;
2218 default:
2219 ath_err(common, "Unknown power mode %u\n", mode);
2220 return false;
2221 }
2222 ah->power_mode = mode;
2223
2224 /*
2225 * XXX: If this warning never comes up after a while then
2226 * simply keep the ATH_DBG_WARN_ON_ONCE() but make
2227 * ath9k_hw_setpower() return type void.
2228 */
2229
2230 if (!(ah->ah_flags & AH_UNPLUGGED))
2231 ATH_DBG_WARN_ON_ONCE(!status);
2232
2233 return status;
2234 }
2235 EXPORT_SYMBOL(ath9k_hw_setpower);
2236
2237 /*******************/
2238 /* Beacon Handling */
2239 /*******************/
2240
2241 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
2242 {
2243 int flags = 0;
2244
2245 ENABLE_REGWRITE_BUFFER(ah);
2246
2247 switch (ah->opmode) {
2248 case NL80211_IFTYPE_ADHOC:
2249 case NL80211_IFTYPE_MESH_POINT:
2250 REG_SET_BIT(ah, AR_TXCFG,
2251 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
2252 REG_WRITE(ah, AR_NEXT_NDP_TIMER, next_beacon +
2253 TU_TO_USEC(ah->atim_window ? ah->atim_window : 1));
2254 flags |= AR_NDP_TIMER_EN;
2255 case NL80211_IFTYPE_AP:
2256 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon);
2257 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon -
2258 TU_TO_USEC(ah->config.dma_beacon_response_time));
2259 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon -
2260 TU_TO_USEC(ah->config.sw_beacon_response_time));
2261 flags |=
2262 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
2263 break;
2264 default:
2265 ath_dbg(ath9k_hw_common(ah), BEACON,
2266 "%s: unsupported opmode: %d\n", __func__, ah->opmode);
2267 return;
2268 break;
2269 }
2270
2271 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period);
2272 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period);
2273 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period);
2274 REG_WRITE(ah, AR_NDP_PERIOD, beacon_period);
2275
2276 REGWRITE_BUFFER_FLUSH(ah);
2277
2278 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
2279 }
2280 EXPORT_SYMBOL(ath9k_hw_beaconinit);
2281
2282 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
2283 const struct ath9k_beacon_state *bs)
2284 {
2285 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
2286 struct ath9k_hw_capabilities *pCap = &ah->caps;
2287 struct ath_common *common = ath9k_hw_common(ah);
2288
2289 ENABLE_REGWRITE_BUFFER(ah);
2290
2291 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
2292
2293 REG_WRITE(ah, AR_BEACON_PERIOD,
2294 TU_TO_USEC(bs->bs_intval));
2295 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
2296 TU_TO_USEC(bs->bs_intval));
2297
2298 REGWRITE_BUFFER_FLUSH(ah);
2299
2300 REG_RMW_FIELD(ah, AR_RSSI_THR,
2301 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
2302
2303 beaconintval = bs->bs_intval;
2304
2305 if (bs->bs_sleepduration > beaconintval)
2306 beaconintval = bs->bs_sleepduration;
2307
2308 dtimperiod = bs->bs_dtimperiod;
2309 if (bs->bs_sleepduration > dtimperiod)
2310 dtimperiod = bs->bs_sleepduration;
2311
2312 if (beaconintval == dtimperiod)
2313 nextTbtt = bs->bs_nextdtim;
2314 else
2315 nextTbtt = bs->bs_nexttbtt;
2316
2317 ath_dbg(common, BEACON, "next DTIM %d\n", bs->bs_nextdtim);
2318 ath_dbg(common, BEACON, "next beacon %d\n", nextTbtt);
2319 ath_dbg(common, BEACON, "beacon period %d\n", beaconintval);
2320 ath_dbg(common, BEACON, "DTIM period %d\n", dtimperiod);
2321
2322 ENABLE_REGWRITE_BUFFER(ah);
2323
2324 REG_WRITE(ah, AR_NEXT_DTIM,
2325 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
2326 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
2327
2328 REG_WRITE(ah, AR_SLEEP1,
2329 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
2330 | AR_SLEEP1_ASSUME_DTIM);
2331
2332 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
2333 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
2334 else
2335 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
2336
2337 REG_WRITE(ah, AR_SLEEP2,
2338 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
2339
2340 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
2341 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
2342
2343 REGWRITE_BUFFER_FLUSH(ah);
2344
2345 REG_SET_BIT(ah, AR_TIMER_MODE,
2346 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
2347 AR_DTIM_TIMER_EN);
2348
2349 /* TSF Out of Range Threshold */
2350 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
2351 }
2352 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
2353
2354 /*******************/
2355 /* HW Capabilities */
2356 /*******************/
2357
2358 static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask)
2359 {
2360 eeprom_chainmask &= chip_chainmask;
2361 if (eeprom_chainmask)
2362 return eeprom_chainmask;
2363 else
2364 return chip_chainmask;
2365 }
2366
2367 /**
2368 * ath9k_hw_dfs_tested - checks if DFS has been tested with used chipset
2369 * @ah: the atheros hardware data structure
2370 *
2371 * We enable DFS support upstream on chipsets which have passed a series
2372 * of tests. The testing requirements are going to be documented. Desired
2373 * test requirements are documented at:
2374 *
2375 * http://wireless.kernel.org/en/users/Drivers/ath9k/dfs
2376 *
2377 * Once a new chipset gets properly tested an individual commit can be used
2378 * to document the testing for DFS for that chipset.
2379 */
2380 static bool ath9k_hw_dfs_tested(struct ath_hw *ah)
2381 {
2382
2383 switch (ah->hw_version.macVersion) {
2384 /* for temporary testing DFS with 9280 */
2385 case AR_SREV_VERSION_9280:
2386 /* AR9580 will likely be our first target to get testing on */
2387 case AR_SREV_VERSION_9580:
2388 return true;
2389 default:
2390 return false;
2391 }
2392 }
2393
2394 int ath9k_hw_fill_cap_info(struct ath_hw *ah)
2395 {
2396 struct ath9k_hw_capabilities *pCap = &ah->caps;
2397 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2398 struct ath_common *common = ath9k_hw_common(ah);
2399 unsigned int chip_chainmask;
2400
2401 u16 eeval;
2402 u8 ant_div_ctl1, tx_chainmask, rx_chainmask;
2403
2404 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
2405 regulatory->current_rd = eeval;
2406
2407 if (ah->opmode != NL80211_IFTYPE_AP &&
2408 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
2409 if (regulatory->current_rd == 0x64 ||
2410 regulatory->current_rd == 0x65)
2411 regulatory->current_rd += 5;
2412 else if (regulatory->current_rd == 0x41)
2413 regulatory->current_rd = 0x43;
2414 ath_dbg(common, REGULATORY, "regdomain mapped to 0x%x\n",
2415 regulatory->current_rd);
2416 }
2417
2418 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
2419 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
2420 ath_err(common,
2421 "no band has been marked as supported in EEPROM\n");
2422 return -EINVAL;
2423 }
2424
2425 if (eeval & AR5416_OPFLAGS_11A)
2426 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
2427
2428 if (eeval & AR5416_OPFLAGS_11G)
2429 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
2430
2431 if (AR_SREV_9485(ah) ||
2432 AR_SREV_9285(ah) ||
2433 AR_SREV_9330(ah) ||
2434 AR_SREV_9565(ah))
2435 chip_chainmask = 1;
2436 else if (AR_SREV_9462(ah))
2437 chip_chainmask = 3;
2438 else if (!AR_SREV_9280_20_OR_LATER(ah))
2439 chip_chainmask = 7;
2440 else if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9340(ah))
2441 chip_chainmask = 3;
2442 else
2443 chip_chainmask = 7;
2444
2445 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
2446 /*
2447 * For AR9271 we will temporarilly uses the rx chainmax as read from
2448 * the EEPROM.
2449 */
2450 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
2451 !(eeval & AR5416_OPFLAGS_11A) &&
2452 !(AR_SREV_9271(ah)))
2453 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
2454 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
2455 else if (AR_SREV_9100(ah))
2456 pCap->rx_chainmask = 0x7;
2457 else
2458 /* Use rx_chainmask from EEPROM. */
2459 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
2460
2461 pCap->tx_chainmask = fixup_chainmask(chip_chainmask, pCap->tx_chainmask);
2462 pCap->rx_chainmask = fixup_chainmask(chip_chainmask, pCap->rx_chainmask);
2463 ah->txchainmask = pCap->tx_chainmask;
2464 ah->rxchainmask = pCap->rx_chainmask;
2465
2466 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
2467
2468 /* enable key search for every frame in an aggregate */
2469 if (AR_SREV_9300_20_OR_LATER(ah))
2470 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
2471
2472 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
2473
2474 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
2475 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2476 else
2477 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
2478
2479 if (AR_SREV_9271(ah))
2480 pCap->num_gpio_pins = AR9271_NUM_GPIO;
2481 else if (AR_DEVID_7010(ah))
2482 pCap->num_gpio_pins = AR7010_NUM_GPIO;
2483 else if (AR_SREV_9300_20_OR_LATER(ah))
2484 pCap->num_gpio_pins = AR9300_NUM_GPIO;
2485 else if (AR_SREV_9287_11_OR_LATER(ah))
2486 pCap->num_gpio_pins = AR9287_NUM_GPIO;
2487 else if (AR_SREV_9285_12_OR_LATER(ah))
2488 pCap->num_gpio_pins = AR9285_NUM_GPIO;
2489 else if (AR_SREV_9280_20_OR_LATER(ah))
2490 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2491 else
2492 pCap->num_gpio_pins = AR_NUM_GPIO;
2493
2494 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah))
2495 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
2496 else
2497 pCap->rts_aggr_limit = (8 * 1024);
2498
2499 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2500 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2501 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2502 ah->rfkill_gpio =
2503 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2504 ah->rfkill_polarity =
2505 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
2506
2507 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
2508 }
2509 #endif
2510 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
2511 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2512 else
2513 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
2514
2515 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
2516 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2517 else
2518 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
2519
2520 if (AR_SREV_9300_20_OR_LATER(ah)) {
2521 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
2522 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah) && !AR_SREV_9565(ah))
2523 pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
2524
2525 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2526 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2527 pCap->rx_status_len = sizeof(struct ar9003_rxs);
2528 pCap->tx_desc_len = sizeof(struct ar9003_txc);
2529 pCap->txs_len = sizeof(struct ar9003_txs);
2530 } else {
2531 pCap->tx_desc_len = sizeof(struct ath_desc);
2532 if (AR_SREV_9280_20(ah))
2533 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
2534 }
2535
2536 if (AR_SREV_9300_20_OR_LATER(ah))
2537 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2538
2539 if (AR_SREV_9300_20_OR_LATER(ah))
2540 ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
2541
2542 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
2543 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
2544
2545 if (AR_SREV_9285(ah))
2546 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
2547 ant_div_ctl1 =
2548 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2549 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1))
2550 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2551 }
2552 if (AR_SREV_9300_20_OR_LATER(ah)) {
2553 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
2554 pCap->hw_caps |= ATH9K_HW_CAP_APM;
2555 }
2556
2557
2558 if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
2559 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2560 /*
2561 * enable the diversity-combining algorithm only when
2562 * both enable_lna_div and enable_fast_div are set
2563 * Table for Diversity
2564 * ant_div_alt_lnaconf bit 0-1
2565 * ant_div_main_lnaconf bit 2-3
2566 * ant_div_alt_gaintb bit 4
2567 * ant_div_main_gaintb bit 5
2568 * enable_ant_div_lnadiv bit 6
2569 * enable_ant_fast_div bit 7
2570 */
2571 if ((ant_div_ctl1 >> 0x6) == 0x3)
2572 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2573 }
2574
2575 if (ath9k_hw_dfs_tested(ah))
2576 pCap->hw_caps |= ATH9K_HW_CAP_DFS;
2577
2578 tx_chainmask = pCap->tx_chainmask;
2579 rx_chainmask = pCap->rx_chainmask;
2580 while (tx_chainmask || rx_chainmask) {
2581 if (tx_chainmask & BIT(0))
2582 pCap->max_txchains++;
2583 if (rx_chainmask & BIT(0))
2584 pCap->max_rxchains++;
2585
2586 tx_chainmask >>= 1;
2587 rx_chainmask >>= 1;
2588 }
2589
2590 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
2591 if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE))
2592 pCap->hw_caps |= ATH9K_HW_CAP_MCI;
2593
2594 if (AR_SREV_9462_20(ah))
2595 pCap->hw_caps |= ATH9K_HW_CAP_RTT;
2596 }
2597
2598 if (AR_SREV_9280_20_OR_LATER(ah)) {
2599 pCap->hw_caps |= ATH9K_HW_WOW_DEVICE_CAPABLE |
2600 ATH9K_HW_WOW_PATTERN_MATCH_EXACT;
2601
2602 if (AR_SREV_9280(ah))
2603 pCap->hw_caps |= ATH9K_HW_WOW_PATTERN_MATCH_DWORD;
2604 }
2605
2606 if (AR_SREV_9300_20_OR_LATER(ah) &&
2607 ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
2608 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
2609
2610 return 0;
2611 }
2612
2613 /****************************/
2614 /* GPIO / RFKILL / Antennae */
2615 /****************************/
2616
2617 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
2618 u32 gpio, u32 type)
2619 {
2620 int addr;
2621 u32 gpio_shift, tmp;
2622
2623 if (gpio > 11)
2624 addr = AR_GPIO_OUTPUT_MUX3;
2625 else if (gpio > 5)
2626 addr = AR_GPIO_OUTPUT_MUX2;
2627 else
2628 addr = AR_GPIO_OUTPUT_MUX1;
2629
2630 gpio_shift = (gpio % 6) * 5;
2631
2632 if (AR_SREV_9280_20_OR_LATER(ah)
2633 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2634 REG_RMW(ah, addr, (type << gpio_shift),
2635 (0x1f << gpio_shift));
2636 } else {
2637 tmp = REG_READ(ah, addr);
2638 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2639 tmp &= ~(0x1f << gpio_shift);
2640 tmp |= (type << gpio_shift);
2641 REG_WRITE(ah, addr, tmp);
2642 }
2643 }
2644
2645 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
2646 {
2647 u32 gpio_shift;
2648
2649 BUG_ON(gpio >= ah->caps.num_gpio_pins);
2650
2651 if (AR_DEVID_7010(ah)) {
2652 gpio_shift = gpio;
2653 REG_RMW(ah, AR7010_GPIO_OE,
2654 (AR7010_GPIO_OE_AS_INPUT << gpio_shift),
2655 (AR7010_GPIO_OE_MASK << gpio_shift));
2656 return;
2657 }
2658
2659 gpio_shift = gpio << 1;
2660 REG_RMW(ah,
2661 AR_GPIO_OE_OUT,
2662 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2663 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2664 }
2665 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
2666
2667 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
2668 {
2669 #define MS_REG_READ(x, y) \
2670 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2671
2672 if (gpio >= ah->caps.num_gpio_pins)
2673 return 0xffffffff;
2674
2675 if (AR_DEVID_7010(ah)) {
2676 u32 val;
2677 val = REG_READ(ah, AR7010_GPIO_IN);
2678 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0;
2679 } else if (AR_SREV_9300_20_OR_LATER(ah))
2680 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) &
2681 AR_GPIO_BIT(gpio)) != 0;
2682 else if (AR_SREV_9271(ah))
2683 return MS_REG_READ(AR9271, gpio) != 0;
2684 else if (AR_SREV_9287_11_OR_LATER(ah))
2685 return MS_REG_READ(AR9287, gpio) != 0;
2686 else if (AR_SREV_9285_12_OR_LATER(ah))
2687 return MS_REG_READ(AR9285, gpio) != 0;
2688 else if (AR_SREV_9280_20_OR_LATER(ah))
2689 return MS_REG_READ(AR928X, gpio) != 0;
2690 else
2691 return MS_REG_READ(AR, gpio) != 0;
2692 }
2693 EXPORT_SYMBOL(ath9k_hw_gpio_get);
2694
2695 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
2696 u32 ah_signal_type)
2697 {
2698 u32 gpio_shift;
2699
2700 if (AR_DEVID_7010(ah)) {
2701 gpio_shift = gpio;
2702 REG_RMW(ah, AR7010_GPIO_OE,
2703 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift),
2704 (AR7010_GPIO_OE_MASK << gpio_shift));
2705 return;
2706 }
2707
2708 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
2709 gpio_shift = 2 * gpio;
2710 REG_RMW(ah,
2711 AR_GPIO_OE_OUT,
2712 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2713 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2714 }
2715 EXPORT_SYMBOL(ath9k_hw_cfg_output);
2716
2717 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
2718 {
2719 if (AR_DEVID_7010(ah)) {
2720 val = val ? 0 : 1;
2721 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio),
2722 AR_GPIO_BIT(gpio));
2723 return;
2724 }
2725
2726 if (AR_SREV_9271(ah))
2727 val = ~val;
2728
2729 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2730 AR_GPIO_BIT(gpio));
2731 }
2732 EXPORT_SYMBOL(ath9k_hw_set_gpio);
2733
2734 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
2735 {
2736 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
2737 }
2738 EXPORT_SYMBOL(ath9k_hw_setantenna);
2739
2740 /*********************/
2741 /* General Operation */
2742 /*********************/
2743
2744 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
2745 {
2746 u32 bits = REG_READ(ah, AR_RX_FILTER);
2747 u32 phybits = REG_READ(ah, AR_PHY_ERR);
2748
2749 if (phybits & AR_PHY_ERR_RADAR)
2750 bits |= ATH9K_RX_FILTER_PHYRADAR;
2751 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2752 bits |= ATH9K_RX_FILTER_PHYERR;
2753
2754 return bits;
2755 }
2756 EXPORT_SYMBOL(ath9k_hw_getrxfilter);
2757
2758 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
2759 {
2760 u32 phybits;
2761
2762 ENABLE_REGWRITE_BUFFER(ah);
2763
2764 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
2765 bits |= ATH9K_RX_FILTER_CONTROL_WRAPPER;
2766
2767 REG_WRITE(ah, AR_RX_FILTER, bits);
2768
2769 phybits = 0;
2770 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2771 phybits |= AR_PHY_ERR_RADAR;
2772 if (bits & ATH9K_RX_FILTER_PHYERR)
2773 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2774 REG_WRITE(ah, AR_PHY_ERR, phybits);
2775
2776 if (phybits)
2777 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
2778 else
2779 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
2780
2781 REGWRITE_BUFFER_FLUSH(ah);
2782 }
2783 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
2784
2785 bool ath9k_hw_phy_disable(struct ath_hw *ah)
2786 {
2787 if (ath9k_hw_mci_is_enabled(ah))
2788 ar9003_mci_bt_gain_ctrl(ah);
2789
2790 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2791 return false;
2792
2793 ath9k_hw_init_pll(ah, NULL);
2794 ah->htc_reset_init = true;
2795 return true;
2796 }
2797 EXPORT_SYMBOL(ath9k_hw_phy_disable);
2798
2799 bool ath9k_hw_disable(struct ath_hw *ah)
2800 {
2801 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2802 return false;
2803
2804 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2805 return false;
2806
2807 ath9k_hw_init_pll(ah, NULL);
2808 return true;
2809 }
2810 EXPORT_SYMBOL(ath9k_hw_disable);
2811
2812 static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan)
2813 {
2814 enum eeprom_param gain_param;
2815
2816 if (IS_CHAN_2GHZ(chan))
2817 gain_param = EEP_ANTENNA_GAIN_2G;
2818 else
2819 gain_param = EEP_ANTENNA_GAIN_5G;
2820
2821 return ah->eep_ops->get_eeprom(ah, gain_param);
2822 }
2823
2824 void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan,
2825 bool test)
2826 {
2827 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2828 struct ieee80211_channel *channel;
2829 int chan_pwr, new_pwr, max_gain;
2830 int ant_gain, ant_reduction = 0;
2831
2832 if (!chan)
2833 return;
2834
2835 channel = chan->chan;
2836 chan_pwr = min_t(int, channel->max_power * 2, MAX_RATE_POWER);
2837 new_pwr = min_t(int, chan_pwr, reg->power_limit);
2838 max_gain = chan_pwr - new_pwr + channel->max_antenna_gain * 2;
2839
2840 ant_gain = get_antenna_gain(ah, chan);
2841 if (ant_gain > max_gain)
2842 ant_reduction = ant_gain - max_gain;
2843
2844 ah->eep_ops->set_txpower(ah, chan,
2845 ath9k_regd_get_ctl(reg, chan),
2846 ant_reduction, new_pwr, test);
2847 }
2848
2849 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
2850 {
2851 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2852 struct ath9k_channel *chan = ah->curchan;
2853 struct ieee80211_channel *channel = chan->chan;
2854
2855 reg->power_limit = min_t(u32, limit, MAX_RATE_POWER);
2856 if (test)
2857 channel->max_power = MAX_RATE_POWER / 2;
2858
2859 ath9k_hw_apply_txpower(ah, chan, test);
2860
2861 if (test)
2862 channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2);
2863 }
2864 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
2865
2866 void ath9k_hw_setopmode(struct ath_hw *ah)
2867 {
2868 ath9k_hw_set_operating_mode(ah, ah->opmode);
2869 }
2870 EXPORT_SYMBOL(ath9k_hw_setopmode);
2871
2872 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
2873 {
2874 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2875 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
2876 }
2877 EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
2878
2879 void ath9k_hw_write_associd(struct ath_hw *ah)
2880 {
2881 struct ath_common *common = ath9k_hw_common(ah);
2882
2883 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2884 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2885 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2886 }
2887 EXPORT_SYMBOL(ath9k_hw_write_associd);
2888
2889 #define ATH9K_MAX_TSF_READ 10
2890
2891 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
2892 {
2893 u32 tsf_lower, tsf_upper1, tsf_upper2;
2894 int i;
2895
2896 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2897 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2898 tsf_lower = REG_READ(ah, AR_TSF_L32);
2899 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2900 if (tsf_upper2 == tsf_upper1)
2901 break;
2902 tsf_upper1 = tsf_upper2;
2903 }
2904
2905 WARN_ON( i == ATH9K_MAX_TSF_READ );
2906
2907 return (((u64)tsf_upper1 << 32) | tsf_lower);
2908 }
2909 EXPORT_SYMBOL(ath9k_hw_gettsf64);
2910
2911 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
2912 {
2913 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
2914 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
2915 }
2916 EXPORT_SYMBOL(ath9k_hw_settsf64);
2917
2918 void ath9k_hw_reset_tsf(struct ath_hw *ah)
2919 {
2920 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2921 AH_TSF_WRITE_TIMEOUT))
2922 ath_dbg(ath9k_hw_common(ah), RESET,
2923 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
2924
2925 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2926 }
2927 EXPORT_SYMBOL(ath9k_hw_reset_tsf);
2928
2929 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set)
2930 {
2931 if (set)
2932 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
2933 else
2934 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
2935 }
2936 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
2937
2938 void ath9k_hw_set11nmac2040(struct ath_hw *ah)
2939 {
2940 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
2941 u32 macmode;
2942
2943 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
2944 macmode = AR_2040_JOINED_RX_CLEAR;
2945 else
2946 macmode = 0;
2947
2948 REG_WRITE(ah, AR_2040_MODE, macmode);
2949 }
2950
2951 /* HW Generic timers configuration */
2952
2953 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2954 {
2955 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2956 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2957 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2958 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2959 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2960 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2961 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2962 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2963 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2964 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2965 AR_NDP2_TIMER_MODE, 0x0002},
2966 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2967 AR_NDP2_TIMER_MODE, 0x0004},
2968 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2969 AR_NDP2_TIMER_MODE, 0x0008},
2970 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2971 AR_NDP2_TIMER_MODE, 0x0010},
2972 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2973 AR_NDP2_TIMER_MODE, 0x0020},
2974 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2975 AR_NDP2_TIMER_MODE, 0x0040},
2976 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2977 AR_NDP2_TIMER_MODE, 0x0080}
2978 };
2979
2980 /* HW generic timer primitives */
2981
2982 /* compute and clear index of rightmost 1 */
2983 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
2984 {
2985 u32 b;
2986
2987 b = *mask;
2988 b &= (0-b);
2989 *mask &= ~b;
2990 b *= debruijn32;
2991 b >>= 27;
2992
2993 return timer_table->gen_timer_index[b];
2994 }
2995
2996 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
2997 {
2998 return REG_READ(ah, AR_TSF_L32);
2999 }
3000 EXPORT_SYMBOL(ath9k_hw_gettsf32);
3001
3002 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
3003 void (*trigger)(void *),
3004 void (*overflow)(void *),
3005 void *arg,
3006 u8 timer_index)
3007 {
3008 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3009 struct ath_gen_timer *timer;
3010
3011 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
3012 if (timer == NULL)
3013 return NULL;
3014
3015 /* allocate a hardware generic timer slot */
3016 timer_table->timers[timer_index] = timer;
3017 timer->index = timer_index;
3018 timer->trigger = trigger;
3019 timer->overflow = overflow;
3020 timer->arg = arg;
3021
3022 return timer;
3023 }
3024 EXPORT_SYMBOL(ath_gen_timer_alloc);
3025
3026 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
3027 struct ath_gen_timer *timer,
3028 u32 trig_timeout,
3029 u32 timer_period)
3030 {
3031 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3032 u32 tsf, timer_next;
3033
3034 BUG_ON(!timer_period);
3035
3036 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
3037
3038 tsf = ath9k_hw_gettsf32(ah);
3039
3040 timer_next = tsf + trig_timeout;
3041
3042 ath_dbg(ath9k_hw_common(ah), HWTIMER,
3043 "current tsf %x period %x timer_next %x\n",
3044 tsf, timer_period, timer_next);
3045
3046 /*
3047 * Program generic timer registers
3048 */
3049 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
3050 timer_next);
3051 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
3052 timer_period);
3053 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3054 gen_tmr_configuration[timer->index].mode_mask);
3055
3056 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
3057 /*
3058 * Starting from AR9462, each generic timer can select which tsf
3059 * to use. But we still follow the old rule, 0 - 7 use tsf and
3060 * 8 - 15 use tsf2.
3061 */
3062 if ((timer->index < AR_GEN_TIMER_BANK_1_LEN))
3063 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3064 (1 << timer->index));
3065 else
3066 REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3067 (1 << timer->index));
3068 }
3069
3070 /* Enable both trigger and thresh interrupt masks */
3071 REG_SET_BIT(ah, AR_IMR_S5,
3072 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3073 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3074 }
3075 EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
3076
3077 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
3078 {
3079 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3080
3081 if ((timer->index < AR_FIRST_NDP_TIMER) ||
3082 (timer->index >= ATH_MAX_GEN_TIMER)) {
3083 return;
3084 }
3085
3086 /* Clear generic timer enable bits. */
3087 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3088 gen_tmr_configuration[timer->index].mode_mask);
3089
3090 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
3091 /*
3092 * Need to switch back to TSF if it was using TSF2.
3093 */
3094 if ((timer->index >= AR_GEN_TIMER_BANK_1_LEN)) {
3095 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3096 (1 << timer->index));
3097 }
3098 }
3099
3100 /* Disable both trigger and thresh interrupt masks */
3101 REG_CLR_BIT(ah, AR_IMR_S5,
3102 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3103 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3104
3105 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
3106 }
3107 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
3108
3109 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
3110 {
3111 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3112
3113 /* free the hardware generic timer slot */
3114 timer_table->timers[timer->index] = NULL;
3115 kfree(timer);
3116 }
3117 EXPORT_SYMBOL(ath_gen_timer_free);
3118
3119 /*
3120 * Generic Timer Interrupts handling
3121 */
3122 void ath_gen_timer_isr(struct ath_hw *ah)
3123 {
3124 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3125 struct ath_gen_timer *timer;
3126 struct ath_common *common = ath9k_hw_common(ah);
3127 u32 trigger_mask, thresh_mask, index;
3128
3129 /* get hardware generic timer interrupt status */
3130 trigger_mask = ah->intr_gen_timer_trigger;
3131 thresh_mask = ah->intr_gen_timer_thresh;
3132 trigger_mask &= timer_table->timer_mask.val;
3133 thresh_mask &= timer_table->timer_mask.val;
3134
3135 trigger_mask &= ~thresh_mask;
3136
3137 while (thresh_mask) {
3138 index = rightmost_index(timer_table, &thresh_mask);
3139 timer = timer_table->timers[index];
3140 BUG_ON(!timer);
3141 ath_dbg(common, HWTIMER, "TSF overflow for Gen timer %d\n",
3142 index);
3143 timer->overflow(timer->arg);
3144 }
3145
3146 while (trigger_mask) {
3147 index = rightmost_index(timer_table, &trigger_mask);
3148 timer = timer_table->timers[index];
3149 BUG_ON(!timer);
3150 ath_dbg(common, HWTIMER,
3151 "Gen timer[%d] trigger\n", index);
3152 timer->trigger(timer->arg);
3153 }
3154 }
3155 EXPORT_SYMBOL(ath_gen_timer_isr);
3156
3157 /********/
3158 /* HTC */
3159 /********/
3160
3161 static struct {
3162 u32 version;
3163 const char * name;
3164 } ath_mac_bb_names[] = {
3165 /* Devices with external radios */
3166 { AR_SREV_VERSION_5416_PCI, "5416" },
3167 { AR_SREV_VERSION_5416_PCIE, "5418" },
3168 { AR_SREV_VERSION_9100, "9100" },
3169 { AR_SREV_VERSION_9160, "9160" },
3170 /* Single-chip solutions */
3171 { AR_SREV_VERSION_9280, "9280" },
3172 { AR_SREV_VERSION_9285, "9285" },
3173 { AR_SREV_VERSION_9287, "9287" },
3174 { AR_SREV_VERSION_9271, "9271" },
3175 { AR_SREV_VERSION_9300, "9300" },
3176 { AR_SREV_VERSION_9330, "9330" },
3177 { AR_SREV_VERSION_9340, "9340" },
3178 { AR_SREV_VERSION_9485, "9485" },
3179 { AR_SREV_VERSION_9462, "9462" },
3180 { AR_SREV_VERSION_9550, "9550" },
3181 { AR_SREV_VERSION_9565, "9565" },
3182 };
3183
3184 /* For devices with external radios */
3185 static struct {
3186 u16 version;
3187 const char * name;
3188 } ath_rf_names[] = {
3189 { 0, "5133" },
3190 { AR_RAD5133_SREV_MAJOR, "5133" },
3191 { AR_RAD5122_SREV_MAJOR, "5122" },
3192 { AR_RAD2133_SREV_MAJOR, "2133" },
3193 { AR_RAD2122_SREV_MAJOR, "2122" }
3194 };
3195
3196 /*
3197 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3198 */
3199 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
3200 {
3201 int i;
3202
3203 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3204 if (ath_mac_bb_names[i].version == mac_bb_version) {
3205 return ath_mac_bb_names[i].name;
3206 }
3207 }
3208
3209 return "????";
3210 }
3211
3212 /*
3213 * Return the RF name. "????" is returned if the RF is unknown.
3214 * Used for devices with external radios.
3215 */
3216 static const char *ath9k_hw_rf_name(u16 rf_version)
3217 {
3218 int i;
3219
3220 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3221 if (ath_rf_names[i].version == rf_version) {
3222 return ath_rf_names[i].name;
3223 }
3224 }
3225
3226 return "????";
3227 }
3228
3229 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
3230 {
3231 int used;
3232
3233 /* chipsets >= AR9280 are single-chip */
3234 if (AR_SREV_9280_20_OR_LATER(ah)) {
3235 used = snprintf(hw_name, len,
3236 "Atheros AR%s Rev:%x",
3237 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3238 ah->hw_version.macRev);
3239 }
3240 else {
3241 used = snprintf(hw_name, len,
3242 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3243 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3244 ah->hw_version.macRev,
3245 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
3246 AR_RADIO_SREV_MAJOR)),
3247 ah->hw_version.phyRev);
3248 }
3249
3250 hw_name[used] = '\0';
3251 }
3252 EXPORT_SYMBOL(ath9k_hw_name);
Linux kernel - Deliverables
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