2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include <linux/slab.h>
19 #include <linux/module.h>
20 #include <asm/unaligned.h>
25 #include "ar9003_mac.h"
26 #include "ar9003_mci.h"
28 static bool ath9k_hw_set_reset_reg(struct ath_hw
*ah
, u32 type
);
30 MODULE_AUTHOR("Atheros Communications");
31 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
32 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
33 MODULE_LICENSE("Dual BSD/GPL");
35 static int __init
ath9k_init(void)
39 module_init(ath9k_init
);
41 static void __exit
ath9k_exit(void)
45 module_exit(ath9k_exit
);
47 /* Private hardware callbacks */
49 static void ath9k_hw_init_cal_settings(struct ath_hw
*ah
)
51 ath9k_hw_private_ops(ah
)->init_cal_settings(ah
);
54 static void ath9k_hw_init_mode_regs(struct ath_hw
*ah
)
56 ath9k_hw_private_ops(ah
)->init_mode_regs(ah
);
59 static u32
ath9k_hw_compute_pll_control(struct ath_hw
*ah
,
60 struct ath9k_channel
*chan
)
62 return ath9k_hw_private_ops(ah
)->compute_pll_control(ah
, chan
);
65 static void ath9k_hw_init_mode_gain_regs(struct ath_hw
*ah
)
67 if (!ath9k_hw_private_ops(ah
)->init_mode_gain_regs
)
70 ath9k_hw_private_ops(ah
)->init_mode_gain_regs(ah
);
73 static void ath9k_hw_ani_cache_ini_regs(struct ath_hw
*ah
)
75 /* You will not have this callback if using the old ANI */
76 if (!ath9k_hw_private_ops(ah
)->ani_cache_ini_regs
)
79 ath9k_hw_private_ops(ah
)->ani_cache_ini_regs(ah
);
82 /********************/
83 /* Helper Functions */
84 /********************/
86 static void ath9k_hw_set_clockrate(struct ath_hw
*ah
)
88 struct ieee80211_conf
*conf
= &ath9k_hw_common(ah
)->hw
->conf
;
89 struct ath_common
*common
= ath9k_hw_common(ah
);
90 unsigned int clockrate
;
92 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */
93 if (AR_SREV_9287(ah
) && AR_SREV_9287_13_OR_LATER(ah
))
95 else if (!ah
->curchan
) /* should really check for CCK instead */
96 clockrate
= ATH9K_CLOCK_RATE_CCK
;
97 else if (conf
->channel
->band
== IEEE80211_BAND_2GHZ
)
98 clockrate
= ATH9K_CLOCK_RATE_2GHZ_OFDM
;
99 else if (ah
->caps
.hw_caps
& ATH9K_HW_CAP_FASTCLOCK
)
100 clockrate
= ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM
;
102 clockrate
= ATH9K_CLOCK_RATE_5GHZ_OFDM
;
104 if (conf_is_ht40(conf
))
108 if (IS_CHAN_HALF_RATE(ah
->curchan
))
110 if (IS_CHAN_QUARTER_RATE(ah
->curchan
))
114 common
->clockrate
= clockrate
;
117 static u32
ath9k_hw_mac_to_clks(struct ath_hw
*ah
, u32 usecs
)
119 struct ath_common
*common
= ath9k_hw_common(ah
);
121 return usecs
* common
->clockrate
;
124 bool ath9k_hw_wait(struct ath_hw
*ah
, u32 reg
, u32 mask
, u32 val
, u32 timeout
)
128 BUG_ON(timeout
< AH_TIME_QUANTUM
);
130 for (i
= 0; i
< (timeout
/ AH_TIME_QUANTUM
); i
++) {
131 if ((REG_READ(ah
, reg
) & mask
) == val
)
134 udelay(AH_TIME_QUANTUM
);
137 ath_dbg(ath9k_hw_common(ah
), ANY
,
138 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
139 timeout
, reg
, REG_READ(ah
, reg
), mask
, val
);
143 EXPORT_SYMBOL(ath9k_hw_wait
);
145 void ath9k_hw_write_array(struct ath_hw
*ah
, struct ar5416IniArray
*array
,
146 int column
, unsigned int *writecnt
)
150 ENABLE_REGWRITE_BUFFER(ah
);
151 for (r
= 0; r
< array
->ia_rows
; r
++) {
152 REG_WRITE(ah
, INI_RA(array
, r
, 0),
153 INI_RA(array
, r
, column
));
156 REGWRITE_BUFFER_FLUSH(ah
);
159 u32
ath9k_hw_reverse_bits(u32 val
, u32 n
)
164 for (i
= 0, retval
= 0; i
< n
; i
++) {
165 retval
= (retval
<< 1) | (val
& 1);
171 u16
ath9k_hw_computetxtime(struct ath_hw
*ah
,
173 u32 frameLen
, u16 rateix
,
176 u32 bitsPerSymbol
, numBits
, numSymbols
, phyTime
, txTime
;
182 case WLAN_RC_PHY_CCK
:
183 phyTime
= CCK_PREAMBLE_BITS
+ CCK_PLCP_BITS
;
186 numBits
= frameLen
<< 3;
187 txTime
= CCK_SIFS_TIME
+ phyTime
+ ((numBits
* 1000) / kbps
);
189 case WLAN_RC_PHY_OFDM
:
190 if (ah
->curchan
&& IS_CHAN_QUARTER_RATE(ah
->curchan
)) {
191 bitsPerSymbol
= (kbps
* OFDM_SYMBOL_TIME_QUARTER
) / 1000;
192 numBits
= OFDM_PLCP_BITS
+ (frameLen
<< 3);
193 numSymbols
= DIV_ROUND_UP(numBits
, bitsPerSymbol
);
194 txTime
= OFDM_SIFS_TIME_QUARTER
195 + OFDM_PREAMBLE_TIME_QUARTER
196 + (numSymbols
* OFDM_SYMBOL_TIME_QUARTER
);
197 } else if (ah
->curchan
&&
198 IS_CHAN_HALF_RATE(ah
->curchan
)) {
199 bitsPerSymbol
= (kbps
* OFDM_SYMBOL_TIME_HALF
) / 1000;
200 numBits
= OFDM_PLCP_BITS
+ (frameLen
<< 3);
201 numSymbols
= DIV_ROUND_UP(numBits
, bitsPerSymbol
);
202 txTime
= OFDM_SIFS_TIME_HALF
+
203 OFDM_PREAMBLE_TIME_HALF
204 + (numSymbols
* OFDM_SYMBOL_TIME_HALF
);
206 bitsPerSymbol
= (kbps
* OFDM_SYMBOL_TIME
) / 1000;
207 numBits
= OFDM_PLCP_BITS
+ (frameLen
<< 3);
208 numSymbols
= DIV_ROUND_UP(numBits
, bitsPerSymbol
);
209 txTime
= OFDM_SIFS_TIME
+ OFDM_PREAMBLE_TIME
210 + (numSymbols
* OFDM_SYMBOL_TIME
);
214 ath_err(ath9k_hw_common(ah
),
215 "Unknown phy %u (rate ix %u)\n", phy
, rateix
);
222 EXPORT_SYMBOL(ath9k_hw_computetxtime
);
224 void ath9k_hw_get_channel_centers(struct ath_hw
*ah
,
225 struct ath9k_channel
*chan
,
226 struct chan_centers
*centers
)
230 if (!IS_CHAN_HT40(chan
)) {
231 centers
->ctl_center
= centers
->ext_center
=
232 centers
->synth_center
= chan
->channel
;
236 if ((chan
->chanmode
== CHANNEL_A_HT40PLUS
) ||
237 (chan
->chanmode
== CHANNEL_G_HT40PLUS
)) {
238 centers
->synth_center
=
239 chan
->channel
+ HT40_CHANNEL_CENTER_SHIFT
;
242 centers
->synth_center
=
243 chan
->channel
- HT40_CHANNEL_CENTER_SHIFT
;
247 centers
->ctl_center
=
248 centers
->synth_center
- (extoff
* HT40_CHANNEL_CENTER_SHIFT
);
249 /* 25 MHz spacing is supported by hw but not on upper layers */
250 centers
->ext_center
=
251 centers
->synth_center
+ (extoff
* HT40_CHANNEL_CENTER_SHIFT
);
258 static void ath9k_hw_read_revisions(struct ath_hw
*ah
)
262 switch (ah
->hw_version
.devid
) {
263 case AR5416_AR9100_DEVID
:
264 ah
->hw_version
.macVersion
= AR_SREV_VERSION_9100
;
266 case AR9300_DEVID_AR9330
:
267 ah
->hw_version
.macVersion
= AR_SREV_VERSION_9330
;
268 if (ah
->get_mac_revision
) {
269 ah
->hw_version
.macRev
= ah
->get_mac_revision();
271 val
= REG_READ(ah
, AR_SREV
);
272 ah
->hw_version
.macRev
= MS(val
, AR_SREV_REVISION2
);
275 case AR9300_DEVID_AR9340
:
276 ah
->hw_version
.macVersion
= AR_SREV_VERSION_9340
;
277 val
= REG_READ(ah
, AR_SREV
);
278 ah
->hw_version
.macRev
= MS(val
, AR_SREV_REVISION2
);
282 val
= REG_READ(ah
, AR_SREV
) & AR_SREV_ID
;
285 val
= REG_READ(ah
, AR_SREV
);
286 ah
->hw_version
.macVersion
=
287 (val
& AR_SREV_VERSION2
) >> AR_SREV_TYPE2_S
;
288 ah
->hw_version
.macRev
= MS(val
, AR_SREV_REVISION2
);
290 if (AR_SREV_9462(ah
))
291 ah
->is_pciexpress
= true;
293 ah
->is_pciexpress
= (val
&
294 AR_SREV_TYPE2_HOST_MODE
) ? 0 : 1;
296 if (!AR_SREV_9100(ah
))
297 ah
->hw_version
.macVersion
= MS(val
, AR_SREV_VERSION
);
299 ah
->hw_version
.macRev
= val
& AR_SREV_REVISION
;
301 if (ah
->hw_version
.macVersion
== AR_SREV_VERSION_5416_PCIE
)
302 ah
->is_pciexpress
= true;
306 /************************************/
307 /* HW Attach, Detach, Init Routines */
308 /************************************/
310 static void ath9k_hw_disablepcie(struct ath_hw
*ah
)
312 if (!AR_SREV_5416(ah
))
315 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x9248fc00);
316 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x24924924);
317 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x28000029);
318 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x57160824);
319 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x25980579);
320 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x00000000);
321 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x1aaabe40);
322 REG_WRITE(ah
, AR_PCIE_SERDES
, 0xbe105554);
323 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x000e1007);
325 REG_WRITE(ah
, AR_PCIE_SERDES2
, 0x00000000);
328 static void ath9k_hw_aspm_init(struct ath_hw
*ah
)
330 struct ath_common
*common
= ath9k_hw_common(ah
);
332 if (common
->bus_ops
->aspm_init
)
333 common
->bus_ops
->aspm_init(common
);
336 /* This should work for all families including legacy */
337 static bool ath9k_hw_chip_test(struct ath_hw
*ah
)
339 struct ath_common
*common
= ath9k_hw_common(ah
);
340 u32 regAddr
[2] = { AR_STA_ID0
};
342 static const u32 patternData
[4] = {
343 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
347 if (!AR_SREV_9300_20_OR_LATER(ah
)) {
349 regAddr
[1] = AR_PHY_BASE
+ (8 << 2);
353 for (i
= 0; i
< loop_max
; i
++) {
354 u32 addr
= regAddr
[i
];
357 regHold
[i
] = REG_READ(ah
, addr
);
358 for (j
= 0; j
< 0x100; j
++) {
359 wrData
= (j
<< 16) | j
;
360 REG_WRITE(ah
, addr
, wrData
);
361 rdData
= REG_READ(ah
, addr
);
362 if (rdData
!= wrData
) {
364 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
365 addr
, wrData
, rdData
);
369 for (j
= 0; j
< 4; j
++) {
370 wrData
= patternData
[j
];
371 REG_WRITE(ah
, addr
, wrData
);
372 rdData
= REG_READ(ah
, addr
);
373 if (wrData
!= rdData
) {
375 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
376 addr
, wrData
, rdData
);
380 REG_WRITE(ah
, regAddr
[i
], regHold
[i
]);
387 static void ath9k_hw_init_config(struct ath_hw
*ah
)
391 ah
->config
.dma_beacon_response_time
= 2;
392 ah
->config
.sw_beacon_response_time
= 10;
393 ah
->config
.additional_swba_backoff
= 0;
394 ah
->config
.ack_6mb
= 0x0;
395 ah
->config
.cwm_ignore_extcca
= 0;
396 ah
->config
.pcie_clock_req
= 0;
397 ah
->config
.pcie_waen
= 0;
398 ah
->config
.analog_shiftreg
= 1;
399 ah
->config
.enable_ani
= true;
401 for (i
= 0; i
< AR_EEPROM_MODAL_SPURS
; i
++) {
402 ah
->config
.spurchans
[i
][0] = AR_NO_SPUR
;
403 ah
->config
.spurchans
[i
][1] = AR_NO_SPUR
;
406 /* PAPRD needs some more work to be enabled */
407 ah
->config
.paprd_disable
= 1;
409 ah
->config
.rx_intr_mitigation
= true;
410 ah
->config
.pcieSerDesWrite
= true;
413 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
414 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
415 * This means we use it for all AR5416 devices, and the few
416 * minor PCI AR9280 devices out there.
418 * Serialization is required because these devices do not handle
419 * well the case of two concurrent reads/writes due to the latency
420 * involved. During one read/write another read/write can be issued
421 * on another CPU while the previous read/write may still be working
422 * on our hardware, if we hit this case the hardware poops in a loop.
423 * We prevent this by serializing reads and writes.
425 * This issue is not present on PCI-Express devices or pre-AR5416
426 * devices (legacy, 802.11abg).
428 if (num_possible_cpus() > 1)
429 ah
->config
.serialize_regmode
= SER_REG_MODE_AUTO
;
432 static void ath9k_hw_init_defaults(struct ath_hw
*ah
)
434 struct ath_regulatory
*regulatory
= ath9k_hw_regulatory(ah
);
436 regulatory
->country_code
= CTRY_DEFAULT
;
437 regulatory
->power_limit
= MAX_RATE_POWER
;
439 ah
->hw_version
.magic
= AR5416_MAGIC
;
440 ah
->hw_version
.subvendorid
= 0;
443 ah
->sta_id1_defaults
=
444 AR_STA_ID1_CRPT_MIC_ENABLE
|
445 AR_STA_ID1_MCAST_KSRCH
;
446 if (AR_SREV_9100(ah
))
447 ah
->sta_id1_defaults
|= AR_STA_ID1_AR9100_BA_FIX
;
448 ah
->enable_32kHz_clock
= DONT_USE_32KHZ
;
449 ah
->slottime
= ATH9K_SLOT_TIME_9
;
450 ah
->globaltxtimeout
= (u32
) -1;
451 ah
->power_mode
= ATH9K_PM_UNDEFINED
;
452 ah
->htc_reset_init
= true;
455 static int ath9k_hw_init_macaddr(struct ath_hw
*ah
)
457 struct ath_common
*common
= ath9k_hw_common(ah
);
461 static const u32 EEP_MAC
[] = { EEP_MAC_LSW
, EEP_MAC_MID
, EEP_MAC_MSW
};
464 for (i
= 0; i
< 3; i
++) {
465 eeval
= ah
->eep_ops
->get_eeprom(ah
, EEP_MAC
[i
]);
467 common
->macaddr
[2 * i
] = eeval
>> 8;
468 common
->macaddr
[2 * i
+ 1] = eeval
& 0xff;
470 if (sum
== 0 || sum
== 0xffff * 3)
471 return -EADDRNOTAVAIL
;
476 static int ath9k_hw_post_init(struct ath_hw
*ah
)
478 struct ath_common
*common
= ath9k_hw_common(ah
);
481 if (common
->bus_ops
->ath_bus_type
!= ATH_USB
) {
482 if (!ath9k_hw_chip_test(ah
))
486 if (!AR_SREV_9300_20_OR_LATER(ah
)) {
487 ecode
= ar9002_hw_rf_claim(ah
);
492 ecode
= ath9k_hw_eeprom_init(ah
);
496 ath_dbg(ath9k_hw_common(ah
), CONFIG
, "Eeprom VER: %d, REV: %d\n",
497 ah
->eep_ops
->get_eeprom_ver(ah
),
498 ah
->eep_ops
->get_eeprom_rev(ah
));
500 ecode
= ath9k_hw_rf_alloc_ext_banks(ah
);
502 ath_err(ath9k_hw_common(ah
),
503 "Failed allocating banks for external radio\n");
504 ath9k_hw_rf_free_ext_banks(ah
);
508 if (ah
->config
.enable_ani
) {
509 ath9k_hw_ani_setup(ah
);
510 ath9k_hw_ani_init(ah
);
516 static void ath9k_hw_attach_ops(struct ath_hw
*ah
)
518 if (AR_SREV_9300_20_OR_LATER(ah
))
519 ar9003_hw_attach_ops(ah
);
521 ar9002_hw_attach_ops(ah
);
524 /* Called for all hardware families */
525 static int __ath9k_hw_init(struct ath_hw
*ah
)
527 struct ath_common
*common
= ath9k_hw_common(ah
);
530 ath9k_hw_read_revisions(ah
);
533 * Read back AR_WA into a permanent copy and set bits 14 and 17.
534 * We need to do this to avoid RMW of this register. We cannot
535 * read the reg when chip is asleep.
537 ah
->WARegVal
= REG_READ(ah
, AR_WA
);
538 ah
->WARegVal
|= (AR_WA_D3_L1_DISABLE
|
539 AR_WA_ASPM_TIMER_BASED_DISABLE
);
541 if (!ath9k_hw_set_reset_reg(ah
, ATH9K_RESET_POWER_ON
)) {
542 ath_err(common
, "Couldn't reset chip\n");
546 if (AR_SREV_9462(ah
))
547 ah
->WARegVal
&= ~AR_WA_D3_L1_DISABLE
;
549 ath9k_hw_init_defaults(ah
);
550 ath9k_hw_init_config(ah
);
552 ath9k_hw_attach_ops(ah
);
554 if (!ath9k_hw_setpower(ah
, ATH9K_PM_AWAKE
)) {
555 ath_err(common
, "Couldn't wakeup chip\n");
559 if (NR_CPUS
> 1 && ah
->config
.serialize_regmode
== SER_REG_MODE_AUTO
) {
560 if (ah
->hw_version
.macVersion
== AR_SREV_VERSION_5416_PCI
||
561 ((AR_SREV_9160(ah
) || AR_SREV_9280(ah
)) &&
562 !ah
->is_pciexpress
)) {
563 ah
->config
.serialize_regmode
=
566 ah
->config
.serialize_regmode
=
571 ath_dbg(common
, RESET
, "serialize_regmode is %d\n",
572 ah
->config
.serialize_regmode
);
574 if (AR_SREV_9285(ah
) || AR_SREV_9271(ah
))
575 ah
->config
.max_txtrig_level
= MAX_TX_FIFO_THRESHOLD
>> 1;
577 ah
->config
.max_txtrig_level
= MAX_TX_FIFO_THRESHOLD
;
579 switch (ah
->hw_version
.macVersion
) {
580 case AR_SREV_VERSION_5416_PCI
:
581 case AR_SREV_VERSION_5416_PCIE
:
582 case AR_SREV_VERSION_9160
:
583 case AR_SREV_VERSION_9100
:
584 case AR_SREV_VERSION_9280
:
585 case AR_SREV_VERSION_9285
:
586 case AR_SREV_VERSION_9287
:
587 case AR_SREV_VERSION_9271
:
588 case AR_SREV_VERSION_9300
:
589 case AR_SREV_VERSION_9330
:
590 case AR_SREV_VERSION_9485
:
591 case AR_SREV_VERSION_9340
:
592 case AR_SREV_VERSION_9462
:
596 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
597 ah
->hw_version
.macVersion
, ah
->hw_version
.macRev
);
601 if (AR_SREV_9271(ah
) || AR_SREV_9100(ah
) || AR_SREV_9340(ah
) ||
603 ah
->is_pciexpress
= false;
605 ah
->hw_version
.phyRev
= REG_READ(ah
, AR_PHY_CHIP_ID
);
606 ath9k_hw_init_cal_settings(ah
);
608 ah
->ani_function
= ATH9K_ANI_ALL
;
609 if (AR_SREV_9280_20_OR_LATER(ah
) && !AR_SREV_9300_20_OR_LATER(ah
))
610 ah
->ani_function
&= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL
;
611 if (!AR_SREV_9300_20_OR_LATER(ah
))
612 ah
->ani_function
&= ~ATH9K_ANI_MRC_CCK
;
614 /* disable ANI for 9340 */
615 if (AR_SREV_9340(ah
))
616 ah
->config
.enable_ani
= false;
618 ath9k_hw_init_mode_regs(ah
);
620 if (!ah
->is_pciexpress
)
621 ath9k_hw_disablepcie(ah
);
623 r
= ath9k_hw_post_init(ah
);
627 ath9k_hw_init_mode_gain_regs(ah
);
628 r
= ath9k_hw_fill_cap_info(ah
);
632 if (ah
->is_pciexpress
)
633 ath9k_hw_aspm_init(ah
);
635 r
= ath9k_hw_init_macaddr(ah
);
637 ath_err(common
, "Failed to initialize MAC address\n");
641 if (AR_SREV_9285(ah
) || AR_SREV_9271(ah
))
642 ah
->tx_trig_level
= (AR_FTRIG_256B
>> AR_FTRIG_S
);
644 ah
->tx_trig_level
= (AR_FTRIG_512B
>> AR_FTRIG_S
);
646 if (AR_SREV_9330(ah
))
647 ah
->bb_watchdog_timeout_ms
= 85;
649 ah
->bb_watchdog_timeout_ms
= 25;
651 common
->state
= ATH_HW_INITIALIZED
;
656 int ath9k_hw_init(struct ath_hw
*ah
)
659 struct ath_common
*common
= ath9k_hw_common(ah
);
661 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
662 switch (ah
->hw_version
.devid
) {
663 case AR5416_DEVID_PCI
:
664 case AR5416_DEVID_PCIE
:
665 case AR5416_AR9100_DEVID
:
666 case AR9160_DEVID_PCI
:
667 case AR9280_DEVID_PCI
:
668 case AR9280_DEVID_PCIE
:
669 case AR9285_DEVID_PCIE
:
670 case AR9287_DEVID_PCI
:
671 case AR9287_DEVID_PCIE
:
672 case AR2427_DEVID_PCIE
:
673 case AR9300_DEVID_PCIE
:
674 case AR9300_DEVID_AR9485_PCIE
:
675 case AR9300_DEVID_AR9330
:
676 case AR9300_DEVID_AR9340
:
677 case AR9300_DEVID_AR9580
:
678 case AR9300_DEVID_AR9462
:
681 if (common
->bus_ops
->ath_bus_type
== ATH_USB
)
683 ath_err(common
, "Hardware device ID 0x%04x not supported\n",
684 ah
->hw_version
.devid
);
688 ret
= __ath9k_hw_init(ah
);
691 "Unable to initialize hardware; initialization status: %d\n",
698 EXPORT_SYMBOL(ath9k_hw_init
);
700 static void ath9k_hw_init_qos(struct ath_hw
*ah
)
702 ENABLE_REGWRITE_BUFFER(ah
);
704 REG_WRITE(ah
, AR_MIC_QOS_CONTROL
, 0x100aa);
705 REG_WRITE(ah
, AR_MIC_QOS_SELECT
, 0x3210);
707 REG_WRITE(ah
, AR_QOS_NO_ACK
,
708 SM(2, AR_QOS_NO_ACK_TWO_BIT
) |
709 SM(5, AR_QOS_NO_ACK_BIT_OFF
) |
710 SM(0, AR_QOS_NO_ACK_BYTE_OFF
));
712 REG_WRITE(ah
, AR_TXOP_X
, AR_TXOP_X_VAL
);
713 REG_WRITE(ah
, AR_TXOP_0_3
, 0xFFFFFFFF);
714 REG_WRITE(ah
, AR_TXOP_4_7
, 0xFFFFFFFF);
715 REG_WRITE(ah
, AR_TXOP_8_11
, 0xFFFFFFFF);
716 REG_WRITE(ah
, AR_TXOP_12_15
, 0xFFFFFFFF);
718 REGWRITE_BUFFER_FLUSH(ah
);
721 u32
ar9003_get_pll_sqsum_dvc(struct ath_hw
*ah
)
723 REG_CLR_BIT(ah
, PLL3
, PLL3_DO_MEAS_MASK
);
725 REG_SET_BIT(ah
, PLL3
, PLL3_DO_MEAS_MASK
);
727 while ((REG_READ(ah
, PLL4
) & PLL4_MEAS_DONE
) == 0)
730 return (REG_READ(ah
, PLL3
) & SQSUM_DVC_MASK
) >> 3;
732 EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc
);
734 static void ath9k_hw_init_pll(struct ath_hw
*ah
,
735 struct ath9k_channel
*chan
)
739 if (AR_SREV_9485(ah
)) {
741 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */
742 REG_RMW_FIELD(ah
, AR_CH0_BB_DPLL2
,
743 AR_CH0_BB_DPLL2_PLL_PWD
, 0x1);
744 REG_RMW_FIELD(ah
, AR_CH0_BB_DPLL2
,
745 AR_CH0_DPLL2_KD
, 0x40);
746 REG_RMW_FIELD(ah
, AR_CH0_BB_DPLL2
,
747 AR_CH0_DPLL2_KI
, 0x4);
749 REG_RMW_FIELD(ah
, AR_CH0_BB_DPLL1
,
750 AR_CH0_BB_DPLL1_REFDIV
, 0x5);
751 REG_RMW_FIELD(ah
, AR_CH0_BB_DPLL1
,
752 AR_CH0_BB_DPLL1_NINI
, 0x58);
753 REG_RMW_FIELD(ah
, AR_CH0_BB_DPLL1
,
754 AR_CH0_BB_DPLL1_NFRAC
, 0x0);
756 REG_RMW_FIELD(ah
, AR_CH0_BB_DPLL2
,
757 AR_CH0_BB_DPLL2_OUTDIV
, 0x1);
758 REG_RMW_FIELD(ah
, AR_CH0_BB_DPLL2
,
759 AR_CH0_BB_DPLL2_LOCAL_PLL
, 0x1);
760 REG_RMW_FIELD(ah
, AR_CH0_BB_DPLL2
,
761 AR_CH0_BB_DPLL2_EN_NEGTRIG
, 0x1);
763 /* program BB PLL phase_shift to 0x6 */
764 REG_RMW_FIELD(ah
, AR_CH0_BB_DPLL3
,
765 AR_CH0_BB_DPLL3_PHASE_SHIFT
, 0x6);
767 REG_RMW_FIELD(ah
, AR_CH0_BB_DPLL2
,
768 AR_CH0_BB_DPLL2_PLL_PWD
, 0x0);
770 } else if (AR_SREV_9330(ah
)) {
771 u32 ddr_dpll2
, pll_control2
, kd
;
773 if (ah
->is_clk_25mhz
) {
774 ddr_dpll2
= 0x18e82f01;
775 pll_control2
= 0xe04a3d;
778 ddr_dpll2
= 0x19e82f01;
779 pll_control2
= 0x886666;
783 /* program DDR PLL ki and kd value */
784 REG_WRITE(ah
, AR_CH0_DDR_DPLL2
, ddr_dpll2
);
786 /* program DDR PLL phase_shift */
787 REG_RMW_FIELD(ah
, AR_CH0_DDR_DPLL3
,
788 AR_CH0_DPLL3_PHASE_SHIFT
, 0x1);
790 REG_WRITE(ah
, AR_RTC_PLL_CONTROL
, 0x1142c);
793 /* program refdiv, nint, frac to RTC register */
794 REG_WRITE(ah
, AR_RTC_PLL_CONTROL2
, pll_control2
);
796 /* program BB PLL kd and ki value */
797 REG_RMW_FIELD(ah
, AR_CH0_BB_DPLL2
, AR_CH0_DPLL2_KD
, kd
);
798 REG_RMW_FIELD(ah
, AR_CH0_BB_DPLL2
, AR_CH0_DPLL2_KI
, 0x06);
800 /* program BB PLL phase_shift */
801 REG_RMW_FIELD(ah
, AR_CH0_BB_DPLL3
,
802 AR_CH0_BB_DPLL3_PHASE_SHIFT
, 0x1);
803 } else if (AR_SREV_9340(ah
)) {
804 u32 regval
, pll2_divint
, pll2_divfrac
, refdiv
;
806 REG_WRITE(ah
, AR_RTC_PLL_CONTROL
, 0x1142c);
809 REG_SET_BIT(ah
, AR_PHY_PLL_MODE
, 0x1 << 16);
812 if (ah
->is_clk_25mhz
) {
814 pll2_divfrac
= 0x1eb85;
822 regval
= REG_READ(ah
, AR_PHY_PLL_MODE
);
823 regval
|= (0x1 << 16);
824 REG_WRITE(ah
, AR_PHY_PLL_MODE
, regval
);
827 REG_WRITE(ah
, AR_PHY_PLL_CONTROL
, (refdiv
<< 27) |
828 (pll2_divint
<< 18) | pll2_divfrac
);
831 regval
= REG_READ(ah
, AR_PHY_PLL_MODE
);
832 regval
= (regval
& 0x80071fff) | (0x1 << 30) | (0x1 << 13) |
833 (0x4 << 26) | (0x18 << 19);
834 REG_WRITE(ah
, AR_PHY_PLL_MODE
, regval
);
835 REG_WRITE(ah
, AR_PHY_PLL_MODE
,
836 REG_READ(ah
, AR_PHY_PLL_MODE
) & 0xfffeffff);
840 pll
= ath9k_hw_compute_pll_control(ah
, chan
);
842 REG_WRITE(ah
, AR_RTC_PLL_CONTROL
, pll
);
844 if (AR_SREV_9485(ah
) || AR_SREV_9340(ah
) || AR_SREV_9330(ah
))
847 /* Switch the core clock for ar9271 to 117Mhz */
848 if (AR_SREV_9271(ah
)) {
850 REG_WRITE(ah
, 0x50040, 0x304);
853 udelay(RTC_PLL_SETTLE_DELAY
);
855 REG_WRITE(ah
, AR_RTC_SLEEP_CLK
, AR_RTC_FORCE_DERIVED_CLK
);
857 if (AR_SREV_9340(ah
)) {
858 if (ah
->is_clk_25mhz
) {
859 REG_WRITE(ah
, AR_RTC_DERIVED_CLK
, 0x17c << 1);
860 REG_WRITE(ah
, AR_SLP32_MODE
, 0x0010f3d7);
861 REG_WRITE(ah
, AR_SLP32_INC
, 0x0001e7ae);
863 REG_WRITE(ah
, AR_RTC_DERIVED_CLK
, 0x261 << 1);
864 REG_WRITE(ah
, AR_SLP32_MODE
, 0x0010f400);
865 REG_WRITE(ah
, AR_SLP32_INC
, 0x0001e800);
871 static void ath9k_hw_init_interrupt_masks(struct ath_hw
*ah
,
872 enum nl80211_iftype opmode
)
874 u32 sync_default
= AR_INTR_SYNC_DEFAULT
;
875 u32 imr_reg
= AR_IMR_TXERR
|
881 if (AR_SREV_9340(ah
))
882 sync_default
&= ~AR_INTR_SYNC_HOST1_FATAL
;
884 if (AR_SREV_9300_20_OR_LATER(ah
)) {
885 imr_reg
|= AR_IMR_RXOK_HP
;
886 if (ah
->config
.rx_intr_mitigation
)
887 imr_reg
|= AR_IMR_RXINTM
| AR_IMR_RXMINTR
;
889 imr_reg
|= AR_IMR_RXOK_LP
;
892 if (ah
->config
.rx_intr_mitigation
)
893 imr_reg
|= AR_IMR_RXINTM
| AR_IMR_RXMINTR
;
895 imr_reg
|= AR_IMR_RXOK
;
898 if (ah
->config
.tx_intr_mitigation
)
899 imr_reg
|= AR_IMR_TXINTM
| AR_IMR_TXMINTR
;
901 imr_reg
|= AR_IMR_TXOK
;
903 if (opmode
== NL80211_IFTYPE_AP
)
904 imr_reg
|= AR_IMR_MIB
;
906 ENABLE_REGWRITE_BUFFER(ah
);
908 REG_WRITE(ah
, AR_IMR
, imr_reg
);
909 ah
->imrs2_reg
|= AR_IMR_S2_GTT
;
910 REG_WRITE(ah
, AR_IMR_S2
, ah
->imrs2_reg
);
912 if (!AR_SREV_9100(ah
)) {
913 REG_WRITE(ah
, AR_INTR_SYNC_CAUSE
, 0xFFFFFFFF);
914 REG_WRITE(ah
, AR_INTR_SYNC_ENABLE
, sync_default
);
915 REG_WRITE(ah
, AR_INTR_SYNC_MASK
, 0);
918 REGWRITE_BUFFER_FLUSH(ah
);
920 if (AR_SREV_9300_20_OR_LATER(ah
)) {
921 REG_WRITE(ah
, AR_INTR_PRIO_ASYNC_ENABLE
, 0);
922 REG_WRITE(ah
, AR_INTR_PRIO_ASYNC_MASK
, 0);
923 REG_WRITE(ah
, AR_INTR_PRIO_SYNC_ENABLE
, 0);
924 REG_WRITE(ah
, AR_INTR_PRIO_SYNC_MASK
, 0);
928 static void ath9k_hw_set_sifs_time(struct ath_hw
*ah
, u32 us
)
930 u32 val
= ath9k_hw_mac_to_clks(ah
, us
- 2);
931 val
= min(val
, (u32
) 0xFFFF);
932 REG_WRITE(ah
, AR_D_GBL_IFS_SIFS
, val
);
935 static void ath9k_hw_setslottime(struct ath_hw
*ah
, u32 us
)
937 u32 val
= ath9k_hw_mac_to_clks(ah
, us
);
938 val
= min(val
, (u32
) 0xFFFF);
939 REG_WRITE(ah
, AR_D_GBL_IFS_SLOT
, val
);
942 static void ath9k_hw_set_ack_timeout(struct ath_hw
*ah
, u32 us
)
944 u32 val
= ath9k_hw_mac_to_clks(ah
, us
);
945 val
= min(val
, (u32
) MS(0xFFFFFFFF, AR_TIME_OUT_ACK
));
946 REG_RMW_FIELD(ah
, AR_TIME_OUT
, AR_TIME_OUT_ACK
, val
);
949 static void ath9k_hw_set_cts_timeout(struct ath_hw
*ah
, u32 us
)
951 u32 val
= ath9k_hw_mac_to_clks(ah
, us
);
952 val
= min(val
, (u32
) MS(0xFFFFFFFF, AR_TIME_OUT_CTS
));
953 REG_RMW_FIELD(ah
, AR_TIME_OUT
, AR_TIME_OUT_CTS
, val
);
956 static bool ath9k_hw_set_global_txtimeout(struct ath_hw
*ah
, u32 tu
)
959 ath_dbg(ath9k_hw_common(ah
), XMIT
, "bad global tx timeout %u\n",
961 ah
->globaltxtimeout
= (u32
) -1;
964 REG_RMW_FIELD(ah
, AR_GTXTO
, AR_GTXTO_TIMEOUT_LIMIT
, tu
);
965 ah
->globaltxtimeout
= tu
;
970 void ath9k_hw_init_global_settings(struct ath_hw
*ah
)
972 struct ath_common
*common
= ath9k_hw_common(ah
);
973 struct ieee80211_conf
*conf
= &common
->hw
->conf
;
974 const struct ath9k_channel
*chan
= ah
->curchan
;
975 int acktimeout
, ctstimeout
;
978 int rx_lat
= 0, tx_lat
= 0, eifs
= 0;
981 ath_dbg(ath9k_hw_common(ah
), RESET
, "ah->misc_mode 0x%x\n",
987 if (ah
->misc_mode
!= 0)
988 REG_SET_BIT(ah
, AR_PCU_MISC
, ah
->misc_mode
);
990 if (IS_CHAN_A_FAST_CLOCK(ah
, chan
))
996 if (IS_CHAN_HALF_RATE(chan
)) {
1000 if (IS_CHAN_A_FAST_CLOCK(ah
, chan
))
1005 } else if (IS_CHAN_QUARTER_RATE(chan
)) {
1007 rx_lat
= (rx_lat
* 4) - 1;
1009 if (IS_CHAN_A_FAST_CLOCK(ah
, chan
))
1015 if (AR_SREV_9287(ah
) && AR_SREV_9287_13_OR_LATER(ah
)) {
1016 eifs
= AR_D_GBL_IFS_EIFS_ASYNC_FIFO
;
1017 reg
= AR_USEC_ASYNC_FIFO
;
1019 eifs
= REG_READ(ah
, AR_D_GBL_IFS_EIFS
)/
1021 reg
= REG_READ(ah
, AR_USEC
);
1023 rx_lat
= MS(reg
, AR_USEC_RX_LAT
);
1024 tx_lat
= MS(reg
, AR_USEC_TX_LAT
);
1026 slottime
= ah
->slottime
;
1027 if (IS_CHAN_5GHZ(chan
))
1033 /* As defined by IEEE 802.11-2007 17.3.8.6 */
1034 acktimeout
= slottime
+ sifstime
+ 3 * ah
->coverage_class
;
1035 ctstimeout
= acktimeout
;
1038 * Workaround for early ACK timeouts, add an offset to match the
1039 * initval's 64us ack timeout value. Use 48us for the CTS timeout.
1040 * This was initially only meant to work around an issue with delayed
1041 * BA frames in some implementations, but it has been found to fix ACK
1042 * timeout issues in other cases as well.
1044 if (conf
->channel
&& conf
->channel
->band
== IEEE80211_BAND_2GHZ
) {
1045 acktimeout
+= 64 - sifstime
- ah
->slottime
;
1046 ctstimeout
+= 48 - sifstime
- ah
->slottime
;
1050 ath9k_hw_set_sifs_time(ah
, sifstime
);
1051 ath9k_hw_setslottime(ah
, slottime
);
1052 ath9k_hw_set_ack_timeout(ah
, acktimeout
);
1053 ath9k_hw_set_cts_timeout(ah
, ctstimeout
);
1054 if (ah
->globaltxtimeout
!= (u32
) -1)
1055 ath9k_hw_set_global_txtimeout(ah
, ah
->globaltxtimeout
);
1057 REG_WRITE(ah
, AR_D_GBL_IFS_EIFS
, ath9k_hw_mac_to_clks(ah
, eifs
));
1058 REG_RMW(ah
, AR_USEC
,
1059 (common
->clockrate
- 1) |
1060 SM(rx_lat
, AR_USEC_RX_LAT
) |
1061 SM(tx_lat
, AR_USEC_TX_LAT
),
1062 AR_USEC_TX_LAT
| AR_USEC_RX_LAT
| AR_USEC_USEC
);
1065 EXPORT_SYMBOL(ath9k_hw_init_global_settings
);
1067 void ath9k_hw_deinit(struct ath_hw
*ah
)
1069 struct ath_common
*common
= ath9k_hw_common(ah
);
1071 if (common
->state
< ATH_HW_INITIALIZED
)
1074 ath9k_hw_setpower(ah
, ATH9K_PM_FULL_SLEEP
);
1077 ath9k_hw_rf_free_ext_banks(ah
);
1079 EXPORT_SYMBOL(ath9k_hw_deinit
);
1085 u32
ath9k_regd_get_ctl(struct ath_regulatory
*reg
, struct ath9k_channel
*chan
)
1087 u32 ctl
= ath_regd_get_band_ctl(reg
, chan
->chan
->band
);
1089 if (IS_CHAN_B(chan
))
1091 else if (IS_CHAN_G(chan
))
1099 /****************************************/
1100 /* Reset and Channel Switching Routines */
1101 /****************************************/
1103 static inline void ath9k_hw_set_dma(struct ath_hw
*ah
)
1105 struct ath_common
*common
= ath9k_hw_common(ah
);
1107 ENABLE_REGWRITE_BUFFER(ah
);
1110 * set AHB_MODE not to do cacheline prefetches
1112 if (!AR_SREV_9300_20_OR_LATER(ah
))
1113 REG_SET_BIT(ah
, AR_AHB_MODE
, AR_AHB_PREFETCH_RD_EN
);
1116 * let mac dma reads be in 128 byte chunks
1118 REG_RMW(ah
, AR_TXCFG
, AR_TXCFG_DMASZ_128B
, AR_TXCFG_DMASZ_MASK
);
1120 REGWRITE_BUFFER_FLUSH(ah
);
1123 * Restore TX Trigger Level to its pre-reset value.
1124 * The initial value depends on whether aggregation is enabled, and is
1125 * adjusted whenever underruns are detected.
1127 if (!AR_SREV_9300_20_OR_LATER(ah
))
1128 REG_RMW_FIELD(ah
, AR_TXCFG
, AR_FTRIG
, ah
->tx_trig_level
);
1130 ENABLE_REGWRITE_BUFFER(ah
);
1133 * let mac dma writes be in 128 byte chunks
1135 REG_RMW(ah
, AR_RXCFG
, AR_RXCFG_DMASZ_128B
, AR_RXCFG_DMASZ_MASK
);
1138 * Setup receive FIFO threshold to hold off TX activities
1140 REG_WRITE(ah
, AR_RXFIFO_CFG
, 0x200);
1142 if (AR_SREV_9300_20_OR_LATER(ah
)) {
1143 REG_RMW_FIELD(ah
, AR_RXBP_THRESH
, AR_RXBP_THRESH_HP
, 0x1);
1144 REG_RMW_FIELD(ah
, AR_RXBP_THRESH
, AR_RXBP_THRESH_LP
, 0x1);
1146 ath9k_hw_set_rx_bufsize(ah
, common
->rx_bufsize
-
1147 ah
->caps
.rx_status_len
);
1151 * reduce the number of usable entries in PCU TXBUF to avoid
1152 * wrap around issues.
1154 if (AR_SREV_9285(ah
)) {
1155 /* For AR9285 the number of Fifos are reduced to half.
1156 * So set the usable tx buf size also to half to
1157 * avoid data/delimiter underruns
1159 REG_WRITE(ah
, AR_PCU_TXBUF_CTRL
,
1160 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE
);
1161 } else if (!AR_SREV_9271(ah
)) {
1162 REG_WRITE(ah
, AR_PCU_TXBUF_CTRL
,
1163 AR_PCU_TXBUF_CTRL_USABLE_SIZE
);
1166 REGWRITE_BUFFER_FLUSH(ah
);
1168 if (AR_SREV_9300_20_OR_LATER(ah
))
1169 ath9k_hw_reset_txstatus_ring(ah
);
1172 static void ath9k_hw_set_operating_mode(struct ath_hw
*ah
, int opmode
)
1174 u32 mask
= AR_STA_ID1_STA_AP
| AR_STA_ID1_ADHOC
;
1175 u32 set
= AR_STA_ID1_KSRCH_MODE
;
1178 case NL80211_IFTYPE_ADHOC
:
1179 case NL80211_IFTYPE_MESH_POINT
:
1180 set
|= AR_STA_ID1_ADHOC
;
1181 REG_SET_BIT(ah
, AR_CFG
, AR_CFG_AP_ADHOC_INDICATION
);
1183 case NL80211_IFTYPE_AP
:
1184 set
|= AR_STA_ID1_STA_AP
;
1186 case NL80211_IFTYPE_STATION
:
1187 REG_CLR_BIT(ah
, AR_CFG
, AR_CFG_AP_ADHOC_INDICATION
);
1190 if (!ah
->is_monitoring
)
1194 REG_RMW(ah
, AR_STA_ID1
, set
, mask
);
1197 void ath9k_hw_get_delta_slope_vals(struct ath_hw
*ah
, u32 coef_scaled
,
1198 u32
*coef_mantissa
, u32
*coef_exponent
)
1200 u32 coef_exp
, coef_man
;
1202 for (coef_exp
= 31; coef_exp
> 0; coef_exp
--)
1203 if ((coef_scaled
>> coef_exp
) & 0x1)
1206 coef_exp
= 14 - (coef_exp
- COEF_SCALE_S
);
1208 coef_man
= coef_scaled
+ (1 << (COEF_SCALE_S
- coef_exp
- 1));
1210 *coef_mantissa
= coef_man
>> (COEF_SCALE_S
- coef_exp
);
1211 *coef_exponent
= coef_exp
- 16;
1214 static bool ath9k_hw_set_reset(struct ath_hw
*ah
, int type
)
1219 if (AR_SREV_9100(ah
)) {
1220 REG_RMW_FIELD(ah
, AR_RTC_DERIVED_CLK
,
1221 AR_RTC_DERIVED_CLK_PERIOD
, 1);
1222 (void)REG_READ(ah
, AR_RTC_DERIVED_CLK
);
1225 ENABLE_REGWRITE_BUFFER(ah
);
1227 if (AR_SREV_9300_20_OR_LATER(ah
)) {
1228 REG_WRITE(ah
, AR_WA
, ah
->WARegVal
);
1232 REG_WRITE(ah
, AR_RTC_FORCE_WAKE
, AR_RTC_FORCE_WAKE_EN
|
1233 AR_RTC_FORCE_WAKE_ON_INT
);
1235 if (AR_SREV_9100(ah
)) {
1236 rst_flags
= AR_RTC_RC_MAC_WARM
| AR_RTC_RC_MAC_COLD
|
1237 AR_RTC_RC_COLD_RESET
| AR_RTC_RC_WARM_RESET
;
1239 tmpReg
= REG_READ(ah
, AR_INTR_SYNC_CAUSE
);
1241 (AR_INTR_SYNC_LOCAL_TIMEOUT
|
1242 AR_INTR_SYNC_RADM_CPL_TIMEOUT
)) {
1244 REG_WRITE(ah
, AR_INTR_SYNC_ENABLE
, 0);
1247 if (!AR_SREV_9300_20_OR_LATER(ah
))
1249 REG_WRITE(ah
, AR_RC
, val
);
1251 } else if (!AR_SREV_9300_20_OR_LATER(ah
))
1252 REG_WRITE(ah
, AR_RC
, AR_RC_AHB
);
1254 rst_flags
= AR_RTC_RC_MAC_WARM
;
1255 if (type
== ATH9K_RESET_COLD
)
1256 rst_flags
|= AR_RTC_RC_MAC_COLD
;
1259 if (AR_SREV_9330(ah
)) {
1264 * call external reset function to reset WMAC if:
1265 * - doing a cold reset
1266 * - we have pending frames in the TX queues
1269 for (i
= 0; i
< AR_NUM_QCU
; i
++) {
1270 npend
= ath9k_hw_numtxpending(ah
, i
);
1275 if (ah
->external_reset
&&
1276 (npend
|| type
== ATH9K_RESET_COLD
)) {
1279 ath_dbg(ath9k_hw_common(ah
), RESET
,
1280 "reset MAC via external reset\n");
1282 reset_err
= ah
->external_reset();
1284 ath_err(ath9k_hw_common(ah
),
1285 "External reset failed, err=%d\n",
1290 REG_WRITE(ah
, AR_RTC_RESET
, 1);
1294 REG_WRITE(ah
, AR_RTC_RC
, rst_flags
);
1296 REGWRITE_BUFFER_FLUSH(ah
);
1300 REG_WRITE(ah
, AR_RTC_RC
, 0);
1301 if (!ath9k_hw_wait(ah
, AR_RTC_RC
, AR_RTC_RC_M
, 0, AH_WAIT_TIMEOUT
)) {
1302 ath_dbg(ath9k_hw_common(ah
), RESET
, "RTC stuck in MAC reset\n");
1306 if (!AR_SREV_9100(ah
))
1307 REG_WRITE(ah
, AR_RC
, 0);
1309 if (AR_SREV_9100(ah
))
1315 static bool ath9k_hw_set_reset_power_on(struct ath_hw
*ah
)
1317 ENABLE_REGWRITE_BUFFER(ah
);
1319 if (AR_SREV_9300_20_OR_LATER(ah
)) {
1320 REG_WRITE(ah
, AR_WA
, ah
->WARegVal
);
1324 REG_WRITE(ah
, AR_RTC_FORCE_WAKE
, AR_RTC_FORCE_WAKE_EN
|
1325 AR_RTC_FORCE_WAKE_ON_INT
);
1327 if (!AR_SREV_9100(ah
) && !AR_SREV_9300_20_OR_LATER(ah
))
1328 REG_WRITE(ah
, AR_RC
, AR_RC_AHB
);
1330 REG_WRITE(ah
, AR_RTC_RESET
, 0);
1332 REGWRITE_BUFFER_FLUSH(ah
);
1334 if (!AR_SREV_9300_20_OR_LATER(ah
))
1337 if (!AR_SREV_9100(ah
) && !AR_SREV_9300_20_OR_LATER(ah
))
1338 REG_WRITE(ah
, AR_RC
, 0);
1340 REG_WRITE(ah
, AR_RTC_RESET
, 1);
1342 if (!ath9k_hw_wait(ah
,
1347 ath_dbg(ath9k_hw_common(ah
), RESET
, "RTC not waking up\n");
1351 return ath9k_hw_set_reset(ah
, ATH9K_RESET_WARM
);
1354 static bool ath9k_hw_set_reset_reg(struct ath_hw
*ah
, u32 type
)
1358 if (AR_SREV_9300_20_OR_LATER(ah
)) {
1359 REG_WRITE(ah
, AR_WA
, ah
->WARegVal
);
1363 REG_WRITE(ah
, AR_RTC_FORCE_WAKE
,
1364 AR_RTC_FORCE_WAKE_EN
| AR_RTC_FORCE_WAKE_ON_INT
);
1367 case ATH9K_RESET_POWER_ON
:
1368 ret
= ath9k_hw_set_reset_power_on(ah
);
1370 case ATH9K_RESET_WARM
:
1371 case ATH9K_RESET_COLD
:
1372 ret
= ath9k_hw_set_reset(ah
, type
);
1378 if (ah
->caps
.hw_caps
& ATH9K_HW_CAP_MCI
)
1379 REG_WRITE(ah
, AR_RTC_KEEP_AWAKE
, 0x2);
1384 static bool ath9k_hw_chip_reset(struct ath_hw
*ah
,
1385 struct ath9k_channel
*chan
)
1387 int reset_type
= ATH9K_RESET_WARM
;
1389 if (AR_SREV_9280(ah
)) {
1390 if (ah
->eep_ops
->get_eeprom(ah
, EEP_OL_PWRCTRL
))
1391 reset_type
= ATH9K_RESET_POWER_ON
;
1393 reset_type
= ATH9K_RESET_COLD
;
1396 if (!ath9k_hw_set_reset_reg(ah
, reset_type
))
1399 if (!ath9k_hw_setpower(ah
, ATH9K_PM_AWAKE
))
1402 ah
->chip_fullsleep
= false;
1403 ath9k_hw_init_pll(ah
, chan
);
1404 ath9k_hw_set_rfmode(ah
, chan
);
1409 static bool ath9k_hw_channel_change(struct ath_hw
*ah
,
1410 struct ath9k_channel
*chan
)
1412 struct ath_common
*common
= ath9k_hw_common(ah
);
1415 bool edma
= !!(ah
->caps
.hw_caps
& ATH9K_HW_CAP_EDMA
);
1416 bool band_switch
, mode_diff
;
1419 band_switch
= (chan
->channelFlags
& (CHANNEL_2GHZ
| CHANNEL_5GHZ
)) !=
1420 (ah
->curchan
->channelFlags
& (CHANNEL_2GHZ
|
1422 mode_diff
= (chan
->chanmode
!= ah
->curchan
->chanmode
);
1424 for (qnum
= 0; qnum
< AR_NUM_QCU
; qnum
++) {
1425 if (ath9k_hw_numtxpending(ah
, qnum
)) {
1426 ath_dbg(common
, QUEUE
,
1427 "Transmit frames pending on queue %d\n", qnum
);
1432 if (!ath9k_hw_rfbus_req(ah
)) {
1433 ath_err(common
, "Could not kill baseband RX\n");
1437 if (edma
&& (band_switch
|| mode_diff
)) {
1438 ath9k_hw_mark_phy_inactive(ah
);
1441 ath9k_hw_init_pll(ah
, NULL
);
1443 if (ath9k_hw_fast_chan_change(ah
, chan
, &ini_reloaded
)) {
1444 ath_err(common
, "Failed to do fast channel change\n");
1449 ath9k_hw_set_channel_regs(ah
, chan
);
1451 r
= ath9k_hw_rf_set_freq(ah
, chan
);
1453 ath_err(common
, "Failed to set channel\n");
1456 ath9k_hw_set_clockrate(ah
);
1457 ath9k_hw_apply_txpower(ah
, chan
);
1458 ath9k_hw_rfbus_done(ah
);
1460 if (IS_CHAN_OFDM(chan
) || IS_CHAN_HT(chan
))
1461 ath9k_hw_set_delta_slope(ah
, chan
);
1463 ath9k_hw_spur_mitigate_freq(ah
, chan
);
1465 if (edma
&& (band_switch
|| mode_diff
)) {
1466 ah
->ah_flags
|= AH_FASTCC
;
1467 if (band_switch
|| ini_reloaded
)
1468 ah
->eep_ops
->set_board_values(ah
, chan
);
1470 ath9k_hw_init_bb(ah
, chan
);
1472 if (band_switch
|| ini_reloaded
)
1473 ath9k_hw_init_cal(ah
, chan
);
1474 ah
->ah_flags
&= ~AH_FASTCC
;
1480 static void ath9k_hw_apply_gpio_override(struct ath_hw
*ah
)
1482 u32 gpio_mask
= ah
->gpio_mask
;
1485 for (i
= 0; gpio_mask
; i
++, gpio_mask
>>= 1) {
1486 if (!(gpio_mask
& 1))
1489 ath9k_hw_cfg_output(ah
, i
, AR_GPIO_OUTPUT_MUX_AS_OUTPUT
);
1490 ath9k_hw_set_gpio(ah
, i
, !!(ah
->gpio_val
& BIT(i
)));
1494 static bool ath9k_hw_check_dcs(u32 dma_dbg
, u32 num_dcu_states
,
1495 int *hang_state
, int *hang_pos
)
1497 static u32 dcu_chain_state
[] = {5, 6, 9}; /* DCU chain stuck states */
1498 u32 chain_state
, dcs_pos
, i
;
1500 for (dcs_pos
= 0; dcs_pos
< num_dcu_states
; dcs_pos
++) {
1501 chain_state
= (dma_dbg
>> (5 * dcs_pos
)) & 0x1f;
1502 for (i
= 0; i
< 3; i
++) {
1503 if (chain_state
== dcu_chain_state
[i
]) {
1504 *hang_state
= chain_state
;
1505 *hang_pos
= dcs_pos
;
1513 #define DCU_COMPLETE_STATE 1
1514 #define DCU_COMPLETE_STATE_MASK 0x3
1515 #define NUM_STATUS_READS 50
1516 static bool ath9k_hw_detect_mac_hang(struct ath_hw
*ah
)
1518 u32 chain_state
, comp_state
, dcs_reg
= AR_DMADBG_4
;
1519 u32 i
, hang_pos
, hang_state
, num_state
= 6;
1521 comp_state
= REG_READ(ah
, AR_DMADBG_6
);
1523 if ((comp_state
& DCU_COMPLETE_STATE_MASK
) != DCU_COMPLETE_STATE
) {
1524 ath_dbg(ath9k_hw_common(ah
), RESET
,
1525 "MAC Hang signature not found at DCU complete\n");
1529 chain_state
= REG_READ(ah
, dcs_reg
);
1530 if (ath9k_hw_check_dcs(chain_state
, num_state
, &hang_state
, &hang_pos
))
1531 goto hang_check_iter
;
1533 dcs_reg
= AR_DMADBG_5
;
1535 chain_state
= REG_READ(ah
, dcs_reg
);
1536 if (ath9k_hw_check_dcs(chain_state
, num_state
, &hang_state
, &hang_pos
))
1537 goto hang_check_iter
;
1539 ath_dbg(ath9k_hw_common(ah
), RESET
,
1540 "MAC Hang signature 1 not found\n");
1544 ath_dbg(ath9k_hw_common(ah
), RESET
,
1545 "DCU registers: chain %08x complete %08x Hang: state %d pos %d\n",
1546 chain_state
, comp_state
, hang_state
, hang_pos
);
1548 for (i
= 0; i
< NUM_STATUS_READS
; i
++) {
1549 chain_state
= REG_READ(ah
, dcs_reg
);
1550 chain_state
= (chain_state
>> (5 * hang_pos
)) & 0x1f;
1551 comp_state
= REG_READ(ah
, AR_DMADBG_6
);
1553 if (((comp_state
& DCU_COMPLETE_STATE_MASK
) !=
1554 DCU_COMPLETE_STATE
) ||
1555 (chain_state
!= hang_state
))
1559 ath_dbg(ath9k_hw_common(ah
), RESET
, "MAC Hang signature 1 found\n");
1564 bool ath9k_hw_check_alive(struct ath_hw
*ah
)
1569 if (AR_SREV_9300(ah
))
1570 return !ath9k_hw_detect_mac_hang(ah
);
1572 if (AR_SREV_9285_12_OR_LATER(ah
))
1576 reg
= REG_READ(ah
, AR_OBS_BUS_1
);
1578 if ((reg
& 0x7E7FFFEF) == 0x00702400)
1581 switch (reg
& 0x7E000B00) {
1589 } while (count
-- > 0);
1593 EXPORT_SYMBOL(ath9k_hw_check_alive
);
1596 * Fast channel change:
1597 * (Change synthesizer based on channel freq without resetting chip)
1601 * - Chip is just coming out of full sleep
1602 * - Channel to be set is same as current channel
1603 * - Channel flags are different, (eg.,moving from 2GHz to 5GHz channel)
1605 static int ath9k_hw_do_fastcc(struct ath_hw
*ah
, struct ath9k_channel
*chan
)
1607 struct ath_common
*common
= ath9k_hw_common(ah
);
1610 if (AR_SREV_9280(ah
) && common
->bus_ops
->ath_bus_type
== ATH_PCI
)
1613 if (ah
->chip_fullsleep
)
1619 if (chan
->channel
== ah
->curchan
->channel
)
1622 if ((chan
->channelFlags
& CHANNEL_ALL
) !=
1623 (ah
->curchan
->channelFlags
& CHANNEL_ALL
))
1626 if (!ath9k_hw_check_alive(ah
))
1630 * For AR9462, make sure that calibration data for
1631 * re-using are present.
1633 if (AR_SREV_9462(ah
) && (!ah
->caldata
||
1634 !ah
->caldata
->done_txiqcal_once
||
1635 !ah
->caldata
->done_txclcal_once
||
1636 !ah
->caldata
->rtt_hist
.num_readings
))
1639 ath_dbg(common
, RESET
, "FastChannelChange for %d -> %d\n",
1640 ah
->curchan
->channel
, chan
->channel
);
1642 ret
= ath9k_hw_channel_change(ah
, chan
);
1646 ath9k_hw_loadnf(ah
, ah
->curchan
);
1647 ath9k_hw_start_nfcal(ah
, true);
1649 if ((ah
->caps
.hw_caps
& ATH9K_HW_CAP_MCI
) && ar9003_mci_is_ready(ah
))
1650 ar9003_mci_2g5g_switch(ah
, true);
1652 if (AR_SREV_9271(ah
))
1653 ar9002_hw_load_ani_reg(ah
, chan
);
1660 int ath9k_hw_reset(struct ath_hw
*ah
, struct ath9k_channel
*chan
,
1661 struct ath9k_hw_cal_data
*caldata
, bool fastcc
)
1663 struct ath_common
*common
= ath9k_hw_common(ah
);
1669 bool start_mci_reset
= false;
1670 bool mci
= !!(ah
->caps
.hw_caps
& ATH9K_HW_CAP_MCI
);
1671 bool save_fullsleep
= ah
->chip_fullsleep
;
1674 start_mci_reset
= ar9003_mci_start_reset(ah
, chan
);
1675 if (start_mci_reset
)
1679 if (!ath9k_hw_setpower(ah
, ATH9K_PM_AWAKE
))
1682 if (ah
->curchan
&& !ah
->chip_fullsleep
)
1683 ath9k_hw_getnf(ah
, ah
->curchan
);
1685 ah
->caldata
= caldata
;
1687 (chan
->channel
!= caldata
->channel
||
1688 (chan
->channelFlags
& ~CHANNEL_CW_INT
) !=
1689 (caldata
->channelFlags
& ~CHANNEL_CW_INT
))) {
1690 /* Operating channel changed, reset channel calibration data */
1691 memset(caldata
, 0, sizeof(*caldata
));
1692 ath9k_init_nfcal_hist_buffer(ah
, chan
);
1694 ah
->noise
= ath9k_hw_getchan_noise(ah
, chan
);
1697 r
= ath9k_hw_do_fastcc(ah
, chan
);
1703 ar9003_mci_stop_bt(ah
, save_fullsleep
);
1705 saveDefAntenna
= REG_READ(ah
, AR_DEF_ANTENNA
);
1706 if (saveDefAntenna
== 0)
1709 macStaId1
= REG_READ(ah
, AR_STA_ID1
) & AR_STA_ID1_BASE_RATE_11B
;
1711 /* For chips on which RTC reset is done, save TSF before it gets cleared */
1712 if (AR_SREV_9100(ah
) ||
1713 (AR_SREV_9280(ah
) && ah
->eep_ops
->get_eeprom(ah
, EEP_OL_PWRCTRL
)))
1714 tsf
= ath9k_hw_gettsf64(ah
);
1716 saveLedState
= REG_READ(ah
, AR_CFG_LED
) &
1717 (AR_CFG_LED_ASSOC_CTL
| AR_CFG_LED_MODE_SEL
|
1718 AR_CFG_LED_BLINK_THRESH_SEL
| AR_CFG_LED_BLINK_SLOW
);
1720 ath9k_hw_mark_phy_inactive(ah
);
1722 ah
->paprd_table_write_done
= false;
1724 /* Only required on the first reset */
1725 if (AR_SREV_9271(ah
) && ah
->htc_reset_init
) {
1727 AR9271_RESET_POWER_DOWN_CONTROL
,
1728 AR9271_RADIO_RF_RST
);
1732 if (!ath9k_hw_chip_reset(ah
, chan
)) {
1733 ath_err(common
, "Chip reset failed\n");
1737 /* Only required on the first reset */
1738 if (AR_SREV_9271(ah
) && ah
->htc_reset_init
) {
1739 ah
->htc_reset_init
= false;
1741 AR9271_RESET_POWER_DOWN_CONTROL
,
1742 AR9271_GATE_MAC_CTL
);
1748 ath9k_hw_settsf64(ah
, tsf
);
1750 if (AR_SREV_9280_20_OR_LATER(ah
))
1751 REG_SET_BIT(ah
, AR_GPIO_INPUT_EN_VAL
, AR_GPIO_JTAG_DISABLE
);
1753 if (!AR_SREV_9300_20_OR_LATER(ah
))
1754 ar9002_hw_enable_async_fifo(ah
);
1756 r
= ath9k_hw_process_ini(ah
, chan
);
1761 ar9003_mci_reset(ah
, false, IS_CHAN_2GHZ(chan
), save_fullsleep
);
1764 * Some AR91xx SoC devices frequently fail to accept TSF writes
1765 * right after the chip reset. When that happens, write a new
1766 * value after the initvals have been applied, with an offset
1767 * based on measured time difference
1769 if (AR_SREV_9100(ah
) && (ath9k_hw_gettsf64(ah
) < tsf
)) {
1771 ath9k_hw_settsf64(ah
, tsf
);
1774 /* Setup MFP options for CCMP */
1775 if (AR_SREV_9280_20_OR_LATER(ah
)) {
1776 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1777 * frames when constructing CCMP AAD. */
1778 REG_RMW_FIELD(ah
, AR_AES_MUTE_MASK1
, AR_AES_MUTE_MASK1_FC_MGMT
,
1780 ah
->sw_mgmt_crypto
= false;
1781 } else if (AR_SREV_9160_10_OR_LATER(ah
)) {
1782 /* Disable hardware crypto for management frames */
1783 REG_CLR_BIT(ah
, AR_PCU_MISC_MODE2
,
1784 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE
);
1785 REG_SET_BIT(ah
, AR_PCU_MISC_MODE2
,
1786 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT
);
1787 ah
->sw_mgmt_crypto
= true;
1789 ah
->sw_mgmt_crypto
= true;
1791 if (IS_CHAN_OFDM(chan
) || IS_CHAN_HT(chan
))
1792 ath9k_hw_set_delta_slope(ah
, chan
);
1794 ath9k_hw_spur_mitigate_freq(ah
, chan
);
1795 ah
->eep_ops
->set_board_values(ah
, chan
);
1797 ENABLE_REGWRITE_BUFFER(ah
);
1799 REG_WRITE(ah
, AR_STA_ID0
, get_unaligned_le32(common
->macaddr
));
1800 REG_WRITE(ah
, AR_STA_ID1
, get_unaligned_le16(common
->macaddr
+ 4)
1802 | AR_STA_ID1_RTS_USE_DEF
1804 ack_6mb
? AR_STA_ID1_ACKCTS_6MB
: 0)
1805 | ah
->sta_id1_defaults
);
1806 ath_hw_setbssidmask(common
);
1807 REG_WRITE(ah
, AR_DEF_ANTENNA
, saveDefAntenna
);
1808 ath9k_hw_write_associd(ah
);
1809 REG_WRITE(ah
, AR_ISR
, ~0);
1810 REG_WRITE(ah
, AR_RSSI_THR
, INIT_RSSI_THR
);
1812 REGWRITE_BUFFER_FLUSH(ah
);
1814 ath9k_hw_set_operating_mode(ah
, ah
->opmode
);
1816 r
= ath9k_hw_rf_set_freq(ah
, chan
);
1820 ath9k_hw_set_clockrate(ah
);
1822 ENABLE_REGWRITE_BUFFER(ah
);
1824 for (i
= 0; i
< AR_NUM_DCU
; i
++)
1825 REG_WRITE(ah
, AR_DQCUMASK(i
), 1 << i
);
1827 REGWRITE_BUFFER_FLUSH(ah
);
1830 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++)
1831 ath9k_hw_resettxqueue(ah
, i
);
1833 ath9k_hw_init_interrupt_masks(ah
, ah
->opmode
);
1834 ath9k_hw_ani_cache_ini_regs(ah
);
1835 ath9k_hw_init_qos(ah
);
1837 if (ah
->caps
.hw_caps
& ATH9K_HW_CAP_RFSILENT
)
1838 ath9k_hw_cfg_gpio_input(ah
, ah
->rfkill_gpio
);
1840 ath9k_hw_init_global_settings(ah
);
1842 if (AR_SREV_9287(ah
) && AR_SREV_9287_13_OR_LATER(ah
)) {
1843 REG_SET_BIT(ah
, AR_MAC_PCU_LOGIC_ANALYZER
,
1844 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768
);
1845 REG_RMW_FIELD(ah
, AR_AHB_MODE
, AR_AHB_CUSTOM_BURST_EN
,
1846 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL
);
1847 REG_SET_BIT(ah
, AR_PCU_MISC_MODE2
,
1848 AR_PCU_MISC_MODE2_ENABLE_AGGWEP
);
1851 REG_SET_BIT(ah
, AR_STA_ID1
, AR_STA_ID1_PRESERVE_SEQNUM
);
1853 ath9k_hw_set_dma(ah
);
1855 REG_WRITE(ah
, AR_OBS
, 8);
1857 if (ah
->config
.rx_intr_mitigation
) {
1858 REG_RMW_FIELD(ah
, AR_RIMT
, AR_RIMT_LAST
, 500);
1859 REG_RMW_FIELD(ah
, AR_RIMT
, AR_RIMT_FIRST
, 2000);
1862 if (ah
->config
.tx_intr_mitigation
) {
1863 REG_RMW_FIELD(ah
, AR_TIMT
, AR_TIMT_LAST
, 300);
1864 REG_RMW_FIELD(ah
, AR_TIMT
, AR_TIMT_FIRST
, 750);
1867 ath9k_hw_init_bb(ah
, chan
);
1870 caldata
->done_txiqcal_once
= false;
1871 caldata
->done_txclcal_once
= false;
1872 caldata
->rtt_hist
.num_readings
= 0;
1874 if (!ath9k_hw_init_cal(ah
, chan
))
1877 ath9k_hw_loadnf(ah
, chan
);
1878 ath9k_hw_start_nfcal(ah
, true);
1880 if (mci
&& ar9003_mci_end_reset(ah
, chan
, caldata
))
1883 ENABLE_REGWRITE_BUFFER(ah
);
1885 ath9k_hw_restore_chainmask(ah
);
1886 REG_WRITE(ah
, AR_CFG_LED
, saveLedState
| AR_CFG_SCLK_32KHZ
);
1888 REGWRITE_BUFFER_FLUSH(ah
);
1891 * For big endian systems turn on swapping for descriptors
1893 if (AR_SREV_9100(ah
)) {
1895 mask
= REG_READ(ah
, AR_CFG
);
1896 if (mask
& (AR_CFG_SWRB
| AR_CFG_SWTB
| AR_CFG_SWRG
)) {
1897 ath_dbg(common
, RESET
, "CFG Byte Swap Set 0x%x\n",
1901 INIT_CONFIG_STATUS
| AR_CFG_SWRB
| AR_CFG_SWTB
;
1902 REG_WRITE(ah
, AR_CFG
, mask
);
1903 ath_dbg(common
, RESET
, "Setting CFG 0x%x\n",
1904 REG_READ(ah
, AR_CFG
));
1907 if (common
->bus_ops
->ath_bus_type
== ATH_USB
) {
1908 /* Configure AR9271 target WLAN */
1909 if (AR_SREV_9271(ah
))
1910 REG_WRITE(ah
, AR_CFG
, AR_CFG_SWRB
| AR_CFG_SWTB
);
1912 REG_WRITE(ah
, AR_CFG
, AR_CFG_SWTD
| AR_CFG_SWRD
);
1915 else if (AR_SREV_9330(ah
) || AR_SREV_9340(ah
))
1916 REG_RMW(ah
, AR_CFG
, AR_CFG_SWRB
| AR_CFG_SWTB
, 0);
1918 REG_WRITE(ah
, AR_CFG
, AR_CFG_SWTD
| AR_CFG_SWRD
);
1922 if (ath9k_hw_btcoex_is_enabled(ah
))
1923 ath9k_hw_btcoex_enable(ah
);
1926 ar9003_mci_check_bt(ah
);
1928 if (AR_SREV_9300_20_OR_LATER(ah
)) {
1929 ar9003_hw_bb_watchdog_config(ah
);
1931 ar9003_hw_disable_phy_restart(ah
);
1934 ath9k_hw_apply_gpio_override(ah
);
1938 EXPORT_SYMBOL(ath9k_hw_reset
);
1940 /******************************/
1941 /* Power Management (Chipset) */
1942 /******************************/
1945 * Notify Power Mgt is disabled in self-generated frames.
1946 * If requested, force chip to sleep.
1948 static void ath9k_set_power_sleep(struct ath_hw
*ah
, int setChip
)
1950 REG_SET_BIT(ah
, AR_STA_ID1
, AR_STA_ID1_PWR_SAV
);
1952 if (AR_SREV_9462(ah
)) {
1953 REG_WRITE(ah
, AR_TIMER_MODE
,
1954 REG_READ(ah
, AR_TIMER_MODE
) & 0xFFFFFF00);
1955 REG_WRITE(ah
, AR_NDP2_TIMER_MODE
, REG_READ(ah
,
1956 AR_NDP2_TIMER_MODE
) & 0xFFFFFF00);
1957 REG_WRITE(ah
, AR_SLP32_INC
,
1958 REG_READ(ah
, AR_SLP32_INC
) & 0xFFF00000);
1959 /* xxx Required for WLAN only case ? */
1960 REG_WRITE(ah
, AR_MCI_INTERRUPT_RX_MSG_EN
, 0);
1965 * Clear the RTC force wake bit to allow the
1966 * mac to go to sleep.
1968 REG_CLR_BIT(ah
, AR_RTC_FORCE_WAKE
, AR_RTC_FORCE_WAKE_EN
);
1970 if (AR_SREV_9462(ah
))
1973 if (!AR_SREV_9100(ah
) && !AR_SREV_9300_20_OR_LATER(ah
))
1974 REG_WRITE(ah
, AR_RC
, AR_RC_AHB
| AR_RC_HOSTIF
);
1976 /* Shutdown chip. Active low */
1977 if (!AR_SREV_5416(ah
) && !AR_SREV_9271(ah
)) {
1978 REG_CLR_BIT(ah
, AR_RTC_RESET
, AR_RTC_RESET_EN
);
1983 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
1984 if (AR_SREV_9300_20_OR_LATER(ah
))
1985 REG_WRITE(ah
, AR_WA
, ah
->WARegVal
& ~AR_WA_D3_L1_DISABLE
);
1989 * Notify Power Management is enabled in self-generating
1990 * frames. If request, set power mode of chip to
1991 * auto/normal. Duration in units of 128us (1/8 TU).
1993 static void ath9k_set_power_network_sleep(struct ath_hw
*ah
, int setChip
)
1997 REG_SET_BIT(ah
, AR_STA_ID1
, AR_STA_ID1_PWR_SAV
);
1999 struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
2001 if (!(pCap
->hw_caps
& ATH9K_HW_CAP_AUTOSLEEP
)) {
2002 /* Set WakeOnInterrupt bit; clear ForceWake bit */
2003 REG_WRITE(ah
, AR_RTC_FORCE_WAKE
,
2004 AR_RTC_FORCE_WAKE_ON_INT
);
2007 /* When chip goes into network sleep, it could be waken
2008 * up by MCI_INT interrupt caused by BT's HW messages
2009 * (LNA_xxx, CONT_xxx) which chould be in a very fast
2010 * rate (~100us). This will cause chip to leave and
2011 * re-enter network sleep mode frequently, which in
2012 * consequence will have WLAN MCI HW to generate lots of
2013 * SYS_WAKING and SYS_SLEEPING messages which will make
2014 * BT CPU to busy to process.
2016 if (AR_SREV_9462(ah
)) {
2017 val
= REG_READ(ah
, AR_MCI_INTERRUPT_RX_MSG_EN
) &
2018 ~AR_MCI_INTERRUPT_RX_HW_MSG_MASK
;
2019 REG_WRITE(ah
, AR_MCI_INTERRUPT_RX_MSG_EN
, val
);
2022 * Clear the RTC force wake bit to allow the
2023 * mac to go to sleep.
2025 REG_CLR_BIT(ah
, AR_RTC_FORCE_WAKE
,
2026 AR_RTC_FORCE_WAKE_EN
);
2028 if (AR_SREV_9462(ah
))
2033 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
2034 if (AR_SREV_9300_20_OR_LATER(ah
))
2035 REG_WRITE(ah
, AR_WA
, ah
->WARegVal
& ~AR_WA_D3_L1_DISABLE
);
2038 static bool ath9k_hw_set_power_awake(struct ath_hw
*ah
, int setChip
)
2043 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */
2044 if (AR_SREV_9300_20_OR_LATER(ah
)) {
2045 REG_WRITE(ah
, AR_WA
, ah
->WARegVal
);
2050 if ((REG_READ(ah
, AR_RTC_STATUS
) &
2051 AR_RTC_STATUS_M
) == AR_RTC_STATUS_SHUTDOWN
) {
2052 if (!ath9k_hw_set_reset_reg(ah
, ATH9K_RESET_POWER_ON
)) {
2055 if (!AR_SREV_9300_20_OR_LATER(ah
))
2056 ath9k_hw_init_pll(ah
, NULL
);
2058 if (AR_SREV_9100(ah
))
2059 REG_SET_BIT(ah
, AR_RTC_RESET
,
2062 REG_SET_BIT(ah
, AR_RTC_FORCE_WAKE
,
2063 AR_RTC_FORCE_WAKE_EN
);
2066 for (i
= POWER_UP_TIME
/ 50; i
> 0; i
--) {
2067 val
= REG_READ(ah
, AR_RTC_STATUS
) & AR_RTC_STATUS_M
;
2068 if (val
== AR_RTC_STATUS_ON
)
2071 REG_SET_BIT(ah
, AR_RTC_FORCE_WAKE
,
2072 AR_RTC_FORCE_WAKE_EN
);
2075 ath_err(ath9k_hw_common(ah
),
2076 "Failed to wakeup in %uus\n",
2077 POWER_UP_TIME
/ 20);
2082 REG_CLR_BIT(ah
, AR_STA_ID1
, AR_STA_ID1_PWR_SAV
);
2087 bool ath9k_hw_setpower(struct ath_hw
*ah
, enum ath9k_power_mode mode
)
2089 struct ath_common
*common
= ath9k_hw_common(ah
);
2090 int status
= true, setChip
= true;
2091 static const char *modes
[] = {
2098 if (ah
->power_mode
== mode
)
2101 ath_dbg(common
, RESET
, "%s -> %s\n",
2102 modes
[ah
->power_mode
], modes
[mode
]);
2105 case ATH9K_PM_AWAKE
:
2106 status
= ath9k_hw_set_power_awake(ah
, setChip
);
2108 if (ah
->caps
.hw_caps
& ATH9K_HW_CAP_MCI
)
2109 REG_WRITE(ah
, AR_RTC_KEEP_AWAKE
, 0x2);
2112 case ATH9K_PM_FULL_SLEEP
:
2113 if (ah
->caps
.hw_caps
& ATH9K_HW_CAP_MCI
)
2114 ar9003_mci_set_full_sleep(ah
);
2116 ath9k_set_power_sleep(ah
, setChip
);
2117 ah
->chip_fullsleep
= true;
2119 case ATH9K_PM_NETWORK_SLEEP
:
2121 if (ah
->caps
.hw_caps
& ATH9K_HW_CAP_MCI
)
2122 REG_WRITE(ah
, AR_RTC_KEEP_AWAKE
, 0x2);
2124 ath9k_set_power_network_sleep(ah
, setChip
);
2127 ath_err(common
, "Unknown power mode %u\n", mode
);
2130 ah
->power_mode
= mode
;
2133 * XXX: If this warning never comes up after a while then
2134 * simply keep the ATH_DBG_WARN_ON_ONCE() but make
2135 * ath9k_hw_setpower() return type void.
2138 if (!(ah
->ah_flags
& AH_UNPLUGGED
))
2139 ATH_DBG_WARN_ON_ONCE(!status
);
2143 EXPORT_SYMBOL(ath9k_hw_setpower
);
2145 /*******************/
2146 /* Beacon Handling */
2147 /*******************/
2149 void ath9k_hw_beaconinit(struct ath_hw
*ah
, u32 next_beacon
, u32 beacon_period
)
2153 ENABLE_REGWRITE_BUFFER(ah
);
2155 switch (ah
->opmode
) {
2156 case NL80211_IFTYPE_ADHOC
:
2157 case NL80211_IFTYPE_MESH_POINT
:
2158 REG_SET_BIT(ah
, AR_TXCFG
,
2159 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY
);
2160 REG_WRITE(ah
, AR_NEXT_NDP_TIMER
, next_beacon
+
2161 TU_TO_USEC(ah
->atim_window
? ah
->atim_window
: 1));
2162 flags
|= AR_NDP_TIMER_EN
;
2163 case NL80211_IFTYPE_AP
:
2164 REG_WRITE(ah
, AR_NEXT_TBTT_TIMER
, next_beacon
);
2165 REG_WRITE(ah
, AR_NEXT_DMA_BEACON_ALERT
, next_beacon
-
2166 TU_TO_USEC(ah
->config
.dma_beacon_response_time
));
2167 REG_WRITE(ah
, AR_NEXT_SWBA
, next_beacon
-
2168 TU_TO_USEC(ah
->config
.sw_beacon_response_time
));
2170 AR_TBTT_TIMER_EN
| AR_DBA_TIMER_EN
| AR_SWBA_TIMER_EN
;
2173 ath_dbg(ath9k_hw_common(ah
), BEACON
,
2174 "%s: unsupported opmode: %d\n", __func__
, ah
->opmode
);
2179 REG_WRITE(ah
, AR_BEACON_PERIOD
, beacon_period
);
2180 REG_WRITE(ah
, AR_DMA_BEACON_PERIOD
, beacon_period
);
2181 REG_WRITE(ah
, AR_SWBA_PERIOD
, beacon_period
);
2182 REG_WRITE(ah
, AR_NDP_PERIOD
, beacon_period
);
2184 REGWRITE_BUFFER_FLUSH(ah
);
2186 REG_SET_BIT(ah
, AR_TIMER_MODE
, flags
);
2188 EXPORT_SYMBOL(ath9k_hw_beaconinit
);
2190 void ath9k_hw_set_sta_beacon_timers(struct ath_hw
*ah
,
2191 const struct ath9k_beacon_state
*bs
)
2193 u32 nextTbtt
, beaconintval
, dtimperiod
, beacontimeout
;
2194 struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
2195 struct ath_common
*common
= ath9k_hw_common(ah
);
2197 ENABLE_REGWRITE_BUFFER(ah
);
2199 REG_WRITE(ah
, AR_NEXT_TBTT_TIMER
, TU_TO_USEC(bs
->bs_nexttbtt
));
2201 REG_WRITE(ah
, AR_BEACON_PERIOD
,
2202 TU_TO_USEC(bs
->bs_intval
));
2203 REG_WRITE(ah
, AR_DMA_BEACON_PERIOD
,
2204 TU_TO_USEC(bs
->bs_intval
));
2206 REGWRITE_BUFFER_FLUSH(ah
);
2208 REG_RMW_FIELD(ah
, AR_RSSI_THR
,
2209 AR_RSSI_THR_BM_THR
, bs
->bs_bmissthreshold
);
2211 beaconintval
= bs
->bs_intval
;
2213 if (bs
->bs_sleepduration
> beaconintval
)
2214 beaconintval
= bs
->bs_sleepduration
;
2216 dtimperiod
= bs
->bs_dtimperiod
;
2217 if (bs
->bs_sleepduration
> dtimperiod
)
2218 dtimperiod
= bs
->bs_sleepduration
;
2220 if (beaconintval
== dtimperiod
)
2221 nextTbtt
= bs
->bs_nextdtim
;
2223 nextTbtt
= bs
->bs_nexttbtt
;
2225 ath_dbg(common
, BEACON
, "next DTIM %d\n", bs
->bs_nextdtim
);
2226 ath_dbg(common
, BEACON
, "next beacon %d\n", nextTbtt
);
2227 ath_dbg(common
, BEACON
, "beacon period %d\n", beaconintval
);
2228 ath_dbg(common
, BEACON
, "DTIM period %d\n", dtimperiod
);
2230 ENABLE_REGWRITE_BUFFER(ah
);
2232 REG_WRITE(ah
, AR_NEXT_DTIM
,
2233 TU_TO_USEC(bs
->bs_nextdtim
- SLEEP_SLOP
));
2234 REG_WRITE(ah
, AR_NEXT_TIM
, TU_TO_USEC(nextTbtt
- SLEEP_SLOP
));
2236 REG_WRITE(ah
, AR_SLEEP1
,
2237 SM((CAB_TIMEOUT_VAL
<< 3), AR_SLEEP1_CAB_TIMEOUT
)
2238 | AR_SLEEP1_ASSUME_DTIM
);
2240 if (pCap
->hw_caps
& ATH9K_HW_CAP_AUTOSLEEP
)
2241 beacontimeout
= (BEACON_TIMEOUT_VAL
<< 3);
2243 beacontimeout
= MIN_BEACON_TIMEOUT_VAL
;
2245 REG_WRITE(ah
, AR_SLEEP2
,
2246 SM(beacontimeout
, AR_SLEEP2_BEACON_TIMEOUT
));
2248 REG_WRITE(ah
, AR_TIM_PERIOD
, TU_TO_USEC(beaconintval
));
2249 REG_WRITE(ah
, AR_DTIM_PERIOD
, TU_TO_USEC(dtimperiod
));
2251 REGWRITE_BUFFER_FLUSH(ah
);
2253 REG_SET_BIT(ah
, AR_TIMER_MODE
,
2254 AR_TBTT_TIMER_EN
| AR_TIM_TIMER_EN
|
2257 /* TSF Out of Range Threshold */
2258 REG_WRITE(ah
, AR_TSFOOR_THRESHOLD
, bs
->bs_tsfoor_threshold
);
2260 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers
);
2262 /*******************/
2263 /* HW Capabilities */
2264 /*******************/
2266 static u8
fixup_chainmask(u8 chip_chainmask
, u8 eeprom_chainmask
)
2268 eeprom_chainmask
&= chip_chainmask
;
2269 if (eeprom_chainmask
)
2270 return eeprom_chainmask
;
2272 return chip_chainmask
;
2276 * ath9k_hw_dfs_tested - checks if DFS has been tested with used chipset
2277 * @ah: the atheros hardware data structure
2279 * We enable DFS support upstream on chipsets which have passed a series
2280 * of tests. The testing requirements are going to be documented. Desired
2281 * test requirements are documented at:
2283 * http://wireless.kernel.org/en/users/Drivers/ath9k/dfs
2285 * Once a new chipset gets properly tested an individual commit can be used
2286 * to document the testing for DFS for that chipset.
2288 static bool ath9k_hw_dfs_tested(struct ath_hw
*ah
)
2291 switch (ah
->hw_version
.macVersion
) {
2292 /* AR9580 will likely be our first target to get testing on */
2293 case AR_SREV_VERSION_9580
:
2299 int ath9k_hw_fill_cap_info(struct ath_hw
*ah
)
2301 struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
2302 struct ath_regulatory
*regulatory
= ath9k_hw_regulatory(ah
);
2303 struct ath_common
*common
= ath9k_hw_common(ah
);
2304 unsigned int chip_chainmask
;
2307 u8 ant_div_ctl1
, tx_chainmask
, rx_chainmask
;
2309 eeval
= ah
->eep_ops
->get_eeprom(ah
, EEP_REG_0
);
2310 regulatory
->current_rd
= eeval
;
2312 if (ah
->opmode
!= NL80211_IFTYPE_AP
&&
2313 ah
->hw_version
.subvendorid
== AR_SUBVENDOR_ID_NEW_A
) {
2314 if (regulatory
->current_rd
== 0x64 ||
2315 regulatory
->current_rd
== 0x65)
2316 regulatory
->current_rd
+= 5;
2317 else if (regulatory
->current_rd
== 0x41)
2318 regulatory
->current_rd
= 0x43;
2319 ath_dbg(common
, REGULATORY
, "regdomain mapped to 0x%x\n",
2320 regulatory
->current_rd
);
2323 eeval
= ah
->eep_ops
->get_eeprom(ah
, EEP_OP_MODE
);
2324 if ((eeval
& (AR5416_OPFLAGS_11G
| AR5416_OPFLAGS_11A
)) == 0) {
2326 "no band has been marked as supported in EEPROM\n");
2330 if (eeval
& AR5416_OPFLAGS_11A
)
2331 pCap
->hw_caps
|= ATH9K_HW_CAP_5GHZ
;
2333 if (eeval
& AR5416_OPFLAGS_11G
)
2334 pCap
->hw_caps
|= ATH9K_HW_CAP_2GHZ
;
2336 if (AR_SREV_9485(ah
) || AR_SREV_9285(ah
) || AR_SREV_9330(ah
))
2338 else if (AR_SREV_9462(ah
))
2340 else if (!AR_SREV_9280_20_OR_LATER(ah
))
2342 else if (!AR_SREV_9300_20_OR_LATER(ah
) || AR_SREV_9340(ah
))
2347 pCap
->tx_chainmask
= ah
->eep_ops
->get_eeprom(ah
, EEP_TX_MASK
);
2349 * For AR9271 we will temporarilly uses the rx chainmax as read from
2352 if ((ah
->hw_version
.devid
== AR5416_DEVID_PCI
) &&
2353 !(eeval
& AR5416_OPFLAGS_11A
) &&
2354 !(AR_SREV_9271(ah
)))
2355 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
2356 pCap
->rx_chainmask
= ath9k_hw_gpio_get(ah
, 0) ? 0x5 : 0x7;
2357 else if (AR_SREV_9100(ah
))
2358 pCap
->rx_chainmask
= 0x7;
2360 /* Use rx_chainmask from EEPROM. */
2361 pCap
->rx_chainmask
= ah
->eep_ops
->get_eeprom(ah
, EEP_RX_MASK
);
2363 pCap
->tx_chainmask
= fixup_chainmask(chip_chainmask
, pCap
->tx_chainmask
);
2364 pCap
->rx_chainmask
= fixup_chainmask(chip_chainmask
, pCap
->rx_chainmask
);
2365 ah
->txchainmask
= pCap
->tx_chainmask
;
2366 ah
->rxchainmask
= pCap
->rx_chainmask
;
2368 ah
->misc_mode
|= AR_PCU_MIC_NEW_LOC_ENA
;
2370 /* enable key search for every frame in an aggregate */
2371 if (AR_SREV_9300_20_OR_LATER(ah
))
2372 ah
->misc_mode
|= AR_PCU_ALWAYS_PERFORM_KEYSEARCH
;
2374 common
->crypt_caps
|= ATH_CRYPT_CAP_CIPHER_AESCCM
;
2376 if (ah
->hw_version
.devid
!= AR2427_DEVID_PCIE
)
2377 pCap
->hw_caps
|= ATH9K_HW_CAP_HT
;
2379 pCap
->hw_caps
&= ~ATH9K_HW_CAP_HT
;
2381 if (AR_SREV_9271(ah
))
2382 pCap
->num_gpio_pins
= AR9271_NUM_GPIO
;
2383 else if (AR_DEVID_7010(ah
))
2384 pCap
->num_gpio_pins
= AR7010_NUM_GPIO
;
2385 else if (AR_SREV_9300_20_OR_LATER(ah
))
2386 pCap
->num_gpio_pins
= AR9300_NUM_GPIO
;
2387 else if (AR_SREV_9287_11_OR_LATER(ah
))
2388 pCap
->num_gpio_pins
= AR9287_NUM_GPIO
;
2389 else if (AR_SREV_9285_12_OR_LATER(ah
))
2390 pCap
->num_gpio_pins
= AR9285_NUM_GPIO
;
2391 else if (AR_SREV_9280_20_OR_LATER(ah
))
2392 pCap
->num_gpio_pins
= AR928X_NUM_GPIO
;
2394 pCap
->num_gpio_pins
= AR_NUM_GPIO
;
2396 if (AR_SREV_9160_10_OR_LATER(ah
) || AR_SREV_9100(ah
))
2397 pCap
->rts_aggr_limit
= ATH_AMPDU_LIMIT_MAX
;
2399 pCap
->rts_aggr_limit
= (8 * 1024);
2401 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2402 ah
->rfsilent
= ah
->eep_ops
->get_eeprom(ah
, EEP_RF_SILENT
);
2403 if (ah
->rfsilent
& EEP_RFSILENT_ENABLED
) {
2405 MS(ah
->rfsilent
, EEP_RFSILENT_GPIO_SEL
);
2406 ah
->rfkill_polarity
=
2407 MS(ah
->rfsilent
, EEP_RFSILENT_POLARITY
);
2409 pCap
->hw_caps
|= ATH9K_HW_CAP_RFSILENT
;
2412 if (AR_SREV_9271(ah
) || AR_SREV_9300_20_OR_LATER(ah
))
2413 pCap
->hw_caps
|= ATH9K_HW_CAP_AUTOSLEEP
;
2415 pCap
->hw_caps
&= ~ATH9K_HW_CAP_AUTOSLEEP
;
2417 if (AR_SREV_9280(ah
) || AR_SREV_9285(ah
))
2418 pCap
->hw_caps
&= ~ATH9K_HW_CAP_4KB_SPLITTRANS
;
2420 pCap
->hw_caps
|= ATH9K_HW_CAP_4KB_SPLITTRANS
;
2422 if (AR_SREV_9300_20_OR_LATER(ah
)) {
2423 pCap
->hw_caps
|= ATH9K_HW_CAP_EDMA
| ATH9K_HW_CAP_FASTCLOCK
;
2424 if (!AR_SREV_9330(ah
) && !AR_SREV_9485(ah
))
2425 pCap
->hw_caps
|= ATH9K_HW_CAP_LDPC
;
2427 pCap
->rx_hp_qdepth
= ATH9K_HW_RX_HP_QDEPTH
;
2428 pCap
->rx_lp_qdepth
= ATH9K_HW_RX_LP_QDEPTH
;
2429 pCap
->rx_status_len
= sizeof(struct ar9003_rxs
);
2430 pCap
->tx_desc_len
= sizeof(struct ar9003_txc
);
2431 pCap
->txs_len
= sizeof(struct ar9003_txs
);
2432 if (!ah
->config
.paprd_disable
&&
2433 ah
->eep_ops
->get_eeprom(ah
, EEP_PAPRD
))
2434 pCap
->hw_caps
|= ATH9K_HW_CAP_PAPRD
;
2436 pCap
->tx_desc_len
= sizeof(struct ath_desc
);
2437 if (AR_SREV_9280_20(ah
))
2438 pCap
->hw_caps
|= ATH9K_HW_CAP_FASTCLOCK
;
2441 if (AR_SREV_9300_20_OR_LATER(ah
))
2442 pCap
->hw_caps
|= ATH9K_HW_CAP_RAC_SUPPORTED
;
2444 if (AR_SREV_9300_20_OR_LATER(ah
))
2445 ah
->ent_mode
= REG_READ(ah
, AR_ENT_OTP
);
2447 if (AR_SREV_9287_11_OR_LATER(ah
) || AR_SREV_9271(ah
))
2448 pCap
->hw_caps
|= ATH9K_HW_CAP_SGI_20
;
2450 if (AR_SREV_9285(ah
))
2451 if (ah
->eep_ops
->get_eeprom(ah
, EEP_MODAL_VER
) >= 3) {
2453 ah
->eep_ops
->get_eeprom(ah
, EEP_ANT_DIV_CTL1
);
2454 if ((ant_div_ctl1
& 0x1) && ((ant_div_ctl1
>> 3) & 0x1))
2455 pCap
->hw_caps
|= ATH9K_HW_CAP_ANT_DIV_COMB
;
2457 if (AR_SREV_9300_20_OR_LATER(ah
)) {
2458 if (ah
->eep_ops
->get_eeprom(ah
, EEP_CHAIN_MASK_REDUCE
))
2459 pCap
->hw_caps
|= ATH9K_HW_CAP_APM
;
2463 if (AR_SREV_9330(ah
) || AR_SREV_9485(ah
)) {
2464 ant_div_ctl1
= ah
->eep_ops
->get_eeprom(ah
, EEP_ANT_DIV_CTL1
);
2466 * enable the diversity-combining algorithm only when
2467 * both enable_lna_div and enable_fast_div are set
2468 * Table for Diversity
2469 * ant_div_alt_lnaconf bit 0-1
2470 * ant_div_main_lnaconf bit 2-3
2471 * ant_div_alt_gaintb bit 4
2472 * ant_div_main_gaintb bit 5
2473 * enable_ant_div_lnadiv bit 6
2474 * enable_ant_fast_div bit 7
2476 if ((ant_div_ctl1
>> 0x6) == 0x3)
2477 pCap
->hw_caps
|= ATH9K_HW_CAP_ANT_DIV_COMB
;
2480 if (AR_SREV_9485_10(ah
)) {
2481 pCap
->pcie_lcr_extsync_en
= true;
2482 pCap
->pcie_lcr_offset
= 0x80;
2485 if (ath9k_hw_dfs_tested(ah
))
2486 pCap
->hw_caps
|= ATH9K_HW_CAP_DFS
;
2488 tx_chainmask
= pCap
->tx_chainmask
;
2489 rx_chainmask
= pCap
->rx_chainmask
;
2490 while (tx_chainmask
|| rx_chainmask
) {
2491 if (tx_chainmask
& BIT(0))
2492 pCap
->max_txchains
++;
2493 if (rx_chainmask
& BIT(0))
2494 pCap
->max_rxchains
++;
2500 if (AR_SREV_9300_20_OR_LATER(ah
)) {
2501 ah
->enabled_cals
|= TX_IQ_CAL
;
2502 if (AR_SREV_9485_OR_LATER(ah
))
2503 ah
->enabled_cals
|= TX_IQ_ON_AGC_CAL
;
2506 if (AR_SREV_9462(ah
)) {
2508 if (!(ah
->ent_mode
& AR_ENT_OTP_49GHZ_DISABLE
))
2509 pCap
->hw_caps
|= ATH9K_HW_CAP_MCI
;
2511 if (AR_SREV_9462_20(ah
))
2512 pCap
->hw_caps
|= ATH9K_HW_CAP_RTT
;
2520 /****************************/
2521 /* GPIO / RFKILL / Antennae */
2522 /****************************/
2524 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw
*ah
,
2528 u32 gpio_shift
, tmp
;
2531 addr
= AR_GPIO_OUTPUT_MUX3
;
2533 addr
= AR_GPIO_OUTPUT_MUX2
;
2535 addr
= AR_GPIO_OUTPUT_MUX1
;
2537 gpio_shift
= (gpio
% 6) * 5;
2539 if (AR_SREV_9280_20_OR_LATER(ah
)
2540 || (addr
!= AR_GPIO_OUTPUT_MUX1
)) {
2541 REG_RMW(ah
, addr
, (type
<< gpio_shift
),
2542 (0x1f << gpio_shift
));
2544 tmp
= REG_READ(ah
, addr
);
2545 tmp
= ((tmp
& 0x1F0) << 1) | (tmp
& ~0x1F0);
2546 tmp
&= ~(0x1f << gpio_shift
);
2547 tmp
|= (type
<< gpio_shift
);
2548 REG_WRITE(ah
, addr
, tmp
);
2552 void ath9k_hw_cfg_gpio_input(struct ath_hw
*ah
, u32 gpio
)
2556 BUG_ON(gpio
>= ah
->caps
.num_gpio_pins
);
2558 if (AR_DEVID_7010(ah
)) {
2560 REG_RMW(ah
, AR7010_GPIO_OE
,
2561 (AR7010_GPIO_OE_AS_INPUT
<< gpio_shift
),
2562 (AR7010_GPIO_OE_MASK
<< gpio_shift
));
2566 gpio_shift
= gpio
<< 1;
2569 (AR_GPIO_OE_OUT_DRV_NO
<< gpio_shift
),
2570 (AR_GPIO_OE_OUT_DRV
<< gpio_shift
));
2572 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input
);
2574 u32
ath9k_hw_gpio_get(struct ath_hw
*ah
, u32 gpio
)
2576 #define MS_REG_READ(x, y) \
2577 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2579 if (gpio
>= ah
->caps
.num_gpio_pins
)
2582 if (AR_DEVID_7010(ah
)) {
2584 val
= REG_READ(ah
, AR7010_GPIO_IN
);
2585 return (MS(val
, AR7010_GPIO_IN_VAL
) & AR_GPIO_BIT(gpio
)) == 0;
2586 } else if (AR_SREV_9300_20_OR_LATER(ah
))
2587 return (MS(REG_READ(ah
, AR_GPIO_IN
), AR9300_GPIO_IN_VAL
) &
2588 AR_GPIO_BIT(gpio
)) != 0;
2589 else if (AR_SREV_9271(ah
))
2590 return MS_REG_READ(AR9271
, gpio
) != 0;
2591 else if (AR_SREV_9287_11_OR_LATER(ah
))
2592 return MS_REG_READ(AR9287
, gpio
) != 0;
2593 else if (AR_SREV_9285_12_OR_LATER(ah
))
2594 return MS_REG_READ(AR9285
, gpio
) != 0;
2595 else if (AR_SREV_9280_20_OR_LATER(ah
))
2596 return MS_REG_READ(AR928X
, gpio
) != 0;
2598 return MS_REG_READ(AR
, gpio
) != 0;
2600 EXPORT_SYMBOL(ath9k_hw_gpio_get
);
2602 void ath9k_hw_cfg_output(struct ath_hw
*ah
, u32 gpio
,
2607 if (AR_DEVID_7010(ah
)) {
2609 REG_RMW(ah
, AR7010_GPIO_OE
,
2610 (AR7010_GPIO_OE_AS_OUTPUT
<< gpio_shift
),
2611 (AR7010_GPIO_OE_MASK
<< gpio_shift
));
2615 ath9k_hw_gpio_cfg_output_mux(ah
, gpio
, ah_signal_type
);
2616 gpio_shift
= 2 * gpio
;
2619 (AR_GPIO_OE_OUT_DRV_ALL
<< gpio_shift
),
2620 (AR_GPIO_OE_OUT_DRV
<< gpio_shift
));
2622 EXPORT_SYMBOL(ath9k_hw_cfg_output
);
2624 void ath9k_hw_set_gpio(struct ath_hw
*ah
, u32 gpio
, u32 val
)
2626 if (AR_DEVID_7010(ah
)) {
2628 REG_RMW(ah
, AR7010_GPIO_OUT
, ((val
&1) << gpio
),
2633 if (AR_SREV_9271(ah
))
2636 REG_RMW(ah
, AR_GPIO_IN_OUT
, ((val
& 1) << gpio
),
2639 EXPORT_SYMBOL(ath9k_hw_set_gpio
);
2641 void ath9k_hw_setantenna(struct ath_hw
*ah
, u32 antenna
)
2643 REG_WRITE(ah
, AR_DEF_ANTENNA
, (antenna
& 0x7));
2645 EXPORT_SYMBOL(ath9k_hw_setantenna
);
2647 /*********************/
2648 /* General Operation */
2649 /*********************/
2651 u32
ath9k_hw_getrxfilter(struct ath_hw
*ah
)
2653 u32 bits
= REG_READ(ah
, AR_RX_FILTER
);
2654 u32 phybits
= REG_READ(ah
, AR_PHY_ERR
);
2656 if (phybits
& AR_PHY_ERR_RADAR
)
2657 bits
|= ATH9K_RX_FILTER_PHYRADAR
;
2658 if (phybits
& (AR_PHY_ERR_OFDM_TIMING
| AR_PHY_ERR_CCK_TIMING
))
2659 bits
|= ATH9K_RX_FILTER_PHYERR
;
2663 EXPORT_SYMBOL(ath9k_hw_getrxfilter
);
2665 void ath9k_hw_setrxfilter(struct ath_hw
*ah
, u32 bits
)
2669 ENABLE_REGWRITE_BUFFER(ah
);
2671 if (AR_SREV_9462(ah
))
2672 bits
|= ATH9K_RX_FILTER_CONTROL_WRAPPER
;
2674 REG_WRITE(ah
, AR_RX_FILTER
, bits
);
2677 if (bits
& ATH9K_RX_FILTER_PHYRADAR
)
2678 phybits
|= AR_PHY_ERR_RADAR
;
2679 if (bits
& ATH9K_RX_FILTER_PHYERR
)
2680 phybits
|= AR_PHY_ERR_OFDM_TIMING
| AR_PHY_ERR_CCK_TIMING
;
2681 REG_WRITE(ah
, AR_PHY_ERR
, phybits
);
2684 REG_SET_BIT(ah
, AR_RXCFG
, AR_RXCFG_ZLFDMA
);
2686 REG_CLR_BIT(ah
, AR_RXCFG
, AR_RXCFG_ZLFDMA
);
2688 REGWRITE_BUFFER_FLUSH(ah
);
2690 EXPORT_SYMBOL(ath9k_hw_setrxfilter
);
2692 bool ath9k_hw_phy_disable(struct ath_hw
*ah
)
2694 if (!ath9k_hw_set_reset_reg(ah
, ATH9K_RESET_WARM
))
2697 ath9k_hw_init_pll(ah
, NULL
);
2698 ah
->htc_reset_init
= true;
2701 EXPORT_SYMBOL(ath9k_hw_phy_disable
);
2703 bool ath9k_hw_disable(struct ath_hw
*ah
)
2705 if (!ath9k_hw_setpower(ah
, ATH9K_PM_AWAKE
))
2708 if (!ath9k_hw_set_reset_reg(ah
, ATH9K_RESET_COLD
))
2711 ath9k_hw_init_pll(ah
, NULL
);
2714 EXPORT_SYMBOL(ath9k_hw_disable
);
2716 static int get_antenna_gain(struct ath_hw
*ah
, struct ath9k_channel
*chan
)
2718 enum eeprom_param gain_param
;
2720 if (IS_CHAN_2GHZ(chan
))
2721 gain_param
= EEP_ANTENNA_GAIN_2G
;
2723 gain_param
= EEP_ANTENNA_GAIN_5G
;
2725 return ah
->eep_ops
->get_eeprom(ah
, gain_param
);
2728 void ath9k_hw_apply_txpower(struct ath_hw
*ah
, struct ath9k_channel
*chan
)
2730 struct ath_regulatory
*reg
= ath9k_hw_regulatory(ah
);
2731 struct ieee80211_channel
*channel
;
2732 int chan_pwr
, new_pwr
, max_gain
;
2733 int ant_gain
, ant_reduction
= 0;
2738 channel
= chan
->chan
;
2739 chan_pwr
= min_t(int, channel
->max_power
* 2, MAX_RATE_POWER
);
2740 new_pwr
= min_t(int, chan_pwr
, reg
->power_limit
);
2741 max_gain
= chan_pwr
- new_pwr
+ channel
->max_antenna_gain
* 2;
2743 ant_gain
= get_antenna_gain(ah
, chan
);
2744 if (ant_gain
> max_gain
)
2745 ant_reduction
= ant_gain
- max_gain
;
2747 ah
->eep_ops
->set_txpower(ah
, chan
,
2748 ath9k_regd_get_ctl(reg
, chan
),
2749 ant_reduction
, new_pwr
, false);
2752 void ath9k_hw_set_txpowerlimit(struct ath_hw
*ah
, u32 limit
, bool test
)
2754 struct ath_regulatory
*reg
= ath9k_hw_regulatory(ah
);
2755 struct ath9k_channel
*chan
= ah
->curchan
;
2756 struct ieee80211_channel
*channel
= chan
->chan
;
2758 reg
->power_limit
= min_t(u32
, limit
, MAX_RATE_POWER
);
2760 channel
->max_power
= MAX_RATE_POWER
/ 2;
2762 ath9k_hw_apply_txpower(ah
, chan
);
2765 channel
->max_power
= DIV_ROUND_UP(reg
->max_power_level
, 2);
2767 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit
);
2769 void ath9k_hw_setopmode(struct ath_hw
*ah
)
2771 ath9k_hw_set_operating_mode(ah
, ah
->opmode
);
2773 EXPORT_SYMBOL(ath9k_hw_setopmode
);
2775 void ath9k_hw_setmcastfilter(struct ath_hw
*ah
, u32 filter0
, u32 filter1
)
2777 REG_WRITE(ah
, AR_MCAST_FIL0
, filter0
);
2778 REG_WRITE(ah
, AR_MCAST_FIL1
, filter1
);
2780 EXPORT_SYMBOL(ath9k_hw_setmcastfilter
);
2782 void ath9k_hw_write_associd(struct ath_hw
*ah
)
2784 struct ath_common
*common
= ath9k_hw_common(ah
);
2786 REG_WRITE(ah
, AR_BSS_ID0
, get_unaligned_le32(common
->curbssid
));
2787 REG_WRITE(ah
, AR_BSS_ID1
, get_unaligned_le16(common
->curbssid
+ 4) |
2788 ((common
->curaid
& 0x3fff) << AR_BSS_ID1_AID_S
));
2790 EXPORT_SYMBOL(ath9k_hw_write_associd
);
2792 #define ATH9K_MAX_TSF_READ 10
2794 u64
ath9k_hw_gettsf64(struct ath_hw
*ah
)
2796 u32 tsf_lower
, tsf_upper1
, tsf_upper2
;
2799 tsf_upper1
= REG_READ(ah
, AR_TSF_U32
);
2800 for (i
= 0; i
< ATH9K_MAX_TSF_READ
; i
++) {
2801 tsf_lower
= REG_READ(ah
, AR_TSF_L32
);
2802 tsf_upper2
= REG_READ(ah
, AR_TSF_U32
);
2803 if (tsf_upper2
== tsf_upper1
)
2805 tsf_upper1
= tsf_upper2
;
2808 WARN_ON( i
== ATH9K_MAX_TSF_READ
);
2810 return (((u64
)tsf_upper1
<< 32) | tsf_lower
);
2812 EXPORT_SYMBOL(ath9k_hw_gettsf64
);
2814 void ath9k_hw_settsf64(struct ath_hw
*ah
, u64 tsf64
)
2816 REG_WRITE(ah
, AR_TSF_L32
, tsf64
& 0xffffffff);
2817 REG_WRITE(ah
, AR_TSF_U32
, (tsf64
>> 32) & 0xffffffff);
2819 EXPORT_SYMBOL(ath9k_hw_settsf64
);
2821 void ath9k_hw_reset_tsf(struct ath_hw
*ah
)
2823 if (!ath9k_hw_wait(ah
, AR_SLP32_MODE
, AR_SLP32_TSF_WRITE_STATUS
, 0,
2824 AH_TSF_WRITE_TIMEOUT
))
2825 ath_dbg(ath9k_hw_common(ah
), RESET
,
2826 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
2828 REG_WRITE(ah
, AR_RESET_TSF
, AR_RESET_TSF_ONCE
);
2830 EXPORT_SYMBOL(ath9k_hw_reset_tsf
);
2832 void ath9k_hw_set_tsfadjust(struct ath_hw
*ah
, u32 setting
)
2835 ah
->misc_mode
|= AR_PCU_TX_ADD_TSF
;
2837 ah
->misc_mode
&= ~AR_PCU_TX_ADD_TSF
;
2839 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust
);
2841 void ath9k_hw_set11nmac2040(struct ath_hw
*ah
)
2843 struct ieee80211_conf
*conf
= &ath9k_hw_common(ah
)->hw
->conf
;
2846 if (conf_is_ht40(conf
) && !ah
->config
.cwm_ignore_extcca
)
2847 macmode
= AR_2040_JOINED_RX_CLEAR
;
2851 REG_WRITE(ah
, AR_2040_MODE
, macmode
);
2854 /* HW Generic timers configuration */
2856 static const struct ath_gen_timer_configuration gen_tmr_configuration
[] =
2858 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
2859 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
2860 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
2861 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
2862 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
2863 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
2864 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
2865 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
2866 {AR_NEXT_NDP2_TIMER
, AR_NDP2_PERIOD
, AR_NDP2_TIMER_MODE
, 0x0001},
2867 {AR_NEXT_NDP2_TIMER
+ 1*4, AR_NDP2_PERIOD
+ 1*4,
2868 AR_NDP2_TIMER_MODE
, 0x0002},
2869 {AR_NEXT_NDP2_TIMER
+ 2*4, AR_NDP2_PERIOD
+ 2*4,
2870 AR_NDP2_TIMER_MODE
, 0x0004},
2871 {AR_NEXT_NDP2_TIMER
+ 3*4, AR_NDP2_PERIOD
+ 3*4,
2872 AR_NDP2_TIMER_MODE
, 0x0008},
2873 {AR_NEXT_NDP2_TIMER
+ 4*4, AR_NDP2_PERIOD
+ 4*4,
2874 AR_NDP2_TIMER_MODE
, 0x0010},
2875 {AR_NEXT_NDP2_TIMER
+ 5*4, AR_NDP2_PERIOD
+ 5*4,
2876 AR_NDP2_TIMER_MODE
, 0x0020},
2877 {AR_NEXT_NDP2_TIMER
+ 6*4, AR_NDP2_PERIOD
+ 6*4,
2878 AR_NDP2_TIMER_MODE
, 0x0040},
2879 {AR_NEXT_NDP2_TIMER
+ 7*4, AR_NDP2_PERIOD
+ 7*4,
2880 AR_NDP2_TIMER_MODE
, 0x0080}
2883 /* HW generic timer primitives */
2885 /* compute and clear index of rightmost 1 */
2886 static u32
rightmost_index(struct ath_gen_timer_table
*timer_table
, u32
*mask
)
2896 return timer_table
->gen_timer_index
[b
];
2899 u32
ath9k_hw_gettsf32(struct ath_hw
*ah
)
2901 return REG_READ(ah
, AR_TSF_L32
);
2903 EXPORT_SYMBOL(ath9k_hw_gettsf32
);
2905 struct ath_gen_timer
*ath_gen_timer_alloc(struct ath_hw
*ah
,
2906 void (*trigger
)(void *),
2907 void (*overflow
)(void *),
2911 struct ath_gen_timer_table
*timer_table
= &ah
->hw_gen_timers
;
2912 struct ath_gen_timer
*timer
;
2914 timer
= kzalloc(sizeof(struct ath_gen_timer
), GFP_KERNEL
);
2916 if (timer
== NULL
) {
2917 ath_err(ath9k_hw_common(ah
),
2918 "Failed to allocate memory for hw timer[%d]\n",
2923 /* allocate a hardware generic timer slot */
2924 timer_table
->timers
[timer_index
] = timer
;
2925 timer
->index
= timer_index
;
2926 timer
->trigger
= trigger
;
2927 timer
->overflow
= overflow
;
2932 EXPORT_SYMBOL(ath_gen_timer_alloc
);
2934 void ath9k_hw_gen_timer_start(struct ath_hw
*ah
,
2935 struct ath_gen_timer
*timer
,
2939 struct ath_gen_timer_table
*timer_table
= &ah
->hw_gen_timers
;
2940 u32 tsf
, timer_next
;
2942 BUG_ON(!timer_period
);
2944 set_bit(timer
->index
, &timer_table
->timer_mask
.timer_bits
);
2946 tsf
= ath9k_hw_gettsf32(ah
);
2948 timer_next
= tsf
+ trig_timeout
;
2950 ath_dbg(ath9k_hw_common(ah
), HWTIMER
,
2951 "current tsf %x period %x timer_next %x\n",
2952 tsf
, timer_period
, timer_next
);
2955 * Program generic timer registers
2957 REG_WRITE(ah
, gen_tmr_configuration
[timer
->index
].next_addr
,
2959 REG_WRITE(ah
, gen_tmr_configuration
[timer
->index
].period_addr
,
2961 REG_SET_BIT(ah
, gen_tmr_configuration
[timer
->index
].mode_addr
,
2962 gen_tmr_configuration
[timer
->index
].mode_mask
);
2964 if (AR_SREV_9462(ah
)) {
2966 * Starting from AR9462, each generic timer can select which tsf
2967 * to use. But we still follow the old rule, 0 - 7 use tsf and
2970 if ((timer
->index
< AR_GEN_TIMER_BANK_1_LEN
))
2971 REG_CLR_BIT(ah
, AR_MAC_PCU_GEN_TIMER_TSF_SEL
,
2972 (1 << timer
->index
));
2974 REG_SET_BIT(ah
, AR_MAC_PCU_GEN_TIMER_TSF_SEL
,
2975 (1 << timer
->index
));
2978 /* Enable both trigger and thresh interrupt masks */
2979 REG_SET_BIT(ah
, AR_IMR_S5
,
2980 (SM(AR_GENTMR_BIT(timer
->index
), AR_IMR_S5_GENTIMER_THRESH
) |
2981 SM(AR_GENTMR_BIT(timer
->index
), AR_IMR_S5_GENTIMER_TRIG
)));
2983 EXPORT_SYMBOL(ath9k_hw_gen_timer_start
);
2985 void ath9k_hw_gen_timer_stop(struct ath_hw
*ah
, struct ath_gen_timer
*timer
)
2987 struct ath_gen_timer_table
*timer_table
= &ah
->hw_gen_timers
;
2989 if ((timer
->index
< AR_FIRST_NDP_TIMER
) ||
2990 (timer
->index
>= ATH_MAX_GEN_TIMER
)) {
2994 /* Clear generic timer enable bits. */
2995 REG_CLR_BIT(ah
, gen_tmr_configuration
[timer
->index
].mode_addr
,
2996 gen_tmr_configuration
[timer
->index
].mode_mask
);
2998 /* Disable both trigger and thresh interrupt masks */
2999 REG_CLR_BIT(ah
, AR_IMR_S5
,
3000 (SM(AR_GENTMR_BIT(timer
->index
), AR_IMR_S5_GENTIMER_THRESH
) |
3001 SM(AR_GENTMR_BIT(timer
->index
), AR_IMR_S5_GENTIMER_TRIG
)));
3003 clear_bit(timer
->index
, &timer_table
->timer_mask
.timer_bits
);
3005 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop
);
3007 void ath_gen_timer_free(struct ath_hw
*ah
, struct ath_gen_timer
*timer
)
3009 struct ath_gen_timer_table
*timer_table
= &ah
->hw_gen_timers
;
3011 /* free the hardware generic timer slot */
3012 timer_table
->timers
[timer
->index
] = NULL
;
3015 EXPORT_SYMBOL(ath_gen_timer_free
);
3018 * Generic Timer Interrupts handling
3020 void ath_gen_timer_isr(struct ath_hw
*ah
)
3022 struct ath_gen_timer_table
*timer_table
= &ah
->hw_gen_timers
;
3023 struct ath_gen_timer
*timer
;
3024 struct ath_common
*common
= ath9k_hw_common(ah
);
3025 u32 trigger_mask
, thresh_mask
, index
;
3027 /* get hardware generic timer interrupt status */
3028 trigger_mask
= ah
->intr_gen_timer_trigger
;
3029 thresh_mask
= ah
->intr_gen_timer_thresh
;
3030 trigger_mask
&= timer_table
->timer_mask
.val
;
3031 thresh_mask
&= timer_table
->timer_mask
.val
;
3033 trigger_mask
&= ~thresh_mask
;
3035 while (thresh_mask
) {
3036 index
= rightmost_index(timer_table
, &thresh_mask
);
3037 timer
= timer_table
->timers
[index
];
3039 ath_dbg(common
, HWTIMER
, "TSF overflow for Gen timer %d\n",
3041 timer
->overflow(timer
->arg
);
3044 while (trigger_mask
) {
3045 index
= rightmost_index(timer_table
, &trigger_mask
);
3046 timer
= timer_table
->timers
[index
];
3048 ath_dbg(common
, HWTIMER
,
3049 "Gen timer[%d] trigger\n", index
);
3050 timer
->trigger(timer
->arg
);
3053 EXPORT_SYMBOL(ath_gen_timer_isr
);
3062 } ath_mac_bb_names
[] = {
3063 /* Devices with external radios */
3064 { AR_SREV_VERSION_5416_PCI
, "5416" },
3065 { AR_SREV_VERSION_5416_PCIE
, "5418" },
3066 { AR_SREV_VERSION_9100
, "9100" },
3067 { AR_SREV_VERSION_9160
, "9160" },
3068 /* Single-chip solutions */
3069 { AR_SREV_VERSION_9280
, "9280" },
3070 { AR_SREV_VERSION_9285
, "9285" },
3071 { AR_SREV_VERSION_9287
, "9287" },
3072 { AR_SREV_VERSION_9271
, "9271" },
3073 { AR_SREV_VERSION_9300
, "9300" },
3074 { AR_SREV_VERSION_9330
, "9330" },
3075 { AR_SREV_VERSION_9340
, "9340" },
3076 { AR_SREV_VERSION_9485
, "9485" },
3077 { AR_SREV_VERSION_9462
, "9462" },
3080 /* For devices with external radios */
3084 } ath_rf_names
[] = {
3086 { AR_RAD5133_SREV_MAJOR
, "5133" },
3087 { AR_RAD5122_SREV_MAJOR
, "5122" },
3088 { AR_RAD2133_SREV_MAJOR
, "2133" },
3089 { AR_RAD2122_SREV_MAJOR
, "2122" }
3093 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3095 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version
)
3099 for (i
=0; i
<ARRAY_SIZE(ath_mac_bb_names
); i
++) {
3100 if (ath_mac_bb_names
[i
].version
== mac_bb_version
) {
3101 return ath_mac_bb_names
[i
].name
;
3109 * Return the RF name. "????" is returned if the RF is unknown.
3110 * Used for devices with external radios.
3112 static const char *ath9k_hw_rf_name(u16 rf_version
)
3116 for (i
=0; i
<ARRAY_SIZE(ath_rf_names
); i
++) {
3117 if (ath_rf_names
[i
].version
== rf_version
) {
3118 return ath_rf_names
[i
].name
;
3125 void ath9k_hw_name(struct ath_hw
*ah
, char *hw_name
, size_t len
)
3129 /* chipsets >= AR9280 are single-chip */
3130 if (AR_SREV_9280_20_OR_LATER(ah
)) {
3131 used
= snprintf(hw_name
, len
,
3132 "Atheros AR%s Rev:%x",
3133 ath9k_hw_mac_bb_name(ah
->hw_version
.macVersion
),
3134 ah
->hw_version
.macRev
);
3137 used
= snprintf(hw_name
, len
,
3138 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3139 ath9k_hw_mac_bb_name(ah
->hw_version
.macVersion
),
3140 ah
->hw_version
.macRev
,
3141 ath9k_hw_rf_name((ah
->hw_version
.analog5GhzRev
&
3142 AR_RADIO_SREV_MAJOR
)),
3143 ah
->hw_version
.phyRev
);
3146 hw_name
[used
] = '\0';
3148 EXPORT_SYMBOL(ath9k_hw_name
);