2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include <asm/unaligned.h>
24 #define ATH9K_CLOCK_RATE_CCK 22
25 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
26 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
28 static bool ath9k_hw_set_reset_reg(struct ath_hw
*ah
, u32 type
);
29 static void ath9k_hw_set_regs(struct ath_hw
*ah
, struct ath9k_channel
*chan
);
30 static u32
ath9k_hw_ini_fixup(struct ath_hw
*ah
,
31 struct ar5416_eeprom_def
*pEepData
,
34 MODULE_AUTHOR("Atheros Communications");
35 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
36 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
37 MODULE_LICENSE("Dual BSD/GPL");
39 static int __init
ath9k_init(void)
43 module_init(ath9k_init
);
45 static void __exit
ath9k_exit(void)
49 module_exit(ath9k_exit
);
51 /********************/
52 /* Helper Functions */
53 /********************/
55 static u32
ath9k_hw_mac_usec(struct ath_hw
*ah
, u32 clks
)
57 struct ieee80211_conf
*conf
= &ath9k_hw_common(ah
)->hw
->conf
;
59 if (!ah
->curchan
) /* should really check for CCK instead */
60 return clks
/ ATH9K_CLOCK_RATE_CCK
;
61 if (conf
->channel
->band
== IEEE80211_BAND_2GHZ
)
62 return clks
/ ATH9K_CLOCK_RATE_2GHZ_OFDM
;
64 return clks
/ ATH9K_CLOCK_RATE_5GHZ_OFDM
;
67 static u32
ath9k_hw_mac_to_usec(struct ath_hw
*ah
, u32 clks
)
69 struct ieee80211_conf
*conf
= &ath9k_hw_common(ah
)->hw
->conf
;
71 if (conf_is_ht40(conf
))
72 return ath9k_hw_mac_usec(ah
, clks
) / 2;
74 return ath9k_hw_mac_usec(ah
, clks
);
77 static u32
ath9k_hw_mac_clks(struct ath_hw
*ah
, u32 usecs
)
79 struct ieee80211_conf
*conf
= &ath9k_hw_common(ah
)->hw
->conf
;
81 if (!ah
->curchan
) /* should really check for CCK instead */
82 return usecs
*ATH9K_CLOCK_RATE_CCK
;
83 if (conf
->channel
->band
== IEEE80211_BAND_2GHZ
)
84 return usecs
*ATH9K_CLOCK_RATE_2GHZ_OFDM
;
85 return usecs
*ATH9K_CLOCK_RATE_5GHZ_OFDM
;
88 static u32
ath9k_hw_mac_to_clks(struct ath_hw
*ah
, u32 usecs
)
90 struct ieee80211_conf
*conf
= &ath9k_hw_common(ah
)->hw
->conf
;
92 if (conf_is_ht40(conf
))
93 return ath9k_hw_mac_clks(ah
, usecs
) * 2;
95 return ath9k_hw_mac_clks(ah
, usecs
);
98 bool ath9k_hw_wait(struct ath_hw
*ah
, u32 reg
, u32 mask
, u32 val
, u32 timeout
)
102 BUG_ON(timeout
< AH_TIME_QUANTUM
);
104 for (i
= 0; i
< (timeout
/ AH_TIME_QUANTUM
); i
++) {
105 if ((REG_READ(ah
, reg
) & mask
) == val
)
108 udelay(AH_TIME_QUANTUM
);
111 ath_print(ath9k_hw_common(ah
), ATH_DBG_ANY
,
112 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
113 timeout
, reg
, REG_READ(ah
, reg
), mask
, val
);
117 EXPORT_SYMBOL(ath9k_hw_wait
);
119 u32
ath9k_hw_reverse_bits(u32 val
, u32 n
)
124 for (i
= 0, retval
= 0; i
< n
; i
++) {
125 retval
= (retval
<< 1) | (val
& 1);
131 bool ath9k_get_channel_edges(struct ath_hw
*ah
,
135 struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
137 if (flags
& CHANNEL_5GHZ
) {
138 *low
= pCap
->low_5ghz_chan
;
139 *high
= pCap
->high_5ghz_chan
;
142 if ((flags
& CHANNEL_2GHZ
)) {
143 *low
= pCap
->low_2ghz_chan
;
144 *high
= pCap
->high_2ghz_chan
;
150 u16
ath9k_hw_computetxtime(struct ath_hw
*ah
,
152 u32 frameLen
, u16 rateix
,
155 u32 bitsPerSymbol
, numBits
, numSymbols
, phyTime
, txTime
;
161 case WLAN_RC_PHY_CCK
:
162 phyTime
= CCK_PREAMBLE_BITS
+ CCK_PLCP_BITS
;
165 numBits
= frameLen
<< 3;
166 txTime
= CCK_SIFS_TIME
+ phyTime
+ ((numBits
* 1000) / kbps
);
168 case WLAN_RC_PHY_OFDM
:
169 if (ah
->curchan
&& IS_CHAN_QUARTER_RATE(ah
->curchan
)) {
170 bitsPerSymbol
= (kbps
* OFDM_SYMBOL_TIME_QUARTER
) / 1000;
171 numBits
= OFDM_PLCP_BITS
+ (frameLen
<< 3);
172 numSymbols
= DIV_ROUND_UP(numBits
, bitsPerSymbol
);
173 txTime
= OFDM_SIFS_TIME_QUARTER
174 + OFDM_PREAMBLE_TIME_QUARTER
175 + (numSymbols
* OFDM_SYMBOL_TIME_QUARTER
);
176 } else if (ah
->curchan
&&
177 IS_CHAN_HALF_RATE(ah
->curchan
)) {
178 bitsPerSymbol
= (kbps
* OFDM_SYMBOL_TIME_HALF
) / 1000;
179 numBits
= OFDM_PLCP_BITS
+ (frameLen
<< 3);
180 numSymbols
= DIV_ROUND_UP(numBits
, bitsPerSymbol
);
181 txTime
= OFDM_SIFS_TIME_HALF
+
182 OFDM_PREAMBLE_TIME_HALF
183 + (numSymbols
* OFDM_SYMBOL_TIME_HALF
);
185 bitsPerSymbol
= (kbps
* OFDM_SYMBOL_TIME
) / 1000;
186 numBits
= OFDM_PLCP_BITS
+ (frameLen
<< 3);
187 numSymbols
= DIV_ROUND_UP(numBits
, bitsPerSymbol
);
188 txTime
= OFDM_SIFS_TIME
+ OFDM_PREAMBLE_TIME
189 + (numSymbols
* OFDM_SYMBOL_TIME
);
193 ath_print(ath9k_hw_common(ah
), ATH_DBG_FATAL
,
194 "Unknown phy %u (rate ix %u)\n", phy
, rateix
);
201 EXPORT_SYMBOL(ath9k_hw_computetxtime
);
203 void ath9k_hw_get_channel_centers(struct ath_hw
*ah
,
204 struct ath9k_channel
*chan
,
205 struct chan_centers
*centers
)
209 if (!IS_CHAN_HT40(chan
)) {
210 centers
->ctl_center
= centers
->ext_center
=
211 centers
->synth_center
= chan
->channel
;
215 if ((chan
->chanmode
== CHANNEL_A_HT40PLUS
) ||
216 (chan
->chanmode
== CHANNEL_G_HT40PLUS
)) {
217 centers
->synth_center
=
218 chan
->channel
+ HT40_CHANNEL_CENTER_SHIFT
;
221 centers
->synth_center
=
222 chan
->channel
- HT40_CHANNEL_CENTER_SHIFT
;
226 centers
->ctl_center
=
227 centers
->synth_center
- (extoff
* HT40_CHANNEL_CENTER_SHIFT
);
228 /* 25 MHz spacing is supported by hw but not on upper layers */
229 centers
->ext_center
=
230 centers
->synth_center
+ (extoff
* HT40_CHANNEL_CENTER_SHIFT
);
237 static void ath9k_hw_read_revisions(struct ath_hw
*ah
)
241 val
= REG_READ(ah
, AR_SREV
) & AR_SREV_ID
;
244 val
= REG_READ(ah
, AR_SREV
);
245 ah
->hw_version
.macVersion
=
246 (val
& AR_SREV_VERSION2
) >> AR_SREV_TYPE2_S
;
247 ah
->hw_version
.macRev
= MS(val
, AR_SREV_REVISION2
);
248 ah
->is_pciexpress
= (val
& AR_SREV_TYPE2_HOST_MODE
) ? 0 : 1;
250 if (!AR_SREV_9100(ah
))
251 ah
->hw_version
.macVersion
= MS(val
, AR_SREV_VERSION
);
253 ah
->hw_version
.macRev
= val
& AR_SREV_REVISION
;
255 if (ah
->hw_version
.macVersion
== AR_SREV_VERSION_5416_PCIE
)
256 ah
->is_pciexpress
= true;
260 static int ath9k_hw_get_radiorev(struct ath_hw
*ah
)
265 REG_WRITE(ah
, AR_PHY(0x36), 0x00007058);
267 for (i
= 0; i
< 8; i
++)
268 REG_WRITE(ah
, AR_PHY(0x20), 0x00010000);
269 val
= (REG_READ(ah
, AR_PHY(256)) >> 24) & 0xff;
270 val
= ((val
& 0xf0) >> 4) | ((val
& 0x0f) << 4);
272 return ath9k_hw_reverse_bits(val
, 8);
275 /************************************/
276 /* HW Attach, Detach, Init Routines */
277 /************************************/
279 static void ath9k_hw_disablepcie(struct ath_hw
*ah
)
281 if (AR_SREV_9100(ah
))
284 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x9248fc00);
285 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x24924924);
286 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x28000029);
287 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x57160824);
288 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x25980579);
289 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x00000000);
290 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x1aaabe40);
291 REG_WRITE(ah
, AR_PCIE_SERDES
, 0xbe105554);
292 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x000e1007);
294 REG_WRITE(ah
, AR_PCIE_SERDES2
, 0x00000000);
297 static bool ath9k_hw_chip_test(struct ath_hw
*ah
)
299 struct ath_common
*common
= ath9k_hw_common(ah
);
300 u32 regAddr
[2] = { AR_STA_ID0
, AR_PHY_BASE
+ (8 << 2) };
302 u32 patternData
[4] = { 0x55555555,
308 for (i
= 0; i
< 2; i
++) {
309 u32 addr
= regAddr
[i
];
312 regHold
[i
] = REG_READ(ah
, addr
);
313 for (j
= 0; j
< 0x100; j
++) {
314 wrData
= (j
<< 16) | j
;
315 REG_WRITE(ah
, addr
, wrData
);
316 rdData
= REG_READ(ah
, addr
);
317 if (rdData
!= wrData
) {
318 ath_print(common
, ATH_DBG_FATAL
,
319 "address test failed "
320 "addr: 0x%08x - wr:0x%08x != "
322 addr
, wrData
, rdData
);
326 for (j
= 0; j
< 4; j
++) {
327 wrData
= patternData
[j
];
328 REG_WRITE(ah
, addr
, wrData
);
329 rdData
= REG_READ(ah
, addr
);
330 if (wrData
!= rdData
) {
331 ath_print(common
, ATH_DBG_FATAL
,
332 "address test failed "
333 "addr: 0x%08x - wr:0x%08x != "
335 addr
, wrData
, rdData
);
339 REG_WRITE(ah
, regAddr
[i
], regHold
[i
]);
346 static const char *ath9k_hw_devname(u16 devid
)
349 case AR5416_DEVID_PCI
:
350 return "Atheros 5416";
351 case AR5416_DEVID_PCIE
:
352 return "Atheros 5418";
353 case AR9160_DEVID_PCI
:
354 return "Atheros 9160";
355 case AR5416_AR9100_DEVID
:
356 return "Atheros 9100";
357 case AR9280_DEVID_PCI
:
358 case AR9280_DEVID_PCIE
:
359 return "Atheros 9280";
360 case AR9285_DEVID_PCIE
:
361 return "Atheros 9285";
362 case AR5416_DEVID_AR9287_PCI
:
363 case AR5416_DEVID_AR9287_PCIE
:
364 return "Atheros 9287";
370 static void ath9k_hw_init_config(struct ath_hw
*ah
)
374 ah
->config
.dma_beacon_response_time
= 2;
375 ah
->config
.sw_beacon_response_time
= 10;
376 ah
->config
.additional_swba_backoff
= 0;
377 ah
->config
.ack_6mb
= 0x0;
378 ah
->config
.cwm_ignore_extcca
= 0;
379 ah
->config
.pcie_powersave_enable
= 0;
380 ah
->config
.pcie_clock_req
= 0;
381 ah
->config
.pcie_waen
= 0;
382 ah
->config
.analog_shiftreg
= 1;
383 ah
->config
.ht_enable
= 1;
384 ah
->config
.ofdm_trig_low
= 200;
385 ah
->config
.ofdm_trig_high
= 500;
386 ah
->config
.cck_trig_high
= 200;
387 ah
->config
.cck_trig_low
= 100;
388 ah
->config
.enable_ani
= 1;
390 for (i
= 0; i
< AR_EEPROM_MODAL_SPURS
; i
++) {
391 ah
->config
.spurchans
[i
][0] = AR_NO_SPUR
;
392 ah
->config
.spurchans
[i
][1] = AR_NO_SPUR
;
395 ah
->config
.intr_mitigation
= true;
398 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
399 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
400 * This means we use it for all AR5416 devices, and the few
401 * minor PCI AR9280 devices out there.
403 * Serialization is required because these devices do not handle
404 * well the case of two concurrent reads/writes due to the latency
405 * involved. During one read/write another read/write can be issued
406 * on another CPU while the previous read/write may still be working
407 * on our hardware, if we hit this case the hardware poops in a loop.
408 * We prevent this by serializing reads and writes.
410 * This issue is not present on PCI-Express devices or pre-AR5416
411 * devices (legacy, 802.11abg).
413 if (num_possible_cpus() > 1)
414 ah
->config
.serialize_regmode
= SER_REG_MODE_AUTO
;
416 EXPORT_SYMBOL(ath9k_hw_init
);
418 static void ath9k_hw_init_defaults(struct ath_hw
*ah
)
420 struct ath_regulatory
*regulatory
= ath9k_hw_regulatory(ah
);
422 regulatory
->country_code
= CTRY_DEFAULT
;
423 regulatory
->power_limit
= MAX_RATE_POWER
;
424 regulatory
->tp_scale
= ATH9K_TP_SCALE_MAX
;
426 ah
->hw_version
.magic
= AR5416_MAGIC
;
427 ah
->hw_version
.subvendorid
= 0;
430 if (ah
->hw_version
.devid
== AR5416_AR9100_DEVID
)
431 ah
->hw_version
.macVersion
= AR_SREV_VERSION_9100
;
432 if (!AR_SREV_9100(ah
))
433 ah
->ah_flags
= AH_USE_EEPROM
;
436 ah
->sta_id1_defaults
= AR_STA_ID1_CRPT_MIC_ENABLE
;
437 ah
->beacon_interval
= 100;
438 ah
->enable_32kHz_clock
= DONT_USE_32KHZ
;
439 ah
->slottime
= (u32
) -1;
440 ah
->acktimeout
= (u32
) -1;
441 ah
->ctstimeout
= (u32
) -1;
442 ah
->globaltxtimeout
= (u32
) -1;
443 ah
->power_mode
= ATH9K_PM_UNDEFINED
;
446 static int ath9k_hw_rf_claim(struct ath_hw
*ah
)
450 REG_WRITE(ah
, AR_PHY(0), 0x00000007);
452 val
= ath9k_hw_get_radiorev(ah
);
453 switch (val
& AR_RADIO_SREV_MAJOR
) {
455 val
= AR_RAD5133_SREV_MAJOR
;
457 case AR_RAD5133_SREV_MAJOR
:
458 case AR_RAD5122_SREV_MAJOR
:
459 case AR_RAD2133_SREV_MAJOR
:
460 case AR_RAD2122_SREV_MAJOR
:
463 ath_print(ath9k_hw_common(ah
), ATH_DBG_FATAL
,
464 "Radio Chip Rev 0x%02X not supported\n",
465 val
& AR_RADIO_SREV_MAJOR
);
469 ah
->hw_version
.analog5GhzRev
= val
;
474 static int ath9k_hw_init_macaddr(struct ath_hw
*ah
)
476 struct ath_common
*common
= ath9k_hw_common(ah
);
482 for (i
= 0; i
< 3; i
++) {
483 eeval
= ah
->eep_ops
->get_eeprom(ah
, AR_EEPROM_MAC(i
));
485 common
->macaddr
[2 * i
] = eeval
>> 8;
486 common
->macaddr
[2 * i
+ 1] = eeval
& 0xff;
488 if (sum
== 0 || sum
== 0xffff * 3)
489 return -EADDRNOTAVAIL
;
494 static void ath9k_hw_init_rxgain_ini(struct ath_hw
*ah
)
498 if (ah
->eep_ops
->get_eeprom(ah
, EEP_MINOR_REV
) >= AR5416_EEP_MINOR_VER_17
) {
499 rxgain_type
= ah
->eep_ops
->get_eeprom(ah
, EEP_RXGAIN_TYPE
);
501 if (rxgain_type
== AR5416_EEP_RXGAIN_13DB_BACKOFF
)
502 INIT_INI_ARRAY(&ah
->iniModesRxGain
,
503 ar9280Modes_backoff_13db_rxgain_9280_2
,
504 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2
), 6);
505 else if (rxgain_type
== AR5416_EEP_RXGAIN_23DB_BACKOFF
)
506 INIT_INI_ARRAY(&ah
->iniModesRxGain
,
507 ar9280Modes_backoff_23db_rxgain_9280_2
,
508 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2
), 6);
510 INIT_INI_ARRAY(&ah
->iniModesRxGain
,
511 ar9280Modes_original_rxgain_9280_2
,
512 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2
), 6);
514 INIT_INI_ARRAY(&ah
->iniModesRxGain
,
515 ar9280Modes_original_rxgain_9280_2
,
516 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2
), 6);
520 static void ath9k_hw_init_txgain_ini(struct ath_hw
*ah
)
524 if (ah
->eep_ops
->get_eeprom(ah
, EEP_MINOR_REV
) >= AR5416_EEP_MINOR_VER_19
) {
525 txgain_type
= ah
->eep_ops
->get_eeprom(ah
, EEP_TXGAIN_TYPE
);
527 if (txgain_type
== AR5416_EEP_TXGAIN_HIGH_POWER
)
528 INIT_INI_ARRAY(&ah
->iniModesTxGain
,
529 ar9280Modes_high_power_tx_gain_9280_2
,
530 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2
), 6);
532 INIT_INI_ARRAY(&ah
->iniModesTxGain
,
533 ar9280Modes_original_tx_gain_9280_2
,
534 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2
), 6);
536 INIT_INI_ARRAY(&ah
->iniModesTxGain
,
537 ar9280Modes_original_tx_gain_9280_2
,
538 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2
), 6);
542 static int ath9k_hw_post_init(struct ath_hw
*ah
)
546 if (!ath9k_hw_chip_test(ah
))
549 ecode
= ath9k_hw_rf_claim(ah
);
553 ecode
= ath9k_hw_eeprom_init(ah
);
557 ath_print(ath9k_hw_common(ah
), ATH_DBG_CONFIG
,
558 "Eeprom VER: %d, REV: %d\n",
559 ah
->eep_ops
->get_eeprom_ver(ah
),
560 ah
->eep_ops
->get_eeprom_rev(ah
));
562 if (!AR_SREV_9280_10_OR_LATER(ah
)) {
563 ecode
= ath9k_hw_rf_alloc_ext_banks(ah
);
565 ath_print(ath9k_hw_common(ah
), ATH_DBG_FATAL
,
566 "Failed allocating banks for "
572 if (!AR_SREV_9100(ah
)) {
573 ath9k_hw_ani_setup(ah
);
574 ath9k_hw_ani_init(ah
);
580 static bool ath9k_hw_devid_supported(u16 devid
)
583 case AR5416_DEVID_PCI
:
584 case AR5416_DEVID_PCIE
:
585 case AR5416_AR9100_DEVID
:
586 case AR9160_DEVID_PCI
:
587 case AR9280_DEVID_PCI
:
588 case AR9280_DEVID_PCIE
:
589 case AR9285_DEVID_PCIE
:
590 case AR5416_DEVID_AR9287_PCI
:
591 case AR5416_DEVID_AR9287_PCIE
:
600 static bool ath9k_hw_macversion_supported(u32 macversion
)
602 switch (macversion
) {
603 case AR_SREV_VERSION_5416_PCI
:
604 case AR_SREV_VERSION_5416_PCIE
:
605 case AR_SREV_VERSION_9160
:
606 case AR_SREV_VERSION_9100
:
607 case AR_SREV_VERSION_9280
:
608 case AR_SREV_VERSION_9285
:
609 case AR_SREV_VERSION_9287
:
610 case AR_SREV_VERSION_9271
:
618 static void ath9k_hw_init_cal_settings(struct ath_hw
*ah
)
620 if (AR_SREV_9160_10_OR_LATER(ah
)) {
621 if (AR_SREV_9280_10_OR_LATER(ah
)) {
622 ah
->iq_caldata
.calData
= &iq_cal_single_sample
;
623 ah
->adcgain_caldata
.calData
=
624 &adc_gain_cal_single_sample
;
625 ah
->adcdc_caldata
.calData
=
626 &adc_dc_cal_single_sample
;
627 ah
->adcdc_calinitdata
.calData
=
630 ah
->iq_caldata
.calData
= &iq_cal_multi_sample
;
631 ah
->adcgain_caldata
.calData
=
632 &adc_gain_cal_multi_sample
;
633 ah
->adcdc_caldata
.calData
=
634 &adc_dc_cal_multi_sample
;
635 ah
->adcdc_calinitdata
.calData
=
638 ah
->supp_cals
= ADC_GAIN_CAL
| ADC_DC_CAL
| IQ_MISMATCH_CAL
;
642 static void ath9k_hw_init_mode_regs(struct ath_hw
*ah
)
644 if (AR_SREV_9271(ah
)) {
645 INIT_INI_ARRAY(&ah
->iniModes
, ar9271Modes_9271
,
646 ARRAY_SIZE(ar9271Modes_9271
), 6);
647 INIT_INI_ARRAY(&ah
->iniCommon
, ar9271Common_9271
,
648 ARRAY_SIZE(ar9271Common_9271
), 2);
649 INIT_INI_ARRAY(&ah
->iniModes_9271_1_0_only
,
650 ar9271Modes_9271_1_0_only
,
651 ARRAY_SIZE(ar9271Modes_9271_1_0_only
), 6);
655 if (AR_SREV_9287_11_OR_LATER(ah
)) {
656 INIT_INI_ARRAY(&ah
->iniModes
, ar9287Modes_9287_1_1
,
657 ARRAY_SIZE(ar9287Modes_9287_1_1
), 6);
658 INIT_INI_ARRAY(&ah
->iniCommon
, ar9287Common_9287_1_1
,
659 ARRAY_SIZE(ar9287Common_9287_1_1
), 2);
660 if (ah
->config
.pcie_clock_req
)
661 INIT_INI_ARRAY(&ah
->iniPcieSerdes
,
662 ar9287PciePhy_clkreq_off_L1_9287_1_1
,
663 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1
), 2);
665 INIT_INI_ARRAY(&ah
->iniPcieSerdes
,
666 ar9287PciePhy_clkreq_always_on_L1_9287_1_1
,
667 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1
),
669 } else if (AR_SREV_9287_10_OR_LATER(ah
)) {
670 INIT_INI_ARRAY(&ah
->iniModes
, ar9287Modes_9287_1_0
,
671 ARRAY_SIZE(ar9287Modes_9287_1_0
), 6);
672 INIT_INI_ARRAY(&ah
->iniCommon
, ar9287Common_9287_1_0
,
673 ARRAY_SIZE(ar9287Common_9287_1_0
), 2);
675 if (ah
->config
.pcie_clock_req
)
676 INIT_INI_ARRAY(&ah
->iniPcieSerdes
,
677 ar9287PciePhy_clkreq_off_L1_9287_1_0
,
678 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0
), 2);
680 INIT_INI_ARRAY(&ah
->iniPcieSerdes
,
681 ar9287PciePhy_clkreq_always_on_L1_9287_1_0
,
682 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0
),
684 } else if (AR_SREV_9285_12_OR_LATER(ah
)) {
687 INIT_INI_ARRAY(&ah
->iniModes
, ar9285Modes_9285_1_2
,
688 ARRAY_SIZE(ar9285Modes_9285_1_2
), 6);
689 INIT_INI_ARRAY(&ah
->iniCommon
, ar9285Common_9285_1_2
,
690 ARRAY_SIZE(ar9285Common_9285_1_2
), 2);
692 if (ah
->config
.pcie_clock_req
) {
693 INIT_INI_ARRAY(&ah
->iniPcieSerdes
,
694 ar9285PciePhy_clkreq_off_L1_9285_1_2
,
695 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2
), 2);
697 INIT_INI_ARRAY(&ah
->iniPcieSerdes
,
698 ar9285PciePhy_clkreq_always_on_L1_9285_1_2
,
699 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2
),
702 } else if (AR_SREV_9285_10_OR_LATER(ah
)) {
703 INIT_INI_ARRAY(&ah
->iniModes
, ar9285Modes_9285
,
704 ARRAY_SIZE(ar9285Modes_9285
), 6);
705 INIT_INI_ARRAY(&ah
->iniCommon
, ar9285Common_9285
,
706 ARRAY_SIZE(ar9285Common_9285
), 2);
708 if (ah
->config
.pcie_clock_req
) {
709 INIT_INI_ARRAY(&ah
->iniPcieSerdes
,
710 ar9285PciePhy_clkreq_off_L1_9285
,
711 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285
), 2);
713 INIT_INI_ARRAY(&ah
->iniPcieSerdes
,
714 ar9285PciePhy_clkreq_always_on_L1_9285
,
715 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285
), 2);
717 } else if (AR_SREV_9280_20_OR_LATER(ah
)) {
718 INIT_INI_ARRAY(&ah
->iniModes
, ar9280Modes_9280_2
,
719 ARRAY_SIZE(ar9280Modes_9280_2
), 6);
720 INIT_INI_ARRAY(&ah
->iniCommon
, ar9280Common_9280_2
,
721 ARRAY_SIZE(ar9280Common_9280_2
), 2);
723 if (ah
->config
.pcie_clock_req
) {
724 INIT_INI_ARRAY(&ah
->iniPcieSerdes
,
725 ar9280PciePhy_clkreq_off_L1_9280
,
726 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280
),2);
728 INIT_INI_ARRAY(&ah
->iniPcieSerdes
,
729 ar9280PciePhy_clkreq_always_on_L1_9280
,
730 ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280
), 2);
732 INIT_INI_ARRAY(&ah
->iniModesAdditional
,
733 ar9280Modes_fast_clock_9280_2
,
734 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2
), 3);
735 } else if (AR_SREV_9280_10_OR_LATER(ah
)) {
736 INIT_INI_ARRAY(&ah
->iniModes
, ar9280Modes_9280
,
737 ARRAY_SIZE(ar9280Modes_9280
), 6);
738 INIT_INI_ARRAY(&ah
->iniCommon
, ar9280Common_9280
,
739 ARRAY_SIZE(ar9280Common_9280
), 2);
740 } else if (AR_SREV_9160_10_OR_LATER(ah
)) {
741 INIT_INI_ARRAY(&ah
->iniModes
, ar5416Modes_9160
,
742 ARRAY_SIZE(ar5416Modes_9160
), 6);
743 INIT_INI_ARRAY(&ah
->iniCommon
, ar5416Common_9160
,
744 ARRAY_SIZE(ar5416Common_9160
), 2);
745 INIT_INI_ARRAY(&ah
->iniBank0
, ar5416Bank0_9160
,
746 ARRAY_SIZE(ar5416Bank0_9160
), 2);
747 INIT_INI_ARRAY(&ah
->iniBB_RfGain
, ar5416BB_RfGain_9160
,
748 ARRAY_SIZE(ar5416BB_RfGain_9160
), 3);
749 INIT_INI_ARRAY(&ah
->iniBank1
, ar5416Bank1_9160
,
750 ARRAY_SIZE(ar5416Bank1_9160
), 2);
751 INIT_INI_ARRAY(&ah
->iniBank2
, ar5416Bank2_9160
,
752 ARRAY_SIZE(ar5416Bank2_9160
), 2);
753 INIT_INI_ARRAY(&ah
->iniBank3
, ar5416Bank3_9160
,
754 ARRAY_SIZE(ar5416Bank3_9160
), 3);
755 INIT_INI_ARRAY(&ah
->iniBank6
, ar5416Bank6_9160
,
756 ARRAY_SIZE(ar5416Bank6_9160
), 3);
757 INIT_INI_ARRAY(&ah
->iniBank6TPC
, ar5416Bank6TPC_9160
,
758 ARRAY_SIZE(ar5416Bank6TPC_9160
), 3);
759 INIT_INI_ARRAY(&ah
->iniBank7
, ar5416Bank7_9160
,
760 ARRAY_SIZE(ar5416Bank7_9160
), 2);
761 if (AR_SREV_9160_11(ah
)) {
762 INIT_INI_ARRAY(&ah
->iniAddac
,
764 ARRAY_SIZE(ar5416Addac_91601_1
), 2);
766 INIT_INI_ARRAY(&ah
->iniAddac
, ar5416Addac_9160
,
767 ARRAY_SIZE(ar5416Addac_9160
), 2);
769 } else if (AR_SREV_9100_OR_LATER(ah
)) {
770 INIT_INI_ARRAY(&ah
->iniModes
, ar5416Modes_9100
,
771 ARRAY_SIZE(ar5416Modes_9100
), 6);
772 INIT_INI_ARRAY(&ah
->iniCommon
, ar5416Common_9100
,
773 ARRAY_SIZE(ar5416Common_9100
), 2);
774 INIT_INI_ARRAY(&ah
->iniBank0
, ar5416Bank0_9100
,
775 ARRAY_SIZE(ar5416Bank0_9100
), 2);
776 INIT_INI_ARRAY(&ah
->iniBB_RfGain
, ar5416BB_RfGain_9100
,
777 ARRAY_SIZE(ar5416BB_RfGain_9100
), 3);
778 INIT_INI_ARRAY(&ah
->iniBank1
, ar5416Bank1_9100
,
779 ARRAY_SIZE(ar5416Bank1_9100
), 2);
780 INIT_INI_ARRAY(&ah
->iniBank2
, ar5416Bank2_9100
,
781 ARRAY_SIZE(ar5416Bank2_9100
), 2);
782 INIT_INI_ARRAY(&ah
->iniBank3
, ar5416Bank3_9100
,
783 ARRAY_SIZE(ar5416Bank3_9100
), 3);
784 INIT_INI_ARRAY(&ah
->iniBank6
, ar5416Bank6_9100
,
785 ARRAY_SIZE(ar5416Bank6_9100
), 3);
786 INIT_INI_ARRAY(&ah
->iniBank6TPC
, ar5416Bank6TPC_9100
,
787 ARRAY_SIZE(ar5416Bank6TPC_9100
), 3);
788 INIT_INI_ARRAY(&ah
->iniBank7
, ar5416Bank7_9100
,
789 ARRAY_SIZE(ar5416Bank7_9100
), 2);
790 INIT_INI_ARRAY(&ah
->iniAddac
, ar5416Addac_9100
,
791 ARRAY_SIZE(ar5416Addac_9100
), 2);
793 INIT_INI_ARRAY(&ah
->iniModes
, ar5416Modes
,
794 ARRAY_SIZE(ar5416Modes
), 6);
795 INIT_INI_ARRAY(&ah
->iniCommon
, ar5416Common
,
796 ARRAY_SIZE(ar5416Common
), 2);
797 INIT_INI_ARRAY(&ah
->iniBank0
, ar5416Bank0
,
798 ARRAY_SIZE(ar5416Bank0
), 2);
799 INIT_INI_ARRAY(&ah
->iniBB_RfGain
, ar5416BB_RfGain
,
800 ARRAY_SIZE(ar5416BB_RfGain
), 3);
801 INIT_INI_ARRAY(&ah
->iniBank1
, ar5416Bank1
,
802 ARRAY_SIZE(ar5416Bank1
), 2);
803 INIT_INI_ARRAY(&ah
->iniBank2
, ar5416Bank2
,
804 ARRAY_SIZE(ar5416Bank2
), 2);
805 INIT_INI_ARRAY(&ah
->iniBank3
, ar5416Bank3
,
806 ARRAY_SIZE(ar5416Bank3
), 3);
807 INIT_INI_ARRAY(&ah
->iniBank6
, ar5416Bank6
,
808 ARRAY_SIZE(ar5416Bank6
), 3);
809 INIT_INI_ARRAY(&ah
->iniBank6TPC
, ar5416Bank6TPC
,
810 ARRAY_SIZE(ar5416Bank6TPC
), 3);
811 INIT_INI_ARRAY(&ah
->iniBank7
, ar5416Bank7
,
812 ARRAY_SIZE(ar5416Bank7
), 2);
813 INIT_INI_ARRAY(&ah
->iniAddac
, ar5416Addac
,
814 ARRAY_SIZE(ar5416Addac
), 2);
818 static void ath9k_hw_init_mode_gain_regs(struct ath_hw
*ah
)
820 if (AR_SREV_9287_11_OR_LATER(ah
))
821 INIT_INI_ARRAY(&ah
->iniModesRxGain
,
822 ar9287Modes_rx_gain_9287_1_1
,
823 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1
), 6);
824 else if (AR_SREV_9287_10(ah
))
825 INIT_INI_ARRAY(&ah
->iniModesRxGain
,
826 ar9287Modes_rx_gain_9287_1_0
,
827 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0
), 6);
828 else if (AR_SREV_9280_20(ah
))
829 ath9k_hw_init_rxgain_ini(ah
);
831 if (AR_SREV_9287_11_OR_LATER(ah
)) {
832 INIT_INI_ARRAY(&ah
->iniModesTxGain
,
833 ar9287Modes_tx_gain_9287_1_1
,
834 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1
), 6);
835 } else if (AR_SREV_9287_10(ah
)) {
836 INIT_INI_ARRAY(&ah
->iniModesTxGain
,
837 ar9287Modes_tx_gain_9287_1_0
,
838 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0
), 6);
839 } else if (AR_SREV_9280_20(ah
)) {
840 ath9k_hw_init_txgain_ini(ah
);
841 } else if (AR_SREV_9285_12_OR_LATER(ah
)) {
842 u32 txgain_type
= ah
->eep_ops
->get_eeprom(ah
, EEP_TXGAIN_TYPE
);
845 if (txgain_type
== AR5416_EEP_TXGAIN_HIGH_POWER
) {
846 INIT_INI_ARRAY(&ah
->iniModesTxGain
,
847 ar9285Modes_high_power_tx_gain_9285_1_2
,
848 ARRAY_SIZE(ar9285Modes_high_power_tx_gain_9285_1_2
), 6);
850 INIT_INI_ARRAY(&ah
->iniModesTxGain
,
851 ar9285Modes_original_tx_gain_9285_1_2
,
852 ARRAY_SIZE(ar9285Modes_original_tx_gain_9285_1_2
), 6);
858 static void ath9k_hw_init_eeprom_fix(struct ath_hw
*ah
)
862 if (ah
->hw_version
.devid
== AR9280_DEVID_PCI
) {
865 for (i
= 0; i
< ah
->iniModes
.ia_rows
; i
++) {
866 u32 reg
= INI_RA(&ah
->iniModes
, i
, 0);
868 for (j
= 1; j
< ah
->iniModes
.ia_columns
; j
++) {
869 u32 val
= INI_RA(&ah
->iniModes
, i
, j
);
871 INI_RA(&ah
->iniModes
, i
, j
) =
872 ath9k_hw_ini_fixup(ah
,
880 int ath9k_hw_init(struct ath_hw
*ah
)
882 struct ath_common
*common
= ath9k_hw_common(ah
);
885 if (!ath9k_hw_devid_supported(ah
->hw_version
.devid
)) {
886 ath_print(common
, ATH_DBG_FATAL
,
887 "Unsupported device ID: 0x%0x\n",
888 ah
->hw_version
.devid
);
892 ath9k_hw_init_defaults(ah
);
893 ath9k_hw_init_config(ah
);
895 if (!ath9k_hw_set_reset_reg(ah
, ATH9K_RESET_POWER_ON
)) {
896 ath_print(common
, ATH_DBG_FATAL
,
897 "Couldn't reset chip\n");
901 if (!ath9k_hw_setpower(ah
, ATH9K_PM_AWAKE
)) {
902 ath_print(common
, ATH_DBG_FATAL
, "Couldn't wakeup chip\n");
906 if (ah
->config
.serialize_regmode
== SER_REG_MODE_AUTO
) {
907 if (ah
->hw_version
.macVersion
== AR_SREV_VERSION_5416_PCI
||
908 (AR_SREV_9280(ah
) && !ah
->is_pciexpress
)) {
909 ah
->config
.serialize_regmode
=
912 ah
->config
.serialize_regmode
=
917 ath_print(common
, ATH_DBG_RESET
, "serialize_regmode is %d\n",
918 ah
->config
.serialize_regmode
);
920 if (AR_SREV_9285(ah
) || AR_SREV_9271(ah
))
921 ah
->config
.max_txtrig_level
= MAX_TX_FIFO_THRESHOLD
>> 1;
923 ah
->config
.max_txtrig_level
= MAX_TX_FIFO_THRESHOLD
;
925 if (!ath9k_hw_macversion_supported(ah
->hw_version
.macVersion
)) {
926 ath_print(common
, ATH_DBG_FATAL
,
927 "Mac Chip Rev 0x%02x.%x is not supported by "
928 "this driver\n", ah
->hw_version
.macVersion
,
929 ah
->hw_version
.macRev
);
933 if (AR_SREV_9100(ah
)) {
934 ah
->iq_caldata
.calData
= &iq_cal_multi_sample
;
935 ah
->supp_cals
= IQ_MISMATCH_CAL
;
936 ah
->is_pciexpress
= false;
939 if (AR_SREV_9271(ah
))
940 ah
->is_pciexpress
= false;
942 ah
->hw_version
.phyRev
= REG_READ(ah
, AR_PHY_CHIP_ID
);
944 ath9k_hw_init_cal_settings(ah
);
946 ah
->ani_function
= ATH9K_ANI_ALL
;
947 if (AR_SREV_9280_10_OR_LATER(ah
)) {
948 ah
->ani_function
&= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL
;
949 ah
->ath9k_hw_rf_set_freq
= &ath9k_hw_ar9280_set_channel
;
950 ah
->ath9k_hw_spur_mitigate_freq
= &ath9k_hw_9280_spur_mitigate
;
952 ah
->ath9k_hw_rf_set_freq
= &ath9k_hw_set_channel
;
953 ah
->ath9k_hw_spur_mitigate_freq
= &ath9k_hw_spur_mitigate
;
956 ath9k_hw_init_mode_regs(ah
);
958 if (ah
->is_pciexpress
)
959 ath9k_hw_configpcipowersave(ah
, 0, 0);
961 ath9k_hw_disablepcie(ah
);
963 /* Support for Japan ch.14 (2484) spread */
964 if (AR_SREV_9287_11_OR_LATER(ah
)) {
965 INIT_INI_ARRAY(&ah
->iniCckfirNormal
,
966 ar9287Common_normal_cck_fir_coeff_92871_1
,
967 ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_92871_1
), 2);
968 INIT_INI_ARRAY(&ah
->iniCckfirJapan2484
,
969 ar9287Common_japan_2484_cck_fir_coeff_92871_1
,
970 ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_92871_1
), 2);
973 r
= ath9k_hw_post_init(ah
);
977 ath9k_hw_init_mode_gain_regs(ah
);
978 r
= ath9k_hw_fill_cap_info(ah
);
982 ath9k_hw_init_eeprom_fix(ah
);
984 r
= ath9k_hw_init_macaddr(ah
);
986 ath_print(common
, ATH_DBG_FATAL
,
987 "Failed to initialize MAC address\n");
991 if (AR_SREV_9285(ah
) || AR_SREV_9271(ah
))
992 ah
->tx_trig_level
= (AR_FTRIG_256B
>> AR_FTRIG_S
);
994 ah
->tx_trig_level
= (AR_FTRIG_512B
>> AR_FTRIG_S
);
996 ath9k_init_nfcal_hist_buffer(ah
);
998 common
->state
= ATH_HW_INITIALIZED
;
1003 static void ath9k_hw_init_bb(struct ath_hw
*ah
,
1004 struct ath9k_channel
*chan
)
1008 synthDelay
= REG_READ(ah
, AR_PHY_RX_DELAY
) & AR_PHY_RX_DELAY_DELAY
;
1009 if (IS_CHAN_B(chan
))
1010 synthDelay
= (4 * synthDelay
) / 22;
1014 REG_WRITE(ah
, AR_PHY_ACTIVE
, AR_PHY_ACTIVE_EN
);
1016 udelay(synthDelay
+ BASE_ACTIVATE_DELAY
);
1019 static void ath9k_hw_init_qos(struct ath_hw
*ah
)
1021 REG_WRITE(ah
, AR_MIC_QOS_CONTROL
, 0x100aa);
1022 REG_WRITE(ah
, AR_MIC_QOS_SELECT
, 0x3210);
1024 REG_WRITE(ah
, AR_QOS_NO_ACK
,
1025 SM(2, AR_QOS_NO_ACK_TWO_BIT
) |
1026 SM(5, AR_QOS_NO_ACK_BIT_OFF
) |
1027 SM(0, AR_QOS_NO_ACK_BYTE_OFF
));
1029 REG_WRITE(ah
, AR_TXOP_X
, AR_TXOP_X_VAL
);
1030 REG_WRITE(ah
, AR_TXOP_0_3
, 0xFFFFFFFF);
1031 REG_WRITE(ah
, AR_TXOP_4_7
, 0xFFFFFFFF);
1032 REG_WRITE(ah
, AR_TXOP_8_11
, 0xFFFFFFFF);
1033 REG_WRITE(ah
, AR_TXOP_12_15
, 0xFFFFFFFF);
1036 static void ath9k_hw_change_target_baud(struct ath_hw
*ah
, u32 freq
, u32 baud
)
1039 u32 baud_divider
= freq
* 1000 * 1000 / 16 / baud
;
1041 lcr
= REG_READ(ah
, 0x5100c);
1044 REG_WRITE(ah
, 0x5100c, lcr
);
1045 REG_WRITE(ah
, 0x51004, (baud_divider
>> 8));
1046 REG_WRITE(ah
, 0x51000, (baud_divider
& 0xff));
1049 REG_WRITE(ah
, 0x5100c, lcr
);
1052 static void ath9k_hw_init_pll(struct ath_hw
*ah
,
1053 struct ath9k_channel
*chan
)
1057 if (AR_SREV_9100(ah
)) {
1058 if (chan
&& IS_CHAN_5GHZ(chan
))
1063 if (AR_SREV_9280_10_OR_LATER(ah
)) {
1064 pll
= SM(0x5, AR_RTC_9160_PLL_REFDIV
);
1066 if (chan
&& IS_CHAN_HALF_RATE(chan
))
1067 pll
|= SM(0x1, AR_RTC_9160_PLL_CLKSEL
);
1068 else if (chan
&& IS_CHAN_QUARTER_RATE(chan
))
1069 pll
|= SM(0x2, AR_RTC_9160_PLL_CLKSEL
);
1071 if (chan
&& IS_CHAN_5GHZ(chan
)) {
1072 pll
|= SM(0x28, AR_RTC_9160_PLL_DIV
);
1075 if (AR_SREV_9280_20(ah
)) {
1076 if (((chan
->channel
% 20) == 0)
1077 || ((chan
->channel
% 10) == 0))
1083 pll
|= SM(0x2c, AR_RTC_9160_PLL_DIV
);
1086 } else if (AR_SREV_9160_10_OR_LATER(ah
)) {
1088 pll
= SM(0x5, AR_RTC_9160_PLL_REFDIV
);
1090 if (chan
&& IS_CHAN_HALF_RATE(chan
))
1091 pll
|= SM(0x1, AR_RTC_9160_PLL_CLKSEL
);
1092 else if (chan
&& IS_CHAN_QUARTER_RATE(chan
))
1093 pll
|= SM(0x2, AR_RTC_9160_PLL_CLKSEL
);
1095 if (chan
&& IS_CHAN_5GHZ(chan
))
1096 pll
|= SM(0x50, AR_RTC_9160_PLL_DIV
);
1098 pll
|= SM(0x58, AR_RTC_9160_PLL_DIV
);
1100 pll
= AR_RTC_PLL_REFDIV_5
| AR_RTC_PLL_DIV2
;
1102 if (chan
&& IS_CHAN_HALF_RATE(chan
))
1103 pll
|= SM(0x1, AR_RTC_PLL_CLKSEL
);
1104 else if (chan
&& IS_CHAN_QUARTER_RATE(chan
))
1105 pll
|= SM(0x2, AR_RTC_PLL_CLKSEL
);
1107 if (chan
&& IS_CHAN_5GHZ(chan
))
1108 pll
|= SM(0xa, AR_RTC_PLL_DIV
);
1110 pll
|= SM(0xb, AR_RTC_PLL_DIV
);
1113 REG_WRITE(ah
, AR_RTC_PLL_CONTROL
, pll
);
1115 /* Switch the core clock for ar9271 to 117Mhz */
1116 if (AR_SREV_9271(ah
)) {
1117 if ((pll
== 0x142c) || (pll
== 0x2850) ) {
1119 /* set CLKOBS to output AHB clock */
1120 REG_WRITE(ah
, 0x7020, 0xe);
1122 * 0x304: 117Mhz, ahb_ratio: 1x1
1123 * 0x306: 40Mhz, ahb_ratio: 1x1
1125 REG_WRITE(ah
, 0x50040, 0x304);
1127 * makes adjustments for the baud dividor to keep the
1128 * targetted baud rate based on the used core clock.
1130 ath9k_hw_change_target_baud(ah
, AR9271_CORE_CLOCK
,
1131 AR9271_TARGET_BAUD_RATE
);
1135 udelay(RTC_PLL_SETTLE_DELAY
);
1137 REG_WRITE(ah
, AR_RTC_SLEEP_CLK
, AR_RTC_FORCE_DERIVED_CLK
);
1140 static void ath9k_hw_init_chain_masks(struct ath_hw
*ah
)
1142 int rx_chainmask
, tx_chainmask
;
1144 rx_chainmask
= ah
->rxchainmask
;
1145 tx_chainmask
= ah
->txchainmask
;
1147 switch (rx_chainmask
) {
1149 REG_SET_BIT(ah
, AR_PHY_ANALOG_SWAP
,
1150 AR_PHY_SWAP_ALT_CHAIN
);
1152 if (ah
->hw_version
.macVersion
== AR_SREV_REVISION_5416_10
) {
1153 REG_WRITE(ah
, AR_PHY_RX_CHAINMASK
, 0x7);
1154 REG_WRITE(ah
, AR_PHY_CAL_CHAINMASK
, 0x7);
1160 REG_WRITE(ah
, AR_PHY_RX_CHAINMASK
, rx_chainmask
);
1161 REG_WRITE(ah
, AR_PHY_CAL_CHAINMASK
, rx_chainmask
);
1167 REG_WRITE(ah
, AR_SELFGEN_MASK
, tx_chainmask
);
1168 if (tx_chainmask
== 0x5) {
1169 REG_SET_BIT(ah
, AR_PHY_ANALOG_SWAP
,
1170 AR_PHY_SWAP_ALT_CHAIN
);
1172 if (AR_SREV_9100(ah
))
1173 REG_WRITE(ah
, AR_PHY_ANALOG_SWAP
,
1174 REG_READ(ah
, AR_PHY_ANALOG_SWAP
) | 0x00000001);
1177 static void ath9k_hw_init_interrupt_masks(struct ath_hw
*ah
,
1178 enum nl80211_iftype opmode
)
1180 ah
->mask_reg
= AR_IMR_TXERR
|
1186 if (ah
->config
.intr_mitigation
)
1187 ah
->mask_reg
|= AR_IMR_RXINTM
| AR_IMR_RXMINTR
;
1189 ah
->mask_reg
|= AR_IMR_RXOK
;
1191 ah
->mask_reg
|= AR_IMR_TXOK
;
1193 if (opmode
== NL80211_IFTYPE_AP
)
1194 ah
->mask_reg
|= AR_IMR_MIB
;
1196 REG_WRITE(ah
, AR_IMR
, ah
->mask_reg
);
1197 REG_WRITE(ah
, AR_IMR_S2
, REG_READ(ah
, AR_IMR_S2
) | AR_IMR_S2_GTT
);
1199 if (!AR_SREV_9100(ah
)) {
1200 REG_WRITE(ah
, AR_INTR_SYNC_CAUSE
, 0xFFFFFFFF);
1201 REG_WRITE(ah
, AR_INTR_SYNC_ENABLE
, AR_INTR_SYNC_DEFAULT
);
1202 REG_WRITE(ah
, AR_INTR_SYNC_MASK
, 0);
1206 static bool ath9k_hw_set_ack_timeout(struct ath_hw
*ah
, u32 us
)
1208 if (us
> ath9k_hw_mac_to_usec(ah
, MS(0xffffffff, AR_TIME_OUT_ACK
))) {
1209 ath_print(ath9k_hw_common(ah
), ATH_DBG_RESET
,
1210 "bad ack timeout %u\n", us
);
1211 ah
->acktimeout
= (u32
) -1;
1214 REG_RMW_FIELD(ah
, AR_TIME_OUT
,
1215 AR_TIME_OUT_ACK
, ath9k_hw_mac_to_clks(ah
, us
));
1216 ah
->acktimeout
= us
;
1221 static bool ath9k_hw_set_cts_timeout(struct ath_hw
*ah
, u32 us
)
1223 if (us
> ath9k_hw_mac_to_usec(ah
, MS(0xffffffff, AR_TIME_OUT_CTS
))) {
1224 ath_print(ath9k_hw_common(ah
), ATH_DBG_RESET
,
1225 "bad cts timeout %u\n", us
);
1226 ah
->ctstimeout
= (u32
) -1;
1229 REG_RMW_FIELD(ah
, AR_TIME_OUT
,
1230 AR_TIME_OUT_CTS
, ath9k_hw_mac_to_clks(ah
, us
));
1231 ah
->ctstimeout
= us
;
1236 static bool ath9k_hw_set_global_txtimeout(struct ath_hw
*ah
, u32 tu
)
1239 ath_print(ath9k_hw_common(ah
), ATH_DBG_XMIT
,
1240 "bad global tx timeout %u\n", tu
);
1241 ah
->globaltxtimeout
= (u32
) -1;
1244 REG_RMW_FIELD(ah
, AR_GTXTO
, AR_GTXTO_TIMEOUT_LIMIT
, tu
);
1245 ah
->globaltxtimeout
= tu
;
1250 static void ath9k_hw_init_user_settings(struct ath_hw
*ah
)
1252 ath_print(ath9k_hw_common(ah
), ATH_DBG_RESET
, "ah->misc_mode 0x%x\n",
1255 if (ah
->misc_mode
!= 0)
1256 REG_WRITE(ah
, AR_PCU_MISC
,
1257 REG_READ(ah
, AR_PCU_MISC
) | ah
->misc_mode
);
1258 if (ah
->slottime
!= (u32
) -1)
1259 ath9k_hw_setslottime(ah
, ah
->slottime
);
1260 if (ah
->acktimeout
!= (u32
) -1)
1261 ath9k_hw_set_ack_timeout(ah
, ah
->acktimeout
);
1262 if (ah
->ctstimeout
!= (u32
) -1)
1263 ath9k_hw_set_cts_timeout(ah
, ah
->ctstimeout
);
1264 if (ah
->globaltxtimeout
!= (u32
) -1)
1265 ath9k_hw_set_global_txtimeout(ah
, ah
->globaltxtimeout
);
1268 const char *ath9k_hw_probe(u16 vendorid
, u16 devid
)
1270 return vendorid
== ATHEROS_VENDOR_ID
?
1271 ath9k_hw_devname(devid
) : NULL
;
1274 void ath9k_hw_detach(struct ath_hw
*ah
)
1276 struct ath_common
*common
= ath9k_hw_common(ah
);
1278 if (common
->state
<= ATH_HW_INITIALIZED
)
1281 if (!AR_SREV_9100(ah
))
1282 ath9k_hw_ani_disable(ah
);
1284 ath9k_hw_setpower(ah
, ATH9K_PM_FULL_SLEEP
);
1287 if (!AR_SREV_9280_10_OR_LATER(ah
))
1288 ath9k_hw_rf_free_ext_banks(ah
);
1292 EXPORT_SYMBOL(ath9k_hw_detach
);
1298 static void ath9k_hw_override_ini(struct ath_hw
*ah
,
1299 struct ath9k_channel
*chan
)
1303 if (AR_SREV_9271(ah
)) {
1305 * Enable spectral scan to solution for issues with stuck
1306 * beacons on AR9271 1.0. The beacon stuck issue is not seeon on
1309 if (AR_SREV_9271_10(ah
)) {
1310 val
= REG_READ(ah
, AR_PHY_SPECTRAL_SCAN
) |
1311 AR_PHY_SPECTRAL_SCAN_ENABLE
;
1312 REG_WRITE(ah
, AR_PHY_SPECTRAL_SCAN
, val
);
1314 else if (AR_SREV_9271_11(ah
))
1316 * change AR_PHY_RF_CTL3 setting to fix MAC issue
1317 * present on AR9271 1.1
1319 REG_WRITE(ah
, AR_PHY_RF_CTL3
, 0x3a020001);
1324 * Set the RX_ABORT and RX_DIS and clear if off only after
1325 * RXE is set for MAC. This prevents frames with corrupted
1326 * descriptor status.
1328 REG_SET_BIT(ah
, AR_DIAG_SW
, (AR_DIAG_RX_DIS
| AR_DIAG_RX_ABORT
));
1330 if (AR_SREV_9280_10_OR_LATER(ah
)) {
1331 val
= REG_READ(ah
, AR_PCU_MISC_MODE2
) &
1332 (~AR_PCU_MISC_MODE2_HWWAR1
);
1334 if (AR_SREV_9287_10_OR_LATER(ah
))
1335 val
= val
& (~AR_PCU_MISC_MODE2_HWWAR2
);
1337 REG_WRITE(ah
, AR_PCU_MISC_MODE2
, val
);
1340 if (!AR_SREV_5416_20_OR_LATER(ah
) ||
1341 AR_SREV_9280_10_OR_LATER(ah
))
1344 * Disable BB clock gating
1345 * Necessary to avoid issues on AR5416 2.0
1347 REG_WRITE(ah
, 0x9800 + (651 << 2), 0x11);
1350 static u32
ath9k_hw_def_ini_fixup(struct ath_hw
*ah
,
1351 struct ar5416_eeprom_def
*pEepData
,
1354 struct base_eep_header
*pBase
= &(pEepData
->baseEepHeader
);
1355 struct ath_common
*common
= ath9k_hw_common(ah
);
1357 switch (ah
->hw_version
.devid
) {
1358 case AR9280_DEVID_PCI
:
1359 if (reg
== 0x7894) {
1360 ath_print(common
, ATH_DBG_EEPROM
,
1361 "ini VAL: %x EEPROM: %x\n", value
,
1362 (pBase
->version
& 0xff));
1364 if ((pBase
->version
& 0xff) > 0x0a) {
1365 ath_print(common
, ATH_DBG_EEPROM
,
1368 value
&= ~AR_AN_TOP2_PWDCLKIND
;
1369 value
|= AR_AN_TOP2_PWDCLKIND
&
1370 (pBase
->pwdclkind
<< AR_AN_TOP2_PWDCLKIND_S
);
1372 ath_print(common
, ATH_DBG_EEPROM
,
1373 "PWDCLKIND Earlier Rev\n");
1376 ath_print(common
, ATH_DBG_EEPROM
,
1377 "final ini VAL: %x\n", value
);
1385 static u32
ath9k_hw_ini_fixup(struct ath_hw
*ah
,
1386 struct ar5416_eeprom_def
*pEepData
,
1389 if (ah
->eep_map
== EEP_MAP_4KBITS
)
1392 return ath9k_hw_def_ini_fixup(ah
, pEepData
, reg
, value
);
1395 static void ath9k_olc_init(struct ath_hw
*ah
)
1399 if (OLC_FOR_AR9287_10_LATER
) {
1400 REG_SET_BIT(ah
, AR_PHY_TX_PWRCTRL9
,
1401 AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL
);
1402 ath9k_hw_analog_shift_rmw(ah
, AR9287_AN_TXPC0
,
1403 AR9287_AN_TXPC0_TXPCMODE
,
1404 AR9287_AN_TXPC0_TXPCMODE_S
,
1405 AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE
);
1408 for (i
= 0; i
< AR9280_TX_GAIN_TABLE_SIZE
; i
++)
1409 ah
->originalGain
[i
] =
1410 MS(REG_READ(ah
, AR_PHY_TX_GAIN_TBL1
+ i
* 4),
1416 static u32
ath9k_regd_get_ctl(struct ath_regulatory
*reg
,
1417 struct ath9k_channel
*chan
)
1419 u32 ctl
= ath_regd_get_band_ctl(reg
, chan
->chan
->band
);
1421 if (IS_CHAN_B(chan
))
1423 else if (IS_CHAN_G(chan
))
1431 static int ath9k_hw_process_ini(struct ath_hw
*ah
,
1432 struct ath9k_channel
*chan
)
1434 struct ath_regulatory
*regulatory
= ath9k_hw_regulatory(ah
);
1435 int i
, regWrites
= 0;
1436 struct ieee80211_channel
*channel
= chan
->chan
;
1437 u32 modesIndex
, freqIndex
;
1439 switch (chan
->chanmode
) {
1441 case CHANNEL_A_HT20
:
1445 case CHANNEL_A_HT40PLUS
:
1446 case CHANNEL_A_HT40MINUS
:
1451 case CHANNEL_G_HT20
:
1456 case CHANNEL_G_HT40PLUS
:
1457 case CHANNEL_G_HT40MINUS
:
1466 REG_WRITE(ah
, AR_PHY(0), 0x00000007);
1467 REG_WRITE(ah
, AR_PHY_ADC_SERIAL_CTL
, AR_PHY_SEL_EXTERNAL_RADIO
);
1468 ah
->eep_ops
->set_addac(ah
, chan
);
1470 if (AR_SREV_5416_22_OR_LATER(ah
)) {
1471 REG_WRITE_ARRAY(&ah
->iniAddac
, 1, regWrites
);
1473 struct ar5416IniArray temp
;
1475 sizeof(u32
) * ah
->iniAddac
.ia_rows
*
1476 ah
->iniAddac
.ia_columns
;
1478 memcpy(ah
->addac5416_21
,
1479 ah
->iniAddac
.ia_array
, addacSize
);
1481 (ah
->addac5416_21
)[31 * ah
->iniAddac
.ia_columns
+ 1] = 0;
1483 temp
.ia_array
= ah
->addac5416_21
;
1484 temp
.ia_columns
= ah
->iniAddac
.ia_columns
;
1485 temp
.ia_rows
= ah
->iniAddac
.ia_rows
;
1486 REG_WRITE_ARRAY(&temp
, 1, regWrites
);
1489 REG_WRITE(ah
, AR_PHY_ADC_SERIAL_CTL
, AR_PHY_SEL_INTERNAL_ADDAC
);
1491 for (i
= 0; i
< ah
->iniModes
.ia_rows
; i
++) {
1492 u32 reg
= INI_RA(&ah
->iniModes
, i
, 0);
1493 u32 val
= INI_RA(&ah
->iniModes
, i
, modesIndex
);
1495 REG_WRITE(ah
, reg
, val
);
1497 if (reg
>= 0x7800 && reg
< 0x78a0
1498 && ah
->config
.analog_shiftreg
) {
1502 DO_DELAY(regWrites
);
1505 if (AR_SREV_9280(ah
) || AR_SREV_9287_10_OR_LATER(ah
))
1506 REG_WRITE_ARRAY(&ah
->iniModesRxGain
, modesIndex
, regWrites
);
1508 if (AR_SREV_9280(ah
) || AR_SREV_9285_12_OR_LATER(ah
) ||
1509 AR_SREV_9287_10_OR_LATER(ah
))
1510 REG_WRITE_ARRAY(&ah
->iniModesTxGain
, modesIndex
, regWrites
);
1512 for (i
= 0; i
< ah
->iniCommon
.ia_rows
; i
++) {
1513 u32 reg
= INI_RA(&ah
->iniCommon
, i
, 0);
1514 u32 val
= INI_RA(&ah
->iniCommon
, i
, 1);
1516 REG_WRITE(ah
, reg
, val
);
1518 if (reg
>= 0x7800 && reg
< 0x78a0
1519 && ah
->config
.analog_shiftreg
) {
1523 DO_DELAY(regWrites
);
1526 ath9k_hw_write_regs(ah
, freqIndex
, regWrites
);
1528 if (AR_SREV_9271_10(ah
))
1529 REG_WRITE_ARRAY(&ah
->iniModes_9271_1_0_only
,
1530 modesIndex
, regWrites
);
1532 if (AR_SREV_9280_20(ah
) && IS_CHAN_A_5MHZ_SPACED(chan
)) {
1533 REG_WRITE_ARRAY(&ah
->iniModesAdditional
, modesIndex
,
1537 ath9k_hw_override_ini(ah
, chan
);
1538 ath9k_hw_set_regs(ah
, chan
);
1539 ath9k_hw_init_chain_masks(ah
);
1541 if (OLC_FOR_AR9280_20_LATER
)
1544 ah
->eep_ops
->set_txpower(ah
, chan
,
1545 ath9k_regd_get_ctl(regulatory
, chan
),
1546 channel
->max_antenna_gain
* 2,
1547 channel
->max_power
* 2,
1548 min((u32
) MAX_RATE_POWER
,
1549 (u32
) regulatory
->power_limit
));
1551 if (!ath9k_hw_set_rf_regs(ah
, chan
, freqIndex
)) {
1552 ath_print(ath9k_hw_common(ah
), ATH_DBG_FATAL
,
1553 "ar5416SetRfRegs failed\n");
1560 /****************************************/
1561 /* Reset and Channel Switching Routines */
1562 /****************************************/
1564 static void ath9k_hw_set_rfmode(struct ath_hw
*ah
, struct ath9k_channel
*chan
)
1571 rfMode
|= (IS_CHAN_B(chan
) || IS_CHAN_G(chan
))
1572 ? AR_PHY_MODE_DYNAMIC
: AR_PHY_MODE_OFDM
;
1574 if (!AR_SREV_9280_10_OR_LATER(ah
))
1575 rfMode
|= (IS_CHAN_5GHZ(chan
)) ?
1576 AR_PHY_MODE_RF5GHZ
: AR_PHY_MODE_RF2GHZ
;
1578 if (AR_SREV_9280_20(ah
) && IS_CHAN_A_5MHZ_SPACED(chan
))
1579 rfMode
|= (AR_PHY_MODE_DYNAMIC
| AR_PHY_MODE_DYN_CCK_DISABLE
);
1581 REG_WRITE(ah
, AR_PHY_MODE
, rfMode
);
1584 static void ath9k_hw_mark_phy_inactive(struct ath_hw
*ah
)
1586 REG_WRITE(ah
, AR_PHY_ACTIVE
, AR_PHY_ACTIVE_DIS
);
1589 static inline void ath9k_hw_set_dma(struct ath_hw
*ah
)
1594 * set AHB_MODE not to do cacheline prefetches
1596 regval
= REG_READ(ah
, AR_AHB_MODE
);
1597 REG_WRITE(ah
, AR_AHB_MODE
, regval
| AR_AHB_PREFETCH_RD_EN
);
1600 * let mac dma reads be in 128 byte chunks
1602 regval
= REG_READ(ah
, AR_TXCFG
) & ~AR_TXCFG_DMASZ_MASK
;
1603 REG_WRITE(ah
, AR_TXCFG
, regval
| AR_TXCFG_DMASZ_128B
);
1606 * Restore TX Trigger Level to its pre-reset value.
1607 * The initial value depends on whether aggregation is enabled, and is
1608 * adjusted whenever underruns are detected.
1610 REG_RMW_FIELD(ah
, AR_TXCFG
, AR_FTRIG
, ah
->tx_trig_level
);
1613 * let mac dma writes be in 128 byte chunks
1615 regval
= REG_READ(ah
, AR_RXCFG
) & ~AR_RXCFG_DMASZ_MASK
;
1616 REG_WRITE(ah
, AR_RXCFG
, regval
| AR_RXCFG_DMASZ_128B
);
1619 * Setup receive FIFO threshold to hold off TX activities
1621 REG_WRITE(ah
, AR_RXFIFO_CFG
, 0x200);
1624 * reduce the number of usable entries in PCU TXBUF to avoid
1625 * wrap around issues.
1627 if (AR_SREV_9285(ah
)) {
1628 /* For AR9285 the number of Fifos are reduced to half.
1629 * So set the usable tx buf size also to half to
1630 * avoid data/delimiter underruns
1632 REG_WRITE(ah
, AR_PCU_TXBUF_CTRL
,
1633 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE
);
1634 } else if (!AR_SREV_9271(ah
)) {
1635 REG_WRITE(ah
, AR_PCU_TXBUF_CTRL
,
1636 AR_PCU_TXBUF_CTRL_USABLE_SIZE
);
1640 static void ath9k_hw_set_operating_mode(struct ath_hw
*ah
, int opmode
)
1644 val
= REG_READ(ah
, AR_STA_ID1
);
1645 val
&= ~(AR_STA_ID1_STA_AP
| AR_STA_ID1_ADHOC
);
1647 case NL80211_IFTYPE_AP
:
1648 REG_WRITE(ah
, AR_STA_ID1
, val
| AR_STA_ID1_STA_AP
1649 | AR_STA_ID1_KSRCH_MODE
);
1650 REG_CLR_BIT(ah
, AR_CFG
, AR_CFG_AP_ADHOC_INDICATION
);
1652 case NL80211_IFTYPE_ADHOC
:
1653 case NL80211_IFTYPE_MESH_POINT
:
1654 REG_WRITE(ah
, AR_STA_ID1
, val
| AR_STA_ID1_ADHOC
1655 | AR_STA_ID1_KSRCH_MODE
);
1656 REG_SET_BIT(ah
, AR_CFG
, AR_CFG_AP_ADHOC_INDICATION
);
1658 case NL80211_IFTYPE_STATION
:
1659 case NL80211_IFTYPE_MONITOR
:
1660 REG_WRITE(ah
, AR_STA_ID1
, val
| AR_STA_ID1_KSRCH_MODE
);
1665 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw
*ah
,
1670 u32 coef_exp
, coef_man
;
1672 for (coef_exp
= 31; coef_exp
> 0; coef_exp
--)
1673 if ((coef_scaled
>> coef_exp
) & 0x1)
1676 coef_exp
= 14 - (coef_exp
- COEF_SCALE_S
);
1678 coef_man
= coef_scaled
+ (1 << (COEF_SCALE_S
- coef_exp
- 1));
1680 *coef_mantissa
= coef_man
>> (COEF_SCALE_S
- coef_exp
);
1681 *coef_exponent
= coef_exp
- 16;
1684 static void ath9k_hw_set_delta_slope(struct ath_hw
*ah
,
1685 struct ath9k_channel
*chan
)
1687 u32 coef_scaled
, ds_coef_exp
, ds_coef_man
;
1688 u32 clockMhzScaled
= 0x64000000;
1689 struct chan_centers centers
;
1691 if (IS_CHAN_HALF_RATE(chan
))
1692 clockMhzScaled
= clockMhzScaled
>> 1;
1693 else if (IS_CHAN_QUARTER_RATE(chan
))
1694 clockMhzScaled
= clockMhzScaled
>> 2;
1696 ath9k_hw_get_channel_centers(ah
, chan
, ¢ers
);
1697 coef_scaled
= clockMhzScaled
/ centers
.synth_center
;
1699 ath9k_hw_get_delta_slope_vals(ah
, coef_scaled
, &ds_coef_man
,
1702 REG_RMW_FIELD(ah
, AR_PHY_TIMING3
,
1703 AR_PHY_TIMING3_DSC_MAN
, ds_coef_man
);
1704 REG_RMW_FIELD(ah
, AR_PHY_TIMING3
,
1705 AR_PHY_TIMING3_DSC_EXP
, ds_coef_exp
);
1707 coef_scaled
= (9 * coef_scaled
) / 10;
1709 ath9k_hw_get_delta_slope_vals(ah
, coef_scaled
, &ds_coef_man
,
1712 REG_RMW_FIELD(ah
, AR_PHY_HALFGI
,
1713 AR_PHY_HALFGI_DSC_MAN
, ds_coef_man
);
1714 REG_RMW_FIELD(ah
, AR_PHY_HALFGI
,
1715 AR_PHY_HALFGI_DSC_EXP
, ds_coef_exp
);
1718 static bool ath9k_hw_set_reset(struct ath_hw
*ah
, int type
)
1723 if (AR_SREV_9100(ah
)) {
1724 u32 val
= REG_READ(ah
, AR_RTC_DERIVED_CLK
);
1725 val
&= ~AR_RTC_DERIVED_CLK_PERIOD
;
1726 val
|= SM(1, AR_RTC_DERIVED_CLK_PERIOD
);
1727 REG_WRITE(ah
, AR_RTC_DERIVED_CLK
, val
);
1728 (void)REG_READ(ah
, AR_RTC_DERIVED_CLK
);
1731 REG_WRITE(ah
, AR_RTC_FORCE_WAKE
, AR_RTC_FORCE_WAKE_EN
|
1732 AR_RTC_FORCE_WAKE_ON_INT
);
1734 if (AR_SREV_9100(ah
)) {
1735 rst_flags
= AR_RTC_RC_MAC_WARM
| AR_RTC_RC_MAC_COLD
|
1736 AR_RTC_RC_COLD_RESET
| AR_RTC_RC_WARM_RESET
;
1738 tmpReg
= REG_READ(ah
, AR_INTR_SYNC_CAUSE
);
1740 (AR_INTR_SYNC_LOCAL_TIMEOUT
|
1741 AR_INTR_SYNC_RADM_CPL_TIMEOUT
)) {
1742 REG_WRITE(ah
, AR_INTR_SYNC_ENABLE
, 0);
1743 REG_WRITE(ah
, AR_RC
, AR_RC_AHB
| AR_RC_HOSTIF
);
1745 REG_WRITE(ah
, AR_RC
, AR_RC_AHB
);
1748 rst_flags
= AR_RTC_RC_MAC_WARM
;
1749 if (type
== ATH9K_RESET_COLD
)
1750 rst_flags
|= AR_RTC_RC_MAC_COLD
;
1753 REG_WRITE(ah
, AR_RTC_RC
, rst_flags
);
1756 REG_WRITE(ah
, AR_RTC_RC
, 0);
1757 if (!ath9k_hw_wait(ah
, AR_RTC_RC
, AR_RTC_RC_M
, 0, AH_WAIT_TIMEOUT
)) {
1758 ath_print(ath9k_hw_common(ah
), ATH_DBG_RESET
,
1759 "RTC stuck in MAC reset\n");
1763 if (!AR_SREV_9100(ah
))
1764 REG_WRITE(ah
, AR_RC
, 0);
1766 if (AR_SREV_9100(ah
))
1772 static bool ath9k_hw_set_reset_power_on(struct ath_hw
*ah
)
1774 REG_WRITE(ah
, AR_RTC_FORCE_WAKE
, AR_RTC_FORCE_WAKE_EN
|
1775 AR_RTC_FORCE_WAKE_ON_INT
);
1777 if (!AR_SREV_9100(ah
))
1778 REG_WRITE(ah
, AR_RC
, AR_RC_AHB
);
1780 REG_WRITE(ah
, AR_RTC_RESET
, 0);
1783 if (!AR_SREV_9100(ah
))
1784 REG_WRITE(ah
, AR_RC
, 0);
1786 REG_WRITE(ah
, AR_RTC_RESET
, 1);
1788 if (!ath9k_hw_wait(ah
,
1793 ath_print(ath9k_hw_common(ah
), ATH_DBG_RESET
,
1794 "RTC not waking up\n");
1798 ath9k_hw_read_revisions(ah
);
1800 return ath9k_hw_set_reset(ah
, ATH9K_RESET_WARM
);
1803 static bool ath9k_hw_set_reset_reg(struct ath_hw
*ah
, u32 type
)
1805 REG_WRITE(ah
, AR_RTC_FORCE_WAKE
,
1806 AR_RTC_FORCE_WAKE_EN
| AR_RTC_FORCE_WAKE_ON_INT
);
1809 case ATH9K_RESET_POWER_ON
:
1810 return ath9k_hw_set_reset_power_on(ah
);
1811 case ATH9K_RESET_WARM
:
1812 case ATH9K_RESET_COLD
:
1813 return ath9k_hw_set_reset(ah
, type
);
1819 static void ath9k_hw_set_regs(struct ath_hw
*ah
, struct ath9k_channel
*chan
)
1822 u32 enableDacFifo
= 0;
1824 if (AR_SREV_9285_10_OR_LATER(ah
))
1825 enableDacFifo
= (REG_READ(ah
, AR_PHY_TURBO
) &
1826 AR_PHY_FC_ENABLE_DAC_FIFO
);
1828 phymode
= AR_PHY_FC_HT_EN
| AR_PHY_FC_SHORT_GI_40
1829 | AR_PHY_FC_SINGLE_HT_LTF1
| AR_PHY_FC_WALSH
| enableDacFifo
;
1831 if (IS_CHAN_HT40(chan
)) {
1832 phymode
|= AR_PHY_FC_DYN2040_EN
;
1834 if ((chan
->chanmode
== CHANNEL_A_HT40PLUS
) ||
1835 (chan
->chanmode
== CHANNEL_G_HT40PLUS
))
1836 phymode
|= AR_PHY_FC_DYN2040_PRI_CH
;
1839 REG_WRITE(ah
, AR_PHY_TURBO
, phymode
);
1841 ath9k_hw_set11nmac2040(ah
);
1843 REG_WRITE(ah
, AR_GTXTO
, 25 << AR_GTXTO_TIMEOUT_LIMIT_S
);
1844 REG_WRITE(ah
, AR_CST
, 0xF << AR_CST_TIMEOUT_LIMIT_S
);
1847 static bool ath9k_hw_chip_reset(struct ath_hw
*ah
,
1848 struct ath9k_channel
*chan
)
1850 if (AR_SREV_9280(ah
) && ah
->eep_ops
->get_eeprom(ah
, EEP_OL_PWRCTRL
)) {
1851 if (!ath9k_hw_set_reset_reg(ah
, ATH9K_RESET_POWER_ON
))
1853 } else if (!ath9k_hw_set_reset_reg(ah
, ATH9K_RESET_WARM
))
1856 if (!ath9k_hw_setpower(ah
, ATH9K_PM_AWAKE
))
1859 ah
->chip_fullsleep
= false;
1860 ath9k_hw_init_pll(ah
, chan
);
1861 ath9k_hw_set_rfmode(ah
, chan
);
1866 static bool ath9k_hw_channel_change(struct ath_hw
*ah
,
1867 struct ath9k_channel
*chan
)
1869 struct ath_regulatory
*regulatory
= ath9k_hw_regulatory(ah
);
1870 struct ath_common
*common
= ath9k_hw_common(ah
);
1871 struct ieee80211_channel
*channel
= chan
->chan
;
1872 u32 synthDelay
, qnum
;
1875 for (qnum
= 0; qnum
< AR_NUM_QCU
; qnum
++) {
1876 if (ath9k_hw_numtxpending(ah
, qnum
)) {
1877 ath_print(common
, ATH_DBG_QUEUE
,
1878 "Transmit frames pending on "
1879 "queue %d\n", qnum
);
1884 REG_WRITE(ah
, AR_PHY_RFBUS_REQ
, AR_PHY_RFBUS_REQ_EN
);
1885 if (!ath9k_hw_wait(ah
, AR_PHY_RFBUS_GRANT
, AR_PHY_RFBUS_GRANT_EN
,
1886 AR_PHY_RFBUS_GRANT_EN
, AH_WAIT_TIMEOUT
)) {
1887 ath_print(common
, ATH_DBG_FATAL
,
1888 "Could not kill baseband RX\n");
1892 ath9k_hw_set_regs(ah
, chan
);
1894 r
= ah
->ath9k_hw_rf_set_freq(ah
, chan
);
1896 ath_print(common
, ATH_DBG_FATAL
,
1897 "Failed to set channel\n");
1901 ah
->eep_ops
->set_txpower(ah
, chan
,
1902 ath9k_regd_get_ctl(regulatory
, chan
),
1903 channel
->max_antenna_gain
* 2,
1904 channel
->max_power
* 2,
1905 min((u32
) MAX_RATE_POWER
,
1906 (u32
) regulatory
->power_limit
));
1908 synthDelay
= REG_READ(ah
, AR_PHY_RX_DELAY
) & AR_PHY_RX_DELAY_DELAY
;
1909 if (IS_CHAN_B(chan
))
1910 synthDelay
= (4 * synthDelay
) / 22;
1914 udelay(synthDelay
+ BASE_ACTIVATE_DELAY
);
1916 REG_WRITE(ah
, AR_PHY_RFBUS_REQ
, 0);
1918 if (IS_CHAN_OFDM(chan
) || IS_CHAN_HT(chan
))
1919 ath9k_hw_set_delta_slope(ah
, chan
);
1921 ah
->ath9k_hw_spur_mitigate_freq(ah
, chan
);
1923 if (!chan
->oneTimeCalsDone
)
1924 chan
->oneTimeCalsDone
= true;
1929 static void ath9k_enable_rfkill(struct ath_hw
*ah
)
1931 REG_SET_BIT(ah
, AR_GPIO_INPUT_EN_VAL
,
1932 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB
);
1934 REG_CLR_BIT(ah
, AR_GPIO_INPUT_MUX2
,
1935 AR_GPIO_INPUT_MUX2_RFSILENT
);
1937 ath9k_hw_cfg_gpio_input(ah
, ah
->rfkill_gpio
);
1938 REG_SET_BIT(ah
, AR_PHY_TEST
, RFSILENT_BB
);
1941 int ath9k_hw_reset(struct ath_hw
*ah
, struct ath9k_channel
*chan
,
1942 bool bChannelChange
)
1944 struct ath_common
*common
= ath9k_hw_common(ah
);
1946 struct ath9k_channel
*curchan
= ah
->curchan
;
1950 int i
, rx_chainmask
, r
;
1952 ah
->txchainmask
= common
->tx_chainmask
;
1953 ah
->rxchainmask
= common
->rx_chainmask
;
1955 if (!ath9k_hw_setpower(ah
, ATH9K_PM_AWAKE
))
1958 if (curchan
&& !ah
->chip_fullsleep
)
1959 ath9k_hw_getnf(ah
, curchan
);
1961 if (bChannelChange
&&
1962 (ah
->chip_fullsleep
!= true) &&
1963 (ah
->curchan
!= NULL
) &&
1964 (chan
->channel
!= ah
->curchan
->channel
) &&
1965 ((chan
->channelFlags
& CHANNEL_ALL
) ==
1966 (ah
->curchan
->channelFlags
& CHANNEL_ALL
)) &&
1967 !(AR_SREV_9280(ah
) || IS_CHAN_A_5MHZ_SPACED(chan
) ||
1968 IS_CHAN_A_5MHZ_SPACED(ah
->curchan
))) {
1970 if (ath9k_hw_channel_change(ah
, chan
)) {
1971 ath9k_hw_loadnf(ah
, ah
->curchan
);
1972 ath9k_hw_start_nfcal(ah
);
1977 saveDefAntenna
= REG_READ(ah
, AR_DEF_ANTENNA
);
1978 if (saveDefAntenna
== 0)
1981 macStaId1
= REG_READ(ah
, AR_STA_ID1
) & AR_STA_ID1_BASE_RATE_11B
;
1983 /* For chips on which RTC reset is done, save TSF before it gets cleared */
1984 if (AR_SREV_9280(ah
) && ah
->eep_ops
->get_eeprom(ah
, EEP_OL_PWRCTRL
))
1985 tsf
= ath9k_hw_gettsf64(ah
);
1987 saveLedState
= REG_READ(ah
, AR_CFG_LED
) &
1988 (AR_CFG_LED_ASSOC_CTL
| AR_CFG_LED_MODE_SEL
|
1989 AR_CFG_LED_BLINK_THRESH_SEL
| AR_CFG_LED_BLINK_SLOW
);
1991 ath9k_hw_mark_phy_inactive(ah
);
1993 if (AR_SREV_9271(ah
) && ah
->htc_reset_init
) {
1995 AR9271_RESET_POWER_DOWN_CONTROL
,
1996 AR9271_RADIO_RF_RST
);
2000 if (!ath9k_hw_chip_reset(ah
, chan
)) {
2001 ath_print(common
, ATH_DBG_FATAL
, "Chip reset failed\n");
2005 if (AR_SREV_9271(ah
) && ah
->htc_reset_init
) {
2006 ah
->htc_reset_init
= false;
2008 AR9271_RESET_POWER_DOWN_CONTROL
,
2009 AR9271_GATE_MAC_CTL
);
2014 if (tsf
&& AR_SREV_9280(ah
) && ah
->eep_ops
->get_eeprom(ah
, EEP_OL_PWRCTRL
))
2015 ath9k_hw_settsf64(ah
, tsf
);
2017 if (AR_SREV_9280_10_OR_LATER(ah
))
2018 REG_SET_BIT(ah
, AR_GPIO_INPUT_EN_VAL
, AR_GPIO_JTAG_DISABLE
);
2020 if (AR_SREV_9287_12_OR_LATER(ah
)) {
2021 /* Enable ASYNC FIFO */
2022 REG_SET_BIT(ah
, AR_MAC_PCU_ASYNC_FIFO_REG3
,
2023 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL
);
2024 REG_SET_BIT(ah
, AR_PHY_MODE
, AR_PHY_MODE_ASYNCFIFO
);
2025 REG_CLR_BIT(ah
, AR_MAC_PCU_ASYNC_FIFO_REG3
,
2026 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET
);
2027 REG_SET_BIT(ah
, AR_MAC_PCU_ASYNC_FIFO_REG3
,
2028 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET
);
2030 r
= ath9k_hw_process_ini(ah
, chan
);
2034 /* Setup MFP options for CCMP */
2035 if (AR_SREV_9280_20_OR_LATER(ah
)) {
2036 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
2037 * frames when constructing CCMP AAD. */
2038 REG_RMW_FIELD(ah
, AR_AES_MUTE_MASK1
, AR_AES_MUTE_MASK1_FC_MGMT
,
2040 ah
->sw_mgmt_crypto
= false;
2041 } else if (AR_SREV_9160_10_OR_LATER(ah
)) {
2042 /* Disable hardware crypto for management frames */
2043 REG_CLR_BIT(ah
, AR_PCU_MISC_MODE2
,
2044 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE
);
2045 REG_SET_BIT(ah
, AR_PCU_MISC_MODE2
,
2046 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT
);
2047 ah
->sw_mgmt_crypto
= true;
2049 ah
->sw_mgmt_crypto
= true;
2051 if (IS_CHAN_OFDM(chan
) || IS_CHAN_HT(chan
))
2052 ath9k_hw_set_delta_slope(ah
, chan
);
2054 ah
->ath9k_hw_spur_mitigate_freq(ah
, chan
);
2055 ah
->eep_ops
->set_board_values(ah
, chan
);
2057 REG_WRITE(ah
, AR_STA_ID0
, get_unaligned_le32(common
->macaddr
));
2058 REG_WRITE(ah
, AR_STA_ID1
, get_unaligned_le16(common
->macaddr
+ 4)
2060 | AR_STA_ID1_RTS_USE_DEF
2062 ack_6mb
? AR_STA_ID1_ACKCTS_6MB
: 0)
2063 | ah
->sta_id1_defaults
);
2064 ath9k_hw_set_operating_mode(ah
, ah
->opmode
);
2066 ath_hw_setbssidmask(common
);
2068 REG_WRITE(ah
, AR_DEF_ANTENNA
, saveDefAntenna
);
2070 ath9k_hw_write_associd(ah
);
2072 REG_WRITE(ah
, AR_ISR
, ~0);
2074 REG_WRITE(ah
, AR_RSSI_THR
, INIT_RSSI_THR
);
2076 r
= ah
->ath9k_hw_rf_set_freq(ah
, chan
);
2080 for (i
= 0; i
< AR_NUM_DCU
; i
++)
2081 REG_WRITE(ah
, AR_DQCUMASK(i
), 1 << i
);
2084 for (i
= 0; i
< ah
->caps
.total_queues
; i
++)
2085 ath9k_hw_resettxqueue(ah
, i
);
2087 ath9k_hw_init_interrupt_masks(ah
, ah
->opmode
);
2088 ath9k_hw_init_qos(ah
);
2090 if (ah
->caps
.hw_caps
& ATH9K_HW_CAP_RFSILENT
)
2091 ath9k_enable_rfkill(ah
);
2093 ath9k_hw_init_user_settings(ah
);
2095 if (AR_SREV_9287_12_OR_LATER(ah
)) {
2096 REG_WRITE(ah
, AR_D_GBL_IFS_SIFS
,
2097 AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR
);
2098 REG_WRITE(ah
, AR_D_GBL_IFS_SLOT
,
2099 AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR
);
2100 REG_WRITE(ah
, AR_D_GBL_IFS_EIFS
,
2101 AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR
);
2103 REG_WRITE(ah
, AR_TIME_OUT
, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR
);
2104 REG_WRITE(ah
, AR_USEC
, AR_USEC_ASYNC_FIFO_DUR
);
2106 REG_SET_BIT(ah
, AR_MAC_PCU_LOGIC_ANALYZER
,
2107 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768
);
2108 REG_RMW_FIELD(ah
, AR_AHB_MODE
, AR_AHB_CUSTOM_BURST_EN
,
2109 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL
);
2111 if (AR_SREV_9287_12_OR_LATER(ah
)) {
2112 REG_SET_BIT(ah
, AR_PCU_MISC_MODE2
,
2113 AR_PCU_MISC_MODE2_ENABLE_AGGWEP
);
2116 REG_WRITE(ah
, AR_STA_ID1
,
2117 REG_READ(ah
, AR_STA_ID1
) | AR_STA_ID1_PRESERVE_SEQNUM
);
2119 ath9k_hw_set_dma(ah
);
2121 REG_WRITE(ah
, AR_OBS
, 8);
2123 if (ah
->config
.intr_mitigation
) {
2124 REG_RMW_FIELD(ah
, AR_RIMT
, AR_RIMT_LAST
, 500);
2125 REG_RMW_FIELD(ah
, AR_RIMT
, AR_RIMT_FIRST
, 2000);
2128 ath9k_hw_init_bb(ah
, chan
);
2130 if (!ath9k_hw_init_cal(ah
, chan
))
2133 rx_chainmask
= ah
->rxchainmask
;
2134 if ((rx_chainmask
== 0x5) || (rx_chainmask
== 0x3)) {
2135 REG_WRITE(ah
, AR_PHY_RX_CHAINMASK
, rx_chainmask
);
2136 REG_WRITE(ah
, AR_PHY_CAL_CHAINMASK
, rx_chainmask
);
2139 REG_WRITE(ah
, AR_CFG_LED
, saveLedState
| AR_CFG_SCLK_32KHZ
);
2142 * For big endian systems turn on swapping for descriptors
2144 if (AR_SREV_9100(ah
)) {
2146 mask
= REG_READ(ah
, AR_CFG
);
2147 if (mask
& (AR_CFG_SWRB
| AR_CFG_SWTB
| AR_CFG_SWRG
)) {
2148 ath_print(common
, ATH_DBG_RESET
,
2149 "CFG Byte Swap Set 0x%x\n", mask
);
2152 INIT_CONFIG_STATUS
| AR_CFG_SWRB
| AR_CFG_SWTB
;
2153 REG_WRITE(ah
, AR_CFG
, mask
);
2154 ath_print(common
, ATH_DBG_RESET
,
2155 "Setting CFG 0x%x\n", REG_READ(ah
, AR_CFG
));
2158 /* Configure AR9271 target WLAN */
2159 if (AR_SREV_9271(ah
))
2160 REG_WRITE(ah
, AR_CFG
, AR_CFG_SWRB
| AR_CFG_SWTB
);
2163 REG_WRITE(ah
, AR_CFG
, AR_CFG_SWTD
| AR_CFG_SWRD
);
2167 if (ah
->btcoex_hw
.enabled
)
2168 ath9k_hw_btcoex_enable(ah
);
2172 EXPORT_SYMBOL(ath9k_hw_reset
);
2174 /************************/
2175 /* Key Cache Management */
2176 /************************/
2178 bool ath9k_hw_keyreset(struct ath_hw
*ah
, u16 entry
)
2182 if (entry
>= ah
->caps
.keycache_size
) {
2183 ath_print(ath9k_hw_common(ah
), ATH_DBG_FATAL
,
2184 "keychache entry %u out of range\n", entry
);
2188 keyType
= REG_READ(ah
, AR_KEYTABLE_TYPE(entry
));
2190 REG_WRITE(ah
, AR_KEYTABLE_KEY0(entry
), 0);
2191 REG_WRITE(ah
, AR_KEYTABLE_KEY1(entry
), 0);
2192 REG_WRITE(ah
, AR_KEYTABLE_KEY2(entry
), 0);
2193 REG_WRITE(ah
, AR_KEYTABLE_KEY3(entry
), 0);
2194 REG_WRITE(ah
, AR_KEYTABLE_KEY4(entry
), 0);
2195 REG_WRITE(ah
, AR_KEYTABLE_TYPE(entry
), AR_KEYTABLE_TYPE_CLR
);
2196 REG_WRITE(ah
, AR_KEYTABLE_MAC0(entry
), 0);
2197 REG_WRITE(ah
, AR_KEYTABLE_MAC1(entry
), 0);
2199 if (keyType
== AR_KEYTABLE_TYPE_TKIP
&& ATH9K_IS_MIC_ENABLED(ah
)) {
2200 u16 micentry
= entry
+ 64;
2202 REG_WRITE(ah
, AR_KEYTABLE_KEY0(micentry
), 0);
2203 REG_WRITE(ah
, AR_KEYTABLE_KEY1(micentry
), 0);
2204 REG_WRITE(ah
, AR_KEYTABLE_KEY2(micentry
), 0);
2205 REG_WRITE(ah
, AR_KEYTABLE_KEY3(micentry
), 0);
2211 EXPORT_SYMBOL(ath9k_hw_keyreset
);
2213 bool ath9k_hw_keysetmac(struct ath_hw
*ah
, u16 entry
, const u8
*mac
)
2217 if (entry
>= ah
->caps
.keycache_size
) {
2218 ath_print(ath9k_hw_common(ah
), ATH_DBG_FATAL
,
2219 "keychache entry %u out of range\n", entry
);
2224 macHi
= (mac
[5] << 8) | mac
[4];
2225 macLo
= (mac
[3] << 24) |
2230 macLo
|= (macHi
& 1) << 31;
2235 REG_WRITE(ah
, AR_KEYTABLE_MAC0(entry
), macLo
);
2236 REG_WRITE(ah
, AR_KEYTABLE_MAC1(entry
), macHi
| AR_KEYTABLE_VALID
);
2240 EXPORT_SYMBOL(ath9k_hw_keysetmac
);
2242 bool ath9k_hw_set_keycache_entry(struct ath_hw
*ah
, u16 entry
,
2243 const struct ath9k_keyval
*k
,
2246 const struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
2247 struct ath_common
*common
= ath9k_hw_common(ah
);
2248 u32 key0
, key1
, key2
, key3
, key4
;
2251 if (entry
>= pCap
->keycache_size
) {
2252 ath_print(common
, ATH_DBG_FATAL
,
2253 "keycache entry %u out of range\n", entry
);
2257 switch (k
->kv_type
) {
2258 case ATH9K_CIPHER_AES_OCB
:
2259 keyType
= AR_KEYTABLE_TYPE_AES
;
2261 case ATH9K_CIPHER_AES_CCM
:
2262 if (!(pCap
->hw_caps
& ATH9K_HW_CAP_CIPHER_AESCCM
)) {
2263 ath_print(common
, ATH_DBG_ANY
,
2264 "AES-CCM not supported by mac rev 0x%x\n",
2265 ah
->hw_version
.macRev
);
2268 keyType
= AR_KEYTABLE_TYPE_CCM
;
2270 case ATH9K_CIPHER_TKIP
:
2271 keyType
= AR_KEYTABLE_TYPE_TKIP
;
2272 if (ATH9K_IS_MIC_ENABLED(ah
)
2273 && entry
+ 64 >= pCap
->keycache_size
) {
2274 ath_print(common
, ATH_DBG_ANY
,
2275 "entry %u inappropriate for TKIP\n", entry
);
2279 case ATH9K_CIPHER_WEP
:
2280 if (k
->kv_len
< WLAN_KEY_LEN_WEP40
) {
2281 ath_print(common
, ATH_DBG_ANY
,
2282 "WEP key length %u too small\n", k
->kv_len
);
2285 if (k
->kv_len
<= WLAN_KEY_LEN_WEP40
)
2286 keyType
= AR_KEYTABLE_TYPE_40
;
2287 else if (k
->kv_len
<= WLAN_KEY_LEN_WEP104
)
2288 keyType
= AR_KEYTABLE_TYPE_104
;
2290 keyType
= AR_KEYTABLE_TYPE_128
;
2292 case ATH9K_CIPHER_CLR
:
2293 keyType
= AR_KEYTABLE_TYPE_CLR
;
2296 ath_print(common
, ATH_DBG_FATAL
,
2297 "cipher %u not supported\n", k
->kv_type
);
2301 key0
= get_unaligned_le32(k
->kv_val
+ 0);
2302 key1
= get_unaligned_le16(k
->kv_val
+ 4);
2303 key2
= get_unaligned_le32(k
->kv_val
+ 6);
2304 key3
= get_unaligned_le16(k
->kv_val
+ 10);
2305 key4
= get_unaligned_le32(k
->kv_val
+ 12);
2306 if (k
->kv_len
<= WLAN_KEY_LEN_WEP104
)
2310 * Note: Key cache registers access special memory area that requires
2311 * two 32-bit writes to actually update the values in the internal
2312 * memory. Consequently, the exact order and pairs used here must be
2316 if (keyType
== AR_KEYTABLE_TYPE_TKIP
&& ATH9K_IS_MIC_ENABLED(ah
)) {
2317 u16 micentry
= entry
+ 64;
2320 * Write inverted key[47:0] first to avoid Michael MIC errors
2321 * on frames that could be sent or received at the same time.
2322 * The correct key will be written in the end once everything
2325 REG_WRITE(ah
, AR_KEYTABLE_KEY0(entry
), ~key0
);
2326 REG_WRITE(ah
, AR_KEYTABLE_KEY1(entry
), ~key1
);
2328 /* Write key[95:48] */
2329 REG_WRITE(ah
, AR_KEYTABLE_KEY2(entry
), key2
);
2330 REG_WRITE(ah
, AR_KEYTABLE_KEY3(entry
), key3
);
2332 /* Write key[127:96] and key type */
2333 REG_WRITE(ah
, AR_KEYTABLE_KEY4(entry
), key4
);
2334 REG_WRITE(ah
, AR_KEYTABLE_TYPE(entry
), keyType
);
2336 /* Write MAC address for the entry */
2337 (void) ath9k_hw_keysetmac(ah
, entry
, mac
);
2339 if (ah
->misc_mode
& AR_PCU_MIC_NEW_LOC_ENA
) {
2341 * TKIP uses two key cache entries:
2342 * Michael MIC TX/RX keys in the same key cache entry
2343 * (idx = main index + 64):
2344 * key0 [31:0] = RX key [31:0]
2345 * key1 [15:0] = TX key [31:16]
2346 * key1 [31:16] = reserved
2347 * key2 [31:0] = RX key [63:32]
2348 * key3 [15:0] = TX key [15:0]
2349 * key3 [31:16] = reserved
2350 * key4 [31:0] = TX key [63:32]
2352 u32 mic0
, mic1
, mic2
, mic3
, mic4
;
2354 mic0
= get_unaligned_le32(k
->kv_mic
+ 0);
2355 mic2
= get_unaligned_le32(k
->kv_mic
+ 4);
2356 mic1
= get_unaligned_le16(k
->kv_txmic
+ 2) & 0xffff;
2357 mic3
= get_unaligned_le16(k
->kv_txmic
+ 0) & 0xffff;
2358 mic4
= get_unaligned_le32(k
->kv_txmic
+ 4);
2360 /* Write RX[31:0] and TX[31:16] */
2361 REG_WRITE(ah
, AR_KEYTABLE_KEY0(micentry
), mic0
);
2362 REG_WRITE(ah
, AR_KEYTABLE_KEY1(micentry
), mic1
);
2364 /* Write RX[63:32] and TX[15:0] */
2365 REG_WRITE(ah
, AR_KEYTABLE_KEY2(micentry
), mic2
);
2366 REG_WRITE(ah
, AR_KEYTABLE_KEY3(micentry
), mic3
);
2368 /* Write TX[63:32] and keyType(reserved) */
2369 REG_WRITE(ah
, AR_KEYTABLE_KEY4(micentry
), mic4
);
2370 REG_WRITE(ah
, AR_KEYTABLE_TYPE(micentry
),
2371 AR_KEYTABLE_TYPE_CLR
);
2375 * TKIP uses four key cache entries (two for group
2377 * Michael MIC TX/RX keys are in different key cache
2378 * entries (idx = main index + 64 for TX and
2379 * main index + 32 + 96 for RX):
2380 * key0 [31:0] = TX/RX MIC key [31:0]
2381 * key1 [31:0] = reserved
2382 * key2 [31:0] = TX/RX MIC key [63:32]
2383 * key3 [31:0] = reserved
2384 * key4 [31:0] = reserved
2386 * Upper layer code will call this function separately
2387 * for TX and RX keys when these registers offsets are
2392 mic0
= get_unaligned_le32(k
->kv_mic
+ 0);
2393 mic2
= get_unaligned_le32(k
->kv_mic
+ 4);
2395 /* Write MIC key[31:0] */
2396 REG_WRITE(ah
, AR_KEYTABLE_KEY0(micentry
), mic0
);
2397 REG_WRITE(ah
, AR_KEYTABLE_KEY1(micentry
), 0);
2399 /* Write MIC key[63:32] */
2400 REG_WRITE(ah
, AR_KEYTABLE_KEY2(micentry
), mic2
);
2401 REG_WRITE(ah
, AR_KEYTABLE_KEY3(micentry
), 0);
2403 /* Write TX[63:32] and keyType(reserved) */
2404 REG_WRITE(ah
, AR_KEYTABLE_KEY4(micentry
), 0);
2405 REG_WRITE(ah
, AR_KEYTABLE_TYPE(micentry
),
2406 AR_KEYTABLE_TYPE_CLR
);
2409 /* MAC address registers are reserved for the MIC entry */
2410 REG_WRITE(ah
, AR_KEYTABLE_MAC0(micentry
), 0);
2411 REG_WRITE(ah
, AR_KEYTABLE_MAC1(micentry
), 0);
2414 * Write the correct (un-inverted) key[47:0] last to enable
2415 * TKIP now that all other registers are set with correct
2418 REG_WRITE(ah
, AR_KEYTABLE_KEY0(entry
), key0
);
2419 REG_WRITE(ah
, AR_KEYTABLE_KEY1(entry
), key1
);
2421 /* Write key[47:0] */
2422 REG_WRITE(ah
, AR_KEYTABLE_KEY0(entry
), key0
);
2423 REG_WRITE(ah
, AR_KEYTABLE_KEY1(entry
), key1
);
2425 /* Write key[95:48] */
2426 REG_WRITE(ah
, AR_KEYTABLE_KEY2(entry
), key2
);
2427 REG_WRITE(ah
, AR_KEYTABLE_KEY3(entry
), key3
);
2429 /* Write key[127:96] and key type */
2430 REG_WRITE(ah
, AR_KEYTABLE_KEY4(entry
), key4
);
2431 REG_WRITE(ah
, AR_KEYTABLE_TYPE(entry
), keyType
);
2433 /* Write MAC address for the entry */
2434 (void) ath9k_hw_keysetmac(ah
, entry
, mac
);
2439 EXPORT_SYMBOL(ath9k_hw_set_keycache_entry
);
2441 bool ath9k_hw_keyisvalid(struct ath_hw
*ah
, u16 entry
)
2443 if (entry
< ah
->caps
.keycache_size
) {
2444 u32 val
= REG_READ(ah
, AR_KEYTABLE_MAC1(entry
));
2445 if (val
& AR_KEYTABLE_VALID
)
2450 EXPORT_SYMBOL(ath9k_hw_keyisvalid
);
2452 /******************************/
2453 /* Power Management (Chipset) */
2454 /******************************/
2456 static void ath9k_set_power_sleep(struct ath_hw
*ah
, int setChip
)
2458 REG_SET_BIT(ah
, AR_STA_ID1
, AR_STA_ID1_PWR_SAV
);
2460 REG_CLR_BIT(ah
, AR_RTC_FORCE_WAKE
,
2461 AR_RTC_FORCE_WAKE_EN
);
2462 if (!AR_SREV_9100(ah
))
2463 REG_WRITE(ah
, AR_RC
, AR_RC_AHB
| AR_RC_HOSTIF
);
2465 if(!AR_SREV_5416(ah
))
2466 REG_CLR_BIT(ah
, (AR_RTC_RESET
),
2471 static void ath9k_set_power_network_sleep(struct ath_hw
*ah
, int setChip
)
2473 REG_SET_BIT(ah
, AR_STA_ID1
, AR_STA_ID1_PWR_SAV
);
2475 struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
2477 if (!(pCap
->hw_caps
& ATH9K_HW_CAP_AUTOSLEEP
)) {
2478 REG_WRITE(ah
, AR_RTC_FORCE_WAKE
,
2479 AR_RTC_FORCE_WAKE_ON_INT
);
2481 REG_CLR_BIT(ah
, AR_RTC_FORCE_WAKE
,
2482 AR_RTC_FORCE_WAKE_EN
);
2487 static bool ath9k_hw_set_power_awake(struct ath_hw
*ah
, int setChip
)
2493 if ((REG_READ(ah
, AR_RTC_STATUS
) &
2494 AR_RTC_STATUS_M
) == AR_RTC_STATUS_SHUTDOWN
) {
2495 if (ath9k_hw_set_reset_reg(ah
,
2496 ATH9K_RESET_POWER_ON
) != true) {
2499 ath9k_hw_init_pll(ah
, NULL
);
2501 if (AR_SREV_9100(ah
))
2502 REG_SET_BIT(ah
, AR_RTC_RESET
,
2505 REG_SET_BIT(ah
, AR_RTC_FORCE_WAKE
,
2506 AR_RTC_FORCE_WAKE_EN
);
2509 for (i
= POWER_UP_TIME
/ 50; i
> 0; i
--) {
2510 val
= REG_READ(ah
, AR_RTC_STATUS
) & AR_RTC_STATUS_M
;
2511 if (val
== AR_RTC_STATUS_ON
)
2514 REG_SET_BIT(ah
, AR_RTC_FORCE_WAKE
,
2515 AR_RTC_FORCE_WAKE_EN
);
2518 ath_print(ath9k_hw_common(ah
), ATH_DBG_FATAL
,
2519 "Failed to wakeup in %uus\n",
2520 POWER_UP_TIME
/ 20);
2525 REG_CLR_BIT(ah
, AR_STA_ID1
, AR_STA_ID1_PWR_SAV
);
2530 bool ath9k_hw_setpower(struct ath_hw
*ah
, enum ath9k_power_mode mode
)
2532 struct ath_common
*common
= ath9k_hw_common(ah
);
2533 int status
= true, setChip
= true;
2534 static const char *modes
[] = {
2541 if (ah
->power_mode
== mode
)
2544 ath_print(common
, ATH_DBG_RESET
, "%s -> %s\n",
2545 modes
[ah
->power_mode
], modes
[mode
]);
2548 case ATH9K_PM_AWAKE
:
2549 status
= ath9k_hw_set_power_awake(ah
, setChip
);
2551 case ATH9K_PM_FULL_SLEEP
:
2552 ath9k_set_power_sleep(ah
, setChip
);
2553 ah
->chip_fullsleep
= true;
2555 case ATH9K_PM_NETWORK_SLEEP
:
2556 ath9k_set_power_network_sleep(ah
, setChip
);
2559 ath_print(common
, ATH_DBG_FATAL
,
2560 "Unknown power mode %u\n", mode
);
2563 ah
->power_mode
= mode
;
2567 EXPORT_SYMBOL(ath9k_hw_setpower
);
2570 * Helper for ASPM support.
2572 * Disable PLL when in L0s as well as receiver clock when in L1.
2573 * This power saving option must be enabled through the SerDes.
2575 * Programming the SerDes must go through the same 288 bit serial shift
2576 * register as the other analog registers. Hence the 9 writes.
2578 void ath9k_hw_configpcipowersave(struct ath_hw
*ah
, int restore
, int power_off
)
2583 if (ah
->is_pciexpress
!= true)
2586 /* Do not touch SerDes registers */
2587 if (ah
->config
.pcie_powersave_enable
== 2)
2590 /* Nothing to do on restore for 11N */
2592 if (AR_SREV_9280_20_OR_LATER(ah
)) {
2594 * AR9280 2.0 or later chips use SerDes values from the
2595 * initvals.h initialized depending on chipset during
2598 for (i
= 0; i
< ah
->iniPcieSerdes
.ia_rows
; i
++) {
2599 REG_WRITE(ah
, INI_RA(&ah
->iniPcieSerdes
, i
, 0),
2600 INI_RA(&ah
->iniPcieSerdes
, i
, 1));
2602 } else if (AR_SREV_9280(ah
) &&
2603 (ah
->hw_version
.macRev
== AR_SREV_REVISION_9280_10
)) {
2604 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x9248fd00);
2605 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x24924924);
2607 /* RX shut off when elecidle is asserted */
2608 REG_WRITE(ah
, AR_PCIE_SERDES
, 0xa8000019);
2609 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x13160820);
2610 REG_WRITE(ah
, AR_PCIE_SERDES
, 0xe5980560);
2612 /* Shut off CLKREQ active in L1 */
2613 if (ah
->config
.pcie_clock_req
)
2614 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x401deffc);
2616 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x401deffd);
2618 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x1aaabe40);
2619 REG_WRITE(ah
, AR_PCIE_SERDES
, 0xbe105554);
2620 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x00043007);
2622 /* Load the new settings */
2623 REG_WRITE(ah
, AR_PCIE_SERDES2
, 0x00000000);
2626 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x9248fc00);
2627 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x24924924);
2629 /* RX shut off when elecidle is asserted */
2630 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x28000039);
2631 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x53160824);
2632 REG_WRITE(ah
, AR_PCIE_SERDES
, 0xe5980579);
2635 * Ignore ah->ah_config.pcie_clock_req setting for
2638 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x001defff);
2640 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x1aaabe40);
2641 REG_WRITE(ah
, AR_PCIE_SERDES
, 0xbe105554);
2642 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x000e3007);
2644 /* Load the new settings */
2645 REG_WRITE(ah
, AR_PCIE_SERDES2
, 0x00000000);
2650 /* set bit 19 to allow forcing of pcie core into L1 state */
2651 REG_SET_BIT(ah
, AR_PCIE_PM_CTRL
, AR_PCIE_PM_CTRL_ENA
);
2653 /* Several PCIe massages to ensure proper behaviour */
2654 if (ah
->config
.pcie_waen
) {
2655 val
= ah
->config
.pcie_waen
;
2657 val
&= (~AR_WA_D3_L1_DISABLE
);
2659 if (AR_SREV_9285(ah
) || AR_SREV_9271(ah
) ||
2661 val
= AR9285_WA_DEFAULT
;
2663 val
&= (~AR_WA_D3_L1_DISABLE
);
2664 } else if (AR_SREV_9280(ah
)) {
2666 * On AR9280 chips bit 22 of 0x4004 needs to be
2667 * set otherwise card may disappear.
2669 val
= AR9280_WA_DEFAULT
;
2671 val
&= (~AR_WA_D3_L1_DISABLE
);
2673 val
= AR_WA_DEFAULT
;
2676 REG_WRITE(ah
, AR_WA
, val
);
2681 * Set PCIe workaround bits
2682 * bit 14 in WA register (disable L1) should only
2683 * be set when device enters D3 and be cleared
2684 * when device comes back to D0.
2686 if (ah
->config
.pcie_waen
) {
2687 if (ah
->config
.pcie_waen
& AR_WA_D3_L1_DISABLE
)
2688 REG_SET_BIT(ah
, AR_WA
, AR_WA_D3_L1_DISABLE
);
2690 if (((AR_SREV_9285(ah
) || AR_SREV_9271(ah
) ||
2691 AR_SREV_9287(ah
)) &&
2692 (AR9285_WA_DEFAULT
& AR_WA_D3_L1_DISABLE
)) ||
2693 (AR_SREV_9280(ah
) &&
2694 (AR9280_WA_DEFAULT
& AR_WA_D3_L1_DISABLE
))) {
2695 REG_SET_BIT(ah
, AR_WA
, AR_WA_D3_L1_DISABLE
);
2700 EXPORT_SYMBOL(ath9k_hw_configpcipowersave
);
2702 /**********************/
2703 /* Interrupt Handling */
2704 /**********************/
2706 bool ath9k_hw_intrpend(struct ath_hw
*ah
)
2710 if (AR_SREV_9100(ah
))
2713 host_isr
= REG_READ(ah
, AR_INTR_ASYNC_CAUSE
);
2714 if ((host_isr
& AR_INTR_MAC_IRQ
) && (host_isr
!= AR_INTR_SPURIOUS
))
2717 host_isr
= REG_READ(ah
, AR_INTR_SYNC_CAUSE
);
2718 if ((host_isr
& AR_INTR_SYNC_DEFAULT
)
2719 && (host_isr
!= AR_INTR_SPURIOUS
))
2724 EXPORT_SYMBOL(ath9k_hw_intrpend
);
2726 bool ath9k_hw_getisr(struct ath_hw
*ah
, enum ath9k_int
*masked
)
2730 struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
2732 bool fatal_int
= false;
2733 struct ath_common
*common
= ath9k_hw_common(ah
);
2735 if (!AR_SREV_9100(ah
)) {
2736 if (REG_READ(ah
, AR_INTR_ASYNC_CAUSE
) & AR_INTR_MAC_IRQ
) {
2737 if ((REG_READ(ah
, AR_RTC_STATUS
) & AR_RTC_STATUS_M
)
2738 == AR_RTC_STATUS_ON
) {
2739 isr
= REG_READ(ah
, AR_ISR
);
2743 sync_cause
= REG_READ(ah
, AR_INTR_SYNC_CAUSE
) &
2744 AR_INTR_SYNC_DEFAULT
;
2748 if (!isr
&& !sync_cause
)
2752 isr
= REG_READ(ah
, AR_ISR
);
2756 if (isr
& AR_ISR_BCNMISC
) {
2758 isr2
= REG_READ(ah
, AR_ISR_S2
);
2759 if (isr2
& AR_ISR_S2_TIM
)
2760 mask2
|= ATH9K_INT_TIM
;
2761 if (isr2
& AR_ISR_S2_DTIM
)
2762 mask2
|= ATH9K_INT_DTIM
;
2763 if (isr2
& AR_ISR_S2_DTIMSYNC
)
2764 mask2
|= ATH9K_INT_DTIMSYNC
;
2765 if (isr2
& (AR_ISR_S2_CABEND
))
2766 mask2
|= ATH9K_INT_CABEND
;
2767 if (isr2
& AR_ISR_S2_GTT
)
2768 mask2
|= ATH9K_INT_GTT
;
2769 if (isr2
& AR_ISR_S2_CST
)
2770 mask2
|= ATH9K_INT_CST
;
2771 if (isr2
& AR_ISR_S2_TSFOOR
)
2772 mask2
|= ATH9K_INT_TSFOOR
;
2775 isr
= REG_READ(ah
, AR_ISR_RAC
);
2776 if (isr
== 0xffffffff) {
2781 *masked
= isr
& ATH9K_INT_COMMON
;
2783 if (ah
->config
.intr_mitigation
) {
2784 if (isr
& (AR_ISR_RXMINTR
| AR_ISR_RXINTM
))
2785 *masked
|= ATH9K_INT_RX
;
2788 if (isr
& (AR_ISR_RXOK
| AR_ISR_RXERR
))
2789 *masked
|= ATH9K_INT_RX
;
2791 (AR_ISR_TXOK
| AR_ISR_TXDESC
| AR_ISR_TXERR
|
2795 *masked
|= ATH9K_INT_TX
;
2797 s0_s
= REG_READ(ah
, AR_ISR_S0_S
);
2798 ah
->intr_txqs
|= MS(s0_s
, AR_ISR_S0_QCU_TXOK
);
2799 ah
->intr_txqs
|= MS(s0_s
, AR_ISR_S0_QCU_TXDESC
);
2801 s1_s
= REG_READ(ah
, AR_ISR_S1_S
);
2802 ah
->intr_txqs
|= MS(s1_s
, AR_ISR_S1_QCU_TXERR
);
2803 ah
->intr_txqs
|= MS(s1_s
, AR_ISR_S1_QCU_TXEOL
);
2806 if (isr
& AR_ISR_RXORN
) {
2807 ath_print(common
, ATH_DBG_INTERRUPT
,
2808 "receive FIFO overrun interrupt\n");
2811 if (!AR_SREV_9100(ah
)) {
2812 if (!(pCap
->hw_caps
& ATH9K_HW_CAP_AUTOSLEEP
)) {
2813 u32 isr5
= REG_READ(ah
, AR_ISR_S5_S
);
2814 if (isr5
& AR_ISR_S5_TIM_TIMER
)
2815 *masked
|= ATH9K_INT_TIM_TIMER
;
2822 if (AR_SREV_9100(ah
))
2825 if (isr
& AR_ISR_GENTMR
) {
2828 s5_s
= REG_READ(ah
, AR_ISR_S5_S
);
2829 if (isr
& AR_ISR_GENTMR
) {
2830 ah
->intr_gen_timer_trigger
=
2831 MS(s5_s
, AR_ISR_S5_GENTIMER_TRIG
);
2833 ah
->intr_gen_timer_thresh
=
2834 MS(s5_s
, AR_ISR_S5_GENTIMER_THRESH
);
2836 if (ah
->intr_gen_timer_trigger
)
2837 *masked
|= ATH9K_INT_GENTIMER
;
2845 (AR_INTR_SYNC_HOST1_FATAL
| AR_INTR_SYNC_HOST1_PERR
))
2849 if (sync_cause
& AR_INTR_SYNC_HOST1_FATAL
) {
2850 ath_print(common
, ATH_DBG_ANY
,
2851 "received PCI FATAL interrupt\n");
2853 if (sync_cause
& AR_INTR_SYNC_HOST1_PERR
) {
2854 ath_print(common
, ATH_DBG_ANY
,
2855 "received PCI PERR interrupt\n");
2857 *masked
|= ATH9K_INT_FATAL
;
2859 if (sync_cause
& AR_INTR_SYNC_RADM_CPL_TIMEOUT
) {
2860 ath_print(common
, ATH_DBG_INTERRUPT
,
2861 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
2862 REG_WRITE(ah
, AR_RC
, AR_RC_HOSTIF
);
2863 REG_WRITE(ah
, AR_RC
, 0);
2864 *masked
|= ATH9K_INT_FATAL
;
2866 if (sync_cause
& AR_INTR_SYNC_LOCAL_TIMEOUT
) {
2867 ath_print(common
, ATH_DBG_INTERRUPT
,
2868 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
2871 REG_WRITE(ah
, AR_INTR_SYNC_CAUSE_CLR
, sync_cause
);
2872 (void) REG_READ(ah
, AR_INTR_SYNC_CAUSE_CLR
);
2877 EXPORT_SYMBOL(ath9k_hw_getisr
);
2879 enum ath9k_int
ath9k_hw_set_interrupts(struct ath_hw
*ah
, enum ath9k_int ints
)
2881 u32 omask
= ah
->mask_reg
;
2883 struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
2884 struct ath_common
*common
= ath9k_hw_common(ah
);
2886 ath_print(common
, ATH_DBG_INTERRUPT
, "0x%x => 0x%x\n", omask
, ints
);
2888 if (omask
& ATH9K_INT_GLOBAL
) {
2889 ath_print(common
, ATH_DBG_INTERRUPT
, "disable IER\n");
2890 REG_WRITE(ah
, AR_IER
, AR_IER_DISABLE
);
2891 (void) REG_READ(ah
, AR_IER
);
2892 if (!AR_SREV_9100(ah
)) {
2893 REG_WRITE(ah
, AR_INTR_ASYNC_ENABLE
, 0);
2894 (void) REG_READ(ah
, AR_INTR_ASYNC_ENABLE
);
2896 REG_WRITE(ah
, AR_INTR_SYNC_ENABLE
, 0);
2897 (void) REG_READ(ah
, AR_INTR_SYNC_ENABLE
);
2901 mask
= ints
& ATH9K_INT_COMMON
;
2904 if (ints
& ATH9K_INT_TX
) {
2905 if (ah
->txok_interrupt_mask
)
2906 mask
|= AR_IMR_TXOK
;
2907 if (ah
->txdesc_interrupt_mask
)
2908 mask
|= AR_IMR_TXDESC
;
2909 if (ah
->txerr_interrupt_mask
)
2910 mask
|= AR_IMR_TXERR
;
2911 if (ah
->txeol_interrupt_mask
)
2912 mask
|= AR_IMR_TXEOL
;
2914 if (ints
& ATH9K_INT_RX
) {
2915 mask
|= AR_IMR_RXERR
;
2916 if (ah
->config
.intr_mitigation
)
2917 mask
|= AR_IMR_RXMINTR
| AR_IMR_RXINTM
;
2919 mask
|= AR_IMR_RXOK
| AR_IMR_RXDESC
;
2920 if (!(pCap
->hw_caps
& ATH9K_HW_CAP_AUTOSLEEP
))
2921 mask
|= AR_IMR_GENTMR
;
2924 if (ints
& (ATH9K_INT_BMISC
)) {
2925 mask
|= AR_IMR_BCNMISC
;
2926 if (ints
& ATH9K_INT_TIM
)
2927 mask2
|= AR_IMR_S2_TIM
;
2928 if (ints
& ATH9K_INT_DTIM
)
2929 mask2
|= AR_IMR_S2_DTIM
;
2930 if (ints
& ATH9K_INT_DTIMSYNC
)
2931 mask2
|= AR_IMR_S2_DTIMSYNC
;
2932 if (ints
& ATH9K_INT_CABEND
)
2933 mask2
|= AR_IMR_S2_CABEND
;
2934 if (ints
& ATH9K_INT_TSFOOR
)
2935 mask2
|= AR_IMR_S2_TSFOOR
;
2938 if (ints
& (ATH9K_INT_GTT
| ATH9K_INT_CST
)) {
2939 mask
|= AR_IMR_BCNMISC
;
2940 if (ints
& ATH9K_INT_GTT
)
2941 mask2
|= AR_IMR_S2_GTT
;
2942 if (ints
& ATH9K_INT_CST
)
2943 mask2
|= AR_IMR_S2_CST
;
2946 ath_print(common
, ATH_DBG_INTERRUPT
, "new IMR 0x%x\n", mask
);
2947 REG_WRITE(ah
, AR_IMR
, mask
);
2948 mask
= REG_READ(ah
, AR_IMR_S2
) & ~(AR_IMR_S2_TIM
|
2950 AR_IMR_S2_DTIMSYNC
|
2954 AR_IMR_S2_GTT
| AR_IMR_S2_CST
);
2955 REG_WRITE(ah
, AR_IMR_S2
, mask
| mask2
);
2956 ah
->mask_reg
= ints
;
2958 if (!(pCap
->hw_caps
& ATH9K_HW_CAP_AUTOSLEEP
)) {
2959 if (ints
& ATH9K_INT_TIM_TIMER
)
2960 REG_SET_BIT(ah
, AR_IMR_S5
, AR_IMR_S5_TIM_TIMER
);
2962 REG_CLR_BIT(ah
, AR_IMR_S5
, AR_IMR_S5_TIM_TIMER
);
2965 if (ints
& ATH9K_INT_GLOBAL
) {
2966 ath_print(common
, ATH_DBG_INTERRUPT
, "enable IER\n");
2967 REG_WRITE(ah
, AR_IER
, AR_IER_ENABLE
);
2968 if (!AR_SREV_9100(ah
)) {
2969 REG_WRITE(ah
, AR_INTR_ASYNC_ENABLE
,
2971 REG_WRITE(ah
, AR_INTR_ASYNC_MASK
, AR_INTR_MAC_IRQ
);
2974 REG_WRITE(ah
, AR_INTR_SYNC_ENABLE
,
2975 AR_INTR_SYNC_DEFAULT
);
2976 REG_WRITE(ah
, AR_INTR_SYNC_MASK
,
2977 AR_INTR_SYNC_DEFAULT
);
2979 ath_print(common
, ATH_DBG_INTERRUPT
, "AR_IMR 0x%x IER 0x%x\n",
2980 REG_READ(ah
, AR_IMR
), REG_READ(ah
, AR_IER
));
2985 EXPORT_SYMBOL(ath9k_hw_set_interrupts
);
2987 /*******************/
2988 /* Beacon Handling */
2989 /*******************/
2991 void ath9k_hw_beaconinit(struct ath_hw
*ah
, u32 next_beacon
, u32 beacon_period
)
2995 ah
->beacon_interval
= beacon_period
;
2997 switch (ah
->opmode
) {
2998 case NL80211_IFTYPE_STATION
:
2999 case NL80211_IFTYPE_MONITOR
:
3000 REG_WRITE(ah
, AR_NEXT_TBTT_TIMER
, TU_TO_USEC(next_beacon
));
3001 REG_WRITE(ah
, AR_NEXT_DMA_BEACON_ALERT
, 0xffff);
3002 REG_WRITE(ah
, AR_NEXT_SWBA
, 0x7ffff);
3003 flags
|= AR_TBTT_TIMER_EN
;
3005 case NL80211_IFTYPE_ADHOC
:
3006 case NL80211_IFTYPE_MESH_POINT
:
3007 REG_SET_BIT(ah
, AR_TXCFG
,
3008 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY
);
3009 REG_WRITE(ah
, AR_NEXT_NDP_TIMER
,
3010 TU_TO_USEC(next_beacon
+
3011 (ah
->atim_window
? ah
->
3013 flags
|= AR_NDP_TIMER_EN
;
3014 case NL80211_IFTYPE_AP
:
3015 REG_WRITE(ah
, AR_NEXT_TBTT_TIMER
, TU_TO_USEC(next_beacon
));
3016 REG_WRITE(ah
, AR_NEXT_DMA_BEACON_ALERT
,
3017 TU_TO_USEC(next_beacon
-
3019 dma_beacon_response_time
));
3020 REG_WRITE(ah
, AR_NEXT_SWBA
,
3021 TU_TO_USEC(next_beacon
-
3023 sw_beacon_response_time
));
3025 AR_TBTT_TIMER_EN
| AR_DBA_TIMER_EN
| AR_SWBA_TIMER_EN
;
3028 ath_print(ath9k_hw_common(ah
), ATH_DBG_BEACON
,
3029 "%s: unsupported opmode: %d\n",
3030 __func__
, ah
->opmode
);
3035 REG_WRITE(ah
, AR_BEACON_PERIOD
, TU_TO_USEC(beacon_period
));
3036 REG_WRITE(ah
, AR_DMA_BEACON_PERIOD
, TU_TO_USEC(beacon_period
));
3037 REG_WRITE(ah
, AR_SWBA_PERIOD
, TU_TO_USEC(beacon_period
));
3038 REG_WRITE(ah
, AR_NDP_PERIOD
, TU_TO_USEC(beacon_period
));
3040 beacon_period
&= ~ATH9K_BEACON_ENA
;
3041 if (beacon_period
& ATH9K_BEACON_RESET_TSF
) {
3042 ath9k_hw_reset_tsf(ah
);
3045 REG_SET_BIT(ah
, AR_TIMER_MODE
, flags
);
3047 EXPORT_SYMBOL(ath9k_hw_beaconinit
);
3049 void ath9k_hw_set_sta_beacon_timers(struct ath_hw
*ah
,
3050 const struct ath9k_beacon_state
*bs
)
3052 u32 nextTbtt
, beaconintval
, dtimperiod
, beacontimeout
;
3053 struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
3054 struct ath_common
*common
= ath9k_hw_common(ah
);
3056 REG_WRITE(ah
, AR_NEXT_TBTT_TIMER
, TU_TO_USEC(bs
->bs_nexttbtt
));
3058 REG_WRITE(ah
, AR_BEACON_PERIOD
,
3059 TU_TO_USEC(bs
->bs_intval
& ATH9K_BEACON_PERIOD
));
3060 REG_WRITE(ah
, AR_DMA_BEACON_PERIOD
,
3061 TU_TO_USEC(bs
->bs_intval
& ATH9K_BEACON_PERIOD
));
3063 REG_RMW_FIELD(ah
, AR_RSSI_THR
,
3064 AR_RSSI_THR_BM_THR
, bs
->bs_bmissthreshold
);
3066 beaconintval
= bs
->bs_intval
& ATH9K_BEACON_PERIOD
;
3068 if (bs
->bs_sleepduration
> beaconintval
)
3069 beaconintval
= bs
->bs_sleepduration
;
3071 dtimperiod
= bs
->bs_dtimperiod
;
3072 if (bs
->bs_sleepduration
> dtimperiod
)
3073 dtimperiod
= bs
->bs_sleepduration
;
3075 if (beaconintval
== dtimperiod
)
3076 nextTbtt
= bs
->bs_nextdtim
;
3078 nextTbtt
= bs
->bs_nexttbtt
;
3080 ath_print(common
, ATH_DBG_BEACON
, "next DTIM %d\n", bs
->bs_nextdtim
);
3081 ath_print(common
, ATH_DBG_BEACON
, "next beacon %d\n", nextTbtt
);
3082 ath_print(common
, ATH_DBG_BEACON
, "beacon period %d\n", beaconintval
);
3083 ath_print(common
, ATH_DBG_BEACON
, "DTIM period %d\n", dtimperiod
);
3085 REG_WRITE(ah
, AR_NEXT_DTIM
,
3086 TU_TO_USEC(bs
->bs_nextdtim
- SLEEP_SLOP
));
3087 REG_WRITE(ah
, AR_NEXT_TIM
, TU_TO_USEC(nextTbtt
- SLEEP_SLOP
));
3089 REG_WRITE(ah
, AR_SLEEP1
,
3090 SM((CAB_TIMEOUT_VAL
<< 3), AR_SLEEP1_CAB_TIMEOUT
)
3091 | AR_SLEEP1_ASSUME_DTIM
);
3093 if (pCap
->hw_caps
& ATH9K_HW_CAP_AUTOSLEEP
)
3094 beacontimeout
= (BEACON_TIMEOUT_VAL
<< 3);
3096 beacontimeout
= MIN_BEACON_TIMEOUT_VAL
;
3098 REG_WRITE(ah
, AR_SLEEP2
,
3099 SM(beacontimeout
, AR_SLEEP2_BEACON_TIMEOUT
));
3101 REG_WRITE(ah
, AR_TIM_PERIOD
, TU_TO_USEC(beaconintval
));
3102 REG_WRITE(ah
, AR_DTIM_PERIOD
, TU_TO_USEC(dtimperiod
));
3104 REG_SET_BIT(ah
, AR_TIMER_MODE
,
3105 AR_TBTT_TIMER_EN
| AR_TIM_TIMER_EN
|
3108 /* TSF Out of Range Threshold */
3109 REG_WRITE(ah
, AR_TSFOOR_THRESHOLD
, bs
->bs_tsfoor_threshold
);
3111 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers
);
3113 /*******************/
3114 /* HW Capabilities */
3115 /*******************/
3117 int ath9k_hw_fill_cap_info(struct ath_hw
*ah
)
3119 struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
3120 struct ath_regulatory
*regulatory
= ath9k_hw_regulatory(ah
);
3121 struct ath_common
*common
= ath9k_hw_common(ah
);
3122 struct ath_btcoex_hw
*btcoex_hw
= &ah
->btcoex_hw
;
3124 u16 capField
= 0, eeval
;
3126 eeval
= ah
->eep_ops
->get_eeprom(ah
, EEP_REG_0
);
3127 regulatory
->current_rd
= eeval
;
3129 eeval
= ah
->eep_ops
->get_eeprom(ah
, EEP_REG_1
);
3130 if (AR_SREV_9285_10_OR_LATER(ah
))
3131 eeval
|= AR9285_RDEXT_DEFAULT
;
3132 regulatory
->current_rd_ext
= eeval
;
3134 capField
= ah
->eep_ops
->get_eeprom(ah
, EEP_OP_CAP
);
3136 if (ah
->opmode
!= NL80211_IFTYPE_AP
&&
3137 ah
->hw_version
.subvendorid
== AR_SUBVENDOR_ID_NEW_A
) {
3138 if (regulatory
->current_rd
== 0x64 ||
3139 regulatory
->current_rd
== 0x65)
3140 regulatory
->current_rd
+= 5;
3141 else if (regulatory
->current_rd
== 0x41)
3142 regulatory
->current_rd
= 0x43;
3143 ath_print(common
, ATH_DBG_REGULATORY
,
3144 "regdomain mapped to 0x%x\n", regulatory
->current_rd
);
3147 eeval
= ah
->eep_ops
->get_eeprom(ah
, EEP_OP_MODE
);
3148 if ((eeval
& (AR5416_OPFLAGS_11G
| AR5416_OPFLAGS_11A
)) == 0) {
3149 ath_print(common
, ATH_DBG_FATAL
,
3150 "no band has been marked as supported in EEPROM.\n");
3154 bitmap_zero(pCap
->wireless_modes
, ATH9K_MODE_MAX
);
3156 if (eeval
& AR5416_OPFLAGS_11A
) {
3157 set_bit(ATH9K_MODE_11A
, pCap
->wireless_modes
);
3158 if (ah
->config
.ht_enable
) {
3159 if (!(eeval
& AR5416_OPFLAGS_N_5G_HT20
))
3160 set_bit(ATH9K_MODE_11NA_HT20
,
3161 pCap
->wireless_modes
);
3162 if (!(eeval
& AR5416_OPFLAGS_N_5G_HT40
)) {
3163 set_bit(ATH9K_MODE_11NA_HT40PLUS
,
3164 pCap
->wireless_modes
);
3165 set_bit(ATH9K_MODE_11NA_HT40MINUS
,
3166 pCap
->wireless_modes
);
3171 if (eeval
& AR5416_OPFLAGS_11G
) {
3172 set_bit(ATH9K_MODE_11G
, pCap
->wireless_modes
);
3173 if (ah
->config
.ht_enable
) {
3174 if (!(eeval
& AR5416_OPFLAGS_N_2G_HT20
))
3175 set_bit(ATH9K_MODE_11NG_HT20
,
3176 pCap
->wireless_modes
);
3177 if (!(eeval
& AR5416_OPFLAGS_N_2G_HT40
)) {
3178 set_bit(ATH9K_MODE_11NG_HT40PLUS
,
3179 pCap
->wireless_modes
);
3180 set_bit(ATH9K_MODE_11NG_HT40MINUS
,
3181 pCap
->wireless_modes
);
3186 pCap
->tx_chainmask
= ah
->eep_ops
->get_eeprom(ah
, EEP_TX_MASK
);
3188 * For AR9271 we will temporarilly uses the rx chainmax as read from
3191 if ((ah
->hw_version
.devid
== AR5416_DEVID_PCI
) &&
3192 !(eeval
& AR5416_OPFLAGS_11A
) &&
3193 !(AR_SREV_9271(ah
)))
3194 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
3195 pCap
->rx_chainmask
= ath9k_hw_gpio_get(ah
, 0) ? 0x5 : 0x7;
3197 /* Use rx_chainmask from EEPROM. */
3198 pCap
->rx_chainmask
= ah
->eep_ops
->get_eeprom(ah
, EEP_RX_MASK
);
3200 if (!(AR_SREV_9280(ah
) && (ah
->hw_version
.macRev
== 0)))
3201 ah
->misc_mode
|= AR_PCU_MIC_NEW_LOC_ENA
;
3203 pCap
->low_2ghz_chan
= 2312;
3204 pCap
->high_2ghz_chan
= 2732;
3206 pCap
->low_5ghz_chan
= 4920;
3207 pCap
->high_5ghz_chan
= 6100;
3209 pCap
->hw_caps
&= ~ATH9K_HW_CAP_CIPHER_CKIP
;
3210 pCap
->hw_caps
|= ATH9K_HW_CAP_CIPHER_TKIP
;
3211 pCap
->hw_caps
|= ATH9K_HW_CAP_CIPHER_AESCCM
;
3213 pCap
->hw_caps
&= ~ATH9K_HW_CAP_MIC_CKIP
;
3214 pCap
->hw_caps
|= ATH9K_HW_CAP_MIC_TKIP
;
3215 pCap
->hw_caps
|= ATH9K_HW_CAP_MIC_AESCCM
;
3217 if (ah
->config
.ht_enable
)
3218 pCap
->hw_caps
|= ATH9K_HW_CAP_HT
;
3220 pCap
->hw_caps
&= ~ATH9K_HW_CAP_HT
;
3222 pCap
->hw_caps
|= ATH9K_HW_CAP_GTT
;
3223 pCap
->hw_caps
|= ATH9K_HW_CAP_VEOL
;
3224 pCap
->hw_caps
|= ATH9K_HW_CAP_BSSIDMASK
;
3225 pCap
->hw_caps
&= ~ATH9K_HW_CAP_MCAST_KEYSEARCH
;
3227 if (capField
& AR_EEPROM_EEPCAP_MAXQCU
)
3228 pCap
->total_queues
=
3229 MS(capField
, AR_EEPROM_EEPCAP_MAXQCU
);
3231 pCap
->total_queues
= ATH9K_NUM_TX_QUEUES
;
3233 if (capField
& AR_EEPROM_EEPCAP_KC_ENTRIES
)
3234 pCap
->keycache_size
=
3235 1 << MS(capField
, AR_EEPROM_EEPCAP_KC_ENTRIES
);
3237 pCap
->keycache_size
= AR_KEYTABLE_SIZE
;
3239 pCap
->hw_caps
|= ATH9K_HW_CAP_FASTCC
;
3241 if (AR_SREV_9285(ah
) || AR_SREV_9271(ah
))
3242 pCap
->tx_triglevel_max
= MAX_TX_FIFO_THRESHOLD
>> 1;
3244 pCap
->tx_triglevel_max
= MAX_TX_FIFO_THRESHOLD
;
3246 if (AR_SREV_9285_10_OR_LATER(ah
))
3247 pCap
->num_gpio_pins
= AR9285_NUM_GPIO
;
3248 else if (AR_SREV_9280_10_OR_LATER(ah
))
3249 pCap
->num_gpio_pins
= AR928X_NUM_GPIO
;
3251 pCap
->num_gpio_pins
= AR_NUM_GPIO
;
3253 if (AR_SREV_9160_10_OR_LATER(ah
) || AR_SREV_9100(ah
)) {
3254 pCap
->hw_caps
|= ATH9K_HW_CAP_CST
;
3255 pCap
->rts_aggr_limit
= ATH_AMPDU_LIMIT_MAX
;
3257 pCap
->rts_aggr_limit
= (8 * 1024);
3260 pCap
->hw_caps
|= ATH9K_HW_CAP_ENHANCEDPM
;
3262 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3263 ah
->rfsilent
= ah
->eep_ops
->get_eeprom(ah
, EEP_RF_SILENT
);
3264 if (ah
->rfsilent
& EEP_RFSILENT_ENABLED
) {
3266 MS(ah
->rfsilent
, EEP_RFSILENT_GPIO_SEL
);
3267 ah
->rfkill_polarity
=
3268 MS(ah
->rfsilent
, EEP_RFSILENT_POLARITY
);
3270 pCap
->hw_caps
|= ATH9K_HW_CAP_RFSILENT
;
3274 pCap
->hw_caps
&= ~ATH9K_HW_CAP_AUTOSLEEP
;
3276 if (AR_SREV_9280(ah
) || AR_SREV_9285(ah
))
3277 pCap
->hw_caps
&= ~ATH9K_HW_CAP_4KB_SPLITTRANS
;
3279 pCap
->hw_caps
|= ATH9K_HW_CAP_4KB_SPLITTRANS
;
3281 if (regulatory
->current_rd_ext
& (1 << REG_EXT_JAPAN_MIDBAND
)) {
3283 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A
|
3284 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN
|
3285 AR_EEPROM_EEREGCAP_EN_KK_U2
|
3286 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND
;
3289 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A
|
3290 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN
;
3293 /* Advertise midband for AR5416 with FCC midband set in eeprom */
3294 if (regulatory
->current_rd_ext
& (1 << REG_EXT_FCC_MIDBAND
) &&
3296 pCap
->reg_cap
|= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND
;
3298 pCap
->num_antcfg_5ghz
=
3299 ah
->eep_ops
->get_num_ant_config(ah
, ATH9K_HAL_FREQ_BAND_5GHZ
);
3300 pCap
->num_antcfg_2ghz
=
3301 ah
->eep_ops
->get_num_ant_config(ah
, ATH9K_HAL_FREQ_BAND_2GHZ
);
3303 if (AR_SREV_9280_10_OR_LATER(ah
) &&
3304 ath9k_hw_btcoex_supported(ah
)) {
3305 btcoex_hw
->btactive_gpio
= ATH_BTACTIVE_GPIO
;
3306 btcoex_hw
->wlanactive_gpio
= ATH_WLANACTIVE_GPIO
;
3308 if (AR_SREV_9285(ah
)) {
3309 btcoex_hw
->scheme
= ATH_BTCOEX_CFG_3WIRE
;
3310 btcoex_hw
->btpriority_gpio
= ATH_BTPRIORITY_GPIO
;
3312 btcoex_hw
->scheme
= ATH_BTCOEX_CFG_2WIRE
;
3315 btcoex_hw
->scheme
= ATH_BTCOEX_CFG_NONE
;
3321 bool ath9k_hw_getcapability(struct ath_hw
*ah
, enum ath9k_capability_type type
,
3322 u32 capability
, u32
*result
)
3324 struct ath_regulatory
*regulatory
= ath9k_hw_regulatory(ah
);
3326 case ATH9K_CAP_CIPHER
:
3327 switch (capability
) {
3328 case ATH9K_CIPHER_AES_CCM
:
3329 case ATH9K_CIPHER_AES_OCB
:
3330 case ATH9K_CIPHER_TKIP
:
3331 case ATH9K_CIPHER_WEP
:
3332 case ATH9K_CIPHER_MIC
:
3333 case ATH9K_CIPHER_CLR
:
3338 case ATH9K_CAP_TKIP_MIC
:
3339 switch (capability
) {
3343 return (ah
->sta_id1_defaults
&
3344 AR_STA_ID1_CRPT_MIC_ENABLE
) ? true :
3347 case ATH9K_CAP_TKIP_SPLIT
:
3348 return (ah
->misc_mode
& AR_PCU_MIC_NEW_LOC_ENA
) ?
3350 case ATH9K_CAP_DIVERSITY
:
3351 return (REG_READ(ah
, AR_PHY_CCK_DETECT
) &
3352 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV
) ?
3354 case ATH9K_CAP_MCAST_KEYSRCH
:
3355 switch (capability
) {
3359 if (REG_READ(ah
, AR_STA_ID1
) & AR_STA_ID1_ADHOC
) {
3362 return (ah
->sta_id1_defaults
&
3363 AR_STA_ID1_MCAST_KSRCH
) ? true :
3368 case ATH9K_CAP_TXPOW
:
3369 switch (capability
) {
3373 *result
= regulatory
->power_limit
;
3376 *result
= regulatory
->max_power_level
;
3379 *result
= regulatory
->tp_scale
;
3384 return (AR_SREV_9280_20_OR_LATER(ah
) &&
3385 (ah
->eep_ops
->get_eeprom(ah
, EEP_RC_CHAIN_MASK
) == 1))
3391 EXPORT_SYMBOL(ath9k_hw_getcapability
);
3393 bool ath9k_hw_setcapability(struct ath_hw
*ah
, enum ath9k_capability_type type
,
3394 u32 capability
, u32 setting
, int *status
)
3399 case ATH9K_CAP_TKIP_MIC
:
3401 ah
->sta_id1_defaults
|=
3402 AR_STA_ID1_CRPT_MIC_ENABLE
;
3404 ah
->sta_id1_defaults
&=
3405 ~AR_STA_ID1_CRPT_MIC_ENABLE
;
3407 case ATH9K_CAP_DIVERSITY
:
3408 v
= REG_READ(ah
, AR_PHY_CCK_DETECT
);
3410 v
|= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV
;
3412 v
&= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV
;
3413 REG_WRITE(ah
, AR_PHY_CCK_DETECT
, v
);
3415 case ATH9K_CAP_MCAST_KEYSRCH
:
3417 ah
->sta_id1_defaults
|= AR_STA_ID1_MCAST_KSRCH
;
3419 ah
->sta_id1_defaults
&= ~AR_STA_ID1_MCAST_KSRCH
;
3425 EXPORT_SYMBOL(ath9k_hw_setcapability
);
3427 /****************************/
3428 /* GPIO / RFKILL / Antennae */
3429 /****************************/
3431 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw
*ah
,
3435 u32 gpio_shift
, tmp
;
3438 addr
= AR_GPIO_OUTPUT_MUX3
;
3440 addr
= AR_GPIO_OUTPUT_MUX2
;
3442 addr
= AR_GPIO_OUTPUT_MUX1
;
3444 gpio_shift
= (gpio
% 6) * 5;
3446 if (AR_SREV_9280_20_OR_LATER(ah
)
3447 || (addr
!= AR_GPIO_OUTPUT_MUX1
)) {
3448 REG_RMW(ah
, addr
, (type
<< gpio_shift
),
3449 (0x1f << gpio_shift
));
3451 tmp
= REG_READ(ah
, addr
);
3452 tmp
= ((tmp
& 0x1F0) << 1) | (tmp
& ~0x1F0);
3453 tmp
&= ~(0x1f << gpio_shift
);
3454 tmp
|= (type
<< gpio_shift
);
3455 REG_WRITE(ah
, addr
, tmp
);
3459 void ath9k_hw_cfg_gpio_input(struct ath_hw
*ah
, u32 gpio
)
3463 BUG_ON(gpio
>= ah
->caps
.num_gpio_pins
);
3465 gpio_shift
= gpio
<< 1;
3469 (AR_GPIO_OE_OUT_DRV_NO
<< gpio_shift
),
3470 (AR_GPIO_OE_OUT_DRV
<< gpio_shift
));
3472 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input
);
3474 u32
ath9k_hw_gpio_get(struct ath_hw
*ah
, u32 gpio
)
3476 #define MS_REG_READ(x, y) \
3477 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3479 if (gpio
>= ah
->caps
.num_gpio_pins
)
3482 if (AR_SREV_9287_10_OR_LATER(ah
))
3483 return MS_REG_READ(AR9287
, gpio
) != 0;
3484 else if (AR_SREV_9285_10_OR_LATER(ah
))
3485 return MS_REG_READ(AR9285
, gpio
) != 0;
3486 else if (AR_SREV_9280_10_OR_LATER(ah
))
3487 return MS_REG_READ(AR928X
, gpio
) != 0;
3489 return MS_REG_READ(AR
, gpio
) != 0;
3491 EXPORT_SYMBOL(ath9k_hw_gpio_get
);
3493 void ath9k_hw_cfg_output(struct ath_hw
*ah
, u32 gpio
,
3498 ath9k_hw_gpio_cfg_output_mux(ah
, gpio
, ah_signal_type
);
3500 gpio_shift
= 2 * gpio
;
3504 (AR_GPIO_OE_OUT_DRV_ALL
<< gpio_shift
),
3505 (AR_GPIO_OE_OUT_DRV
<< gpio_shift
));
3507 EXPORT_SYMBOL(ath9k_hw_cfg_output
);
3509 void ath9k_hw_set_gpio(struct ath_hw
*ah
, u32 gpio
, u32 val
)
3511 REG_RMW(ah
, AR_GPIO_IN_OUT
, ((val
& 1) << gpio
),
3514 EXPORT_SYMBOL(ath9k_hw_set_gpio
);
3516 u32
ath9k_hw_getdefantenna(struct ath_hw
*ah
)
3518 return REG_READ(ah
, AR_DEF_ANTENNA
) & 0x7;
3520 EXPORT_SYMBOL(ath9k_hw_getdefantenna
);
3522 void ath9k_hw_setantenna(struct ath_hw
*ah
, u32 antenna
)
3524 REG_WRITE(ah
, AR_DEF_ANTENNA
, (antenna
& 0x7));
3526 EXPORT_SYMBOL(ath9k_hw_setantenna
);
3528 /*********************/
3529 /* General Operation */
3530 /*********************/
3532 u32
ath9k_hw_getrxfilter(struct ath_hw
*ah
)
3534 u32 bits
= REG_READ(ah
, AR_RX_FILTER
);
3535 u32 phybits
= REG_READ(ah
, AR_PHY_ERR
);
3537 if (phybits
& AR_PHY_ERR_RADAR
)
3538 bits
|= ATH9K_RX_FILTER_PHYRADAR
;
3539 if (phybits
& (AR_PHY_ERR_OFDM_TIMING
| AR_PHY_ERR_CCK_TIMING
))
3540 bits
|= ATH9K_RX_FILTER_PHYERR
;
3544 EXPORT_SYMBOL(ath9k_hw_getrxfilter
);
3546 void ath9k_hw_setrxfilter(struct ath_hw
*ah
, u32 bits
)
3550 REG_WRITE(ah
, AR_RX_FILTER
, bits
);
3553 if (bits
& ATH9K_RX_FILTER_PHYRADAR
)
3554 phybits
|= AR_PHY_ERR_RADAR
;
3555 if (bits
& ATH9K_RX_FILTER_PHYERR
)
3556 phybits
|= AR_PHY_ERR_OFDM_TIMING
| AR_PHY_ERR_CCK_TIMING
;
3557 REG_WRITE(ah
, AR_PHY_ERR
, phybits
);
3560 REG_WRITE(ah
, AR_RXCFG
,
3561 REG_READ(ah
, AR_RXCFG
) | AR_RXCFG_ZLFDMA
);
3563 REG_WRITE(ah
, AR_RXCFG
,
3564 REG_READ(ah
, AR_RXCFG
) & ~AR_RXCFG_ZLFDMA
);
3566 EXPORT_SYMBOL(ath9k_hw_setrxfilter
);
3568 bool ath9k_hw_phy_disable(struct ath_hw
*ah
)
3570 if (!ath9k_hw_set_reset_reg(ah
, ATH9K_RESET_WARM
))
3573 ath9k_hw_init_pll(ah
, NULL
);
3576 EXPORT_SYMBOL(ath9k_hw_phy_disable
);
3578 bool ath9k_hw_disable(struct ath_hw
*ah
)
3580 if (!ath9k_hw_setpower(ah
, ATH9K_PM_AWAKE
))
3583 if (!ath9k_hw_set_reset_reg(ah
, ATH9K_RESET_COLD
))
3586 ath9k_hw_init_pll(ah
, NULL
);
3589 EXPORT_SYMBOL(ath9k_hw_disable
);
3591 void ath9k_hw_set_txpowerlimit(struct ath_hw
*ah
, u32 limit
)
3593 struct ath_regulatory
*regulatory
= ath9k_hw_regulatory(ah
);
3594 struct ath9k_channel
*chan
= ah
->curchan
;
3595 struct ieee80211_channel
*channel
= chan
->chan
;
3597 regulatory
->power_limit
= min(limit
, (u32
) MAX_RATE_POWER
);
3599 ah
->eep_ops
->set_txpower(ah
, chan
,
3600 ath9k_regd_get_ctl(regulatory
, chan
),
3601 channel
->max_antenna_gain
* 2,
3602 channel
->max_power
* 2,
3603 min((u32
) MAX_RATE_POWER
,
3604 (u32
) regulatory
->power_limit
));
3606 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit
);
3608 void ath9k_hw_setmac(struct ath_hw
*ah
, const u8
*mac
)
3610 memcpy(ath9k_hw_common(ah
)->macaddr
, mac
, ETH_ALEN
);
3612 EXPORT_SYMBOL(ath9k_hw_setmac
);
3614 void ath9k_hw_setopmode(struct ath_hw
*ah
)
3616 ath9k_hw_set_operating_mode(ah
, ah
->opmode
);
3618 EXPORT_SYMBOL(ath9k_hw_setopmode
);
3620 void ath9k_hw_setmcastfilter(struct ath_hw
*ah
, u32 filter0
, u32 filter1
)
3622 REG_WRITE(ah
, AR_MCAST_FIL0
, filter0
);
3623 REG_WRITE(ah
, AR_MCAST_FIL1
, filter1
);
3625 EXPORT_SYMBOL(ath9k_hw_setmcastfilter
);
3627 void ath9k_hw_write_associd(struct ath_hw
*ah
)
3629 struct ath_common
*common
= ath9k_hw_common(ah
);
3631 REG_WRITE(ah
, AR_BSS_ID0
, get_unaligned_le32(common
->curbssid
));
3632 REG_WRITE(ah
, AR_BSS_ID1
, get_unaligned_le16(common
->curbssid
+ 4) |
3633 ((common
->curaid
& 0x3fff) << AR_BSS_ID1_AID_S
));
3635 EXPORT_SYMBOL(ath9k_hw_write_associd
);
3637 u64
ath9k_hw_gettsf64(struct ath_hw
*ah
)
3641 tsf
= REG_READ(ah
, AR_TSF_U32
);
3642 tsf
= (tsf
<< 32) | REG_READ(ah
, AR_TSF_L32
);
3646 EXPORT_SYMBOL(ath9k_hw_gettsf64
);
3648 void ath9k_hw_settsf64(struct ath_hw
*ah
, u64 tsf64
)
3650 REG_WRITE(ah
, AR_TSF_L32
, tsf64
& 0xffffffff);
3651 REG_WRITE(ah
, AR_TSF_U32
, (tsf64
>> 32) & 0xffffffff);
3653 EXPORT_SYMBOL(ath9k_hw_settsf64
);
3655 void ath9k_hw_reset_tsf(struct ath_hw
*ah
)
3657 if (!ath9k_hw_wait(ah
, AR_SLP32_MODE
, AR_SLP32_TSF_WRITE_STATUS
, 0,
3658 AH_TSF_WRITE_TIMEOUT
))
3659 ath_print(ath9k_hw_common(ah
), ATH_DBG_RESET
,
3660 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
3662 REG_WRITE(ah
, AR_RESET_TSF
, AR_RESET_TSF_ONCE
);
3664 EXPORT_SYMBOL(ath9k_hw_reset_tsf
);
3666 void ath9k_hw_set_tsfadjust(struct ath_hw
*ah
, u32 setting
)
3669 ah
->misc_mode
|= AR_PCU_TX_ADD_TSF
;
3671 ah
->misc_mode
&= ~AR_PCU_TX_ADD_TSF
;
3673 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust
);
3676 * Extend 15-bit time stamp from rx descriptor to
3677 * a full 64-bit TSF using the current h/w TSF.
3679 u64
ath9k_hw_extend_tsf(struct ath_hw
*ah
, u32 rstamp
)
3683 tsf
= ath9k_hw_gettsf64(ah
);
3684 if ((tsf
& 0x7fff) < rstamp
)
3686 return (tsf
& ~0x7fff) | rstamp
;
3688 EXPORT_SYMBOL(ath9k_hw_extend_tsf
);
3690 bool ath9k_hw_setslottime(struct ath_hw
*ah
, u32 us
)
3692 if (us
< ATH9K_SLOT_TIME_9
|| us
> ath9k_hw_mac_to_usec(ah
, 0xffff)) {
3693 ath_print(ath9k_hw_common(ah
), ATH_DBG_RESET
,
3694 "bad slot time %u\n", us
);
3695 ah
->slottime
= (u32
) -1;
3698 REG_WRITE(ah
, AR_D_GBL_IFS_SLOT
, ath9k_hw_mac_to_clks(ah
, us
));
3703 EXPORT_SYMBOL(ath9k_hw_setslottime
);
3705 void ath9k_hw_set11nmac2040(struct ath_hw
*ah
)
3707 struct ieee80211_conf
*conf
= &ath9k_hw_common(ah
)->hw
->conf
;
3710 if (conf_is_ht40(conf
) && !ah
->config
.cwm_ignore_extcca
)
3711 macmode
= AR_2040_JOINED_RX_CLEAR
;
3715 REG_WRITE(ah
, AR_2040_MODE
, macmode
);
3718 /* HW Generic timers configuration */
3720 static const struct ath_gen_timer_configuration gen_tmr_configuration
[] =
3722 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
3723 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
3724 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
3725 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
3726 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
3727 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
3728 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
3729 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
3730 {AR_NEXT_NDP2_TIMER
, AR_NDP2_PERIOD
, AR_NDP2_TIMER_MODE
, 0x0001},
3731 {AR_NEXT_NDP2_TIMER
+ 1*4, AR_NDP2_PERIOD
+ 1*4,
3732 AR_NDP2_TIMER_MODE
, 0x0002},
3733 {AR_NEXT_NDP2_TIMER
+ 2*4, AR_NDP2_PERIOD
+ 2*4,
3734 AR_NDP2_TIMER_MODE
, 0x0004},
3735 {AR_NEXT_NDP2_TIMER
+ 3*4, AR_NDP2_PERIOD
+ 3*4,
3736 AR_NDP2_TIMER_MODE
, 0x0008},
3737 {AR_NEXT_NDP2_TIMER
+ 4*4, AR_NDP2_PERIOD
+ 4*4,
3738 AR_NDP2_TIMER_MODE
, 0x0010},
3739 {AR_NEXT_NDP2_TIMER
+ 5*4, AR_NDP2_PERIOD
+ 5*4,
3740 AR_NDP2_TIMER_MODE
, 0x0020},
3741 {AR_NEXT_NDP2_TIMER
+ 6*4, AR_NDP2_PERIOD
+ 6*4,
3742 AR_NDP2_TIMER_MODE
, 0x0040},
3743 {AR_NEXT_NDP2_TIMER
+ 7*4, AR_NDP2_PERIOD
+ 7*4,
3744 AR_NDP2_TIMER_MODE
, 0x0080}
3747 /* HW generic timer primitives */
3749 /* compute and clear index of rightmost 1 */
3750 static u32
rightmost_index(struct ath_gen_timer_table
*timer_table
, u32
*mask
)
3760 return timer_table
->gen_timer_index
[b
];
3763 u32
ath9k_hw_gettsf32(struct ath_hw
*ah
)
3765 return REG_READ(ah
, AR_TSF_L32
);
3767 EXPORT_SYMBOL(ath9k_hw_gettsf32
);
3769 struct ath_gen_timer
*ath_gen_timer_alloc(struct ath_hw
*ah
,
3770 void (*trigger
)(void *),
3771 void (*overflow
)(void *),
3775 struct ath_gen_timer_table
*timer_table
= &ah
->hw_gen_timers
;
3776 struct ath_gen_timer
*timer
;
3778 timer
= kzalloc(sizeof(struct ath_gen_timer
), GFP_KERNEL
);
3780 if (timer
== NULL
) {
3781 ath_print(ath9k_hw_common(ah
), ATH_DBG_FATAL
,
3782 "Failed to allocate memory"
3783 "for hw timer[%d]\n", timer_index
);
3787 /* allocate a hardware generic timer slot */
3788 timer_table
->timers
[timer_index
] = timer
;
3789 timer
->index
= timer_index
;
3790 timer
->trigger
= trigger
;
3791 timer
->overflow
= overflow
;
3796 EXPORT_SYMBOL(ath_gen_timer_alloc
);
3798 void ath9k_hw_gen_timer_start(struct ath_hw
*ah
,
3799 struct ath_gen_timer
*timer
,
3803 struct ath_gen_timer_table
*timer_table
= &ah
->hw_gen_timers
;
3806 BUG_ON(!timer_period
);
3808 set_bit(timer
->index
, &timer_table
->timer_mask
.timer_bits
);
3810 tsf
= ath9k_hw_gettsf32(ah
);
3812 ath_print(ath9k_hw_common(ah
), ATH_DBG_HWTIMER
,
3813 "curent tsf %x period %x"
3814 "timer_next %x\n", tsf
, timer_period
, timer_next
);
3817 * Pull timer_next forward if the current TSF already passed it
3818 * because of software latency
3820 if (timer_next
< tsf
)
3821 timer_next
= tsf
+ timer_period
;
3824 * Program generic timer registers
3826 REG_WRITE(ah
, gen_tmr_configuration
[timer
->index
].next_addr
,
3828 REG_WRITE(ah
, gen_tmr_configuration
[timer
->index
].period_addr
,
3830 REG_SET_BIT(ah
, gen_tmr_configuration
[timer
->index
].mode_addr
,
3831 gen_tmr_configuration
[timer
->index
].mode_mask
);
3833 /* Enable both trigger and thresh interrupt masks */
3834 REG_SET_BIT(ah
, AR_IMR_S5
,
3835 (SM(AR_GENTMR_BIT(timer
->index
), AR_IMR_S5_GENTIMER_THRESH
) |
3836 SM(AR_GENTMR_BIT(timer
->index
), AR_IMR_S5_GENTIMER_TRIG
)));
3838 EXPORT_SYMBOL(ath9k_hw_gen_timer_start
);
3840 void ath9k_hw_gen_timer_stop(struct ath_hw
*ah
, struct ath_gen_timer
*timer
)
3842 struct ath_gen_timer_table
*timer_table
= &ah
->hw_gen_timers
;
3844 if ((timer
->index
< AR_FIRST_NDP_TIMER
) ||
3845 (timer
->index
>= ATH_MAX_GEN_TIMER
)) {
3849 /* Clear generic timer enable bits. */
3850 REG_CLR_BIT(ah
, gen_tmr_configuration
[timer
->index
].mode_addr
,
3851 gen_tmr_configuration
[timer
->index
].mode_mask
);
3853 /* Disable both trigger and thresh interrupt masks */
3854 REG_CLR_BIT(ah
, AR_IMR_S5
,
3855 (SM(AR_GENTMR_BIT(timer
->index
), AR_IMR_S5_GENTIMER_THRESH
) |
3856 SM(AR_GENTMR_BIT(timer
->index
), AR_IMR_S5_GENTIMER_TRIG
)));
3858 clear_bit(timer
->index
, &timer_table
->timer_mask
.timer_bits
);
3860 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop
);
3862 void ath_gen_timer_free(struct ath_hw
*ah
, struct ath_gen_timer
*timer
)
3864 struct ath_gen_timer_table
*timer_table
= &ah
->hw_gen_timers
;
3866 /* free the hardware generic timer slot */
3867 timer_table
->timers
[timer
->index
] = NULL
;
3870 EXPORT_SYMBOL(ath_gen_timer_free
);
3873 * Generic Timer Interrupts handling
3875 void ath_gen_timer_isr(struct ath_hw
*ah
)
3877 struct ath_gen_timer_table
*timer_table
= &ah
->hw_gen_timers
;
3878 struct ath_gen_timer
*timer
;
3879 struct ath_common
*common
= ath9k_hw_common(ah
);
3880 u32 trigger_mask
, thresh_mask
, index
;
3882 /* get hardware generic timer interrupt status */
3883 trigger_mask
= ah
->intr_gen_timer_trigger
;
3884 thresh_mask
= ah
->intr_gen_timer_thresh
;
3885 trigger_mask
&= timer_table
->timer_mask
.val
;
3886 thresh_mask
&= timer_table
->timer_mask
.val
;
3888 trigger_mask
&= ~thresh_mask
;
3890 while (thresh_mask
) {
3891 index
= rightmost_index(timer_table
, &thresh_mask
);
3892 timer
= timer_table
->timers
[index
];
3894 ath_print(common
, ATH_DBG_HWTIMER
,
3895 "TSF overflow for Gen timer %d\n", index
);
3896 timer
->overflow(timer
->arg
);
3899 while (trigger_mask
) {
3900 index
= rightmost_index(timer_table
, &trigger_mask
);
3901 timer
= timer_table
->timers
[index
];
3903 ath_print(common
, ATH_DBG_HWTIMER
,
3904 "Gen timer[%d] trigger\n", index
);
3905 timer
->trigger(timer
->arg
);
3908 EXPORT_SYMBOL(ath_gen_timer_isr
);
3913 } ath_mac_bb_names
[] = {
3914 /* Devices with external radios */
3915 { AR_SREV_VERSION_5416_PCI
, "5416" },
3916 { AR_SREV_VERSION_5416_PCIE
, "5418" },
3917 { AR_SREV_VERSION_9100
, "9100" },
3918 { AR_SREV_VERSION_9160
, "9160" },
3919 /* Single-chip solutions */
3920 { AR_SREV_VERSION_9280
, "9280" },
3921 { AR_SREV_VERSION_9285
, "9285" },
3922 { AR_SREV_VERSION_9287
, "9287" },
3923 { AR_SREV_VERSION_9271
, "9271" },
3926 /* For devices with external radios */
3930 } ath_rf_names
[] = {
3932 { AR_RAD5133_SREV_MAJOR
, "5133" },
3933 { AR_RAD5122_SREV_MAJOR
, "5122" },
3934 { AR_RAD2133_SREV_MAJOR
, "2133" },
3935 { AR_RAD2122_SREV_MAJOR
, "2122" }
3939 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3941 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version
)
3945 for (i
=0; i
<ARRAY_SIZE(ath_mac_bb_names
); i
++) {
3946 if (ath_mac_bb_names
[i
].version
== mac_bb_version
) {
3947 return ath_mac_bb_names
[i
].name
;
3955 * Return the RF name. "????" is returned if the RF is unknown.
3956 * Used for devices with external radios.
3958 static const char *ath9k_hw_rf_name(u16 rf_version
)
3962 for (i
=0; i
<ARRAY_SIZE(ath_rf_names
); i
++) {
3963 if (ath_rf_names
[i
].version
== rf_version
) {
3964 return ath_rf_names
[i
].name
;
3971 void ath9k_hw_name(struct ath_hw
*ah
, char *hw_name
, size_t len
)
3975 /* chipsets >= AR9280 are single-chip */
3976 if (AR_SREV_9280_10_OR_LATER(ah
)) {
3977 used
= snprintf(hw_name
, len
,
3978 "Atheros AR%s Rev:%x",
3979 ath9k_hw_mac_bb_name(ah
->hw_version
.macVersion
),
3980 ah
->hw_version
.macRev
);
3983 used
= snprintf(hw_name
, len
,
3984 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3985 ath9k_hw_mac_bb_name(ah
->hw_version
.macVersion
),
3986 ah
->hw_version
.macRev
,
3987 ath9k_hw_rf_name((ah
->hw_version
.analog5GhzRev
&
3988 AR_RADIO_SREV_MAJOR
)),
3989 ah
->hw_version
.phyRev
);
3992 hw_name
[used
] = '\0';
3994 EXPORT_SYMBOL(ath9k_hw_name
);