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Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / hw.c
1 /*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/io.h>
18 #include <asm/unaligned.h>
19
20 #include "hw.h"
21 #include "rc.h"
22 #include "initvals.h"
23
24 #define ATH9K_CLOCK_RATE_CCK 22
25 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
26 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
27
28 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
29 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan);
30 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
31 struct ar5416_eeprom_def *pEepData,
32 u32 reg, u32 value);
33
34 MODULE_AUTHOR("Atheros Communications");
35 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
36 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
37 MODULE_LICENSE("Dual BSD/GPL");
38
39 static int __init ath9k_init(void)
40 {
41 return 0;
42 }
43 module_init(ath9k_init);
44
45 static void __exit ath9k_exit(void)
46 {
47 return;
48 }
49 module_exit(ath9k_exit);
50
51 /********************/
52 /* Helper Functions */
53 /********************/
54
55 static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
56 {
57 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
58
59 if (!ah->curchan) /* should really check for CCK instead */
60 return usecs *ATH9K_CLOCK_RATE_CCK;
61 if (conf->channel->band == IEEE80211_BAND_2GHZ)
62 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
63 return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
64 }
65
66 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
67 {
68 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
69
70 if (conf_is_ht40(conf))
71 return ath9k_hw_mac_clks(ah, usecs) * 2;
72 else
73 return ath9k_hw_mac_clks(ah, usecs);
74 }
75
76 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
77 {
78 int i;
79
80 BUG_ON(timeout < AH_TIME_QUANTUM);
81
82 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
83 if ((REG_READ(ah, reg) & mask) == val)
84 return true;
85
86 udelay(AH_TIME_QUANTUM);
87 }
88
89 ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
90 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
91 timeout, reg, REG_READ(ah, reg), mask, val);
92
93 return false;
94 }
95 EXPORT_SYMBOL(ath9k_hw_wait);
96
97 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
98 {
99 u32 retval;
100 int i;
101
102 for (i = 0, retval = 0; i < n; i++) {
103 retval = (retval << 1) | (val & 1);
104 val >>= 1;
105 }
106 return retval;
107 }
108
109 bool ath9k_get_channel_edges(struct ath_hw *ah,
110 u16 flags, u16 *low,
111 u16 *high)
112 {
113 struct ath9k_hw_capabilities *pCap = &ah->caps;
114
115 if (flags & CHANNEL_5GHZ) {
116 *low = pCap->low_5ghz_chan;
117 *high = pCap->high_5ghz_chan;
118 return true;
119 }
120 if ((flags & CHANNEL_2GHZ)) {
121 *low = pCap->low_2ghz_chan;
122 *high = pCap->high_2ghz_chan;
123 return true;
124 }
125 return false;
126 }
127
128 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
129 u8 phy, int kbps,
130 u32 frameLen, u16 rateix,
131 bool shortPreamble)
132 {
133 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
134
135 if (kbps == 0)
136 return 0;
137
138 switch (phy) {
139 case WLAN_RC_PHY_CCK:
140 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
141 if (shortPreamble)
142 phyTime >>= 1;
143 numBits = frameLen << 3;
144 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
145 break;
146 case WLAN_RC_PHY_OFDM:
147 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
148 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
149 numBits = OFDM_PLCP_BITS + (frameLen << 3);
150 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
151 txTime = OFDM_SIFS_TIME_QUARTER
152 + OFDM_PREAMBLE_TIME_QUARTER
153 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
154 } else if (ah->curchan &&
155 IS_CHAN_HALF_RATE(ah->curchan)) {
156 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
157 numBits = OFDM_PLCP_BITS + (frameLen << 3);
158 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
159 txTime = OFDM_SIFS_TIME_HALF +
160 OFDM_PREAMBLE_TIME_HALF
161 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
162 } else {
163 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
164 numBits = OFDM_PLCP_BITS + (frameLen << 3);
165 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
166 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
167 + (numSymbols * OFDM_SYMBOL_TIME);
168 }
169 break;
170 default:
171 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
172 "Unknown phy %u (rate ix %u)\n", phy, rateix);
173 txTime = 0;
174 break;
175 }
176
177 return txTime;
178 }
179 EXPORT_SYMBOL(ath9k_hw_computetxtime);
180
181 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
182 struct ath9k_channel *chan,
183 struct chan_centers *centers)
184 {
185 int8_t extoff;
186
187 if (!IS_CHAN_HT40(chan)) {
188 centers->ctl_center = centers->ext_center =
189 centers->synth_center = chan->channel;
190 return;
191 }
192
193 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
194 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
195 centers->synth_center =
196 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
197 extoff = 1;
198 } else {
199 centers->synth_center =
200 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
201 extoff = -1;
202 }
203
204 centers->ctl_center =
205 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
206 /* 25 MHz spacing is supported by hw but not on upper layers */
207 centers->ext_center =
208 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
209 }
210
211 /******************/
212 /* Chip Revisions */
213 /******************/
214
215 static void ath9k_hw_read_revisions(struct ath_hw *ah)
216 {
217 u32 val;
218
219 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
220
221 if (val == 0xFF) {
222 val = REG_READ(ah, AR_SREV);
223 ah->hw_version.macVersion =
224 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
225 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
226 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
227 } else {
228 if (!AR_SREV_9100(ah))
229 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
230
231 ah->hw_version.macRev = val & AR_SREV_REVISION;
232
233 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
234 ah->is_pciexpress = true;
235 }
236 }
237
238 static int ath9k_hw_get_radiorev(struct ath_hw *ah)
239 {
240 u32 val;
241 int i;
242
243 REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
244
245 for (i = 0; i < 8; i++)
246 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
247 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
248 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
249
250 return ath9k_hw_reverse_bits(val, 8);
251 }
252
253 /************************************/
254 /* HW Attach, Detach, Init Routines */
255 /************************************/
256
257 static void ath9k_hw_disablepcie(struct ath_hw *ah)
258 {
259 if (AR_SREV_9100(ah))
260 return;
261
262 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
263 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
264 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
265 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
266 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
267 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
268 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
269 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
270 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
271
272 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
273 }
274
275 static bool ath9k_hw_chip_test(struct ath_hw *ah)
276 {
277 struct ath_common *common = ath9k_hw_common(ah);
278 u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
279 u32 regHold[2];
280 u32 patternData[4] = { 0x55555555,
281 0xaaaaaaaa,
282 0x66666666,
283 0x99999999 };
284 int i, j;
285
286 for (i = 0; i < 2; i++) {
287 u32 addr = regAddr[i];
288 u32 wrData, rdData;
289
290 regHold[i] = REG_READ(ah, addr);
291 for (j = 0; j < 0x100; j++) {
292 wrData = (j << 16) | j;
293 REG_WRITE(ah, addr, wrData);
294 rdData = REG_READ(ah, addr);
295 if (rdData != wrData) {
296 ath_print(common, ATH_DBG_FATAL,
297 "address test failed "
298 "addr: 0x%08x - wr:0x%08x != "
299 "rd:0x%08x\n",
300 addr, wrData, rdData);
301 return false;
302 }
303 }
304 for (j = 0; j < 4; j++) {
305 wrData = patternData[j];
306 REG_WRITE(ah, addr, wrData);
307 rdData = REG_READ(ah, addr);
308 if (wrData != rdData) {
309 ath_print(common, ATH_DBG_FATAL,
310 "address test failed "
311 "addr: 0x%08x - wr:0x%08x != "
312 "rd:0x%08x\n",
313 addr, wrData, rdData);
314 return false;
315 }
316 }
317 REG_WRITE(ah, regAddr[i], regHold[i]);
318 }
319 udelay(100);
320
321 return true;
322 }
323
324 static void ath9k_hw_init_config(struct ath_hw *ah)
325 {
326 int i;
327
328 ah->config.dma_beacon_response_time = 2;
329 ah->config.sw_beacon_response_time = 10;
330 ah->config.additional_swba_backoff = 0;
331 ah->config.ack_6mb = 0x0;
332 ah->config.cwm_ignore_extcca = 0;
333 ah->config.pcie_powersave_enable = 0;
334 ah->config.pcie_clock_req = 0;
335 ah->config.pcie_waen = 0;
336 ah->config.analog_shiftreg = 1;
337 ah->config.ofdm_trig_low = 200;
338 ah->config.ofdm_trig_high = 500;
339 ah->config.cck_trig_high = 200;
340 ah->config.cck_trig_low = 100;
341 ah->config.enable_ani = 1;
342
343 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
344 ah->config.spurchans[i][0] = AR_NO_SPUR;
345 ah->config.spurchans[i][1] = AR_NO_SPUR;
346 }
347
348 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
349 ah->config.ht_enable = 1;
350 else
351 ah->config.ht_enable = 0;
352
353 ah->config.rx_intr_mitigation = true;
354
355 /*
356 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
357 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
358 * This means we use it for all AR5416 devices, and the few
359 * minor PCI AR9280 devices out there.
360 *
361 * Serialization is required because these devices do not handle
362 * well the case of two concurrent reads/writes due to the latency
363 * involved. During one read/write another read/write can be issued
364 * on another CPU while the previous read/write may still be working
365 * on our hardware, if we hit this case the hardware poops in a loop.
366 * We prevent this by serializing reads and writes.
367 *
368 * This issue is not present on PCI-Express devices or pre-AR5416
369 * devices (legacy, 802.11abg).
370 */
371 if (num_possible_cpus() > 1)
372 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
373 }
374 EXPORT_SYMBOL(ath9k_hw_init);
375
376 static void ath9k_hw_init_defaults(struct ath_hw *ah)
377 {
378 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
379
380 regulatory->country_code = CTRY_DEFAULT;
381 regulatory->power_limit = MAX_RATE_POWER;
382 regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
383
384 ah->hw_version.magic = AR5416_MAGIC;
385 ah->hw_version.subvendorid = 0;
386
387 ah->ah_flags = 0;
388 if (ah->hw_version.devid == AR5416_AR9100_DEVID)
389 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
390 if (!AR_SREV_9100(ah))
391 ah->ah_flags = AH_USE_EEPROM;
392
393 ah->atim_window = 0;
394 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
395 ah->beacon_interval = 100;
396 ah->enable_32kHz_clock = DONT_USE_32KHZ;
397 ah->slottime = (u32) -1;
398 ah->globaltxtimeout = (u32) -1;
399 ah->power_mode = ATH9K_PM_UNDEFINED;
400 }
401
402 static int ath9k_hw_rf_claim(struct ath_hw *ah)
403 {
404 u32 val;
405
406 REG_WRITE(ah, AR_PHY(0), 0x00000007);
407
408 val = ath9k_hw_get_radiorev(ah);
409 switch (val & AR_RADIO_SREV_MAJOR) {
410 case 0:
411 val = AR_RAD5133_SREV_MAJOR;
412 break;
413 case AR_RAD5133_SREV_MAJOR:
414 case AR_RAD5122_SREV_MAJOR:
415 case AR_RAD2133_SREV_MAJOR:
416 case AR_RAD2122_SREV_MAJOR:
417 break;
418 default:
419 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
420 "Radio Chip Rev 0x%02X not supported\n",
421 val & AR_RADIO_SREV_MAJOR);
422 return -EOPNOTSUPP;
423 }
424
425 ah->hw_version.analog5GhzRev = val;
426
427 return 0;
428 }
429
430 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
431 {
432 struct ath_common *common = ath9k_hw_common(ah);
433 u32 sum;
434 int i;
435 u16 eeval;
436
437 sum = 0;
438 for (i = 0; i < 3; i++) {
439 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
440 sum += eeval;
441 common->macaddr[2 * i] = eeval >> 8;
442 common->macaddr[2 * i + 1] = eeval & 0xff;
443 }
444 if (sum == 0 || sum == 0xffff * 3)
445 return -EADDRNOTAVAIL;
446
447 return 0;
448 }
449
450 static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
451 {
452 u32 rxgain_type;
453
454 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
455 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
456
457 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
458 INIT_INI_ARRAY(&ah->iniModesRxGain,
459 ar9280Modes_backoff_13db_rxgain_9280_2,
460 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
461 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
462 INIT_INI_ARRAY(&ah->iniModesRxGain,
463 ar9280Modes_backoff_23db_rxgain_9280_2,
464 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
465 else
466 INIT_INI_ARRAY(&ah->iniModesRxGain,
467 ar9280Modes_original_rxgain_9280_2,
468 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
469 } else {
470 INIT_INI_ARRAY(&ah->iniModesRxGain,
471 ar9280Modes_original_rxgain_9280_2,
472 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
473 }
474 }
475
476 static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
477 {
478 u32 txgain_type;
479
480 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
481 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
482
483 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
484 INIT_INI_ARRAY(&ah->iniModesTxGain,
485 ar9280Modes_high_power_tx_gain_9280_2,
486 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
487 else
488 INIT_INI_ARRAY(&ah->iniModesTxGain,
489 ar9280Modes_original_tx_gain_9280_2,
490 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
491 } else {
492 INIT_INI_ARRAY(&ah->iniModesTxGain,
493 ar9280Modes_original_tx_gain_9280_2,
494 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
495 }
496 }
497
498 static int ath9k_hw_post_init(struct ath_hw *ah)
499 {
500 int ecode;
501
502 if (!ath9k_hw_chip_test(ah))
503 return -ENODEV;
504
505 ecode = ath9k_hw_rf_claim(ah);
506 if (ecode != 0)
507 return ecode;
508
509 ecode = ath9k_hw_eeprom_init(ah);
510 if (ecode != 0)
511 return ecode;
512
513 ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
514 "Eeprom VER: %d, REV: %d\n",
515 ah->eep_ops->get_eeprom_ver(ah),
516 ah->eep_ops->get_eeprom_rev(ah));
517
518 if (!AR_SREV_9280_10_OR_LATER(ah)) {
519 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
520 if (ecode) {
521 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
522 "Failed allocating banks for "
523 "external radio\n");
524 return ecode;
525 }
526 }
527
528 if (!AR_SREV_9100(ah)) {
529 ath9k_hw_ani_setup(ah);
530 ath9k_hw_ani_init(ah);
531 }
532
533 return 0;
534 }
535
536 static bool ath9k_hw_devid_supported(u16 devid)
537 {
538 switch (devid) {
539 case AR5416_DEVID_PCI:
540 case AR5416_DEVID_PCIE:
541 case AR5416_AR9100_DEVID:
542 case AR9160_DEVID_PCI:
543 case AR9280_DEVID_PCI:
544 case AR9280_DEVID_PCIE:
545 case AR9285_DEVID_PCIE:
546 case AR5416_DEVID_AR9287_PCI:
547 case AR5416_DEVID_AR9287_PCIE:
548 case AR9271_USB:
549 case AR2427_DEVID_PCIE:
550 return true;
551 default:
552 break;
553 }
554 return false;
555 }
556
557 static bool ath9k_hw_macversion_supported(u32 macversion)
558 {
559 switch (macversion) {
560 case AR_SREV_VERSION_5416_PCI:
561 case AR_SREV_VERSION_5416_PCIE:
562 case AR_SREV_VERSION_9160:
563 case AR_SREV_VERSION_9100:
564 case AR_SREV_VERSION_9280:
565 case AR_SREV_VERSION_9285:
566 case AR_SREV_VERSION_9287:
567 case AR_SREV_VERSION_9271:
568 return true;
569 default:
570 break;
571 }
572 return false;
573 }
574
575 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
576 {
577 if (AR_SREV_9160_10_OR_LATER(ah)) {
578 if (AR_SREV_9280_10_OR_LATER(ah)) {
579 ah->iq_caldata.calData = &iq_cal_single_sample;
580 ah->adcgain_caldata.calData =
581 &adc_gain_cal_single_sample;
582 ah->adcdc_caldata.calData =
583 &adc_dc_cal_single_sample;
584 ah->adcdc_calinitdata.calData =
585 &adc_init_dc_cal;
586 } else {
587 ah->iq_caldata.calData = &iq_cal_multi_sample;
588 ah->adcgain_caldata.calData =
589 &adc_gain_cal_multi_sample;
590 ah->adcdc_caldata.calData =
591 &adc_dc_cal_multi_sample;
592 ah->adcdc_calinitdata.calData =
593 &adc_init_dc_cal;
594 }
595 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
596 }
597 }
598
599 static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
600 {
601 if (AR_SREV_9271(ah)) {
602 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271,
603 ARRAY_SIZE(ar9271Modes_9271), 6);
604 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271,
605 ARRAY_SIZE(ar9271Common_9271), 2);
606 INIT_INI_ARRAY(&ah->iniModes_9271_1_0_only,
607 ar9271Modes_9271_1_0_only,
608 ARRAY_SIZE(ar9271Modes_9271_1_0_only), 6);
609 return;
610 }
611
612 if (AR_SREV_9287_11_OR_LATER(ah)) {
613 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
614 ARRAY_SIZE(ar9287Modes_9287_1_1), 6);
615 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
616 ARRAY_SIZE(ar9287Common_9287_1_1), 2);
617 if (ah->config.pcie_clock_req)
618 INIT_INI_ARRAY(&ah->iniPcieSerdes,
619 ar9287PciePhy_clkreq_off_L1_9287_1_1,
620 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2);
621 else
622 INIT_INI_ARRAY(&ah->iniPcieSerdes,
623 ar9287PciePhy_clkreq_always_on_L1_9287_1_1,
624 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1),
625 2);
626 } else if (AR_SREV_9287_10_OR_LATER(ah)) {
627 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0,
628 ARRAY_SIZE(ar9287Modes_9287_1_0), 6);
629 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0,
630 ARRAY_SIZE(ar9287Common_9287_1_0), 2);
631
632 if (ah->config.pcie_clock_req)
633 INIT_INI_ARRAY(&ah->iniPcieSerdes,
634 ar9287PciePhy_clkreq_off_L1_9287_1_0,
635 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2);
636 else
637 INIT_INI_ARRAY(&ah->iniPcieSerdes,
638 ar9287PciePhy_clkreq_always_on_L1_9287_1_0,
639 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0),
640 2);
641 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
642
643
644 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
645 ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
646 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
647 ARRAY_SIZE(ar9285Common_9285_1_2), 2);
648
649 if (ah->config.pcie_clock_req) {
650 INIT_INI_ARRAY(&ah->iniPcieSerdes,
651 ar9285PciePhy_clkreq_off_L1_9285_1_2,
652 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
653 } else {
654 INIT_INI_ARRAY(&ah->iniPcieSerdes,
655 ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
656 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
657 2);
658 }
659 } else if (AR_SREV_9285_10_OR_LATER(ah)) {
660 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
661 ARRAY_SIZE(ar9285Modes_9285), 6);
662 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
663 ARRAY_SIZE(ar9285Common_9285), 2);
664
665 if (ah->config.pcie_clock_req) {
666 INIT_INI_ARRAY(&ah->iniPcieSerdes,
667 ar9285PciePhy_clkreq_off_L1_9285,
668 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
669 } else {
670 INIT_INI_ARRAY(&ah->iniPcieSerdes,
671 ar9285PciePhy_clkreq_always_on_L1_9285,
672 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
673 }
674 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
675 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
676 ARRAY_SIZE(ar9280Modes_9280_2), 6);
677 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
678 ARRAY_SIZE(ar9280Common_9280_2), 2);
679
680 if (ah->config.pcie_clock_req) {
681 INIT_INI_ARRAY(&ah->iniPcieSerdes,
682 ar9280PciePhy_clkreq_off_L1_9280,
683 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
684 } else {
685 INIT_INI_ARRAY(&ah->iniPcieSerdes,
686 ar9280PciePhy_clkreq_always_on_L1_9280,
687 ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
688 }
689 INIT_INI_ARRAY(&ah->iniModesAdditional,
690 ar9280Modes_fast_clock_9280_2,
691 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
692 } else if (AR_SREV_9280_10_OR_LATER(ah)) {
693 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
694 ARRAY_SIZE(ar9280Modes_9280), 6);
695 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
696 ARRAY_SIZE(ar9280Common_9280), 2);
697 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
698 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
699 ARRAY_SIZE(ar5416Modes_9160), 6);
700 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
701 ARRAY_SIZE(ar5416Common_9160), 2);
702 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
703 ARRAY_SIZE(ar5416Bank0_9160), 2);
704 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
705 ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
706 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
707 ARRAY_SIZE(ar5416Bank1_9160), 2);
708 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
709 ARRAY_SIZE(ar5416Bank2_9160), 2);
710 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
711 ARRAY_SIZE(ar5416Bank3_9160), 3);
712 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
713 ARRAY_SIZE(ar5416Bank6_9160), 3);
714 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
715 ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
716 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
717 ARRAY_SIZE(ar5416Bank7_9160), 2);
718 if (AR_SREV_9160_11(ah)) {
719 INIT_INI_ARRAY(&ah->iniAddac,
720 ar5416Addac_91601_1,
721 ARRAY_SIZE(ar5416Addac_91601_1), 2);
722 } else {
723 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
724 ARRAY_SIZE(ar5416Addac_9160), 2);
725 }
726 } else if (AR_SREV_9100_OR_LATER(ah)) {
727 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
728 ARRAY_SIZE(ar5416Modes_9100), 6);
729 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
730 ARRAY_SIZE(ar5416Common_9100), 2);
731 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
732 ARRAY_SIZE(ar5416Bank0_9100), 2);
733 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
734 ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
735 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
736 ARRAY_SIZE(ar5416Bank1_9100), 2);
737 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
738 ARRAY_SIZE(ar5416Bank2_9100), 2);
739 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
740 ARRAY_SIZE(ar5416Bank3_9100), 3);
741 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
742 ARRAY_SIZE(ar5416Bank6_9100), 3);
743 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
744 ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
745 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
746 ARRAY_SIZE(ar5416Bank7_9100), 2);
747 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
748 ARRAY_SIZE(ar5416Addac_9100), 2);
749 } else {
750 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
751 ARRAY_SIZE(ar5416Modes), 6);
752 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
753 ARRAY_SIZE(ar5416Common), 2);
754 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
755 ARRAY_SIZE(ar5416Bank0), 2);
756 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
757 ARRAY_SIZE(ar5416BB_RfGain), 3);
758 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
759 ARRAY_SIZE(ar5416Bank1), 2);
760 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
761 ARRAY_SIZE(ar5416Bank2), 2);
762 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
763 ARRAY_SIZE(ar5416Bank3), 3);
764 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
765 ARRAY_SIZE(ar5416Bank6), 3);
766 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
767 ARRAY_SIZE(ar5416Bank6TPC), 3);
768 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
769 ARRAY_SIZE(ar5416Bank7), 2);
770 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
771 ARRAY_SIZE(ar5416Addac), 2);
772 }
773 }
774
775 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
776 {
777 if (AR_SREV_9287_11_OR_LATER(ah))
778 INIT_INI_ARRAY(&ah->iniModesRxGain,
779 ar9287Modes_rx_gain_9287_1_1,
780 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
781 else if (AR_SREV_9287_10(ah))
782 INIT_INI_ARRAY(&ah->iniModesRxGain,
783 ar9287Modes_rx_gain_9287_1_0,
784 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6);
785 else if (AR_SREV_9280_20(ah))
786 ath9k_hw_init_rxgain_ini(ah);
787
788 if (AR_SREV_9287_11_OR_LATER(ah)) {
789 INIT_INI_ARRAY(&ah->iniModesTxGain,
790 ar9287Modes_tx_gain_9287_1_1,
791 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
792 } else if (AR_SREV_9287_10(ah)) {
793 INIT_INI_ARRAY(&ah->iniModesTxGain,
794 ar9287Modes_tx_gain_9287_1_0,
795 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6);
796 } else if (AR_SREV_9280_20(ah)) {
797 ath9k_hw_init_txgain_ini(ah);
798 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
799 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
800
801 /* txgain table */
802 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
803 INIT_INI_ARRAY(&ah->iniModesTxGain,
804 ar9285Modes_high_power_tx_gain_9285_1_2,
805 ARRAY_SIZE(ar9285Modes_high_power_tx_gain_9285_1_2), 6);
806 } else {
807 INIT_INI_ARRAY(&ah->iniModesTxGain,
808 ar9285Modes_original_tx_gain_9285_1_2,
809 ARRAY_SIZE(ar9285Modes_original_tx_gain_9285_1_2), 6);
810 }
811
812 }
813 }
814
815 static void ath9k_hw_init_eeprom_fix(struct ath_hw *ah)
816 {
817 u32 i, j;
818
819 if (ah->hw_version.devid == AR9280_DEVID_PCI) {
820
821 /* EEPROM Fixup */
822 for (i = 0; i < ah->iniModes.ia_rows; i++) {
823 u32 reg = INI_RA(&ah->iniModes, i, 0);
824
825 for (j = 1; j < ah->iniModes.ia_columns; j++) {
826 u32 val = INI_RA(&ah->iniModes, i, j);
827
828 INI_RA(&ah->iniModes, i, j) =
829 ath9k_hw_ini_fixup(ah,
830 &ah->eeprom.def,
831 reg, val);
832 }
833 }
834 }
835 }
836
837 int ath9k_hw_init(struct ath_hw *ah)
838 {
839 struct ath_common *common = ath9k_hw_common(ah);
840 int r = 0;
841
842 if (!ath9k_hw_devid_supported(ah->hw_version.devid)) {
843 ath_print(common, ATH_DBG_FATAL,
844 "Unsupported device ID: 0x%0x\n",
845 ah->hw_version.devid);
846 return -EOPNOTSUPP;
847 }
848
849 ath9k_hw_init_defaults(ah);
850 ath9k_hw_init_config(ah);
851
852 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
853 ath_print(common, ATH_DBG_FATAL,
854 "Couldn't reset chip\n");
855 return -EIO;
856 }
857
858 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
859 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
860 return -EIO;
861 }
862
863 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
864 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
865 (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
866 ah->config.serialize_regmode =
867 SER_REG_MODE_ON;
868 } else {
869 ah->config.serialize_regmode =
870 SER_REG_MODE_OFF;
871 }
872 }
873
874 ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
875 ah->config.serialize_regmode);
876
877 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
878 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
879 else
880 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
881
882 if (!ath9k_hw_macversion_supported(ah->hw_version.macVersion)) {
883 ath_print(common, ATH_DBG_FATAL,
884 "Mac Chip Rev 0x%02x.%x is not supported by "
885 "this driver\n", ah->hw_version.macVersion,
886 ah->hw_version.macRev);
887 return -EOPNOTSUPP;
888 }
889
890 if (AR_SREV_9100(ah)) {
891 ah->iq_caldata.calData = &iq_cal_multi_sample;
892 ah->supp_cals = IQ_MISMATCH_CAL;
893 ah->is_pciexpress = false;
894 }
895
896 if (AR_SREV_9271(ah))
897 ah->is_pciexpress = false;
898
899 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
900
901 ath9k_hw_init_cal_settings(ah);
902
903 ah->ani_function = ATH9K_ANI_ALL;
904 if (AR_SREV_9280_10_OR_LATER(ah)) {
905 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
906 ah->ath9k_hw_rf_set_freq = &ath9k_hw_ar9280_set_channel;
907 ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_9280_spur_mitigate;
908 } else {
909 ah->ath9k_hw_rf_set_freq = &ath9k_hw_set_channel;
910 ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_spur_mitigate;
911 }
912
913 ath9k_hw_init_mode_regs(ah);
914
915 if (ah->is_pciexpress)
916 ath9k_hw_configpcipowersave(ah, 0, 0);
917 else
918 ath9k_hw_disablepcie(ah);
919
920 /* Support for Japan ch.14 (2484) spread */
921 if (AR_SREV_9287_11_OR_LATER(ah)) {
922 INIT_INI_ARRAY(&ah->iniCckfirNormal,
923 ar9287Common_normal_cck_fir_coeff_92871_1,
924 ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_92871_1), 2);
925 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
926 ar9287Common_japan_2484_cck_fir_coeff_92871_1,
927 ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_92871_1), 2);
928 }
929
930 r = ath9k_hw_post_init(ah);
931 if (r)
932 return r;
933
934 ath9k_hw_init_mode_gain_regs(ah);
935 r = ath9k_hw_fill_cap_info(ah);
936 if (r)
937 return r;
938
939 ath9k_hw_init_eeprom_fix(ah);
940
941 r = ath9k_hw_init_macaddr(ah);
942 if (r) {
943 ath_print(common, ATH_DBG_FATAL,
944 "Failed to initialize MAC address\n");
945 return r;
946 }
947
948 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
949 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
950 else
951 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
952
953 ath9k_init_nfcal_hist_buffer(ah);
954
955 common->state = ATH_HW_INITIALIZED;
956
957 return 0;
958 }
959
960 static void ath9k_hw_init_bb(struct ath_hw *ah,
961 struct ath9k_channel *chan)
962 {
963 u32 synthDelay;
964
965 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
966 if (IS_CHAN_B(chan))
967 synthDelay = (4 * synthDelay) / 22;
968 else
969 synthDelay /= 10;
970
971 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
972
973 udelay(synthDelay + BASE_ACTIVATE_DELAY);
974 }
975
976 static void ath9k_hw_init_qos(struct ath_hw *ah)
977 {
978 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
979 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
980
981 REG_WRITE(ah, AR_QOS_NO_ACK,
982 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
983 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
984 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
985
986 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
987 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
988 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
989 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
990 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
991 }
992
993 static void ath9k_hw_change_target_baud(struct ath_hw *ah, u32 freq, u32 baud)
994 {
995 u32 lcr;
996 u32 baud_divider = freq * 1000 * 1000 / 16 / baud;
997
998 lcr = REG_READ(ah , 0x5100c);
999 lcr |= 0x80;
1000
1001 REG_WRITE(ah, 0x5100c, lcr);
1002 REG_WRITE(ah, 0x51004, (baud_divider >> 8));
1003 REG_WRITE(ah, 0x51000, (baud_divider & 0xff));
1004
1005 lcr &= ~0x80;
1006 REG_WRITE(ah, 0x5100c, lcr);
1007 }
1008
1009 static void ath9k_hw_init_pll(struct ath_hw *ah,
1010 struct ath9k_channel *chan)
1011 {
1012 u32 pll;
1013
1014 if (AR_SREV_9100(ah)) {
1015 if (chan && IS_CHAN_5GHZ(chan))
1016 pll = 0x1450;
1017 else
1018 pll = 0x1458;
1019 } else {
1020 if (AR_SREV_9280_10_OR_LATER(ah)) {
1021 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1022
1023 if (chan && IS_CHAN_HALF_RATE(chan))
1024 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1025 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1026 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1027
1028 if (chan && IS_CHAN_5GHZ(chan)) {
1029 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
1030
1031
1032 if (AR_SREV_9280_20(ah)) {
1033 if (((chan->channel % 20) == 0)
1034 || ((chan->channel % 10) == 0))
1035 pll = 0x2850;
1036 else
1037 pll = 0x142c;
1038 }
1039 } else {
1040 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
1041 }
1042
1043 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1044
1045 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1046
1047 if (chan && IS_CHAN_HALF_RATE(chan))
1048 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1049 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1050 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1051
1052 if (chan && IS_CHAN_5GHZ(chan))
1053 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1054 else
1055 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1056 } else {
1057 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
1058
1059 if (chan && IS_CHAN_HALF_RATE(chan))
1060 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1061 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1062 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1063
1064 if (chan && IS_CHAN_5GHZ(chan))
1065 pll |= SM(0xa, AR_RTC_PLL_DIV);
1066 else
1067 pll |= SM(0xb, AR_RTC_PLL_DIV);
1068 }
1069 }
1070 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
1071
1072 /* Switch the core clock for ar9271 to 117Mhz */
1073 if (AR_SREV_9271(ah)) {
1074 if ((pll == 0x142c) || (pll == 0x2850) ) {
1075 udelay(500);
1076 /* set CLKOBS to output AHB clock */
1077 REG_WRITE(ah, 0x7020, 0xe);
1078 /*
1079 * 0x304: 117Mhz, ahb_ratio: 1x1
1080 * 0x306: 40Mhz, ahb_ratio: 1x1
1081 */
1082 REG_WRITE(ah, 0x50040, 0x304);
1083 /*
1084 * makes adjustments for the baud dividor to keep the
1085 * targetted baud rate based on the used core clock.
1086 */
1087 ath9k_hw_change_target_baud(ah, AR9271_CORE_CLOCK,
1088 AR9271_TARGET_BAUD_RATE);
1089 }
1090 }
1091
1092 udelay(RTC_PLL_SETTLE_DELAY);
1093
1094 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1095 }
1096
1097 static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
1098 {
1099 int rx_chainmask, tx_chainmask;
1100
1101 rx_chainmask = ah->rxchainmask;
1102 tx_chainmask = ah->txchainmask;
1103
1104 switch (rx_chainmask) {
1105 case 0x5:
1106 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1107 AR_PHY_SWAP_ALT_CHAIN);
1108 case 0x3:
1109 if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) {
1110 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1111 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1112 break;
1113 }
1114 case 0x1:
1115 case 0x2:
1116 case 0x7:
1117 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1118 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1119 break;
1120 default:
1121 break;
1122 }
1123
1124 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1125 if (tx_chainmask == 0x5) {
1126 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1127 AR_PHY_SWAP_ALT_CHAIN);
1128 }
1129 if (AR_SREV_9100(ah))
1130 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1131 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1132 }
1133
1134 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
1135 enum nl80211_iftype opmode)
1136 {
1137 ah->mask_reg = AR_IMR_TXERR |
1138 AR_IMR_TXURN |
1139 AR_IMR_RXERR |
1140 AR_IMR_RXORN |
1141 AR_IMR_BCNMISC;
1142
1143 if (ah->config.rx_intr_mitigation)
1144 ah->mask_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1145 else
1146 ah->mask_reg |= AR_IMR_RXOK;
1147
1148 ah->mask_reg |= AR_IMR_TXOK;
1149
1150 if (opmode == NL80211_IFTYPE_AP)
1151 ah->mask_reg |= AR_IMR_MIB;
1152
1153 REG_WRITE(ah, AR_IMR, ah->mask_reg);
1154 REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
1155
1156 if (!AR_SREV_9100(ah)) {
1157 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1158 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1159 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1160 }
1161 }
1162
1163 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
1164 {
1165 u32 val = ath9k_hw_mac_to_clks(ah, us);
1166 val = min(val, (u32) 0xFFFF);
1167 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
1168 }
1169
1170 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1171 {
1172 u32 val = ath9k_hw_mac_to_clks(ah, us);
1173 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
1174 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
1175 }
1176
1177 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1178 {
1179 u32 val = ath9k_hw_mac_to_clks(ah, us);
1180 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
1181 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
1182 }
1183
1184 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1185 {
1186 if (tu > 0xFFFF) {
1187 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
1188 "bad global tx timeout %u\n", tu);
1189 ah->globaltxtimeout = (u32) -1;
1190 return false;
1191 } else {
1192 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1193 ah->globaltxtimeout = tu;
1194 return true;
1195 }
1196 }
1197
1198 void ath9k_hw_init_global_settings(struct ath_hw *ah)
1199 {
1200 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
1201 int acktimeout;
1202 int slottime;
1203 int sifstime;
1204
1205 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
1206 ah->misc_mode);
1207
1208 if (ah->misc_mode != 0)
1209 REG_WRITE(ah, AR_PCU_MISC,
1210 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
1211
1212 if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
1213 sifstime = 16;
1214 else
1215 sifstime = 10;
1216
1217 /* As defined by IEEE 802.11-2007 17.3.8.6 */
1218 slottime = ah->slottime + 3 * ah->coverage_class;
1219 acktimeout = slottime + sifstime;
1220
1221 /*
1222 * Workaround for early ACK timeouts, add an offset to match the
1223 * initval's 64us ack timeout value.
1224 * This was initially only meant to work around an issue with delayed
1225 * BA frames in some implementations, but it has been found to fix ACK
1226 * timeout issues in other cases as well.
1227 */
1228 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
1229 acktimeout += 64 - sifstime - ah->slottime;
1230
1231 ath9k_hw_setslottime(ah, slottime);
1232 ath9k_hw_set_ack_timeout(ah, acktimeout);
1233 ath9k_hw_set_cts_timeout(ah, acktimeout);
1234 if (ah->globaltxtimeout != (u32) -1)
1235 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1236 }
1237 EXPORT_SYMBOL(ath9k_hw_init_global_settings);
1238
1239 void ath9k_hw_deinit(struct ath_hw *ah)
1240 {
1241 struct ath_common *common = ath9k_hw_common(ah);
1242
1243 if (common->state <= ATH_HW_INITIALIZED)
1244 goto free_hw;
1245
1246 if (!AR_SREV_9100(ah))
1247 ath9k_hw_ani_disable(ah);
1248
1249 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1250
1251 free_hw:
1252 if (!AR_SREV_9280_10_OR_LATER(ah))
1253 ath9k_hw_rf_free_ext_banks(ah);
1254 kfree(ah);
1255 ah = NULL;
1256 }
1257 EXPORT_SYMBOL(ath9k_hw_deinit);
1258
1259 /*******/
1260 /* INI */
1261 /*******/
1262
1263 static void ath9k_hw_override_ini(struct ath_hw *ah,
1264 struct ath9k_channel *chan)
1265 {
1266 u32 val;
1267
1268 if (AR_SREV_9271(ah)) {
1269 /*
1270 * Enable spectral scan to solution for issues with stuck
1271 * beacons on AR9271 1.0. The beacon stuck issue is not seeon on
1272 * AR9271 1.1
1273 */
1274 if (AR_SREV_9271_10(ah)) {
1275 val = REG_READ(ah, AR_PHY_SPECTRAL_SCAN) |
1276 AR_PHY_SPECTRAL_SCAN_ENABLE;
1277 REG_WRITE(ah, AR_PHY_SPECTRAL_SCAN, val);
1278 }
1279 else if (AR_SREV_9271_11(ah))
1280 /*
1281 * change AR_PHY_RF_CTL3 setting to fix MAC issue
1282 * present on AR9271 1.1
1283 */
1284 REG_WRITE(ah, AR_PHY_RF_CTL3, 0x3a020001);
1285 return;
1286 }
1287
1288 /*
1289 * Set the RX_ABORT and RX_DIS and clear if off only after
1290 * RXE is set for MAC. This prevents frames with corrupted
1291 * descriptor status.
1292 */
1293 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1294
1295 if (AR_SREV_9280_10_OR_LATER(ah)) {
1296 val = REG_READ(ah, AR_PCU_MISC_MODE2) &
1297 (~AR_PCU_MISC_MODE2_HWWAR1);
1298
1299 if (AR_SREV_9287_10_OR_LATER(ah))
1300 val = val & (~AR_PCU_MISC_MODE2_HWWAR2);
1301
1302 REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
1303 }
1304
1305 if (!AR_SREV_5416_20_OR_LATER(ah) ||
1306 AR_SREV_9280_10_OR_LATER(ah))
1307 return;
1308 /*
1309 * Disable BB clock gating
1310 * Necessary to avoid issues on AR5416 2.0
1311 */
1312 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1313 }
1314
1315 static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah,
1316 struct ar5416_eeprom_def *pEepData,
1317 u32 reg, u32 value)
1318 {
1319 struct base_eep_header *pBase = &(pEepData->baseEepHeader);
1320 struct ath_common *common = ath9k_hw_common(ah);
1321
1322 switch (ah->hw_version.devid) {
1323 case AR9280_DEVID_PCI:
1324 if (reg == 0x7894) {
1325 ath_print(common, ATH_DBG_EEPROM,
1326 "ini VAL: %x EEPROM: %x\n", value,
1327 (pBase->version & 0xff));
1328
1329 if ((pBase->version & 0xff) > 0x0a) {
1330 ath_print(common, ATH_DBG_EEPROM,
1331 "PWDCLKIND: %d\n",
1332 pBase->pwdclkind);
1333 value &= ~AR_AN_TOP2_PWDCLKIND;
1334 value |= AR_AN_TOP2_PWDCLKIND &
1335 (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1336 } else {
1337 ath_print(common, ATH_DBG_EEPROM,
1338 "PWDCLKIND Earlier Rev\n");
1339 }
1340
1341 ath_print(common, ATH_DBG_EEPROM,
1342 "final ini VAL: %x\n", value);
1343 }
1344 break;
1345 }
1346
1347 return value;
1348 }
1349
1350 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
1351 struct ar5416_eeprom_def *pEepData,
1352 u32 reg, u32 value)
1353 {
1354 if (ah->eep_map == EEP_MAP_4KBITS)
1355 return value;
1356 else
1357 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
1358 }
1359
1360 static void ath9k_olc_init(struct ath_hw *ah)
1361 {
1362 u32 i;
1363
1364 if (OLC_FOR_AR9287_10_LATER) {
1365 REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9,
1366 AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL);
1367 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TXPC0,
1368 AR9287_AN_TXPC0_TXPCMODE,
1369 AR9287_AN_TXPC0_TXPCMODE_S,
1370 AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE);
1371 udelay(100);
1372 } else {
1373 for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
1374 ah->originalGain[i] =
1375 MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
1376 AR_PHY_TX_GAIN);
1377 ah->PDADCdelta = 0;
1378 }
1379 }
1380
1381 static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg,
1382 struct ath9k_channel *chan)
1383 {
1384 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1385
1386 if (IS_CHAN_B(chan))
1387 ctl |= CTL_11B;
1388 else if (IS_CHAN_G(chan))
1389 ctl |= CTL_11G;
1390 else
1391 ctl |= CTL_11A;
1392
1393 return ctl;
1394 }
1395
1396 static int ath9k_hw_process_ini(struct ath_hw *ah,
1397 struct ath9k_channel *chan)
1398 {
1399 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1400 int i, regWrites = 0;
1401 struct ieee80211_channel *channel = chan->chan;
1402 u32 modesIndex, freqIndex;
1403
1404 switch (chan->chanmode) {
1405 case CHANNEL_A:
1406 case CHANNEL_A_HT20:
1407 modesIndex = 1;
1408 freqIndex = 1;
1409 break;
1410 case CHANNEL_A_HT40PLUS:
1411 case CHANNEL_A_HT40MINUS:
1412 modesIndex = 2;
1413 freqIndex = 1;
1414 break;
1415 case CHANNEL_G:
1416 case CHANNEL_G_HT20:
1417 case CHANNEL_B:
1418 modesIndex = 4;
1419 freqIndex = 2;
1420 break;
1421 case CHANNEL_G_HT40PLUS:
1422 case CHANNEL_G_HT40MINUS:
1423 modesIndex = 3;
1424 freqIndex = 2;
1425 break;
1426
1427 default:
1428 return -EINVAL;
1429 }
1430
1431 REG_WRITE(ah, AR_PHY(0), 0x00000007);
1432 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1433 ah->eep_ops->set_addac(ah, chan);
1434
1435 if (AR_SREV_5416_22_OR_LATER(ah)) {
1436 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
1437 } else {
1438 struct ar5416IniArray temp;
1439 u32 addacSize =
1440 sizeof(u32) * ah->iniAddac.ia_rows *
1441 ah->iniAddac.ia_columns;
1442
1443 memcpy(ah->addac5416_21,
1444 ah->iniAddac.ia_array, addacSize);
1445
1446 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
1447
1448 temp.ia_array = ah->addac5416_21;
1449 temp.ia_columns = ah->iniAddac.ia_columns;
1450 temp.ia_rows = ah->iniAddac.ia_rows;
1451 REG_WRITE_ARRAY(&temp, 1, regWrites);
1452 }
1453
1454 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1455
1456 for (i = 0; i < ah->iniModes.ia_rows; i++) {
1457 u32 reg = INI_RA(&ah->iniModes, i, 0);
1458 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
1459
1460 REG_WRITE(ah, reg, val);
1461
1462 if (reg >= 0x7800 && reg < 0x78a0
1463 && ah->config.analog_shiftreg) {
1464 udelay(100);
1465 }
1466
1467 DO_DELAY(regWrites);
1468 }
1469
1470 if (AR_SREV_9280(ah) || AR_SREV_9287_10_OR_LATER(ah))
1471 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
1472
1473 if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
1474 AR_SREV_9287_10_OR_LATER(ah))
1475 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1476
1477 for (i = 0; i < ah->iniCommon.ia_rows; i++) {
1478 u32 reg = INI_RA(&ah->iniCommon, i, 0);
1479 u32 val = INI_RA(&ah->iniCommon, i, 1);
1480
1481 REG_WRITE(ah, reg, val);
1482
1483 if (reg >= 0x7800 && reg < 0x78a0
1484 && ah->config.analog_shiftreg) {
1485 udelay(100);
1486 }
1487
1488 DO_DELAY(regWrites);
1489 }
1490
1491 ath9k_hw_write_regs(ah, freqIndex, regWrites);
1492
1493 if (AR_SREV_9271_10(ah))
1494 REG_WRITE_ARRAY(&ah->iniModes_9271_1_0_only,
1495 modesIndex, regWrites);
1496
1497 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1498 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
1499 regWrites);
1500 }
1501
1502 ath9k_hw_override_ini(ah, chan);
1503 ath9k_hw_set_regs(ah, chan);
1504 ath9k_hw_init_chain_masks(ah);
1505
1506 if (OLC_FOR_AR9280_20_LATER)
1507 ath9k_olc_init(ah);
1508
1509 ah->eep_ops->set_txpower(ah, chan,
1510 ath9k_regd_get_ctl(regulatory, chan),
1511 channel->max_antenna_gain * 2,
1512 channel->max_power * 2,
1513 min((u32) MAX_RATE_POWER,
1514 (u32) regulatory->power_limit));
1515
1516 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1517 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1518 "ar5416SetRfRegs failed\n");
1519 return -EIO;
1520 }
1521
1522 return 0;
1523 }
1524
1525 /****************************************/
1526 /* Reset and Channel Switching Routines */
1527 /****************************************/
1528
1529 static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
1530 {
1531 u32 rfMode = 0;
1532
1533 if (chan == NULL)
1534 return;
1535
1536 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1537 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1538
1539 if (!AR_SREV_9280_10_OR_LATER(ah))
1540 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1541 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1542
1543 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1544 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1545
1546 REG_WRITE(ah, AR_PHY_MODE, rfMode);
1547 }
1548
1549 static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
1550 {
1551 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1552 }
1553
1554 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1555 {
1556 u32 regval;
1557
1558 /*
1559 * set AHB_MODE not to do cacheline prefetches
1560 */
1561 regval = REG_READ(ah, AR_AHB_MODE);
1562 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1563
1564 /*
1565 * let mac dma reads be in 128 byte chunks
1566 */
1567 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1568 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1569
1570 /*
1571 * Restore TX Trigger Level to its pre-reset value.
1572 * The initial value depends on whether aggregation is enabled, and is
1573 * adjusted whenever underruns are detected.
1574 */
1575 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1576
1577 /*
1578 * let mac dma writes be in 128 byte chunks
1579 */
1580 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1581 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1582
1583 /*
1584 * Setup receive FIFO threshold to hold off TX activities
1585 */
1586 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1587
1588 /*
1589 * reduce the number of usable entries in PCU TXBUF to avoid
1590 * wrap around issues.
1591 */
1592 if (AR_SREV_9285(ah)) {
1593 /* For AR9285 the number of Fifos are reduced to half.
1594 * So set the usable tx buf size also to half to
1595 * avoid data/delimiter underruns
1596 */
1597 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1598 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1599 } else if (!AR_SREV_9271(ah)) {
1600 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1601 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1602 }
1603 }
1604
1605 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1606 {
1607 u32 val;
1608
1609 val = REG_READ(ah, AR_STA_ID1);
1610 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1611 switch (opmode) {
1612 case NL80211_IFTYPE_AP:
1613 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1614 | AR_STA_ID1_KSRCH_MODE);
1615 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1616 break;
1617 case NL80211_IFTYPE_ADHOC:
1618 case NL80211_IFTYPE_MESH_POINT:
1619 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1620 | AR_STA_ID1_KSRCH_MODE);
1621 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1622 break;
1623 case NL80211_IFTYPE_STATION:
1624 case NL80211_IFTYPE_MONITOR:
1625 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1626 break;
1627 }
1628 }
1629
1630 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
1631 u32 coef_scaled,
1632 u32 *coef_mantissa,
1633 u32 *coef_exponent)
1634 {
1635 u32 coef_exp, coef_man;
1636
1637 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1638 if ((coef_scaled >> coef_exp) & 0x1)
1639 break;
1640
1641 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1642
1643 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1644
1645 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1646 *coef_exponent = coef_exp - 16;
1647 }
1648
1649 static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
1650 struct ath9k_channel *chan)
1651 {
1652 u32 coef_scaled, ds_coef_exp, ds_coef_man;
1653 u32 clockMhzScaled = 0x64000000;
1654 struct chan_centers centers;
1655
1656 if (IS_CHAN_HALF_RATE(chan))
1657 clockMhzScaled = clockMhzScaled >> 1;
1658 else if (IS_CHAN_QUARTER_RATE(chan))
1659 clockMhzScaled = clockMhzScaled >> 2;
1660
1661 ath9k_hw_get_channel_centers(ah, chan, &centers);
1662 coef_scaled = clockMhzScaled / centers.synth_center;
1663
1664 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1665 &ds_coef_exp);
1666
1667 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1668 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1669 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1670 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1671
1672 coef_scaled = (9 * coef_scaled) / 10;
1673
1674 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1675 &ds_coef_exp);
1676
1677 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1678 AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1679 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1680 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1681 }
1682
1683 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1684 {
1685 u32 rst_flags;
1686 u32 tmpReg;
1687
1688 if (AR_SREV_9100(ah)) {
1689 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
1690 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
1691 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1692 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1693 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1694 }
1695
1696 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1697 AR_RTC_FORCE_WAKE_ON_INT);
1698
1699 if (AR_SREV_9100(ah)) {
1700 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1701 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1702 } else {
1703 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1704 if (tmpReg &
1705 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1706 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1707 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1708 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1709 } else {
1710 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1711 }
1712
1713 rst_flags = AR_RTC_RC_MAC_WARM;
1714 if (type == ATH9K_RESET_COLD)
1715 rst_flags |= AR_RTC_RC_MAC_COLD;
1716 }
1717
1718 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1719 udelay(50);
1720
1721 REG_WRITE(ah, AR_RTC_RC, 0);
1722 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1723 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1724 "RTC stuck in MAC reset\n");
1725 return false;
1726 }
1727
1728 if (!AR_SREV_9100(ah))
1729 REG_WRITE(ah, AR_RC, 0);
1730
1731 if (AR_SREV_9100(ah))
1732 udelay(50);
1733
1734 return true;
1735 }
1736
1737 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1738 {
1739 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1740 AR_RTC_FORCE_WAKE_ON_INT);
1741
1742 if (!AR_SREV_9100(ah))
1743 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1744
1745 REG_WRITE(ah, AR_RTC_RESET, 0);
1746 udelay(2);
1747
1748 if (!AR_SREV_9100(ah))
1749 REG_WRITE(ah, AR_RC, 0);
1750
1751 REG_WRITE(ah, AR_RTC_RESET, 1);
1752
1753 if (!ath9k_hw_wait(ah,
1754 AR_RTC_STATUS,
1755 AR_RTC_STATUS_M,
1756 AR_RTC_STATUS_ON,
1757 AH_WAIT_TIMEOUT)) {
1758 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1759 "RTC not waking up\n");
1760 return false;
1761 }
1762
1763 ath9k_hw_read_revisions(ah);
1764
1765 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1766 }
1767
1768 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1769 {
1770 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1771 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1772
1773 switch (type) {
1774 case ATH9K_RESET_POWER_ON:
1775 return ath9k_hw_set_reset_power_on(ah);
1776 case ATH9K_RESET_WARM:
1777 case ATH9K_RESET_COLD:
1778 return ath9k_hw_set_reset(ah, type);
1779 default:
1780 return false;
1781 }
1782 }
1783
1784 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan)
1785 {
1786 u32 phymode;
1787 u32 enableDacFifo = 0;
1788
1789 if (AR_SREV_9285_10_OR_LATER(ah))
1790 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1791 AR_PHY_FC_ENABLE_DAC_FIFO);
1792
1793 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1794 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
1795
1796 if (IS_CHAN_HT40(chan)) {
1797 phymode |= AR_PHY_FC_DYN2040_EN;
1798
1799 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1800 (chan->chanmode == CHANNEL_G_HT40PLUS))
1801 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1802
1803 }
1804 REG_WRITE(ah, AR_PHY_TURBO, phymode);
1805
1806 ath9k_hw_set11nmac2040(ah);
1807
1808 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1809 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1810 }
1811
1812 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1813 struct ath9k_channel *chan)
1814 {
1815 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
1816 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1817 return false;
1818 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1819 return false;
1820
1821 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1822 return false;
1823
1824 ah->chip_fullsleep = false;
1825 ath9k_hw_init_pll(ah, chan);
1826 ath9k_hw_set_rfmode(ah, chan);
1827
1828 return true;
1829 }
1830
1831 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1832 struct ath9k_channel *chan)
1833 {
1834 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1835 struct ath_common *common = ath9k_hw_common(ah);
1836 struct ieee80211_channel *channel = chan->chan;
1837 u32 synthDelay, qnum;
1838 int r;
1839
1840 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1841 if (ath9k_hw_numtxpending(ah, qnum)) {
1842 ath_print(common, ATH_DBG_QUEUE,
1843 "Transmit frames pending on "
1844 "queue %d\n", qnum);
1845 return false;
1846 }
1847 }
1848
1849 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1850 if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1851 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
1852 ath_print(common, ATH_DBG_FATAL,
1853 "Could not kill baseband RX\n");
1854 return false;
1855 }
1856
1857 ath9k_hw_set_regs(ah, chan);
1858
1859 r = ah->ath9k_hw_rf_set_freq(ah, chan);
1860 if (r) {
1861 ath_print(common, ATH_DBG_FATAL,
1862 "Failed to set channel\n");
1863 return false;
1864 }
1865
1866 ah->eep_ops->set_txpower(ah, chan,
1867 ath9k_regd_get_ctl(regulatory, chan),
1868 channel->max_antenna_gain * 2,
1869 channel->max_power * 2,
1870 min((u32) MAX_RATE_POWER,
1871 (u32) regulatory->power_limit));
1872
1873 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1874 if (IS_CHAN_B(chan))
1875 synthDelay = (4 * synthDelay) / 22;
1876 else
1877 synthDelay /= 10;
1878
1879 udelay(synthDelay + BASE_ACTIVATE_DELAY);
1880
1881 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1882
1883 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1884 ath9k_hw_set_delta_slope(ah, chan);
1885
1886 ah->ath9k_hw_spur_mitigate_freq(ah, chan);
1887
1888 if (!chan->oneTimeCalsDone)
1889 chan->oneTimeCalsDone = true;
1890
1891 return true;
1892 }
1893
1894 static void ath9k_enable_rfkill(struct ath_hw *ah)
1895 {
1896 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
1897 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
1898
1899 REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
1900 AR_GPIO_INPUT_MUX2_RFSILENT);
1901
1902 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
1903 REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
1904 }
1905
1906 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1907 bool bChannelChange)
1908 {
1909 struct ath_common *common = ath9k_hw_common(ah);
1910 u32 saveLedState;
1911 struct ath9k_channel *curchan = ah->curchan;
1912 u32 saveDefAntenna;
1913 u32 macStaId1;
1914 u64 tsf = 0;
1915 int i, rx_chainmask, r;
1916
1917 ah->txchainmask = common->tx_chainmask;
1918 ah->rxchainmask = common->rx_chainmask;
1919
1920 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1921 return -EIO;
1922
1923 if (curchan && !ah->chip_fullsleep)
1924 ath9k_hw_getnf(ah, curchan);
1925
1926 if (bChannelChange &&
1927 (ah->chip_fullsleep != true) &&
1928 (ah->curchan != NULL) &&
1929 (chan->channel != ah->curchan->channel) &&
1930 ((chan->channelFlags & CHANNEL_ALL) ==
1931 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
1932 !(AR_SREV_9280(ah) || IS_CHAN_A_5MHZ_SPACED(chan) ||
1933 IS_CHAN_A_5MHZ_SPACED(ah->curchan))) {
1934
1935 if (ath9k_hw_channel_change(ah, chan)) {
1936 ath9k_hw_loadnf(ah, ah->curchan);
1937 ath9k_hw_start_nfcal(ah);
1938 return 0;
1939 }
1940 }
1941
1942 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1943 if (saveDefAntenna == 0)
1944 saveDefAntenna = 1;
1945
1946 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1947
1948 /* For chips on which RTC reset is done, save TSF before it gets cleared */
1949 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1950 tsf = ath9k_hw_gettsf64(ah);
1951
1952 saveLedState = REG_READ(ah, AR_CFG_LED) &
1953 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1954 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1955
1956 ath9k_hw_mark_phy_inactive(ah);
1957
1958 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1959 REG_WRITE(ah,
1960 AR9271_RESET_POWER_DOWN_CONTROL,
1961 AR9271_RADIO_RF_RST);
1962 udelay(50);
1963 }
1964
1965 if (!ath9k_hw_chip_reset(ah, chan)) {
1966 ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n");
1967 return -EINVAL;
1968 }
1969
1970 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1971 ah->htc_reset_init = false;
1972 REG_WRITE(ah,
1973 AR9271_RESET_POWER_DOWN_CONTROL,
1974 AR9271_GATE_MAC_CTL);
1975 udelay(50);
1976 }
1977
1978 /* Restore TSF */
1979 if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1980 ath9k_hw_settsf64(ah, tsf);
1981
1982 if (AR_SREV_9280_10_OR_LATER(ah))
1983 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1984
1985 if (AR_SREV_9287_12_OR_LATER(ah)) {
1986 /* Enable ASYNC FIFO */
1987 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
1988 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
1989 REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
1990 REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
1991 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
1992 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
1993 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
1994 }
1995 r = ath9k_hw_process_ini(ah, chan);
1996 if (r)
1997 return r;
1998
1999 /* Setup MFP options for CCMP */
2000 if (AR_SREV_9280_20_OR_LATER(ah)) {
2001 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
2002 * frames when constructing CCMP AAD. */
2003 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
2004 0xc7ff);
2005 ah->sw_mgmt_crypto = false;
2006 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
2007 /* Disable hardware crypto for management frames */
2008 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
2009 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
2010 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2011 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
2012 ah->sw_mgmt_crypto = true;
2013 } else
2014 ah->sw_mgmt_crypto = true;
2015
2016 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2017 ath9k_hw_set_delta_slope(ah, chan);
2018
2019 ah->ath9k_hw_spur_mitigate_freq(ah, chan);
2020 ah->eep_ops->set_board_values(ah, chan);
2021
2022 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
2023 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
2024 | macStaId1
2025 | AR_STA_ID1_RTS_USE_DEF
2026 | (ah->config.
2027 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2028 | ah->sta_id1_defaults);
2029 ath9k_hw_set_operating_mode(ah, ah->opmode);
2030
2031 ath_hw_setbssidmask(common);
2032
2033 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2034
2035 ath9k_hw_write_associd(ah);
2036
2037 REG_WRITE(ah, AR_ISR, ~0);
2038
2039 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2040
2041 r = ah->ath9k_hw_rf_set_freq(ah, chan);
2042 if (r)
2043 return r;
2044
2045 for (i = 0; i < AR_NUM_DCU; i++)
2046 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2047
2048 ah->intr_txqs = 0;
2049 for (i = 0; i < ah->caps.total_queues; i++)
2050 ath9k_hw_resettxqueue(ah, i);
2051
2052 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
2053 ath9k_hw_init_qos(ah);
2054
2055 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2056 ath9k_enable_rfkill(ah);
2057
2058 ath9k_hw_init_global_settings(ah);
2059
2060 if (AR_SREV_9287_12_OR_LATER(ah)) {
2061 REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
2062 AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
2063 REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
2064 AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
2065 REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
2066 AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
2067
2068 REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
2069 REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
2070
2071 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
2072 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
2073 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
2074 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
2075 }
2076 if (AR_SREV_9287_12_OR_LATER(ah)) {
2077 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2078 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
2079 }
2080
2081 REG_WRITE(ah, AR_STA_ID1,
2082 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2083
2084 ath9k_hw_set_dma(ah);
2085
2086 REG_WRITE(ah, AR_OBS, 8);
2087
2088 if (ah->config.rx_intr_mitigation) {
2089 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2090 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2091 }
2092
2093 ath9k_hw_init_bb(ah, chan);
2094
2095 if (!ath9k_hw_init_cal(ah, chan))
2096 return -EIO;
2097
2098 rx_chainmask = ah->rxchainmask;
2099 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2100 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2101 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2102 }
2103
2104 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2105
2106 /*
2107 * For big endian systems turn on swapping for descriptors
2108 */
2109 if (AR_SREV_9100(ah)) {
2110 u32 mask;
2111 mask = REG_READ(ah, AR_CFG);
2112 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2113 ath_print(common, ATH_DBG_RESET,
2114 "CFG Byte Swap Set 0x%x\n", mask);
2115 } else {
2116 mask =
2117 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2118 REG_WRITE(ah, AR_CFG, mask);
2119 ath_print(common, ATH_DBG_RESET,
2120 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
2121 }
2122 } else {
2123 /* Configure AR9271 target WLAN */
2124 if (AR_SREV_9271(ah))
2125 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
2126 #ifdef __BIG_ENDIAN
2127 else
2128 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2129 #endif
2130 }
2131
2132 if (ah->btcoex_hw.enabled)
2133 ath9k_hw_btcoex_enable(ah);
2134
2135 return 0;
2136 }
2137 EXPORT_SYMBOL(ath9k_hw_reset);
2138
2139 /************************/
2140 /* Key Cache Management */
2141 /************************/
2142
2143 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
2144 {
2145 u32 keyType;
2146
2147 if (entry >= ah->caps.keycache_size) {
2148 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2149 "keychache entry %u out of range\n", entry);
2150 return false;
2151 }
2152
2153 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
2154
2155 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2156 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2157 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2158 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2159 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2160 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2161 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2162 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
2163
2164 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2165 u16 micentry = entry + 64;
2166
2167 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2168 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2169 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2170 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2171
2172 }
2173
2174 return true;
2175 }
2176 EXPORT_SYMBOL(ath9k_hw_keyreset);
2177
2178 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
2179 {
2180 u32 macHi, macLo;
2181
2182 if (entry >= ah->caps.keycache_size) {
2183 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2184 "keychache entry %u out of range\n", entry);
2185 return false;
2186 }
2187
2188 if (mac != NULL) {
2189 macHi = (mac[5] << 8) | mac[4];
2190 macLo = (mac[3] << 24) |
2191 (mac[2] << 16) |
2192 (mac[1] << 8) |
2193 mac[0];
2194 macLo >>= 1;
2195 macLo |= (macHi & 1) << 31;
2196 macHi >>= 1;
2197 } else {
2198 macLo = macHi = 0;
2199 }
2200 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2201 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
2202
2203 return true;
2204 }
2205 EXPORT_SYMBOL(ath9k_hw_keysetmac);
2206
2207 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2208 const struct ath9k_keyval *k,
2209 const u8 *mac)
2210 {
2211 const struct ath9k_hw_capabilities *pCap = &ah->caps;
2212 struct ath_common *common = ath9k_hw_common(ah);
2213 u32 key0, key1, key2, key3, key4;
2214 u32 keyType;
2215
2216 if (entry >= pCap->keycache_size) {
2217 ath_print(common, ATH_DBG_FATAL,
2218 "keycache entry %u out of range\n", entry);
2219 return false;
2220 }
2221
2222 switch (k->kv_type) {
2223 case ATH9K_CIPHER_AES_OCB:
2224 keyType = AR_KEYTABLE_TYPE_AES;
2225 break;
2226 case ATH9K_CIPHER_AES_CCM:
2227 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2228 ath_print(common, ATH_DBG_ANY,
2229 "AES-CCM not supported by mac rev 0x%x\n",
2230 ah->hw_version.macRev);
2231 return false;
2232 }
2233 keyType = AR_KEYTABLE_TYPE_CCM;
2234 break;
2235 case ATH9K_CIPHER_TKIP:
2236 keyType = AR_KEYTABLE_TYPE_TKIP;
2237 if (ATH9K_IS_MIC_ENABLED(ah)
2238 && entry + 64 >= pCap->keycache_size) {
2239 ath_print(common, ATH_DBG_ANY,
2240 "entry %u inappropriate for TKIP\n", entry);
2241 return false;
2242 }
2243 break;
2244 case ATH9K_CIPHER_WEP:
2245 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
2246 ath_print(common, ATH_DBG_ANY,
2247 "WEP key length %u too small\n", k->kv_len);
2248 return false;
2249 }
2250 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
2251 keyType = AR_KEYTABLE_TYPE_40;
2252 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
2253 keyType = AR_KEYTABLE_TYPE_104;
2254 else
2255 keyType = AR_KEYTABLE_TYPE_128;
2256 break;
2257 case ATH9K_CIPHER_CLR:
2258 keyType = AR_KEYTABLE_TYPE_CLR;
2259 break;
2260 default:
2261 ath_print(common, ATH_DBG_FATAL,
2262 "cipher %u not supported\n", k->kv_type);
2263 return false;
2264 }
2265
2266 key0 = get_unaligned_le32(k->kv_val + 0);
2267 key1 = get_unaligned_le16(k->kv_val + 4);
2268 key2 = get_unaligned_le32(k->kv_val + 6);
2269 key3 = get_unaligned_le16(k->kv_val + 10);
2270 key4 = get_unaligned_le32(k->kv_val + 12);
2271 if (k->kv_len <= WLAN_KEY_LEN_WEP104)
2272 key4 &= 0xff;
2273
2274 /*
2275 * Note: Key cache registers access special memory area that requires
2276 * two 32-bit writes to actually update the values in the internal
2277 * memory. Consequently, the exact order and pairs used here must be
2278 * maintained.
2279 */
2280
2281 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2282 u16 micentry = entry + 64;
2283
2284 /*
2285 * Write inverted key[47:0] first to avoid Michael MIC errors
2286 * on frames that could be sent or received at the same time.
2287 * The correct key will be written in the end once everything
2288 * else is ready.
2289 */
2290 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2291 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
2292
2293 /* Write key[95:48] */
2294 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2295 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2296
2297 /* Write key[127:96] and key type */
2298 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2299 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2300
2301 /* Write MAC address for the entry */
2302 (void) ath9k_hw_keysetmac(ah, entry, mac);
2303
2304 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
2305 /*
2306 * TKIP uses two key cache entries:
2307 * Michael MIC TX/RX keys in the same key cache entry
2308 * (idx = main index + 64):
2309 * key0 [31:0] = RX key [31:0]
2310 * key1 [15:0] = TX key [31:16]
2311 * key1 [31:16] = reserved
2312 * key2 [31:0] = RX key [63:32]
2313 * key3 [15:0] = TX key [15:0]
2314 * key3 [31:16] = reserved
2315 * key4 [31:0] = TX key [63:32]
2316 */
2317 u32 mic0, mic1, mic2, mic3, mic4;
2318
2319 mic0 = get_unaligned_le32(k->kv_mic + 0);
2320 mic2 = get_unaligned_le32(k->kv_mic + 4);
2321 mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2322 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2323 mic4 = get_unaligned_le32(k->kv_txmic + 4);
2324
2325 /* Write RX[31:0] and TX[31:16] */
2326 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2327 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2328
2329 /* Write RX[63:32] and TX[15:0] */
2330 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2331 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2332
2333 /* Write TX[63:32] and keyType(reserved) */
2334 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2335 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2336 AR_KEYTABLE_TYPE_CLR);
2337
2338 } else {
2339 /*
2340 * TKIP uses four key cache entries (two for group
2341 * keys):
2342 * Michael MIC TX/RX keys are in different key cache
2343 * entries (idx = main index + 64 for TX and
2344 * main index + 32 + 96 for RX):
2345 * key0 [31:0] = TX/RX MIC key [31:0]
2346 * key1 [31:0] = reserved
2347 * key2 [31:0] = TX/RX MIC key [63:32]
2348 * key3 [31:0] = reserved
2349 * key4 [31:0] = reserved
2350 *
2351 * Upper layer code will call this function separately
2352 * for TX and RX keys when these registers offsets are
2353 * used.
2354 */
2355 u32 mic0, mic2;
2356
2357 mic0 = get_unaligned_le32(k->kv_mic + 0);
2358 mic2 = get_unaligned_le32(k->kv_mic + 4);
2359
2360 /* Write MIC key[31:0] */
2361 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2362 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2363
2364 /* Write MIC key[63:32] */
2365 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2366 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2367
2368 /* Write TX[63:32] and keyType(reserved) */
2369 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2370 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2371 AR_KEYTABLE_TYPE_CLR);
2372 }
2373
2374 /* MAC address registers are reserved for the MIC entry */
2375 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2376 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2377
2378 /*
2379 * Write the correct (un-inverted) key[47:0] last to enable
2380 * TKIP now that all other registers are set with correct
2381 * values.
2382 */
2383 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2384 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2385 } else {
2386 /* Write key[47:0] */
2387 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2388 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2389
2390 /* Write key[95:48] */
2391 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2392 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2393
2394 /* Write key[127:96] and key type */
2395 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2396 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2397
2398 /* Write MAC address for the entry */
2399 (void) ath9k_hw_keysetmac(ah, entry, mac);
2400 }
2401
2402 return true;
2403 }
2404 EXPORT_SYMBOL(ath9k_hw_set_keycache_entry);
2405
2406 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
2407 {
2408 if (entry < ah->caps.keycache_size) {
2409 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2410 if (val & AR_KEYTABLE_VALID)
2411 return true;
2412 }
2413 return false;
2414 }
2415 EXPORT_SYMBOL(ath9k_hw_keyisvalid);
2416
2417 /******************************/
2418 /* Power Management (Chipset) */
2419 /******************************/
2420
2421 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
2422 {
2423 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2424 if (setChip) {
2425 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2426 AR_RTC_FORCE_WAKE_EN);
2427 if (!AR_SREV_9100(ah))
2428 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2429
2430 if(!AR_SREV_5416(ah))
2431 REG_CLR_BIT(ah, (AR_RTC_RESET),
2432 AR_RTC_RESET_EN);
2433 }
2434 }
2435
2436 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
2437 {
2438 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2439 if (setChip) {
2440 struct ath9k_hw_capabilities *pCap = &ah->caps;
2441
2442 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2443 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2444 AR_RTC_FORCE_WAKE_ON_INT);
2445 } else {
2446 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2447 AR_RTC_FORCE_WAKE_EN);
2448 }
2449 }
2450 }
2451
2452 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2453 {
2454 u32 val;
2455 int i;
2456
2457 if (setChip) {
2458 if ((REG_READ(ah, AR_RTC_STATUS) &
2459 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2460 if (ath9k_hw_set_reset_reg(ah,
2461 ATH9K_RESET_POWER_ON) != true) {
2462 return false;
2463 }
2464 ath9k_hw_init_pll(ah, NULL);
2465 }
2466 if (AR_SREV_9100(ah))
2467 REG_SET_BIT(ah, AR_RTC_RESET,
2468 AR_RTC_RESET_EN);
2469
2470 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2471 AR_RTC_FORCE_WAKE_EN);
2472 udelay(50);
2473
2474 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2475 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2476 if (val == AR_RTC_STATUS_ON)
2477 break;
2478 udelay(50);
2479 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2480 AR_RTC_FORCE_WAKE_EN);
2481 }
2482 if (i == 0) {
2483 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2484 "Failed to wakeup in %uus\n",
2485 POWER_UP_TIME / 20);
2486 return false;
2487 }
2488 }
2489
2490 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2491
2492 return true;
2493 }
2494
2495 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2496 {
2497 struct ath_common *common = ath9k_hw_common(ah);
2498 int status = true, setChip = true;
2499 static const char *modes[] = {
2500 "AWAKE",
2501 "FULL-SLEEP",
2502 "NETWORK SLEEP",
2503 "UNDEFINED"
2504 };
2505
2506 if (ah->power_mode == mode)
2507 return status;
2508
2509 ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
2510 modes[ah->power_mode], modes[mode]);
2511
2512 switch (mode) {
2513 case ATH9K_PM_AWAKE:
2514 status = ath9k_hw_set_power_awake(ah, setChip);
2515 break;
2516 case ATH9K_PM_FULL_SLEEP:
2517 ath9k_set_power_sleep(ah, setChip);
2518 ah->chip_fullsleep = true;
2519 break;
2520 case ATH9K_PM_NETWORK_SLEEP:
2521 ath9k_set_power_network_sleep(ah, setChip);
2522 break;
2523 default:
2524 ath_print(common, ATH_DBG_FATAL,
2525 "Unknown power mode %u\n", mode);
2526 return false;
2527 }
2528 ah->power_mode = mode;
2529
2530 return status;
2531 }
2532 EXPORT_SYMBOL(ath9k_hw_setpower);
2533
2534 /*
2535 * Helper for ASPM support.
2536 *
2537 * Disable PLL when in L0s as well as receiver clock when in L1.
2538 * This power saving option must be enabled through the SerDes.
2539 *
2540 * Programming the SerDes must go through the same 288 bit serial shift
2541 * register as the other analog registers. Hence the 9 writes.
2542 */
2543 void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off)
2544 {
2545 u8 i;
2546 u32 val;
2547
2548 if (ah->is_pciexpress != true)
2549 return;
2550
2551 /* Do not touch SerDes registers */
2552 if (ah->config.pcie_powersave_enable == 2)
2553 return;
2554
2555 /* Nothing to do on restore for 11N */
2556 if (!restore) {
2557 if (AR_SREV_9280_20_OR_LATER(ah)) {
2558 /*
2559 * AR9280 2.0 or later chips use SerDes values from the
2560 * initvals.h initialized depending on chipset during
2561 * ath9k_hw_init()
2562 */
2563 for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
2564 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
2565 INI_RA(&ah->iniPcieSerdes, i, 1));
2566 }
2567 } else if (AR_SREV_9280(ah) &&
2568 (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
2569 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2570 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2571
2572 /* RX shut off when elecidle is asserted */
2573 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2574 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2575 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2576
2577 /* Shut off CLKREQ active in L1 */
2578 if (ah->config.pcie_clock_req)
2579 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2580 else
2581 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
2582
2583 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2584 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2585 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
2586
2587 /* Load the new settings */
2588 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2589
2590 } else {
2591 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2592 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2593
2594 /* RX shut off when elecidle is asserted */
2595 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2596 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2597 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
2598
2599 /*
2600 * Ignore ah->ah_config.pcie_clock_req setting for
2601 * pre-AR9280 11n
2602 */
2603 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2604
2605 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2606 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2607 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
2608
2609 /* Load the new settings */
2610 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2611 }
2612
2613 udelay(1000);
2614
2615 /* set bit 19 to allow forcing of pcie core into L1 state */
2616 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
2617
2618 /* Several PCIe massages to ensure proper behaviour */
2619 if (ah->config.pcie_waen) {
2620 val = ah->config.pcie_waen;
2621 if (!power_off)
2622 val &= (~AR_WA_D3_L1_DISABLE);
2623 } else {
2624 if (AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
2625 AR_SREV_9287(ah)) {
2626 val = AR9285_WA_DEFAULT;
2627 if (!power_off)
2628 val &= (~AR_WA_D3_L1_DISABLE);
2629 } else if (AR_SREV_9280(ah)) {
2630 /*
2631 * On AR9280 chips bit 22 of 0x4004 needs to be
2632 * set otherwise card may disappear.
2633 */
2634 val = AR9280_WA_DEFAULT;
2635 if (!power_off)
2636 val &= (~AR_WA_D3_L1_DISABLE);
2637 } else
2638 val = AR_WA_DEFAULT;
2639 }
2640
2641 REG_WRITE(ah, AR_WA, val);
2642 }
2643
2644 if (power_off) {
2645 /*
2646 * Set PCIe workaround bits
2647 * bit 14 in WA register (disable L1) should only
2648 * be set when device enters D3 and be cleared
2649 * when device comes back to D0.
2650 */
2651 if (ah->config.pcie_waen) {
2652 if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE)
2653 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
2654 } else {
2655 if (((AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
2656 AR_SREV_9287(ah)) &&
2657 (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) ||
2658 (AR_SREV_9280(ah) &&
2659 (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) {
2660 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
2661 }
2662 }
2663 }
2664 }
2665 EXPORT_SYMBOL(ath9k_hw_configpcipowersave);
2666
2667 /**********************/
2668 /* Interrupt Handling */
2669 /**********************/
2670
2671 bool ath9k_hw_intrpend(struct ath_hw *ah)
2672 {
2673 u32 host_isr;
2674
2675 if (AR_SREV_9100(ah))
2676 return true;
2677
2678 host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
2679 if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
2680 return true;
2681
2682 host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
2683 if ((host_isr & AR_INTR_SYNC_DEFAULT)
2684 && (host_isr != AR_INTR_SPURIOUS))
2685 return true;
2686
2687 return false;
2688 }
2689 EXPORT_SYMBOL(ath9k_hw_intrpend);
2690
2691 bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
2692 {
2693 u32 isr = 0;
2694 u32 mask2 = 0;
2695 struct ath9k_hw_capabilities *pCap = &ah->caps;
2696 u32 sync_cause = 0;
2697 bool fatal_int = false;
2698 struct ath_common *common = ath9k_hw_common(ah);
2699
2700 if (!AR_SREV_9100(ah)) {
2701 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
2702 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
2703 == AR_RTC_STATUS_ON) {
2704 isr = REG_READ(ah, AR_ISR);
2705 }
2706 }
2707
2708 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
2709 AR_INTR_SYNC_DEFAULT;
2710
2711 *masked = 0;
2712
2713 if (!isr && !sync_cause)
2714 return false;
2715 } else {
2716 *masked = 0;
2717 isr = REG_READ(ah, AR_ISR);
2718 }
2719
2720 if (isr) {
2721 if (isr & AR_ISR_BCNMISC) {
2722 u32 isr2;
2723 isr2 = REG_READ(ah, AR_ISR_S2);
2724 if (isr2 & AR_ISR_S2_TIM)
2725 mask2 |= ATH9K_INT_TIM;
2726 if (isr2 & AR_ISR_S2_DTIM)
2727 mask2 |= ATH9K_INT_DTIM;
2728 if (isr2 & AR_ISR_S2_DTIMSYNC)
2729 mask2 |= ATH9K_INT_DTIMSYNC;
2730 if (isr2 & (AR_ISR_S2_CABEND))
2731 mask2 |= ATH9K_INT_CABEND;
2732 if (isr2 & AR_ISR_S2_GTT)
2733 mask2 |= ATH9K_INT_GTT;
2734 if (isr2 & AR_ISR_S2_CST)
2735 mask2 |= ATH9K_INT_CST;
2736 if (isr2 & AR_ISR_S2_TSFOOR)
2737 mask2 |= ATH9K_INT_TSFOOR;
2738 }
2739
2740 isr = REG_READ(ah, AR_ISR_RAC);
2741 if (isr == 0xffffffff) {
2742 *masked = 0;
2743 return false;
2744 }
2745
2746 *masked = isr & ATH9K_INT_COMMON;
2747
2748 if (ah->config.rx_intr_mitigation) {
2749 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
2750 *masked |= ATH9K_INT_RX;
2751 }
2752
2753 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
2754 *masked |= ATH9K_INT_RX;
2755 if (isr &
2756 (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
2757 AR_ISR_TXEOL)) {
2758 u32 s0_s, s1_s;
2759
2760 *masked |= ATH9K_INT_TX;
2761
2762 s0_s = REG_READ(ah, AR_ISR_S0_S);
2763 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
2764 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
2765
2766 s1_s = REG_READ(ah, AR_ISR_S1_S);
2767 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
2768 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
2769 }
2770
2771 if (isr & AR_ISR_RXORN) {
2772 ath_print(common, ATH_DBG_INTERRUPT,
2773 "receive FIFO overrun interrupt\n");
2774 }
2775
2776 if (!AR_SREV_9100(ah)) {
2777 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2778 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
2779 if (isr5 & AR_ISR_S5_TIM_TIMER)
2780 *masked |= ATH9K_INT_TIM_TIMER;
2781 }
2782 }
2783
2784 *masked |= mask2;
2785 }
2786
2787 if (AR_SREV_9100(ah))
2788 return true;
2789
2790 if (isr & AR_ISR_GENTMR) {
2791 u32 s5_s;
2792
2793 s5_s = REG_READ(ah, AR_ISR_S5_S);
2794 if (isr & AR_ISR_GENTMR) {
2795 ah->intr_gen_timer_trigger =
2796 MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
2797
2798 ah->intr_gen_timer_thresh =
2799 MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);
2800
2801 if (ah->intr_gen_timer_trigger)
2802 *masked |= ATH9K_INT_GENTIMER;
2803
2804 }
2805 }
2806
2807 if (sync_cause) {
2808 fatal_int =
2809 (sync_cause &
2810 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
2811 ? true : false;
2812
2813 if (fatal_int) {
2814 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
2815 ath_print(common, ATH_DBG_ANY,
2816 "received PCI FATAL interrupt\n");
2817 }
2818 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
2819 ath_print(common, ATH_DBG_ANY,
2820 "received PCI PERR interrupt\n");
2821 }
2822 *masked |= ATH9K_INT_FATAL;
2823 }
2824 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
2825 ath_print(common, ATH_DBG_INTERRUPT,
2826 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
2827 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
2828 REG_WRITE(ah, AR_RC, 0);
2829 *masked |= ATH9K_INT_FATAL;
2830 }
2831 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
2832 ath_print(common, ATH_DBG_INTERRUPT,
2833 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
2834 }
2835
2836 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
2837 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
2838 }
2839
2840 return true;
2841 }
2842 EXPORT_SYMBOL(ath9k_hw_getisr);
2843
2844 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
2845 {
2846 u32 omask = ah->mask_reg;
2847 u32 mask, mask2;
2848 struct ath9k_hw_capabilities *pCap = &ah->caps;
2849 struct ath_common *common = ath9k_hw_common(ah);
2850
2851 ath_print(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
2852
2853 if (omask & ATH9K_INT_GLOBAL) {
2854 ath_print(common, ATH_DBG_INTERRUPT, "disable IER\n");
2855 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
2856 (void) REG_READ(ah, AR_IER);
2857 if (!AR_SREV_9100(ah)) {
2858 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
2859 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
2860
2861 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
2862 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
2863 }
2864 }
2865
2866 mask = ints & ATH9K_INT_COMMON;
2867 mask2 = 0;
2868
2869 if (ints & ATH9K_INT_TX) {
2870 if (ah->txok_interrupt_mask)
2871 mask |= AR_IMR_TXOK;
2872 if (ah->txdesc_interrupt_mask)
2873 mask |= AR_IMR_TXDESC;
2874 if (ah->txerr_interrupt_mask)
2875 mask |= AR_IMR_TXERR;
2876 if (ah->txeol_interrupt_mask)
2877 mask |= AR_IMR_TXEOL;
2878 }
2879 if (ints & ATH9K_INT_RX) {
2880 mask |= AR_IMR_RXERR;
2881 if (ah->config.rx_intr_mitigation)
2882 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
2883 else
2884 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
2885 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
2886 mask |= AR_IMR_GENTMR;
2887 }
2888
2889 if (ints & (ATH9K_INT_BMISC)) {
2890 mask |= AR_IMR_BCNMISC;
2891 if (ints & ATH9K_INT_TIM)
2892 mask2 |= AR_IMR_S2_TIM;
2893 if (ints & ATH9K_INT_DTIM)
2894 mask2 |= AR_IMR_S2_DTIM;
2895 if (ints & ATH9K_INT_DTIMSYNC)
2896 mask2 |= AR_IMR_S2_DTIMSYNC;
2897 if (ints & ATH9K_INT_CABEND)
2898 mask2 |= AR_IMR_S2_CABEND;
2899 if (ints & ATH9K_INT_TSFOOR)
2900 mask2 |= AR_IMR_S2_TSFOOR;
2901 }
2902
2903 if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
2904 mask |= AR_IMR_BCNMISC;
2905 if (ints & ATH9K_INT_GTT)
2906 mask2 |= AR_IMR_S2_GTT;
2907 if (ints & ATH9K_INT_CST)
2908 mask2 |= AR_IMR_S2_CST;
2909 }
2910
2911 ath_print(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
2912 REG_WRITE(ah, AR_IMR, mask);
2913 mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
2914 AR_IMR_S2_DTIM |
2915 AR_IMR_S2_DTIMSYNC |
2916 AR_IMR_S2_CABEND |
2917 AR_IMR_S2_CABTO |
2918 AR_IMR_S2_TSFOOR |
2919 AR_IMR_S2_GTT | AR_IMR_S2_CST);
2920 REG_WRITE(ah, AR_IMR_S2, mask | mask2);
2921 ah->mask_reg = ints;
2922
2923 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2924 if (ints & ATH9K_INT_TIM_TIMER)
2925 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
2926 else
2927 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
2928 }
2929
2930 if (ints & ATH9K_INT_GLOBAL) {
2931 ath_print(common, ATH_DBG_INTERRUPT, "enable IER\n");
2932 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
2933 if (!AR_SREV_9100(ah)) {
2934 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
2935 AR_INTR_MAC_IRQ);
2936 REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
2937
2938
2939 REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
2940 AR_INTR_SYNC_DEFAULT);
2941 REG_WRITE(ah, AR_INTR_SYNC_MASK,
2942 AR_INTR_SYNC_DEFAULT);
2943 }
2944 ath_print(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
2945 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
2946 }
2947
2948 return omask;
2949 }
2950 EXPORT_SYMBOL(ath9k_hw_set_interrupts);
2951
2952 /*******************/
2953 /* Beacon Handling */
2954 /*******************/
2955
2956 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
2957 {
2958 int flags = 0;
2959
2960 ah->beacon_interval = beacon_period;
2961
2962 switch (ah->opmode) {
2963 case NL80211_IFTYPE_STATION:
2964 case NL80211_IFTYPE_MONITOR:
2965 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
2966 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
2967 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
2968 flags |= AR_TBTT_TIMER_EN;
2969 break;
2970 case NL80211_IFTYPE_ADHOC:
2971 case NL80211_IFTYPE_MESH_POINT:
2972 REG_SET_BIT(ah, AR_TXCFG,
2973 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
2974 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
2975 TU_TO_USEC(next_beacon +
2976 (ah->atim_window ? ah->
2977 atim_window : 1)));
2978 flags |= AR_NDP_TIMER_EN;
2979 case NL80211_IFTYPE_AP:
2980 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
2981 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
2982 TU_TO_USEC(next_beacon -
2983 ah->config.
2984 dma_beacon_response_time));
2985 REG_WRITE(ah, AR_NEXT_SWBA,
2986 TU_TO_USEC(next_beacon -
2987 ah->config.
2988 sw_beacon_response_time));
2989 flags |=
2990 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
2991 break;
2992 default:
2993 ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
2994 "%s: unsupported opmode: %d\n",
2995 __func__, ah->opmode);
2996 return;
2997 break;
2998 }
2999
3000 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3001 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3002 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
3003 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
3004
3005 beacon_period &= ~ATH9K_BEACON_ENA;
3006 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
3007 ath9k_hw_reset_tsf(ah);
3008 }
3009
3010 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3011 }
3012 EXPORT_SYMBOL(ath9k_hw_beaconinit);
3013
3014 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
3015 const struct ath9k_beacon_state *bs)
3016 {
3017 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
3018 struct ath9k_hw_capabilities *pCap = &ah->caps;
3019 struct ath_common *common = ath9k_hw_common(ah);
3020
3021 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3022
3023 REG_WRITE(ah, AR_BEACON_PERIOD,
3024 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3025 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3026 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3027
3028 REG_RMW_FIELD(ah, AR_RSSI_THR,
3029 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3030
3031 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3032
3033 if (bs->bs_sleepduration > beaconintval)
3034 beaconintval = bs->bs_sleepduration;
3035
3036 dtimperiod = bs->bs_dtimperiod;
3037 if (bs->bs_sleepduration > dtimperiod)
3038 dtimperiod = bs->bs_sleepduration;
3039
3040 if (beaconintval == dtimperiod)
3041 nextTbtt = bs->bs_nextdtim;
3042 else
3043 nextTbtt = bs->bs_nexttbtt;
3044
3045 ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3046 ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3047 ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3048 ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
3049
3050 REG_WRITE(ah, AR_NEXT_DTIM,
3051 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3052 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
3053
3054 REG_WRITE(ah, AR_SLEEP1,
3055 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3056 | AR_SLEEP1_ASSUME_DTIM);
3057
3058 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3059 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3060 else
3061 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
3062
3063 REG_WRITE(ah, AR_SLEEP2,
3064 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
3065
3066 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3067 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
3068
3069 REG_SET_BIT(ah, AR_TIMER_MODE,
3070 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3071 AR_DTIM_TIMER_EN);
3072
3073 /* TSF Out of Range Threshold */
3074 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
3075 }
3076 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
3077
3078 /*******************/
3079 /* HW Capabilities */
3080 /*******************/
3081
3082 int ath9k_hw_fill_cap_info(struct ath_hw *ah)
3083 {
3084 struct ath9k_hw_capabilities *pCap = &ah->caps;
3085 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3086 struct ath_common *common = ath9k_hw_common(ah);
3087 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
3088
3089 u16 capField = 0, eeval;
3090
3091 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
3092 regulatory->current_rd = eeval;
3093
3094 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
3095 if (AR_SREV_9285_10_OR_LATER(ah))
3096 eeval |= AR9285_RDEXT_DEFAULT;
3097 regulatory->current_rd_ext = eeval;
3098
3099 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
3100
3101 if (ah->opmode != NL80211_IFTYPE_AP &&
3102 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3103 if (regulatory->current_rd == 0x64 ||
3104 regulatory->current_rd == 0x65)
3105 regulatory->current_rd += 5;
3106 else if (regulatory->current_rd == 0x41)
3107 regulatory->current_rd = 0x43;
3108 ath_print(common, ATH_DBG_REGULATORY,
3109 "regdomain mapped to 0x%x\n", regulatory->current_rd);
3110 }
3111
3112 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
3113 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
3114 ath_print(common, ATH_DBG_FATAL,
3115 "no band has been marked as supported in EEPROM.\n");
3116 return -EINVAL;
3117 }
3118
3119 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
3120
3121 if (eeval & AR5416_OPFLAGS_11A) {
3122 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
3123 if (ah->config.ht_enable) {
3124 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3125 set_bit(ATH9K_MODE_11NA_HT20,
3126 pCap->wireless_modes);
3127 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3128 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3129 pCap->wireless_modes);
3130 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3131 pCap->wireless_modes);
3132 }
3133 }
3134 }
3135
3136 if (eeval & AR5416_OPFLAGS_11G) {
3137 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
3138 if (ah->config.ht_enable) {
3139 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3140 set_bit(ATH9K_MODE_11NG_HT20,
3141 pCap->wireless_modes);
3142 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3143 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3144 pCap->wireless_modes);
3145 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3146 pCap->wireless_modes);
3147 }
3148 }
3149 }
3150
3151 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
3152 /*
3153 * For AR9271 we will temporarilly uses the rx chainmax as read from
3154 * the EEPROM.
3155 */
3156 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
3157 !(eeval & AR5416_OPFLAGS_11A) &&
3158 !(AR_SREV_9271(ah)))
3159 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
3160 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
3161 else
3162 /* Use rx_chainmask from EEPROM. */
3163 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
3164
3165 if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
3166 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
3167
3168 pCap->low_2ghz_chan = 2312;
3169 pCap->high_2ghz_chan = 2732;
3170
3171 pCap->low_5ghz_chan = 4920;
3172 pCap->high_5ghz_chan = 6100;
3173
3174 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3175 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3176 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3177
3178 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3179 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3180 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3181
3182 if (ah->config.ht_enable)
3183 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3184 else
3185 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3186
3187 pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3188 pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3189 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3190 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3191
3192 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3193 pCap->total_queues =
3194 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3195 else
3196 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3197
3198 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3199 pCap->keycache_size =
3200 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3201 else
3202 pCap->keycache_size = AR_KEYTABLE_SIZE;
3203
3204 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3205
3206 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
3207 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1;
3208 else
3209 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3210
3211 if (AR_SREV_9285_10_OR_LATER(ah))
3212 pCap->num_gpio_pins = AR9285_NUM_GPIO;
3213 else if (AR_SREV_9280_10_OR_LATER(ah))
3214 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3215 else
3216 pCap->num_gpio_pins = AR_NUM_GPIO;
3217
3218 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3219 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3220 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3221 } else {
3222 pCap->rts_aggr_limit = (8 * 1024);
3223 }
3224
3225 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3226
3227 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3228 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
3229 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
3230 ah->rfkill_gpio =
3231 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
3232 ah->rfkill_polarity =
3233 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
3234
3235 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3236 }
3237 #endif
3238
3239 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3240
3241 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
3242 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3243 else
3244 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3245
3246 if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
3247 pCap->reg_cap =
3248 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3249 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3250 AR_EEPROM_EEREGCAP_EN_KK_U2 |
3251 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3252 } else {
3253 pCap->reg_cap =
3254 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3255 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3256 }
3257
3258 /* Advertise midband for AR5416 with FCC midband set in eeprom */
3259 if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
3260 AR_SREV_5416(ah))
3261 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3262
3263 pCap->num_antcfg_5ghz =
3264 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
3265 pCap->num_antcfg_2ghz =
3266 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
3267
3268 if (AR_SREV_9280_10_OR_LATER(ah) &&
3269 ath9k_hw_btcoex_supported(ah)) {
3270 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
3271 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
3272
3273 if (AR_SREV_9285(ah)) {
3274 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
3275 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
3276 } else {
3277 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
3278 }
3279 } else {
3280 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
3281 }
3282
3283 return 0;
3284 }
3285
3286 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3287 u32 capability, u32 *result)
3288 {
3289 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3290 switch (type) {
3291 case ATH9K_CAP_CIPHER:
3292 switch (capability) {
3293 case ATH9K_CIPHER_AES_CCM:
3294 case ATH9K_CIPHER_AES_OCB:
3295 case ATH9K_CIPHER_TKIP:
3296 case ATH9K_CIPHER_WEP:
3297 case ATH9K_CIPHER_MIC:
3298 case ATH9K_CIPHER_CLR:
3299 return true;
3300 default:
3301 return false;
3302 }
3303 case ATH9K_CAP_TKIP_MIC:
3304 switch (capability) {
3305 case 0:
3306 return true;
3307 case 1:
3308 return (ah->sta_id1_defaults &
3309 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3310 false;
3311 }
3312 case ATH9K_CAP_TKIP_SPLIT:
3313 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
3314 false : true;
3315 case ATH9K_CAP_DIVERSITY:
3316 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3317 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3318 true : false;
3319 case ATH9K_CAP_MCAST_KEYSRCH:
3320 switch (capability) {
3321 case 0:
3322 return true;
3323 case 1:
3324 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3325 return false;
3326 } else {
3327 return (ah->sta_id1_defaults &
3328 AR_STA_ID1_MCAST_KSRCH) ? true :
3329 false;
3330 }
3331 }
3332 return false;
3333 case ATH9K_CAP_TXPOW:
3334 switch (capability) {
3335 case 0:
3336 return 0;
3337 case 1:
3338 *result = regulatory->power_limit;
3339 return 0;
3340 case 2:
3341 *result = regulatory->max_power_level;
3342 return 0;
3343 case 3:
3344 *result = regulatory->tp_scale;
3345 return 0;
3346 }
3347 return false;
3348 case ATH9K_CAP_DS:
3349 return (AR_SREV_9280_20_OR_LATER(ah) &&
3350 (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
3351 ? false : true;
3352 default:
3353 return false;
3354 }
3355 }
3356 EXPORT_SYMBOL(ath9k_hw_getcapability);
3357
3358 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3359 u32 capability, u32 setting, int *status)
3360 {
3361 u32 v;
3362
3363 switch (type) {
3364 case ATH9K_CAP_TKIP_MIC:
3365 if (setting)
3366 ah->sta_id1_defaults |=
3367 AR_STA_ID1_CRPT_MIC_ENABLE;
3368 else
3369 ah->sta_id1_defaults &=
3370 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3371 return true;
3372 case ATH9K_CAP_DIVERSITY:
3373 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3374 if (setting)
3375 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3376 else
3377 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3378 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3379 return true;
3380 case ATH9K_CAP_MCAST_KEYSRCH:
3381 if (setting)
3382 ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
3383 else
3384 ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
3385 return true;
3386 default:
3387 return false;
3388 }
3389 }
3390 EXPORT_SYMBOL(ath9k_hw_setcapability);
3391
3392 /****************************/
3393 /* GPIO / RFKILL / Antennae */
3394 /****************************/
3395
3396 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
3397 u32 gpio, u32 type)
3398 {
3399 int addr;
3400 u32 gpio_shift, tmp;
3401
3402 if (gpio > 11)
3403 addr = AR_GPIO_OUTPUT_MUX3;
3404 else if (gpio > 5)
3405 addr = AR_GPIO_OUTPUT_MUX2;
3406 else
3407 addr = AR_GPIO_OUTPUT_MUX1;
3408
3409 gpio_shift = (gpio % 6) * 5;
3410
3411 if (AR_SREV_9280_20_OR_LATER(ah)
3412 || (addr != AR_GPIO_OUTPUT_MUX1)) {
3413 REG_RMW(ah, addr, (type << gpio_shift),
3414 (0x1f << gpio_shift));
3415 } else {
3416 tmp = REG_READ(ah, addr);
3417 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3418 tmp &= ~(0x1f << gpio_shift);
3419 tmp |= (type << gpio_shift);
3420 REG_WRITE(ah, addr, tmp);
3421 }
3422 }
3423
3424 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
3425 {
3426 u32 gpio_shift;
3427
3428 BUG_ON(gpio >= ah->caps.num_gpio_pins);
3429
3430 gpio_shift = gpio << 1;
3431
3432 REG_RMW(ah,
3433 AR_GPIO_OE_OUT,
3434 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3435 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3436 }
3437 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
3438
3439 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
3440 {
3441 #define MS_REG_READ(x, y) \
3442 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3443
3444 if (gpio >= ah->caps.num_gpio_pins)
3445 return 0xffffffff;
3446
3447 if (AR_SREV_9287_10_OR_LATER(ah))
3448 return MS_REG_READ(AR9287, gpio) != 0;
3449 else if (AR_SREV_9285_10_OR_LATER(ah))
3450 return MS_REG_READ(AR9285, gpio) != 0;
3451 else if (AR_SREV_9280_10_OR_LATER(ah))
3452 return MS_REG_READ(AR928X, gpio) != 0;
3453 else
3454 return MS_REG_READ(AR, gpio) != 0;
3455 }
3456 EXPORT_SYMBOL(ath9k_hw_gpio_get);
3457
3458 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
3459 u32 ah_signal_type)
3460 {
3461 u32 gpio_shift;
3462
3463 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
3464
3465 gpio_shift = 2 * gpio;
3466
3467 REG_RMW(ah,
3468 AR_GPIO_OE_OUT,
3469 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3470 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3471 }
3472 EXPORT_SYMBOL(ath9k_hw_cfg_output);
3473
3474 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
3475 {
3476 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3477 AR_GPIO_BIT(gpio));
3478 }
3479 EXPORT_SYMBOL(ath9k_hw_set_gpio);
3480
3481 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
3482 {
3483 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3484 }
3485 EXPORT_SYMBOL(ath9k_hw_getdefantenna);
3486
3487 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
3488 {
3489 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3490 }
3491 EXPORT_SYMBOL(ath9k_hw_setantenna);
3492
3493 /*********************/
3494 /* General Operation */
3495 /*********************/
3496
3497 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
3498 {
3499 u32 bits = REG_READ(ah, AR_RX_FILTER);
3500 u32 phybits = REG_READ(ah, AR_PHY_ERR);
3501
3502 if (phybits & AR_PHY_ERR_RADAR)
3503 bits |= ATH9K_RX_FILTER_PHYRADAR;
3504 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3505 bits |= ATH9K_RX_FILTER_PHYERR;
3506
3507 return bits;
3508 }
3509 EXPORT_SYMBOL(ath9k_hw_getrxfilter);
3510
3511 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
3512 {
3513 u32 phybits;
3514
3515 REG_WRITE(ah, AR_RX_FILTER, bits);
3516
3517 phybits = 0;
3518 if (bits & ATH9K_RX_FILTER_PHYRADAR)
3519 phybits |= AR_PHY_ERR_RADAR;
3520 if (bits & ATH9K_RX_FILTER_PHYERR)
3521 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3522 REG_WRITE(ah, AR_PHY_ERR, phybits);
3523
3524 if (phybits)
3525 REG_WRITE(ah, AR_RXCFG,
3526 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3527 else
3528 REG_WRITE(ah, AR_RXCFG,
3529 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3530 }
3531 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
3532
3533 bool ath9k_hw_phy_disable(struct ath_hw *ah)
3534 {
3535 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
3536 return false;
3537
3538 ath9k_hw_init_pll(ah, NULL);
3539 return true;
3540 }
3541 EXPORT_SYMBOL(ath9k_hw_phy_disable);
3542
3543 bool ath9k_hw_disable(struct ath_hw *ah)
3544 {
3545 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3546 return false;
3547
3548 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
3549 return false;
3550
3551 ath9k_hw_init_pll(ah, NULL);
3552 return true;
3553 }
3554 EXPORT_SYMBOL(ath9k_hw_disable);
3555
3556 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
3557 {
3558 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3559 struct ath9k_channel *chan = ah->curchan;
3560 struct ieee80211_channel *channel = chan->chan;
3561
3562 regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
3563
3564 ah->eep_ops->set_txpower(ah, chan,
3565 ath9k_regd_get_ctl(regulatory, chan),
3566 channel->max_antenna_gain * 2,
3567 channel->max_power * 2,
3568 min((u32) MAX_RATE_POWER,
3569 (u32) regulatory->power_limit));
3570 }
3571 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
3572
3573 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
3574 {
3575 memcpy(ath9k_hw_common(ah)->macaddr, mac, ETH_ALEN);
3576 }
3577 EXPORT_SYMBOL(ath9k_hw_setmac);
3578
3579 void ath9k_hw_setopmode(struct ath_hw *ah)
3580 {
3581 ath9k_hw_set_operating_mode(ah, ah->opmode);
3582 }
3583 EXPORT_SYMBOL(ath9k_hw_setopmode);
3584
3585 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
3586 {
3587 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3588 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
3589 }
3590 EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
3591
3592 void ath9k_hw_write_associd(struct ath_hw *ah)
3593 {
3594 struct ath_common *common = ath9k_hw_common(ah);
3595
3596 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
3597 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
3598 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
3599 }
3600 EXPORT_SYMBOL(ath9k_hw_write_associd);
3601
3602 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
3603 {
3604 u64 tsf;
3605
3606 tsf = REG_READ(ah, AR_TSF_U32);
3607 tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
3608
3609 return tsf;
3610 }
3611 EXPORT_SYMBOL(ath9k_hw_gettsf64);
3612
3613 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
3614 {
3615 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
3616 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
3617 }
3618 EXPORT_SYMBOL(ath9k_hw_settsf64);
3619
3620 void ath9k_hw_reset_tsf(struct ath_hw *ah)
3621 {
3622 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
3623 AH_TSF_WRITE_TIMEOUT))
3624 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
3625 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
3626
3627 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3628 }
3629 EXPORT_SYMBOL(ath9k_hw_reset_tsf);
3630
3631 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
3632 {
3633 if (setting)
3634 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
3635 else
3636 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
3637 }
3638 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
3639
3640 /*
3641 * Extend 15-bit time stamp from rx descriptor to
3642 * a full 64-bit TSF using the current h/w TSF.
3643 */
3644 u64 ath9k_hw_extend_tsf(struct ath_hw *ah, u32 rstamp)
3645 {
3646 u64 tsf;
3647
3648 tsf = ath9k_hw_gettsf64(ah);
3649 if ((tsf & 0x7fff) < rstamp)
3650 tsf -= 0x8000;
3651 return (tsf & ~0x7fff) | rstamp;
3652 }
3653 EXPORT_SYMBOL(ath9k_hw_extend_tsf);
3654
3655 void ath9k_hw_set11nmac2040(struct ath_hw *ah)
3656 {
3657 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
3658 u32 macmode;
3659
3660 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
3661 macmode = AR_2040_JOINED_RX_CLEAR;
3662 else
3663 macmode = 0;
3664
3665 REG_WRITE(ah, AR_2040_MODE, macmode);
3666 }
3667
3668 /* HW Generic timers configuration */
3669
3670 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
3671 {
3672 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3673 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3674 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3675 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3676 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3677 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3678 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3679 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3680 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
3681 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
3682 AR_NDP2_TIMER_MODE, 0x0002},
3683 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
3684 AR_NDP2_TIMER_MODE, 0x0004},
3685 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
3686 AR_NDP2_TIMER_MODE, 0x0008},
3687 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
3688 AR_NDP2_TIMER_MODE, 0x0010},
3689 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
3690 AR_NDP2_TIMER_MODE, 0x0020},
3691 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
3692 AR_NDP2_TIMER_MODE, 0x0040},
3693 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
3694 AR_NDP2_TIMER_MODE, 0x0080}
3695 };
3696
3697 /* HW generic timer primitives */
3698
3699 /* compute and clear index of rightmost 1 */
3700 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
3701 {
3702 u32 b;
3703
3704 b = *mask;
3705 b &= (0-b);
3706 *mask &= ~b;
3707 b *= debruijn32;
3708 b >>= 27;
3709
3710 return timer_table->gen_timer_index[b];
3711 }
3712
3713 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
3714 {
3715 return REG_READ(ah, AR_TSF_L32);
3716 }
3717 EXPORT_SYMBOL(ath9k_hw_gettsf32);
3718
3719 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
3720 void (*trigger)(void *),
3721 void (*overflow)(void *),
3722 void *arg,
3723 u8 timer_index)
3724 {
3725 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3726 struct ath_gen_timer *timer;
3727
3728 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
3729
3730 if (timer == NULL) {
3731 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
3732 "Failed to allocate memory"
3733 "for hw timer[%d]\n", timer_index);
3734 return NULL;
3735 }
3736
3737 /* allocate a hardware generic timer slot */
3738 timer_table->timers[timer_index] = timer;
3739 timer->index = timer_index;
3740 timer->trigger = trigger;
3741 timer->overflow = overflow;
3742 timer->arg = arg;
3743
3744 return timer;
3745 }
3746 EXPORT_SYMBOL(ath_gen_timer_alloc);
3747
3748 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
3749 struct ath_gen_timer *timer,
3750 u32 timer_next,
3751 u32 timer_period)
3752 {
3753 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3754 u32 tsf;
3755
3756 BUG_ON(!timer_period);
3757
3758 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
3759
3760 tsf = ath9k_hw_gettsf32(ah);
3761
3762 ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
3763 "curent tsf %x period %x"
3764 "timer_next %x\n", tsf, timer_period, timer_next);
3765
3766 /*
3767 * Pull timer_next forward if the current TSF already passed it
3768 * because of software latency
3769 */
3770 if (timer_next < tsf)
3771 timer_next = tsf + timer_period;
3772
3773 /*
3774 * Program generic timer registers
3775 */
3776 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
3777 timer_next);
3778 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
3779 timer_period);
3780 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3781 gen_tmr_configuration[timer->index].mode_mask);
3782
3783 /* Enable both trigger and thresh interrupt masks */
3784 REG_SET_BIT(ah, AR_IMR_S5,
3785 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3786 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3787 }
3788 EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
3789
3790 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
3791 {
3792 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3793
3794 if ((timer->index < AR_FIRST_NDP_TIMER) ||
3795 (timer->index >= ATH_MAX_GEN_TIMER)) {
3796 return;
3797 }
3798
3799 /* Clear generic timer enable bits. */
3800 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3801 gen_tmr_configuration[timer->index].mode_mask);
3802
3803 /* Disable both trigger and thresh interrupt masks */
3804 REG_CLR_BIT(ah, AR_IMR_S5,
3805 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3806 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3807
3808 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
3809 }
3810 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
3811
3812 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
3813 {
3814 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3815
3816 /* free the hardware generic timer slot */
3817 timer_table->timers[timer->index] = NULL;
3818 kfree(timer);
3819 }
3820 EXPORT_SYMBOL(ath_gen_timer_free);
3821
3822 /*
3823 * Generic Timer Interrupts handling
3824 */
3825 void ath_gen_timer_isr(struct ath_hw *ah)
3826 {
3827 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3828 struct ath_gen_timer *timer;
3829 struct ath_common *common = ath9k_hw_common(ah);
3830 u32 trigger_mask, thresh_mask, index;
3831
3832 /* get hardware generic timer interrupt status */
3833 trigger_mask = ah->intr_gen_timer_trigger;
3834 thresh_mask = ah->intr_gen_timer_thresh;
3835 trigger_mask &= timer_table->timer_mask.val;
3836 thresh_mask &= timer_table->timer_mask.val;
3837
3838 trigger_mask &= ~thresh_mask;
3839
3840 while (thresh_mask) {
3841 index = rightmost_index(timer_table, &thresh_mask);
3842 timer = timer_table->timers[index];
3843 BUG_ON(!timer);
3844 ath_print(common, ATH_DBG_HWTIMER,
3845 "TSF overflow for Gen timer %d\n", index);
3846 timer->overflow(timer->arg);
3847 }
3848
3849 while (trigger_mask) {
3850 index = rightmost_index(timer_table, &trigger_mask);
3851 timer = timer_table->timers[index];
3852 BUG_ON(!timer);
3853 ath_print(common, ATH_DBG_HWTIMER,
3854 "Gen timer[%d] trigger\n", index);
3855 timer->trigger(timer->arg);
3856 }
3857 }
3858 EXPORT_SYMBOL(ath_gen_timer_isr);
3859
3860 static struct {
3861 u32 version;
3862 const char * name;
3863 } ath_mac_bb_names[] = {
3864 /* Devices with external radios */
3865 { AR_SREV_VERSION_5416_PCI, "5416" },
3866 { AR_SREV_VERSION_5416_PCIE, "5418" },
3867 { AR_SREV_VERSION_9100, "9100" },
3868 { AR_SREV_VERSION_9160, "9160" },
3869 /* Single-chip solutions */
3870 { AR_SREV_VERSION_9280, "9280" },
3871 { AR_SREV_VERSION_9285, "9285" },
3872 { AR_SREV_VERSION_9287, "9287" },
3873 { AR_SREV_VERSION_9271, "9271" },
3874 };
3875
3876 /* For devices with external radios */
3877 static struct {
3878 u16 version;
3879 const char * name;
3880 } ath_rf_names[] = {
3881 { 0, "5133" },
3882 { AR_RAD5133_SREV_MAJOR, "5133" },
3883 { AR_RAD5122_SREV_MAJOR, "5122" },
3884 { AR_RAD2133_SREV_MAJOR, "2133" },
3885 { AR_RAD2122_SREV_MAJOR, "2122" }
3886 };
3887
3888 /*
3889 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3890 */
3891 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
3892 {
3893 int i;
3894
3895 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3896 if (ath_mac_bb_names[i].version == mac_bb_version) {
3897 return ath_mac_bb_names[i].name;
3898 }
3899 }
3900
3901 return "????";
3902 }
3903
3904 /*
3905 * Return the RF name. "????" is returned if the RF is unknown.
3906 * Used for devices with external radios.
3907 */
3908 static const char *ath9k_hw_rf_name(u16 rf_version)
3909 {
3910 int i;
3911
3912 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3913 if (ath_rf_names[i].version == rf_version) {
3914 return ath_rf_names[i].name;
3915 }
3916 }
3917
3918 return "????";
3919 }
3920
3921 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
3922 {
3923 int used;
3924
3925 /* chipsets >= AR9280 are single-chip */
3926 if (AR_SREV_9280_10_OR_LATER(ah)) {
3927 used = snprintf(hw_name, len,
3928 "Atheros AR%s Rev:%x",
3929 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3930 ah->hw_version.macRev);
3931 }
3932 else {
3933 used = snprintf(hw_name, len,
3934 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3935 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3936 ah->hw_version.macRev,
3937 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
3938 AR_RADIO_SREV_MAJOR)),
3939 ah->hw_version.phyRev);
3940 }
3941
3942 hw_name[used] = '\0';
3943 }
3944 EXPORT_SYMBOL(ath9k_hw_name);
Linux kernel - Deliverables
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