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ath9k_hw: Fix full sleep setup for AR9271
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / hw.c
1 /*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/io.h>
18 #include <asm/unaligned.h>
19
20 #include "hw.h"
21 #include "rc.h"
22 #include "initvals.h"
23
24 #define ATH9K_CLOCK_RATE_CCK 22
25 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
26 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
27
28 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
29 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan);
30 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
31 struct ar5416_eeprom_def *pEepData,
32 u32 reg, u32 value);
33
34 MODULE_AUTHOR("Atheros Communications");
35 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
36 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
37 MODULE_LICENSE("Dual BSD/GPL");
38
39 static int __init ath9k_init(void)
40 {
41 return 0;
42 }
43 module_init(ath9k_init);
44
45 static void __exit ath9k_exit(void)
46 {
47 return;
48 }
49 module_exit(ath9k_exit);
50
51 /********************/
52 /* Helper Functions */
53 /********************/
54
55 static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
56 {
57 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
58
59 if (!ah->curchan) /* should really check for CCK instead */
60 return usecs *ATH9K_CLOCK_RATE_CCK;
61 if (conf->channel->band == IEEE80211_BAND_2GHZ)
62 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
63 return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
64 }
65
66 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
67 {
68 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
69
70 if (conf_is_ht40(conf))
71 return ath9k_hw_mac_clks(ah, usecs) * 2;
72 else
73 return ath9k_hw_mac_clks(ah, usecs);
74 }
75
76 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
77 {
78 int i;
79
80 BUG_ON(timeout < AH_TIME_QUANTUM);
81
82 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
83 if ((REG_READ(ah, reg) & mask) == val)
84 return true;
85
86 udelay(AH_TIME_QUANTUM);
87 }
88
89 ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
90 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
91 timeout, reg, REG_READ(ah, reg), mask, val);
92
93 return false;
94 }
95 EXPORT_SYMBOL(ath9k_hw_wait);
96
97 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
98 {
99 u32 retval;
100 int i;
101
102 for (i = 0, retval = 0; i < n; i++) {
103 retval = (retval << 1) | (val & 1);
104 val >>= 1;
105 }
106 return retval;
107 }
108
109 bool ath9k_get_channel_edges(struct ath_hw *ah,
110 u16 flags, u16 *low,
111 u16 *high)
112 {
113 struct ath9k_hw_capabilities *pCap = &ah->caps;
114
115 if (flags & CHANNEL_5GHZ) {
116 *low = pCap->low_5ghz_chan;
117 *high = pCap->high_5ghz_chan;
118 return true;
119 }
120 if ((flags & CHANNEL_2GHZ)) {
121 *low = pCap->low_2ghz_chan;
122 *high = pCap->high_2ghz_chan;
123 return true;
124 }
125 return false;
126 }
127
128 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
129 u8 phy, int kbps,
130 u32 frameLen, u16 rateix,
131 bool shortPreamble)
132 {
133 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
134
135 if (kbps == 0)
136 return 0;
137
138 switch (phy) {
139 case WLAN_RC_PHY_CCK:
140 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
141 if (shortPreamble)
142 phyTime >>= 1;
143 numBits = frameLen << 3;
144 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
145 break;
146 case WLAN_RC_PHY_OFDM:
147 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
148 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
149 numBits = OFDM_PLCP_BITS + (frameLen << 3);
150 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
151 txTime = OFDM_SIFS_TIME_QUARTER
152 + OFDM_PREAMBLE_TIME_QUARTER
153 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
154 } else if (ah->curchan &&
155 IS_CHAN_HALF_RATE(ah->curchan)) {
156 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
157 numBits = OFDM_PLCP_BITS + (frameLen << 3);
158 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
159 txTime = OFDM_SIFS_TIME_HALF +
160 OFDM_PREAMBLE_TIME_HALF
161 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
162 } else {
163 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
164 numBits = OFDM_PLCP_BITS + (frameLen << 3);
165 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
166 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
167 + (numSymbols * OFDM_SYMBOL_TIME);
168 }
169 break;
170 default:
171 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
172 "Unknown phy %u (rate ix %u)\n", phy, rateix);
173 txTime = 0;
174 break;
175 }
176
177 return txTime;
178 }
179 EXPORT_SYMBOL(ath9k_hw_computetxtime);
180
181 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
182 struct ath9k_channel *chan,
183 struct chan_centers *centers)
184 {
185 int8_t extoff;
186
187 if (!IS_CHAN_HT40(chan)) {
188 centers->ctl_center = centers->ext_center =
189 centers->synth_center = chan->channel;
190 return;
191 }
192
193 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
194 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
195 centers->synth_center =
196 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
197 extoff = 1;
198 } else {
199 centers->synth_center =
200 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
201 extoff = -1;
202 }
203
204 centers->ctl_center =
205 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
206 /* 25 MHz spacing is supported by hw but not on upper layers */
207 centers->ext_center =
208 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
209 }
210
211 /******************/
212 /* Chip Revisions */
213 /******************/
214
215 static void ath9k_hw_read_revisions(struct ath_hw *ah)
216 {
217 u32 val;
218
219 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
220
221 if (val == 0xFF) {
222 val = REG_READ(ah, AR_SREV);
223 ah->hw_version.macVersion =
224 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
225 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
226 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
227 } else {
228 if (!AR_SREV_9100(ah))
229 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
230
231 ah->hw_version.macRev = val & AR_SREV_REVISION;
232
233 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
234 ah->is_pciexpress = true;
235 }
236 }
237
238 static int ath9k_hw_get_radiorev(struct ath_hw *ah)
239 {
240 u32 val;
241 int i;
242
243 REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
244
245 for (i = 0; i < 8; i++)
246 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
247 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
248 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
249
250 return ath9k_hw_reverse_bits(val, 8);
251 }
252
253 /************************************/
254 /* HW Attach, Detach, Init Routines */
255 /************************************/
256
257 static void ath9k_hw_disablepcie(struct ath_hw *ah)
258 {
259 if (AR_SREV_9100(ah))
260 return;
261
262 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
263 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
264 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
265 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
266 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
267 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
268 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
269 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
270 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
271
272 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
273 }
274
275 static bool ath9k_hw_chip_test(struct ath_hw *ah)
276 {
277 struct ath_common *common = ath9k_hw_common(ah);
278 u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
279 u32 regHold[2];
280 u32 patternData[4] = { 0x55555555,
281 0xaaaaaaaa,
282 0x66666666,
283 0x99999999 };
284 int i, j;
285
286 for (i = 0; i < 2; i++) {
287 u32 addr = regAddr[i];
288 u32 wrData, rdData;
289
290 regHold[i] = REG_READ(ah, addr);
291 for (j = 0; j < 0x100; j++) {
292 wrData = (j << 16) | j;
293 REG_WRITE(ah, addr, wrData);
294 rdData = REG_READ(ah, addr);
295 if (rdData != wrData) {
296 ath_print(common, ATH_DBG_FATAL,
297 "address test failed "
298 "addr: 0x%08x - wr:0x%08x != "
299 "rd:0x%08x\n",
300 addr, wrData, rdData);
301 return false;
302 }
303 }
304 for (j = 0; j < 4; j++) {
305 wrData = patternData[j];
306 REG_WRITE(ah, addr, wrData);
307 rdData = REG_READ(ah, addr);
308 if (wrData != rdData) {
309 ath_print(common, ATH_DBG_FATAL,
310 "address test failed "
311 "addr: 0x%08x - wr:0x%08x != "
312 "rd:0x%08x\n",
313 addr, wrData, rdData);
314 return false;
315 }
316 }
317 REG_WRITE(ah, regAddr[i], regHold[i]);
318 }
319 udelay(100);
320
321 return true;
322 }
323
324 static void ath9k_hw_init_config(struct ath_hw *ah)
325 {
326 int i;
327
328 ah->config.dma_beacon_response_time = 2;
329 ah->config.sw_beacon_response_time = 10;
330 ah->config.additional_swba_backoff = 0;
331 ah->config.ack_6mb = 0x0;
332 ah->config.cwm_ignore_extcca = 0;
333 ah->config.pcie_powersave_enable = 0;
334 ah->config.pcie_clock_req = 0;
335 ah->config.pcie_waen = 0;
336 ah->config.analog_shiftreg = 1;
337 ah->config.ofdm_trig_low = 200;
338 ah->config.ofdm_trig_high = 500;
339 ah->config.cck_trig_high = 200;
340 ah->config.cck_trig_low = 100;
341 ah->config.enable_ani = 1;
342
343 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
344 ah->config.spurchans[i][0] = AR_NO_SPUR;
345 ah->config.spurchans[i][1] = AR_NO_SPUR;
346 }
347
348 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
349 ah->config.ht_enable = 1;
350 else
351 ah->config.ht_enable = 0;
352
353 ah->config.rx_intr_mitigation = true;
354
355 /*
356 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
357 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
358 * This means we use it for all AR5416 devices, and the few
359 * minor PCI AR9280 devices out there.
360 *
361 * Serialization is required because these devices do not handle
362 * well the case of two concurrent reads/writes due to the latency
363 * involved. During one read/write another read/write can be issued
364 * on another CPU while the previous read/write may still be working
365 * on our hardware, if we hit this case the hardware poops in a loop.
366 * We prevent this by serializing reads and writes.
367 *
368 * This issue is not present on PCI-Express devices or pre-AR5416
369 * devices (legacy, 802.11abg).
370 */
371 if (num_possible_cpus() > 1)
372 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
373 }
374 EXPORT_SYMBOL(ath9k_hw_init);
375
376 static void ath9k_hw_init_defaults(struct ath_hw *ah)
377 {
378 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
379
380 regulatory->country_code = CTRY_DEFAULT;
381 regulatory->power_limit = MAX_RATE_POWER;
382 regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
383
384 ah->hw_version.magic = AR5416_MAGIC;
385 ah->hw_version.subvendorid = 0;
386
387 ah->ah_flags = 0;
388 if (ah->hw_version.devid == AR5416_AR9100_DEVID)
389 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
390 if (!AR_SREV_9100(ah))
391 ah->ah_flags = AH_USE_EEPROM;
392
393 ah->atim_window = 0;
394 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
395 ah->beacon_interval = 100;
396 ah->enable_32kHz_clock = DONT_USE_32KHZ;
397 ah->slottime = (u32) -1;
398 ah->globaltxtimeout = (u32) -1;
399 ah->power_mode = ATH9K_PM_UNDEFINED;
400 }
401
402 static int ath9k_hw_rf_claim(struct ath_hw *ah)
403 {
404 u32 val;
405
406 REG_WRITE(ah, AR_PHY(0), 0x00000007);
407
408 val = ath9k_hw_get_radiorev(ah);
409 switch (val & AR_RADIO_SREV_MAJOR) {
410 case 0:
411 val = AR_RAD5133_SREV_MAJOR;
412 break;
413 case AR_RAD5133_SREV_MAJOR:
414 case AR_RAD5122_SREV_MAJOR:
415 case AR_RAD2133_SREV_MAJOR:
416 case AR_RAD2122_SREV_MAJOR:
417 break;
418 default:
419 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
420 "Radio Chip Rev 0x%02X not supported\n",
421 val & AR_RADIO_SREV_MAJOR);
422 return -EOPNOTSUPP;
423 }
424
425 ah->hw_version.analog5GhzRev = val;
426
427 return 0;
428 }
429
430 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
431 {
432 struct ath_common *common = ath9k_hw_common(ah);
433 u32 sum;
434 int i;
435 u16 eeval;
436
437 sum = 0;
438 for (i = 0; i < 3; i++) {
439 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
440 sum += eeval;
441 common->macaddr[2 * i] = eeval >> 8;
442 common->macaddr[2 * i + 1] = eeval & 0xff;
443 }
444 if (sum == 0 || sum == 0xffff * 3)
445 return -EADDRNOTAVAIL;
446
447 return 0;
448 }
449
450 static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
451 {
452 u32 rxgain_type;
453
454 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
455 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
456
457 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
458 INIT_INI_ARRAY(&ah->iniModesRxGain,
459 ar9280Modes_backoff_13db_rxgain_9280_2,
460 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
461 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
462 INIT_INI_ARRAY(&ah->iniModesRxGain,
463 ar9280Modes_backoff_23db_rxgain_9280_2,
464 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
465 else
466 INIT_INI_ARRAY(&ah->iniModesRxGain,
467 ar9280Modes_original_rxgain_9280_2,
468 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
469 } else {
470 INIT_INI_ARRAY(&ah->iniModesRxGain,
471 ar9280Modes_original_rxgain_9280_2,
472 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
473 }
474 }
475
476 static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
477 {
478 u32 txgain_type;
479
480 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
481 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
482
483 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
484 INIT_INI_ARRAY(&ah->iniModesTxGain,
485 ar9280Modes_high_power_tx_gain_9280_2,
486 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
487 else
488 INIT_INI_ARRAY(&ah->iniModesTxGain,
489 ar9280Modes_original_tx_gain_9280_2,
490 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
491 } else {
492 INIT_INI_ARRAY(&ah->iniModesTxGain,
493 ar9280Modes_original_tx_gain_9280_2,
494 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
495 }
496 }
497
498 static int ath9k_hw_post_init(struct ath_hw *ah)
499 {
500 int ecode;
501
502 if (!AR_SREV_9271(ah)) {
503 if (!ath9k_hw_chip_test(ah))
504 return -ENODEV;
505 }
506
507 ecode = ath9k_hw_rf_claim(ah);
508 if (ecode != 0)
509 return ecode;
510
511 ecode = ath9k_hw_eeprom_init(ah);
512 if (ecode != 0)
513 return ecode;
514
515 ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
516 "Eeprom VER: %d, REV: %d\n",
517 ah->eep_ops->get_eeprom_ver(ah),
518 ah->eep_ops->get_eeprom_rev(ah));
519
520 if (!AR_SREV_9280_10_OR_LATER(ah)) {
521 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
522 if (ecode) {
523 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
524 "Failed allocating banks for "
525 "external radio\n");
526 return ecode;
527 }
528 }
529
530 if (!AR_SREV_9100(ah)) {
531 ath9k_hw_ani_setup(ah);
532 ath9k_hw_ani_init(ah);
533 }
534
535 return 0;
536 }
537
538 static bool ath9k_hw_devid_supported(u16 devid)
539 {
540 switch (devid) {
541 case AR5416_DEVID_PCI:
542 case AR5416_DEVID_PCIE:
543 case AR5416_AR9100_DEVID:
544 case AR9160_DEVID_PCI:
545 case AR9280_DEVID_PCI:
546 case AR9280_DEVID_PCIE:
547 case AR9285_DEVID_PCIE:
548 case AR5416_DEVID_AR9287_PCI:
549 case AR5416_DEVID_AR9287_PCIE:
550 case AR9271_USB:
551 case AR2427_DEVID_PCIE:
552 return true;
553 default:
554 break;
555 }
556 return false;
557 }
558
559 static bool ath9k_hw_macversion_supported(u32 macversion)
560 {
561 switch (macversion) {
562 case AR_SREV_VERSION_5416_PCI:
563 case AR_SREV_VERSION_5416_PCIE:
564 case AR_SREV_VERSION_9160:
565 case AR_SREV_VERSION_9100:
566 case AR_SREV_VERSION_9280:
567 case AR_SREV_VERSION_9285:
568 case AR_SREV_VERSION_9287:
569 case AR_SREV_VERSION_9271:
570 return true;
571 default:
572 break;
573 }
574 return false;
575 }
576
577 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
578 {
579 if (AR_SREV_9160_10_OR_LATER(ah)) {
580 if (AR_SREV_9280_10_OR_LATER(ah)) {
581 ah->iq_caldata.calData = &iq_cal_single_sample;
582 ah->adcgain_caldata.calData =
583 &adc_gain_cal_single_sample;
584 ah->adcdc_caldata.calData =
585 &adc_dc_cal_single_sample;
586 ah->adcdc_calinitdata.calData =
587 &adc_init_dc_cal;
588 } else {
589 ah->iq_caldata.calData = &iq_cal_multi_sample;
590 ah->adcgain_caldata.calData =
591 &adc_gain_cal_multi_sample;
592 ah->adcdc_caldata.calData =
593 &adc_dc_cal_multi_sample;
594 ah->adcdc_calinitdata.calData =
595 &adc_init_dc_cal;
596 }
597 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
598 }
599 }
600
601 static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
602 {
603 if (AR_SREV_9271(ah)) {
604 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271,
605 ARRAY_SIZE(ar9271Modes_9271), 6);
606 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271,
607 ARRAY_SIZE(ar9271Common_9271), 2);
608 INIT_INI_ARRAY(&ah->iniCommon_normal_cck_fir_coeff_9271,
609 ar9271Common_normal_cck_fir_coeff_9271,
610 ARRAY_SIZE(ar9271Common_normal_cck_fir_coeff_9271), 2);
611 INIT_INI_ARRAY(&ah->iniCommon_japan_2484_cck_fir_coeff_9271,
612 ar9271Common_japan_2484_cck_fir_coeff_9271,
613 ARRAY_SIZE(ar9271Common_japan_2484_cck_fir_coeff_9271), 2);
614 INIT_INI_ARRAY(&ah->iniModes_9271_1_0_only,
615 ar9271Modes_9271_1_0_only,
616 ARRAY_SIZE(ar9271Modes_9271_1_0_only), 6);
617 INIT_INI_ARRAY(&ah->iniModes_9271_ANI_reg, ar9271Modes_9271_ANI_reg,
618 ARRAY_SIZE(ar9271Modes_9271_ANI_reg), 6);
619 INIT_INI_ARRAY(&ah->iniModes_high_power_tx_gain_9271,
620 ar9271Modes_high_power_tx_gain_9271,
621 ARRAY_SIZE(ar9271Modes_high_power_tx_gain_9271), 6);
622 INIT_INI_ARRAY(&ah->iniModes_normal_power_tx_gain_9271,
623 ar9271Modes_normal_power_tx_gain_9271,
624 ARRAY_SIZE(ar9271Modes_normal_power_tx_gain_9271), 6);
625 return;
626 }
627
628 if (AR_SREV_9287_11_OR_LATER(ah)) {
629 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
630 ARRAY_SIZE(ar9287Modes_9287_1_1), 6);
631 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
632 ARRAY_SIZE(ar9287Common_9287_1_1), 2);
633 if (ah->config.pcie_clock_req)
634 INIT_INI_ARRAY(&ah->iniPcieSerdes,
635 ar9287PciePhy_clkreq_off_L1_9287_1_1,
636 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2);
637 else
638 INIT_INI_ARRAY(&ah->iniPcieSerdes,
639 ar9287PciePhy_clkreq_always_on_L1_9287_1_1,
640 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1),
641 2);
642 } else if (AR_SREV_9287_10_OR_LATER(ah)) {
643 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0,
644 ARRAY_SIZE(ar9287Modes_9287_1_0), 6);
645 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0,
646 ARRAY_SIZE(ar9287Common_9287_1_0), 2);
647
648 if (ah->config.pcie_clock_req)
649 INIT_INI_ARRAY(&ah->iniPcieSerdes,
650 ar9287PciePhy_clkreq_off_L1_9287_1_0,
651 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2);
652 else
653 INIT_INI_ARRAY(&ah->iniPcieSerdes,
654 ar9287PciePhy_clkreq_always_on_L1_9287_1_0,
655 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0),
656 2);
657 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
658
659
660 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
661 ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
662 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
663 ARRAY_SIZE(ar9285Common_9285_1_2), 2);
664
665 if (ah->config.pcie_clock_req) {
666 INIT_INI_ARRAY(&ah->iniPcieSerdes,
667 ar9285PciePhy_clkreq_off_L1_9285_1_2,
668 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
669 } else {
670 INIT_INI_ARRAY(&ah->iniPcieSerdes,
671 ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
672 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
673 2);
674 }
675 } else if (AR_SREV_9285_10_OR_LATER(ah)) {
676 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
677 ARRAY_SIZE(ar9285Modes_9285), 6);
678 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
679 ARRAY_SIZE(ar9285Common_9285), 2);
680
681 if (ah->config.pcie_clock_req) {
682 INIT_INI_ARRAY(&ah->iniPcieSerdes,
683 ar9285PciePhy_clkreq_off_L1_9285,
684 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
685 } else {
686 INIT_INI_ARRAY(&ah->iniPcieSerdes,
687 ar9285PciePhy_clkreq_always_on_L1_9285,
688 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
689 }
690 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
691 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
692 ARRAY_SIZE(ar9280Modes_9280_2), 6);
693 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
694 ARRAY_SIZE(ar9280Common_9280_2), 2);
695
696 if (ah->config.pcie_clock_req) {
697 INIT_INI_ARRAY(&ah->iniPcieSerdes,
698 ar9280PciePhy_clkreq_off_L1_9280,
699 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
700 } else {
701 INIT_INI_ARRAY(&ah->iniPcieSerdes,
702 ar9280PciePhy_clkreq_always_on_L1_9280,
703 ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
704 }
705 INIT_INI_ARRAY(&ah->iniModesAdditional,
706 ar9280Modes_fast_clock_9280_2,
707 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
708 } else if (AR_SREV_9280_10_OR_LATER(ah)) {
709 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
710 ARRAY_SIZE(ar9280Modes_9280), 6);
711 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
712 ARRAY_SIZE(ar9280Common_9280), 2);
713 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
714 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
715 ARRAY_SIZE(ar5416Modes_9160), 6);
716 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
717 ARRAY_SIZE(ar5416Common_9160), 2);
718 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
719 ARRAY_SIZE(ar5416Bank0_9160), 2);
720 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
721 ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
722 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
723 ARRAY_SIZE(ar5416Bank1_9160), 2);
724 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
725 ARRAY_SIZE(ar5416Bank2_9160), 2);
726 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
727 ARRAY_SIZE(ar5416Bank3_9160), 3);
728 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
729 ARRAY_SIZE(ar5416Bank6_9160), 3);
730 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
731 ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
732 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
733 ARRAY_SIZE(ar5416Bank7_9160), 2);
734 if (AR_SREV_9160_11(ah)) {
735 INIT_INI_ARRAY(&ah->iniAddac,
736 ar5416Addac_91601_1,
737 ARRAY_SIZE(ar5416Addac_91601_1), 2);
738 } else {
739 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
740 ARRAY_SIZE(ar5416Addac_9160), 2);
741 }
742 } else if (AR_SREV_9100_OR_LATER(ah)) {
743 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
744 ARRAY_SIZE(ar5416Modes_9100), 6);
745 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
746 ARRAY_SIZE(ar5416Common_9100), 2);
747 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
748 ARRAY_SIZE(ar5416Bank0_9100), 2);
749 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
750 ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
751 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
752 ARRAY_SIZE(ar5416Bank1_9100), 2);
753 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
754 ARRAY_SIZE(ar5416Bank2_9100), 2);
755 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
756 ARRAY_SIZE(ar5416Bank3_9100), 3);
757 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
758 ARRAY_SIZE(ar5416Bank6_9100), 3);
759 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
760 ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
761 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
762 ARRAY_SIZE(ar5416Bank7_9100), 2);
763 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
764 ARRAY_SIZE(ar5416Addac_9100), 2);
765 } else {
766 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
767 ARRAY_SIZE(ar5416Modes), 6);
768 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
769 ARRAY_SIZE(ar5416Common), 2);
770 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
771 ARRAY_SIZE(ar5416Bank0), 2);
772 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
773 ARRAY_SIZE(ar5416BB_RfGain), 3);
774 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
775 ARRAY_SIZE(ar5416Bank1), 2);
776 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
777 ARRAY_SIZE(ar5416Bank2), 2);
778 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
779 ARRAY_SIZE(ar5416Bank3), 3);
780 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
781 ARRAY_SIZE(ar5416Bank6), 3);
782 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
783 ARRAY_SIZE(ar5416Bank6TPC), 3);
784 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
785 ARRAY_SIZE(ar5416Bank7), 2);
786 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
787 ARRAY_SIZE(ar5416Addac), 2);
788 }
789 }
790
791 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
792 {
793 if (AR_SREV_9287_11_OR_LATER(ah))
794 INIT_INI_ARRAY(&ah->iniModesRxGain,
795 ar9287Modes_rx_gain_9287_1_1,
796 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
797 else if (AR_SREV_9287_10(ah))
798 INIT_INI_ARRAY(&ah->iniModesRxGain,
799 ar9287Modes_rx_gain_9287_1_0,
800 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6);
801 else if (AR_SREV_9280_20(ah))
802 ath9k_hw_init_rxgain_ini(ah);
803
804 if (AR_SREV_9287_11_OR_LATER(ah)) {
805 INIT_INI_ARRAY(&ah->iniModesTxGain,
806 ar9287Modes_tx_gain_9287_1_1,
807 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
808 } else if (AR_SREV_9287_10(ah)) {
809 INIT_INI_ARRAY(&ah->iniModesTxGain,
810 ar9287Modes_tx_gain_9287_1_0,
811 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6);
812 } else if (AR_SREV_9280_20(ah)) {
813 ath9k_hw_init_txgain_ini(ah);
814 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
815 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
816
817 /* txgain table */
818 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
819 INIT_INI_ARRAY(&ah->iniModesTxGain,
820 ar9285Modes_high_power_tx_gain_9285_1_2,
821 ARRAY_SIZE(ar9285Modes_high_power_tx_gain_9285_1_2), 6);
822 } else {
823 INIT_INI_ARRAY(&ah->iniModesTxGain,
824 ar9285Modes_original_tx_gain_9285_1_2,
825 ARRAY_SIZE(ar9285Modes_original_tx_gain_9285_1_2), 6);
826 }
827
828 }
829 }
830
831 static void ath9k_hw_init_eeprom_fix(struct ath_hw *ah)
832 {
833 u32 i, j;
834
835 if (ah->hw_version.devid == AR9280_DEVID_PCI) {
836
837 /* EEPROM Fixup */
838 for (i = 0; i < ah->iniModes.ia_rows; i++) {
839 u32 reg = INI_RA(&ah->iniModes, i, 0);
840
841 for (j = 1; j < ah->iniModes.ia_columns; j++) {
842 u32 val = INI_RA(&ah->iniModes, i, j);
843
844 INI_RA(&ah->iniModes, i, j) =
845 ath9k_hw_ini_fixup(ah,
846 &ah->eeprom.def,
847 reg, val);
848 }
849 }
850 }
851 }
852
853 int ath9k_hw_init(struct ath_hw *ah)
854 {
855 struct ath_common *common = ath9k_hw_common(ah);
856 int r = 0;
857
858 if (!ath9k_hw_devid_supported(ah->hw_version.devid)) {
859 ath_print(common, ATH_DBG_FATAL,
860 "Unsupported device ID: 0x%0x\n",
861 ah->hw_version.devid);
862 return -EOPNOTSUPP;
863 }
864
865 ath9k_hw_init_defaults(ah);
866 ath9k_hw_init_config(ah);
867
868 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
869 ath_print(common, ATH_DBG_FATAL,
870 "Couldn't reset chip\n");
871 return -EIO;
872 }
873
874 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
875 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
876 return -EIO;
877 }
878
879 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
880 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
881 (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
882 ah->config.serialize_regmode =
883 SER_REG_MODE_ON;
884 } else {
885 ah->config.serialize_regmode =
886 SER_REG_MODE_OFF;
887 }
888 }
889
890 ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
891 ah->config.serialize_regmode);
892
893 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
894 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
895 else
896 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
897
898 if (!ath9k_hw_macversion_supported(ah->hw_version.macVersion)) {
899 ath_print(common, ATH_DBG_FATAL,
900 "Mac Chip Rev 0x%02x.%x is not supported by "
901 "this driver\n", ah->hw_version.macVersion,
902 ah->hw_version.macRev);
903 return -EOPNOTSUPP;
904 }
905
906 if (AR_SREV_9100(ah)) {
907 ah->iq_caldata.calData = &iq_cal_multi_sample;
908 ah->supp_cals = IQ_MISMATCH_CAL;
909 ah->is_pciexpress = false;
910 }
911
912 if (AR_SREV_9271(ah))
913 ah->is_pciexpress = false;
914
915 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
916
917 ath9k_hw_init_cal_settings(ah);
918
919 ah->ani_function = ATH9K_ANI_ALL;
920 if (AR_SREV_9280_10_OR_LATER(ah)) {
921 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
922 ah->ath9k_hw_rf_set_freq = &ath9k_hw_ar9280_set_channel;
923 ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_9280_spur_mitigate;
924 } else {
925 ah->ath9k_hw_rf_set_freq = &ath9k_hw_set_channel;
926 ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_spur_mitigate;
927 }
928
929 ath9k_hw_init_mode_regs(ah);
930
931 if (ah->is_pciexpress)
932 ath9k_hw_configpcipowersave(ah, 0, 0);
933 else
934 ath9k_hw_disablepcie(ah);
935
936 /* Support for Japan ch.14 (2484) spread */
937 if (AR_SREV_9287_11_OR_LATER(ah)) {
938 INIT_INI_ARRAY(&ah->iniCckfirNormal,
939 ar9287Common_normal_cck_fir_coeff_92871_1,
940 ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_92871_1), 2);
941 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
942 ar9287Common_japan_2484_cck_fir_coeff_92871_1,
943 ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_92871_1), 2);
944 }
945
946 r = ath9k_hw_post_init(ah);
947 if (r)
948 return r;
949
950 ath9k_hw_init_mode_gain_regs(ah);
951 r = ath9k_hw_fill_cap_info(ah);
952 if (r)
953 return r;
954
955 ath9k_hw_init_eeprom_fix(ah);
956
957 r = ath9k_hw_init_macaddr(ah);
958 if (r) {
959 ath_print(common, ATH_DBG_FATAL,
960 "Failed to initialize MAC address\n");
961 return r;
962 }
963
964 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
965 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
966 else
967 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
968
969 ath9k_init_nfcal_hist_buffer(ah);
970
971 common->state = ATH_HW_INITIALIZED;
972
973 return 0;
974 }
975
976 static void ath9k_hw_init_bb(struct ath_hw *ah,
977 struct ath9k_channel *chan)
978 {
979 u32 synthDelay;
980
981 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
982 if (IS_CHAN_B(chan))
983 synthDelay = (4 * synthDelay) / 22;
984 else
985 synthDelay /= 10;
986
987 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
988
989 udelay(synthDelay + BASE_ACTIVATE_DELAY);
990 }
991
992 static void ath9k_hw_init_qos(struct ath_hw *ah)
993 {
994 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
995 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
996
997 REG_WRITE(ah, AR_QOS_NO_ACK,
998 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
999 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
1000 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
1001
1002 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
1003 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
1004 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
1005 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
1006 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
1007 }
1008
1009 static void ath9k_hw_change_target_baud(struct ath_hw *ah, u32 freq, u32 baud)
1010 {
1011 u32 lcr;
1012 u32 baud_divider = freq * 1000 * 1000 / 16 / baud;
1013
1014 lcr = REG_READ(ah , 0x5100c);
1015 lcr |= 0x80;
1016
1017 REG_WRITE(ah, 0x5100c, lcr);
1018 REG_WRITE(ah, 0x51004, (baud_divider >> 8));
1019 REG_WRITE(ah, 0x51000, (baud_divider & 0xff));
1020
1021 lcr &= ~0x80;
1022 REG_WRITE(ah, 0x5100c, lcr);
1023 }
1024
1025 static void ath9k_hw_init_pll(struct ath_hw *ah,
1026 struct ath9k_channel *chan)
1027 {
1028 u32 pll;
1029
1030 if (AR_SREV_9100(ah)) {
1031 if (chan && IS_CHAN_5GHZ(chan))
1032 pll = 0x1450;
1033 else
1034 pll = 0x1458;
1035 } else {
1036 if (AR_SREV_9280_10_OR_LATER(ah)) {
1037 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1038
1039 if (chan && IS_CHAN_HALF_RATE(chan))
1040 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1041 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1042 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1043
1044 if (chan && IS_CHAN_5GHZ(chan)) {
1045 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
1046
1047
1048 if (AR_SREV_9280_20(ah)) {
1049 if (((chan->channel % 20) == 0)
1050 || ((chan->channel % 10) == 0))
1051 pll = 0x2850;
1052 else
1053 pll = 0x142c;
1054 }
1055 } else {
1056 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
1057 }
1058
1059 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1060
1061 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1062
1063 if (chan && IS_CHAN_HALF_RATE(chan))
1064 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1065 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1066 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1067
1068 if (chan && IS_CHAN_5GHZ(chan))
1069 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1070 else
1071 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1072 } else {
1073 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
1074
1075 if (chan && IS_CHAN_HALF_RATE(chan))
1076 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1077 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1078 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1079
1080 if (chan && IS_CHAN_5GHZ(chan))
1081 pll |= SM(0xa, AR_RTC_PLL_DIV);
1082 else
1083 pll |= SM(0xb, AR_RTC_PLL_DIV);
1084 }
1085 }
1086 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
1087
1088 /* Switch the core clock for ar9271 to 117Mhz */
1089 if (AR_SREV_9271(ah)) {
1090 if ((pll == 0x142c) || (pll == 0x2850) ) {
1091 udelay(500);
1092 /* set CLKOBS to output AHB clock */
1093 REG_WRITE(ah, 0x7020, 0xe);
1094 /*
1095 * 0x304: 117Mhz, ahb_ratio: 1x1
1096 * 0x306: 40Mhz, ahb_ratio: 1x1
1097 */
1098 REG_WRITE(ah, 0x50040, 0x304);
1099 /*
1100 * makes adjustments for the baud dividor to keep the
1101 * targetted baud rate based on the used core clock.
1102 */
1103 ath9k_hw_change_target_baud(ah, AR9271_CORE_CLOCK,
1104 AR9271_TARGET_BAUD_RATE);
1105 }
1106 }
1107
1108 udelay(RTC_PLL_SETTLE_DELAY);
1109
1110 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1111 }
1112
1113 static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
1114 {
1115 int rx_chainmask, tx_chainmask;
1116
1117 rx_chainmask = ah->rxchainmask;
1118 tx_chainmask = ah->txchainmask;
1119
1120 switch (rx_chainmask) {
1121 case 0x5:
1122 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1123 AR_PHY_SWAP_ALT_CHAIN);
1124 case 0x3:
1125 if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) {
1126 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1127 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1128 break;
1129 }
1130 case 0x1:
1131 case 0x2:
1132 case 0x7:
1133 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1134 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1135 break;
1136 default:
1137 break;
1138 }
1139
1140 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1141 if (tx_chainmask == 0x5) {
1142 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1143 AR_PHY_SWAP_ALT_CHAIN);
1144 }
1145 if (AR_SREV_9100(ah))
1146 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1147 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1148 }
1149
1150 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
1151 enum nl80211_iftype opmode)
1152 {
1153 ah->mask_reg = AR_IMR_TXERR |
1154 AR_IMR_TXURN |
1155 AR_IMR_RXERR |
1156 AR_IMR_RXORN |
1157 AR_IMR_BCNMISC;
1158
1159 if (ah->config.rx_intr_mitigation)
1160 ah->mask_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1161 else
1162 ah->mask_reg |= AR_IMR_RXOK;
1163
1164 ah->mask_reg |= AR_IMR_TXOK;
1165
1166 if (opmode == NL80211_IFTYPE_AP)
1167 ah->mask_reg |= AR_IMR_MIB;
1168
1169 REG_WRITE(ah, AR_IMR, ah->mask_reg);
1170 ah->imrs2_reg |= AR_IMR_S2_GTT;
1171 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
1172
1173 if (!AR_SREV_9100(ah)) {
1174 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1175 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1176 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1177 }
1178 }
1179
1180 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
1181 {
1182 u32 val = ath9k_hw_mac_to_clks(ah, us);
1183 val = min(val, (u32) 0xFFFF);
1184 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
1185 }
1186
1187 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1188 {
1189 u32 val = ath9k_hw_mac_to_clks(ah, us);
1190 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
1191 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
1192 }
1193
1194 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1195 {
1196 u32 val = ath9k_hw_mac_to_clks(ah, us);
1197 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
1198 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
1199 }
1200
1201 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1202 {
1203 if (tu > 0xFFFF) {
1204 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
1205 "bad global tx timeout %u\n", tu);
1206 ah->globaltxtimeout = (u32) -1;
1207 return false;
1208 } else {
1209 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1210 ah->globaltxtimeout = tu;
1211 return true;
1212 }
1213 }
1214
1215 void ath9k_hw_init_global_settings(struct ath_hw *ah)
1216 {
1217 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
1218 int acktimeout;
1219 int slottime;
1220 int sifstime;
1221
1222 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
1223 ah->misc_mode);
1224
1225 if (ah->misc_mode != 0)
1226 REG_WRITE(ah, AR_PCU_MISC,
1227 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
1228
1229 if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
1230 sifstime = 16;
1231 else
1232 sifstime = 10;
1233
1234 /* As defined by IEEE 802.11-2007 17.3.8.6 */
1235 slottime = ah->slottime + 3 * ah->coverage_class;
1236 acktimeout = slottime + sifstime;
1237
1238 /*
1239 * Workaround for early ACK timeouts, add an offset to match the
1240 * initval's 64us ack timeout value.
1241 * This was initially only meant to work around an issue with delayed
1242 * BA frames in some implementations, but it has been found to fix ACK
1243 * timeout issues in other cases as well.
1244 */
1245 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
1246 acktimeout += 64 - sifstime - ah->slottime;
1247
1248 ath9k_hw_setslottime(ah, slottime);
1249 ath9k_hw_set_ack_timeout(ah, acktimeout);
1250 ath9k_hw_set_cts_timeout(ah, acktimeout);
1251 if (ah->globaltxtimeout != (u32) -1)
1252 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1253 }
1254 EXPORT_SYMBOL(ath9k_hw_init_global_settings);
1255
1256 void ath9k_hw_deinit(struct ath_hw *ah)
1257 {
1258 struct ath_common *common = ath9k_hw_common(ah);
1259
1260 if (common->state <= ATH_HW_INITIALIZED)
1261 goto free_hw;
1262
1263 if (!AR_SREV_9100(ah))
1264 ath9k_hw_ani_disable(ah);
1265
1266 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1267
1268 free_hw:
1269 if (!AR_SREV_9280_10_OR_LATER(ah))
1270 ath9k_hw_rf_free_ext_banks(ah);
1271 kfree(ah);
1272 ah = NULL;
1273 }
1274 EXPORT_SYMBOL(ath9k_hw_deinit);
1275
1276 /*******/
1277 /* INI */
1278 /*******/
1279
1280 static void ath9k_hw_override_ini(struct ath_hw *ah,
1281 struct ath9k_channel *chan)
1282 {
1283 u32 val;
1284
1285 /*
1286 * Set the RX_ABORT and RX_DIS and clear if off only after
1287 * RXE is set for MAC. This prevents frames with corrupted
1288 * descriptor status.
1289 */
1290 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1291
1292 if (AR_SREV_9280_10_OR_LATER(ah)) {
1293 val = REG_READ(ah, AR_PCU_MISC_MODE2);
1294
1295 if (!AR_SREV_9271(ah))
1296 val &= ~AR_PCU_MISC_MODE2_HWWAR1;
1297
1298 if (AR_SREV_9287_10_OR_LATER(ah))
1299 val = val & (~AR_PCU_MISC_MODE2_HWWAR2);
1300
1301 REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
1302 }
1303
1304 if (!AR_SREV_5416_20_OR_LATER(ah) ||
1305 AR_SREV_9280_10_OR_LATER(ah))
1306 return;
1307 /*
1308 * Disable BB clock gating
1309 * Necessary to avoid issues on AR5416 2.0
1310 */
1311 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1312
1313 /*
1314 * Disable RIFS search on some chips to avoid baseband
1315 * hang issues.
1316 */
1317 if (AR_SREV_9100(ah) || AR_SREV_9160(ah)) {
1318 val = REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS);
1319 val &= ~AR_PHY_RIFS_INIT_DELAY;
1320 REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val);
1321 }
1322 }
1323
1324 static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah,
1325 struct ar5416_eeprom_def *pEepData,
1326 u32 reg, u32 value)
1327 {
1328 struct base_eep_header *pBase = &(pEepData->baseEepHeader);
1329 struct ath_common *common = ath9k_hw_common(ah);
1330
1331 switch (ah->hw_version.devid) {
1332 case AR9280_DEVID_PCI:
1333 if (reg == 0x7894) {
1334 ath_print(common, ATH_DBG_EEPROM,
1335 "ini VAL: %x EEPROM: %x\n", value,
1336 (pBase->version & 0xff));
1337
1338 if ((pBase->version & 0xff) > 0x0a) {
1339 ath_print(common, ATH_DBG_EEPROM,
1340 "PWDCLKIND: %d\n",
1341 pBase->pwdclkind);
1342 value &= ~AR_AN_TOP2_PWDCLKIND;
1343 value |= AR_AN_TOP2_PWDCLKIND &
1344 (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1345 } else {
1346 ath_print(common, ATH_DBG_EEPROM,
1347 "PWDCLKIND Earlier Rev\n");
1348 }
1349
1350 ath_print(common, ATH_DBG_EEPROM,
1351 "final ini VAL: %x\n", value);
1352 }
1353 break;
1354 }
1355
1356 return value;
1357 }
1358
1359 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
1360 struct ar5416_eeprom_def *pEepData,
1361 u32 reg, u32 value)
1362 {
1363 if (ah->eep_map == EEP_MAP_4KBITS)
1364 return value;
1365 else
1366 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
1367 }
1368
1369 static void ath9k_olc_init(struct ath_hw *ah)
1370 {
1371 u32 i;
1372
1373 if (OLC_FOR_AR9287_10_LATER) {
1374 REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9,
1375 AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL);
1376 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TXPC0,
1377 AR9287_AN_TXPC0_TXPCMODE,
1378 AR9287_AN_TXPC0_TXPCMODE_S,
1379 AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE);
1380 udelay(100);
1381 } else {
1382 for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
1383 ah->originalGain[i] =
1384 MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
1385 AR_PHY_TX_GAIN);
1386 ah->PDADCdelta = 0;
1387 }
1388 }
1389
1390 static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg,
1391 struct ath9k_channel *chan)
1392 {
1393 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1394
1395 if (IS_CHAN_B(chan))
1396 ctl |= CTL_11B;
1397 else if (IS_CHAN_G(chan))
1398 ctl |= CTL_11G;
1399 else
1400 ctl |= CTL_11A;
1401
1402 return ctl;
1403 }
1404
1405 static int ath9k_hw_process_ini(struct ath_hw *ah,
1406 struct ath9k_channel *chan)
1407 {
1408 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1409 int i, regWrites = 0;
1410 struct ieee80211_channel *channel = chan->chan;
1411 u32 modesIndex, freqIndex;
1412
1413 switch (chan->chanmode) {
1414 case CHANNEL_A:
1415 case CHANNEL_A_HT20:
1416 modesIndex = 1;
1417 freqIndex = 1;
1418 break;
1419 case CHANNEL_A_HT40PLUS:
1420 case CHANNEL_A_HT40MINUS:
1421 modesIndex = 2;
1422 freqIndex = 1;
1423 break;
1424 case CHANNEL_G:
1425 case CHANNEL_G_HT20:
1426 case CHANNEL_B:
1427 modesIndex = 4;
1428 freqIndex = 2;
1429 break;
1430 case CHANNEL_G_HT40PLUS:
1431 case CHANNEL_G_HT40MINUS:
1432 modesIndex = 3;
1433 freqIndex = 2;
1434 break;
1435
1436 default:
1437 return -EINVAL;
1438 }
1439
1440 /* Set correct baseband to analog shift setting to access analog chips */
1441 REG_WRITE(ah, AR_PHY(0), 0x00000007);
1442
1443 /* Write ADDAC shifts */
1444 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1445 ah->eep_ops->set_addac(ah, chan);
1446
1447 if (AR_SREV_5416_22_OR_LATER(ah)) {
1448 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
1449 } else {
1450 struct ar5416IniArray temp;
1451 u32 addacSize =
1452 sizeof(u32) * ah->iniAddac.ia_rows *
1453 ah->iniAddac.ia_columns;
1454
1455 /* For AR5416 2.0/2.1 */
1456 memcpy(ah->addac5416_21,
1457 ah->iniAddac.ia_array, addacSize);
1458
1459 /* override CLKDRV value at [row, column] = [31, 1] */
1460 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
1461
1462 temp.ia_array = ah->addac5416_21;
1463 temp.ia_columns = ah->iniAddac.ia_columns;
1464 temp.ia_rows = ah->iniAddac.ia_rows;
1465 REG_WRITE_ARRAY(&temp, 1, regWrites);
1466 }
1467
1468 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1469
1470 for (i = 0; i < ah->iniModes.ia_rows; i++) {
1471 u32 reg = INI_RA(&ah->iniModes, i, 0);
1472 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
1473
1474 REG_WRITE(ah, reg, val);
1475
1476 if (reg >= 0x7800 && reg < 0x78a0
1477 && ah->config.analog_shiftreg) {
1478 udelay(100);
1479 }
1480
1481 DO_DELAY(regWrites);
1482 }
1483
1484 if (AR_SREV_9280(ah) || AR_SREV_9287_10_OR_LATER(ah))
1485 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
1486
1487 if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
1488 AR_SREV_9287_10_OR_LATER(ah))
1489 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1490
1491 if (AR_SREV_9271_10(ah))
1492 REG_WRITE_ARRAY(&ah->iniModes_9271_1_0_only,
1493 modesIndex, regWrites);
1494
1495 /* Write common array parameters */
1496 for (i = 0; i < ah->iniCommon.ia_rows; i++) {
1497 u32 reg = INI_RA(&ah->iniCommon, i, 0);
1498 u32 val = INI_RA(&ah->iniCommon, i, 1);
1499
1500 REG_WRITE(ah, reg, val);
1501
1502 if (reg >= 0x7800 && reg < 0x78a0
1503 && ah->config.analog_shiftreg) {
1504 udelay(100);
1505 }
1506
1507 DO_DELAY(regWrites);
1508 }
1509
1510 if (AR_SREV_9271(ah)) {
1511 if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) == 1)
1512 REG_WRITE_ARRAY(&ah->iniModes_high_power_tx_gain_9271,
1513 modesIndex, regWrites);
1514 else
1515 REG_WRITE_ARRAY(&ah->iniModes_normal_power_tx_gain_9271,
1516 modesIndex, regWrites);
1517 }
1518
1519 ath9k_hw_write_regs(ah, freqIndex, regWrites);
1520
1521 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1522 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
1523 regWrites);
1524 }
1525
1526 ath9k_hw_override_ini(ah, chan);
1527 ath9k_hw_set_regs(ah, chan);
1528 ath9k_hw_init_chain_masks(ah);
1529
1530 if (OLC_FOR_AR9280_20_LATER)
1531 ath9k_olc_init(ah);
1532
1533 /* Set TX power */
1534 ah->eep_ops->set_txpower(ah, chan,
1535 ath9k_regd_get_ctl(regulatory, chan),
1536 channel->max_antenna_gain * 2,
1537 channel->max_power * 2,
1538 min((u32) MAX_RATE_POWER,
1539 (u32) regulatory->power_limit));
1540
1541 /* Write analog registers */
1542 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1543 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1544 "ar5416SetRfRegs failed\n");
1545 return -EIO;
1546 }
1547
1548 return 0;
1549 }
1550
1551 /****************************************/
1552 /* Reset and Channel Switching Routines */
1553 /****************************************/
1554
1555 static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
1556 {
1557 u32 rfMode = 0;
1558
1559 if (chan == NULL)
1560 return;
1561
1562 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1563 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1564
1565 if (!AR_SREV_9280_10_OR_LATER(ah))
1566 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1567 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1568
1569 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1570 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1571
1572 REG_WRITE(ah, AR_PHY_MODE, rfMode);
1573 }
1574
1575 static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
1576 {
1577 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1578 }
1579
1580 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1581 {
1582 u32 regval;
1583
1584 /*
1585 * set AHB_MODE not to do cacheline prefetches
1586 */
1587 regval = REG_READ(ah, AR_AHB_MODE);
1588 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1589
1590 /*
1591 * let mac dma reads be in 128 byte chunks
1592 */
1593 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1594 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1595
1596 /*
1597 * Restore TX Trigger Level to its pre-reset value.
1598 * The initial value depends on whether aggregation is enabled, and is
1599 * adjusted whenever underruns are detected.
1600 */
1601 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1602
1603 /*
1604 * let mac dma writes be in 128 byte chunks
1605 */
1606 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1607 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1608
1609 /*
1610 * Setup receive FIFO threshold to hold off TX activities
1611 */
1612 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1613
1614 /*
1615 * reduce the number of usable entries in PCU TXBUF to avoid
1616 * wrap around issues.
1617 */
1618 if (AR_SREV_9285(ah)) {
1619 /* For AR9285 the number of Fifos are reduced to half.
1620 * So set the usable tx buf size also to half to
1621 * avoid data/delimiter underruns
1622 */
1623 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1624 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1625 } else if (!AR_SREV_9271(ah)) {
1626 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1627 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1628 }
1629 }
1630
1631 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1632 {
1633 u32 val;
1634
1635 val = REG_READ(ah, AR_STA_ID1);
1636 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1637 switch (opmode) {
1638 case NL80211_IFTYPE_AP:
1639 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1640 | AR_STA_ID1_KSRCH_MODE);
1641 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1642 break;
1643 case NL80211_IFTYPE_ADHOC:
1644 case NL80211_IFTYPE_MESH_POINT:
1645 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1646 | AR_STA_ID1_KSRCH_MODE);
1647 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1648 break;
1649 case NL80211_IFTYPE_STATION:
1650 case NL80211_IFTYPE_MONITOR:
1651 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1652 break;
1653 }
1654 }
1655
1656 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
1657 u32 coef_scaled,
1658 u32 *coef_mantissa,
1659 u32 *coef_exponent)
1660 {
1661 u32 coef_exp, coef_man;
1662
1663 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1664 if ((coef_scaled >> coef_exp) & 0x1)
1665 break;
1666
1667 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1668
1669 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1670
1671 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1672 *coef_exponent = coef_exp - 16;
1673 }
1674
1675 static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
1676 struct ath9k_channel *chan)
1677 {
1678 u32 coef_scaled, ds_coef_exp, ds_coef_man;
1679 u32 clockMhzScaled = 0x64000000;
1680 struct chan_centers centers;
1681
1682 if (IS_CHAN_HALF_RATE(chan))
1683 clockMhzScaled = clockMhzScaled >> 1;
1684 else if (IS_CHAN_QUARTER_RATE(chan))
1685 clockMhzScaled = clockMhzScaled >> 2;
1686
1687 ath9k_hw_get_channel_centers(ah, chan, &centers);
1688 coef_scaled = clockMhzScaled / centers.synth_center;
1689
1690 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1691 &ds_coef_exp);
1692
1693 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1694 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1695 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1696 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1697
1698 coef_scaled = (9 * coef_scaled) / 10;
1699
1700 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1701 &ds_coef_exp);
1702
1703 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1704 AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1705 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1706 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1707 }
1708
1709 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1710 {
1711 u32 rst_flags;
1712 u32 tmpReg;
1713
1714 if (AR_SREV_9100(ah)) {
1715 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
1716 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
1717 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1718 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1719 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1720 }
1721
1722 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1723 AR_RTC_FORCE_WAKE_ON_INT);
1724
1725 if (AR_SREV_9100(ah)) {
1726 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1727 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1728 } else {
1729 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1730 if (tmpReg &
1731 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1732 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1733 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1734 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1735 } else {
1736 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1737 }
1738
1739 rst_flags = AR_RTC_RC_MAC_WARM;
1740 if (type == ATH9K_RESET_COLD)
1741 rst_flags |= AR_RTC_RC_MAC_COLD;
1742 }
1743
1744 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1745 udelay(50);
1746
1747 REG_WRITE(ah, AR_RTC_RC, 0);
1748 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1749 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1750 "RTC stuck in MAC reset\n");
1751 return false;
1752 }
1753
1754 if (!AR_SREV_9100(ah))
1755 REG_WRITE(ah, AR_RC, 0);
1756
1757 if (AR_SREV_9100(ah))
1758 udelay(50);
1759
1760 return true;
1761 }
1762
1763 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1764 {
1765 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1766 AR_RTC_FORCE_WAKE_ON_INT);
1767
1768 if (!AR_SREV_9100(ah))
1769 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1770
1771 REG_WRITE(ah, AR_RTC_RESET, 0);
1772 udelay(2);
1773
1774 if (!AR_SREV_9100(ah))
1775 REG_WRITE(ah, AR_RC, 0);
1776
1777 REG_WRITE(ah, AR_RTC_RESET, 1);
1778
1779 if (!ath9k_hw_wait(ah,
1780 AR_RTC_STATUS,
1781 AR_RTC_STATUS_M,
1782 AR_RTC_STATUS_ON,
1783 AH_WAIT_TIMEOUT)) {
1784 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1785 "RTC not waking up\n");
1786 return false;
1787 }
1788
1789 ath9k_hw_read_revisions(ah);
1790
1791 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1792 }
1793
1794 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1795 {
1796 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1797 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1798
1799 switch (type) {
1800 case ATH9K_RESET_POWER_ON:
1801 return ath9k_hw_set_reset_power_on(ah);
1802 case ATH9K_RESET_WARM:
1803 case ATH9K_RESET_COLD:
1804 return ath9k_hw_set_reset(ah, type);
1805 default:
1806 return false;
1807 }
1808 }
1809
1810 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan)
1811 {
1812 u32 phymode;
1813 u32 enableDacFifo = 0;
1814
1815 if (AR_SREV_9285_10_OR_LATER(ah))
1816 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1817 AR_PHY_FC_ENABLE_DAC_FIFO);
1818
1819 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1820 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
1821
1822 if (IS_CHAN_HT40(chan)) {
1823 phymode |= AR_PHY_FC_DYN2040_EN;
1824
1825 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1826 (chan->chanmode == CHANNEL_G_HT40PLUS))
1827 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1828
1829 }
1830 REG_WRITE(ah, AR_PHY_TURBO, phymode);
1831
1832 ath9k_hw_set11nmac2040(ah);
1833
1834 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1835 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1836 }
1837
1838 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1839 struct ath9k_channel *chan)
1840 {
1841 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
1842 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1843 return false;
1844 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1845 return false;
1846
1847 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1848 return false;
1849
1850 ah->chip_fullsleep = false;
1851 ath9k_hw_init_pll(ah, chan);
1852 ath9k_hw_set_rfmode(ah, chan);
1853
1854 return true;
1855 }
1856
1857 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1858 struct ath9k_channel *chan)
1859 {
1860 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1861 struct ath_common *common = ath9k_hw_common(ah);
1862 struct ieee80211_channel *channel = chan->chan;
1863 u32 synthDelay, qnum;
1864 int r;
1865
1866 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1867 if (ath9k_hw_numtxpending(ah, qnum)) {
1868 ath_print(common, ATH_DBG_QUEUE,
1869 "Transmit frames pending on "
1870 "queue %d\n", qnum);
1871 return false;
1872 }
1873 }
1874
1875 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1876 if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1877 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
1878 ath_print(common, ATH_DBG_FATAL,
1879 "Could not kill baseband RX\n");
1880 return false;
1881 }
1882
1883 ath9k_hw_set_regs(ah, chan);
1884
1885 r = ah->ath9k_hw_rf_set_freq(ah, chan);
1886 if (r) {
1887 ath_print(common, ATH_DBG_FATAL,
1888 "Failed to set channel\n");
1889 return false;
1890 }
1891
1892 ah->eep_ops->set_txpower(ah, chan,
1893 ath9k_regd_get_ctl(regulatory, chan),
1894 channel->max_antenna_gain * 2,
1895 channel->max_power * 2,
1896 min((u32) MAX_RATE_POWER,
1897 (u32) regulatory->power_limit));
1898
1899 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1900 if (IS_CHAN_B(chan))
1901 synthDelay = (4 * synthDelay) / 22;
1902 else
1903 synthDelay /= 10;
1904
1905 udelay(synthDelay + BASE_ACTIVATE_DELAY);
1906
1907 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1908
1909 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1910 ath9k_hw_set_delta_slope(ah, chan);
1911
1912 ah->ath9k_hw_spur_mitigate_freq(ah, chan);
1913
1914 if (!chan->oneTimeCalsDone)
1915 chan->oneTimeCalsDone = true;
1916
1917 return true;
1918 }
1919
1920 static void ath9k_enable_rfkill(struct ath_hw *ah)
1921 {
1922 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
1923 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
1924
1925 REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
1926 AR_GPIO_INPUT_MUX2_RFSILENT);
1927
1928 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
1929 REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
1930 }
1931
1932 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1933 bool bChannelChange)
1934 {
1935 struct ath_common *common = ath9k_hw_common(ah);
1936 u32 saveLedState;
1937 struct ath9k_channel *curchan = ah->curchan;
1938 u32 saveDefAntenna;
1939 u32 macStaId1;
1940 u64 tsf = 0;
1941 int i, rx_chainmask, r;
1942
1943 ah->txchainmask = common->tx_chainmask;
1944 ah->rxchainmask = common->rx_chainmask;
1945
1946 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1947 return -EIO;
1948
1949 if (curchan && !ah->chip_fullsleep)
1950 ath9k_hw_getnf(ah, curchan);
1951
1952 if (bChannelChange &&
1953 (ah->chip_fullsleep != true) &&
1954 (ah->curchan != NULL) &&
1955 (chan->channel != ah->curchan->channel) &&
1956 ((chan->channelFlags & CHANNEL_ALL) ==
1957 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
1958 !(AR_SREV_9280(ah) || IS_CHAN_A_5MHZ_SPACED(chan) ||
1959 IS_CHAN_A_5MHZ_SPACED(ah->curchan))) {
1960
1961 if (ath9k_hw_channel_change(ah, chan)) {
1962 ath9k_hw_loadnf(ah, ah->curchan);
1963 ath9k_hw_start_nfcal(ah);
1964 return 0;
1965 }
1966 }
1967
1968 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1969 if (saveDefAntenna == 0)
1970 saveDefAntenna = 1;
1971
1972 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1973
1974 /* For chips on which RTC reset is done, save TSF before it gets cleared */
1975 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1976 tsf = ath9k_hw_gettsf64(ah);
1977
1978 saveLedState = REG_READ(ah, AR_CFG_LED) &
1979 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1980 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1981
1982 ath9k_hw_mark_phy_inactive(ah);
1983
1984 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1985 REG_WRITE(ah,
1986 AR9271_RESET_POWER_DOWN_CONTROL,
1987 AR9271_RADIO_RF_RST);
1988 udelay(50);
1989 }
1990
1991 if (!ath9k_hw_chip_reset(ah, chan)) {
1992 ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n");
1993 return -EINVAL;
1994 }
1995
1996 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1997 ah->htc_reset_init = false;
1998 REG_WRITE(ah,
1999 AR9271_RESET_POWER_DOWN_CONTROL,
2000 AR9271_GATE_MAC_CTL);
2001 udelay(50);
2002 }
2003
2004 /* Restore TSF */
2005 if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
2006 ath9k_hw_settsf64(ah, tsf);
2007
2008 if (AR_SREV_9280_10_OR_LATER(ah))
2009 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
2010
2011 if (AR_SREV_9287_12_OR_LATER(ah)) {
2012 /* Enable ASYNC FIFO */
2013 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2014 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
2015 REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
2016 REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2017 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
2018 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2019 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
2020 }
2021 r = ath9k_hw_process_ini(ah, chan);
2022 if (r)
2023 return r;
2024
2025 /* Setup MFP options for CCMP */
2026 if (AR_SREV_9280_20_OR_LATER(ah)) {
2027 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
2028 * frames when constructing CCMP AAD. */
2029 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
2030 0xc7ff);
2031 ah->sw_mgmt_crypto = false;
2032 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
2033 /* Disable hardware crypto for management frames */
2034 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
2035 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
2036 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2037 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
2038 ah->sw_mgmt_crypto = true;
2039 } else
2040 ah->sw_mgmt_crypto = true;
2041
2042 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2043 ath9k_hw_set_delta_slope(ah, chan);
2044
2045 ah->ath9k_hw_spur_mitigate_freq(ah, chan);
2046 ah->eep_ops->set_board_values(ah, chan);
2047
2048 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
2049 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
2050 | macStaId1
2051 | AR_STA_ID1_RTS_USE_DEF
2052 | (ah->config.
2053 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2054 | ah->sta_id1_defaults);
2055 ath9k_hw_set_operating_mode(ah, ah->opmode);
2056
2057 ath_hw_setbssidmask(common);
2058
2059 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2060
2061 ath9k_hw_write_associd(ah);
2062
2063 REG_WRITE(ah, AR_ISR, ~0);
2064
2065 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2066
2067 r = ah->ath9k_hw_rf_set_freq(ah, chan);
2068 if (r)
2069 return r;
2070
2071 for (i = 0; i < AR_NUM_DCU; i++)
2072 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2073
2074 ah->intr_txqs = 0;
2075 for (i = 0; i < ah->caps.total_queues; i++)
2076 ath9k_hw_resettxqueue(ah, i);
2077
2078 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
2079 ath9k_hw_init_qos(ah);
2080
2081 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2082 ath9k_enable_rfkill(ah);
2083
2084 ath9k_hw_init_global_settings(ah);
2085
2086 if (AR_SREV_9287_12_OR_LATER(ah)) {
2087 REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
2088 AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
2089 REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
2090 AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
2091 REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
2092 AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
2093
2094 REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
2095 REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
2096
2097 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
2098 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
2099 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
2100 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
2101 }
2102 if (AR_SREV_9287_12_OR_LATER(ah)) {
2103 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2104 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
2105 }
2106
2107 REG_WRITE(ah, AR_STA_ID1,
2108 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2109
2110 ath9k_hw_set_dma(ah);
2111
2112 REG_WRITE(ah, AR_OBS, 8);
2113
2114 if (ah->config.rx_intr_mitigation) {
2115 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2116 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2117 }
2118
2119 ath9k_hw_init_bb(ah, chan);
2120
2121 if (!ath9k_hw_init_cal(ah, chan))
2122 return -EIO;
2123
2124 rx_chainmask = ah->rxchainmask;
2125 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2126 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2127 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2128 }
2129
2130 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2131
2132 /*
2133 * For big endian systems turn on swapping for descriptors
2134 */
2135 if (AR_SREV_9100(ah)) {
2136 u32 mask;
2137 mask = REG_READ(ah, AR_CFG);
2138 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2139 ath_print(common, ATH_DBG_RESET,
2140 "CFG Byte Swap Set 0x%x\n", mask);
2141 } else {
2142 mask =
2143 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2144 REG_WRITE(ah, AR_CFG, mask);
2145 ath_print(common, ATH_DBG_RESET,
2146 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
2147 }
2148 } else {
2149 /* Configure AR9271 target WLAN */
2150 if (AR_SREV_9271(ah))
2151 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
2152 #ifdef __BIG_ENDIAN
2153 else
2154 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2155 #endif
2156 }
2157
2158 if (ah->btcoex_hw.enabled)
2159 ath9k_hw_btcoex_enable(ah);
2160
2161 return 0;
2162 }
2163 EXPORT_SYMBOL(ath9k_hw_reset);
2164
2165 /************************/
2166 /* Key Cache Management */
2167 /************************/
2168
2169 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
2170 {
2171 u32 keyType;
2172
2173 if (entry >= ah->caps.keycache_size) {
2174 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2175 "keychache entry %u out of range\n", entry);
2176 return false;
2177 }
2178
2179 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
2180
2181 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2182 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2183 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2184 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2185 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2186 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2187 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2188 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
2189
2190 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2191 u16 micentry = entry + 64;
2192
2193 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2194 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2195 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2196 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2197
2198 }
2199
2200 return true;
2201 }
2202 EXPORT_SYMBOL(ath9k_hw_keyreset);
2203
2204 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
2205 {
2206 u32 macHi, macLo;
2207
2208 if (entry >= ah->caps.keycache_size) {
2209 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2210 "keychache entry %u out of range\n", entry);
2211 return false;
2212 }
2213
2214 if (mac != NULL) {
2215 macHi = (mac[5] << 8) | mac[4];
2216 macLo = (mac[3] << 24) |
2217 (mac[2] << 16) |
2218 (mac[1] << 8) |
2219 mac[0];
2220 macLo >>= 1;
2221 macLo |= (macHi & 1) << 31;
2222 macHi >>= 1;
2223 } else {
2224 macLo = macHi = 0;
2225 }
2226 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2227 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
2228
2229 return true;
2230 }
2231 EXPORT_SYMBOL(ath9k_hw_keysetmac);
2232
2233 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2234 const struct ath9k_keyval *k,
2235 const u8 *mac)
2236 {
2237 const struct ath9k_hw_capabilities *pCap = &ah->caps;
2238 struct ath_common *common = ath9k_hw_common(ah);
2239 u32 key0, key1, key2, key3, key4;
2240 u32 keyType;
2241
2242 if (entry >= pCap->keycache_size) {
2243 ath_print(common, ATH_DBG_FATAL,
2244 "keycache entry %u out of range\n", entry);
2245 return false;
2246 }
2247
2248 switch (k->kv_type) {
2249 case ATH9K_CIPHER_AES_OCB:
2250 keyType = AR_KEYTABLE_TYPE_AES;
2251 break;
2252 case ATH9K_CIPHER_AES_CCM:
2253 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2254 ath_print(common, ATH_DBG_ANY,
2255 "AES-CCM not supported by mac rev 0x%x\n",
2256 ah->hw_version.macRev);
2257 return false;
2258 }
2259 keyType = AR_KEYTABLE_TYPE_CCM;
2260 break;
2261 case ATH9K_CIPHER_TKIP:
2262 keyType = AR_KEYTABLE_TYPE_TKIP;
2263 if (ATH9K_IS_MIC_ENABLED(ah)
2264 && entry + 64 >= pCap->keycache_size) {
2265 ath_print(common, ATH_DBG_ANY,
2266 "entry %u inappropriate for TKIP\n", entry);
2267 return false;
2268 }
2269 break;
2270 case ATH9K_CIPHER_WEP:
2271 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
2272 ath_print(common, ATH_DBG_ANY,
2273 "WEP key length %u too small\n", k->kv_len);
2274 return false;
2275 }
2276 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
2277 keyType = AR_KEYTABLE_TYPE_40;
2278 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
2279 keyType = AR_KEYTABLE_TYPE_104;
2280 else
2281 keyType = AR_KEYTABLE_TYPE_128;
2282 break;
2283 case ATH9K_CIPHER_CLR:
2284 keyType = AR_KEYTABLE_TYPE_CLR;
2285 break;
2286 default:
2287 ath_print(common, ATH_DBG_FATAL,
2288 "cipher %u not supported\n", k->kv_type);
2289 return false;
2290 }
2291
2292 key0 = get_unaligned_le32(k->kv_val + 0);
2293 key1 = get_unaligned_le16(k->kv_val + 4);
2294 key2 = get_unaligned_le32(k->kv_val + 6);
2295 key3 = get_unaligned_le16(k->kv_val + 10);
2296 key4 = get_unaligned_le32(k->kv_val + 12);
2297 if (k->kv_len <= WLAN_KEY_LEN_WEP104)
2298 key4 &= 0xff;
2299
2300 /*
2301 * Note: Key cache registers access special memory area that requires
2302 * two 32-bit writes to actually update the values in the internal
2303 * memory. Consequently, the exact order and pairs used here must be
2304 * maintained.
2305 */
2306
2307 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2308 u16 micentry = entry + 64;
2309
2310 /*
2311 * Write inverted key[47:0] first to avoid Michael MIC errors
2312 * on frames that could be sent or received at the same time.
2313 * The correct key will be written in the end once everything
2314 * else is ready.
2315 */
2316 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2317 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
2318
2319 /* Write key[95:48] */
2320 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2321 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2322
2323 /* Write key[127:96] and key type */
2324 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2325 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2326
2327 /* Write MAC address for the entry */
2328 (void) ath9k_hw_keysetmac(ah, entry, mac);
2329
2330 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
2331 /*
2332 * TKIP uses two key cache entries:
2333 * Michael MIC TX/RX keys in the same key cache entry
2334 * (idx = main index + 64):
2335 * key0 [31:0] = RX key [31:0]
2336 * key1 [15:0] = TX key [31:16]
2337 * key1 [31:16] = reserved
2338 * key2 [31:0] = RX key [63:32]
2339 * key3 [15:0] = TX key [15:0]
2340 * key3 [31:16] = reserved
2341 * key4 [31:0] = TX key [63:32]
2342 */
2343 u32 mic0, mic1, mic2, mic3, mic4;
2344
2345 mic0 = get_unaligned_le32(k->kv_mic + 0);
2346 mic2 = get_unaligned_le32(k->kv_mic + 4);
2347 mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2348 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2349 mic4 = get_unaligned_le32(k->kv_txmic + 4);
2350
2351 /* Write RX[31:0] and TX[31:16] */
2352 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2353 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2354
2355 /* Write RX[63:32] and TX[15:0] */
2356 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2357 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2358
2359 /* Write TX[63:32] and keyType(reserved) */
2360 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2361 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2362 AR_KEYTABLE_TYPE_CLR);
2363
2364 } else {
2365 /*
2366 * TKIP uses four key cache entries (two for group
2367 * keys):
2368 * Michael MIC TX/RX keys are in different key cache
2369 * entries (idx = main index + 64 for TX and
2370 * main index + 32 + 96 for RX):
2371 * key0 [31:0] = TX/RX MIC key [31:0]
2372 * key1 [31:0] = reserved
2373 * key2 [31:0] = TX/RX MIC key [63:32]
2374 * key3 [31:0] = reserved
2375 * key4 [31:0] = reserved
2376 *
2377 * Upper layer code will call this function separately
2378 * for TX and RX keys when these registers offsets are
2379 * used.
2380 */
2381 u32 mic0, mic2;
2382
2383 mic0 = get_unaligned_le32(k->kv_mic + 0);
2384 mic2 = get_unaligned_le32(k->kv_mic + 4);
2385
2386 /* Write MIC key[31:0] */
2387 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2388 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2389
2390 /* Write MIC key[63:32] */
2391 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2392 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2393
2394 /* Write TX[63:32] and keyType(reserved) */
2395 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2396 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2397 AR_KEYTABLE_TYPE_CLR);
2398 }
2399
2400 /* MAC address registers are reserved for the MIC entry */
2401 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2402 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2403
2404 /*
2405 * Write the correct (un-inverted) key[47:0] last to enable
2406 * TKIP now that all other registers are set with correct
2407 * values.
2408 */
2409 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2410 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2411 } else {
2412 /* Write key[47:0] */
2413 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2414 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2415
2416 /* Write key[95:48] */
2417 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2418 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2419
2420 /* Write key[127:96] and key type */
2421 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2422 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2423
2424 /* Write MAC address for the entry */
2425 (void) ath9k_hw_keysetmac(ah, entry, mac);
2426 }
2427
2428 return true;
2429 }
2430 EXPORT_SYMBOL(ath9k_hw_set_keycache_entry);
2431
2432 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
2433 {
2434 if (entry < ah->caps.keycache_size) {
2435 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2436 if (val & AR_KEYTABLE_VALID)
2437 return true;
2438 }
2439 return false;
2440 }
2441 EXPORT_SYMBOL(ath9k_hw_keyisvalid);
2442
2443 /******************************/
2444 /* Power Management (Chipset) */
2445 /******************************/
2446
2447 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
2448 {
2449 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2450 if (setChip) {
2451 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2452 AR_RTC_FORCE_WAKE_EN);
2453 if (!AR_SREV_9100(ah))
2454 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2455
2456 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah))
2457 REG_CLR_BIT(ah, (AR_RTC_RESET),
2458 AR_RTC_RESET_EN);
2459 }
2460 }
2461
2462 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
2463 {
2464 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2465 if (setChip) {
2466 struct ath9k_hw_capabilities *pCap = &ah->caps;
2467
2468 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2469 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2470 AR_RTC_FORCE_WAKE_ON_INT);
2471 } else {
2472 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2473 AR_RTC_FORCE_WAKE_EN);
2474 }
2475 }
2476 }
2477
2478 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2479 {
2480 u32 val;
2481 int i;
2482
2483 if (setChip) {
2484 if ((REG_READ(ah, AR_RTC_STATUS) &
2485 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2486 if (ath9k_hw_set_reset_reg(ah,
2487 ATH9K_RESET_POWER_ON) != true) {
2488 return false;
2489 }
2490 ath9k_hw_init_pll(ah, NULL);
2491 }
2492 if (AR_SREV_9100(ah))
2493 REG_SET_BIT(ah, AR_RTC_RESET,
2494 AR_RTC_RESET_EN);
2495
2496 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2497 AR_RTC_FORCE_WAKE_EN);
2498 udelay(50);
2499
2500 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2501 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2502 if (val == AR_RTC_STATUS_ON)
2503 break;
2504 udelay(50);
2505 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2506 AR_RTC_FORCE_WAKE_EN);
2507 }
2508 if (i == 0) {
2509 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2510 "Failed to wakeup in %uus\n",
2511 POWER_UP_TIME / 20);
2512 return false;
2513 }
2514 }
2515
2516 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2517
2518 return true;
2519 }
2520
2521 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2522 {
2523 struct ath_common *common = ath9k_hw_common(ah);
2524 int status = true, setChip = true;
2525 static const char *modes[] = {
2526 "AWAKE",
2527 "FULL-SLEEP",
2528 "NETWORK SLEEP",
2529 "UNDEFINED"
2530 };
2531
2532 if (ah->power_mode == mode)
2533 return status;
2534
2535 ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
2536 modes[ah->power_mode], modes[mode]);
2537
2538 switch (mode) {
2539 case ATH9K_PM_AWAKE:
2540 status = ath9k_hw_set_power_awake(ah, setChip);
2541 break;
2542 case ATH9K_PM_FULL_SLEEP:
2543 ath9k_set_power_sleep(ah, setChip);
2544 ah->chip_fullsleep = true;
2545 break;
2546 case ATH9K_PM_NETWORK_SLEEP:
2547 ath9k_set_power_network_sleep(ah, setChip);
2548 break;
2549 default:
2550 ath_print(common, ATH_DBG_FATAL,
2551 "Unknown power mode %u\n", mode);
2552 return false;
2553 }
2554 ah->power_mode = mode;
2555
2556 return status;
2557 }
2558 EXPORT_SYMBOL(ath9k_hw_setpower);
2559
2560 /*
2561 * Helper for ASPM support.
2562 *
2563 * Disable PLL when in L0s as well as receiver clock when in L1.
2564 * This power saving option must be enabled through the SerDes.
2565 *
2566 * Programming the SerDes must go through the same 288 bit serial shift
2567 * register as the other analog registers. Hence the 9 writes.
2568 */
2569 void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off)
2570 {
2571 u8 i;
2572 u32 val;
2573
2574 if (ah->is_pciexpress != true)
2575 return;
2576
2577 /* Do not touch SerDes registers */
2578 if (ah->config.pcie_powersave_enable == 2)
2579 return;
2580
2581 /* Nothing to do on restore for 11N */
2582 if (!restore) {
2583 if (AR_SREV_9280_20_OR_LATER(ah)) {
2584 /*
2585 * AR9280 2.0 or later chips use SerDes values from the
2586 * initvals.h initialized depending on chipset during
2587 * ath9k_hw_init()
2588 */
2589 for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
2590 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
2591 INI_RA(&ah->iniPcieSerdes, i, 1));
2592 }
2593 } else if (AR_SREV_9280(ah) &&
2594 (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
2595 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2596 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2597
2598 /* RX shut off when elecidle is asserted */
2599 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2600 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2601 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2602
2603 /* Shut off CLKREQ active in L1 */
2604 if (ah->config.pcie_clock_req)
2605 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2606 else
2607 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
2608
2609 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2610 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2611 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
2612
2613 /* Load the new settings */
2614 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2615
2616 } else {
2617 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2618 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2619
2620 /* RX shut off when elecidle is asserted */
2621 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2622 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2623 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
2624
2625 /*
2626 * Ignore ah->ah_config.pcie_clock_req setting for
2627 * pre-AR9280 11n
2628 */
2629 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2630
2631 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2632 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2633 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
2634
2635 /* Load the new settings */
2636 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2637 }
2638
2639 udelay(1000);
2640
2641 /* set bit 19 to allow forcing of pcie core into L1 state */
2642 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
2643
2644 /* Several PCIe massages to ensure proper behaviour */
2645 if (ah->config.pcie_waen) {
2646 val = ah->config.pcie_waen;
2647 if (!power_off)
2648 val &= (~AR_WA_D3_L1_DISABLE);
2649 } else {
2650 if (AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
2651 AR_SREV_9287(ah)) {
2652 val = AR9285_WA_DEFAULT;
2653 if (!power_off)
2654 val &= (~AR_WA_D3_L1_DISABLE);
2655 } else if (AR_SREV_9280(ah)) {
2656 /*
2657 * On AR9280 chips bit 22 of 0x4004 needs to be
2658 * set otherwise card may disappear.
2659 */
2660 val = AR9280_WA_DEFAULT;
2661 if (!power_off)
2662 val &= (~AR_WA_D3_L1_DISABLE);
2663 } else
2664 val = AR_WA_DEFAULT;
2665 }
2666
2667 REG_WRITE(ah, AR_WA, val);
2668 }
2669
2670 if (power_off) {
2671 /*
2672 * Set PCIe workaround bits
2673 * bit 14 in WA register (disable L1) should only
2674 * be set when device enters D3 and be cleared
2675 * when device comes back to D0.
2676 */
2677 if (ah->config.pcie_waen) {
2678 if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE)
2679 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
2680 } else {
2681 if (((AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
2682 AR_SREV_9287(ah)) &&
2683 (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) ||
2684 (AR_SREV_9280(ah) &&
2685 (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) {
2686 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
2687 }
2688 }
2689 }
2690 }
2691 EXPORT_SYMBOL(ath9k_hw_configpcipowersave);
2692
2693 /**********************/
2694 /* Interrupt Handling */
2695 /**********************/
2696
2697 bool ath9k_hw_intrpend(struct ath_hw *ah)
2698 {
2699 u32 host_isr;
2700
2701 if (AR_SREV_9100(ah))
2702 return true;
2703
2704 host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
2705 if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
2706 return true;
2707
2708 host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
2709 if ((host_isr & AR_INTR_SYNC_DEFAULT)
2710 && (host_isr != AR_INTR_SPURIOUS))
2711 return true;
2712
2713 return false;
2714 }
2715 EXPORT_SYMBOL(ath9k_hw_intrpend);
2716
2717 bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
2718 {
2719 u32 isr = 0;
2720 u32 mask2 = 0;
2721 struct ath9k_hw_capabilities *pCap = &ah->caps;
2722 u32 sync_cause = 0;
2723 bool fatal_int = false;
2724 struct ath_common *common = ath9k_hw_common(ah);
2725
2726 if (!AR_SREV_9100(ah)) {
2727 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
2728 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
2729 == AR_RTC_STATUS_ON) {
2730 isr = REG_READ(ah, AR_ISR);
2731 }
2732 }
2733
2734 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
2735 AR_INTR_SYNC_DEFAULT;
2736
2737 *masked = 0;
2738
2739 if (!isr && !sync_cause)
2740 return false;
2741 } else {
2742 *masked = 0;
2743 isr = REG_READ(ah, AR_ISR);
2744 }
2745
2746 if (isr) {
2747 if (isr & AR_ISR_BCNMISC) {
2748 u32 isr2;
2749 isr2 = REG_READ(ah, AR_ISR_S2);
2750 if (isr2 & AR_ISR_S2_TIM)
2751 mask2 |= ATH9K_INT_TIM;
2752 if (isr2 & AR_ISR_S2_DTIM)
2753 mask2 |= ATH9K_INT_DTIM;
2754 if (isr2 & AR_ISR_S2_DTIMSYNC)
2755 mask2 |= ATH9K_INT_DTIMSYNC;
2756 if (isr2 & (AR_ISR_S2_CABEND))
2757 mask2 |= ATH9K_INT_CABEND;
2758 if (isr2 & AR_ISR_S2_GTT)
2759 mask2 |= ATH9K_INT_GTT;
2760 if (isr2 & AR_ISR_S2_CST)
2761 mask2 |= ATH9K_INT_CST;
2762 if (isr2 & AR_ISR_S2_TSFOOR)
2763 mask2 |= ATH9K_INT_TSFOOR;
2764 }
2765
2766 isr = REG_READ(ah, AR_ISR_RAC);
2767 if (isr == 0xffffffff) {
2768 *masked = 0;
2769 return false;
2770 }
2771
2772 *masked = isr & ATH9K_INT_COMMON;
2773
2774 if (ah->config.rx_intr_mitigation) {
2775 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
2776 *masked |= ATH9K_INT_RX;
2777 }
2778
2779 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
2780 *masked |= ATH9K_INT_RX;
2781 if (isr &
2782 (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
2783 AR_ISR_TXEOL)) {
2784 u32 s0_s, s1_s;
2785
2786 *masked |= ATH9K_INT_TX;
2787
2788 s0_s = REG_READ(ah, AR_ISR_S0_S);
2789 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
2790 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
2791
2792 s1_s = REG_READ(ah, AR_ISR_S1_S);
2793 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
2794 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
2795 }
2796
2797 if (isr & AR_ISR_RXORN) {
2798 ath_print(common, ATH_DBG_INTERRUPT,
2799 "receive FIFO overrun interrupt\n");
2800 }
2801
2802 if (!AR_SREV_9100(ah)) {
2803 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2804 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
2805 if (isr5 & AR_ISR_S5_TIM_TIMER)
2806 *masked |= ATH9K_INT_TIM_TIMER;
2807 }
2808 }
2809
2810 *masked |= mask2;
2811 }
2812
2813 if (AR_SREV_9100(ah))
2814 return true;
2815
2816 if (isr & AR_ISR_GENTMR) {
2817 u32 s5_s;
2818
2819 s5_s = REG_READ(ah, AR_ISR_S5_S);
2820 if (isr & AR_ISR_GENTMR) {
2821 ah->intr_gen_timer_trigger =
2822 MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
2823
2824 ah->intr_gen_timer_thresh =
2825 MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);
2826
2827 if (ah->intr_gen_timer_trigger)
2828 *masked |= ATH9K_INT_GENTIMER;
2829
2830 }
2831 }
2832
2833 if (sync_cause) {
2834 fatal_int =
2835 (sync_cause &
2836 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
2837 ? true : false;
2838
2839 if (fatal_int) {
2840 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
2841 ath_print(common, ATH_DBG_ANY,
2842 "received PCI FATAL interrupt\n");
2843 }
2844 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
2845 ath_print(common, ATH_DBG_ANY,
2846 "received PCI PERR interrupt\n");
2847 }
2848 *masked |= ATH9K_INT_FATAL;
2849 }
2850 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
2851 ath_print(common, ATH_DBG_INTERRUPT,
2852 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
2853 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
2854 REG_WRITE(ah, AR_RC, 0);
2855 *masked |= ATH9K_INT_FATAL;
2856 }
2857 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
2858 ath_print(common, ATH_DBG_INTERRUPT,
2859 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
2860 }
2861
2862 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
2863 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
2864 }
2865
2866 return true;
2867 }
2868 EXPORT_SYMBOL(ath9k_hw_getisr);
2869
2870 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
2871 {
2872 u32 omask = ah->mask_reg;
2873 u32 mask, mask2;
2874 struct ath9k_hw_capabilities *pCap = &ah->caps;
2875 struct ath_common *common = ath9k_hw_common(ah);
2876
2877 ath_print(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
2878
2879 if (omask & ATH9K_INT_GLOBAL) {
2880 ath_print(common, ATH_DBG_INTERRUPT, "disable IER\n");
2881 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
2882 (void) REG_READ(ah, AR_IER);
2883 if (!AR_SREV_9100(ah)) {
2884 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
2885 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
2886
2887 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
2888 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
2889 }
2890 }
2891
2892 mask = ints & ATH9K_INT_COMMON;
2893 mask2 = 0;
2894
2895 if (ints & ATH9K_INT_TX) {
2896 if (ah->txok_interrupt_mask)
2897 mask |= AR_IMR_TXOK;
2898 if (ah->txdesc_interrupt_mask)
2899 mask |= AR_IMR_TXDESC;
2900 if (ah->txerr_interrupt_mask)
2901 mask |= AR_IMR_TXERR;
2902 if (ah->txeol_interrupt_mask)
2903 mask |= AR_IMR_TXEOL;
2904 }
2905 if (ints & ATH9K_INT_RX) {
2906 mask |= AR_IMR_RXERR;
2907 if (ah->config.rx_intr_mitigation)
2908 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
2909 else
2910 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
2911 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
2912 mask |= AR_IMR_GENTMR;
2913 }
2914
2915 if (ints & (ATH9K_INT_BMISC)) {
2916 mask |= AR_IMR_BCNMISC;
2917 if (ints & ATH9K_INT_TIM)
2918 mask2 |= AR_IMR_S2_TIM;
2919 if (ints & ATH9K_INT_DTIM)
2920 mask2 |= AR_IMR_S2_DTIM;
2921 if (ints & ATH9K_INT_DTIMSYNC)
2922 mask2 |= AR_IMR_S2_DTIMSYNC;
2923 if (ints & ATH9K_INT_CABEND)
2924 mask2 |= AR_IMR_S2_CABEND;
2925 if (ints & ATH9K_INT_TSFOOR)
2926 mask2 |= AR_IMR_S2_TSFOOR;
2927 }
2928
2929 if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
2930 mask |= AR_IMR_BCNMISC;
2931 if (ints & ATH9K_INT_GTT)
2932 mask2 |= AR_IMR_S2_GTT;
2933 if (ints & ATH9K_INT_CST)
2934 mask2 |= AR_IMR_S2_CST;
2935 }
2936
2937 ath_print(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
2938 REG_WRITE(ah, AR_IMR, mask);
2939 ah->imrs2_reg &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC |
2940 AR_IMR_S2_CABEND | AR_IMR_S2_CABTO |
2941 AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST);
2942 ah->imrs2_reg |= mask2;
2943 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
2944 ah->mask_reg = ints;
2945
2946 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2947 if (ints & ATH9K_INT_TIM_TIMER)
2948 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
2949 else
2950 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
2951 }
2952
2953 if (ints & ATH9K_INT_GLOBAL) {
2954 ath_print(common, ATH_DBG_INTERRUPT, "enable IER\n");
2955 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
2956 if (!AR_SREV_9100(ah)) {
2957 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
2958 AR_INTR_MAC_IRQ);
2959 REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
2960
2961
2962 REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
2963 AR_INTR_SYNC_DEFAULT);
2964 REG_WRITE(ah, AR_INTR_SYNC_MASK,
2965 AR_INTR_SYNC_DEFAULT);
2966 }
2967 ath_print(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
2968 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
2969 }
2970
2971 return omask;
2972 }
2973 EXPORT_SYMBOL(ath9k_hw_set_interrupts);
2974
2975 /*******************/
2976 /* Beacon Handling */
2977 /*******************/
2978
2979 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
2980 {
2981 int flags = 0;
2982
2983 ah->beacon_interval = beacon_period;
2984
2985 switch (ah->opmode) {
2986 case NL80211_IFTYPE_STATION:
2987 case NL80211_IFTYPE_MONITOR:
2988 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
2989 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
2990 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
2991 flags |= AR_TBTT_TIMER_EN;
2992 break;
2993 case NL80211_IFTYPE_ADHOC:
2994 case NL80211_IFTYPE_MESH_POINT:
2995 REG_SET_BIT(ah, AR_TXCFG,
2996 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
2997 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
2998 TU_TO_USEC(next_beacon +
2999 (ah->atim_window ? ah->
3000 atim_window : 1)));
3001 flags |= AR_NDP_TIMER_EN;
3002 case NL80211_IFTYPE_AP:
3003 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3004 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
3005 TU_TO_USEC(next_beacon -
3006 ah->config.
3007 dma_beacon_response_time));
3008 REG_WRITE(ah, AR_NEXT_SWBA,
3009 TU_TO_USEC(next_beacon -
3010 ah->config.
3011 sw_beacon_response_time));
3012 flags |=
3013 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
3014 break;
3015 default:
3016 ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
3017 "%s: unsupported opmode: %d\n",
3018 __func__, ah->opmode);
3019 return;
3020 break;
3021 }
3022
3023 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3024 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3025 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
3026 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
3027
3028 beacon_period &= ~ATH9K_BEACON_ENA;
3029 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
3030 ath9k_hw_reset_tsf(ah);
3031 }
3032
3033 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3034 }
3035 EXPORT_SYMBOL(ath9k_hw_beaconinit);
3036
3037 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
3038 const struct ath9k_beacon_state *bs)
3039 {
3040 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
3041 struct ath9k_hw_capabilities *pCap = &ah->caps;
3042 struct ath_common *common = ath9k_hw_common(ah);
3043
3044 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3045
3046 REG_WRITE(ah, AR_BEACON_PERIOD,
3047 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3048 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3049 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3050
3051 REG_RMW_FIELD(ah, AR_RSSI_THR,
3052 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3053
3054 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3055
3056 if (bs->bs_sleepduration > beaconintval)
3057 beaconintval = bs->bs_sleepduration;
3058
3059 dtimperiod = bs->bs_dtimperiod;
3060 if (bs->bs_sleepduration > dtimperiod)
3061 dtimperiod = bs->bs_sleepduration;
3062
3063 if (beaconintval == dtimperiod)
3064 nextTbtt = bs->bs_nextdtim;
3065 else
3066 nextTbtt = bs->bs_nexttbtt;
3067
3068 ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3069 ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3070 ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3071 ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
3072
3073 REG_WRITE(ah, AR_NEXT_DTIM,
3074 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3075 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
3076
3077 REG_WRITE(ah, AR_SLEEP1,
3078 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3079 | AR_SLEEP1_ASSUME_DTIM);
3080
3081 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3082 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3083 else
3084 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
3085
3086 REG_WRITE(ah, AR_SLEEP2,
3087 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
3088
3089 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3090 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
3091
3092 REG_SET_BIT(ah, AR_TIMER_MODE,
3093 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3094 AR_DTIM_TIMER_EN);
3095
3096 /* TSF Out of Range Threshold */
3097 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
3098 }
3099 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
3100
3101 /*******************/
3102 /* HW Capabilities */
3103 /*******************/
3104
3105 int ath9k_hw_fill_cap_info(struct ath_hw *ah)
3106 {
3107 struct ath9k_hw_capabilities *pCap = &ah->caps;
3108 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3109 struct ath_common *common = ath9k_hw_common(ah);
3110 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
3111
3112 u16 capField = 0, eeval;
3113
3114 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
3115 regulatory->current_rd = eeval;
3116
3117 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
3118 if (AR_SREV_9285_10_OR_LATER(ah))
3119 eeval |= AR9285_RDEXT_DEFAULT;
3120 regulatory->current_rd_ext = eeval;
3121
3122 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
3123
3124 if (ah->opmode != NL80211_IFTYPE_AP &&
3125 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3126 if (regulatory->current_rd == 0x64 ||
3127 regulatory->current_rd == 0x65)
3128 regulatory->current_rd += 5;
3129 else if (regulatory->current_rd == 0x41)
3130 regulatory->current_rd = 0x43;
3131 ath_print(common, ATH_DBG_REGULATORY,
3132 "regdomain mapped to 0x%x\n", regulatory->current_rd);
3133 }
3134
3135 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
3136 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
3137 ath_print(common, ATH_DBG_FATAL,
3138 "no band has been marked as supported in EEPROM.\n");
3139 return -EINVAL;
3140 }
3141
3142 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
3143
3144 if (eeval & AR5416_OPFLAGS_11A) {
3145 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
3146 if (ah->config.ht_enable) {
3147 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3148 set_bit(ATH9K_MODE_11NA_HT20,
3149 pCap->wireless_modes);
3150 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3151 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3152 pCap->wireless_modes);
3153 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3154 pCap->wireless_modes);
3155 }
3156 }
3157 }
3158
3159 if (eeval & AR5416_OPFLAGS_11G) {
3160 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
3161 if (ah->config.ht_enable) {
3162 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3163 set_bit(ATH9K_MODE_11NG_HT20,
3164 pCap->wireless_modes);
3165 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3166 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3167 pCap->wireless_modes);
3168 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3169 pCap->wireless_modes);
3170 }
3171 }
3172 }
3173
3174 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
3175 /*
3176 * For AR9271 we will temporarilly uses the rx chainmax as read from
3177 * the EEPROM.
3178 */
3179 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
3180 !(eeval & AR5416_OPFLAGS_11A) &&
3181 !(AR_SREV_9271(ah)))
3182 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
3183 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
3184 else
3185 /* Use rx_chainmask from EEPROM. */
3186 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
3187
3188 if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
3189 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
3190
3191 pCap->low_2ghz_chan = 2312;
3192 pCap->high_2ghz_chan = 2732;
3193
3194 pCap->low_5ghz_chan = 4920;
3195 pCap->high_5ghz_chan = 6100;
3196
3197 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3198 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3199 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3200
3201 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3202 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3203 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3204
3205 if (ah->config.ht_enable)
3206 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3207 else
3208 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3209
3210 pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3211 pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3212 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3213 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3214
3215 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3216 pCap->total_queues =
3217 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3218 else
3219 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3220
3221 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3222 pCap->keycache_size =
3223 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3224 else
3225 pCap->keycache_size = AR_KEYTABLE_SIZE;
3226
3227 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3228
3229 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
3230 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1;
3231 else
3232 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3233
3234 if (AR_SREV_9271(ah))
3235 pCap->num_gpio_pins = AR9271_NUM_GPIO;
3236 else if (AR_SREV_9285_10_OR_LATER(ah))
3237 pCap->num_gpio_pins = AR9285_NUM_GPIO;
3238 else if (AR_SREV_9280_10_OR_LATER(ah))
3239 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3240 else
3241 pCap->num_gpio_pins = AR_NUM_GPIO;
3242
3243 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3244 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3245 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3246 } else {
3247 pCap->rts_aggr_limit = (8 * 1024);
3248 }
3249
3250 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3251
3252 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3253 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
3254 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
3255 ah->rfkill_gpio =
3256 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
3257 ah->rfkill_polarity =
3258 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
3259
3260 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3261 }
3262 #endif
3263
3264 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3265
3266 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
3267 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3268 else
3269 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3270
3271 if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
3272 pCap->reg_cap =
3273 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3274 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3275 AR_EEPROM_EEREGCAP_EN_KK_U2 |
3276 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3277 } else {
3278 pCap->reg_cap =
3279 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3280 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3281 }
3282
3283 /* Advertise midband for AR5416 with FCC midband set in eeprom */
3284 if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
3285 AR_SREV_5416(ah))
3286 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3287
3288 pCap->num_antcfg_5ghz =
3289 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
3290 pCap->num_antcfg_2ghz =
3291 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
3292
3293 if (AR_SREV_9280_10_OR_LATER(ah) &&
3294 ath9k_hw_btcoex_supported(ah)) {
3295 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
3296 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
3297
3298 if (AR_SREV_9285(ah)) {
3299 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
3300 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
3301 } else {
3302 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
3303 }
3304 } else {
3305 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
3306 }
3307
3308 return 0;
3309 }
3310
3311 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3312 u32 capability, u32 *result)
3313 {
3314 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3315 switch (type) {
3316 case ATH9K_CAP_CIPHER:
3317 switch (capability) {
3318 case ATH9K_CIPHER_AES_CCM:
3319 case ATH9K_CIPHER_AES_OCB:
3320 case ATH9K_CIPHER_TKIP:
3321 case ATH9K_CIPHER_WEP:
3322 case ATH9K_CIPHER_MIC:
3323 case ATH9K_CIPHER_CLR:
3324 return true;
3325 default:
3326 return false;
3327 }
3328 case ATH9K_CAP_TKIP_MIC:
3329 switch (capability) {
3330 case 0:
3331 return true;
3332 case 1:
3333 return (ah->sta_id1_defaults &
3334 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3335 false;
3336 }
3337 case ATH9K_CAP_TKIP_SPLIT:
3338 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
3339 false : true;
3340 case ATH9K_CAP_DIVERSITY:
3341 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3342 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3343 true : false;
3344 case ATH9K_CAP_MCAST_KEYSRCH:
3345 switch (capability) {
3346 case 0:
3347 return true;
3348 case 1:
3349 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3350 return false;
3351 } else {
3352 return (ah->sta_id1_defaults &
3353 AR_STA_ID1_MCAST_KSRCH) ? true :
3354 false;
3355 }
3356 }
3357 return false;
3358 case ATH9K_CAP_TXPOW:
3359 switch (capability) {
3360 case 0:
3361 return 0;
3362 case 1:
3363 *result = regulatory->power_limit;
3364 return 0;
3365 case 2:
3366 *result = regulatory->max_power_level;
3367 return 0;
3368 case 3:
3369 *result = regulatory->tp_scale;
3370 return 0;
3371 }
3372 return false;
3373 case ATH9K_CAP_DS:
3374 return (AR_SREV_9280_20_OR_LATER(ah) &&
3375 (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
3376 ? false : true;
3377 default:
3378 return false;
3379 }
3380 }
3381 EXPORT_SYMBOL(ath9k_hw_getcapability);
3382
3383 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3384 u32 capability, u32 setting, int *status)
3385 {
3386 u32 v;
3387
3388 switch (type) {
3389 case ATH9K_CAP_TKIP_MIC:
3390 if (setting)
3391 ah->sta_id1_defaults |=
3392 AR_STA_ID1_CRPT_MIC_ENABLE;
3393 else
3394 ah->sta_id1_defaults &=
3395 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3396 return true;
3397 case ATH9K_CAP_DIVERSITY:
3398 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3399 if (setting)
3400 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3401 else
3402 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3403 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3404 return true;
3405 case ATH9K_CAP_MCAST_KEYSRCH:
3406 if (setting)
3407 ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
3408 else
3409 ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
3410 return true;
3411 default:
3412 return false;
3413 }
3414 }
3415 EXPORT_SYMBOL(ath9k_hw_setcapability);
3416
3417 /****************************/
3418 /* GPIO / RFKILL / Antennae */
3419 /****************************/
3420
3421 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
3422 u32 gpio, u32 type)
3423 {
3424 int addr;
3425 u32 gpio_shift, tmp;
3426
3427 if (gpio > 11)
3428 addr = AR_GPIO_OUTPUT_MUX3;
3429 else if (gpio > 5)
3430 addr = AR_GPIO_OUTPUT_MUX2;
3431 else
3432 addr = AR_GPIO_OUTPUT_MUX1;
3433
3434 gpio_shift = (gpio % 6) * 5;
3435
3436 if (AR_SREV_9280_20_OR_LATER(ah)
3437 || (addr != AR_GPIO_OUTPUT_MUX1)) {
3438 REG_RMW(ah, addr, (type << gpio_shift),
3439 (0x1f << gpio_shift));
3440 } else {
3441 tmp = REG_READ(ah, addr);
3442 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3443 tmp &= ~(0x1f << gpio_shift);
3444 tmp |= (type << gpio_shift);
3445 REG_WRITE(ah, addr, tmp);
3446 }
3447 }
3448
3449 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
3450 {
3451 u32 gpio_shift;
3452
3453 BUG_ON(gpio >= ah->caps.num_gpio_pins);
3454
3455 gpio_shift = gpio << 1;
3456
3457 REG_RMW(ah,
3458 AR_GPIO_OE_OUT,
3459 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3460 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3461 }
3462 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
3463
3464 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
3465 {
3466 #define MS_REG_READ(x, y) \
3467 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3468
3469 if (gpio >= ah->caps.num_gpio_pins)
3470 return 0xffffffff;
3471
3472 if (AR_SREV_9271(ah))
3473 return MS_REG_READ(AR9271, gpio) != 0;
3474 else if (AR_SREV_9287_10_OR_LATER(ah))
3475 return MS_REG_READ(AR9287, gpio) != 0;
3476 else if (AR_SREV_9285_10_OR_LATER(ah))
3477 return MS_REG_READ(AR9285, gpio) != 0;
3478 else if (AR_SREV_9280_10_OR_LATER(ah))
3479 return MS_REG_READ(AR928X, gpio) != 0;
3480 else
3481 return MS_REG_READ(AR, gpio) != 0;
3482 }
3483 EXPORT_SYMBOL(ath9k_hw_gpio_get);
3484
3485 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
3486 u32 ah_signal_type)
3487 {
3488 u32 gpio_shift;
3489
3490 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
3491
3492 gpio_shift = 2 * gpio;
3493
3494 REG_RMW(ah,
3495 AR_GPIO_OE_OUT,
3496 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3497 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3498 }
3499 EXPORT_SYMBOL(ath9k_hw_cfg_output);
3500
3501 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
3502 {
3503 if (AR_SREV_9271(ah))
3504 val = ~val;
3505
3506 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3507 AR_GPIO_BIT(gpio));
3508 }
3509 EXPORT_SYMBOL(ath9k_hw_set_gpio);
3510
3511 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
3512 {
3513 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3514 }
3515 EXPORT_SYMBOL(ath9k_hw_getdefantenna);
3516
3517 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
3518 {
3519 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3520 }
3521 EXPORT_SYMBOL(ath9k_hw_setantenna);
3522
3523 /*********************/
3524 /* General Operation */
3525 /*********************/
3526
3527 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
3528 {
3529 u32 bits = REG_READ(ah, AR_RX_FILTER);
3530 u32 phybits = REG_READ(ah, AR_PHY_ERR);
3531
3532 if (phybits & AR_PHY_ERR_RADAR)
3533 bits |= ATH9K_RX_FILTER_PHYRADAR;
3534 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3535 bits |= ATH9K_RX_FILTER_PHYERR;
3536
3537 return bits;
3538 }
3539 EXPORT_SYMBOL(ath9k_hw_getrxfilter);
3540
3541 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
3542 {
3543 u32 phybits;
3544
3545 REG_WRITE(ah, AR_RX_FILTER, bits);
3546
3547 phybits = 0;
3548 if (bits & ATH9K_RX_FILTER_PHYRADAR)
3549 phybits |= AR_PHY_ERR_RADAR;
3550 if (bits & ATH9K_RX_FILTER_PHYERR)
3551 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3552 REG_WRITE(ah, AR_PHY_ERR, phybits);
3553
3554 if (phybits)
3555 REG_WRITE(ah, AR_RXCFG,
3556 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3557 else
3558 REG_WRITE(ah, AR_RXCFG,
3559 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3560 }
3561 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
3562
3563 bool ath9k_hw_phy_disable(struct ath_hw *ah)
3564 {
3565 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
3566 return false;
3567
3568 ath9k_hw_init_pll(ah, NULL);
3569 return true;
3570 }
3571 EXPORT_SYMBOL(ath9k_hw_phy_disable);
3572
3573 bool ath9k_hw_disable(struct ath_hw *ah)
3574 {
3575 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3576 return false;
3577
3578 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
3579 return false;
3580
3581 ath9k_hw_init_pll(ah, NULL);
3582 return true;
3583 }
3584 EXPORT_SYMBOL(ath9k_hw_disable);
3585
3586 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
3587 {
3588 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3589 struct ath9k_channel *chan = ah->curchan;
3590 struct ieee80211_channel *channel = chan->chan;
3591
3592 regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
3593
3594 ah->eep_ops->set_txpower(ah, chan,
3595 ath9k_regd_get_ctl(regulatory, chan),
3596 channel->max_antenna_gain * 2,
3597 channel->max_power * 2,
3598 min((u32) MAX_RATE_POWER,
3599 (u32) regulatory->power_limit));
3600 }
3601 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
3602
3603 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
3604 {
3605 memcpy(ath9k_hw_common(ah)->macaddr, mac, ETH_ALEN);
3606 }
3607 EXPORT_SYMBOL(ath9k_hw_setmac);
3608
3609 void ath9k_hw_setopmode(struct ath_hw *ah)
3610 {
3611 ath9k_hw_set_operating_mode(ah, ah->opmode);
3612 }
3613 EXPORT_SYMBOL(ath9k_hw_setopmode);
3614
3615 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
3616 {
3617 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3618 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
3619 }
3620 EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
3621
3622 void ath9k_hw_write_associd(struct ath_hw *ah)
3623 {
3624 struct ath_common *common = ath9k_hw_common(ah);
3625
3626 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
3627 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
3628 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
3629 }
3630 EXPORT_SYMBOL(ath9k_hw_write_associd);
3631
3632 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
3633 {
3634 u64 tsf;
3635
3636 tsf = REG_READ(ah, AR_TSF_U32);
3637 tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
3638
3639 return tsf;
3640 }
3641 EXPORT_SYMBOL(ath9k_hw_gettsf64);
3642
3643 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
3644 {
3645 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
3646 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
3647 }
3648 EXPORT_SYMBOL(ath9k_hw_settsf64);
3649
3650 void ath9k_hw_reset_tsf(struct ath_hw *ah)
3651 {
3652 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
3653 AH_TSF_WRITE_TIMEOUT))
3654 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
3655 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
3656
3657 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3658 }
3659 EXPORT_SYMBOL(ath9k_hw_reset_tsf);
3660
3661 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
3662 {
3663 if (setting)
3664 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
3665 else
3666 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
3667 }
3668 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
3669
3670 /*
3671 * Extend 15-bit time stamp from rx descriptor to
3672 * a full 64-bit TSF using the current h/w TSF.
3673 */
3674 u64 ath9k_hw_extend_tsf(struct ath_hw *ah, u32 rstamp)
3675 {
3676 u64 tsf;
3677
3678 tsf = ath9k_hw_gettsf64(ah);
3679 if ((tsf & 0x7fff) < rstamp)
3680 tsf -= 0x8000;
3681 return (tsf & ~0x7fff) | rstamp;
3682 }
3683 EXPORT_SYMBOL(ath9k_hw_extend_tsf);
3684
3685 void ath9k_hw_set11nmac2040(struct ath_hw *ah)
3686 {
3687 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
3688 u32 macmode;
3689
3690 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
3691 macmode = AR_2040_JOINED_RX_CLEAR;
3692 else
3693 macmode = 0;
3694
3695 REG_WRITE(ah, AR_2040_MODE, macmode);
3696 }
3697
3698 /* HW Generic timers configuration */
3699
3700 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
3701 {
3702 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3703 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3704 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3705 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3706 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3707 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3708 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3709 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3710 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
3711 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
3712 AR_NDP2_TIMER_MODE, 0x0002},
3713 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
3714 AR_NDP2_TIMER_MODE, 0x0004},
3715 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
3716 AR_NDP2_TIMER_MODE, 0x0008},
3717 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
3718 AR_NDP2_TIMER_MODE, 0x0010},
3719 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
3720 AR_NDP2_TIMER_MODE, 0x0020},
3721 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
3722 AR_NDP2_TIMER_MODE, 0x0040},
3723 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
3724 AR_NDP2_TIMER_MODE, 0x0080}
3725 };
3726
3727 /* HW generic timer primitives */
3728
3729 /* compute and clear index of rightmost 1 */
3730 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
3731 {
3732 u32 b;
3733
3734 b = *mask;
3735 b &= (0-b);
3736 *mask &= ~b;
3737 b *= debruijn32;
3738 b >>= 27;
3739
3740 return timer_table->gen_timer_index[b];
3741 }
3742
3743 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
3744 {
3745 return REG_READ(ah, AR_TSF_L32);
3746 }
3747 EXPORT_SYMBOL(ath9k_hw_gettsf32);
3748
3749 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
3750 void (*trigger)(void *),
3751 void (*overflow)(void *),
3752 void *arg,
3753 u8 timer_index)
3754 {
3755 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3756 struct ath_gen_timer *timer;
3757
3758 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
3759
3760 if (timer == NULL) {
3761 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
3762 "Failed to allocate memory"
3763 "for hw timer[%d]\n", timer_index);
3764 return NULL;
3765 }
3766
3767 /* allocate a hardware generic timer slot */
3768 timer_table->timers[timer_index] = timer;
3769 timer->index = timer_index;
3770 timer->trigger = trigger;
3771 timer->overflow = overflow;
3772 timer->arg = arg;
3773
3774 return timer;
3775 }
3776 EXPORT_SYMBOL(ath_gen_timer_alloc);
3777
3778 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
3779 struct ath_gen_timer *timer,
3780 u32 timer_next,
3781 u32 timer_period)
3782 {
3783 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3784 u32 tsf;
3785
3786 BUG_ON(!timer_period);
3787
3788 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
3789
3790 tsf = ath9k_hw_gettsf32(ah);
3791
3792 ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
3793 "curent tsf %x period %x"
3794 "timer_next %x\n", tsf, timer_period, timer_next);
3795
3796 /*
3797 * Pull timer_next forward if the current TSF already passed it
3798 * because of software latency
3799 */
3800 if (timer_next < tsf)
3801 timer_next = tsf + timer_period;
3802
3803 /*
3804 * Program generic timer registers
3805 */
3806 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
3807 timer_next);
3808 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
3809 timer_period);
3810 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3811 gen_tmr_configuration[timer->index].mode_mask);
3812
3813 /* Enable both trigger and thresh interrupt masks */
3814 REG_SET_BIT(ah, AR_IMR_S5,
3815 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3816 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3817 }
3818 EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
3819
3820 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
3821 {
3822 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3823
3824 if ((timer->index < AR_FIRST_NDP_TIMER) ||
3825 (timer->index >= ATH_MAX_GEN_TIMER)) {
3826 return;
3827 }
3828
3829 /* Clear generic timer enable bits. */
3830 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3831 gen_tmr_configuration[timer->index].mode_mask);
3832
3833 /* Disable both trigger and thresh interrupt masks */
3834 REG_CLR_BIT(ah, AR_IMR_S5,
3835 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3836 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3837
3838 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
3839 }
3840 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
3841
3842 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
3843 {
3844 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3845
3846 /* free the hardware generic timer slot */
3847 timer_table->timers[timer->index] = NULL;
3848 kfree(timer);
3849 }
3850 EXPORT_SYMBOL(ath_gen_timer_free);
3851
3852 /*
3853 * Generic Timer Interrupts handling
3854 */
3855 void ath_gen_timer_isr(struct ath_hw *ah)
3856 {
3857 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3858 struct ath_gen_timer *timer;
3859 struct ath_common *common = ath9k_hw_common(ah);
3860 u32 trigger_mask, thresh_mask, index;
3861
3862 /* get hardware generic timer interrupt status */
3863 trigger_mask = ah->intr_gen_timer_trigger;
3864 thresh_mask = ah->intr_gen_timer_thresh;
3865 trigger_mask &= timer_table->timer_mask.val;
3866 thresh_mask &= timer_table->timer_mask.val;
3867
3868 trigger_mask &= ~thresh_mask;
3869
3870 while (thresh_mask) {
3871 index = rightmost_index(timer_table, &thresh_mask);
3872 timer = timer_table->timers[index];
3873 BUG_ON(!timer);
3874 ath_print(common, ATH_DBG_HWTIMER,
3875 "TSF overflow for Gen timer %d\n", index);
3876 timer->overflow(timer->arg);
3877 }
3878
3879 while (trigger_mask) {
3880 index = rightmost_index(timer_table, &trigger_mask);
3881 timer = timer_table->timers[index];
3882 BUG_ON(!timer);
3883 ath_print(common, ATH_DBG_HWTIMER,
3884 "Gen timer[%d] trigger\n", index);
3885 timer->trigger(timer->arg);
3886 }
3887 }
3888 EXPORT_SYMBOL(ath_gen_timer_isr);
3889
3890 static struct {
3891 u32 version;
3892 const char * name;
3893 } ath_mac_bb_names[] = {
3894 /* Devices with external radios */
3895 { AR_SREV_VERSION_5416_PCI, "5416" },
3896 { AR_SREV_VERSION_5416_PCIE, "5418" },
3897 { AR_SREV_VERSION_9100, "9100" },
3898 { AR_SREV_VERSION_9160, "9160" },
3899 /* Single-chip solutions */
3900 { AR_SREV_VERSION_9280, "9280" },
3901 { AR_SREV_VERSION_9285, "9285" },
3902 { AR_SREV_VERSION_9287, "9287" },
3903 { AR_SREV_VERSION_9271, "9271" },
3904 };
3905
3906 /* For devices with external radios */
3907 static struct {
3908 u16 version;
3909 const char * name;
3910 } ath_rf_names[] = {
3911 { 0, "5133" },
3912 { AR_RAD5133_SREV_MAJOR, "5133" },
3913 { AR_RAD5122_SREV_MAJOR, "5122" },
3914 { AR_RAD2133_SREV_MAJOR, "2133" },
3915 { AR_RAD2122_SREV_MAJOR, "2122" }
3916 };
3917
3918 /*
3919 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3920 */
3921 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
3922 {
3923 int i;
3924
3925 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3926 if (ath_mac_bb_names[i].version == mac_bb_version) {
3927 return ath_mac_bb_names[i].name;
3928 }
3929 }
3930
3931 return "????";
3932 }
3933
3934 /*
3935 * Return the RF name. "????" is returned if the RF is unknown.
3936 * Used for devices with external radios.
3937 */
3938 static const char *ath9k_hw_rf_name(u16 rf_version)
3939 {
3940 int i;
3941
3942 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3943 if (ath_rf_names[i].version == rf_version) {
3944 return ath_rf_names[i].name;
3945 }
3946 }
3947
3948 return "????";
3949 }
3950
3951 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
3952 {
3953 int used;
3954
3955 /* chipsets >= AR9280 are single-chip */
3956 if (AR_SREV_9280_10_OR_LATER(ah)) {
3957 used = snprintf(hw_name, len,
3958 "Atheros AR%s Rev:%x",
3959 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3960 ah->hw_version.macRev);
3961 }
3962 else {
3963 used = snprintf(hw_name, len,
3964 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3965 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3966 ah->hw_version.macRev,
3967 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
3968 AR_RADIO_SREV_MAJOR)),
3969 ah->hw_version.phyRev);
3970 }
3971
3972 hw_name[used] = '\0';
3973 }
3974 EXPORT_SYMBOL(ath9k_hw_name);
Linux kernel - Deliverables
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