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ath9k_hw: Initialize interrupt mask for AR9003
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / hw.c
1 /*
2 * Copyright (c) 2008-2010 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/io.h>
18 #include <asm/unaligned.h>
19
20 #include "hw.h"
21 #include "hw-ops.h"
22 #include "rc.h"
23
24 #define ATH9K_CLOCK_RATE_CCK 22
25 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
26 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
27
28 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
29
30 MODULE_AUTHOR("Atheros Communications");
31 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
32 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
33 MODULE_LICENSE("Dual BSD/GPL");
34
35 static int __init ath9k_init(void)
36 {
37 return 0;
38 }
39 module_init(ath9k_init);
40
41 static void __exit ath9k_exit(void)
42 {
43 return;
44 }
45 module_exit(ath9k_exit);
46
47 /* Private hardware callbacks */
48
49 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
50 {
51 ath9k_hw_private_ops(ah)->init_cal_settings(ah);
52 }
53
54 static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
55 {
56 ath9k_hw_private_ops(ah)->init_mode_regs(ah);
57 }
58
59 static bool ath9k_hw_macversion_supported(struct ath_hw *ah)
60 {
61 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
62
63 return priv_ops->macversion_supported(ah->hw_version.macVersion);
64 }
65
66 static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
67 struct ath9k_channel *chan)
68 {
69 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
70 }
71
72 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
73 {
74 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
75 return;
76
77 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
78 }
79
80 /********************/
81 /* Helper Functions */
82 /********************/
83
84 static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
85 {
86 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
87
88 if (!ah->curchan) /* should really check for CCK instead */
89 return usecs *ATH9K_CLOCK_RATE_CCK;
90 if (conf->channel->band == IEEE80211_BAND_2GHZ)
91 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
92 return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
93 }
94
95 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
96 {
97 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
98
99 if (conf_is_ht40(conf))
100 return ath9k_hw_mac_clks(ah, usecs) * 2;
101 else
102 return ath9k_hw_mac_clks(ah, usecs);
103 }
104
105 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
106 {
107 int i;
108
109 BUG_ON(timeout < AH_TIME_QUANTUM);
110
111 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
112 if ((REG_READ(ah, reg) & mask) == val)
113 return true;
114
115 udelay(AH_TIME_QUANTUM);
116 }
117
118 ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
119 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
120 timeout, reg, REG_READ(ah, reg), mask, val);
121
122 return false;
123 }
124 EXPORT_SYMBOL(ath9k_hw_wait);
125
126 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
127 {
128 u32 retval;
129 int i;
130
131 for (i = 0, retval = 0; i < n; i++) {
132 retval = (retval << 1) | (val & 1);
133 val >>= 1;
134 }
135 return retval;
136 }
137
138 bool ath9k_get_channel_edges(struct ath_hw *ah,
139 u16 flags, u16 *low,
140 u16 *high)
141 {
142 struct ath9k_hw_capabilities *pCap = &ah->caps;
143
144 if (flags & CHANNEL_5GHZ) {
145 *low = pCap->low_5ghz_chan;
146 *high = pCap->high_5ghz_chan;
147 return true;
148 }
149 if ((flags & CHANNEL_2GHZ)) {
150 *low = pCap->low_2ghz_chan;
151 *high = pCap->high_2ghz_chan;
152 return true;
153 }
154 return false;
155 }
156
157 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
158 u8 phy, int kbps,
159 u32 frameLen, u16 rateix,
160 bool shortPreamble)
161 {
162 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
163
164 if (kbps == 0)
165 return 0;
166
167 switch (phy) {
168 case WLAN_RC_PHY_CCK:
169 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
170 if (shortPreamble)
171 phyTime >>= 1;
172 numBits = frameLen << 3;
173 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
174 break;
175 case WLAN_RC_PHY_OFDM:
176 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
177 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
178 numBits = OFDM_PLCP_BITS + (frameLen << 3);
179 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
180 txTime = OFDM_SIFS_TIME_QUARTER
181 + OFDM_PREAMBLE_TIME_QUARTER
182 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
183 } else if (ah->curchan &&
184 IS_CHAN_HALF_RATE(ah->curchan)) {
185 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
186 numBits = OFDM_PLCP_BITS + (frameLen << 3);
187 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
188 txTime = OFDM_SIFS_TIME_HALF +
189 OFDM_PREAMBLE_TIME_HALF
190 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
191 } else {
192 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
193 numBits = OFDM_PLCP_BITS + (frameLen << 3);
194 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
195 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
196 + (numSymbols * OFDM_SYMBOL_TIME);
197 }
198 break;
199 default:
200 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
201 "Unknown phy %u (rate ix %u)\n", phy, rateix);
202 txTime = 0;
203 break;
204 }
205
206 return txTime;
207 }
208 EXPORT_SYMBOL(ath9k_hw_computetxtime);
209
210 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
211 struct ath9k_channel *chan,
212 struct chan_centers *centers)
213 {
214 int8_t extoff;
215
216 if (!IS_CHAN_HT40(chan)) {
217 centers->ctl_center = centers->ext_center =
218 centers->synth_center = chan->channel;
219 return;
220 }
221
222 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
223 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
224 centers->synth_center =
225 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
226 extoff = 1;
227 } else {
228 centers->synth_center =
229 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
230 extoff = -1;
231 }
232
233 centers->ctl_center =
234 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
235 /* 25 MHz spacing is supported by hw but not on upper layers */
236 centers->ext_center =
237 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
238 }
239
240 /******************/
241 /* Chip Revisions */
242 /******************/
243
244 static void ath9k_hw_read_revisions(struct ath_hw *ah)
245 {
246 u32 val;
247
248 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
249
250 if (val == 0xFF) {
251 val = REG_READ(ah, AR_SREV);
252 ah->hw_version.macVersion =
253 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
254 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
255 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
256 } else {
257 if (!AR_SREV_9100(ah))
258 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
259
260 ah->hw_version.macRev = val & AR_SREV_REVISION;
261
262 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
263 ah->is_pciexpress = true;
264 }
265 }
266
267 static int ath9k_hw_get_radiorev(struct ath_hw *ah)
268 {
269 u32 val;
270 int i;
271
272 REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
273
274 for (i = 0; i < 8; i++)
275 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
276 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
277 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
278
279 return ath9k_hw_reverse_bits(val, 8);
280 }
281
282 /************************************/
283 /* HW Attach, Detach, Init Routines */
284 /************************************/
285
286 static void ath9k_hw_disablepcie(struct ath_hw *ah)
287 {
288 if (AR_SREV_9100(ah))
289 return;
290
291 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
292 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
293 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
294 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
295 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
296 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
297 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
298 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
299 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
300
301 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
302 }
303
304 /* This should work for all families including legacy */
305 static bool ath9k_hw_chip_test(struct ath_hw *ah)
306 {
307 struct ath_common *common = ath9k_hw_common(ah);
308 u32 regAddr[2] = { AR_STA_ID0 };
309 u32 regHold[2];
310 u32 patternData[4] = { 0x55555555,
311 0xaaaaaaaa,
312 0x66666666,
313 0x99999999 };
314 int i, j, loop_max;
315
316 if (!AR_SREV_9300_20_OR_LATER(ah)) {
317 loop_max = 2;
318 regAddr[1] = AR_PHY_BASE + (8 << 2);
319 } else
320 loop_max = 1;
321
322 for (i = 0; i < loop_max; i++) {
323 u32 addr = regAddr[i];
324 u32 wrData, rdData;
325
326 regHold[i] = REG_READ(ah, addr);
327 for (j = 0; j < 0x100; j++) {
328 wrData = (j << 16) | j;
329 REG_WRITE(ah, addr, wrData);
330 rdData = REG_READ(ah, addr);
331 if (rdData != wrData) {
332 ath_print(common, ATH_DBG_FATAL,
333 "address test failed "
334 "addr: 0x%08x - wr:0x%08x != "
335 "rd:0x%08x\n",
336 addr, wrData, rdData);
337 return false;
338 }
339 }
340 for (j = 0; j < 4; j++) {
341 wrData = patternData[j];
342 REG_WRITE(ah, addr, wrData);
343 rdData = REG_READ(ah, addr);
344 if (wrData != rdData) {
345 ath_print(common, ATH_DBG_FATAL,
346 "address test failed "
347 "addr: 0x%08x - wr:0x%08x != "
348 "rd:0x%08x\n",
349 addr, wrData, rdData);
350 return false;
351 }
352 }
353 REG_WRITE(ah, regAddr[i], regHold[i]);
354 }
355 udelay(100);
356
357 return true;
358 }
359
360 static void ath9k_hw_init_config(struct ath_hw *ah)
361 {
362 int i;
363
364 ah->config.dma_beacon_response_time = 2;
365 ah->config.sw_beacon_response_time = 10;
366 ah->config.additional_swba_backoff = 0;
367 ah->config.ack_6mb = 0x0;
368 ah->config.cwm_ignore_extcca = 0;
369 ah->config.pcie_powersave_enable = 0;
370 ah->config.pcie_clock_req = 0;
371 ah->config.pcie_waen = 0;
372 ah->config.analog_shiftreg = 1;
373 ah->config.ofdm_trig_low = 200;
374 ah->config.ofdm_trig_high = 500;
375 ah->config.cck_trig_high = 200;
376 ah->config.cck_trig_low = 100;
377
378 /*
379 * For now ANI is disabled for AR9003, it is still
380 * being tested.
381 */
382 if (!AR_SREV_9300_20_OR_LATER(ah))
383 ah->config.enable_ani = 1;
384
385 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
386 ah->config.spurchans[i][0] = AR_NO_SPUR;
387 ah->config.spurchans[i][1] = AR_NO_SPUR;
388 }
389
390 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
391 ah->config.ht_enable = 1;
392 else
393 ah->config.ht_enable = 0;
394
395 ah->config.rx_intr_mitigation = true;
396
397 /*
398 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
399 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
400 * This means we use it for all AR5416 devices, and the few
401 * minor PCI AR9280 devices out there.
402 *
403 * Serialization is required because these devices do not handle
404 * well the case of two concurrent reads/writes due to the latency
405 * involved. During one read/write another read/write can be issued
406 * on another CPU while the previous read/write may still be working
407 * on our hardware, if we hit this case the hardware poops in a loop.
408 * We prevent this by serializing reads and writes.
409 *
410 * This issue is not present on PCI-Express devices or pre-AR5416
411 * devices (legacy, 802.11abg).
412 */
413 if (num_possible_cpus() > 1)
414 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
415 }
416
417 static void ath9k_hw_init_defaults(struct ath_hw *ah)
418 {
419 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
420
421 regulatory->country_code = CTRY_DEFAULT;
422 regulatory->power_limit = MAX_RATE_POWER;
423 regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
424
425 ah->hw_version.magic = AR5416_MAGIC;
426 ah->hw_version.subvendorid = 0;
427
428 ah->ah_flags = 0;
429 if (!AR_SREV_9100(ah))
430 ah->ah_flags = AH_USE_EEPROM;
431
432 ah->atim_window = 0;
433 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
434 ah->beacon_interval = 100;
435 ah->enable_32kHz_clock = DONT_USE_32KHZ;
436 ah->slottime = (u32) -1;
437 ah->globaltxtimeout = (u32) -1;
438 ah->power_mode = ATH9K_PM_UNDEFINED;
439 }
440
441 static int ath9k_hw_rf_claim(struct ath_hw *ah)
442 {
443 u32 val;
444
445 REG_WRITE(ah, AR_PHY(0), 0x00000007);
446
447 val = ath9k_hw_get_radiorev(ah);
448 switch (val & AR_RADIO_SREV_MAJOR) {
449 case 0:
450 val = AR_RAD5133_SREV_MAJOR;
451 break;
452 case AR_RAD5133_SREV_MAJOR:
453 case AR_RAD5122_SREV_MAJOR:
454 case AR_RAD2133_SREV_MAJOR:
455 case AR_RAD2122_SREV_MAJOR:
456 break;
457 default:
458 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
459 "Radio Chip Rev 0x%02X not supported\n",
460 val & AR_RADIO_SREV_MAJOR);
461 return -EOPNOTSUPP;
462 }
463
464 ah->hw_version.analog5GhzRev = val;
465
466 return 0;
467 }
468
469 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
470 {
471 struct ath_common *common = ath9k_hw_common(ah);
472 u32 sum;
473 int i;
474 u16 eeval;
475
476 sum = 0;
477 for (i = 0; i < 3; i++) {
478 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
479 sum += eeval;
480 common->macaddr[2 * i] = eeval >> 8;
481 common->macaddr[2 * i + 1] = eeval & 0xff;
482 }
483 if (sum == 0 || sum == 0xffff * 3)
484 return -EADDRNOTAVAIL;
485
486 return 0;
487 }
488
489 static int ath9k_hw_post_init(struct ath_hw *ah)
490 {
491 int ecode;
492
493 if (!AR_SREV_9271(ah)) {
494 if (!ath9k_hw_chip_test(ah))
495 return -ENODEV;
496 }
497
498 ecode = ath9k_hw_rf_claim(ah);
499 if (ecode != 0)
500 return ecode;
501
502 ecode = ath9k_hw_eeprom_init(ah);
503 if (ecode != 0)
504 return ecode;
505
506 ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
507 "Eeprom VER: %d, REV: %d\n",
508 ah->eep_ops->get_eeprom_ver(ah),
509 ah->eep_ops->get_eeprom_rev(ah));
510
511 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
512 if (ecode) {
513 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
514 "Failed allocating banks for "
515 "external radio\n");
516 return ecode;
517 }
518
519 if (!AR_SREV_9100(ah)) {
520 ath9k_hw_ani_setup(ah);
521 ath9k_hw_ani_init(ah);
522 }
523
524 return 0;
525 }
526
527 static void ath9k_hw_init_eeprom_fix(struct ath_hw *ah)
528 {
529 struct base_eep_header *pBase = &(ah->eeprom.def.baseEepHeader);
530 struct ath_common *common = ath9k_hw_common(ah);
531
532 ah->need_an_top2_fixup = (ah->hw_version.devid == AR9280_DEVID_PCI) &&
533 !AR_SREV_9285(ah) && !AR_SREV_9271(ah) &&
534 ((pBase->version & 0xff) > 0x0a) &&
535 (pBase->pwdclkind == 0);
536
537 if (ah->need_an_top2_fixup)
538 ath_print(common, ATH_DBG_EEPROM,
539 "needs fixup for AR_AN_TOP2 register\n");
540 }
541
542 static void ath9k_hw_attach_ops(struct ath_hw *ah)
543 {
544 if (AR_SREV_9300_20_OR_LATER(ah))
545 ar9003_hw_attach_ops(ah);
546 else
547 ar9002_hw_attach_ops(ah);
548 }
549
550 /* Called for all hardware families */
551 static int __ath9k_hw_init(struct ath_hw *ah)
552 {
553 struct ath_common *common = ath9k_hw_common(ah);
554 int r = 0;
555
556 if (ah->hw_version.devid == AR5416_AR9100_DEVID)
557 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
558
559 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
560 ath_print(common, ATH_DBG_FATAL,
561 "Couldn't reset chip\n");
562 return -EIO;
563 }
564
565 ath9k_hw_init_defaults(ah);
566 ath9k_hw_init_config(ah);
567
568 ath9k_hw_attach_ops(ah);
569
570 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
571 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
572 return -EIO;
573 }
574
575 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
576 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
577 (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
578 ah->config.serialize_regmode =
579 SER_REG_MODE_ON;
580 } else {
581 ah->config.serialize_regmode =
582 SER_REG_MODE_OFF;
583 }
584 }
585
586 ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
587 ah->config.serialize_regmode);
588
589 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
590 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
591 else
592 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
593
594 if (!ath9k_hw_macversion_supported(ah)) {
595 ath_print(common, ATH_DBG_FATAL,
596 "Mac Chip Rev 0x%02x.%x is not supported by "
597 "this driver\n", ah->hw_version.macVersion,
598 ah->hw_version.macRev);
599 return -EOPNOTSUPP;
600 }
601
602 if (AR_SREV_9271(ah) || AR_SREV_9100(ah))
603 ah->is_pciexpress = false;
604
605 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
606 ath9k_hw_init_cal_settings(ah);
607
608 ah->ani_function = ATH9K_ANI_ALL;
609 if (AR_SREV_9280_10_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
610 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
611
612 ath9k_hw_init_mode_regs(ah);
613
614 if (ah->is_pciexpress)
615 ath9k_hw_configpcipowersave(ah, 0, 0);
616 else
617 ath9k_hw_disablepcie(ah);
618
619 if (!AR_SREV_9300_20_OR_LATER(ah))
620 ar9002_hw_cck_chan14_spread(ah);
621
622 r = ath9k_hw_post_init(ah);
623 if (r)
624 return r;
625
626 ath9k_hw_init_mode_gain_regs(ah);
627 r = ath9k_hw_fill_cap_info(ah);
628 if (r)
629 return r;
630
631 ath9k_hw_init_eeprom_fix(ah);
632
633 r = ath9k_hw_init_macaddr(ah);
634 if (r) {
635 ath_print(common, ATH_DBG_FATAL,
636 "Failed to initialize MAC address\n");
637 return r;
638 }
639
640 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
641 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
642 else
643 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
644
645 if (AR_SREV_9300_20_OR_LATER(ah))
646 ar9003_hw_set_nf_limits(ah);
647
648 ath9k_init_nfcal_hist_buffer(ah);
649
650 common->state = ATH_HW_INITIALIZED;
651
652 return 0;
653 }
654
655 int ath9k_hw_init(struct ath_hw *ah)
656 {
657 int ret;
658 struct ath_common *common = ath9k_hw_common(ah);
659
660 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
661 switch (ah->hw_version.devid) {
662 case AR5416_DEVID_PCI:
663 case AR5416_DEVID_PCIE:
664 case AR5416_AR9100_DEVID:
665 case AR9160_DEVID_PCI:
666 case AR9280_DEVID_PCI:
667 case AR9280_DEVID_PCIE:
668 case AR9285_DEVID_PCIE:
669 case AR9287_DEVID_PCI:
670 case AR9287_DEVID_PCIE:
671 case AR2427_DEVID_PCIE:
672 case AR9300_DEVID_PCIE:
673 break;
674 default:
675 if (common->bus_ops->ath_bus_type == ATH_USB)
676 break;
677 ath_print(common, ATH_DBG_FATAL,
678 "Hardware device ID 0x%04x not supported\n",
679 ah->hw_version.devid);
680 return -EOPNOTSUPP;
681 }
682
683 ret = __ath9k_hw_init(ah);
684 if (ret) {
685 ath_print(common, ATH_DBG_FATAL,
686 "Unable to initialize hardware; "
687 "initialization status: %d\n", ret);
688 return ret;
689 }
690
691 return 0;
692 }
693 EXPORT_SYMBOL(ath9k_hw_init);
694
695 static void ath9k_hw_init_qos(struct ath_hw *ah)
696 {
697 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
698 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
699
700 REG_WRITE(ah, AR_QOS_NO_ACK,
701 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
702 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
703 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
704
705 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
706 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
707 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
708 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
709 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
710 }
711
712 static void ath9k_hw_init_pll(struct ath_hw *ah,
713 struct ath9k_channel *chan)
714 {
715 u32 pll = ath9k_hw_compute_pll_control(ah, chan);
716
717 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
718
719 /* Switch the core clock for ar9271 to 117Mhz */
720 if (AR_SREV_9271(ah)) {
721 udelay(500);
722 REG_WRITE(ah, 0x50040, 0x304);
723 }
724
725 udelay(RTC_PLL_SETTLE_DELAY);
726
727 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
728 }
729
730 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
731 enum nl80211_iftype opmode)
732 {
733 u32 imr_reg = AR_IMR_TXERR |
734 AR_IMR_TXURN |
735 AR_IMR_RXERR |
736 AR_IMR_RXORN |
737 AR_IMR_BCNMISC;
738
739 if (AR_SREV_9300_20_OR_LATER(ah)) {
740 imr_reg |= AR_IMR_RXOK_HP;
741 if (ah->config.rx_intr_mitigation)
742 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
743 else
744 imr_reg |= AR_IMR_RXOK_LP;
745
746 } else {
747 if (ah->config.rx_intr_mitigation)
748 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
749 else
750 imr_reg |= AR_IMR_RXOK;
751 }
752
753 if (ah->config.tx_intr_mitigation)
754 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
755 else
756 imr_reg |= AR_IMR_TXOK;
757
758 if (opmode == NL80211_IFTYPE_AP)
759 imr_reg |= AR_IMR_MIB;
760
761 REG_WRITE(ah, AR_IMR, imr_reg);
762 ah->imrs2_reg |= AR_IMR_S2_GTT;
763 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
764
765 if (!AR_SREV_9100(ah)) {
766 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
767 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
768 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
769 }
770
771 if (AR_SREV_9300_20_OR_LATER(ah)) {
772 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
773 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
774 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
775 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
776 }
777 }
778
779 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
780 {
781 u32 val = ath9k_hw_mac_to_clks(ah, us);
782 val = min(val, (u32) 0xFFFF);
783 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
784 }
785
786 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
787 {
788 u32 val = ath9k_hw_mac_to_clks(ah, us);
789 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
790 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
791 }
792
793 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
794 {
795 u32 val = ath9k_hw_mac_to_clks(ah, us);
796 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
797 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
798 }
799
800 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
801 {
802 if (tu > 0xFFFF) {
803 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
804 "bad global tx timeout %u\n", tu);
805 ah->globaltxtimeout = (u32) -1;
806 return false;
807 } else {
808 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
809 ah->globaltxtimeout = tu;
810 return true;
811 }
812 }
813
814 void ath9k_hw_init_global_settings(struct ath_hw *ah)
815 {
816 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
817 int acktimeout;
818 int slottime;
819 int sifstime;
820
821 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
822 ah->misc_mode);
823
824 if (ah->misc_mode != 0)
825 REG_WRITE(ah, AR_PCU_MISC,
826 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
827
828 if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
829 sifstime = 16;
830 else
831 sifstime = 10;
832
833 /* As defined by IEEE 802.11-2007 17.3.8.6 */
834 slottime = ah->slottime + 3 * ah->coverage_class;
835 acktimeout = slottime + sifstime;
836
837 /*
838 * Workaround for early ACK timeouts, add an offset to match the
839 * initval's 64us ack timeout value.
840 * This was initially only meant to work around an issue with delayed
841 * BA frames in some implementations, but it has been found to fix ACK
842 * timeout issues in other cases as well.
843 */
844 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
845 acktimeout += 64 - sifstime - ah->slottime;
846
847 ath9k_hw_setslottime(ah, slottime);
848 ath9k_hw_set_ack_timeout(ah, acktimeout);
849 ath9k_hw_set_cts_timeout(ah, acktimeout);
850 if (ah->globaltxtimeout != (u32) -1)
851 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
852 }
853 EXPORT_SYMBOL(ath9k_hw_init_global_settings);
854
855 void ath9k_hw_deinit(struct ath_hw *ah)
856 {
857 struct ath_common *common = ath9k_hw_common(ah);
858
859 if (common->state < ATH_HW_INITIALIZED)
860 goto free_hw;
861
862 if (!AR_SREV_9100(ah))
863 ath9k_hw_ani_disable(ah);
864
865 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
866
867 free_hw:
868 ath9k_hw_rf_free_ext_banks(ah);
869 }
870 EXPORT_SYMBOL(ath9k_hw_deinit);
871
872 /*******/
873 /* INI */
874 /*******/
875
876 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
877 {
878 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
879
880 if (IS_CHAN_B(chan))
881 ctl |= CTL_11B;
882 else if (IS_CHAN_G(chan))
883 ctl |= CTL_11G;
884 else
885 ctl |= CTL_11A;
886
887 return ctl;
888 }
889
890 /****************************************/
891 /* Reset and Channel Switching Routines */
892 /****************************************/
893
894 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
895 {
896 u32 regval;
897
898 /*
899 * set AHB_MODE not to do cacheline prefetches
900 */
901 regval = REG_READ(ah, AR_AHB_MODE);
902 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
903
904 /*
905 * let mac dma reads be in 128 byte chunks
906 */
907 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
908 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
909
910 /*
911 * Restore TX Trigger Level to its pre-reset value.
912 * The initial value depends on whether aggregation is enabled, and is
913 * adjusted whenever underruns are detected.
914 */
915 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
916
917 /*
918 * let mac dma writes be in 128 byte chunks
919 */
920 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
921 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
922
923 /*
924 * Setup receive FIFO threshold to hold off TX activities
925 */
926 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
927
928 /*
929 * reduce the number of usable entries in PCU TXBUF to avoid
930 * wrap around issues.
931 */
932 if (AR_SREV_9285(ah)) {
933 /* For AR9285 the number of Fifos are reduced to half.
934 * So set the usable tx buf size also to half to
935 * avoid data/delimiter underruns
936 */
937 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
938 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
939 } else if (!AR_SREV_9271(ah)) {
940 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
941 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
942 }
943 }
944
945 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
946 {
947 u32 val;
948
949 val = REG_READ(ah, AR_STA_ID1);
950 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
951 switch (opmode) {
952 case NL80211_IFTYPE_AP:
953 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
954 | AR_STA_ID1_KSRCH_MODE);
955 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
956 break;
957 case NL80211_IFTYPE_ADHOC:
958 case NL80211_IFTYPE_MESH_POINT:
959 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
960 | AR_STA_ID1_KSRCH_MODE);
961 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
962 break;
963 case NL80211_IFTYPE_STATION:
964 case NL80211_IFTYPE_MONITOR:
965 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
966 break;
967 }
968 }
969
970 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
971 u32 *coef_mantissa, u32 *coef_exponent)
972 {
973 u32 coef_exp, coef_man;
974
975 for (coef_exp = 31; coef_exp > 0; coef_exp--)
976 if ((coef_scaled >> coef_exp) & 0x1)
977 break;
978
979 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
980
981 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
982
983 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
984 *coef_exponent = coef_exp - 16;
985 }
986
987 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
988 {
989 u32 rst_flags;
990 u32 tmpReg;
991
992 if (AR_SREV_9100(ah)) {
993 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
994 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
995 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
996 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
997 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
998 }
999
1000 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1001 AR_RTC_FORCE_WAKE_ON_INT);
1002
1003 if (AR_SREV_9100(ah)) {
1004 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1005 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1006 } else {
1007 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1008 if (tmpReg &
1009 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1010 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1011 u32 val;
1012 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1013
1014 val = AR_RC_HOSTIF;
1015 if (!AR_SREV_9300_20_OR_LATER(ah))
1016 val |= AR_RC_AHB;
1017 REG_WRITE(ah, AR_RC, val);
1018
1019 } else if (!AR_SREV_9300_20_OR_LATER(ah))
1020 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1021
1022 rst_flags = AR_RTC_RC_MAC_WARM;
1023 if (type == ATH9K_RESET_COLD)
1024 rst_flags |= AR_RTC_RC_MAC_COLD;
1025 }
1026
1027 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1028 udelay(50);
1029
1030 REG_WRITE(ah, AR_RTC_RC, 0);
1031 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1032 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1033 "RTC stuck in MAC reset\n");
1034 return false;
1035 }
1036
1037 if (!AR_SREV_9100(ah))
1038 REG_WRITE(ah, AR_RC, 0);
1039
1040 if (AR_SREV_9100(ah))
1041 udelay(50);
1042
1043 return true;
1044 }
1045
1046 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1047 {
1048 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1049 AR_RTC_FORCE_WAKE_ON_INT);
1050
1051 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1052 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1053
1054 REG_WRITE(ah, AR_RTC_RESET, 0);
1055
1056 if (!AR_SREV_9300_20_OR_LATER(ah))
1057 udelay(2);
1058
1059 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1060 REG_WRITE(ah, AR_RC, 0);
1061
1062 REG_WRITE(ah, AR_RTC_RESET, 1);
1063
1064 if (!ath9k_hw_wait(ah,
1065 AR_RTC_STATUS,
1066 AR_RTC_STATUS_M,
1067 AR_RTC_STATUS_ON,
1068 AH_WAIT_TIMEOUT)) {
1069 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1070 "RTC not waking up\n");
1071 return false;
1072 }
1073
1074 ath9k_hw_read_revisions(ah);
1075
1076 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1077 }
1078
1079 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1080 {
1081 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1082 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1083
1084 switch (type) {
1085 case ATH9K_RESET_POWER_ON:
1086 return ath9k_hw_set_reset_power_on(ah);
1087 case ATH9K_RESET_WARM:
1088 case ATH9K_RESET_COLD:
1089 return ath9k_hw_set_reset(ah, type);
1090 default:
1091 return false;
1092 }
1093 }
1094
1095 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1096 struct ath9k_channel *chan)
1097 {
1098 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
1099 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1100 return false;
1101 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1102 return false;
1103
1104 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1105 return false;
1106
1107 ah->chip_fullsleep = false;
1108 ath9k_hw_init_pll(ah, chan);
1109 ath9k_hw_set_rfmode(ah, chan);
1110
1111 return true;
1112 }
1113
1114 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1115 struct ath9k_channel *chan)
1116 {
1117 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1118 struct ath_common *common = ath9k_hw_common(ah);
1119 struct ieee80211_channel *channel = chan->chan;
1120 u32 qnum;
1121 int r;
1122
1123 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1124 if (ath9k_hw_numtxpending(ah, qnum)) {
1125 ath_print(common, ATH_DBG_QUEUE,
1126 "Transmit frames pending on "
1127 "queue %d\n", qnum);
1128 return false;
1129 }
1130 }
1131
1132 if (!ath9k_hw_rfbus_req(ah)) {
1133 ath_print(common, ATH_DBG_FATAL,
1134 "Could not kill baseband RX\n");
1135 return false;
1136 }
1137
1138 ath9k_hw_set_channel_regs(ah, chan);
1139
1140 r = ath9k_hw_rf_set_freq(ah, chan);
1141 if (r) {
1142 ath_print(common, ATH_DBG_FATAL,
1143 "Failed to set channel\n");
1144 return false;
1145 }
1146
1147 ah->eep_ops->set_txpower(ah, chan,
1148 ath9k_regd_get_ctl(regulatory, chan),
1149 channel->max_antenna_gain * 2,
1150 channel->max_power * 2,
1151 min((u32) MAX_RATE_POWER,
1152 (u32) regulatory->power_limit));
1153
1154 ath9k_hw_rfbus_done(ah);
1155
1156 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1157 ath9k_hw_set_delta_slope(ah, chan);
1158
1159 ath9k_hw_spur_mitigate_freq(ah, chan);
1160
1161 if (!chan->oneTimeCalsDone)
1162 chan->oneTimeCalsDone = true;
1163
1164 return true;
1165 }
1166
1167 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1168 bool bChannelChange)
1169 {
1170 struct ath_common *common = ath9k_hw_common(ah);
1171 u32 saveLedState;
1172 struct ath9k_channel *curchan = ah->curchan;
1173 u32 saveDefAntenna;
1174 u32 macStaId1;
1175 u64 tsf = 0;
1176 int i, r;
1177
1178 ah->txchainmask = common->tx_chainmask;
1179 ah->rxchainmask = common->rx_chainmask;
1180
1181 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1182 return -EIO;
1183
1184 if (curchan && !ah->chip_fullsleep)
1185 ath9k_hw_getnf(ah, curchan);
1186
1187 if (bChannelChange &&
1188 (ah->chip_fullsleep != true) &&
1189 (ah->curchan != NULL) &&
1190 (chan->channel != ah->curchan->channel) &&
1191 ((chan->channelFlags & CHANNEL_ALL) ==
1192 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
1193 !(AR_SREV_9280(ah) || IS_CHAN_A_5MHZ_SPACED(chan) ||
1194 IS_CHAN_A_5MHZ_SPACED(ah->curchan))) {
1195
1196 if (ath9k_hw_channel_change(ah, chan)) {
1197 ath9k_hw_loadnf(ah, ah->curchan);
1198 ath9k_hw_start_nfcal(ah);
1199 return 0;
1200 }
1201 }
1202
1203 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1204 if (saveDefAntenna == 0)
1205 saveDefAntenna = 1;
1206
1207 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1208
1209 /* For chips on which RTC reset is done, save TSF before it gets cleared */
1210 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1211 tsf = ath9k_hw_gettsf64(ah);
1212
1213 saveLedState = REG_READ(ah, AR_CFG_LED) &
1214 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1215 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1216
1217 ath9k_hw_mark_phy_inactive(ah);
1218
1219 /* Only required on the first reset */
1220 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1221 REG_WRITE(ah,
1222 AR9271_RESET_POWER_DOWN_CONTROL,
1223 AR9271_RADIO_RF_RST);
1224 udelay(50);
1225 }
1226
1227 if (!ath9k_hw_chip_reset(ah, chan)) {
1228 ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n");
1229 return -EINVAL;
1230 }
1231
1232 /* Only required on the first reset */
1233 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1234 ah->htc_reset_init = false;
1235 REG_WRITE(ah,
1236 AR9271_RESET_POWER_DOWN_CONTROL,
1237 AR9271_GATE_MAC_CTL);
1238 udelay(50);
1239 }
1240
1241 /* Restore TSF */
1242 if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1243 ath9k_hw_settsf64(ah, tsf);
1244
1245 if (AR_SREV_9280_10_OR_LATER(ah))
1246 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1247
1248 r = ath9k_hw_process_ini(ah, chan);
1249 if (r)
1250 return r;
1251
1252 /* Setup MFP options for CCMP */
1253 if (AR_SREV_9280_20_OR_LATER(ah)) {
1254 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1255 * frames when constructing CCMP AAD. */
1256 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1257 0xc7ff);
1258 ah->sw_mgmt_crypto = false;
1259 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1260 /* Disable hardware crypto for management frames */
1261 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1262 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1263 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1264 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1265 ah->sw_mgmt_crypto = true;
1266 } else
1267 ah->sw_mgmt_crypto = true;
1268
1269 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1270 ath9k_hw_set_delta_slope(ah, chan);
1271
1272 ath9k_hw_spur_mitigate_freq(ah, chan);
1273 ah->eep_ops->set_board_values(ah, chan);
1274
1275 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
1276 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
1277 | macStaId1
1278 | AR_STA_ID1_RTS_USE_DEF
1279 | (ah->config.
1280 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
1281 | ah->sta_id1_defaults);
1282 ath9k_hw_set_operating_mode(ah, ah->opmode);
1283
1284 ath_hw_setbssidmask(common);
1285
1286 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1287
1288 ath9k_hw_write_associd(ah);
1289
1290 REG_WRITE(ah, AR_ISR, ~0);
1291
1292 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1293
1294 r = ath9k_hw_rf_set_freq(ah, chan);
1295 if (r)
1296 return r;
1297
1298 for (i = 0; i < AR_NUM_DCU; i++)
1299 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1300
1301 ah->intr_txqs = 0;
1302 for (i = 0; i < ah->caps.total_queues; i++)
1303 ath9k_hw_resettxqueue(ah, i);
1304
1305 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
1306 ath9k_hw_init_qos(ah);
1307
1308 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1309 ath9k_enable_rfkill(ah);
1310
1311 ath9k_hw_init_global_settings(ah);
1312
1313 if (AR_SREV_9287_12_OR_LATER(ah)) {
1314 REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
1315 AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
1316 REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
1317 AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
1318 REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
1319 AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
1320
1321 REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
1322 REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
1323
1324 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
1325 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
1326 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
1327 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
1328 }
1329 if (AR_SREV_9287_12_OR_LATER(ah)) {
1330 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1331 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
1332 }
1333
1334 REG_WRITE(ah, AR_STA_ID1,
1335 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
1336
1337 ath9k_hw_set_dma(ah);
1338
1339 REG_WRITE(ah, AR_OBS, 8);
1340
1341 if (ah->config.rx_intr_mitigation) {
1342 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
1343 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
1344 }
1345
1346 ath9k_hw_init_bb(ah, chan);
1347
1348 if (!ath9k_hw_init_cal(ah, chan))
1349 return -EIO;
1350
1351 ath9k_hw_restore_chainmask(ah);
1352 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1353
1354 /*
1355 * For big endian systems turn on swapping for descriptors
1356 */
1357 if (AR_SREV_9100(ah)) {
1358 u32 mask;
1359 mask = REG_READ(ah, AR_CFG);
1360 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1361 ath_print(common, ATH_DBG_RESET,
1362 "CFG Byte Swap Set 0x%x\n", mask);
1363 } else {
1364 mask =
1365 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1366 REG_WRITE(ah, AR_CFG, mask);
1367 ath_print(common, ATH_DBG_RESET,
1368 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
1369 }
1370 } else {
1371 /* Configure AR9271 target WLAN */
1372 if (AR_SREV_9271(ah))
1373 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1374 #ifdef __BIG_ENDIAN
1375 else
1376 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1377 #endif
1378 }
1379
1380 if (ah->btcoex_hw.enabled)
1381 ath9k_hw_btcoex_enable(ah);
1382
1383 return 0;
1384 }
1385 EXPORT_SYMBOL(ath9k_hw_reset);
1386
1387 /************************/
1388 /* Key Cache Management */
1389 /************************/
1390
1391 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
1392 {
1393 u32 keyType;
1394
1395 if (entry >= ah->caps.keycache_size) {
1396 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1397 "keychache entry %u out of range\n", entry);
1398 return false;
1399 }
1400
1401 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
1402
1403 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
1404 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
1405 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
1406 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
1407 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
1408 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
1409 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
1410 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
1411
1412 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
1413 u16 micentry = entry + 64;
1414
1415 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
1416 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
1417 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
1418 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
1419
1420 }
1421
1422 return true;
1423 }
1424 EXPORT_SYMBOL(ath9k_hw_keyreset);
1425
1426 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
1427 {
1428 u32 macHi, macLo;
1429
1430 if (entry >= ah->caps.keycache_size) {
1431 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1432 "keychache entry %u out of range\n", entry);
1433 return false;
1434 }
1435
1436 if (mac != NULL) {
1437 macHi = (mac[5] << 8) | mac[4];
1438 macLo = (mac[3] << 24) |
1439 (mac[2] << 16) |
1440 (mac[1] << 8) |
1441 mac[0];
1442 macLo >>= 1;
1443 macLo |= (macHi & 1) << 31;
1444 macHi >>= 1;
1445 } else {
1446 macLo = macHi = 0;
1447 }
1448 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
1449 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
1450
1451 return true;
1452 }
1453 EXPORT_SYMBOL(ath9k_hw_keysetmac);
1454
1455 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
1456 const struct ath9k_keyval *k,
1457 const u8 *mac)
1458 {
1459 const struct ath9k_hw_capabilities *pCap = &ah->caps;
1460 struct ath_common *common = ath9k_hw_common(ah);
1461 u32 key0, key1, key2, key3, key4;
1462 u32 keyType;
1463
1464 if (entry >= pCap->keycache_size) {
1465 ath_print(common, ATH_DBG_FATAL,
1466 "keycache entry %u out of range\n", entry);
1467 return false;
1468 }
1469
1470 switch (k->kv_type) {
1471 case ATH9K_CIPHER_AES_OCB:
1472 keyType = AR_KEYTABLE_TYPE_AES;
1473 break;
1474 case ATH9K_CIPHER_AES_CCM:
1475 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
1476 ath_print(common, ATH_DBG_ANY,
1477 "AES-CCM not supported by mac rev 0x%x\n",
1478 ah->hw_version.macRev);
1479 return false;
1480 }
1481 keyType = AR_KEYTABLE_TYPE_CCM;
1482 break;
1483 case ATH9K_CIPHER_TKIP:
1484 keyType = AR_KEYTABLE_TYPE_TKIP;
1485 if (ATH9K_IS_MIC_ENABLED(ah)
1486 && entry + 64 >= pCap->keycache_size) {
1487 ath_print(common, ATH_DBG_ANY,
1488 "entry %u inappropriate for TKIP\n", entry);
1489 return false;
1490 }
1491 break;
1492 case ATH9K_CIPHER_WEP:
1493 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
1494 ath_print(common, ATH_DBG_ANY,
1495 "WEP key length %u too small\n", k->kv_len);
1496 return false;
1497 }
1498 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
1499 keyType = AR_KEYTABLE_TYPE_40;
1500 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
1501 keyType = AR_KEYTABLE_TYPE_104;
1502 else
1503 keyType = AR_KEYTABLE_TYPE_128;
1504 break;
1505 case ATH9K_CIPHER_CLR:
1506 keyType = AR_KEYTABLE_TYPE_CLR;
1507 break;
1508 default:
1509 ath_print(common, ATH_DBG_FATAL,
1510 "cipher %u not supported\n", k->kv_type);
1511 return false;
1512 }
1513
1514 key0 = get_unaligned_le32(k->kv_val + 0);
1515 key1 = get_unaligned_le16(k->kv_val + 4);
1516 key2 = get_unaligned_le32(k->kv_val + 6);
1517 key3 = get_unaligned_le16(k->kv_val + 10);
1518 key4 = get_unaligned_le32(k->kv_val + 12);
1519 if (k->kv_len <= WLAN_KEY_LEN_WEP104)
1520 key4 &= 0xff;
1521
1522 /*
1523 * Note: Key cache registers access special memory area that requires
1524 * two 32-bit writes to actually update the values in the internal
1525 * memory. Consequently, the exact order and pairs used here must be
1526 * maintained.
1527 */
1528
1529 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
1530 u16 micentry = entry + 64;
1531
1532 /*
1533 * Write inverted key[47:0] first to avoid Michael MIC errors
1534 * on frames that could be sent or received at the same time.
1535 * The correct key will be written in the end once everything
1536 * else is ready.
1537 */
1538 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
1539 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
1540
1541 /* Write key[95:48] */
1542 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
1543 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
1544
1545 /* Write key[127:96] and key type */
1546 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
1547 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
1548
1549 /* Write MAC address for the entry */
1550 (void) ath9k_hw_keysetmac(ah, entry, mac);
1551
1552 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
1553 /*
1554 * TKIP uses two key cache entries:
1555 * Michael MIC TX/RX keys in the same key cache entry
1556 * (idx = main index + 64):
1557 * key0 [31:0] = RX key [31:0]
1558 * key1 [15:0] = TX key [31:16]
1559 * key1 [31:16] = reserved
1560 * key2 [31:0] = RX key [63:32]
1561 * key3 [15:0] = TX key [15:0]
1562 * key3 [31:16] = reserved
1563 * key4 [31:0] = TX key [63:32]
1564 */
1565 u32 mic0, mic1, mic2, mic3, mic4;
1566
1567 mic0 = get_unaligned_le32(k->kv_mic + 0);
1568 mic2 = get_unaligned_le32(k->kv_mic + 4);
1569 mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
1570 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
1571 mic4 = get_unaligned_le32(k->kv_txmic + 4);
1572
1573 /* Write RX[31:0] and TX[31:16] */
1574 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
1575 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
1576
1577 /* Write RX[63:32] and TX[15:0] */
1578 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
1579 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
1580
1581 /* Write TX[63:32] and keyType(reserved) */
1582 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
1583 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
1584 AR_KEYTABLE_TYPE_CLR);
1585
1586 } else {
1587 /*
1588 * TKIP uses four key cache entries (two for group
1589 * keys):
1590 * Michael MIC TX/RX keys are in different key cache
1591 * entries (idx = main index + 64 for TX and
1592 * main index + 32 + 96 for RX):
1593 * key0 [31:0] = TX/RX MIC key [31:0]
1594 * key1 [31:0] = reserved
1595 * key2 [31:0] = TX/RX MIC key [63:32]
1596 * key3 [31:0] = reserved
1597 * key4 [31:0] = reserved
1598 *
1599 * Upper layer code will call this function separately
1600 * for TX and RX keys when these registers offsets are
1601 * used.
1602 */
1603 u32 mic0, mic2;
1604
1605 mic0 = get_unaligned_le32(k->kv_mic + 0);
1606 mic2 = get_unaligned_le32(k->kv_mic + 4);
1607
1608 /* Write MIC key[31:0] */
1609 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
1610 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
1611
1612 /* Write MIC key[63:32] */
1613 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
1614 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
1615
1616 /* Write TX[63:32] and keyType(reserved) */
1617 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
1618 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
1619 AR_KEYTABLE_TYPE_CLR);
1620 }
1621
1622 /* MAC address registers are reserved for the MIC entry */
1623 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
1624 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
1625
1626 /*
1627 * Write the correct (un-inverted) key[47:0] last to enable
1628 * TKIP now that all other registers are set with correct
1629 * values.
1630 */
1631 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
1632 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
1633 } else {
1634 /* Write key[47:0] */
1635 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
1636 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
1637
1638 /* Write key[95:48] */
1639 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
1640 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
1641
1642 /* Write key[127:96] and key type */
1643 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
1644 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
1645
1646 /* Write MAC address for the entry */
1647 (void) ath9k_hw_keysetmac(ah, entry, mac);
1648 }
1649
1650 return true;
1651 }
1652 EXPORT_SYMBOL(ath9k_hw_set_keycache_entry);
1653
1654 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
1655 {
1656 if (entry < ah->caps.keycache_size) {
1657 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
1658 if (val & AR_KEYTABLE_VALID)
1659 return true;
1660 }
1661 return false;
1662 }
1663 EXPORT_SYMBOL(ath9k_hw_keyisvalid);
1664
1665 /******************************/
1666 /* Power Management (Chipset) */
1667 /******************************/
1668
1669 /*
1670 * Notify Power Mgt is disabled in self-generated frames.
1671 * If requested, force chip to sleep.
1672 */
1673 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
1674 {
1675 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1676 if (setChip) {
1677 /*
1678 * Clear the RTC force wake bit to allow the
1679 * mac to go to sleep.
1680 */
1681 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1682 AR_RTC_FORCE_WAKE_EN);
1683 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1684 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1685
1686 /* Shutdown chip. Active low */
1687 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah))
1688 REG_CLR_BIT(ah, (AR_RTC_RESET),
1689 AR_RTC_RESET_EN);
1690 }
1691 }
1692
1693 /*
1694 * Notify Power Management is enabled in self-generating
1695 * frames. If request, set power mode of chip to
1696 * auto/normal. Duration in units of 128us (1/8 TU).
1697 */
1698 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
1699 {
1700 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1701 if (setChip) {
1702 struct ath9k_hw_capabilities *pCap = &ah->caps;
1703
1704 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1705 /* Set WakeOnInterrupt bit; clear ForceWake bit */
1706 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1707 AR_RTC_FORCE_WAKE_ON_INT);
1708 } else {
1709 /*
1710 * Clear the RTC force wake bit to allow the
1711 * mac to go to sleep.
1712 */
1713 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1714 AR_RTC_FORCE_WAKE_EN);
1715 }
1716 }
1717 }
1718
1719 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
1720 {
1721 u32 val;
1722 int i;
1723
1724 if (setChip) {
1725 if ((REG_READ(ah, AR_RTC_STATUS) &
1726 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
1727 if (ath9k_hw_set_reset_reg(ah,
1728 ATH9K_RESET_POWER_ON) != true) {
1729 return false;
1730 }
1731 if (!AR_SREV_9300_20_OR_LATER(ah))
1732 ath9k_hw_init_pll(ah, NULL);
1733 }
1734 if (AR_SREV_9100(ah))
1735 REG_SET_BIT(ah, AR_RTC_RESET,
1736 AR_RTC_RESET_EN);
1737
1738 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1739 AR_RTC_FORCE_WAKE_EN);
1740 udelay(50);
1741
1742 for (i = POWER_UP_TIME / 50; i > 0; i--) {
1743 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
1744 if (val == AR_RTC_STATUS_ON)
1745 break;
1746 udelay(50);
1747 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1748 AR_RTC_FORCE_WAKE_EN);
1749 }
1750 if (i == 0) {
1751 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1752 "Failed to wakeup in %uus\n",
1753 POWER_UP_TIME / 20);
1754 return false;
1755 }
1756 }
1757
1758 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1759
1760 return true;
1761 }
1762
1763 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
1764 {
1765 struct ath_common *common = ath9k_hw_common(ah);
1766 int status = true, setChip = true;
1767 static const char *modes[] = {
1768 "AWAKE",
1769 "FULL-SLEEP",
1770 "NETWORK SLEEP",
1771 "UNDEFINED"
1772 };
1773
1774 if (ah->power_mode == mode)
1775 return status;
1776
1777 ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
1778 modes[ah->power_mode], modes[mode]);
1779
1780 switch (mode) {
1781 case ATH9K_PM_AWAKE:
1782 status = ath9k_hw_set_power_awake(ah, setChip);
1783 break;
1784 case ATH9K_PM_FULL_SLEEP:
1785 ath9k_set_power_sleep(ah, setChip);
1786 ah->chip_fullsleep = true;
1787 break;
1788 case ATH9K_PM_NETWORK_SLEEP:
1789 ath9k_set_power_network_sleep(ah, setChip);
1790 break;
1791 default:
1792 ath_print(common, ATH_DBG_FATAL,
1793 "Unknown power mode %u\n", mode);
1794 return false;
1795 }
1796 ah->power_mode = mode;
1797
1798 return status;
1799 }
1800 EXPORT_SYMBOL(ath9k_hw_setpower);
1801
1802 /*******************/
1803 /* Beacon Handling */
1804 /*******************/
1805
1806 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
1807 {
1808 int flags = 0;
1809
1810 ah->beacon_interval = beacon_period;
1811
1812 switch (ah->opmode) {
1813 case NL80211_IFTYPE_STATION:
1814 case NL80211_IFTYPE_MONITOR:
1815 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
1816 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
1817 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
1818 flags |= AR_TBTT_TIMER_EN;
1819 break;
1820 case NL80211_IFTYPE_ADHOC:
1821 case NL80211_IFTYPE_MESH_POINT:
1822 REG_SET_BIT(ah, AR_TXCFG,
1823 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
1824 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
1825 TU_TO_USEC(next_beacon +
1826 (ah->atim_window ? ah->
1827 atim_window : 1)));
1828 flags |= AR_NDP_TIMER_EN;
1829 case NL80211_IFTYPE_AP:
1830 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
1831 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
1832 TU_TO_USEC(next_beacon -
1833 ah->config.
1834 dma_beacon_response_time));
1835 REG_WRITE(ah, AR_NEXT_SWBA,
1836 TU_TO_USEC(next_beacon -
1837 ah->config.
1838 sw_beacon_response_time));
1839 flags |=
1840 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
1841 break;
1842 default:
1843 ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
1844 "%s: unsupported opmode: %d\n",
1845 __func__, ah->opmode);
1846 return;
1847 break;
1848 }
1849
1850 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
1851 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
1852 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
1853 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
1854
1855 beacon_period &= ~ATH9K_BEACON_ENA;
1856 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
1857 ath9k_hw_reset_tsf(ah);
1858 }
1859
1860 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
1861 }
1862 EXPORT_SYMBOL(ath9k_hw_beaconinit);
1863
1864 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
1865 const struct ath9k_beacon_state *bs)
1866 {
1867 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
1868 struct ath9k_hw_capabilities *pCap = &ah->caps;
1869 struct ath_common *common = ath9k_hw_common(ah);
1870
1871 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
1872
1873 REG_WRITE(ah, AR_BEACON_PERIOD,
1874 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1875 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
1876 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1877
1878 REG_RMW_FIELD(ah, AR_RSSI_THR,
1879 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
1880
1881 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
1882
1883 if (bs->bs_sleepduration > beaconintval)
1884 beaconintval = bs->bs_sleepduration;
1885
1886 dtimperiod = bs->bs_dtimperiod;
1887 if (bs->bs_sleepduration > dtimperiod)
1888 dtimperiod = bs->bs_sleepduration;
1889
1890 if (beaconintval == dtimperiod)
1891 nextTbtt = bs->bs_nextdtim;
1892 else
1893 nextTbtt = bs->bs_nexttbtt;
1894
1895 ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
1896 ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
1897 ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
1898 ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
1899
1900 REG_WRITE(ah, AR_NEXT_DTIM,
1901 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
1902 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
1903
1904 REG_WRITE(ah, AR_SLEEP1,
1905 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
1906 | AR_SLEEP1_ASSUME_DTIM);
1907
1908 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
1909 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
1910 else
1911 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
1912
1913 REG_WRITE(ah, AR_SLEEP2,
1914 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
1915
1916 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
1917 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
1918
1919 REG_SET_BIT(ah, AR_TIMER_MODE,
1920 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
1921 AR_DTIM_TIMER_EN);
1922
1923 /* TSF Out of Range Threshold */
1924 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
1925 }
1926 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
1927
1928 /*******************/
1929 /* HW Capabilities */
1930 /*******************/
1931
1932 int ath9k_hw_fill_cap_info(struct ath_hw *ah)
1933 {
1934 struct ath9k_hw_capabilities *pCap = &ah->caps;
1935 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1936 struct ath_common *common = ath9k_hw_common(ah);
1937 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
1938
1939 u16 capField = 0, eeval;
1940
1941 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
1942 regulatory->current_rd = eeval;
1943
1944 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
1945 if (AR_SREV_9285_10_OR_LATER(ah))
1946 eeval |= AR9285_RDEXT_DEFAULT;
1947 regulatory->current_rd_ext = eeval;
1948
1949 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
1950
1951 if (ah->opmode != NL80211_IFTYPE_AP &&
1952 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
1953 if (regulatory->current_rd == 0x64 ||
1954 regulatory->current_rd == 0x65)
1955 regulatory->current_rd += 5;
1956 else if (regulatory->current_rd == 0x41)
1957 regulatory->current_rd = 0x43;
1958 ath_print(common, ATH_DBG_REGULATORY,
1959 "regdomain mapped to 0x%x\n", regulatory->current_rd);
1960 }
1961
1962 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
1963 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
1964 ath_print(common, ATH_DBG_FATAL,
1965 "no band has been marked as supported in EEPROM.\n");
1966 return -EINVAL;
1967 }
1968
1969 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
1970
1971 if (eeval & AR5416_OPFLAGS_11A) {
1972 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
1973 if (ah->config.ht_enable) {
1974 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
1975 set_bit(ATH9K_MODE_11NA_HT20,
1976 pCap->wireless_modes);
1977 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
1978 set_bit(ATH9K_MODE_11NA_HT40PLUS,
1979 pCap->wireless_modes);
1980 set_bit(ATH9K_MODE_11NA_HT40MINUS,
1981 pCap->wireless_modes);
1982 }
1983 }
1984 }
1985
1986 if (eeval & AR5416_OPFLAGS_11G) {
1987 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
1988 if (ah->config.ht_enable) {
1989 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
1990 set_bit(ATH9K_MODE_11NG_HT20,
1991 pCap->wireless_modes);
1992 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
1993 set_bit(ATH9K_MODE_11NG_HT40PLUS,
1994 pCap->wireless_modes);
1995 set_bit(ATH9K_MODE_11NG_HT40MINUS,
1996 pCap->wireless_modes);
1997 }
1998 }
1999 }
2000
2001 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
2002 /*
2003 * For AR9271 we will temporarilly uses the rx chainmax as read from
2004 * the EEPROM.
2005 */
2006 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
2007 !(eeval & AR5416_OPFLAGS_11A) &&
2008 !(AR_SREV_9271(ah)))
2009 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
2010 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
2011 else
2012 /* Use rx_chainmask from EEPROM. */
2013 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
2014
2015 if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
2016 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
2017
2018 pCap->low_2ghz_chan = 2312;
2019 pCap->high_2ghz_chan = 2732;
2020
2021 pCap->low_5ghz_chan = 4920;
2022 pCap->high_5ghz_chan = 6100;
2023
2024 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
2025 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
2026 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
2027
2028 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
2029 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
2030 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
2031
2032 if (ah->config.ht_enable)
2033 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2034 else
2035 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
2036
2037 pCap->hw_caps |= ATH9K_HW_CAP_GTT;
2038 pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
2039 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
2040 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
2041
2042 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
2043 pCap->total_queues =
2044 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
2045 else
2046 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
2047
2048 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
2049 pCap->keycache_size =
2050 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
2051 else
2052 pCap->keycache_size = AR_KEYTABLE_SIZE;
2053
2054 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
2055
2056 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
2057 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1;
2058 else
2059 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
2060
2061 if (AR_SREV_9271(ah))
2062 pCap->num_gpio_pins = AR9271_NUM_GPIO;
2063 else if (AR_SREV_9285_10_OR_LATER(ah))
2064 pCap->num_gpio_pins = AR9285_NUM_GPIO;
2065 else if (AR_SREV_9280_10_OR_LATER(ah))
2066 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2067 else
2068 pCap->num_gpio_pins = AR_NUM_GPIO;
2069
2070 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
2071 pCap->hw_caps |= ATH9K_HW_CAP_CST;
2072 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
2073 } else {
2074 pCap->rts_aggr_limit = (8 * 1024);
2075 }
2076
2077 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
2078
2079 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2080 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2081 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2082 ah->rfkill_gpio =
2083 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2084 ah->rfkill_polarity =
2085 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
2086
2087 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
2088 }
2089 #endif
2090 if (AR_SREV_9271(ah))
2091 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2092 else
2093 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
2094
2095 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
2096 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2097 else
2098 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
2099
2100 if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
2101 pCap->reg_cap =
2102 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
2103 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
2104 AR_EEPROM_EEREGCAP_EN_KK_U2 |
2105 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
2106 } else {
2107 pCap->reg_cap =
2108 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
2109 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
2110 }
2111
2112 /* Advertise midband for AR5416 with FCC midband set in eeprom */
2113 if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
2114 AR_SREV_5416(ah))
2115 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
2116
2117 pCap->num_antcfg_5ghz =
2118 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
2119 pCap->num_antcfg_2ghz =
2120 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
2121
2122 if (AR_SREV_9280_10_OR_LATER(ah) &&
2123 ath9k_hw_btcoex_supported(ah)) {
2124 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
2125 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
2126
2127 if (AR_SREV_9285(ah)) {
2128 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
2129 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
2130 } else {
2131 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
2132 }
2133 } else {
2134 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
2135 }
2136
2137 if (AR_SREV_9300_20_OR_LATER(ah)) {
2138 pCap->hw_caps |= ATH9K_HW_CAP_EDMA;
2139 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2140 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2141 pCap->rx_status_len = sizeof(struct ar9003_rxs);
2142 pCap->tx_desc_len = sizeof(struct ar9003_txc);
2143 } else {
2144 pCap->tx_desc_len = sizeof(struct ath_desc);
2145 }
2146
2147 return 0;
2148 }
2149
2150 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
2151 u32 capability, u32 *result)
2152 {
2153 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2154 switch (type) {
2155 case ATH9K_CAP_CIPHER:
2156 switch (capability) {
2157 case ATH9K_CIPHER_AES_CCM:
2158 case ATH9K_CIPHER_AES_OCB:
2159 case ATH9K_CIPHER_TKIP:
2160 case ATH9K_CIPHER_WEP:
2161 case ATH9K_CIPHER_MIC:
2162 case ATH9K_CIPHER_CLR:
2163 return true;
2164 default:
2165 return false;
2166 }
2167 case ATH9K_CAP_TKIP_MIC:
2168 switch (capability) {
2169 case 0:
2170 return true;
2171 case 1:
2172 return (ah->sta_id1_defaults &
2173 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
2174 false;
2175 }
2176 case ATH9K_CAP_TKIP_SPLIT:
2177 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
2178 false : true;
2179 case ATH9K_CAP_MCAST_KEYSRCH:
2180 switch (capability) {
2181 case 0:
2182 return true;
2183 case 1:
2184 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
2185 return false;
2186 } else {
2187 return (ah->sta_id1_defaults &
2188 AR_STA_ID1_MCAST_KSRCH) ? true :
2189 false;
2190 }
2191 }
2192 return false;
2193 case ATH9K_CAP_TXPOW:
2194 switch (capability) {
2195 case 0:
2196 return 0;
2197 case 1:
2198 *result = regulatory->power_limit;
2199 return 0;
2200 case 2:
2201 *result = regulatory->max_power_level;
2202 return 0;
2203 case 3:
2204 *result = regulatory->tp_scale;
2205 return 0;
2206 }
2207 return false;
2208 case ATH9K_CAP_DS:
2209 return (AR_SREV_9280_20_OR_LATER(ah) &&
2210 (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
2211 ? false : true;
2212 default:
2213 return false;
2214 }
2215 }
2216 EXPORT_SYMBOL(ath9k_hw_getcapability);
2217
2218 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
2219 u32 capability, u32 setting, int *status)
2220 {
2221 switch (type) {
2222 case ATH9K_CAP_TKIP_MIC:
2223 if (setting)
2224 ah->sta_id1_defaults |=
2225 AR_STA_ID1_CRPT_MIC_ENABLE;
2226 else
2227 ah->sta_id1_defaults &=
2228 ~AR_STA_ID1_CRPT_MIC_ENABLE;
2229 return true;
2230 case ATH9K_CAP_MCAST_KEYSRCH:
2231 if (setting)
2232 ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
2233 else
2234 ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
2235 return true;
2236 default:
2237 return false;
2238 }
2239 }
2240 EXPORT_SYMBOL(ath9k_hw_setcapability);
2241
2242 /****************************/
2243 /* GPIO / RFKILL / Antennae */
2244 /****************************/
2245
2246 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
2247 u32 gpio, u32 type)
2248 {
2249 int addr;
2250 u32 gpio_shift, tmp;
2251
2252 if (gpio > 11)
2253 addr = AR_GPIO_OUTPUT_MUX3;
2254 else if (gpio > 5)
2255 addr = AR_GPIO_OUTPUT_MUX2;
2256 else
2257 addr = AR_GPIO_OUTPUT_MUX1;
2258
2259 gpio_shift = (gpio % 6) * 5;
2260
2261 if (AR_SREV_9280_20_OR_LATER(ah)
2262 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2263 REG_RMW(ah, addr, (type << gpio_shift),
2264 (0x1f << gpio_shift));
2265 } else {
2266 tmp = REG_READ(ah, addr);
2267 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2268 tmp &= ~(0x1f << gpio_shift);
2269 tmp |= (type << gpio_shift);
2270 REG_WRITE(ah, addr, tmp);
2271 }
2272 }
2273
2274 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
2275 {
2276 u32 gpio_shift;
2277
2278 BUG_ON(gpio >= ah->caps.num_gpio_pins);
2279
2280 gpio_shift = gpio << 1;
2281
2282 REG_RMW(ah,
2283 AR_GPIO_OE_OUT,
2284 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2285 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2286 }
2287 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
2288
2289 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
2290 {
2291 #define MS_REG_READ(x, y) \
2292 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2293
2294 if (gpio >= ah->caps.num_gpio_pins)
2295 return 0xffffffff;
2296
2297 if (AR_SREV_9300_20_OR_LATER(ah))
2298 return MS_REG_READ(AR9300, gpio) != 0;
2299 else if (AR_SREV_9271(ah))
2300 return MS_REG_READ(AR9271, gpio) != 0;
2301 else if (AR_SREV_9287_10_OR_LATER(ah))
2302 return MS_REG_READ(AR9287, gpio) != 0;
2303 else if (AR_SREV_9285_10_OR_LATER(ah))
2304 return MS_REG_READ(AR9285, gpio) != 0;
2305 else if (AR_SREV_9280_10_OR_LATER(ah))
2306 return MS_REG_READ(AR928X, gpio) != 0;
2307 else
2308 return MS_REG_READ(AR, gpio) != 0;
2309 }
2310 EXPORT_SYMBOL(ath9k_hw_gpio_get);
2311
2312 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
2313 u32 ah_signal_type)
2314 {
2315 u32 gpio_shift;
2316
2317 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
2318
2319 gpio_shift = 2 * gpio;
2320
2321 REG_RMW(ah,
2322 AR_GPIO_OE_OUT,
2323 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2324 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2325 }
2326 EXPORT_SYMBOL(ath9k_hw_cfg_output);
2327
2328 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
2329 {
2330 if (AR_SREV_9271(ah))
2331 val = ~val;
2332
2333 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2334 AR_GPIO_BIT(gpio));
2335 }
2336 EXPORT_SYMBOL(ath9k_hw_set_gpio);
2337
2338 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
2339 {
2340 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
2341 }
2342 EXPORT_SYMBOL(ath9k_hw_getdefantenna);
2343
2344 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
2345 {
2346 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
2347 }
2348 EXPORT_SYMBOL(ath9k_hw_setantenna);
2349
2350 /*********************/
2351 /* General Operation */
2352 /*********************/
2353
2354 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
2355 {
2356 u32 bits = REG_READ(ah, AR_RX_FILTER);
2357 u32 phybits = REG_READ(ah, AR_PHY_ERR);
2358
2359 if (phybits & AR_PHY_ERR_RADAR)
2360 bits |= ATH9K_RX_FILTER_PHYRADAR;
2361 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2362 bits |= ATH9K_RX_FILTER_PHYERR;
2363
2364 return bits;
2365 }
2366 EXPORT_SYMBOL(ath9k_hw_getrxfilter);
2367
2368 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
2369 {
2370 u32 phybits;
2371
2372 REG_WRITE(ah, AR_RX_FILTER, bits);
2373
2374 phybits = 0;
2375 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2376 phybits |= AR_PHY_ERR_RADAR;
2377 if (bits & ATH9K_RX_FILTER_PHYERR)
2378 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2379 REG_WRITE(ah, AR_PHY_ERR, phybits);
2380
2381 if (phybits)
2382 REG_WRITE(ah, AR_RXCFG,
2383 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
2384 else
2385 REG_WRITE(ah, AR_RXCFG,
2386 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
2387 }
2388 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
2389
2390 bool ath9k_hw_phy_disable(struct ath_hw *ah)
2391 {
2392 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2393 return false;
2394
2395 ath9k_hw_init_pll(ah, NULL);
2396 return true;
2397 }
2398 EXPORT_SYMBOL(ath9k_hw_phy_disable);
2399
2400 bool ath9k_hw_disable(struct ath_hw *ah)
2401 {
2402 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2403 return false;
2404
2405 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2406 return false;
2407
2408 ath9k_hw_init_pll(ah, NULL);
2409 return true;
2410 }
2411 EXPORT_SYMBOL(ath9k_hw_disable);
2412
2413 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
2414 {
2415 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2416 struct ath9k_channel *chan = ah->curchan;
2417 struct ieee80211_channel *channel = chan->chan;
2418
2419 regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
2420
2421 ah->eep_ops->set_txpower(ah, chan,
2422 ath9k_regd_get_ctl(regulatory, chan),
2423 channel->max_antenna_gain * 2,
2424 channel->max_power * 2,
2425 min((u32) MAX_RATE_POWER,
2426 (u32) regulatory->power_limit));
2427 }
2428 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
2429
2430 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
2431 {
2432 memcpy(ath9k_hw_common(ah)->macaddr, mac, ETH_ALEN);
2433 }
2434 EXPORT_SYMBOL(ath9k_hw_setmac);
2435
2436 void ath9k_hw_setopmode(struct ath_hw *ah)
2437 {
2438 ath9k_hw_set_operating_mode(ah, ah->opmode);
2439 }
2440 EXPORT_SYMBOL(ath9k_hw_setopmode);
2441
2442 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
2443 {
2444 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2445 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
2446 }
2447 EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
2448
2449 void ath9k_hw_write_associd(struct ath_hw *ah)
2450 {
2451 struct ath_common *common = ath9k_hw_common(ah);
2452
2453 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2454 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2455 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2456 }
2457 EXPORT_SYMBOL(ath9k_hw_write_associd);
2458
2459 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
2460 {
2461 u64 tsf;
2462
2463 tsf = REG_READ(ah, AR_TSF_U32);
2464 tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
2465
2466 return tsf;
2467 }
2468 EXPORT_SYMBOL(ath9k_hw_gettsf64);
2469
2470 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
2471 {
2472 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
2473 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
2474 }
2475 EXPORT_SYMBOL(ath9k_hw_settsf64);
2476
2477 void ath9k_hw_reset_tsf(struct ath_hw *ah)
2478 {
2479 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2480 AH_TSF_WRITE_TIMEOUT))
2481 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
2482 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
2483
2484 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2485 }
2486 EXPORT_SYMBOL(ath9k_hw_reset_tsf);
2487
2488 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
2489 {
2490 if (setting)
2491 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
2492 else
2493 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
2494 }
2495 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
2496
2497 /*
2498 * Extend 15-bit time stamp from rx descriptor to
2499 * a full 64-bit TSF using the current h/w TSF.
2500 */
2501 u64 ath9k_hw_extend_tsf(struct ath_hw *ah, u32 rstamp)
2502 {
2503 u64 tsf;
2504
2505 tsf = ath9k_hw_gettsf64(ah);
2506 if ((tsf & 0x7fff) < rstamp)
2507 tsf -= 0x8000;
2508 return (tsf & ~0x7fff) | rstamp;
2509 }
2510 EXPORT_SYMBOL(ath9k_hw_extend_tsf);
2511
2512 void ath9k_hw_set11nmac2040(struct ath_hw *ah)
2513 {
2514 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
2515 u32 macmode;
2516
2517 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
2518 macmode = AR_2040_JOINED_RX_CLEAR;
2519 else
2520 macmode = 0;
2521
2522 REG_WRITE(ah, AR_2040_MODE, macmode);
2523 }
2524
2525 /* HW Generic timers configuration */
2526
2527 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2528 {
2529 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2530 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2531 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2532 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2533 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2534 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2535 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2536 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2537 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2538 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2539 AR_NDP2_TIMER_MODE, 0x0002},
2540 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2541 AR_NDP2_TIMER_MODE, 0x0004},
2542 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2543 AR_NDP2_TIMER_MODE, 0x0008},
2544 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2545 AR_NDP2_TIMER_MODE, 0x0010},
2546 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2547 AR_NDP2_TIMER_MODE, 0x0020},
2548 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2549 AR_NDP2_TIMER_MODE, 0x0040},
2550 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2551 AR_NDP2_TIMER_MODE, 0x0080}
2552 };
2553
2554 /* HW generic timer primitives */
2555
2556 /* compute and clear index of rightmost 1 */
2557 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
2558 {
2559 u32 b;
2560
2561 b = *mask;
2562 b &= (0-b);
2563 *mask &= ~b;
2564 b *= debruijn32;
2565 b >>= 27;
2566
2567 return timer_table->gen_timer_index[b];
2568 }
2569
2570 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
2571 {
2572 return REG_READ(ah, AR_TSF_L32);
2573 }
2574 EXPORT_SYMBOL(ath9k_hw_gettsf32);
2575
2576 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2577 void (*trigger)(void *),
2578 void (*overflow)(void *),
2579 void *arg,
2580 u8 timer_index)
2581 {
2582 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2583 struct ath_gen_timer *timer;
2584
2585 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
2586
2587 if (timer == NULL) {
2588 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2589 "Failed to allocate memory"
2590 "for hw timer[%d]\n", timer_index);
2591 return NULL;
2592 }
2593
2594 /* allocate a hardware generic timer slot */
2595 timer_table->timers[timer_index] = timer;
2596 timer->index = timer_index;
2597 timer->trigger = trigger;
2598 timer->overflow = overflow;
2599 timer->arg = arg;
2600
2601 return timer;
2602 }
2603 EXPORT_SYMBOL(ath_gen_timer_alloc);
2604
2605 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2606 struct ath_gen_timer *timer,
2607 u32 timer_next,
2608 u32 timer_period)
2609 {
2610 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2611 u32 tsf;
2612
2613 BUG_ON(!timer_period);
2614
2615 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
2616
2617 tsf = ath9k_hw_gettsf32(ah);
2618
2619 ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
2620 "curent tsf %x period %x"
2621 "timer_next %x\n", tsf, timer_period, timer_next);
2622
2623 /*
2624 * Pull timer_next forward if the current TSF already passed it
2625 * because of software latency
2626 */
2627 if (timer_next < tsf)
2628 timer_next = tsf + timer_period;
2629
2630 /*
2631 * Program generic timer registers
2632 */
2633 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
2634 timer_next);
2635 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
2636 timer_period);
2637 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2638 gen_tmr_configuration[timer->index].mode_mask);
2639
2640 /* Enable both trigger and thresh interrupt masks */
2641 REG_SET_BIT(ah, AR_IMR_S5,
2642 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2643 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2644 }
2645 EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
2646
2647 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
2648 {
2649 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2650
2651 if ((timer->index < AR_FIRST_NDP_TIMER) ||
2652 (timer->index >= ATH_MAX_GEN_TIMER)) {
2653 return;
2654 }
2655
2656 /* Clear generic timer enable bits. */
2657 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2658 gen_tmr_configuration[timer->index].mode_mask);
2659
2660 /* Disable both trigger and thresh interrupt masks */
2661 REG_CLR_BIT(ah, AR_IMR_S5,
2662 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2663 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2664
2665 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
2666 }
2667 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
2668
2669 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
2670 {
2671 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2672
2673 /* free the hardware generic timer slot */
2674 timer_table->timers[timer->index] = NULL;
2675 kfree(timer);
2676 }
2677 EXPORT_SYMBOL(ath_gen_timer_free);
2678
2679 /*
2680 * Generic Timer Interrupts handling
2681 */
2682 void ath_gen_timer_isr(struct ath_hw *ah)
2683 {
2684 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2685 struct ath_gen_timer *timer;
2686 struct ath_common *common = ath9k_hw_common(ah);
2687 u32 trigger_mask, thresh_mask, index;
2688
2689 /* get hardware generic timer interrupt status */
2690 trigger_mask = ah->intr_gen_timer_trigger;
2691 thresh_mask = ah->intr_gen_timer_thresh;
2692 trigger_mask &= timer_table->timer_mask.val;
2693 thresh_mask &= timer_table->timer_mask.val;
2694
2695 trigger_mask &= ~thresh_mask;
2696
2697 while (thresh_mask) {
2698 index = rightmost_index(timer_table, &thresh_mask);
2699 timer = timer_table->timers[index];
2700 BUG_ON(!timer);
2701 ath_print(common, ATH_DBG_HWTIMER,
2702 "TSF overflow for Gen timer %d\n", index);
2703 timer->overflow(timer->arg);
2704 }
2705
2706 while (trigger_mask) {
2707 index = rightmost_index(timer_table, &trigger_mask);
2708 timer = timer_table->timers[index];
2709 BUG_ON(!timer);
2710 ath_print(common, ATH_DBG_HWTIMER,
2711 "Gen timer[%d] trigger\n", index);
2712 timer->trigger(timer->arg);
2713 }
2714 }
2715 EXPORT_SYMBOL(ath_gen_timer_isr);
2716
2717 /********/
2718 /* HTC */
2719 /********/
2720
2721 void ath9k_hw_htc_resetinit(struct ath_hw *ah)
2722 {
2723 ah->htc_reset_init = true;
2724 }
2725 EXPORT_SYMBOL(ath9k_hw_htc_resetinit);
2726
2727 static struct {
2728 u32 version;
2729 const char * name;
2730 } ath_mac_bb_names[] = {
2731 /* Devices with external radios */
2732 { AR_SREV_VERSION_5416_PCI, "5416" },
2733 { AR_SREV_VERSION_5416_PCIE, "5418" },
2734 { AR_SREV_VERSION_9100, "9100" },
2735 { AR_SREV_VERSION_9160, "9160" },
2736 /* Single-chip solutions */
2737 { AR_SREV_VERSION_9280, "9280" },
2738 { AR_SREV_VERSION_9285, "9285" },
2739 { AR_SREV_VERSION_9287, "9287" },
2740 { AR_SREV_VERSION_9271, "9271" },
2741 };
2742
2743 /* For devices with external radios */
2744 static struct {
2745 u16 version;
2746 const char * name;
2747 } ath_rf_names[] = {
2748 { 0, "5133" },
2749 { AR_RAD5133_SREV_MAJOR, "5133" },
2750 { AR_RAD5122_SREV_MAJOR, "5122" },
2751 { AR_RAD2133_SREV_MAJOR, "2133" },
2752 { AR_RAD2122_SREV_MAJOR, "2122" }
2753 };
2754
2755 /*
2756 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2757 */
2758 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
2759 {
2760 int i;
2761
2762 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2763 if (ath_mac_bb_names[i].version == mac_bb_version) {
2764 return ath_mac_bb_names[i].name;
2765 }
2766 }
2767
2768 return "????";
2769 }
2770
2771 /*
2772 * Return the RF name. "????" is returned if the RF is unknown.
2773 * Used for devices with external radios.
2774 */
2775 static const char *ath9k_hw_rf_name(u16 rf_version)
2776 {
2777 int i;
2778
2779 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2780 if (ath_rf_names[i].version == rf_version) {
2781 return ath_rf_names[i].name;
2782 }
2783 }
2784
2785 return "????";
2786 }
2787
2788 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
2789 {
2790 int used;
2791
2792 /* chipsets >= AR9280 are single-chip */
2793 if (AR_SREV_9280_10_OR_LATER(ah)) {
2794 used = snprintf(hw_name, len,
2795 "Atheros AR%s Rev:%x",
2796 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2797 ah->hw_version.macRev);
2798 }
2799 else {
2800 used = snprintf(hw_name, len,
2801 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
2802 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2803 ah->hw_version.macRev,
2804 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
2805 AR_RADIO_SREV_MAJOR)),
2806 ah->hw_version.phyRev);
2807 }
2808
2809 hw_name[used] = '\0';
2810 }
2811 EXPORT_SYMBOL(ath9k_hw_name);
Linux kernel - Deliverables
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