2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include <linux/slab.h>
19 #include <linux/module.h>
20 #include <asm/unaligned.h>
25 #include "ar9003_mac.h"
26 #include "ar9003_mci.h"
27 #include "ar9003_phy.h"
31 static bool ath9k_hw_set_reset_reg(struct ath_hw
*ah
, u32 type
);
33 MODULE_AUTHOR("Atheros Communications");
34 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
35 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
36 MODULE_LICENSE("Dual BSD/GPL");
38 static int __init
ath9k_init(void)
42 module_init(ath9k_init
);
44 static void __exit
ath9k_exit(void)
48 module_exit(ath9k_exit
);
50 /* Private hardware callbacks */
52 static void ath9k_hw_init_cal_settings(struct ath_hw
*ah
)
54 ath9k_hw_private_ops(ah
)->init_cal_settings(ah
);
57 static u32
ath9k_hw_compute_pll_control(struct ath_hw
*ah
,
58 struct ath9k_channel
*chan
)
60 return ath9k_hw_private_ops(ah
)->compute_pll_control(ah
, chan
);
63 static void ath9k_hw_init_mode_gain_regs(struct ath_hw
*ah
)
65 if (!ath9k_hw_private_ops(ah
)->init_mode_gain_regs
)
68 ath9k_hw_private_ops(ah
)->init_mode_gain_regs(ah
);
71 static void ath9k_hw_ani_cache_ini_regs(struct ath_hw
*ah
)
73 /* You will not have this callback if using the old ANI */
74 if (!ath9k_hw_private_ops(ah
)->ani_cache_ini_regs
)
77 ath9k_hw_private_ops(ah
)->ani_cache_ini_regs(ah
);
80 /********************/
81 /* Helper Functions */
82 /********************/
84 #ifdef CONFIG_ATH9K_DEBUGFS
86 void ath9k_debug_sync_cause(struct ath_common
*common
, u32 sync_cause
)
88 struct ath_softc
*sc
= common
->priv
;
90 sc
->debug
.stats
.istats
.sync_cause_all
++;
91 if (sync_cause
& AR_INTR_SYNC_RTC_IRQ
)
92 sc
->debug
.stats
.istats
.sync_rtc_irq
++;
93 if (sync_cause
& AR_INTR_SYNC_MAC_IRQ
)
94 sc
->debug
.stats
.istats
.sync_mac_irq
++;
95 if (sync_cause
& AR_INTR_SYNC_EEPROM_ILLEGAL_ACCESS
)
96 sc
->debug
.stats
.istats
.eeprom_illegal_access
++;
97 if (sync_cause
& AR_INTR_SYNC_APB_TIMEOUT
)
98 sc
->debug
.stats
.istats
.apb_timeout
++;
99 if (sync_cause
& AR_INTR_SYNC_PCI_MODE_CONFLICT
)
100 sc
->debug
.stats
.istats
.pci_mode_conflict
++;
101 if (sync_cause
& AR_INTR_SYNC_HOST1_FATAL
)
102 sc
->debug
.stats
.istats
.host1_fatal
++;
103 if (sync_cause
& AR_INTR_SYNC_HOST1_PERR
)
104 sc
->debug
.stats
.istats
.host1_perr
++;
105 if (sync_cause
& AR_INTR_SYNC_TRCV_FIFO_PERR
)
106 sc
->debug
.stats
.istats
.trcv_fifo_perr
++;
107 if (sync_cause
& AR_INTR_SYNC_RADM_CPL_EP
)
108 sc
->debug
.stats
.istats
.radm_cpl_ep
++;
109 if (sync_cause
& AR_INTR_SYNC_RADM_CPL_DLLP_ABORT
)
110 sc
->debug
.stats
.istats
.radm_cpl_dllp_abort
++;
111 if (sync_cause
& AR_INTR_SYNC_RADM_CPL_TLP_ABORT
)
112 sc
->debug
.stats
.istats
.radm_cpl_tlp_abort
++;
113 if (sync_cause
& AR_INTR_SYNC_RADM_CPL_ECRC_ERR
)
114 sc
->debug
.stats
.istats
.radm_cpl_ecrc_err
++;
115 if (sync_cause
& AR_INTR_SYNC_RADM_CPL_TIMEOUT
)
116 sc
->debug
.stats
.istats
.radm_cpl_timeout
++;
117 if (sync_cause
& AR_INTR_SYNC_LOCAL_TIMEOUT
)
118 sc
->debug
.stats
.istats
.local_timeout
++;
119 if (sync_cause
& AR_INTR_SYNC_PM_ACCESS
)
120 sc
->debug
.stats
.istats
.pm_access
++;
121 if (sync_cause
& AR_INTR_SYNC_MAC_AWAKE
)
122 sc
->debug
.stats
.istats
.mac_awake
++;
123 if (sync_cause
& AR_INTR_SYNC_MAC_ASLEEP
)
124 sc
->debug
.stats
.istats
.mac_asleep
++;
125 if (sync_cause
& AR_INTR_SYNC_MAC_SLEEP_ACCESS
)
126 sc
->debug
.stats
.istats
.mac_sleep_access
++;
131 static void ath9k_hw_set_clockrate(struct ath_hw
*ah
)
133 struct ath_common
*common
= ath9k_hw_common(ah
);
134 struct ath9k_channel
*chan
= ah
->curchan
;
135 unsigned int clockrate
;
137 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */
138 if (AR_SREV_9287(ah
) && AR_SREV_9287_13_OR_LATER(ah
))
140 else if (!chan
) /* should really check for CCK instead */
141 clockrate
= ATH9K_CLOCK_RATE_CCK
;
142 else if (IS_CHAN_2GHZ(chan
))
143 clockrate
= ATH9K_CLOCK_RATE_2GHZ_OFDM
;
144 else if (ah
->caps
.hw_caps
& ATH9K_HW_CAP_FASTCLOCK
)
145 clockrate
= ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM
;
147 clockrate
= ATH9K_CLOCK_RATE_5GHZ_OFDM
;
150 if (IS_CHAN_HT40(chan
))
152 if (IS_CHAN_HALF_RATE(chan
))
154 if (IS_CHAN_QUARTER_RATE(chan
))
158 common
->clockrate
= clockrate
;
161 static u32
ath9k_hw_mac_to_clks(struct ath_hw
*ah
, u32 usecs
)
163 struct ath_common
*common
= ath9k_hw_common(ah
);
165 return usecs
* common
->clockrate
;
168 bool ath9k_hw_wait(struct ath_hw
*ah
, u32 reg
, u32 mask
, u32 val
, u32 timeout
)
172 BUG_ON(timeout
< AH_TIME_QUANTUM
);
174 for (i
= 0; i
< (timeout
/ AH_TIME_QUANTUM
); i
++) {
175 if ((REG_READ(ah
, reg
) & mask
) == val
)
178 udelay(AH_TIME_QUANTUM
);
181 ath_dbg(ath9k_hw_common(ah
), ANY
,
182 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
183 timeout
, reg
, REG_READ(ah
, reg
), mask
, val
);
187 EXPORT_SYMBOL(ath9k_hw_wait
);
189 void ath9k_hw_synth_delay(struct ath_hw
*ah
, struct ath9k_channel
*chan
,
194 if (IS_CHAN_HALF_RATE(chan
))
196 else if (IS_CHAN_QUARTER_RATE(chan
))
199 udelay(hw_delay
+ BASE_ACTIVATE_DELAY
);
202 void ath9k_hw_write_array(struct ath_hw
*ah
, const struct ar5416IniArray
*array
,
203 int column
, unsigned int *writecnt
)
207 ENABLE_REGWRITE_BUFFER(ah
);
208 for (r
= 0; r
< array
->ia_rows
; r
++) {
209 REG_WRITE(ah
, INI_RA(array
, r
, 0),
210 INI_RA(array
, r
, column
));
213 REGWRITE_BUFFER_FLUSH(ah
);
216 u32
ath9k_hw_reverse_bits(u32 val
, u32 n
)
221 for (i
= 0, retval
= 0; i
< n
; i
++) {
222 retval
= (retval
<< 1) | (val
& 1);
228 u16
ath9k_hw_computetxtime(struct ath_hw
*ah
,
230 u32 frameLen
, u16 rateix
,
233 u32 bitsPerSymbol
, numBits
, numSymbols
, phyTime
, txTime
;
239 case WLAN_RC_PHY_CCK
:
240 phyTime
= CCK_PREAMBLE_BITS
+ CCK_PLCP_BITS
;
243 numBits
= frameLen
<< 3;
244 txTime
= CCK_SIFS_TIME
+ phyTime
+ ((numBits
* 1000) / kbps
);
246 case WLAN_RC_PHY_OFDM
:
247 if (ah
->curchan
&& IS_CHAN_QUARTER_RATE(ah
->curchan
)) {
248 bitsPerSymbol
= (kbps
* OFDM_SYMBOL_TIME_QUARTER
) / 1000;
249 numBits
= OFDM_PLCP_BITS
+ (frameLen
<< 3);
250 numSymbols
= DIV_ROUND_UP(numBits
, bitsPerSymbol
);
251 txTime
= OFDM_SIFS_TIME_QUARTER
252 + OFDM_PREAMBLE_TIME_QUARTER
253 + (numSymbols
* OFDM_SYMBOL_TIME_QUARTER
);
254 } else if (ah
->curchan
&&
255 IS_CHAN_HALF_RATE(ah
->curchan
)) {
256 bitsPerSymbol
= (kbps
* OFDM_SYMBOL_TIME_HALF
) / 1000;
257 numBits
= OFDM_PLCP_BITS
+ (frameLen
<< 3);
258 numSymbols
= DIV_ROUND_UP(numBits
, bitsPerSymbol
);
259 txTime
= OFDM_SIFS_TIME_HALF
+
260 OFDM_PREAMBLE_TIME_HALF
261 + (numSymbols
* OFDM_SYMBOL_TIME_HALF
);
263 bitsPerSymbol
= (kbps
* OFDM_SYMBOL_TIME
) / 1000;
264 numBits
= OFDM_PLCP_BITS
+ (frameLen
<< 3);
265 numSymbols
= DIV_ROUND_UP(numBits
, bitsPerSymbol
);
266 txTime
= OFDM_SIFS_TIME
+ OFDM_PREAMBLE_TIME
267 + (numSymbols
* OFDM_SYMBOL_TIME
);
271 ath_err(ath9k_hw_common(ah
),
272 "Unknown phy %u (rate ix %u)\n", phy
, rateix
);
279 EXPORT_SYMBOL(ath9k_hw_computetxtime
);
281 void ath9k_hw_get_channel_centers(struct ath_hw
*ah
,
282 struct ath9k_channel
*chan
,
283 struct chan_centers
*centers
)
287 if (!IS_CHAN_HT40(chan
)) {
288 centers
->ctl_center
= centers
->ext_center
=
289 centers
->synth_center
= chan
->channel
;
293 if (IS_CHAN_HT40PLUS(chan
)) {
294 centers
->synth_center
=
295 chan
->channel
+ HT40_CHANNEL_CENTER_SHIFT
;
298 centers
->synth_center
=
299 chan
->channel
- HT40_CHANNEL_CENTER_SHIFT
;
303 centers
->ctl_center
=
304 centers
->synth_center
- (extoff
* HT40_CHANNEL_CENTER_SHIFT
);
305 /* 25 MHz spacing is supported by hw but not on upper layers */
306 centers
->ext_center
=
307 centers
->synth_center
+ (extoff
* HT40_CHANNEL_CENTER_SHIFT
);
314 static void ath9k_hw_read_revisions(struct ath_hw
*ah
)
318 switch (ah
->hw_version
.devid
) {
319 case AR5416_AR9100_DEVID
:
320 ah
->hw_version
.macVersion
= AR_SREV_VERSION_9100
;
322 case AR9300_DEVID_AR9330
:
323 ah
->hw_version
.macVersion
= AR_SREV_VERSION_9330
;
324 if (ah
->get_mac_revision
) {
325 ah
->hw_version
.macRev
= ah
->get_mac_revision();
327 val
= REG_READ(ah
, AR_SREV
);
328 ah
->hw_version
.macRev
= MS(val
, AR_SREV_REVISION2
);
331 case AR9300_DEVID_AR9340
:
332 ah
->hw_version
.macVersion
= AR_SREV_VERSION_9340
;
333 val
= REG_READ(ah
, AR_SREV
);
334 ah
->hw_version
.macRev
= MS(val
, AR_SREV_REVISION2
);
336 case AR9300_DEVID_QCA955X
:
337 ah
->hw_version
.macVersion
= AR_SREV_VERSION_9550
;
341 val
= REG_READ(ah
, AR_SREV
) & AR_SREV_ID
;
344 val
= REG_READ(ah
, AR_SREV
);
345 ah
->hw_version
.macVersion
=
346 (val
& AR_SREV_VERSION2
) >> AR_SREV_TYPE2_S
;
347 ah
->hw_version
.macRev
= MS(val
, AR_SREV_REVISION2
);
349 if (AR_SREV_9462(ah
) || AR_SREV_9565(ah
))
350 ah
->is_pciexpress
= true;
352 ah
->is_pciexpress
= (val
&
353 AR_SREV_TYPE2_HOST_MODE
) ? 0 : 1;
355 if (!AR_SREV_9100(ah
))
356 ah
->hw_version
.macVersion
= MS(val
, AR_SREV_VERSION
);
358 ah
->hw_version
.macRev
= val
& AR_SREV_REVISION
;
360 if (ah
->hw_version
.macVersion
== AR_SREV_VERSION_5416_PCIE
)
361 ah
->is_pciexpress
= true;
365 /************************************/
366 /* HW Attach, Detach, Init Routines */
367 /************************************/
369 static void ath9k_hw_disablepcie(struct ath_hw
*ah
)
371 if (!AR_SREV_5416(ah
))
374 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x9248fc00);
375 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x24924924);
376 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x28000029);
377 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x57160824);
378 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x25980579);
379 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x00000000);
380 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x1aaabe40);
381 REG_WRITE(ah
, AR_PCIE_SERDES
, 0xbe105554);
382 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x000e1007);
384 REG_WRITE(ah
, AR_PCIE_SERDES2
, 0x00000000);
387 /* This should work for all families including legacy */
388 static bool ath9k_hw_chip_test(struct ath_hw
*ah
)
390 struct ath_common
*common
= ath9k_hw_common(ah
);
391 u32 regAddr
[2] = { AR_STA_ID0
};
393 static const u32 patternData
[4] = {
394 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
398 if (!AR_SREV_9300_20_OR_LATER(ah
)) {
400 regAddr
[1] = AR_PHY_BASE
+ (8 << 2);
404 for (i
= 0; i
< loop_max
; i
++) {
405 u32 addr
= regAddr
[i
];
408 regHold
[i
] = REG_READ(ah
, addr
);
409 for (j
= 0; j
< 0x100; j
++) {
410 wrData
= (j
<< 16) | j
;
411 REG_WRITE(ah
, addr
, wrData
);
412 rdData
= REG_READ(ah
, addr
);
413 if (rdData
!= wrData
) {
415 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
416 addr
, wrData
, rdData
);
420 for (j
= 0; j
< 4; j
++) {
421 wrData
= patternData
[j
];
422 REG_WRITE(ah
, addr
, wrData
);
423 rdData
= REG_READ(ah
, addr
);
424 if (wrData
!= rdData
) {
426 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
427 addr
, wrData
, rdData
);
431 REG_WRITE(ah
, regAddr
[i
], regHold
[i
]);
438 static void ath9k_hw_init_config(struct ath_hw
*ah
)
442 ah
->config
.dma_beacon_response_time
= 1;
443 ah
->config
.sw_beacon_response_time
= 6;
444 ah
->config
.additional_swba_backoff
= 0;
445 ah
->config
.ack_6mb
= 0x0;
446 ah
->config
.cwm_ignore_extcca
= 0;
447 ah
->config
.pcie_clock_req
= 0;
448 ah
->config
.analog_shiftreg
= 1;
450 for (i
= 0; i
< AR_EEPROM_MODAL_SPURS
; i
++) {
451 ah
->config
.spurchans
[i
][0] = AR_NO_SPUR
;
452 ah
->config
.spurchans
[i
][1] = AR_NO_SPUR
;
455 ah
->config
.rx_intr_mitigation
= true;
456 ah
->config
.pcieSerDesWrite
= true;
459 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
460 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
461 * This means we use it for all AR5416 devices, and the few
462 * minor PCI AR9280 devices out there.
464 * Serialization is required because these devices do not handle
465 * well the case of two concurrent reads/writes due to the latency
466 * involved. During one read/write another read/write can be issued
467 * on another CPU while the previous read/write may still be working
468 * on our hardware, if we hit this case the hardware poops in a loop.
469 * We prevent this by serializing reads and writes.
471 * This issue is not present on PCI-Express devices or pre-AR5416
472 * devices (legacy, 802.11abg).
474 if (num_possible_cpus() > 1)
475 ah
->config
.serialize_regmode
= SER_REG_MODE_AUTO
;
478 static void ath9k_hw_init_defaults(struct ath_hw
*ah
)
480 struct ath_regulatory
*regulatory
= ath9k_hw_regulatory(ah
);
482 regulatory
->country_code
= CTRY_DEFAULT
;
483 regulatory
->power_limit
= MAX_RATE_POWER
;
485 ah
->hw_version
.magic
= AR5416_MAGIC
;
486 ah
->hw_version
.subvendorid
= 0;
489 ah
->sta_id1_defaults
=
490 AR_STA_ID1_CRPT_MIC_ENABLE
|
491 AR_STA_ID1_MCAST_KSRCH
;
492 if (AR_SREV_9100(ah
))
493 ah
->sta_id1_defaults
|= AR_STA_ID1_AR9100_BA_FIX
;
494 ah
->slottime
= ATH9K_SLOT_TIME_9
;
495 ah
->globaltxtimeout
= (u32
) -1;
496 ah
->power_mode
= ATH9K_PM_UNDEFINED
;
497 ah
->htc_reset_init
= true;
500 static int ath9k_hw_init_macaddr(struct ath_hw
*ah
)
502 struct ath_common
*common
= ath9k_hw_common(ah
);
506 static const u32 EEP_MAC
[] = { EEP_MAC_LSW
, EEP_MAC_MID
, EEP_MAC_MSW
};
509 for (i
= 0; i
< 3; i
++) {
510 eeval
= ah
->eep_ops
->get_eeprom(ah
, EEP_MAC
[i
]);
512 common
->macaddr
[2 * i
] = eeval
>> 8;
513 common
->macaddr
[2 * i
+ 1] = eeval
& 0xff;
515 if (sum
== 0 || sum
== 0xffff * 3)
516 return -EADDRNOTAVAIL
;
521 static int ath9k_hw_post_init(struct ath_hw
*ah
)
523 struct ath_common
*common
= ath9k_hw_common(ah
);
526 if (common
->bus_ops
->ath_bus_type
!= ATH_USB
) {
527 if (!ath9k_hw_chip_test(ah
))
531 if (!AR_SREV_9300_20_OR_LATER(ah
)) {
532 ecode
= ar9002_hw_rf_claim(ah
);
537 ecode
= ath9k_hw_eeprom_init(ah
);
541 ath_dbg(ath9k_hw_common(ah
), CONFIG
, "Eeprom VER: %d, REV: %d\n",
542 ah
->eep_ops
->get_eeprom_ver(ah
),
543 ah
->eep_ops
->get_eeprom_rev(ah
));
545 ath9k_hw_ani_init(ah
);
548 * EEPROM needs to be initialized before we do this.
549 * This is required for regulatory compliance.
551 if (AR_SREV_9462(ah
) || AR_SREV_9565(ah
)) {
552 u16 regdmn
= ah
->eep_ops
->get_eeprom(ah
, EEP_REG_0
);
553 if ((regdmn
& 0xF0) == CTL_FCC
) {
554 ah
->nf_2g
.max
= AR_PHY_CCA_MAX_GOOD_VAL_9462_FCC_2GHZ
;
555 ah
->nf_5g
.max
= AR_PHY_CCA_MAX_GOOD_VAL_9462_FCC_5GHZ
;
562 static int ath9k_hw_attach_ops(struct ath_hw
*ah
)
564 if (!AR_SREV_9300_20_OR_LATER(ah
))
565 return ar9002_hw_attach_ops(ah
);
567 ar9003_hw_attach_ops(ah
);
571 /* Called for all hardware families */
572 static int __ath9k_hw_init(struct ath_hw
*ah
)
574 struct ath_common
*common
= ath9k_hw_common(ah
);
577 ath9k_hw_read_revisions(ah
);
580 * Read back AR_WA into a permanent copy and set bits 14 and 17.
581 * We need to do this to avoid RMW of this register. We cannot
582 * read the reg when chip is asleep.
584 if (AR_SREV_9300_20_OR_LATER(ah
)) {
585 ah
->WARegVal
= REG_READ(ah
, AR_WA
);
586 ah
->WARegVal
|= (AR_WA_D3_L1_DISABLE
|
587 AR_WA_ASPM_TIMER_BASED_DISABLE
);
590 if (!ath9k_hw_set_reset_reg(ah
, ATH9K_RESET_POWER_ON
)) {
591 ath_err(common
, "Couldn't reset chip\n");
595 if (AR_SREV_9565(ah
)) {
596 ah
->WARegVal
|= AR_WA_BIT22
;
597 REG_WRITE(ah
, AR_WA
, ah
->WARegVal
);
600 ath9k_hw_init_defaults(ah
);
601 ath9k_hw_init_config(ah
);
603 r
= ath9k_hw_attach_ops(ah
);
607 if (!ath9k_hw_setpower(ah
, ATH9K_PM_AWAKE
)) {
608 ath_err(common
, "Couldn't wakeup chip\n");
612 if (NR_CPUS
> 1 && ah
->config
.serialize_regmode
== SER_REG_MODE_AUTO
) {
613 if (ah
->hw_version
.macVersion
== AR_SREV_VERSION_5416_PCI
||
614 ((AR_SREV_9160(ah
) || AR_SREV_9280(ah
) || AR_SREV_9287(ah
)) &&
615 !ah
->is_pciexpress
)) {
616 ah
->config
.serialize_regmode
=
619 ah
->config
.serialize_regmode
=
624 ath_dbg(common
, RESET
, "serialize_regmode is %d\n",
625 ah
->config
.serialize_regmode
);
627 if (AR_SREV_9285(ah
) || AR_SREV_9271(ah
))
628 ah
->config
.max_txtrig_level
= MAX_TX_FIFO_THRESHOLD
>> 1;
630 ah
->config
.max_txtrig_level
= MAX_TX_FIFO_THRESHOLD
;
632 switch (ah
->hw_version
.macVersion
) {
633 case AR_SREV_VERSION_5416_PCI
:
634 case AR_SREV_VERSION_5416_PCIE
:
635 case AR_SREV_VERSION_9160
:
636 case AR_SREV_VERSION_9100
:
637 case AR_SREV_VERSION_9280
:
638 case AR_SREV_VERSION_9285
:
639 case AR_SREV_VERSION_9287
:
640 case AR_SREV_VERSION_9271
:
641 case AR_SREV_VERSION_9300
:
642 case AR_SREV_VERSION_9330
:
643 case AR_SREV_VERSION_9485
:
644 case AR_SREV_VERSION_9340
:
645 case AR_SREV_VERSION_9462
:
646 case AR_SREV_VERSION_9550
:
647 case AR_SREV_VERSION_9565
:
651 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
652 ah
->hw_version
.macVersion
, ah
->hw_version
.macRev
);
656 if (AR_SREV_9271(ah
) || AR_SREV_9100(ah
) || AR_SREV_9340(ah
) ||
657 AR_SREV_9330(ah
) || AR_SREV_9550(ah
))
658 ah
->is_pciexpress
= false;
660 ah
->hw_version
.phyRev
= REG_READ(ah
, AR_PHY_CHIP_ID
);
661 ath9k_hw_init_cal_settings(ah
);
663 ah
->ani_function
= ATH9K_ANI_ALL
;
664 if (!AR_SREV_9300_20_OR_LATER(ah
))
665 ah
->ani_function
&= ~ATH9K_ANI_MRC_CCK
;
667 if (!ah
->is_pciexpress
)
668 ath9k_hw_disablepcie(ah
);
670 r
= ath9k_hw_post_init(ah
);
674 ath9k_hw_init_mode_gain_regs(ah
);
675 r
= ath9k_hw_fill_cap_info(ah
);
679 r
= ath9k_hw_init_macaddr(ah
);
681 ath_err(common
, "Failed to initialize MAC address\n");
685 if (AR_SREV_9285(ah
) || AR_SREV_9271(ah
))
686 ah
->tx_trig_level
= (AR_FTRIG_256B
>> AR_FTRIG_S
);
688 ah
->tx_trig_level
= (AR_FTRIG_512B
>> AR_FTRIG_S
);
690 if (AR_SREV_9330(ah
))
691 ah
->bb_watchdog_timeout_ms
= 85;
693 ah
->bb_watchdog_timeout_ms
= 25;
695 common
->state
= ATH_HW_INITIALIZED
;
700 int ath9k_hw_init(struct ath_hw
*ah
)
703 struct ath_common
*common
= ath9k_hw_common(ah
);
705 /* These are all the AR5008/AR9001/AR9002/AR9003 hardware family of chipsets */
706 switch (ah
->hw_version
.devid
) {
707 case AR5416_DEVID_PCI
:
708 case AR5416_DEVID_PCIE
:
709 case AR5416_AR9100_DEVID
:
710 case AR9160_DEVID_PCI
:
711 case AR9280_DEVID_PCI
:
712 case AR9280_DEVID_PCIE
:
713 case AR9285_DEVID_PCIE
:
714 case AR9287_DEVID_PCI
:
715 case AR9287_DEVID_PCIE
:
716 case AR2427_DEVID_PCIE
:
717 case AR9300_DEVID_PCIE
:
718 case AR9300_DEVID_AR9485_PCIE
:
719 case AR9300_DEVID_AR9330
:
720 case AR9300_DEVID_AR9340
:
721 case AR9300_DEVID_QCA955X
:
722 case AR9300_DEVID_AR9580
:
723 case AR9300_DEVID_AR9462
:
724 case AR9485_DEVID_AR1111
:
725 case AR9300_DEVID_AR9565
:
728 if (common
->bus_ops
->ath_bus_type
== ATH_USB
)
730 ath_err(common
, "Hardware device ID 0x%04x not supported\n",
731 ah
->hw_version
.devid
);
735 ret
= __ath9k_hw_init(ah
);
738 "Unable to initialize hardware; initialization status: %d\n",
745 EXPORT_SYMBOL(ath9k_hw_init
);
747 static void ath9k_hw_init_qos(struct ath_hw
*ah
)
749 ENABLE_REGWRITE_BUFFER(ah
);
751 REG_WRITE(ah
, AR_MIC_QOS_CONTROL
, 0x100aa);
752 REG_WRITE(ah
, AR_MIC_QOS_SELECT
, 0x3210);
754 REG_WRITE(ah
, AR_QOS_NO_ACK
,
755 SM(2, AR_QOS_NO_ACK_TWO_BIT
) |
756 SM(5, AR_QOS_NO_ACK_BIT_OFF
) |
757 SM(0, AR_QOS_NO_ACK_BYTE_OFF
));
759 REG_WRITE(ah
, AR_TXOP_X
, AR_TXOP_X_VAL
);
760 REG_WRITE(ah
, AR_TXOP_0_3
, 0xFFFFFFFF);
761 REG_WRITE(ah
, AR_TXOP_4_7
, 0xFFFFFFFF);
762 REG_WRITE(ah
, AR_TXOP_8_11
, 0xFFFFFFFF);
763 REG_WRITE(ah
, AR_TXOP_12_15
, 0xFFFFFFFF);
765 REGWRITE_BUFFER_FLUSH(ah
);
768 u32
ar9003_get_pll_sqsum_dvc(struct ath_hw
*ah
)
770 struct ath_common
*common
= ath9k_hw_common(ah
);
773 REG_CLR_BIT(ah
, PLL3
, PLL3_DO_MEAS_MASK
);
775 REG_SET_BIT(ah
, PLL3
, PLL3_DO_MEAS_MASK
);
777 while ((REG_READ(ah
, PLL4
) & PLL4_MEAS_DONE
) == 0) {
781 if (WARN_ON_ONCE(i
>= 100)) {
782 ath_err(common
, "PLL4 meaurement not done\n");
789 return (REG_READ(ah
, PLL3
) & SQSUM_DVC_MASK
) >> 3;
791 EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc
);
793 static void ath9k_hw_init_pll(struct ath_hw
*ah
,
794 struct ath9k_channel
*chan
)
798 if (AR_SREV_9485(ah
) || AR_SREV_9565(ah
)) {
799 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */
800 REG_RMW_FIELD(ah
, AR_CH0_BB_DPLL2
,
801 AR_CH0_BB_DPLL2_PLL_PWD
, 0x1);
802 REG_RMW_FIELD(ah
, AR_CH0_BB_DPLL2
,
803 AR_CH0_DPLL2_KD
, 0x40);
804 REG_RMW_FIELD(ah
, AR_CH0_BB_DPLL2
,
805 AR_CH0_DPLL2_KI
, 0x4);
807 REG_RMW_FIELD(ah
, AR_CH0_BB_DPLL1
,
808 AR_CH0_BB_DPLL1_REFDIV
, 0x5);
809 REG_RMW_FIELD(ah
, AR_CH0_BB_DPLL1
,
810 AR_CH0_BB_DPLL1_NINI
, 0x58);
811 REG_RMW_FIELD(ah
, AR_CH0_BB_DPLL1
,
812 AR_CH0_BB_DPLL1_NFRAC
, 0x0);
814 REG_RMW_FIELD(ah
, AR_CH0_BB_DPLL2
,
815 AR_CH0_BB_DPLL2_OUTDIV
, 0x1);
816 REG_RMW_FIELD(ah
, AR_CH0_BB_DPLL2
,
817 AR_CH0_BB_DPLL2_LOCAL_PLL
, 0x1);
818 REG_RMW_FIELD(ah
, AR_CH0_BB_DPLL2
,
819 AR_CH0_BB_DPLL2_EN_NEGTRIG
, 0x1);
821 /* program BB PLL phase_shift to 0x6 */
822 REG_RMW_FIELD(ah
, AR_CH0_BB_DPLL3
,
823 AR_CH0_BB_DPLL3_PHASE_SHIFT
, 0x6);
825 REG_RMW_FIELD(ah
, AR_CH0_BB_DPLL2
,
826 AR_CH0_BB_DPLL2_PLL_PWD
, 0x0);
828 } else if (AR_SREV_9330(ah
)) {
829 u32 ddr_dpll2
, pll_control2
, kd
;
831 if (ah
->is_clk_25mhz
) {
832 ddr_dpll2
= 0x18e82f01;
833 pll_control2
= 0xe04a3d;
836 ddr_dpll2
= 0x19e82f01;
837 pll_control2
= 0x886666;
841 /* program DDR PLL ki and kd value */
842 REG_WRITE(ah
, AR_CH0_DDR_DPLL2
, ddr_dpll2
);
844 /* program DDR PLL phase_shift */
845 REG_RMW_FIELD(ah
, AR_CH0_DDR_DPLL3
,
846 AR_CH0_DPLL3_PHASE_SHIFT
, 0x1);
848 REG_WRITE(ah
, AR_RTC_PLL_CONTROL
, 0x1142c);
851 /* program refdiv, nint, frac to RTC register */
852 REG_WRITE(ah
, AR_RTC_PLL_CONTROL2
, pll_control2
);
854 /* program BB PLL kd and ki value */
855 REG_RMW_FIELD(ah
, AR_CH0_BB_DPLL2
, AR_CH0_DPLL2_KD
, kd
);
856 REG_RMW_FIELD(ah
, AR_CH0_BB_DPLL2
, AR_CH0_DPLL2_KI
, 0x06);
858 /* program BB PLL phase_shift */
859 REG_RMW_FIELD(ah
, AR_CH0_BB_DPLL3
,
860 AR_CH0_BB_DPLL3_PHASE_SHIFT
, 0x1);
861 } else if (AR_SREV_9340(ah
) || AR_SREV_9550(ah
)) {
862 u32 regval
, pll2_divint
, pll2_divfrac
, refdiv
;
864 REG_WRITE(ah
, AR_RTC_PLL_CONTROL
, 0x1142c);
867 REG_SET_BIT(ah
, AR_PHY_PLL_MODE
, 0x1 << 16);
870 if (ah
->is_clk_25mhz
) {
872 pll2_divfrac
= 0x1eb85;
875 if (AR_SREV_9340(ah
)) {
881 pll2_divfrac
= 0x26666;
886 regval
= REG_READ(ah
, AR_PHY_PLL_MODE
);
887 regval
|= (0x1 << 16);
888 REG_WRITE(ah
, AR_PHY_PLL_MODE
, regval
);
891 REG_WRITE(ah
, AR_PHY_PLL_CONTROL
, (refdiv
<< 27) |
892 (pll2_divint
<< 18) | pll2_divfrac
);
895 regval
= REG_READ(ah
, AR_PHY_PLL_MODE
);
896 if (AR_SREV_9340(ah
))
897 regval
= (regval
& 0x80071fff) | (0x1 << 30) |
898 (0x1 << 13) | (0x4 << 26) | (0x18 << 19);
900 regval
= (regval
& 0x80071fff) | (0x3 << 30) |
901 (0x1 << 13) | (0x4 << 26) | (0x60 << 19);
902 REG_WRITE(ah
, AR_PHY_PLL_MODE
, regval
);
903 REG_WRITE(ah
, AR_PHY_PLL_MODE
,
904 REG_READ(ah
, AR_PHY_PLL_MODE
) & 0xfffeffff);
908 pll
= ath9k_hw_compute_pll_control(ah
, chan
);
909 if (AR_SREV_9565(ah
))
911 REG_WRITE(ah
, AR_RTC_PLL_CONTROL
, pll
);
913 if (AR_SREV_9485(ah
) || AR_SREV_9340(ah
) || AR_SREV_9330(ah
) ||
917 /* Switch the core clock for ar9271 to 117Mhz */
918 if (AR_SREV_9271(ah
)) {
920 REG_WRITE(ah
, 0x50040, 0x304);
923 udelay(RTC_PLL_SETTLE_DELAY
);
925 REG_WRITE(ah
, AR_RTC_SLEEP_CLK
, AR_RTC_FORCE_DERIVED_CLK
);
927 if (AR_SREV_9340(ah
) || AR_SREV_9550(ah
)) {
928 if (ah
->is_clk_25mhz
) {
929 REG_WRITE(ah
, AR_RTC_DERIVED_CLK
, 0x17c << 1);
930 REG_WRITE(ah
, AR_SLP32_MODE
, 0x0010f3d7);
931 REG_WRITE(ah
, AR_SLP32_INC
, 0x0001e7ae);
933 REG_WRITE(ah
, AR_RTC_DERIVED_CLK
, 0x261 << 1);
934 REG_WRITE(ah
, AR_SLP32_MODE
, 0x0010f400);
935 REG_WRITE(ah
, AR_SLP32_INC
, 0x0001e800);
941 static void ath9k_hw_init_interrupt_masks(struct ath_hw
*ah
,
942 enum nl80211_iftype opmode
)
944 u32 sync_default
= AR_INTR_SYNC_DEFAULT
;
945 u32 imr_reg
= AR_IMR_TXERR
|
951 if (AR_SREV_9340(ah
) || AR_SREV_9550(ah
))
952 sync_default
&= ~AR_INTR_SYNC_HOST1_FATAL
;
954 if (AR_SREV_9300_20_OR_LATER(ah
)) {
955 imr_reg
|= AR_IMR_RXOK_HP
;
956 if (ah
->config
.rx_intr_mitigation
)
957 imr_reg
|= AR_IMR_RXINTM
| AR_IMR_RXMINTR
;
959 imr_reg
|= AR_IMR_RXOK_LP
;
962 if (ah
->config
.rx_intr_mitigation
)
963 imr_reg
|= AR_IMR_RXINTM
| AR_IMR_RXMINTR
;
965 imr_reg
|= AR_IMR_RXOK
;
968 if (ah
->config
.tx_intr_mitigation
)
969 imr_reg
|= AR_IMR_TXINTM
| AR_IMR_TXMINTR
;
971 imr_reg
|= AR_IMR_TXOK
;
973 ENABLE_REGWRITE_BUFFER(ah
);
975 REG_WRITE(ah
, AR_IMR
, imr_reg
);
976 ah
->imrs2_reg
|= AR_IMR_S2_GTT
;
977 REG_WRITE(ah
, AR_IMR_S2
, ah
->imrs2_reg
);
979 if (!AR_SREV_9100(ah
)) {
980 REG_WRITE(ah
, AR_INTR_SYNC_CAUSE
, 0xFFFFFFFF);
981 REG_WRITE(ah
, AR_INTR_SYNC_ENABLE
, sync_default
);
982 REG_WRITE(ah
, AR_INTR_SYNC_MASK
, 0);
985 REGWRITE_BUFFER_FLUSH(ah
);
987 if (AR_SREV_9300_20_OR_LATER(ah
)) {
988 REG_WRITE(ah
, AR_INTR_PRIO_ASYNC_ENABLE
, 0);
989 REG_WRITE(ah
, AR_INTR_PRIO_ASYNC_MASK
, 0);
990 REG_WRITE(ah
, AR_INTR_PRIO_SYNC_ENABLE
, 0);
991 REG_WRITE(ah
, AR_INTR_PRIO_SYNC_MASK
, 0);
995 static void ath9k_hw_set_sifs_time(struct ath_hw
*ah
, u32 us
)
997 u32 val
= ath9k_hw_mac_to_clks(ah
, us
- 2);
998 val
= min(val
, (u32
) 0xFFFF);
999 REG_WRITE(ah
, AR_D_GBL_IFS_SIFS
, val
);
1002 static void ath9k_hw_setslottime(struct ath_hw
*ah
, u32 us
)
1004 u32 val
= ath9k_hw_mac_to_clks(ah
, us
);
1005 val
= min(val
, (u32
) 0xFFFF);
1006 REG_WRITE(ah
, AR_D_GBL_IFS_SLOT
, val
);
1009 static void ath9k_hw_set_ack_timeout(struct ath_hw
*ah
, u32 us
)
1011 u32 val
= ath9k_hw_mac_to_clks(ah
, us
);
1012 val
= min(val
, (u32
) MS(0xFFFFFFFF, AR_TIME_OUT_ACK
));
1013 REG_RMW_FIELD(ah
, AR_TIME_OUT
, AR_TIME_OUT_ACK
, val
);
1016 static void ath9k_hw_set_cts_timeout(struct ath_hw
*ah
, u32 us
)
1018 u32 val
= ath9k_hw_mac_to_clks(ah
, us
);
1019 val
= min(val
, (u32
) MS(0xFFFFFFFF, AR_TIME_OUT_CTS
));
1020 REG_RMW_FIELD(ah
, AR_TIME_OUT
, AR_TIME_OUT_CTS
, val
);
1023 static bool ath9k_hw_set_global_txtimeout(struct ath_hw
*ah
, u32 tu
)
1026 ath_dbg(ath9k_hw_common(ah
), XMIT
, "bad global tx timeout %u\n",
1028 ah
->globaltxtimeout
= (u32
) -1;
1031 REG_RMW_FIELD(ah
, AR_GTXTO
, AR_GTXTO_TIMEOUT_LIMIT
, tu
);
1032 ah
->globaltxtimeout
= tu
;
1037 void ath9k_hw_init_global_settings(struct ath_hw
*ah
)
1039 struct ath_common
*common
= ath9k_hw_common(ah
);
1040 const struct ath9k_channel
*chan
= ah
->curchan
;
1041 int acktimeout
, ctstimeout
, ack_offset
= 0;
1044 int rx_lat
= 0, tx_lat
= 0, eifs
= 0;
1047 ath_dbg(ath9k_hw_common(ah
), RESET
, "ah->misc_mode 0x%x\n",
1053 if (ah
->misc_mode
!= 0)
1054 REG_SET_BIT(ah
, AR_PCU_MISC
, ah
->misc_mode
);
1056 if (IS_CHAN_A_FAST_CLOCK(ah
, chan
))
1062 if (IS_CHAN_5GHZ(chan
))
1067 if (IS_CHAN_HALF_RATE(chan
)) {
1071 if (IS_CHAN_A_FAST_CLOCK(ah
, chan
))
1077 } else if (IS_CHAN_QUARTER_RATE(chan
)) {
1079 rx_lat
= (rx_lat
* 4) - 1;
1081 if (IS_CHAN_A_FAST_CLOCK(ah
, chan
))
1088 if (AR_SREV_9287(ah
) && AR_SREV_9287_13_OR_LATER(ah
)) {
1089 eifs
= AR_D_GBL_IFS_EIFS_ASYNC_FIFO
;
1090 reg
= AR_USEC_ASYNC_FIFO
;
1092 eifs
= REG_READ(ah
, AR_D_GBL_IFS_EIFS
)/
1094 reg
= REG_READ(ah
, AR_USEC
);
1096 rx_lat
= MS(reg
, AR_USEC_RX_LAT
);
1097 tx_lat
= MS(reg
, AR_USEC_TX_LAT
);
1099 slottime
= ah
->slottime
;
1102 /* As defined by IEEE 802.11-2007 17.3.8.6 */
1103 slottime
+= 3 * ah
->coverage_class
;
1104 acktimeout
= slottime
+ sifstime
+ ack_offset
;
1105 ctstimeout
= acktimeout
;
1108 * Workaround for early ACK timeouts, add an offset to match the
1109 * initval's 64us ack timeout value. Use 48us for the CTS timeout.
1110 * This was initially only meant to work around an issue with delayed
1111 * BA frames in some implementations, but it has been found to fix ACK
1112 * timeout issues in other cases as well.
1114 if (IS_CHAN_2GHZ(chan
) &&
1115 !IS_CHAN_HALF_RATE(chan
) && !IS_CHAN_QUARTER_RATE(chan
)) {
1116 acktimeout
+= 64 - sifstime
- ah
->slottime
;
1117 ctstimeout
+= 48 - sifstime
- ah
->slottime
;
1120 ath9k_hw_set_sifs_time(ah
, sifstime
);
1121 ath9k_hw_setslottime(ah
, slottime
);
1122 ath9k_hw_set_ack_timeout(ah
, acktimeout
);
1123 ath9k_hw_set_cts_timeout(ah
, ctstimeout
);
1124 if (ah
->globaltxtimeout
!= (u32
) -1)
1125 ath9k_hw_set_global_txtimeout(ah
, ah
->globaltxtimeout
);
1127 REG_WRITE(ah
, AR_D_GBL_IFS_EIFS
, ath9k_hw_mac_to_clks(ah
, eifs
));
1128 REG_RMW(ah
, AR_USEC
,
1129 (common
->clockrate
- 1) |
1130 SM(rx_lat
, AR_USEC_RX_LAT
) |
1131 SM(tx_lat
, AR_USEC_TX_LAT
),
1132 AR_USEC_TX_LAT
| AR_USEC_RX_LAT
| AR_USEC_USEC
);
1135 EXPORT_SYMBOL(ath9k_hw_init_global_settings
);
1137 void ath9k_hw_deinit(struct ath_hw
*ah
)
1139 struct ath_common
*common
= ath9k_hw_common(ah
);
1141 if (common
->state
< ATH_HW_INITIALIZED
)
1144 ath9k_hw_setpower(ah
, ATH9K_PM_FULL_SLEEP
);
1146 EXPORT_SYMBOL(ath9k_hw_deinit
);
1152 u32
ath9k_regd_get_ctl(struct ath_regulatory
*reg
, struct ath9k_channel
*chan
)
1154 u32 ctl
= ath_regd_get_band_ctl(reg
, chan
->chan
->band
);
1156 if (IS_CHAN_2GHZ(chan
))
1164 /****************************************/
1165 /* Reset and Channel Switching Routines */
1166 /****************************************/
1168 static inline void ath9k_hw_set_dma(struct ath_hw
*ah
)
1170 struct ath_common
*common
= ath9k_hw_common(ah
);
1173 ENABLE_REGWRITE_BUFFER(ah
);
1176 * set AHB_MODE not to do cacheline prefetches
1178 if (!AR_SREV_9300_20_OR_LATER(ah
))
1179 REG_SET_BIT(ah
, AR_AHB_MODE
, AR_AHB_PREFETCH_RD_EN
);
1182 * let mac dma reads be in 128 byte chunks
1184 REG_RMW(ah
, AR_TXCFG
, AR_TXCFG_DMASZ_128B
, AR_TXCFG_DMASZ_MASK
);
1186 REGWRITE_BUFFER_FLUSH(ah
);
1189 * Restore TX Trigger Level to its pre-reset value.
1190 * The initial value depends on whether aggregation is enabled, and is
1191 * adjusted whenever underruns are detected.
1193 if (!AR_SREV_9300_20_OR_LATER(ah
))
1194 REG_RMW_FIELD(ah
, AR_TXCFG
, AR_FTRIG
, ah
->tx_trig_level
);
1196 ENABLE_REGWRITE_BUFFER(ah
);
1199 * let mac dma writes be in 128 byte chunks
1201 REG_RMW(ah
, AR_RXCFG
, AR_RXCFG_DMASZ_128B
, AR_RXCFG_DMASZ_MASK
);
1204 * Setup receive FIFO threshold to hold off TX activities
1206 REG_WRITE(ah
, AR_RXFIFO_CFG
, 0x200);
1208 if (AR_SREV_9300_20_OR_LATER(ah
)) {
1209 REG_RMW_FIELD(ah
, AR_RXBP_THRESH
, AR_RXBP_THRESH_HP
, 0x1);
1210 REG_RMW_FIELD(ah
, AR_RXBP_THRESH
, AR_RXBP_THRESH_LP
, 0x1);
1212 ath9k_hw_set_rx_bufsize(ah
, common
->rx_bufsize
-
1213 ah
->caps
.rx_status_len
);
1217 * reduce the number of usable entries in PCU TXBUF to avoid
1218 * wrap around issues.
1220 if (AR_SREV_9285(ah
)) {
1221 /* For AR9285 the number of Fifos are reduced to half.
1222 * So set the usable tx buf size also to half to
1223 * avoid data/delimiter underruns
1225 txbuf_size
= AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE
;
1226 } else if (AR_SREV_9340_13_OR_LATER(ah
)) {
1227 /* Uses fewer entries for AR934x v1.3+ to prevent rx overruns */
1228 txbuf_size
= AR_9340_PCU_TXBUF_CTRL_USABLE_SIZE
;
1230 txbuf_size
= AR_PCU_TXBUF_CTRL_USABLE_SIZE
;
1233 if (!AR_SREV_9271(ah
))
1234 REG_WRITE(ah
, AR_PCU_TXBUF_CTRL
, txbuf_size
);
1236 REGWRITE_BUFFER_FLUSH(ah
);
1238 if (AR_SREV_9300_20_OR_LATER(ah
))
1239 ath9k_hw_reset_txstatus_ring(ah
);
1242 static void ath9k_hw_set_operating_mode(struct ath_hw
*ah
, int opmode
)
1244 u32 mask
= AR_STA_ID1_STA_AP
| AR_STA_ID1_ADHOC
;
1245 u32 set
= AR_STA_ID1_KSRCH_MODE
;
1248 case NL80211_IFTYPE_ADHOC
:
1249 set
|= AR_STA_ID1_ADHOC
;
1250 REG_SET_BIT(ah
, AR_CFG
, AR_CFG_AP_ADHOC_INDICATION
);
1252 case NL80211_IFTYPE_MESH_POINT
:
1253 case NL80211_IFTYPE_AP
:
1254 set
|= AR_STA_ID1_STA_AP
;
1256 case NL80211_IFTYPE_STATION
:
1257 REG_CLR_BIT(ah
, AR_CFG
, AR_CFG_AP_ADHOC_INDICATION
);
1260 if (!ah
->is_monitoring
)
1264 REG_RMW(ah
, AR_STA_ID1
, set
, mask
);
1267 void ath9k_hw_get_delta_slope_vals(struct ath_hw
*ah
, u32 coef_scaled
,
1268 u32
*coef_mantissa
, u32
*coef_exponent
)
1270 u32 coef_exp
, coef_man
;
1272 for (coef_exp
= 31; coef_exp
> 0; coef_exp
--)
1273 if ((coef_scaled
>> coef_exp
) & 0x1)
1276 coef_exp
= 14 - (coef_exp
- COEF_SCALE_S
);
1278 coef_man
= coef_scaled
+ (1 << (COEF_SCALE_S
- coef_exp
- 1));
1280 *coef_mantissa
= coef_man
>> (COEF_SCALE_S
- coef_exp
);
1281 *coef_exponent
= coef_exp
- 16;
1284 static bool ath9k_hw_set_reset(struct ath_hw
*ah
, int type
)
1289 if (AR_SREV_9100(ah
)) {
1290 REG_RMW_FIELD(ah
, AR_RTC_DERIVED_CLK
,
1291 AR_RTC_DERIVED_CLK_PERIOD
, 1);
1292 (void)REG_READ(ah
, AR_RTC_DERIVED_CLK
);
1295 ENABLE_REGWRITE_BUFFER(ah
);
1297 if (AR_SREV_9300_20_OR_LATER(ah
)) {
1298 REG_WRITE(ah
, AR_WA
, ah
->WARegVal
);
1302 REG_WRITE(ah
, AR_RTC_FORCE_WAKE
, AR_RTC_FORCE_WAKE_EN
|
1303 AR_RTC_FORCE_WAKE_ON_INT
);
1305 if (AR_SREV_9100(ah
)) {
1306 rst_flags
= AR_RTC_RC_MAC_WARM
| AR_RTC_RC_MAC_COLD
|
1307 AR_RTC_RC_COLD_RESET
| AR_RTC_RC_WARM_RESET
;
1309 tmpReg
= REG_READ(ah
, AR_INTR_SYNC_CAUSE
);
1310 if (AR_SREV_9340(ah
))
1311 tmpReg
&= AR9340_INTR_SYNC_LOCAL_TIMEOUT
;
1313 tmpReg
&= AR_INTR_SYNC_LOCAL_TIMEOUT
|
1314 AR_INTR_SYNC_RADM_CPL_TIMEOUT
;
1318 REG_WRITE(ah
, AR_INTR_SYNC_ENABLE
, 0);
1321 if (!AR_SREV_9300_20_OR_LATER(ah
))
1323 REG_WRITE(ah
, AR_RC
, val
);
1325 } else if (!AR_SREV_9300_20_OR_LATER(ah
))
1326 REG_WRITE(ah
, AR_RC
, AR_RC_AHB
);
1328 rst_flags
= AR_RTC_RC_MAC_WARM
;
1329 if (type
== ATH9K_RESET_COLD
)
1330 rst_flags
|= AR_RTC_RC_MAC_COLD
;
1333 if (AR_SREV_9330(ah
)) {
1338 * call external reset function to reset WMAC if:
1339 * - doing a cold reset
1340 * - we have pending frames in the TX queues
1343 for (i
= 0; i
< AR_NUM_QCU
; i
++) {
1344 npend
= ath9k_hw_numtxpending(ah
, i
);
1349 if (ah
->external_reset
&&
1350 (npend
|| type
== ATH9K_RESET_COLD
)) {
1353 ath_dbg(ath9k_hw_common(ah
), RESET
,
1354 "reset MAC via external reset\n");
1356 reset_err
= ah
->external_reset();
1358 ath_err(ath9k_hw_common(ah
),
1359 "External reset failed, err=%d\n",
1364 REG_WRITE(ah
, AR_RTC_RESET
, 1);
1368 if (ath9k_hw_mci_is_enabled(ah
))
1369 ar9003_mci_check_gpm_offset(ah
);
1371 REG_WRITE(ah
, AR_RTC_RC
, rst_flags
);
1373 REGWRITE_BUFFER_FLUSH(ah
);
1377 REG_WRITE(ah
, AR_RTC_RC
, 0);
1378 if (!ath9k_hw_wait(ah
, AR_RTC_RC
, AR_RTC_RC_M
, 0, AH_WAIT_TIMEOUT
)) {
1379 ath_dbg(ath9k_hw_common(ah
), RESET
, "RTC stuck in MAC reset\n");
1383 if (!AR_SREV_9100(ah
))
1384 REG_WRITE(ah
, AR_RC
, 0);
1386 if (AR_SREV_9100(ah
))
1392 static bool ath9k_hw_set_reset_power_on(struct ath_hw
*ah
)
1394 ENABLE_REGWRITE_BUFFER(ah
);
1396 if (AR_SREV_9300_20_OR_LATER(ah
)) {
1397 REG_WRITE(ah
, AR_WA
, ah
->WARegVal
);
1401 REG_WRITE(ah
, AR_RTC_FORCE_WAKE
, AR_RTC_FORCE_WAKE_EN
|
1402 AR_RTC_FORCE_WAKE_ON_INT
);
1404 if (!AR_SREV_9100(ah
) && !AR_SREV_9300_20_OR_LATER(ah
))
1405 REG_WRITE(ah
, AR_RC
, AR_RC_AHB
);
1407 REG_WRITE(ah
, AR_RTC_RESET
, 0);
1409 REGWRITE_BUFFER_FLUSH(ah
);
1411 if (!AR_SREV_9300_20_OR_LATER(ah
))
1414 if (!AR_SREV_9100(ah
) && !AR_SREV_9300_20_OR_LATER(ah
))
1415 REG_WRITE(ah
, AR_RC
, 0);
1417 REG_WRITE(ah
, AR_RTC_RESET
, 1);
1419 if (!ath9k_hw_wait(ah
,
1424 ath_dbg(ath9k_hw_common(ah
), RESET
, "RTC not waking up\n");
1428 return ath9k_hw_set_reset(ah
, ATH9K_RESET_WARM
);
1431 static bool ath9k_hw_set_reset_reg(struct ath_hw
*ah
, u32 type
)
1435 if (AR_SREV_9300_20_OR_LATER(ah
)) {
1436 REG_WRITE(ah
, AR_WA
, ah
->WARegVal
);
1440 REG_WRITE(ah
, AR_RTC_FORCE_WAKE
,
1441 AR_RTC_FORCE_WAKE_EN
| AR_RTC_FORCE_WAKE_ON_INT
);
1443 if (!ah
->reset_power_on
)
1444 type
= ATH9K_RESET_POWER_ON
;
1447 case ATH9K_RESET_POWER_ON
:
1448 ret
= ath9k_hw_set_reset_power_on(ah
);
1450 ah
->reset_power_on
= true;
1452 case ATH9K_RESET_WARM
:
1453 case ATH9K_RESET_COLD
:
1454 ret
= ath9k_hw_set_reset(ah
, type
);
1463 static bool ath9k_hw_chip_reset(struct ath_hw
*ah
,
1464 struct ath9k_channel
*chan
)
1466 int reset_type
= ATH9K_RESET_WARM
;
1468 if (AR_SREV_9280(ah
)) {
1469 if (ah
->eep_ops
->get_eeprom(ah
, EEP_OL_PWRCTRL
))
1470 reset_type
= ATH9K_RESET_POWER_ON
;
1472 reset_type
= ATH9K_RESET_COLD
;
1473 } else if (ah
->chip_fullsleep
|| REG_READ(ah
, AR_Q_TXE
) ||
1474 (REG_READ(ah
, AR_CR
) & AR_CR_RXE
))
1475 reset_type
= ATH9K_RESET_COLD
;
1477 if (!ath9k_hw_set_reset_reg(ah
, reset_type
))
1480 if (!ath9k_hw_setpower(ah
, ATH9K_PM_AWAKE
))
1483 ah
->chip_fullsleep
= false;
1485 if (AR_SREV_9330(ah
))
1486 ar9003_hw_internal_regulator_apply(ah
);
1487 ath9k_hw_init_pll(ah
, chan
);
1488 ath9k_hw_set_rfmode(ah
, chan
);
1493 static bool ath9k_hw_channel_change(struct ath_hw
*ah
,
1494 struct ath9k_channel
*chan
)
1496 struct ath_common
*common
= ath9k_hw_common(ah
);
1497 struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
1498 bool band_switch
= false, mode_diff
= false;
1499 u8 ini_reloaded
= 0;
1503 if (pCap
->hw_caps
& ATH9K_HW_CAP_FCC_BAND_SWITCH
) {
1504 band_switch
= IS_CHAN_5GHZ(ah
->curchan
) != IS_CHAN_5GHZ(chan
);
1505 mode_diff
= (chan
->channelFlags
!= ah
->curchan
->channelFlags
);
1508 for (qnum
= 0; qnum
< AR_NUM_QCU
; qnum
++) {
1509 if (ath9k_hw_numtxpending(ah
, qnum
)) {
1510 ath_dbg(common
, QUEUE
,
1511 "Transmit frames pending on queue %d\n", qnum
);
1516 if (!ath9k_hw_rfbus_req(ah
)) {
1517 ath_err(common
, "Could not kill baseband RX\n");
1521 if (band_switch
|| mode_diff
) {
1522 ath9k_hw_mark_phy_inactive(ah
);
1526 ath9k_hw_init_pll(ah
, chan
);
1528 if (ath9k_hw_fast_chan_change(ah
, chan
, &ini_reloaded
)) {
1529 ath_err(common
, "Failed to do fast channel change\n");
1534 ath9k_hw_set_channel_regs(ah
, chan
);
1536 r
= ath9k_hw_rf_set_freq(ah
, chan
);
1538 ath_err(common
, "Failed to set channel\n");
1541 ath9k_hw_set_clockrate(ah
);
1542 ath9k_hw_apply_txpower(ah
, chan
, false);
1544 ath9k_hw_set_delta_slope(ah
, chan
);
1545 ath9k_hw_spur_mitigate_freq(ah
, chan
);
1547 if (band_switch
|| ini_reloaded
)
1548 ah
->eep_ops
->set_board_values(ah
, chan
);
1550 ath9k_hw_init_bb(ah
, chan
);
1551 ath9k_hw_rfbus_done(ah
);
1553 if (band_switch
|| ini_reloaded
) {
1554 ah
->ah_flags
|= AH_FASTCC
;
1555 ath9k_hw_init_cal(ah
, chan
);
1556 ah
->ah_flags
&= ~AH_FASTCC
;
1562 static void ath9k_hw_apply_gpio_override(struct ath_hw
*ah
)
1564 u32 gpio_mask
= ah
->gpio_mask
;
1567 for (i
= 0; gpio_mask
; i
++, gpio_mask
>>= 1) {
1568 if (!(gpio_mask
& 1))
1571 ath9k_hw_cfg_output(ah
, i
, AR_GPIO_OUTPUT_MUX_AS_OUTPUT
);
1572 ath9k_hw_set_gpio(ah
, i
, !!(ah
->gpio_val
& BIT(i
)));
1576 static bool ath9k_hw_check_dcs(u32 dma_dbg
, u32 num_dcu_states
,
1577 int *hang_state
, int *hang_pos
)
1579 static u32 dcu_chain_state
[] = {5, 6, 9}; /* DCU chain stuck states */
1580 u32 chain_state
, dcs_pos
, i
;
1582 for (dcs_pos
= 0; dcs_pos
< num_dcu_states
; dcs_pos
++) {
1583 chain_state
= (dma_dbg
>> (5 * dcs_pos
)) & 0x1f;
1584 for (i
= 0; i
< 3; i
++) {
1585 if (chain_state
== dcu_chain_state
[i
]) {
1586 *hang_state
= chain_state
;
1587 *hang_pos
= dcs_pos
;
1595 #define DCU_COMPLETE_STATE 1
1596 #define DCU_COMPLETE_STATE_MASK 0x3
1597 #define NUM_STATUS_READS 50
1598 static bool ath9k_hw_detect_mac_hang(struct ath_hw
*ah
)
1600 u32 chain_state
, comp_state
, dcs_reg
= AR_DMADBG_4
;
1601 u32 i
, hang_pos
, hang_state
, num_state
= 6;
1603 comp_state
= REG_READ(ah
, AR_DMADBG_6
);
1605 if ((comp_state
& DCU_COMPLETE_STATE_MASK
) != DCU_COMPLETE_STATE
) {
1606 ath_dbg(ath9k_hw_common(ah
), RESET
,
1607 "MAC Hang signature not found at DCU complete\n");
1611 chain_state
= REG_READ(ah
, dcs_reg
);
1612 if (ath9k_hw_check_dcs(chain_state
, num_state
, &hang_state
, &hang_pos
))
1613 goto hang_check_iter
;
1615 dcs_reg
= AR_DMADBG_5
;
1617 chain_state
= REG_READ(ah
, dcs_reg
);
1618 if (ath9k_hw_check_dcs(chain_state
, num_state
, &hang_state
, &hang_pos
))
1619 goto hang_check_iter
;
1621 ath_dbg(ath9k_hw_common(ah
), RESET
,
1622 "MAC Hang signature 1 not found\n");
1626 ath_dbg(ath9k_hw_common(ah
), RESET
,
1627 "DCU registers: chain %08x complete %08x Hang: state %d pos %d\n",
1628 chain_state
, comp_state
, hang_state
, hang_pos
);
1630 for (i
= 0; i
< NUM_STATUS_READS
; i
++) {
1631 chain_state
= REG_READ(ah
, dcs_reg
);
1632 chain_state
= (chain_state
>> (5 * hang_pos
)) & 0x1f;
1633 comp_state
= REG_READ(ah
, AR_DMADBG_6
);
1635 if (((comp_state
& DCU_COMPLETE_STATE_MASK
) !=
1636 DCU_COMPLETE_STATE
) ||
1637 (chain_state
!= hang_state
))
1641 ath_dbg(ath9k_hw_common(ah
), RESET
, "MAC Hang signature 1 found\n");
1646 void ath9k_hw_check_nav(struct ath_hw
*ah
)
1648 struct ath_common
*common
= ath9k_hw_common(ah
);
1651 val
= REG_READ(ah
, AR_NAV
);
1652 if (val
!= 0xdeadbeef && val
> 0x7fff) {
1653 ath_dbg(common
, BSTUCK
, "Abnormal NAV: 0x%x\n", val
);
1654 REG_WRITE(ah
, AR_NAV
, 0);
1657 EXPORT_SYMBOL(ath9k_hw_check_nav
);
1659 bool ath9k_hw_check_alive(struct ath_hw
*ah
)
1664 if (AR_SREV_9300(ah
))
1665 return !ath9k_hw_detect_mac_hang(ah
);
1667 if (AR_SREV_9285_12_OR_LATER(ah
))
1671 reg
= REG_READ(ah
, AR_OBS_BUS_1
);
1673 if ((reg
& 0x7E7FFFEF) == 0x00702400)
1676 switch (reg
& 0x7E000B00) {
1684 } while (count
-- > 0);
1688 EXPORT_SYMBOL(ath9k_hw_check_alive
);
1690 static void ath9k_hw_init_mfp(struct ath_hw
*ah
)
1692 /* Setup MFP options for CCMP */
1693 if (AR_SREV_9280_20_OR_LATER(ah
)) {
1694 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1695 * frames when constructing CCMP AAD. */
1696 REG_RMW_FIELD(ah
, AR_AES_MUTE_MASK1
, AR_AES_MUTE_MASK1_FC_MGMT
,
1698 ah
->sw_mgmt_crypto
= false;
1699 } else if (AR_SREV_9160_10_OR_LATER(ah
)) {
1700 /* Disable hardware crypto for management frames */
1701 REG_CLR_BIT(ah
, AR_PCU_MISC_MODE2
,
1702 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE
);
1703 REG_SET_BIT(ah
, AR_PCU_MISC_MODE2
,
1704 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT
);
1705 ah
->sw_mgmt_crypto
= true;
1707 ah
->sw_mgmt_crypto
= true;
1711 static void ath9k_hw_reset_opmode(struct ath_hw
*ah
,
1712 u32 macStaId1
, u32 saveDefAntenna
)
1714 struct ath_common
*common
= ath9k_hw_common(ah
);
1716 ENABLE_REGWRITE_BUFFER(ah
);
1718 REG_RMW(ah
, AR_STA_ID1
, macStaId1
1719 | AR_STA_ID1_RTS_USE_DEF
1720 | (ah
->config
.ack_6mb
? AR_STA_ID1_ACKCTS_6MB
: 0)
1721 | ah
->sta_id1_defaults
,
1722 ~AR_STA_ID1_SADH_MASK
);
1723 ath_hw_setbssidmask(common
);
1724 REG_WRITE(ah
, AR_DEF_ANTENNA
, saveDefAntenna
);
1725 ath9k_hw_write_associd(ah
);
1726 REG_WRITE(ah
, AR_ISR
, ~0);
1727 REG_WRITE(ah
, AR_RSSI_THR
, INIT_RSSI_THR
);
1729 REGWRITE_BUFFER_FLUSH(ah
);
1731 ath9k_hw_set_operating_mode(ah
, ah
->opmode
);
1734 static void ath9k_hw_init_queues(struct ath_hw
*ah
)
1738 ENABLE_REGWRITE_BUFFER(ah
);
1740 for (i
= 0; i
< AR_NUM_DCU
; i
++)
1741 REG_WRITE(ah
, AR_DQCUMASK(i
), 1 << i
);
1743 REGWRITE_BUFFER_FLUSH(ah
);
1746 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++)
1747 ath9k_hw_resettxqueue(ah
, i
);
1751 * For big endian systems turn on swapping for descriptors
1753 static void ath9k_hw_init_desc(struct ath_hw
*ah
)
1755 struct ath_common
*common
= ath9k_hw_common(ah
);
1757 if (AR_SREV_9100(ah
)) {
1759 mask
= REG_READ(ah
, AR_CFG
);
1760 if (mask
& (AR_CFG_SWRB
| AR_CFG_SWTB
| AR_CFG_SWRG
)) {
1761 ath_dbg(common
, RESET
, "CFG Byte Swap Set 0x%x\n",
1764 mask
= INIT_CONFIG_STATUS
| AR_CFG_SWRB
| AR_CFG_SWTB
;
1765 REG_WRITE(ah
, AR_CFG
, mask
);
1766 ath_dbg(common
, RESET
, "Setting CFG 0x%x\n",
1767 REG_READ(ah
, AR_CFG
));
1770 if (common
->bus_ops
->ath_bus_type
== ATH_USB
) {
1771 /* Configure AR9271 target WLAN */
1772 if (AR_SREV_9271(ah
))
1773 REG_WRITE(ah
, AR_CFG
, AR_CFG_SWRB
| AR_CFG_SWTB
);
1775 REG_WRITE(ah
, AR_CFG
, AR_CFG_SWTD
| AR_CFG_SWRD
);
1778 else if (AR_SREV_9330(ah
) || AR_SREV_9340(ah
) ||
1780 REG_RMW(ah
, AR_CFG
, AR_CFG_SWRB
| AR_CFG_SWTB
, 0);
1782 REG_WRITE(ah
, AR_CFG
, AR_CFG_SWTD
| AR_CFG_SWRD
);
1788 * Fast channel change:
1789 * (Change synthesizer based on channel freq without resetting chip)
1791 static int ath9k_hw_do_fastcc(struct ath_hw
*ah
, struct ath9k_channel
*chan
)
1793 struct ath_common
*common
= ath9k_hw_common(ah
);
1794 struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
1797 if (AR_SREV_9280(ah
) && common
->bus_ops
->ath_bus_type
== ATH_PCI
)
1800 if (ah
->chip_fullsleep
)
1806 if (chan
->channel
== ah
->curchan
->channel
)
1809 if ((ah
->curchan
->channelFlags
| chan
->channelFlags
) &
1810 (CHANNEL_HALF
| CHANNEL_QUARTER
))
1814 * If cross-band fcc is not supoprted, bail out if channelFlags differ.
1816 if (!(pCap
->hw_caps
& ATH9K_HW_CAP_FCC_BAND_SWITCH
) &&
1817 chan
->channelFlags
!= ah
->curchan
->channelFlags
)
1820 if (!ath9k_hw_check_alive(ah
))
1824 * For AR9462, make sure that calibration data for
1825 * re-using are present.
1827 if (AR_SREV_9462(ah
) && (ah
->caldata
&&
1828 (!test_bit(TXIQCAL_DONE
, &ah
->caldata
->cal_flags
) ||
1829 !test_bit(TXCLCAL_DONE
, &ah
->caldata
->cal_flags
) ||
1830 !test_bit(RTT_DONE
, &ah
->caldata
->cal_flags
))))
1833 ath_dbg(common
, RESET
, "FastChannelChange for %d -> %d\n",
1834 ah
->curchan
->channel
, chan
->channel
);
1836 ret
= ath9k_hw_channel_change(ah
, chan
);
1840 if (ath9k_hw_mci_is_enabled(ah
))
1841 ar9003_mci_2g5g_switch(ah
, false);
1843 ath9k_hw_loadnf(ah
, ah
->curchan
);
1844 ath9k_hw_start_nfcal(ah
, true);
1846 if (AR_SREV_9271(ah
))
1847 ar9002_hw_load_ani_reg(ah
, chan
);
1854 int ath9k_hw_reset(struct ath_hw
*ah
, struct ath9k_channel
*chan
,
1855 struct ath9k_hw_cal_data
*caldata
, bool fastcc
)
1857 struct ath_common
*common
= ath9k_hw_common(ah
);
1863 bool start_mci_reset
= false;
1864 bool save_fullsleep
= ah
->chip_fullsleep
;
1866 if (ath9k_hw_mci_is_enabled(ah
)) {
1867 start_mci_reset
= ar9003_mci_start_reset(ah
, chan
);
1868 if (start_mci_reset
)
1872 if (!ath9k_hw_setpower(ah
, ATH9K_PM_AWAKE
))
1875 if (ah
->curchan
&& !ah
->chip_fullsleep
)
1876 ath9k_hw_getnf(ah
, ah
->curchan
);
1878 ah
->caldata
= caldata
;
1879 if (caldata
&& (chan
->channel
!= caldata
->channel
||
1880 chan
->channelFlags
!= caldata
->channelFlags
)) {
1881 /* Operating channel changed, reset channel calibration data */
1882 memset(caldata
, 0, sizeof(*caldata
));
1883 ath9k_init_nfcal_hist_buffer(ah
, chan
);
1884 } else if (caldata
) {
1885 clear_bit(PAPRD_PACKET_SENT
, &caldata
->cal_flags
);
1887 ah
->noise
= ath9k_hw_getchan_noise(ah
, chan
, chan
->noisefloor
);
1890 r
= ath9k_hw_do_fastcc(ah
, chan
);
1895 if (ath9k_hw_mci_is_enabled(ah
))
1896 ar9003_mci_stop_bt(ah
, save_fullsleep
);
1898 saveDefAntenna
= REG_READ(ah
, AR_DEF_ANTENNA
);
1899 if (saveDefAntenna
== 0)
1902 macStaId1
= REG_READ(ah
, AR_STA_ID1
) & AR_STA_ID1_BASE_RATE_11B
;
1904 /* For chips on which RTC reset is done, save TSF before it gets cleared */
1905 if (AR_SREV_9100(ah
) ||
1906 (AR_SREV_9280(ah
) && ah
->eep_ops
->get_eeprom(ah
, EEP_OL_PWRCTRL
)))
1907 tsf
= ath9k_hw_gettsf64(ah
);
1909 saveLedState
= REG_READ(ah
, AR_CFG_LED
) &
1910 (AR_CFG_LED_ASSOC_CTL
| AR_CFG_LED_MODE_SEL
|
1911 AR_CFG_LED_BLINK_THRESH_SEL
| AR_CFG_LED_BLINK_SLOW
);
1913 ath9k_hw_mark_phy_inactive(ah
);
1915 ah
->paprd_table_write_done
= false;
1917 /* Only required on the first reset */
1918 if (AR_SREV_9271(ah
) && ah
->htc_reset_init
) {
1920 AR9271_RESET_POWER_DOWN_CONTROL
,
1921 AR9271_RADIO_RF_RST
);
1925 if (!ath9k_hw_chip_reset(ah
, chan
)) {
1926 ath_err(common
, "Chip reset failed\n");
1930 /* Only required on the first reset */
1931 if (AR_SREV_9271(ah
) && ah
->htc_reset_init
) {
1932 ah
->htc_reset_init
= false;
1934 AR9271_RESET_POWER_DOWN_CONTROL
,
1935 AR9271_GATE_MAC_CTL
);
1941 ath9k_hw_settsf64(ah
, tsf
);
1943 if (AR_SREV_9280_20_OR_LATER(ah
))
1944 REG_SET_BIT(ah
, AR_GPIO_INPUT_EN_VAL
, AR_GPIO_JTAG_DISABLE
);
1946 if (!AR_SREV_9300_20_OR_LATER(ah
))
1947 ar9002_hw_enable_async_fifo(ah
);
1949 r
= ath9k_hw_process_ini(ah
, chan
);
1953 if (ath9k_hw_mci_is_enabled(ah
))
1954 ar9003_mci_reset(ah
, false, IS_CHAN_2GHZ(chan
), save_fullsleep
);
1957 * Some AR91xx SoC devices frequently fail to accept TSF writes
1958 * right after the chip reset. When that happens, write a new
1959 * value after the initvals have been applied, with an offset
1960 * based on measured time difference
1962 if (AR_SREV_9100(ah
) && (ath9k_hw_gettsf64(ah
) < tsf
)) {
1964 ath9k_hw_settsf64(ah
, tsf
);
1967 ath9k_hw_init_mfp(ah
);
1969 ath9k_hw_set_delta_slope(ah
, chan
);
1970 ath9k_hw_spur_mitigate_freq(ah
, chan
);
1971 ah
->eep_ops
->set_board_values(ah
, chan
);
1973 ath9k_hw_reset_opmode(ah
, macStaId1
, saveDefAntenna
);
1975 r
= ath9k_hw_rf_set_freq(ah
, chan
);
1979 ath9k_hw_set_clockrate(ah
);
1981 ath9k_hw_init_queues(ah
);
1982 ath9k_hw_init_interrupt_masks(ah
, ah
->opmode
);
1983 ath9k_hw_ani_cache_ini_regs(ah
);
1984 ath9k_hw_init_qos(ah
);
1986 if (ah
->caps
.hw_caps
& ATH9K_HW_CAP_RFSILENT
)
1987 ath9k_hw_cfg_gpio_input(ah
, ah
->rfkill_gpio
);
1989 ath9k_hw_init_global_settings(ah
);
1991 if (AR_SREV_9287(ah
) && AR_SREV_9287_13_OR_LATER(ah
)) {
1992 REG_SET_BIT(ah
, AR_MAC_PCU_LOGIC_ANALYZER
,
1993 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768
);
1994 REG_RMW_FIELD(ah
, AR_AHB_MODE
, AR_AHB_CUSTOM_BURST_EN
,
1995 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL
);
1996 REG_SET_BIT(ah
, AR_PCU_MISC_MODE2
,
1997 AR_PCU_MISC_MODE2_ENABLE_AGGWEP
);
2000 REG_SET_BIT(ah
, AR_STA_ID1
, AR_STA_ID1_PRESERVE_SEQNUM
);
2002 ath9k_hw_set_dma(ah
);
2004 if (!ath9k_hw_mci_is_enabled(ah
))
2005 REG_WRITE(ah
, AR_OBS
, 8);
2007 if (ah
->config
.rx_intr_mitigation
) {
2008 REG_RMW_FIELD(ah
, AR_RIMT
, AR_RIMT_LAST
, 500);
2009 REG_RMW_FIELD(ah
, AR_RIMT
, AR_RIMT_FIRST
, 2000);
2012 if (ah
->config
.tx_intr_mitigation
) {
2013 REG_RMW_FIELD(ah
, AR_TIMT
, AR_TIMT_LAST
, 300);
2014 REG_RMW_FIELD(ah
, AR_TIMT
, AR_TIMT_FIRST
, 750);
2017 ath9k_hw_init_bb(ah
, chan
);
2020 clear_bit(TXIQCAL_DONE
, &caldata
->cal_flags
);
2021 clear_bit(TXCLCAL_DONE
, &caldata
->cal_flags
);
2023 if (!ath9k_hw_init_cal(ah
, chan
))
2026 if (ath9k_hw_mci_is_enabled(ah
) && ar9003_mci_end_reset(ah
, chan
, caldata
))
2029 ENABLE_REGWRITE_BUFFER(ah
);
2031 ath9k_hw_restore_chainmask(ah
);
2032 REG_WRITE(ah
, AR_CFG_LED
, saveLedState
| AR_CFG_SCLK_32KHZ
);
2034 REGWRITE_BUFFER_FLUSH(ah
);
2036 ath9k_hw_init_desc(ah
);
2038 if (ath9k_hw_btcoex_is_enabled(ah
))
2039 ath9k_hw_btcoex_enable(ah
);
2041 if (ath9k_hw_mci_is_enabled(ah
))
2042 ar9003_mci_check_bt(ah
);
2044 ath9k_hw_loadnf(ah
, chan
);
2045 ath9k_hw_start_nfcal(ah
, true);
2047 if (AR_SREV_9300_20_OR_LATER(ah
)) {
2048 ar9003_hw_bb_watchdog_config(ah
);
2049 ar9003_hw_disable_phy_restart(ah
);
2052 ath9k_hw_apply_gpio_override(ah
);
2054 if (AR_SREV_9565(ah
) && common
->bt_ant_diversity
)
2055 REG_SET_BIT(ah
, AR_BTCOEX_WL_LNADIV
, AR_BTCOEX_WL_LNADIV_FORCE_ON
);
2059 EXPORT_SYMBOL(ath9k_hw_reset
);
2061 /******************************/
2062 /* Power Management (Chipset) */
2063 /******************************/
2066 * Notify Power Mgt is disabled in self-generated frames.
2067 * If requested, force chip to sleep.
2069 static void ath9k_set_power_sleep(struct ath_hw
*ah
)
2071 REG_SET_BIT(ah
, AR_STA_ID1
, AR_STA_ID1_PWR_SAV
);
2073 if (AR_SREV_9462(ah
) || AR_SREV_9565(ah
)) {
2074 REG_CLR_BIT(ah
, AR_TIMER_MODE
, 0xff);
2075 REG_CLR_BIT(ah
, AR_NDP2_TIMER_MODE
, 0xff);
2076 REG_CLR_BIT(ah
, AR_SLP32_INC
, 0xfffff);
2077 /* xxx Required for WLAN only case ? */
2078 REG_WRITE(ah
, AR_MCI_INTERRUPT_RX_MSG_EN
, 0);
2083 * Clear the RTC force wake bit to allow the
2084 * mac to go to sleep.
2086 REG_CLR_BIT(ah
, AR_RTC_FORCE_WAKE
, AR_RTC_FORCE_WAKE_EN
);
2088 if (ath9k_hw_mci_is_enabled(ah
))
2091 if (!AR_SREV_9100(ah
) && !AR_SREV_9300_20_OR_LATER(ah
))
2092 REG_WRITE(ah
, AR_RC
, AR_RC_AHB
| AR_RC_HOSTIF
);
2094 /* Shutdown chip. Active low */
2095 if (!AR_SREV_5416(ah
) && !AR_SREV_9271(ah
)) {
2096 REG_CLR_BIT(ah
, AR_RTC_RESET
, AR_RTC_RESET_EN
);
2100 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
2101 if (AR_SREV_9300_20_OR_LATER(ah
))
2102 REG_WRITE(ah
, AR_WA
, ah
->WARegVal
& ~AR_WA_D3_L1_DISABLE
);
2106 * Notify Power Management is enabled in self-generating
2107 * frames. If request, set power mode of chip to
2108 * auto/normal. Duration in units of 128us (1/8 TU).
2110 static void ath9k_set_power_network_sleep(struct ath_hw
*ah
)
2112 struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
2114 REG_SET_BIT(ah
, AR_STA_ID1
, AR_STA_ID1_PWR_SAV
);
2116 if (!(pCap
->hw_caps
& ATH9K_HW_CAP_AUTOSLEEP
)) {
2117 /* Set WakeOnInterrupt bit; clear ForceWake bit */
2118 REG_WRITE(ah
, AR_RTC_FORCE_WAKE
,
2119 AR_RTC_FORCE_WAKE_ON_INT
);
2122 /* When chip goes into network sleep, it could be waken
2123 * up by MCI_INT interrupt caused by BT's HW messages
2124 * (LNA_xxx, CONT_xxx) which chould be in a very fast
2125 * rate (~100us). This will cause chip to leave and
2126 * re-enter network sleep mode frequently, which in
2127 * consequence will have WLAN MCI HW to generate lots of
2128 * SYS_WAKING and SYS_SLEEPING messages which will make
2129 * BT CPU to busy to process.
2131 if (ath9k_hw_mci_is_enabled(ah
))
2132 REG_CLR_BIT(ah
, AR_MCI_INTERRUPT_RX_MSG_EN
,
2133 AR_MCI_INTERRUPT_RX_HW_MSG_MASK
);
2135 * Clear the RTC force wake bit to allow the
2136 * mac to go to sleep.
2138 REG_CLR_BIT(ah
, AR_RTC_FORCE_WAKE
, AR_RTC_FORCE_WAKE_EN
);
2140 if (ath9k_hw_mci_is_enabled(ah
))
2144 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
2145 if (AR_SREV_9300_20_OR_LATER(ah
))
2146 REG_WRITE(ah
, AR_WA
, ah
->WARegVal
& ~AR_WA_D3_L1_DISABLE
);
2149 static bool ath9k_hw_set_power_awake(struct ath_hw
*ah
)
2154 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */
2155 if (AR_SREV_9300_20_OR_LATER(ah
)) {
2156 REG_WRITE(ah
, AR_WA
, ah
->WARegVal
);
2160 if ((REG_READ(ah
, AR_RTC_STATUS
) &
2161 AR_RTC_STATUS_M
) == AR_RTC_STATUS_SHUTDOWN
) {
2162 if (!ath9k_hw_set_reset_reg(ah
, ATH9K_RESET_POWER_ON
)) {
2165 if (!AR_SREV_9300_20_OR_LATER(ah
))
2166 ath9k_hw_init_pll(ah
, NULL
);
2168 if (AR_SREV_9100(ah
))
2169 REG_SET_BIT(ah
, AR_RTC_RESET
,
2172 REG_SET_BIT(ah
, AR_RTC_FORCE_WAKE
,
2173 AR_RTC_FORCE_WAKE_EN
);
2176 for (i
= POWER_UP_TIME
/ 50; i
> 0; i
--) {
2177 val
= REG_READ(ah
, AR_RTC_STATUS
) & AR_RTC_STATUS_M
;
2178 if (val
== AR_RTC_STATUS_ON
)
2181 REG_SET_BIT(ah
, AR_RTC_FORCE_WAKE
,
2182 AR_RTC_FORCE_WAKE_EN
);
2185 ath_err(ath9k_hw_common(ah
),
2186 "Failed to wakeup in %uus\n",
2187 POWER_UP_TIME
/ 20);
2191 if (ath9k_hw_mci_is_enabled(ah
))
2192 ar9003_mci_set_power_awake(ah
);
2194 REG_CLR_BIT(ah
, AR_STA_ID1
, AR_STA_ID1_PWR_SAV
);
2199 bool ath9k_hw_setpower(struct ath_hw
*ah
, enum ath9k_power_mode mode
)
2201 struct ath_common
*common
= ath9k_hw_common(ah
);
2203 static const char *modes
[] = {
2210 if (ah
->power_mode
== mode
)
2213 ath_dbg(common
, RESET
, "%s -> %s\n",
2214 modes
[ah
->power_mode
], modes
[mode
]);
2217 case ATH9K_PM_AWAKE
:
2218 status
= ath9k_hw_set_power_awake(ah
);
2220 case ATH9K_PM_FULL_SLEEP
:
2221 if (ath9k_hw_mci_is_enabled(ah
))
2222 ar9003_mci_set_full_sleep(ah
);
2224 ath9k_set_power_sleep(ah
);
2225 ah
->chip_fullsleep
= true;
2227 case ATH9K_PM_NETWORK_SLEEP
:
2228 ath9k_set_power_network_sleep(ah
);
2231 ath_err(common
, "Unknown power mode %u\n", mode
);
2234 ah
->power_mode
= mode
;
2237 * XXX: If this warning never comes up after a while then
2238 * simply keep the ATH_DBG_WARN_ON_ONCE() but make
2239 * ath9k_hw_setpower() return type void.
2242 if (!(ah
->ah_flags
& AH_UNPLUGGED
))
2243 ATH_DBG_WARN_ON_ONCE(!status
);
2247 EXPORT_SYMBOL(ath9k_hw_setpower
);
2249 /*******************/
2250 /* Beacon Handling */
2251 /*******************/
2253 void ath9k_hw_beaconinit(struct ath_hw
*ah
, u32 next_beacon
, u32 beacon_period
)
2257 ENABLE_REGWRITE_BUFFER(ah
);
2259 switch (ah
->opmode
) {
2260 case NL80211_IFTYPE_ADHOC
:
2261 REG_SET_BIT(ah
, AR_TXCFG
,
2262 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY
);
2263 REG_WRITE(ah
, AR_NEXT_NDP_TIMER
, next_beacon
+
2264 TU_TO_USEC(ah
->atim_window
? ah
->atim_window
: 1));
2265 flags
|= AR_NDP_TIMER_EN
;
2266 case NL80211_IFTYPE_MESH_POINT
:
2267 case NL80211_IFTYPE_AP
:
2268 REG_WRITE(ah
, AR_NEXT_TBTT_TIMER
, next_beacon
);
2269 REG_WRITE(ah
, AR_NEXT_DMA_BEACON_ALERT
, next_beacon
-
2270 TU_TO_USEC(ah
->config
.dma_beacon_response_time
));
2271 REG_WRITE(ah
, AR_NEXT_SWBA
, next_beacon
-
2272 TU_TO_USEC(ah
->config
.sw_beacon_response_time
));
2274 AR_TBTT_TIMER_EN
| AR_DBA_TIMER_EN
| AR_SWBA_TIMER_EN
;
2277 ath_dbg(ath9k_hw_common(ah
), BEACON
,
2278 "%s: unsupported opmode: %d\n", __func__
, ah
->opmode
);
2283 REG_WRITE(ah
, AR_BEACON_PERIOD
, beacon_period
);
2284 REG_WRITE(ah
, AR_DMA_BEACON_PERIOD
, beacon_period
);
2285 REG_WRITE(ah
, AR_SWBA_PERIOD
, beacon_period
);
2286 REG_WRITE(ah
, AR_NDP_PERIOD
, beacon_period
);
2288 REGWRITE_BUFFER_FLUSH(ah
);
2290 REG_SET_BIT(ah
, AR_TIMER_MODE
, flags
);
2292 EXPORT_SYMBOL(ath9k_hw_beaconinit
);
2294 void ath9k_hw_set_sta_beacon_timers(struct ath_hw
*ah
,
2295 const struct ath9k_beacon_state
*bs
)
2297 u32 nextTbtt
, beaconintval
, dtimperiod
, beacontimeout
;
2298 struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
2299 struct ath_common
*common
= ath9k_hw_common(ah
);
2301 ENABLE_REGWRITE_BUFFER(ah
);
2303 REG_WRITE(ah
, AR_NEXT_TBTT_TIMER
, TU_TO_USEC(bs
->bs_nexttbtt
));
2305 REG_WRITE(ah
, AR_BEACON_PERIOD
,
2306 TU_TO_USEC(bs
->bs_intval
));
2307 REG_WRITE(ah
, AR_DMA_BEACON_PERIOD
,
2308 TU_TO_USEC(bs
->bs_intval
));
2310 REGWRITE_BUFFER_FLUSH(ah
);
2312 REG_RMW_FIELD(ah
, AR_RSSI_THR
,
2313 AR_RSSI_THR_BM_THR
, bs
->bs_bmissthreshold
);
2315 beaconintval
= bs
->bs_intval
;
2317 if (bs
->bs_sleepduration
> beaconintval
)
2318 beaconintval
= bs
->bs_sleepduration
;
2320 dtimperiod
= bs
->bs_dtimperiod
;
2321 if (bs
->bs_sleepduration
> dtimperiod
)
2322 dtimperiod
= bs
->bs_sleepduration
;
2324 if (beaconintval
== dtimperiod
)
2325 nextTbtt
= bs
->bs_nextdtim
;
2327 nextTbtt
= bs
->bs_nexttbtt
;
2329 ath_dbg(common
, BEACON
, "next DTIM %d\n", bs
->bs_nextdtim
);
2330 ath_dbg(common
, BEACON
, "next beacon %d\n", nextTbtt
);
2331 ath_dbg(common
, BEACON
, "beacon period %d\n", beaconintval
);
2332 ath_dbg(common
, BEACON
, "DTIM period %d\n", dtimperiod
);
2334 ENABLE_REGWRITE_BUFFER(ah
);
2336 REG_WRITE(ah
, AR_NEXT_DTIM
,
2337 TU_TO_USEC(bs
->bs_nextdtim
- SLEEP_SLOP
));
2338 REG_WRITE(ah
, AR_NEXT_TIM
, TU_TO_USEC(nextTbtt
- SLEEP_SLOP
));
2340 REG_WRITE(ah
, AR_SLEEP1
,
2341 SM((CAB_TIMEOUT_VAL
<< 3), AR_SLEEP1_CAB_TIMEOUT
)
2342 | AR_SLEEP1_ASSUME_DTIM
);
2344 if (pCap
->hw_caps
& ATH9K_HW_CAP_AUTOSLEEP
)
2345 beacontimeout
= (BEACON_TIMEOUT_VAL
<< 3);
2347 beacontimeout
= MIN_BEACON_TIMEOUT_VAL
;
2349 REG_WRITE(ah
, AR_SLEEP2
,
2350 SM(beacontimeout
, AR_SLEEP2_BEACON_TIMEOUT
));
2352 REG_WRITE(ah
, AR_TIM_PERIOD
, TU_TO_USEC(beaconintval
));
2353 REG_WRITE(ah
, AR_DTIM_PERIOD
, TU_TO_USEC(dtimperiod
));
2355 REGWRITE_BUFFER_FLUSH(ah
);
2357 REG_SET_BIT(ah
, AR_TIMER_MODE
,
2358 AR_TBTT_TIMER_EN
| AR_TIM_TIMER_EN
|
2361 /* TSF Out of Range Threshold */
2362 REG_WRITE(ah
, AR_TSFOOR_THRESHOLD
, bs
->bs_tsfoor_threshold
);
2364 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers
);
2366 /*******************/
2367 /* HW Capabilities */
2368 /*******************/
2370 static u8
fixup_chainmask(u8 chip_chainmask
, u8 eeprom_chainmask
)
2372 eeprom_chainmask
&= chip_chainmask
;
2373 if (eeprom_chainmask
)
2374 return eeprom_chainmask
;
2376 return chip_chainmask
;
2380 * ath9k_hw_dfs_tested - checks if DFS has been tested with used chipset
2381 * @ah: the atheros hardware data structure
2383 * We enable DFS support upstream on chipsets which have passed a series
2384 * of tests. The testing requirements are going to be documented. Desired
2385 * test requirements are documented at:
2387 * http://wireless.kernel.org/en/users/Drivers/ath9k/dfs
2389 * Once a new chipset gets properly tested an individual commit can be used
2390 * to document the testing for DFS for that chipset.
2392 static bool ath9k_hw_dfs_tested(struct ath_hw
*ah
)
2395 switch (ah
->hw_version
.macVersion
) {
2396 /* for temporary testing DFS with 9280 */
2397 case AR_SREV_VERSION_9280
:
2398 /* AR9580 will likely be our first target to get testing on */
2399 case AR_SREV_VERSION_9580
:
2406 int ath9k_hw_fill_cap_info(struct ath_hw
*ah
)
2408 struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
2409 struct ath_regulatory
*regulatory
= ath9k_hw_regulatory(ah
);
2410 struct ath_common
*common
= ath9k_hw_common(ah
);
2411 unsigned int chip_chainmask
;
2414 u8 ant_div_ctl1
, tx_chainmask
, rx_chainmask
;
2416 eeval
= ah
->eep_ops
->get_eeprom(ah
, EEP_REG_0
);
2417 regulatory
->current_rd
= eeval
;
2419 if (ah
->opmode
!= NL80211_IFTYPE_AP
&&
2420 ah
->hw_version
.subvendorid
== AR_SUBVENDOR_ID_NEW_A
) {
2421 if (regulatory
->current_rd
== 0x64 ||
2422 regulatory
->current_rd
== 0x65)
2423 regulatory
->current_rd
+= 5;
2424 else if (regulatory
->current_rd
== 0x41)
2425 regulatory
->current_rd
= 0x43;
2426 ath_dbg(common
, REGULATORY
, "regdomain mapped to 0x%x\n",
2427 regulatory
->current_rd
);
2430 eeval
= ah
->eep_ops
->get_eeprom(ah
, EEP_OP_MODE
);
2431 if ((eeval
& (AR5416_OPFLAGS_11G
| AR5416_OPFLAGS_11A
)) == 0) {
2433 "no band has been marked as supported in EEPROM\n");
2437 if (eeval
& AR5416_OPFLAGS_11A
)
2438 pCap
->hw_caps
|= ATH9K_HW_CAP_5GHZ
;
2440 if (eeval
& AR5416_OPFLAGS_11G
)
2441 pCap
->hw_caps
|= ATH9K_HW_CAP_2GHZ
;
2443 if (AR_SREV_9485(ah
) ||
2448 else if (AR_SREV_9462(ah
))
2450 else if (!AR_SREV_9280_20_OR_LATER(ah
))
2452 else if (!AR_SREV_9300_20_OR_LATER(ah
) || AR_SREV_9340(ah
))
2457 pCap
->tx_chainmask
= ah
->eep_ops
->get_eeprom(ah
, EEP_TX_MASK
);
2459 * For AR9271 we will temporarilly uses the rx chainmax as read from
2462 if ((ah
->hw_version
.devid
== AR5416_DEVID_PCI
) &&
2463 !(eeval
& AR5416_OPFLAGS_11A
) &&
2464 !(AR_SREV_9271(ah
)))
2465 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
2466 pCap
->rx_chainmask
= ath9k_hw_gpio_get(ah
, 0) ? 0x5 : 0x7;
2467 else if (AR_SREV_9100(ah
))
2468 pCap
->rx_chainmask
= 0x7;
2470 /* Use rx_chainmask from EEPROM. */
2471 pCap
->rx_chainmask
= ah
->eep_ops
->get_eeprom(ah
, EEP_RX_MASK
);
2473 pCap
->tx_chainmask
= fixup_chainmask(chip_chainmask
, pCap
->tx_chainmask
);
2474 pCap
->rx_chainmask
= fixup_chainmask(chip_chainmask
, pCap
->rx_chainmask
);
2475 ah
->txchainmask
= pCap
->tx_chainmask
;
2476 ah
->rxchainmask
= pCap
->rx_chainmask
;
2478 ah
->misc_mode
|= AR_PCU_MIC_NEW_LOC_ENA
;
2480 /* enable key search for every frame in an aggregate */
2481 if (AR_SREV_9300_20_OR_LATER(ah
))
2482 ah
->misc_mode
|= AR_PCU_ALWAYS_PERFORM_KEYSEARCH
;
2484 common
->crypt_caps
|= ATH_CRYPT_CAP_CIPHER_AESCCM
;
2486 if (ah
->hw_version
.devid
!= AR2427_DEVID_PCIE
)
2487 pCap
->hw_caps
|= ATH9K_HW_CAP_HT
;
2489 pCap
->hw_caps
&= ~ATH9K_HW_CAP_HT
;
2491 if (AR_SREV_9271(ah
))
2492 pCap
->num_gpio_pins
= AR9271_NUM_GPIO
;
2493 else if (AR_DEVID_7010(ah
))
2494 pCap
->num_gpio_pins
= AR7010_NUM_GPIO
;
2495 else if (AR_SREV_9300_20_OR_LATER(ah
))
2496 pCap
->num_gpio_pins
= AR9300_NUM_GPIO
;
2497 else if (AR_SREV_9287_11_OR_LATER(ah
))
2498 pCap
->num_gpio_pins
= AR9287_NUM_GPIO
;
2499 else if (AR_SREV_9285_12_OR_LATER(ah
))
2500 pCap
->num_gpio_pins
= AR9285_NUM_GPIO
;
2501 else if (AR_SREV_9280_20_OR_LATER(ah
))
2502 pCap
->num_gpio_pins
= AR928X_NUM_GPIO
;
2504 pCap
->num_gpio_pins
= AR_NUM_GPIO
;
2506 if (AR_SREV_9160_10_OR_LATER(ah
) || AR_SREV_9100(ah
))
2507 pCap
->rts_aggr_limit
= ATH_AMPDU_LIMIT_MAX
;
2509 pCap
->rts_aggr_limit
= (8 * 1024);
2511 #ifdef CONFIG_ATH9K_RFKILL
2512 ah
->rfsilent
= ah
->eep_ops
->get_eeprom(ah
, EEP_RF_SILENT
);
2513 if (ah
->rfsilent
& EEP_RFSILENT_ENABLED
) {
2515 MS(ah
->rfsilent
, EEP_RFSILENT_GPIO_SEL
);
2516 ah
->rfkill_polarity
=
2517 MS(ah
->rfsilent
, EEP_RFSILENT_POLARITY
);
2519 pCap
->hw_caps
|= ATH9K_HW_CAP_RFSILENT
;
2522 if (AR_SREV_9271(ah
) || AR_SREV_9300_20_OR_LATER(ah
))
2523 pCap
->hw_caps
|= ATH9K_HW_CAP_AUTOSLEEP
;
2525 pCap
->hw_caps
&= ~ATH9K_HW_CAP_AUTOSLEEP
;
2527 if (AR_SREV_9280(ah
) || AR_SREV_9285(ah
))
2528 pCap
->hw_caps
&= ~ATH9K_HW_CAP_4KB_SPLITTRANS
;
2530 pCap
->hw_caps
|= ATH9K_HW_CAP_4KB_SPLITTRANS
;
2532 if (AR_SREV_9300_20_OR_LATER(ah
)) {
2533 pCap
->hw_caps
|= ATH9K_HW_CAP_EDMA
| ATH9K_HW_CAP_FASTCLOCK
;
2534 if (!AR_SREV_9330(ah
) && !AR_SREV_9485(ah
) && !AR_SREV_9565(ah
))
2535 pCap
->hw_caps
|= ATH9K_HW_CAP_LDPC
;
2537 pCap
->rx_hp_qdepth
= ATH9K_HW_RX_HP_QDEPTH
;
2538 pCap
->rx_lp_qdepth
= ATH9K_HW_RX_LP_QDEPTH
;
2539 pCap
->rx_status_len
= sizeof(struct ar9003_rxs
);
2540 pCap
->tx_desc_len
= sizeof(struct ar9003_txc
);
2541 pCap
->txs_len
= sizeof(struct ar9003_txs
);
2543 pCap
->tx_desc_len
= sizeof(struct ath_desc
);
2544 if (AR_SREV_9280_20(ah
))
2545 pCap
->hw_caps
|= ATH9K_HW_CAP_FASTCLOCK
;
2548 if (AR_SREV_9300_20_OR_LATER(ah
))
2549 pCap
->hw_caps
|= ATH9K_HW_CAP_RAC_SUPPORTED
;
2551 if (AR_SREV_9300_20_OR_LATER(ah
))
2552 ah
->ent_mode
= REG_READ(ah
, AR_ENT_OTP
);
2554 if (AR_SREV_9287_11_OR_LATER(ah
) || AR_SREV_9271(ah
))
2555 pCap
->hw_caps
|= ATH9K_HW_CAP_SGI_20
;
2557 if (AR_SREV_9285(ah
)) {
2558 if (ah
->eep_ops
->get_eeprom(ah
, EEP_MODAL_VER
) >= 3) {
2560 ah
->eep_ops
->get_eeprom(ah
, EEP_ANT_DIV_CTL1
);
2561 if ((ant_div_ctl1
& 0x1) && ((ant_div_ctl1
>> 3) & 0x1)) {
2562 pCap
->hw_caps
|= ATH9K_HW_CAP_ANT_DIV_COMB
;
2563 ath_info(common
, "Enable LNA combining\n");
2568 if (AR_SREV_9300_20_OR_LATER(ah
)) {
2569 if (ah
->eep_ops
->get_eeprom(ah
, EEP_CHAIN_MASK_REDUCE
))
2570 pCap
->hw_caps
|= ATH9K_HW_CAP_APM
;
2573 if (AR_SREV_9330(ah
) || AR_SREV_9485(ah
) || AR_SREV_9565(ah
)) {
2574 ant_div_ctl1
= ah
->eep_ops
->get_eeprom(ah
, EEP_ANT_DIV_CTL1
);
2575 if ((ant_div_ctl1
>> 0x6) == 0x3) {
2576 pCap
->hw_caps
|= ATH9K_HW_CAP_ANT_DIV_COMB
;
2577 ath_info(common
, "Enable LNA combining\n");
2581 if (ath9k_hw_dfs_tested(ah
))
2582 pCap
->hw_caps
|= ATH9K_HW_CAP_DFS
;
2584 tx_chainmask
= pCap
->tx_chainmask
;
2585 rx_chainmask
= pCap
->rx_chainmask
;
2586 while (tx_chainmask
|| rx_chainmask
) {
2587 if (tx_chainmask
& BIT(0))
2588 pCap
->max_txchains
++;
2589 if (rx_chainmask
& BIT(0))
2590 pCap
->max_rxchains
++;
2596 if (AR_SREV_9462(ah
) || AR_SREV_9565(ah
)) {
2597 if (!(ah
->ent_mode
& AR_ENT_OTP_49GHZ_DISABLE
))
2598 pCap
->hw_caps
|= ATH9K_HW_CAP_MCI
;
2600 if (AR_SREV_9462_20_OR_LATER(ah
))
2601 pCap
->hw_caps
|= ATH9K_HW_CAP_RTT
;
2604 if (AR_SREV_9462(ah
))
2605 pCap
->hw_caps
|= ATH9K_HW_WOW_DEVICE_CAPABLE
;
2607 if (AR_SREV_9300_20_OR_LATER(ah
) &&
2608 ah
->eep_ops
->get_eeprom(ah
, EEP_PAPRD
))
2609 pCap
->hw_caps
|= ATH9K_HW_CAP_PAPRD
;
2612 * Fast channel change across bands is available
2613 * only for AR9462 and AR9565.
2615 if (AR_SREV_9462(ah
) || AR_SREV_9565(ah
))
2616 pCap
->hw_caps
|= ATH9K_HW_CAP_FCC_BAND_SWITCH
;
2621 /****************************/
2622 /* GPIO / RFKILL / Antennae */
2623 /****************************/
2625 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw
*ah
,
2629 u32 gpio_shift
, tmp
;
2632 addr
= AR_GPIO_OUTPUT_MUX3
;
2634 addr
= AR_GPIO_OUTPUT_MUX2
;
2636 addr
= AR_GPIO_OUTPUT_MUX1
;
2638 gpio_shift
= (gpio
% 6) * 5;
2640 if (AR_SREV_9280_20_OR_LATER(ah
)
2641 || (addr
!= AR_GPIO_OUTPUT_MUX1
)) {
2642 REG_RMW(ah
, addr
, (type
<< gpio_shift
),
2643 (0x1f << gpio_shift
));
2645 tmp
= REG_READ(ah
, addr
);
2646 tmp
= ((tmp
& 0x1F0) << 1) | (tmp
& ~0x1F0);
2647 tmp
&= ~(0x1f << gpio_shift
);
2648 tmp
|= (type
<< gpio_shift
);
2649 REG_WRITE(ah
, addr
, tmp
);
2653 void ath9k_hw_cfg_gpio_input(struct ath_hw
*ah
, u32 gpio
)
2657 BUG_ON(gpio
>= ah
->caps
.num_gpio_pins
);
2659 if (AR_DEVID_7010(ah
)) {
2661 REG_RMW(ah
, AR7010_GPIO_OE
,
2662 (AR7010_GPIO_OE_AS_INPUT
<< gpio_shift
),
2663 (AR7010_GPIO_OE_MASK
<< gpio_shift
));
2667 gpio_shift
= gpio
<< 1;
2670 (AR_GPIO_OE_OUT_DRV_NO
<< gpio_shift
),
2671 (AR_GPIO_OE_OUT_DRV
<< gpio_shift
));
2673 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input
);
2675 u32
ath9k_hw_gpio_get(struct ath_hw
*ah
, u32 gpio
)
2677 #define MS_REG_READ(x, y) \
2678 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2680 if (gpio
>= ah
->caps
.num_gpio_pins
)
2683 if (AR_DEVID_7010(ah
)) {
2685 val
= REG_READ(ah
, AR7010_GPIO_IN
);
2686 return (MS(val
, AR7010_GPIO_IN_VAL
) & AR_GPIO_BIT(gpio
)) == 0;
2687 } else if (AR_SREV_9300_20_OR_LATER(ah
))
2688 return (MS(REG_READ(ah
, AR_GPIO_IN
), AR9300_GPIO_IN_VAL
) &
2689 AR_GPIO_BIT(gpio
)) != 0;
2690 else if (AR_SREV_9271(ah
))
2691 return MS_REG_READ(AR9271
, gpio
) != 0;
2692 else if (AR_SREV_9287_11_OR_LATER(ah
))
2693 return MS_REG_READ(AR9287
, gpio
) != 0;
2694 else if (AR_SREV_9285_12_OR_LATER(ah
))
2695 return MS_REG_READ(AR9285
, gpio
) != 0;
2696 else if (AR_SREV_9280_20_OR_LATER(ah
))
2697 return MS_REG_READ(AR928X
, gpio
) != 0;
2699 return MS_REG_READ(AR
, gpio
) != 0;
2701 EXPORT_SYMBOL(ath9k_hw_gpio_get
);
2703 void ath9k_hw_cfg_output(struct ath_hw
*ah
, u32 gpio
,
2708 if (AR_DEVID_7010(ah
)) {
2710 REG_RMW(ah
, AR7010_GPIO_OE
,
2711 (AR7010_GPIO_OE_AS_OUTPUT
<< gpio_shift
),
2712 (AR7010_GPIO_OE_MASK
<< gpio_shift
));
2716 ath9k_hw_gpio_cfg_output_mux(ah
, gpio
, ah_signal_type
);
2717 gpio_shift
= 2 * gpio
;
2720 (AR_GPIO_OE_OUT_DRV_ALL
<< gpio_shift
),
2721 (AR_GPIO_OE_OUT_DRV
<< gpio_shift
));
2723 EXPORT_SYMBOL(ath9k_hw_cfg_output
);
2725 void ath9k_hw_set_gpio(struct ath_hw
*ah
, u32 gpio
, u32 val
)
2727 if (AR_DEVID_7010(ah
)) {
2729 REG_RMW(ah
, AR7010_GPIO_OUT
, ((val
&1) << gpio
),
2734 if (AR_SREV_9271(ah
))
2737 REG_RMW(ah
, AR_GPIO_IN_OUT
, ((val
& 1) << gpio
),
2740 EXPORT_SYMBOL(ath9k_hw_set_gpio
);
2742 void ath9k_hw_setantenna(struct ath_hw
*ah
, u32 antenna
)
2744 REG_WRITE(ah
, AR_DEF_ANTENNA
, (antenna
& 0x7));
2746 EXPORT_SYMBOL(ath9k_hw_setantenna
);
2748 /*********************/
2749 /* General Operation */
2750 /*********************/
2752 u32
ath9k_hw_getrxfilter(struct ath_hw
*ah
)
2754 u32 bits
= REG_READ(ah
, AR_RX_FILTER
);
2755 u32 phybits
= REG_READ(ah
, AR_PHY_ERR
);
2757 if (phybits
& AR_PHY_ERR_RADAR
)
2758 bits
|= ATH9K_RX_FILTER_PHYRADAR
;
2759 if (phybits
& (AR_PHY_ERR_OFDM_TIMING
| AR_PHY_ERR_CCK_TIMING
))
2760 bits
|= ATH9K_RX_FILTER_PHYERR
;
2764 EXPORT_SYMBOL(ath9k_hw_getrxfilter
);
2766 void ath9k_hw_setrxfilter(struct ath_hw
*ah
, u32 bits
)
2770 ENABLE_REGWRITE_BUFFER(ah
);
2772 if (AR_SREV_9462(ah
) || AR_SREV_9565(ah
))
2773 bits
|= ATH9K_RX_FILTER_CONTROL_WRAPPER
;
2775 REG_WRITE(ah
, AR_RX_FILTER
, bits
);
2778 if (bits
& ATH9K_RX_FILTER_PHYRADAR
)
2779 phybits
|= AR_PHY_ERR_RADAR
;
2780 if (bits
& ATH9K_RX_FILTER_PHYERR
)
2781 phybits
|= AR_PHY_ERR_OFDM_TIMING
| AR_PHY_ERR_CCK_TIMING
;
2782 REG_WRITE(ah
, AR_PHY_ERR
, phybits
);
2785 REG_SET_BIT(ah
, AR_RXCFG
, AR_RXCFG_ZLFDMA
);
2787 REG_CLR_BIT(ah
, AR_RXCFG
, AR_RXCFG_ZLFDMA
);
2789 REGWRITE_BUFFER_FLUSH(ah
);
2791 EXPORT_SYMBOL(ath9k_hw_setrxfilter
);
2793 bool ath9k_hw_phy_disable(struct ath_hw
*ah
)
2795 if (ath9k_hw_mci_is_enabled(ah
))
2796 ar9003_mci_bt_gain_ctrl(ah
);
2798 if (!ath9k_hw_set_reset_reg(ah
, ATH9K_RESET_WARM
))
2801 ath9k_hw_init_pll(ah
, NULL
);
2802 ah
->htc_reset_init
= true;
2805 EXPORT_SYMBOL(ath9k_hw_phy_disable
);
2807 bool ath9k_hw_disable(struct ath_hw
*ah
)
2809 if (!ath9k_hw_setpower(ah
, ATH9K_PM_AWAKE
))
2812 if (!ath9k_hw_set_reset_reg(ah
, ATH9K_RESET_COLD
))
2815 ath9k_hw_init_pll(ah
, NULL
);
2818 EXPORT_SYMBOL(ath9k_hw_disable
);
2820 static int get_antenna_gain(struct ath_hw
*ah
, struct ath9k_channel
*chan
)
2822 enum eeprom_param gain_param
;
2824 if (IS_CHAN_2GHZ(chan
))
2825 gain_param
= EEP_ANTENNA_GAIN_2G
;
2827 gain_param
= EEP_ANTENNA_GAIN_5G
;
2829 return ah
->eep_ops
->get_eeprom(ah
, gain_param
);
2832 void ath9k_hw_apply_txpower(struct ath_hw
*ah
, struct ath9k_channel
*chan
,
2835 struct ath_regulatory
*reg
= ath9k_hw_regulatory(ah
);
2836 struct ieee80211_channel
*channel
;
2837 int chan_pwr
, new_pwr
, max_gain
;
2838 int ant_gain
, ant_reduction
= 0;
2843 channel
= chan
->chan
;
2844 chan_pwr
= min_t(int, channel
->max_power
* 2, MAX_RATE_POWER
);
2845 new_pwr
= min_t(int, chan_pwr
, reg
->power_limit
);
2846 max_gain
= chan_pwr
- new_pwr
+ channel
->max_antenna_gain
* 2;
2848 ant_gain
= get_antenna_gain(ah
, chan
);
2849 if (ant_gain
> max_gain
)
2850 ant_reduction
= ant_gain
- max_gain
;
2852 ah
->eep_ops
->set_txpower(ah
, chan
,
2853 ath9k_regd_get_ctl(reg
, chan
),
2854 ant_reduction
, new_pwr
, test
);
2857 void ath9k_hw_set_txpowerlimit(struct ath_hw
*ah
, u32 limit
, bool test
)
2859 struct ath_regulatory
*reg
= ath9k_hw_regulatory(ah
);
2860 struct ath9k_channel
*chan
= ah
->curchan
;
2861 struct ieee80211_channel
*channel
= chan
->chan
;
2863 reg
->power_limit
= min_t(u32
, limit
, MAX_RATE_POWER
);
2865 channel
->max_power
= MAX_RATE_POWER
/ 2;
2867 ath9k_hw_apply_txpower(ah
, chan
, test
);
2870 channel
->max_power
= DIV_ROUND_UP(reg
->max_power_level
, 2);
2872 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit
);
2874 void ath9k_hw_setopmode(struct ath_hw
*ah
)
2876 ath9k_hw_set_operating_mode(ah
, ah
->opmode
);
2878 EXPORT_SYMBOL(ath9k_hw_setopmode
);
2880 void ath9k_hw_setmcastfilter(struct ath_hw
*ah
, u32 filter0
, u32 filter1
)
2882 REG_WRITE(ah
, AR_MCAST_FIL0
, filter0
);
2883 REG_WRITE(ah
, AR_MCAST_FIL1
, filter1
);
2885 EXPORT_SYMBOL(ath9k_hw_setmcastfilter
);
2887 void ath9k_hw_write_associd(struct ath_hw
*ah
)
2889 struct ath_common
*common
= ath9k_hw_common(ah
);
2891 REG_WRITE(ah
, AR_BSS_ID0
, get_unaligned_le32(common
->curbssid
));
2892 REG_WRITE(ah
, AR_BSS_ID1
, get_unaligned_le16(common
->curbssid
+ 4) |
2893 ((common
->curaid
& 0x3fff) << AR_BSS_ID1_AID_S
));
2895 EXPORT_SYMBOL(ath9k_hw_write_associd
);
2897 #define ATH9K_MAX_TSF_READ 10
2899 u64
ath9k_hw_gettsf64(struct ath_hw
*ah
)
2901 u32 tsf_lower
, tsf_upper1
, tsf_upper2
;
2904 tsf_upper1
= REG_READ(ah
, AR_TSF_U32
);
2905 for (i
= 0; i
< ATH9K_MAX_TSF_READ
; i
++) {
2906 tsf_lower
= REG_READ(ah
, AR_TSF_L32
);
2907 tsf_upper2
= REG_READ(ah
, AR_TSF_U32
);
2908 if (tsf_upper2
== tsf_upper1
)
2910 tsf_upper1
= tsf_upper2
;
2913 WARN_ON( i
== ATH9K_MAX_TSF_READ
);
2915 return (((u64
)tsf_upper1
<< 32) | tsf_lower
);
2917 EXPORT_SYMBOL(ath9k_hw_gettsf64
);
2919 void ath9k_hw_settsf64(struct ath_hw
*ah
, u64 tsf64
)
2921 REG_WRITE(ah
, AR_TSF_L32
, tsf64
& 0xffffffff);
2922 REG_WRITE(ah
, AR_TSF_U32
, (tsf64
>> 32) & 0xffffffff);
2924 EXPORT_SYMBOL(ath9k_hw_settsf64
);
2926 void ath9k_hw_reset_tsf(struct ath_hw
*ah
)
2928 if (!ath9k_hw_wait(ah
, AR_SLP32_MODE
, AR_SLP32_TSF_WRITE_STATUS
, 0,
2929 AH_TSF_WRITE_TIMEOUT
))
2930 ath_dbg(ath9k_hw_common(ah
), RESET
,
2931 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
2933 REG_WRITE(ah
, AR_RESET_TSF
, AR_RESET_TSF_ONCE
);
2935 EXPORT_SYMBOL(ath9k_hw_reset_tsf
);
2937 void ath9k_hw_set_tsfadjust(struct ath_hw
*ah
, bool set
)
2940 ah
->misc_mode
|= AR_PCU_TX_ADD_TSF
;
2942 ah
->misc_mode
&= ~AR_PCU_TX_ADD_TSF
;
2944 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust
);
2946 void ath9k_hw_set11nmac2040(struct ath_hw
*ah
, struct ath9k_channel
*chan
)
2950 if (IS_CHAN_HT40(chan
) && !ah
->config
.cwm_ignore_extcca
)
2951 macmode
= AR_2040_JOINED_RX_CLEAR
;
2955 REG_WRITE(ah
, AR_2040_MODE
, macmode
);
2958 /* HW Generic timers configuration */
2960 static const struct ath_gen_timer_configuration gen_tmr_configuration
[] =
2962 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
2963 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
2964 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
2965 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
2966 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
2967 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
2968 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
2969 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
2970 {AR_NEXT_NDP2_TIMER
, AR_NDP2_PERIOD
, AR_NDP2_TIMER_MODE
, 0x0001},
2971 {AR_NEXT_NDP2_TIMER
+ 1*4, AR_NDP2_PERIOD
+ 1*4,
2972 AR_NDP2_TIMER_MODE
, 0x0002},
2973 {AR_NEXT_NDP2_TIMER
+ 2*4, AR_NDP2_PERIOD
+ 2*4,
2974 AR_NDP2_TIMER_MODE
, 0x0004},
2975 {AR_NEXT_NDP2_TIMER
+ 3*4, AR_NDP2_PERIOD
+ 3*4,
2976 AR_NDP2_TIMER_MODE
, 0x0008},
2977 {AR_NEXT_NDP2_TIMER
+ 4*4, AR_NDP2_PERIOD
+ 4*4,
2978 AR_NDP2_TIMER_MODE
, 0x0010},
2979 {AR_NEXT_NDP2_TIMER
+ 5*4, AR_NDP2_PERIOD
+ 5*4,
2980 AR_NDP2_TIMER_MODE
, 0x0020},
2981 {AR_NEXT_NDP2_TIMER
+ 6*4, AR_NDP2_PERIOD
+ 6*4,
2982 AR_NDP2_TIMER_MODE
, 0x0040},
2983 {AR_NEXT_NDP2_TIMER
+ 7*4, AR_NDP2_PERIOD
+ 7*4,
2984 AR_NDP2_TIMER_MODE
, 0x0080}
2987 /* HW generic timer primitives */
2989 /* compute and clear index of rightmost 1 */
2990 static u32
rightmost_index(struct ath_gen_timer_table
*timer_table
, u32
*mask
)
3000 return timer_table
->gen_timer_index
[b
];
3003 u32
ath9k_hw_gettsf32(struct ath_hw
*ah
)
3005 return REG_READ(ah
, AR_TSF_L32
);
3007 EXPORT_SYMBOL(ath9k_hw_gettsf32
);
3009 struct ath_gen_timer
*ath_gen_timer_alloc(struct ath_hw
*ah
,
3010 void (*trigger
)(void *),
3011 void (*overflow
)(void *),
3015 struct ath_gen_timer_table
*timer_table
= &ah
->hw_gen_timers
;
3016 struct ath_gen_timer
*timer
;
3018 timer
= kzalloc(sizeof(struct ath_gen_timer
), GFP_KERNEL
);
3022 /* allocate a hardware generic timer slot */
3023 timer_table
->timers
[timer_index
] = timer
;
3024 timer
->index
= timer_index
;
3025 timer
->trigger
= trigger
;
3026 timer
->overflow
= overflow
;
3031 EXPORT_SYMBOL(ath_gen_timer_alloc
);
3033 void ath9k_hw_gen_timer_start(struct ath_hw
*ah
,
3034 struct ath_gen_timer
*timer
,
3038 struct ath_gen_timer_table
*timer_table
= &ah
->hw_gen_timers
;
3039 u32 tsf
, timer_next
;
3041 BUG_ON(!timer_period
);
3043 set_bit(timer
->index
, &timer_table
->timer_mask
.timer_bits
);
3045 tsf
= ath9k_hw_gettsf32(ah
);
3047 timer_next
= tsf
+ trig_timeout
;
3049 ath_dbg(ath9k_hw_common(ah
), BTCOEX
,
3050 "current tsf %x period %x timer_next %x\n",
3051 tsf
, timer_period
, timer_next
);
3054 * Program generic timer registers
3056 REG_WRITE(ah
, gen_tmr_configuration
[timer
->index
].next_addr
,
3058 REG_WRITE(ah
, gen_tmr_configuration
[timer
->index
].period_addr
,
3060 REG_SET_BIT(ah
, gen_tmr_configuration
[timer
->index
].mode_addr
,
3061 gen_tmr_configuration
[timer
->index
].mode_mask
);
3063 if (AR_SREV_9462(ah
) || AR_SREV_9565(ah
)) {
3065 * Starting from AR9462, each generic timer can select which tsf
3066 * to use. But we still follow the old rule, 0 - 7 use tsf and
3069 if ((timer
->index
< AR_GEN_TIMER_BANK_1_LEN
))
3070 REG_CLR_BIT(ah
, AR_MAC_PCU_GEN_TIMER_TSF_SEL
,
3071 (1 << timer
->index
));
3073 REG_SET_BIT(ah
, AR_MAC_PCU_GEN_TIMER_TSF_SEL
,
3074 (1 << timer
->index
));
3077 /* Enable both trigger and thresh interrupt masks */
3078 REG_SET_BIT(ah
, AR_IMR_S5
,
3079 (SM(AR_GENTMR_BIT(timer
->index
), AR_IMR_S5_GENTIMER_THRESH
) |
3080 SM(AR_GENTMR_BIT(timer
->index
), AR_IMR_S5_GENTIMER_TRIG
)));
3082 EXPORT_SYMBOL(ath9k_hw_gen_timer_start
);
3084 void ath9k_hw_gen_timer_stop(struct ath_hw
*ah
, struct ath_gen_timer
*timer
)
3086 struct ath_gen_timer_table
*timer_table
= &ah
->hw_gen_timers
;
3088 if ((timer
->index
< AR_FIRST_NDP_TIMER
) ||
3089 (timer
->index
>= ATH_MAX_GEN_TIMER
)) {
3093 /* Clear generic timer enable bits. */
3094 REG_CLR_BIT(ah
, gen_tmr_configuration
[timer
->index
].mode_addr
,
3095 gen_tmr_configuration
[timer
->index
].mode_mask
);
3097 if (AR_SREV_9462(ah
) || AR_SREV_9565(ah
)) {
3099 * Need to switch back to TSF if it was using TSF2.
3101 if ((timer
->index
>= AR_GEN_TIMER_BANK_1_LEN
)) {
3102 REG_CLR_BIT(ah
, AR_MAC_PCU_GEN_TIMER_TSF_SEL
,
3103 (1 << timer
->index
));
3107 /* Disable both trigger and thresh interrupt masks */
3108 REG_CLR_BIT(ah
, AR_IMR_S5
,
3109 (SM(AR_GENTMR_BIT(timer
->index
), AR_IMR_S5_GENTIMER_THRESH
) |
3110 SM(AR_GENTMR_BIT(timer
->index
), AR_IMR_S5_GENTIMER_TRIG
)));
3112 clear_bit(timer
->index
, &timer_table
->timer_mask
.timer_bits
);
3114 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop
);
3116 void ath_gen_timer_free(struct ath_hw
*ah
, struct ath_gen_timer
*timer
)
3118 struct ath_gen_timer_table
*timer_table
= &ah
->hw_gen_timers
;
3120 /* free the hardware generic timer slot */
3121 timer_table
->timers
[timer
->index
] = NULL
;
3124 EXPORT_SYMBOL(ath_gen_timer_free
);
3127 * Generic Timer Interrupts handling
3129 void ath_gen_timer_isr(struct ath_hw
*ah
)
3131 struct ath_gen_timer_table
*timer_table
= &ah
->hw_gen_timers
;
3132 struct ath_gen_timer
*timer
;
3133 struct ath_common
*common
= ath9k_hw_common(ah
);
3134 u32 trigger_mask
, thresh_mask
, index
;
3136 /* get hardware generic timer interrupt status */
3137 trigger_mask
= ah
->intr_gen_timer_trigger
;
3138 thresh_mask
= ah
->intr_gen_timer_thresh
;
3139 trigger_mask
&= timer_table
->timer_mask
.val
;
3140 thresh_mask
&= timer_table
->timer_mask
.val
;
3142 trigger_mask
&= ~thresh_mask
;
3144 while (thresh_mask
) {
3145 index
= rightmost_index(timer_table
, &thresh_mask
);
3146 timer
= timer_table
->timers
[index
];
3148 ath_dbg(common
, BTCOEX
, "TSF overflow for Gen timer %d\n",
3150 timer
->overflow(timer
->arg
);
3153 while (trigger_mask
) {
3154 index
= rightmost_index(timer_table
, &trigger_mask
);
3155 timer
= timer_table
->timers
[index
];
3157 ath_dbg(common
, BTCOEX
,
3158 "Gen timer[%d] trigger\n", index
);
3159 timer
->trigger(timer
->arg
);
3162 EXPORT_SYMBOL(ath_gen_timer_isr
);
3171 } ath_mac_bb_names
[] = {
3172 /* Devices with external radios */
3173 { AR_SREV_VERSION_5416_PCI
, "5416" },
3174 { AR_SREV_VERSION_5416_PCIE
, "5418" },
3175 { AR_SREV_VERSION_9100
, "9100" },
3176 { AR_SREV_VERSION_9160
, "9160" },
3177 /* Single-chip solutions */
3178 { AR_SREV_VERSION_9280
, "9280" },
3179 { AR_SREV_VERSION_9285
, "9285" },
3180 { AR_SREV_VERSION_9287
, "9287" },
3181 { AR_SREV_VERSION_9271
, "9271" },
3182 { AR_SREV_VERSION_9300
, "9300" },
3183 { AR_SREV_VERSION_9330
, "9330" },
3184 { AR_SREV_VERSION_9340
, "9340" },
3185 { AR_SREV_VERSION_9485
, "9485" },
3186 { AR_SREV_VERSION_9462
, "9462" },
3187 { AR_SREV_VERSION_9550
, "9550" },
3188 { AR_SREV_VERSION_9565
, "9565" },
3191 /* For devices with external radios */
3195 } ath_rf_names
[] = {
3197 { AR_RAD5133_SREV_MAJOR
, "5133" },
3198 { AR_RAD5122_SREV_MAJOR
, "5122" },
3199 { AR_RAD2133_SREV_MAJOR
, "2133" },
3200 { AR_RAD2122_SREV_MAJOR
, "2122" }
3204 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3206 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version
)
3210 for (i
=0; i
<ARRAY_SIZE(ath_mac_bb_names
); i
++) {
3211 if (ath_mac_bb_names
[i
].version
== mac_bb_version
) {
3212 return ath_mac_bb_names
[i
].name
;
3220 * Return the RF name. "????" is returned if the RF is unknown.
3221 * Used for devices with external radios.
3223 static const char *ath9k_hw_rf_name(u16 rf_version
)
3227 for (i
=0; i
<ARRAY_SIZE(ath_rf_names
); i
++) {
3228 if (ath_rf_names
[i
].version
== rf_version
) {
3229 return ath_rf_names
[i
].name
;
3236 void ath9k_hw_name(struct ath_hw
*ah
, char *hw_name
, size_t len
)
3240 /* chipsets >= AR9280 are single-chip */
3241 if (AR_SREV_9280_20_OR_LATER(ah
)) {
3242 used
= scnprintf(hw_name
, len
,
3243 "Atheros AR%s Rev:%x",
3244 ath9k_hw_mac_bb_name(ah
->hw_version
.macVersion
),
3245 ah
->hw_version
.macRev
);
3248 used
= scnprintf(hw_name
, len
,
3249 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3250 ath9k_hw_mac_bb_name(ah
->hw_version
.macVersion
),
3251 ah
->hw_version
.macRev
,
3252 ath9k_hw_rf_name((ah
->hw_version
.analog5GhzRev
3253 & AR_RADIO_SREV_MAJOR
)),
3254 ah
->hw_version
.phyRev
);
3257 hw_name
[used
] = '\0';
3259 EXPORT_SYMBOL(ath9k_hw_name
);