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ath9k_hw: Fill rx_enable() for the AR9003 hardware family
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / hw.c
1 /*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/io.h>
18 #include <asm/unaligned.h>
19
20 #include "hw.h"
21 #include "hw-ops.h"
22 #include "rc.h"
23 #include "initvals.h"
24
25 #define ATH9K_CLOCK_RATE_CCK 22
26 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
27 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
28
29 static void ar9002_hw_attach_ops(struct ath_hw *ah);
30 static void ar9003_hw_attach_ops(struct ath_hw *ah);
31
32 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
33
34 MODULE_AUTHOR("Atheros Communications");
35 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
36 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
37 MODULE_LICENSE("Dual BSD/GPL");
38
39 static int __init ath9k_init(void)
40 {
41 return 0;
42 }
43 module_init(ath9k_init);
44
45 static void __exit ath9k_exit(void)
46 {
47 return;
48 }
49 module_exit(ath9k_exit);
50
51 /* Private hardware callbacks */
52
53 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
54 {
55 ath9k_hw_private_ops(ah)->init_cal_settings(ah);
56 }
57
58 static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
59 {
60 ath9k_hw_private_ops(ah)->init_mode_regs(ah);
61 }
62
63 static bool ath9k_hw_macversion_supported(struct ath_hw *ah)
64 {
65 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
66
67 return priv_ops->macversion_supported(ah->hw_version.macVersion);
68 }
69
70 static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
71 struct ath9k_channel *chan)
72 {
73 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
74 }
75
76 /********************/
77 /* Helper Functions */
78 /********************/
79
80 static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
81 {
82 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
83
84 if (!ah->curchan) /* should really check for CCK instead */
85 return usecs *ATH9K_CLOCK_RATE_CCK;
86 if (conf->channel->band == IEEE80211_BAND_2GHZ)
87 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
88 return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
89 }
90
91 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
92 {
93 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
94
95 if (conf_is_ht40(conf))
96 return ath9k_hw_mac_clks(ah, usecs) * 2;
97 else
98 return ath9k_hw_mac_clks(ah, usecs);
99 }
100
101 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
102 {
103 int i;
104
105 BUG_ON(timeout < AH_TIME_QUANTUM);
106
107 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
108 if ((REG_READ(ah, reg) & mask) == val)
109 return true;
110
111 udelay(AH_TIME_QUANTUM);
112 }
113
114 ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
115 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
116 timeout, reg, REG_READ(ah, reg), mask, val);
117
118 return false;
119 }
120 EXPORT_SYMBOL(ath9k_hw_wait);
121
122 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
123 {
124 u32 retval;
125 int i;
126
127 for (i = 0, retval = 0; i < n; i++) {
128 retval = (retval << 1) | (val & 1);
129 val >>= 1;
130 }
131 return retval;
132 }
133
134 bool ath9k_get_channel_edges(struct ath_hw *ah,
135 u16 flags, u16 *low,
136 u16 *high)
137 {
138 struct ath9k_hw_capabilities *pCap = &ah->caps;
139
140 if (flags & CHANNEL_5GHZ) {
141 *low = pCap->low_5ghz_chan;
142 *high = pCap->high_5ghz_chan;
143 return true;
144 }
145 if ((flags & CHANNEL_2GHZ)) {
146 *low = pCap->low_2ghz_chan;
147 *high = pCap->high_2ghz_chan;
148 return true;
149 }
150 return false;
151 }
152
153 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
154 u8 phy, int kbps,
155 u32 frameLen, u16 rateix,
156 bool shortPreamble)
157 {
158 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
159
160 if (kbps == 0)
161 return 0;
162
163 switch (phy) {
164 case WLAN_RC_PHY_CCK:
165 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
166 if (shortPreamble)
167 phyTime >>= 1;
168 numBits = frameLen << 3;
169 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
170 break;
171 case WLAN_RC_PHY_OFDM:
172 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
173 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
174 numBits = OFDM_PLCP_BITS + (frameLen << 3);
175 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
176 txTime = OFDM_SIFS_TIME_QUARTER
177 + OFDM_PREAMBLE_TIME_QUARTER
178 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
179 } else if (ah->curchan &&
180 IS_CHAN_HALF_RATE(ah->curchan)) {
181 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
182 numBits = OFDM_PLCP_BITS + (frameLen << 3);
183 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
184 txTime = OFDM_SIFS_TIME_HALF +
185 OFDM_PREAMBLE_TIME_HALF
186 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
187 } else {
188 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
189 numBits = OFDM_PLCP_BITS + (frameLen << 3);
190 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
191 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
192 + (numSymbols * OFDM_SYMBOL_TIME);
193 }
194 break;
195 default:
196 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
197 "Unknown phy %u (rate ix %u)\n", phy, rateix);
198 txTime = 0;
199 break;
200 }
201
202 return txTime;
203 }
204 EXPORT_SYMBOL(ath9k_hw_computetxtime);
205
206 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
207 struct ath9k_channel *chan,
208 struct chan_centers *centers)
209 {
210 int8_t extoff;
211
212 if (!IS_CHAN_HT40(chan)) {
213 centers->ctl_center = centers->ext_center =
214 centers->synth_center = chan->channel;
215 return;
216 }
217
218 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
219 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
220 centers->synth_center =
221 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
222 extoff = 1;
223 } else {
224 centers->synth_center =
225 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
226 extoff = -1;
227 }
228
229 centers->ctl_center =
230 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
231 /* 25 MHz spacing is supported by hw but not on upper layers */
232 centers->ext_center =
233 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
234 }
235
236 /******************/
237 /* Chip Revisions */
238 /******************/
239
240 static void ath9k_hw_read_revisions(struct ath_hw *ah)
241 {
242 u32 val;
243
244 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
245
246 if (val == 0xFF) {
247 val = REG_READ(ah, AR_SREV);
248 ah->hw_version.macVersion =
249 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
250 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
251 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
252 } else {
253 if (!AR_SREV_9100(ah))
254 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
255
256 ah->hw_version.macRev = val & AR_SREV_REVISION;
257
258 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
259 ah->is_pciexpress = true;
260 }
261 }
262
263 static int ath9k_hw_get_radiorev(struct ath_hw *ah)
264 {
265 u32 val;
266 int i;
267
268 REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
269
270 for (i = 0; i < 8; i++)
271 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
272 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
273 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
274
275 return ath9k_hw_reverse_bits(val, 8);
276 }
277
278 /************************************/
279 /* HW Attach, Detach, Init Routines */
280 /************************************/
281
282 static void ath9k_hw_disablepcie(struct ath_hw *ah)
283 {
284 if (AR_SREV_9100(ah))
285 return;
286
287 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
288 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
289 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
290 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
291 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
292 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
293 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
294 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
295 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
296
297 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
298 }
299
300 static bool ath9k_hw_chip_test(struct ath_hw *ah)
301 {
302 struct ath_common *common = ath9k_hw_common(ah);
303 u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
304 u32 regHold[2];
305 u32 patternData[4] = { 0x55555555,
306 0xaaaaaaaa,
307 0x66666666,
308 0x99999999 };
309 int i, j;
310
311 for (i = 0; i < 2; i++) {
312 u32 addr = regAddr[i];
313 u32 wrData, rdData;
314
315 regHold[i] = REG_READ(ah, addr);
316 for (j = 0; j < 0x100; j++) {
317 wrData = (j << 16) | j;
318 REG_WRITE(ah, addr, wrData);
319 rdData = REG_READ(ah, addr);
320 if (rdData != wrData) {
321 ath_print(common, ATH_DBG_FATAL,
322 "address test failed "
323 "addr: 0x%08x - wr:0x%08x != "
324 "rd:0x%08x\n",
325 addr, wrData, rdData);
326 return false;
327 }
328 }
329 for (j = 0; j < 4; j++) {
330 wrData = patternData[j];
331 REG_WRITE(ah, addr, wrData);
332 rdData = REG_READ(ah, addr);
333 if (wrData != rdData) {
334 ath_print(common, ATH_DBG_FATAL,
335 "address test failed "
336 "addr: 0x%08x - wr:0x%08x != "
337 "rd:0x%08x\n",
338 addr, wrData, rdData);
339 return false;
340 }
341 }
342 REG_WRITE(ah, regAddr[i], regHold[i]);
343 }
344 udelay(100);
345
346 return true;
347 }
348
349 static void ath9k_hw_init_config(struct ath_hw *ah)
350 {
351 int i;
352
353 ah->config.dma_beacon_response_time = 2;
354 ah->config.sw_beacon_response_time = 10;
355 ah->config.additional_swba_backoff = 0;
356 ah->config.ack_6mb = 0x0;
357 ah->config.cwm_ignore_extcca = 0;
358 ah->config.pcie_powersave_enable = 0;
359 ah->config.pcie_clock_req = 0;
360 ah->config.pcie_waen = 0;
361 ah->config.analog_shiftreg = 1;
362 ah->config.ofdm_trig_low = 200;
363 ah->config.ofdm_trig_high = 500;
364 ah->config.cck_trig_high = 200;
365 ah->config.cck_trig_low = 100;
366
367 /*
368 * For now ANI is disabled for AR9003, it is still
369 * being tested.
370 */
371 if (!AR_SREV_9300_20_OR_LATER(ah))
372 ah->config.enable_ani = 1;
373
374 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
375 ah->config.spurchans[i][0] = AR_NO_SPUR;
376 ah->config.spurchans[i][1] = AR_NO_SPUR;
377 }
378
379 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
380 ah->config.ht_enable = 1;
381 else
382 ah->config.ht_enable = 0;
383
384 ah->config.rx_intr_mitigation = true;
385
386 /*
387 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
388 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
389 * This means we use it for all AR5416 devices, and the few
390 * minor PCI AR9280 devices out there.
391 *
392 * Serialization is required because these devices do not handle
393 * well the case of two concurrent reads/writes due to the latency
394 * involved. During one read/write another read/write can be issued
395 * on another CPU while the previous read/write may still be working
396 * on our hardware, if we hit this case the hardware poops in a loop.
397 * We prevent this by serializing reads and writes.
398 *
399 * This issue is not present on PCI-Express devices or pre-AR5416
400 * devices (legacy, 802.11abg).
401 */
402 if (num_possible_cpus() > 1)
403 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
404 }
405
406 static void ath9k_hw_init_defaults(struct ath_hw *ah)
407 {
408 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
409
410 regulatory->country_code = CTRY_DEFAULT;
411 regulatory->power_limit = MAX_RATE_POWER;
412 regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
413
414 ah->hw_version.magic = AR5416_MAGIC;
415 ah->hw_version.subvendorid = 0;
416
417 ah->ah_flags = 0;
418 if (!AR_SREV_9100(ah))
419 ah->ah_flags = AH_USE_EEPROM;
420
421 ah->atim_window = 0;
422 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
423 ah->beacon_interval = 100;
424 ah->enable_32kHz_clock = DONT_USE_32KHZ;
425 ah->slottime = (u32) -1;
426 ah->globaltxtimeout = (u32) -1;
427 ah->power_mode = ATH9K_PM_UNDEFINED;
428 }
429
430 static int ath9k_hw_rf_claim(struct ath_hw *ah)
431 {
432 u32 val;
433
434 REG_WRITE(ah, AR_PHY(0), 0x00000007);
435
436 val = ath9k_hw_get_radiorev(ah);
437 switch (val & AR_RADIO_SREV_MAJOR) {
438 case 0:
439 val = AR_RAD5133_SREV_MAJOR;
440 break;
441 case AR_RAD5133_SREV_MAJOR:
442 case AR_RAD5122_SREV_MAJOR:
443 case AR_RAD2133_SREV_MAJOR:
444 case AR_RAD2122_SREV_MAJOR:
445 break;
446 default:
447 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
448 "Radio Chip Rev 0x%02X not supported\n",
449 val & AR_RADIO_SREV_MAJOR);
450 return -EOPNOTSUPP;
451 }
452
453 ah->hw_version.analog5GhzRev = val;
454
455 return 0;
456 }
457
458 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
459 {
460 struct ath_common *common = ath9k_hw_common(ah);
461 u32 sum;
462 int i;
463 u16 eeval;
464
465 sum = 0;
466 for (i = 0; i < 3; i++) {
467 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
468 sum += eeval;
469 common->macaddr[2 * i] = eeval >> 8;
470 common->macaddr[2 * i + 1] = eeval & 0xff;
471 }
472 if (sum == 0 || sum == 0xffff * 3)
473 return -EADDRNOTAVAIL;
474
475 return 0;
476 }
477
478 static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
479 {
480 u32 rxgain_type;
481
482 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
483 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
484
485 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
486 INIT_INI_ARRAY(&ah->iniModesRxGain,
487 ar9280Modes_backoff_13db_rxgain_9280_2,
488 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
489 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
490 INIT_INI_ARRAY(&ah->iniModesRxGain,
491 ar9280Modes_backoff_23db_rxgain_9280_2,
492 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
493 else
494 INIT_INI_ARRAY(&ah->iniModesRxGain,
495 ar9280Modes_original_rxgain_9280_2,
496 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
497 } else {
498 INIT_INI_ARRAY(&ah->iniModesRxGain,
499 ar9280Modes_original_rxgain_9280_2,
500 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
501 }
502 }
503
504 static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
505 {
506 u32 txgain_type;
507
508 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
509 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
510
511 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
512 INIT_INI_ARRAY(&ah->iniModesTxGain,
513 ar9280Modes_high_power_tx_gain_9280_2,
514 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
515 else
516 INIT_INI_ARRAY(&ah->iniModesTxGain,
517 ar9280Modes_original_tx_gain_9280_2,
518 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
519 } else {
520 INIT_INI_ARRAY(&ah->iniModesTxGain,
521 ar9280Modes_original_tx_gain_9280_2,
522 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
523 }
524 }
525
526 static int ath9k_hw_post_init(struct ath_hw *ah)
527 {
528 int ecode;
529
530 if (!AR_SREV_9271(ah)) {
531 if (!ath9k_hw_chip_test(ah))
532 return -ENODEV;
533 }
534
535 ecode = ath9k_hw_rf_claim(ah);
536 if (ecode != 0)
537 return ecode;
538
539 ecode = ath9k_hw_eeprom_init(ah);
540 if (ecode != 0)
541 return ecode;
542
543 ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
544 "Eeprom VER: %d, REV: %d\n",
545 ah->eep_ops->get_eeprom_ver(ah),
546 ah->eep_ops->get_eeprom_rev(ah));
547
548 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
549 if (ecode) {
550 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
551 "Failed allocating banks for "
552 "external radio\n");
553 return ecode;
554 }
555
556 if (!AR_SREV_9100(ah)) {
557 ath9k_hw_ani_setup(ah);
558 ath9k_hw_ani_init(ah);
559 }
560
561 return 0;
562 }
563
564 static bool ar9002_hw_macversion_supported(u32 macversion)
565 {
566 switch (macversion) {
567 case AR_SREV_VERSION_5416_PCI:
568 case AR_SREV_VERSION_5416_PCIE:
569 case AR_SREV_VERSION_9160:
570 case AR_SREV_VERSION_9100:
571 case AR_SREV_VERSION_9280:
572 case AR_SREV_VERSION_9285:
573 case AR_SREV_VERSION_9287:
574 case AR_SREV_VERSION_9271:
575 return true;
576 default:
577 break;
578 }
579 return false;
580 }
581
582 static bool ar9003_hw_macversion_supported(u32 macversion)
583 {
584 switch (macversion) {
585 case AR_SREV_VERSION_9300:
586 return true;
587 default:
588 break;
589 }
590 return false;
591 }
592
593 static void ar9002_hw_init_cal_settings(struct ath_hw *ah)
594 {
595 if (AR_SREV_9160_10_OR_LATER(ah)) {
596 if (AR_SREV_9280_10_OR_LATER(ah)) {
597 ah->iq_caldata.calData = &iq_cal_single_sample;
598 ah->adcgain_caldata.calData =
599 &adc_gain_cal_single_sample;
600 ah->adcdc_caldata.calData =
601 &adc_dc_cal_single_sample;
602 ah->adcdc_calinitdata.calData =
603 &adc_init_dc_cal;
604 } else {
605 ah->iq_caldata.calData = &iq_cal_multi_sample;
606 ah->adcgain_caldata.calData =
607 &adc_gain_cal_multi_sample;
608 ah->adcdc_caldata.calData =
609 &adc_dc_cal_multi_sample;
610 ah->adcdc_calinitdata.calData =
611 &adc_init_dc_cal;
612 }
613 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
614 }
615 }
616
617 static void ar9002_hw_init_mode_regs(struct ath_hw *ah)
618 {
619 if (AR_SREV_9271(ah)) {
620 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271,
621 ARRAY_SIZE(ar9271Modes_9271), 6);
622 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271,
623 ARRAY_SIZE(ar9271Common_9271), 2);
624 INIT_INI_ARRAY(&ah->iniCommon_normal_cck_fir_coeff_9271,
625 ar9271Common_normal_cck_fir_coeff_9271,
626 ARRAY_SIZE(ar9271Common_normal_cck_fir_coeff_9271), 2);
627 INIT_INI_ARRAY(&ah->iniCommon_japan_2484_cck_fir_coeff_9271,
628 ar9271Common_japan_2484_cck_fir_coeff_9271,
629 ARRAY_SIZE(ar9271Common_japan_2484_cck_fir_coeff_9271), 2);
630 INIT_INI_ARRAY(&ah->iniModes_9271_1_0_only,
631 ar9271Modes_9271_1_0_only,
632 ARRAY_SIZE(ar9271Modes_9271_1_0_only), 6);
633 INIT_INI_ARRAY(&ah->iniModes_9271_ANI_reg, ar9271Modes_9271_ANI_reg,
634 ARRAY_SIZE(ar9271Modes_9271_ANI_reg), 6);
635 INIT_INI_ARRAY(&ah->iniModes_high_power_tx_gain_9271,
636 ar9271Modes_high_power_tx_gain_9271,
637 ARRAY_SIZE(ar9271Modes_high_power_tx_gain_9271), 6);
638 INIT_INI_ARRAY(&ah->iniModes_normal_power_tx_gain_9271,
639 ar9271Modes_normal_power_tx_gain_9271,
640 ARRAY_SIZE(ar9271Modes_normal_power_tx_gain_9271), 6);
641 return;
642 }
643
644 if (AR_SREV_9287_11_OR_LATER(ah)) {
645 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
646 ARRAY_SIZE(ar9287Modes_9287_1_1), 6);
647 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
648 ARRAY_SIZE(ar9287Common_9287_1_1), 2);
649 if (ah->config.pcie_clock_req)
650 INIT_INI_ARRAY(&ah->iniPcieSerdes,
651 ar9287PciePhy_clkreq_off_L1_9287_1_1,
652 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2);
653 else
654 INIT_INI_ARRAY(&ah->iniPcieSerdes,
655 ar9287PciePhy_clkreq_always_on_L1_9287_1_1,
656 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1),
657 2);
658 } else if (AR_SREV_9287_10_OR_LATER(ah)) {
659 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0,
660 ARRAY_SIZE(ar9287Modes_9287_1_0), 6);
661 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0,
662 ARRAY_SIZE(ar9287Common_9287_1_0), 2);
663
664 if (ah->config.pcie_clock_req)
665 INIT_INI_ARRAY(&ah->iniPcieSerdes,
666 ar9287PciePhy_clkreq_off_L1_9287_1_0,
667 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2);
668 else
669 INIT_INI_ARRAY(&ah->iniPcieSerdes,
670 ar9287PciePhy_clkreq_always_on_L1_9287_1_0,
671 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0),
672 2);
673 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
674
675
676 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
677 ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
678 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
679 ARRAY_SIZE(ar9285Common_9285_1_2), 2);
680
681 if (ah->config.pcie_clock_req) {
682 INIT_INI_ARRAY(&ah->iniPcieSerdes,
683 ar9285PciePhy_clkreq_off_L1_9285_1_2,
684 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
685 } else {
686 INIT_INI_ARRAY(&ah->iniPcieSerdes,
687 ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
688 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
689 2);
690 }
691 } else if (AR_SREV_9285_10_OR_LATER(ah)) {
692 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
693 ARRAY_SIZE(ar9285Modes_9285), 6);
694 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
695 ARRAY_SIZE(ar9285Common_9285), 2);
696
697 if (ah->config.pcie_clock_req) {
698 INIT_INI_ARRAY(&ah->iniPcieSerdes,
699 ar9285PciePhy_clkreq_off_L1_9285,
700 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
701 } else {
702 INIT_INI_ARRAY(&ah->iniPcieSerdes,
703 ar9285PciePhy_clkreq_always_on_L1_9285,
704 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
705 }
706 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
707 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
708 ARRAY_SIZE(ar9280Modes_9280_2), 6);
709 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
710 ARRAY_SIZE(ar9280Common_9280_2), 2);
711
712 if (ah->config.pcie_clock_req) {
713 INIT_INI_ARRAY(&ah->iniPcieSerdes,
714 ar9280PciePhy_clkreq_off_L1_9280,
715 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
716 } else {
717 INIT_INI_ARRAY(&ah->iniPcieSerdes,
718 ar9280PciePhy_clkreq_always_on_L1_9280,
719 ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
720 }
721 INIT_INI_ARRAY(&ah->iniModesAdditional,
722 ar9280Modes_fast_clock_9280_2,
723 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
724 } else if (AR_SREV_9280_10_OR_LATER(ah)) {
725 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
726 ARRAY_SIZE(ar9280Modes_9280), 6);
727 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
728 ARRAY_SIZE(ar9280Common_9280), 2);
729 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
730 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
731 ARRAY_SIZE(ar5416Modes_9160), 6);
732 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
733 ARRAY_SIZE(ar5416Common_9160), 2);
734 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
735 ARRAY_SIZE(ar5416Bank0_9160), 2);
736 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
737 ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
738 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
739 ARRAY_SIZE(ar5416Bank1_9160), 2);
740 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
741 ARRAY_SIZE(ar5416Bank2_9160), 2);
742 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
743 ARRAY_SIZE(ar5416Bank3_9160), 3);
744 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
745 ARRAY_SIZE(ar5416Bank6_9160), 3);
746 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
747 ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
748 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
749 ARRAY_SIZE(ar5416Bank7_9160), 2);
750 if (AR_SREV_9160_11(ah)) {
751 INIT_INI_ARRAY(&ah->iniAddac,
752 ar5416Addac_91601_1,
753 ARRAY_SIZE(ar5416Addac_91601_1), 2);
754 } else {
755 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
756 ARRAY_SIZE(ar5416Addac_9160), 2);
757 }
758 } else if (AR_SREV_9100_OR_LATER(ah)) {
759 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
760 ARRAY_SIZE(ar5416Modes_9100), 6);
761 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
762 ARRAY_SIZE(ar5416Common_9100), 2);
763 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
764 ARRAY_SIZE(ar5416Bank0_9100), 2);
765 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
766 ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
767 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
768 ARRAY_SIZE(ar5416Bank1_9100), 2);
769 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
770 ARRAY_SIZE(ar5416Bank2_9100), 2);
771 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
772 ARRAY_SIZE(ar5416Bank3_9100), 3);
773 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
774 ARRAY_SIZE(ar5416Bank6_9100), 3);
775 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
776 ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
777 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
778 ARRAY_SIZE(ar5416Bank7_9100), 2);
779 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
780 ARRAY_SIZE(ar5416Addac_9100), 2);
781 } else {
782 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
783 ARRAY_SIZE(ar5416Modes), 6);
784 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
785 ARRAY_SIZE(ar5416Common), 2);
786 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
787 ARRAY_SIZE(ar5416Bank0), 2);
788 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
789 ARRAY_SIZE(ar5416BB_RfGain), 3);
790 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
791 ARRAY_SIZE(ar5416Bank1), 2);
792 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
793 ARRAY_SIZE(ar5416Bank2), 2);
794 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
795 ARRAY_SIZE(ar5416Bank3), 3);
796 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
797 ARRAY_SIZE(ar5416Bank6), 3);
798 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
799 ARRAY_SIZE(ar5416Bank6TPC), 3);
800 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
801 ARRAY_SIZE(ar5416Bank7), 2);
802 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
803 ARRAY_SIZE(ar5416Addac), 2);
804 }
805 }
806
807 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
808 {
809 if (AR_SREV_9287_11_OR_LATER(ah))
810 INIT_INI_ARRAY(&ah->iniModesRxGain,
811 ar9287Modes_rx_gain_9287_1_1,
812 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
813 else if (AR_SREV_9287_10(ah))
814 INIT_INI_ARRAY(&ah->iniModesRxGain,
815 ar9287Modes_rx_gain_9287_1_0,
816 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6);
817 else if (AR_SREV_9280_20(ah))
818 ath9k_hw_init_rxgain_ini(ah);
819
820 if (AR_SREV_9287_11_OR_LATER(ah)) {
821 INIT_INI_ARRAY(&ah->iniModesTxGain,
822 ar9287Modes_tx_gain_9287_1_1,
823 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
824 } else if (AR_SREV_9287_10(ah)) {
825 INIT_INI_ARRAY(&ah->iniModesTxGain,
826 ar9287Modes_tx_gain_9287_1_0,
827 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6);
828 } else if (AR_SREV_9280_20(ah)) {
829 ath9k_hw_init_txgain_ini(ah);
830 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
831 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
832
833 /* txgain table */
834 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
835 if (AR_SREV_9285E_20(ah)) {
836 INIT_INI_ARRAY(&ah->iniModesTxGain,
837 ar9285Modes_XE2_0_high_power,
838 ARRAY_SIZE(
839 ar9285Modes_XE2_0_high_power), 6);
840 } else {
841 INIT_INI_ARRAY(&ah->iniModesTxGain,
842 ar9285Modes_high_power_tx_gain_9285_1_2,
843 ARRAY_SIZE(
844 ar9285Modes_high_power_tx_gain_9285_1_2), 6);
845 }
846 } else {
847 if (AR_SREV_9285E_20(ah)) {
848 INIT_INI_ARRAY(&ah->iniModesTxGain,
849 ar9285Modes_XE2_0_normal_power,
850 ARRAY_SIZE(
851 ar9285Modes_XE2_0_normal_power), 6);
852 } else {
853 INIT_INI_ARRAY(&ah->iniModesTxGain,
854 ar9285Modes_original_tx_gain_9285_1_2,
855 ARRAY_SIZE(
856 ar9285Modes_original_tx_gain_9285_1_2), 6);
857 }
858 }
859 }
860 }
861
862 static void ath9k_hw_init_eeprom_fix(struct ath_hw *ah)
863 {
864 struct base_eep_header *pBase = &(ah->eeprom.def.baseEepHeader);
865 struct ath_common *common = ath9k_hw_common(ah);
866
867 ah->need_an_top2_fixup = (ah->hw_version.devid == AR9280_DEVID_PCI) &&
868 (ah->eep_map != EEP_MAP_4KBITS) &&
869 ((pBase->version & 0xff) > 0x0a) &&
870 (pBase->pwdclkind == 0);
871
872 if (ah->need_an_top2_fixup)
873 ath_print(common, ATH_DBG_EEPROM,
874 "needs fixup for AR_AN_TOP2 register\n");
875 }
876
877 static void ath9k_hw_attach_ops(struct ath_hw *ah)
878 {
879 if (AR_SREV_9300_20_OR_LATER(ah))
880 ar9003_hw_attach_ops(ah);
881 else
882 ar9002_hw_attach_ops(ah);
883 }
884
885 /* Called for all hardware families */
886 static int __ath9k_hw_init(struct ath_hw *ah)
887 {
888 struct ath_common *common = ath9k_hw_common(ah);
889 int r = 0;
890
891 if (ah->hw_version.devid == AR5416_AR9100_DEVID)
892 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
893
894 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
895 ath_print(common, ATH_DBG_FATAL,
896 "Couldn't reset chip\n");
897 return -EIO;
898 }
899
900 ath9k_hw_init_defaults(ah);
901 ath9k_hw_init_config(ah);
902
903 ath9k_hw_attach_ops(ah);
904
905 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
906 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
907 return -EIO;
908 }
909
910 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
911 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
912 (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
913 ah->config.serialize_regmode =
914 SER_REG_MODE_ON;
915 } else {
916 ah->config.serialize_regmode =
917 SER_REG_MODE_OFF;
918 }
919 }
920
921 ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
922 ah->config.serialize_regmode);
923
924 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
925 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
926 else
927 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
928
929 if (!ath9k_hw_macversion_supported(ah)) {
930 ath_print(common, ATH_DBG_FATAL,
931 "Mac Chip Rev 0x%02x.%x is not supported by "
932 "this driver\n", ah->hw_version.macVersion,
933 ah->hw_version.macRev);
934 return -EOPNOTSUPP;
935 }
936
937 if (AR_SREV_9100(ah)) {
938 ah->iq_caldata.calData = &iq_cal_multi_sample;
939 ah->supp_cals = IQ_MISMATCH_CAL;
940 ah->is_pciexpress = false;
941 }
942
943 if (AR_SREV_9271(ah))
944 ah->is_pciexpress = false;
945
946 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
947 ath9k_hw_init_cal_settings(ah);
948
949 ah->ani_function = ATH9K_ANI_ALL;
950 if (AR_SREV_9280_10_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
951 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
952
953 ath9k_hw_init_mode_regs(ah);
954
955 if (ah->is_pciexpress)
956 ath9k_hw_configpcipowersave(ah, 0, 0);
957 else
958 ath9k_hw_disablepcie(ah);
959
960 /* Support for Japan ch.14 (2484) spread */
961 if (AR_SREV_9287_11_OR_LATER(ah)) {
962 INIT_INI_ARRAY(&ah->iniCckfirNormal,
963 ar9287Common_normal_cck_fir_coeff_92871_1,
964 ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_92871_1), 2);
965 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
966 ar9287Common_japan_2484_cck_fir_coeff_92871_1,
967 ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_92871_1), 2);
968 }
969
970 r = ath9k_hw_post_init(ah);
971 if (r)
972 return r;
973
974 ath9k_hw_init_mode_gain_regs(ah);
975 r = ath9k_hw_fill_cap_info(ah);
976 if (r)
977 return r;
978
979 ath9k_hw_init_eeprom_fix(ah);
980
981 r = ath9k_hw_init_macaddr(ah);
982 if (r) {
983 ath_print(common, ATH_DBG_FATAL,
984 "Failed to initialize MAC address\n");
985 return r;
986 }
987
988 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
989 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
990 else
991 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
992
993 ath9k_init_nfcal_hist_buffer(ah);
994
995 common->state = ATH_HW_INITIALIZED;
996
997 return 0;
998 }
999
1000 int ath9k_hw_init(struct ath_hw *ah)
1001 {
1002 int ret;
1003 struct ath_common *common = ath9k_hw_common(ah);
1004
1005 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
1006 switch (ah->hw_version.devid) {
1007 case AR5416_DEVID_PCI:
1008 case AR5416_DEVID_PCIE:
1009 case AR5416_AR9100_DEVID:
1010 case AR9160_DEVID_PCI:
1011 case AR9280_DEVID_PCI:
1012 case AR9280_DEVID_PCIE:
1013 case AR9285_DEVID_PCIE:
1014 case AR9287_DEVID_PCI:
1015 case AR9287_DEVID_PCIE:
1016 case AR2427_DEVID_PCIE:
1017 case AR9300_DEVID_PCIE:
1018 break;
1019 default:
1020 if (common->bus_ops->ath_bus_type == ATH_USB)
1021 break;
1022 ath_print(common, ATH_DBG_FATAL,
1023 "Hardware device ID 0x%04x not supported\n",
1024 ah->hw_version.devid);
1025 return -EOPNOTSUPP;
1026 }
1027
1028 ret = __ath9k_hw_init(ah);
1029 if (ret) {
1030 ath_print(common, ATH_DBG_FATAL,
1031 "Unable to initialize hardware; "
1032 "initialization status: %d\n", ret);
1033 return ret;
1034 }
1035
1036 return 0;
1037 }
1038 EXPORT_SYMBOL(ath9k_hw_init);
1039
1040 static void ath9k_hw_init_qos(struct ath_hw *ah)
1041 {
1042 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
1043 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
1044
1045 REG_WRITE(ah, AR_QOS_NO_ACK,
1046 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
1047 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
1048 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
1049
1050 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
1051 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
1052 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
1053 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
1054 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
1055 }
1056
1057 static void ath9k_hw_init_pll(struct ath_hw *ah,
1058 struct ath9k_channel *chan)
1059 {
1060 u32 pll = ath9k_hw_compute_pll_control(ah, chan);
1061
1062 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
1063
1064 /* Switch the core clock for ar9271 to 117Mhz */
1065 if (AR_SREV_9271(ah)) {
1066 udelay(500);
1067 REG_WRITE(ah, 0x50040, 0x304);
1068 }
1069
1070 udelay(RTC_PLL_SETTLE_DELAY);
1071
1072 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1073 }
1074
1075 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
1076 enum nl80211_iftype opmode)
1077 {
1078 u32 imr_reg = AR_IMR_TXERR |
1079 AR_IMR_TXURN |
1080 AR_IMR_RXERR |
1081 AR_IMR_RXORN |
1082 AR_IMR_BCNMISC;
1083
1084 if (ah->config.rx_intr_mitigation)
1085 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1086 else
1087 imr_reg |= AR_IMR_RXOK;
1088
1089 imr_reg |= AR_IMR_TXOK;
1090
1091 if (opmode == NL80211_IFTYPE_AP)
1092 imr_reg |= AR_IMR_MIB;
1093
1094 REG_WRITE(ah, AR_IMR, imr_reg);
1095 ah->imrs2_reg |= AR_IMR_S2_GTT;
1096 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
1097
1098 if (!AR_SREV_9100(ah)) {
1099 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1100 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1101 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1102 }
1103 }
1104
1105 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
1106 {
1107 u32 val = ath9k_hw_mac_to_clks(ah, us);
1108 val = min(val, (u32) 0xFFFF);
1109 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
1110 }
1111
1112 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1113 {
1114 u32 val = ath9k_hw_mac_to_clks(ah, us);
1115 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
1116 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
1117 }
1118
1119 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1120 {
1121 u32 val = ath9k_hw_mac_to_clks(ah, us);
1122 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
1123 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
1124 }
1125
1126 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1127 {
1128 if (tu > 0xFFFF) {
1129 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
1130 "bad global tx timeout %u\n", tu);
1131 ah->globaltxtimeout = (u32) -1;
1132 return false;
1133 } else {
1134 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1135 ah->globaltxtimeout = tu;
1136 return true;
1137 }
1138 }
1139
1140 void ath9k_hw_init_global_settings(struct ath_hw *ah)
1141 {
1142 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
1143 int acktimeout;
1144 int slottime;
1145 int sifstime;
1146
1147 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
1148 ah->misc_mode);
1149
1150 if (ah->misc_mode != 0)
1151 REG_WRITE(ah, AR_PCU_MISC,
1152 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
1153
1154 if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
1155 sifstime = 16;
1156 else
1157 sifstime = 10;
1158
1159 /* As defined by IEEE 802.11-2007 17.3.8.6 */
1160 slottime = ah->slottime + 3 * ah->coverage_class;
1161 acktimeout = slottime + sifstime;
1162
1163 /*
1164 * Workaround for early ACK timeouts, add an offset to match the
1165 * initval's 64us ack timeout value.
1166 * This was initially only meant to work around an issue with delayed
1167 * BA frames in some implementations, but it has been found to fix ACK
1168 * timeout issues in other cases as well.
1169 */
1170 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
1171 acktimeout += 64 - sifstime - ah->slottime;
1172
1173 ath9k_hw_setslottime(ah, slottime);
1174 ath9k_hw_set_ack_timeout(ah, acktimeout);
1175 ath9k_hw_set_cts_timeout(ah, acktimeout);
1176 if (ah->globaltxtimeout != (u32) -1)
1177 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1178 }
1179 EXPORT_SYMBOL(ath9k_hw_init_global_settings);
1180
1181 void ath9k_hw_deinit(struct ath_hw *ah)
1182 {
1183 struct ath_common *common = ath9k_hw_common(ah);
1184
1185 if (common->state < ATH_HW_INITIALIZED)
1186 goto free_hw;
1187
1188 if (!AR_SREV_9100(ah))
1189 ath9k_hw_ani_disable(ah);
1190
1191 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1192
1193 free_hw:
1194 ath9k_hw_rf_free_ext_banks(ah);
1195 }
1196 EXPORT_SYMBOL(ath9k_hw_deinit);
1197
1198 /*******/
1199 /* INI */
1200 /*******/
1201
1202 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
1203 {
1204 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1205
1206 if (IS_CHAN_B(chan))
1207 ctl |= CTL_11B;
1208 else if (IS_CHAN_G(chan))
1209 ctl |= CTL_11G;
1210 else
1211 ctl |= CTL_11A;
1212
1213 return ctl;
1214 }
1215
1216 /****************************************/
1217 /* Reset and Channel Switching Routines */
1218 /****************************************/
1219
1220 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1221 {
1222 u32 regval;
1223
1224 /*
1225 * set AHB_MODE not to do cacheline prefetches
1226 */
1227 regval = REG_READ(ah, AR_AHB_MODE);
1228 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1229
1230 /*
1231 * let mac dma reads be in 128 byte chunks
1232 */
1233 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1234 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1235
1236 /*
1237 * Restore TX Trigger Level to its pre-reset value.
1238 * The initial value depends on whether aggregation is enabled, and is
1239 * adjusted whenever underruns are detected.
1240 */
1241 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1242
1243 /*
1244 * let mac dma writes be in 128 byte chunks
1245 */
1246 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1247 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1248
1249 /*
1250 * Setup receive FIFO threshold to hold off TX activities
1251 */
1252 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1253
1254 /*
1255 * reduce the number of usable entries in PCU TXBUF to avoid
1256 * wrap around issues.
1257 */
1258 if (AR_SREV_9285(ah)) {
1259 /* For AR9285 the number of Fifos are reduced to half.
1260 * So set the usable tx buf size also to half to
1261 * avoid data/delimiter underruns
1262 */
1263 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1264 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1265 } else if (!AR_SREV_9271(ah)) {
1266 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1267 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1268 }
1269 }
1270
1271 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1272 {
1273 u32 val;
1274
1275 val = REG_READ(ah, AR_STA_ID1);
1276 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1277 switch (opmode) {
1278 case NL80211_IFTYPE_AP:
1279 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1280 | AR_STA_ID1_KSRCH_MODE);
1281 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1282 break;
1283 case NL80211_IFTYPE_ADHOC:
1284 case NL80211_IFTYPE_MESH_POINT:
1285 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1286 | AR_STA_ID1_KSRCH_MODE);
1287 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1288 break;
1289 case NL80211_IFTYPE_STATION:
1290 case NL80211_IFTYPE_MONITOR:
1291 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1292 break;
1293 }
1294 }
1295
1296 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1297 u32 *coef_mantissa, u32 *coef_exponent)
1298 {
1299 u32 coef_exp, coef_man;
1300
1301 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1302 if ((coef_scaled >> coef_exp) & 0x1)
1303 break;
1304
1305 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1306
1307 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1308
1309 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1310 *coef_exponent = coef_exp - 16;
1311 }
1312
1313 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1314 {
1315 u32 rst_flags;
1316 u32 tmpReg;
1317
1318 if (AR_SREV_9100(ah)) {
1319 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
1320 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
1321 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1322 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1323 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1324 }
1325
1326 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1327 AR_RTC_FORCE_WAKE_ON_INT);
1328
1329 if (AR_SREV_9100(ah)) {
1330 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1331 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1332 } else {
1333 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1334 if (tmpReg &
1335 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1336 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1337 u32 val;
1338 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1339
1340 val = AR_RC_HOSTIF;
1341 if (!AR_SREV_9300_20_OR_LATER(ah))
1342 val |= AR_RC_AHB;
1343 REG_WRITE(ah, AR_RC, val);
1344
1345 } else if (!AR_SREV_9300_20_OR_LATER(ah))
1346 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1347
1348 rst_flags = AR_RTC_RC_MAC_WARM;
1349 if (type == ATH9K_RESET_COLD)
1350 rst_flags |= AR_RTC_RC_MAC_COLD;
1351 }
1352
1353 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1354 udelay(50);
1355
1356 REG_WRITE(ah, AR_RTC_RC, 0);
1357 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1358 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1359 "RTC stuck in MAC reset\n");
1360 return false;
1361 }
1362
1363 if (!AR_SREV_9100(ah))
1364 REG_WRITE(ah, AR_RC, 0);
1365
1366 if (AR_SREV_9100(ah))
1367 udelay(50);
1368
1369 return true;
1370 }
1371
1372 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1373 {
1374 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1375 AR_RTC_FORCE_WAKE_ON_INT);
1376
1377 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1378 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1379
1380 REG_WRITE(ah, AR_RTC_RESET, 0);
1381 udelay(2);
1382
1383 if (!AR_SREV_9100(ah))
1384 REG_WRITE(ah, AR_RC, 0);
1385
1386 REG_WRITE(ah, AR_RTC_RESET, 1);
1387
1388 if (!ath9k_hw_wait(ah,
1389 AR_RTC_STATUS,
1390 AR_RTC_STATUS_M,
1391 AR_RTC_STATUS_ON,
1392 AH_WAIT_TIMEOUT)) {
1393 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1394 "RTC not waking up\n");
1395 return false;
1396 }
1397
1398 ath9k_hw_read_revisions(ah);
1399
1400 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1401 }
1402
1403 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1404 {
1405 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1406 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1407
1408 switch (type) {
1409 case ATH9K_RESET_POWER_ON:
1410 return ath9k_hw_set_reset_power_on(ah);
1411 case ATH9K_RESET_WARM:
1412 case ATH9K_RESET_COLD:
1413 return ath9k_hw_set_reset(ah, type);
1414 default:
1415 return false;
1416 }
1417 }
1418
1419 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1420 struct ath9k_channel *chan)
1421 {
1422 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
1423 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1424 return false;
1425 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1426 return false;
1427
1428 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1429 return false;
1430
1431 ah->chip_fullsleep = false;
1432 ath9k_hw_init_pll(ah, chan);
1433 ath9k_hw_set_rfmode(ah, chan);
1434
1435 return true;
1436 }
1437
1438 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1439 struct ath9k_channel *chan)
1440 {
1441 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1442 struct ath_common *common = ath9k_hw_common(ah);
1443 struct ieee80211_channel *channel = chan->chan;
1444 u32 qnum;
1445 int r;
1446
1447 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1448 if (ath9k_hw_numtxpending(ah, qnum)) {
1449 ath_print(common, ATH_DBG_QUEUE,
1450 "Transmit frames pending on "
1451 "queue %d\n", qnum);
1452 return false;
1453 }
1454 }
1455
1456 if (!ath9k_hw_rfbus_req(ah)) {
1457 ath_print(common, ATH_DBG_FATAL,
1458 "Could not kill baseband RX\n");
1459 return false;
1460 }
1461
1462 ath9k_hw_set_channel_regs(ah, chan);
1463
1464 r = ath9k_hw_rf_set_freq(ah, chan);
1465 if (r) {
1466 ath_print(common, ATH_DBG_FATAL,
1467 "Failed to set channel\n");
1468 return false;
1469 }
1470
1471 ah->eep_ops->set_txpower(ah, chan,
1472 ath9k_regd_get_ctl(regulatory, chan),
1473 channel->max_antenna_gain * 2,
1474 channel->max_power * 2,
1475 min((u32) MAX_RATE_POWER,
1476 (u32) regulatory->power_limit));
1477
1478 ath9k_hw_rfbus_done(ah);
1479
1480 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1481 ath9k_hw_set_delta_slope(ah, chan);
1482
1483 ath9k_hw_spur_mitigate_freq(ah, chan);
1484
1485 if (!chan->oneTimeCalsDone)
1486 chan->oneTimeCalsDone = true;
1487
1488 return true;
1489 }
1490
1491 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1492 bool bChannelChange)
1493 {
1494 struct ath_common *common = ath9k_hw_common(ah);
1495 u32 saveLedState;
1496 struct ath9k_channel *curchan = ah->curchan;
1497 u32 saveDefAntenna;
1498 u32 macStaId1;
1499 u64 tsf = 0;
1500 int i, r;
1501
1502 ah->txchainmask = common->tx_chainmask;
1503 ah->rxchainmask = common->rx_chainmask;
1504
1505 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1506 return -EIO;
1507
1508 if (curchan && !ah->chip_fullsleep)
1509 ath9k_hw_getnf(ah, curchan);
1510
1511 if (bChannelChange &&
1512 (ah->chip_fullsleep != true) &&
1513 (ah->curchan != NULL) &&
1514 (chan->channel != ah->curchan->channel) &&
1515 ((chan->channelFlags & CHANNEL_ALL) ==
1516 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
1517 !(AR_SREV_9280(ah) || IS_CHAN_A_5MHZ_SPACED(chan) ||
1518 IS_CHAN_A_5MHZ_SPACED(ah->curchan))) {
1519
1520 if (ath9k_hw_channel_change(ah, chan)) {
1521 ath9k_hw_loadnf(ah, ah->curchan);
1522 ath9k_hw_start_nfcal(ah);
1523 return 0;
1524 }
1525 }
1526
1527 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1528 if (saveDefAntenna == 0)
1529 saveDefAntenna = 1;
1530
1531 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1532
1533 /* For chips on which RTC reset is done, save TSF before it gets cleared */
1534 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1535 tsf = ath9k_hw_gettsf64(ah);
1536
1537 saveLedState = REG_READ(ah, AR_CFG_LED) &
1538 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1539 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1540
1541 ath9k_hw_mark_phy_inactive(ah);
1542
1543 /* Only required on the first reset */
1544 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1545 REG_WRITE(ah,
1546 AR9271_RESET_POWER_DOWN_CONTROL,
1547 AR9271_RADIO_RF_RST);
1548 udelay(50);
1549 }
1550
1551 if (!ath9k_hw_chip_reset(ah, chan)) {
1552 ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n");
1553 return -EINVAL;
1554 }
1555
1556 /* Only required on the first reset */
1557 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1558 ah->htc_reset_init = false;
1559 REG_WRITE(ah,
1560 AR9271_RESET_POWER_DOWN_CONTROL,
1561 AR9271_GATE_MAC_CTL);
1562 udelay(50);
1563 }
1564
1565 /* Restore TSF */
1566 if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1567 ath9k_hw_settsf64(ah, tsf);
1568
1569 if (AR_SREV_9280_10_OR_LATER(ah))
1570 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1571
1572 r = ath9k_hw_process_ini(ah, chan);
1573 if (r)
1574 return r;
1575
1576 /* Setup MFP options for CCMP */
1577 if (AR_SREV_9280_20_OR_LATER(ah)) {
1578 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1579 * frames when constructing CCMP AAD. */
1580 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1581 0xc7ff);
1582 ah->sw_mgmt_crypto = false;
1583 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1584 /* Disable hardware crypto for management frames */
1585 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1586 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1587 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1588 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1589 ah->sw_mgmt_crypto = true;
1590 } else
1591 ah->sw_mgmt_crypto = true;
1592
1593 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1594 ath9k_hw_set_delta_slope(ah, chan);
1595
1596 ath9k_hw_spur_mitigate_freq(ah, chan);
1597 ah->eep_ops->set_board_values(ah, chan);
1598
1599 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
1600 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
1601 | macStaId1
1602 | AR_STA_ID1_RTS_USE_DEF
1603 | (ah->config.
1604 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
1605 | ah->sta_id1_defaults);
1606 ath9k_hw_set_operating_mode(ah, ah->opmode);
1607
1608 ath_hw_setbssidmask(common);
1609
1610 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1611
1612 ath9k_hw_write_associd(ah);
1613
1614 REG_WRITE(ah, AR_ISR, ~0);
1615
1616 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1617
1618 r = ath9k_hw_rf_set_freq(ah, chan);
1619 if (r)
1620 return r;
1621
1622 for (i = 0; i < AR_NUM_DCU; i++)
1623 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1624
1625 ah->intr_txqs = 0;
1626 for (i = 0; i < ah->caps.total_queues; i++)
1627 ath9k_hw_resettxqueue(ah, i);
1628
1629 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
1630 ath9k_hw_init_qos(ah);
1631
1632 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1633 ath9k_enable_rfkill(ah);
1634
1635 ath9k_hw_init_global_settings(ah);
1636
1637 if (AR_SREV_9287_12_OR_LATER(ah)) {
1638 REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
1639 AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
1640 REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
1641 AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
1642 REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
1643 AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
1644
1645 REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
1646 REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
1647
1648 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
1649 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
1650 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
1651 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
1652 }
1653 if (AR_SREV_9287_12_OR_LATER(ah)) {
1654 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1655 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
1656 }
1657
1658 REG_WRITE(ah, AR_STA_ID1,
1659 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
1660
1661 ath9k_hw_set_dma(ah);
1662
1663 REG_WRITE(ah, AR_OBS, 8);
1664
1665 if (ah->config.rx_intr_mitigation) {
1666 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
1667 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
1668 }
1669
1670 ath9k_hw_init_bb(ah, chan);
1671
1672 if (!ath9k_hw_init_cal(ah, chan))
1673 return -EIO;
1674
1675 ath9k_hw_restore_chainmask(ah);
1676 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1677
1678 /*
1679 * For big endian systems turn on swapping for descriptors
1680 */
1681 if (AR_SREV_9100(ah)) {
1682 u32 mask;
1683 mask = REG_READ(ah, AR_CFG);
1684 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1685 ath_print(common, ATH_DBG_RESET,
1686 "CFG Byte Swap Set 0x%x\n", mask);
1687 } else {
1688 mask =
1689 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1690 REG_WRITE(ah, AR_CFG, mask);
1691 ath_print(common, ATH_DBG_RESET,
1692 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
1693 }
1694 } else {
1695 /* Configure AR9271 target WLAN */
1696 if (AR_SREV_9271(ah))
1697 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1698 #ifdef __BIG_ENDIAN
1699 else
1700 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1701 #endif
1702 }
1703
1704 if (ah->btcoex_hw.enabled)
1705 ath9k_hw_btcoex_enable(ah);
1706
1707 return 0;
1708 }
1709 EXPORT_SYMBOL(ath9k_hw_reset);
1710
1711 /************************/
1712 /* Key Cache Management */
1713 /************************/
1714
1715 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
1716 {
1717 u32 keyType;
1718
1719 if (entry >= ah->caps.keycache_size) {
1720 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1721 "keychache entry %u out of range\n", entry);
1722 return false;
1723 }
1724
1725 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
1726
1727 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
1728 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
1729 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
1730 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
1731 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
1732 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
1733 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
1734 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
1735
1736 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
1737 u16 micentry = entry + 64;
1738
1739 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
1740 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
1741 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
1742 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
1743
1744 }
1745
1746 return true;
1747 }
1748 EXPORT_SYMBOL(ath9k_hw_keyreset);
1749
1750 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
1751 {
1752 u32 macHi, macLo;
1753
1754 if (entry >= ah->caps.keycache_size) {
1755 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1756 "keychache entry %u out of range\n", entry);
1757 return false;
1758 }
1759
1760 if (mac != NULL) {
1761 macHi = (mac[5] << 8) | mac[4];
1762 macLo = (mac[3] << 24) |
1763 (mac[2] << 16) |
1764 (mac[1] << 8) |
1765 mac[0];
1766 macLo >>= 1;
1767 macLo |= (macHi & 1) << 31;
1768 macHi >>= 1;
1769 } else {
1770 macLo = macHi = 0;
1771 }
1772 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
1773 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
1774
1775 return true;
1776 }
1777 EXPORT_SYMBOL(ath9k_hw_keysetmac);
1778
1779 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
1780 const struct ath9k_keyval *k,
1781 const u8 *mac)
1782 {
1783 const struct ath9k_hw_capabilities *pCap = &ah->caps;
1784 struct ath_common *common = ath9k_hw_common(ah);
1785 u32 key0, key1, key2, key3, key4;
1786 u32 keyType;
1787
1788 if (entry >= pCap->keycache_size) {
1789 ath_print(common, ATH_DBG_FATAL,
1790 "keycache entry %u out of range\n", entry);
1791 return false;
1792 }
1793
1794 switch (k->kv_type) {
1795 case ATH9K_CIPHER_AES_OCB:
1796 keyType = AR_KEYTABLE_TYPE_AES;
1797 break;
1798 case ATH9K_CIPHER_AES_CCM:
1799 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
1800 ath_print(common, ATH_DBG_ANY,
1801 "AES-CCM not supported by mac rev 0x%x\n",
1802 ah->hw_version.macRev);
1803 return false;
1804 }
1805 keyType = AR_KEYTABLE_TYPE_CCM;
1806 break;
1807 case ATH9K_CIPHER_TKIP:
1808 keyType = AR_KEYTABLE_TYPE_TKIP;
1809 if (ATH9K_IS_MIC_ENABLED(ah)
1810 && entry + 64 >= pCap->keycache_size) {
1811 ath_print(common, ATH_DBG_ANY,
1812 "entry %u inappropriate for TKIP\n", entry);
1813 return false;
1814 }
1815 break;
1816 case ATH9K_CIPHER_WEP:
1817 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
1818 ath_print(common, ATH_DBG_ANY,
1819 "WEP key length %u too small\n", k->kv_len);
1820 return false;
1821 }
1822 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
1823 keyType = AR_KEYTABLE_TYPE_40;
1824 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
1825 keyType = AR_KEYTABLE_TYPE_104;
1826 else
1827 keyType = AR_KEYTABLE_TYPE_128;
1828 break;
1829 case ATH9K_CIPHER_CLR:
1830 keyType = AR_KEYTABLE_TYPE_CLR;
1831 break;
1832 default:
1833 ath_print(common, ATH_DBG_FATAL,
1834 "cipher %u not supported\n", k->kv_type);
1835 return false;
1836 }
1837
1838 key0 = get_unaligned_le32(k->kv_val + 0);
1839 key1 = get_unaligned_le16(k->kv_val + 4);
1840 key2 = get_unaligned_le32(k->kv_val + 6);
1841 key3 = get_unaligned_le16(k->kv_val + 10);
1842 key4 = get_unaligned_le32(k->kv_val + 12);
1843 if (k->kv_len <= WLAN_KEY_LEN_WEP104)
1844 key4 &= 0xff;
1845
1846 /*
1847 * Note: Key cache registers access special memory area that requires
1848 * two 32-bit writes to actually update the values in the internal
1849 * memory. Consequently, the exact order and pairs used here must be
1850 * maintained.
1851 */
1852
1853 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
1854 u16 micentry = entry + 64;
1855
1856 /*
1857 * Write inverted key[47:0] first to avoid Michael MIC errors
1858 * on frames that could be sent or received at the same time.
1859 * The correct key will be written in the end once everything
1860 * else is ready.
1861 */
1862 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
1863 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
1864
1865 /* Write key[95:48] */
1866 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
1867 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
1868
1869 /* Write key[127:96] and key type */
1870 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
1871 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
1872
1873 /* Write MAC address for the entry */
1874 (void) ath9k_hw_keysetmac(ah, entry, mac);
1875
1876 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
1877 /*
1878 * TKIP uses two key cache entries:
1879 * Michael MIC TX/RX keys in the same key cache entry
1880 * (idx = main index + 64):
1881 * key0 [31:0] = RX key [31:0]
1882 * key1 [15:0] = TX key [31:16]
1883 * key1 [31:16] = reserved
1884 * key2 [31:0] = RX key [63:32]
1885 * key3 [15:0] = TX key [15:0]
1886 * key3 [31:16] = reserved
1887 * key4 [31:0] = TX key [63:32]
1888 */
1889 u32 mic0, mic1, mic2, mic3, mic4;
1890
1891 mic0 = get_unaligned_le32(k->kv_mic + 0);
1892 mic2 = get_unaligned_le32(k->kv_mic + 4);
1893 mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
1894 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
1895 mic4 = get_unaligned_le32(k->kv_txmic + 4);
1896
1897 /* Write RX[31:0] and TX[31:16] */
1898 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
1899 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
1900
1901 /* Write RX[63:32] and TX[15:0] */
1902 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
1903 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
1904
1905 /* Write TX[63:32] and keyType(reserved) */
1906 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
1907 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
1908 AR_KEYTABLE_TYPE_CLR);
1909
1910 } else {
1911 /*
1912 * TKIP uses four key cache entries (two for group
1913 * keys):
1914 * Michael MIC TX/RX keys are in different key cache
1915 * entries (idx = main index + 64 for TX and
1916 * main index + 32 + 96 for RX):
1917 * key0 [31:0] = TX/RX MIC key [31:0]
1918 * key1 [31:0] = reserved
1919 * key2 [31:0] = TX/RX MIC key [63:32]
1920 * key3 [31:0] = reserved
1921 * key4 [31:0] = reserved
1922 *
1923 * Upper layer code will call this function separately
1924 * for TX and RX keys when these registers offsets are
1925 * used.
1926 */
1927 u32 mic0, mic2;
1928
1929 mic0 = get_unaligned_le32(k->kv_mic + 0);
1930 mic2 = get_unaligned_le32(k->kv_mic + 4);
1931
1932 /* Write MIC key[31:0] */
1933 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
1934 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
1935
1936 /* Write MIC key[63:32] */
1937 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
1938 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
1939
1940 /* Write TX[63:32] and keyType(reserved) */
1941 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
1942 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
1943 AR_KEYTABLE_TYPE_CLR);
1944 }
1945
1946 /* MAC address registers are reserved for the MIC entry */
1947 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
1948 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
1949
1950 /*
1951 * Write the correct (un-inverted) key[47:0] last to enable
1952 * TKIP now that all other registers are set with correct
1953 * values.
1954 */
1955 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
1956 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
1957 } else {
1958 /* Write key[47:0] */
1959 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
1960 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
1961
1962 /* Write key[95:48] */
1963 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
1964 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
1965
1966 /* Write key[127:96] and key type */
1967 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
1968 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
1969
1970 /* Write MAC address for the entry */
1971 (void) ath9k_hw_keysetmac(ah, entry, mac);
1972 }
1973
1974 return true;
1975 }
1976 EXPORT_SYMBOL(ath9k_hw_set_keycache_entry);
1977
1978 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
1979 {
1980 if (entry < ah->caps.keycache_size) {
1981 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
1982 if (val & AR_KEYTABLE_VALID)
1983 return true;
1984 }
1985 return false;
1986 }
1987 EXPORT_SYMBOL(ath9k_hw_keyisvalid);
1988
1989 /******************************/
1990 /* Power Management (Chipset) */
1991 /******************************/
1992
1993 /*
1994 * Notify Power Mgt is disabled in self-generated frames.
1995 * If requested, force chip to sleep.
1996 */
1997 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
1998 {
1999 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2000 if (setChip) {
2001 /*
2002 * Clear the RTC force wake bit to allow the
2003 * mac to go to sleep.
2004 */
2005 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2006 AR_RTC_FORCE_WAKE_EN);
2007 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
2008 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2009
2010 /* Shutdown chip. Active low */
2011 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah))
2012 REG_CLR_BIT(ah, (AR_RTC_RESET),
2013 AR_RTC_RESET_EN);
2014 }
2015 }
2016
2017 /*
2018 * Notify Power Management is enabled in self-generating
2019 * frames. If request, set power mode of chip to
2020 * auto/normal. Duration in units of 128us (1/8 TU).
2021 */
2022 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
2023 {
2024 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2025 if (setChip) {
2026 struct ath9k_hw_capabilities *pCap = &ah->caps;
2027
2028 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2029 /* Set WakeOnInterrupt bit; clear ForceWake bit */
2030 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2031 AR_RTC_FORCE_WAKE_ON_INT);
2032 } else {
2033 /*
2034 * Clear the RTC force wake bit to allow the
2035 * mac to go to sleep.
2036 */
2037 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2038 AR_RTC_FORCE_WAKE_EN);
2039 }
2040 }
2041 }
2042
2043 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2044 {
2045 u32 val;
2046 int i;
2047
2048 if (setChip) {
2049 if ((REG_READ(ah, AR_RTC_STATUS) &
2050 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2051 if (ath9k_hw_set_reset_reg(ah,
2052 ATH9K_RESET_POWER_ON) != true) {
2053 return false;
2054 }
2055 if (!AR_SREV_9300_20_OR_LATER(ah))
2056 ath9k_hw_init_pll(ah, NULL);
2057 }
2058 if (AR_SREV_9100(ah))
2059 REG_SET_BIT(ah, AR_RTC_RESET,
2060 AR_RTC_RESET_EN);
2061
2062 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2063 AR_RTC_FORCE_WAKE_EN);
2064 udelay(50);
2065
2066 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2067 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2068 if (val == AR_RTC_STATUS_ON)
2069 break;
2070 udelay(50);
2071 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2072 AR_RTC_FORCE_WAKE_EN);
2073 }
2074 if (i == 0) {
2075 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2076 "Failed to wakeup in %uus\n",
2077 POWER_UP_TIME / 20);
2078 return false;
2079 }
2080 }
2081
2082 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2083
2084 return true;
2085 }
2086
2087 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2088 {
2089 struct ath_common *common = ath9k_hw_common(ah);
2090 int status = true, setChip = true;
2091 static const char *modes[] = {
2092 "AWAKE",
2093 "FULL-SLEEP",
2094 "NETWORK SLEEP",
2095 "UNDEFINED"
2096 };
2097
2098 if (ah->power_mode == mode)
2099 return status;
2100
2101 ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
2102 modes[ah->power_mode], modes[mode]);
2103
2104 switch (mode) {
2105 case ATH9K_PM_AWAKE:
2106 status = ath9k_hw_set_power_awake(ah, setChip);
2107 break;
2108 case ATH9K_PM_FULL_SLEEP:
2109 ath9k_set_power_sleep(ah, setChip);
2110 ah->chip_fullsleep = true;
2111 break;
2112 case ATH9K_PM_NETWORK_SLEEP:
2113 ath9k_set_power_network_sleep(ah, setChip);
2114 break;
2115 default:
2116 ath_print(common, ATH_DBG_FATAL,
2117 "Unknown power mode %u\n", mode);
2118 return false;
2119 }
2120 ah->power_mode = mode;
2121
2122 return status;
2123 }
2124 EXPORT_SYMBOL(ath9k_hw_setpower);
2125
2126 /*
2127 * Helper for ASPM support.
2128 *
2129 * Disable PLL when in L0s as well as receiver clock when in L1.
2130 * This power saving option must be enabled through the SerDes.
2131 *
2132 * Programming the SerDes must go through the same 288 bit serial shift
2133 * register as the other analog registers. Hence the 9 writes.
2134 */
2135 static void ar9002_hw_configpcipowersave(struct ath_hw *ah,
2136 int restore,
2137 int power_off)
2138 {
2139 u8 i;
2140 u32 val;
2141
2142 if (ah->is_pciexpress != true)
2143 return;
2144
2145 /* Do not touch SerDes registers */
2146 if (ah->config.pcie_powersave_enable == 2)
2147 return;
2148
2149 /* Nothing to do on restore for 11N */
2150 if (!restore) {
2151 if (AR_SREV_9280_20_OR_LATER(ah)) {
2152 /*
2153 * AR9280 2.0 or later chips use SerDes values from the
2154 * initvals.h initialized depending on chipset during
2155 * __ath9k_hw_init()
2156 */
2157 for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
2158 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
2159 INI_RA(&ah->iniPcieSerdes, i, 1));
2160 }
2161 } else if (AR_SREV_9280(ah) &&
2162 (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
2163 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2164 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2165
2166 /* RX shut off when elecidle is asserted */
2167 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2168 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2169 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2170
2171 /* Shut off CLKREQ active in L1 */
2172 if (ah->config.pcie_clock_req)
2173 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2174 else
2175 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
2176
2177 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2178 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2179 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
2180
2181 /* Load the new settings */
2182 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2183
2184 } else {
2185 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2186 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2187
2188 /* RX shut off when elecidle is asserted */
2189 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2190 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2191 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
2192
2193 /*
2194 * Ignore ah->ah_config.pcie_clock_req setting for
2195 * pre-AR9280 11n
2196 */
2197 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2198
2199 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2200 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2201 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
2202
2203 /* Load the new settings */
2204 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2205 }
2206
2207 udelay(1000);
2208
2209 /* set bit 19 to allow forcing of pcie core into L1 state */
2210 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
2211
2212 /* Several PCIe massages to ensure proper behaviour */
2213 if (ah->config.pcie_waen) {
2214 val = ah->config.pcie_waen;
2215 if (!power_off)
2216 val &= (~AR_WA_D3_L1_DISABLE);
2217 } else {
2218 if (AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
2219 AR_SREV_9287(ah)) {
2220 val = AR9285_WA_DEFAULT;
2221 if (!power_off)
2222 val &= (~AR_WA_D3_L1_DISABLE);
2223 } else if (AR_SREV_9280(ah)) {
2224 /*
2225 * On AR9280 chips bit 22 of 0x4004 needs to be
2226 * set otherwise card may disappear.
2227 */
2228 val = AR9280_WA_DEFAULT;
2229 if (!power_off)
2230 val &= (~AR_WA_D3_L1_DISABLE);
2231 } else
2232 val = AR_WA_DEFAULT;
2233 }
2234
2235 REG_WRITE(ah, AR_WA, val);
2236 }
2237
2238 if (power_off) {
2239 /*
2240 * Set PCIe workaround bits
2241 * bit 14 in WA register (disable L1) should only
2242 * be set when device enters D3 and be cleared
2243 * when device comes back to D0.
2244 */
2245 if (ah->config.pcie_waen) {
2246 if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE)
2247 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
2248 } else {
2249 if (((AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
2250 AR_SREV_9287(ah)) &&
2251 (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) ||
2252 (AR_SREV_9280(ah) &&
2253 (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) {
2254 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
2255 }
2256 }
2257 }
2258 }
2259
2260 /**********************/
2261 /* Interrupt Handling */
2262 /**********************/
2263
2264 bool ath9k_hw_intrpend(struct ath_hw *ah)
2265 {
2266 u32 host_isr;
2267
2268 if (AR_SREV_9100(ah))
2269 return true;
2270
2271 host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
2272 if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
2273 return true;
2274
2275 host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
2276 if ((host_isr & AR_INTR_SYNC_DEFAULT)
2277 && (host_isr != AR_INTR_SPURIOUS))
2278 return true;
2279
2280 return false;
2281 }
2282 EXPORT_SYMBOL(ath9k_hw_intrpend);
2283
2284 bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
2285 {
2286 u32 isr = 0;
2287 u32 mask2 = 0;
2288 struct ath9k_hw_capabilities *pCap = &ah->caps;
2289 u32 sync_cause = 0;
2290 bool fatal_int = false;
2291 struct ath_common *common = ath9k_hw_common(ah);
2292
2293 if (!AR_SREV_9100(ah)) {
2294 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
2295 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
2296 == AR_RTC_STATUS_ON) {
2297 isr = REG_READ(ah, AR_ISR);
2298 }
2299 }
2300
2301 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
2302 AR_INTR_SYNC_DEFAULT;
2303
2304 *masked = 0;
2305
2306 if (!isr && !sync_cause)
2307 return false;
2308 } else {
2309 *masked = 0;
2310 isr = REG_READ(ah, AR_ISR);
2311 }
2312
2313 if (isr) {
2314 if (isr & AR_ISR_BCNMISC) {
2315 u32 isr2;
2316 isr2 = REG_READ(ah, AR_ISR_S2);
2317 if (isr2 & AR_ISR_S2_TIM)
2318 mask2 |= ATH9K_INT_TIM;
2319 if (isr2 & AR_ISR_S2_DTIM)
2320 mask2 |= ATH9K_INT_DTIM;
2321 if (isr2 & AR_ISR_S2_DTIMSYNC)
2322 mask2 |= ATH9K_INT_DTIMSYNC;
2323 if (isr2 & (AR_ISR_S2_CABEND))
2324 mask2 |= ATH9K_INT_CABEND;
2325 if (isr2 & AR_ISR_S2_GTT)
2326 mask2 |= ATH9K_INT_GTT;
2327 if (isr2 & AR_ISR_S2_CST)
2328 mask2 |= ATH9K_INT_CST;
2329 if (isr2 & AR_ISR_S2_TSFOOR)
2330 mask2 |= ATH9K_INT_TSFOOR;
2331 }
2332
2333 isr = REG_READ(ah, AR_ISR_RAC);
2334 if (isr == 0xffffffff) {
2335 *masked = 0;
2336 return false;
2337 }
2338
2339 *masked = isr & ATH9K_INT_COMMON;
2340
2341 if (ah->config.rx_intr_mitigation) {
2342 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
2343 *masked |= ATH9K_INT_RX;
2344 }
2345
2346 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
2347 *masked |= ATH9K_INT_RX;
2348 if (isr &
2349 (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
2350 AR_ISR_TXEOL)) {
2351 u32 s0_s, s1_s;
2352
2353 *masked |= ATH9K_INT_TX;
2354
2355 s0_s = REG_READ(ah, AR_ISR_S0_S);
2356 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
2357 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
2358
2359 s1_s = REG_READ(ah, AR_ISR_S1_S);
2360 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
2361 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
2362 }
2363
2364 if (isr & AR_ISR_RXORN) {
2365 ath_print(common, ATH_DBG_INTERRUPT,
2366 "receive FIFO overrun interrupt\n");
2367 }
2368
2369 if (!AR_SREV_9100(ah)) {
2370 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2371 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
2372 if (isr5 & AR_ISR_S5_TIM_TIMER)
2373 *masked |= ATH9K_INT_TIM_TIMER;
2374 }
2375 }
2376
2377 *masked |= mask2;
2378 }
2379
2380 if (AR_SREV_9100(ah))
2381 return true;
2382
2383 if (isr & AR_ISR_GENTMR) {
2384 u32 s5_s;
2385
2386 s5_s = REG_READ(ah, AR_ISR_S5_S);
2387 if (isr & AR_ISR_GENTMR) {
2388 ah->intr_gen_timer_trigger =
2389 MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
2390
2391 ah->intr_gen_timer_thresh =
2392 MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);
2393
2394 if (ah->intr_gen_timer_trigger)
2395 *masked |= ATH9K_INT_GENTIMER;
2396
2397 }
2398 }
2399
2400 if (sync_cause) {
2401 fatal_int =
2402 (sync_cause &
2403 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
2404 ? true : false;
2405
2406 if (fatal_int) {
2407 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
2408 ath_print(common, ATH_DBG_ANY,
2409 "received PCI FATAL interrupt\n");
2410 }
2411 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
2412 ath_print(common, ATH_DBG_ANY,
2413 "received PCI PERR interrupt\n");
2414 }
2415 *masked |= ATH9K_INT_FATAL;
2416 }
2417 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
2418 ath_print(common, ATH_DBG_INTERRUPT,
2419 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
2420 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
2421 REG_WRITE(ah, AR_RC, 0);
2422 *masked |= ATH9K_INT_FATAL;
2423 }
2424 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
2425 ath_print(common, ATH_DBG_INTERRUPT,
2426 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
2427 }
2428
2429 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
2430 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
2431 }
2432
2433 return true;
2434 }
2435 EXPORT_SYMBOL(ath9k_hw_getisr);
2436
2437 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
2438 {
2439 enum ath9k_int omask = ah->imask;
2440 u32 mask, mask2;
2441 struct ath9k_hw_capabilities *pCap = &ah->caps;
2442 struct ath_common *common = ath9k_hw_common(ah);
2443
2444 ath_print(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
2445
2446 if (omask & ATH9K_INT_GLOBAL) {
2447 ath_print(common, ATH_DBG_INTERRUPT, "disable IER\n");
2448 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
2449 (void) REG_READ(ah, AR_IER);
2450 if (!AR_SREV_9100(ah)) {
2451 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
2452 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
2453
2454 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
2455 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
2456 }
2457 }
2458
2459 mask = ints & ATH9K_INT_COMMON;
2460 mask2 = 0;
2461
2462 if (ints & ATH9K_INT_TX) {
2463 if (ah->txok_interrupt_mask)
2464 mask |= AR_IMR_TXOK;
2465 if (ah->txdesc_interrupt_mask)
2466 mask |= AR_IMR_TXDESC;
2467 if (ah->txerr_interrupt_mask)
2468 mask |= AR_IMR_TXERR;
2469 if (ah->txeol_interrupt_mask)
2470 mask |= AR_IMR_TXEOL;
2471 }
2472 if (ints & ATH9K_INT_RX) {
2473 mask |= AR_IMR_RXERR;
2474 if (ah->config.rx_intr_mitigation)
2475 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
2476 else
2477 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
2478 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
2479 mask |= AR_IMR_GENTMR;
2480 }
2481
2482 if (ints & (ATH9K_INT_BMISC)) {
2483 mask |= AR_IMR_BCNMISC;
2484 if (ints & ATH9K_INT_TIM)
2485 mask2 |= AR_IMR_S2_TIM;
2486 if (ints & ATH9K_INT_DTIM)
2487 mask2 |= AR_IMR_S2_DTIM;
2488 if (ints & ATH9K_INT_DTIMSYNC)
2489 mask2 |= AR_IMR_S2_DTIMSYNC;
2490 if (ints & ATH9K_INT_CABEND)
2491 mask2 |= AR_IMR_S2_CABEND;
2492 if (ints & ATH9K_INT_TSFOOR)
2493 mask2 |= AR_IMR_S2_TSFOOR;
2494 }
2495
2496 if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
2497 mask |= AR_IMR_BCNMISC;
2498 if (ints & ATH9K_INT_GTT)
2499 mask2 |= AR_IMR_S2_GTT;
2500 if (ints & ATH9K_INT_CST)
2501 mask2 |= AR_IMR_S2_CST;
2502 }
2503
2504 ath_print(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
2505 REG_WRITE(ah, AR_IMR, mask);
2506 ah->imrs2_reg &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC |
2507 AR_IMR_S2_CABEND | AR_IMR_S2_CABTO |
2508 AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST);
2509 ah->imrs2_reg |= mask2;
2510 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
2511
2512 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2513 if (ints & ATH9K_INT_TIM_TIMER)
2514 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
2515 else
2516 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
2517 }
2518
2519 if (ints & ATH9K_INT_GLOBAL) {
2520 ath_print(common, ATH_DBG_INTERRUPT, "enable IER\n");
2521 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
2522 if (!AR_SREV_9100(ah)) {
2523 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
2524 AR_INTR_MAC_IRQ);
2525 REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
2526
2527
2528 REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
2529 AR_INTR_SYNC_DEFAULT);
2530 REG_WRITE(ah, AR_INTR_SYNC_MASK,
2531 AR_INTR_SYNC_DEFAULT);
2532 }
2533 ath_print(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
2534 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
2535 }
2536
2537 return omask;
2538 }
2539 EXPORT_SYMBOL(ath9k_hw_set_interrupts);
2540
2541 /*******************/
2542 /* Beacon Handling */
2543 /*******************/
2544
2545 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
2546 {
2547 int flags = 0;
2548
2549 ah->beacon_interval = beacon_period;
2550
2551 switch (ah->opmode) {
2552 case NL80211_IFTYPE_STATION:
2553 case NL80211_IFTYPE_MONITOR:
2554 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
2555 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
2556 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
2557 flags |= AR_TBTT_TIMER_EN;
2558 break;
2559 case NL80211_IFTYPE_ADHOC:
2560 case NL80211_IFTYPE_MESH_POINT:
2561 REG_SET_BIT(ah, AR_TXCFG,
2562 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
2563 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
2564 TU_TO_USEC(next_beacon +
2565 (ah->atim_window ? ah->
2566 atim_window : 1)));
2567 flags |= AR_NDP_TIMER_EN;
2568 case NL80211_IFTYPE_AP:
2569 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
2570 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
2571 TU_TO_USEC(next_beacon -
2572 ah->config.
2573 dma_beacon_response_time));
2574 REG_WRITE(ah, AR_NEXT_SWBA,
2575 TU_TO_USEC(next_beacon -
2576 ah->config.
2577 sw_beacon_response_time));
2578 flags |=
2579 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
2580 break;
2581 default:
2582 ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
2583 "%s: unsupported opmode: %d\n",
2584 __func__, ah->opmode);
2585 return;
2586 break;
2587 }
2588
2589 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
2590 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
2591 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
2592 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
2593
2594 beacon_period &= ~ATH9K_BEACON_ENA;
2595 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
2596 ath9k_hw_reset_tsf(ah);
2597 }
2598
2599 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
2600 }
2601 EXPORT_SYMBOL(ath9k_hw_beaconinit);
2602
2603 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
2604 const struct ath9k_beacon_state *bs)
2605 {
2606 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
2607 struct ath9k_hw_capabilities *pCap = &ah->caps;
2608 struct ath_common *common = ath9k_hw_common(ah);
2609
2610 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
2611
2612 REG_WRITE(ah, AR_BEACON_PERIOD,
2613 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
2614 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
2615 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
2616
2617 REG_RMW_FIELD(ah, AR_RSSI_THR,
2618 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
2619
2620 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
2621
2622 if (bs->bs_sleepduration > beaconintval)
2623 beaconintval = bs->bs_sleepduration;
2624
2625 dtimperiod = bs->bs_dtimperiod;
2626 if (bs->bs_sleepduration > dtimperiod)
2627 dtimperiod = bs->bs_sleepduration;
2628
2629 if (beaconintval == dtimperiod)
2630 nextTbtt = bs->bs_nextdtim;
2631 else
2632 nextTbtt = bs->bs_nexttbtt;
2633
2634 ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
2635 ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
2636 ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
2637 ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
2638
2639 REG_WRITE(ah, AR_NEXT_DTIM,
2640 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
2641 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
2642
2643 REG_WRITE(ah, AR_SLEEP1,
2644 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
2645 | AR_SLEEP1_ASSUME_DTIM);
2646
2647 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
2648 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
2649 else
2650 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
2651
2652 REG_WRITE(ah, AR_SLEEP2,
2653 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
2654
2655 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
2656 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
2657
2658 REG_SET_BIT(ah, AR_TIMER_MODE,
2659 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
2660 AR_DTIM_TIMER_EN);
2661
2662 /* TSF Out of Range Threshold */
2663 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
2664 }
2665 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
2666
2667 /*******************/
2668 /* HW Capabilities */
2669 /*******************/
2670
2671 int ath9k_hw_fill_cap_info(struct ath_hw *ah)
2672 {
2673 struct ath9k_hw_capabilities *pCap = &ah->caps;
2674 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2675 struct ath_common *common = ath9k_hw_common(ah);
2676 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
2677
2678 u16 capField = 0, eeval;
2679
2680 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
2681 regulatory->current_rd = eeval;
2682
2683 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
2684 if (AR_SREV_9285_10_OR_LATER(ah))
2685 eeval |= AR9285_RDEXT_DEFAULT;
2686 regulatory->current_rd_ext = eeval;
2687
2688 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
2689
2690 if (ah->opmode != NL80211_IFTYPE_AP &&
2691 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
2692 if (regulatory->current_rd == 0x64 ||
2693 regulatory->current_rd == 0x65)
2694 regulatory->current_rd += 5;
2695 else if (regulatory->current_rd == 0x41)
2696 regulatory->current_rd = 0x43;
2697 ath_print(common, ATH_DBG_REGULATORY,
2698 "regdomain mapped to 0x%x\n", regulatory->current_rd);
2699 }
2700
2701 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
2702 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
2703 ath_print(common, ATH_DBG_FATAL,
2704 "no band has been marked as supported in EEPROM.\n");
2705 return -EINVAL;
2706 }
2707
2708 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
2709
2710 if (eeval & AR5416_OPFLAGS_11A) {
2711 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
2712 if (ah->config.ht_enable) {
2713 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
2714 set_bit(ATH9K_MODE_11NA_HT20,
2715 pCap->wireless_modes);
2716 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
2717 set_bit(ATH9K_MODE_11NA_HT40PLUS,
2718 pCap->wireless_modes);
2719 set_bit(ATH9K_MODE_11NA_HT40MINUS,
2720 pCap->wireless_modes);
2721 }
2722 }
2723 }
2724
2725 if (eeval & AR5416_OPFLAGS_11G) {
2726 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
2727 if (ah->config.ht_enable) {
2728 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
2729 set_bit(ATH9K_MODE_11NG_HT20,
2730 pCap->wireless_modes);
2731 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
2732 set_bit(ATH9K_MODE_11NG_HT40PLUS,
2733 pCap->wireless_modes);
2734 set_bit(ATH9K_MODE_11NG_HT40MINUS,
2735 pCap->wireless_modes);
2736 }
2737 }
2738 }
2739
2740 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
2741 /*
2742 * For AR9271 we will temporarilly uses the rx chainmax as read from
2743 * the EEPROM.
2744 */
2745 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
2746 !(eeval & AR5416_OPFLAGS_11A) &&
2747 !(AR_SREV_9271(ah)))
2748 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
2749 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
2750 else
2751 /* Use rx_chainmask from EEPROM. */
2752 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
2753
2754 if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
2755 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
2756
2757 pCap->low_2ghz_chan = 2312;
2758 pCap->high_2ghz_chan = 2732;
2759
2760 pCap->low_5ghz_chan = 4920;
2761 pCap->high_5ghz_chan = 6100;
2762
2763 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
2764 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
2765 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
2766
2767 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
2768 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
2769 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
2770
2771 if (ah->config.ht_enable)
2772 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2773 else
2774 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
2775
2776 pCap->hw_caps |= ATH9K_HW_CAP_GTT;
2777 pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
2778 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
2779 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
2780
2781 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
2782 pCap->total_queues =
2783 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
2784 else
2785 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
2786
2787 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
2788 pCap->keycache_size =
2789 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
2790 else
2791 pCap->keycache_size = AR_KEYTABLE_SIZE;
2792
2793 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
2794
2795 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
2796 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1;
2797 else
2798 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
2799
2800 if (AR_SREV_9271(ah))
2801 pCap->num_gpio_pins = AR9271_NUM_GPIO;
2802 else if (AR_SREV_9285_10_OR_LATER(ah))
2803 pCap->num_gpio_pins = AR9285_NUM_GPIO;
2804 else if (AR_SREV_9280_10_OR_LATER(ah))
2805 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2806 else
2807 pCap->num_gpio_pins = AR_NUM_GPIO;
2808
2809 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
2810 pCap->hw_caps |= ATH9K_HW_CAP_CST;
2811 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
2812 } else {
2813 pCap->rts_aggr_limit = (8 * 1024);
2814 }
2815
2816 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
2817
2818 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2819 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2820 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2821 ah->rfkill_gpio =
2822 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2823 ah->rfkill_polarity =
2824 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
2825
2826 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
2827 }
2828 #endif
2829 if (AR_SREV_9271(ah))
2830 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2831 else
2832 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
2833
2834 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
2835 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2836 else
2837 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
2838
2839 if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
2840 pCap->reg_cap =
2841 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
2842 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
2843 AR_EEPROM_EEREGCAP_EN_KK_U2 |
2844 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
2845 } else {
2846 pCap->reg_cap =
2847 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
2848 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
2849 }
2850
2851 /* Advertise midband for AR5416 with FCC midband set in eeprom */
2852 if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
2853 AR_SREV_5416(ah))
2854 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
2855
2856 pCap->num_antcfg_5ghz =
2857 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
2858 pCap->num_antcfg_2ghz =
2859 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
2860
2861 if (AR_SREV_9280_10_OR_LATER(ah) &&
2862 ath9k_hw_btcoex_supported(ah)) {
2863 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
2864 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
2865
2866 if (AR_SREV_9285(ah)) {
2867 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
2868 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
2869 } else {
2870 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
2871 }
2872 } else {
2873 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
2874 }
2875
2876 if (AR_SREV_9300_20_OR_LATER(ah)) {
2877 pCap->hw_caps |= ATH9K_HW_CAP_EDMA;
2878 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2879 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2880 pCap->rx_status_len = sizeof(struct ar9003_rxs);
2881 }
2882
2883 return 0;
2884 }
2885
2886 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
2887 u32 capability, u32 *result)
2888 {
2889 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2890 switch (type) {
2891 case ATH9K_CAP_CIPHER:
2892 switch (capability) {
2893 case ATH9K_CIPHER_AES_CCM:
2894 case ATH9K_CIPHER_AES_OCB:
2895 case ATH9K_CIPHER_TKIP:
2896 case ATH9K_CIPHER_WEP:
2897 case ATH9K_CIPHER_MIC:
2898 case ATH9K_CIPHER_CLR:
2899 return true;
2900 default:
2901 return false;
2902 }
2903 case ATH9K_CAP_TKIP_MIC:
2904 switch (capability) {
2905 case 0:
2906 return true;
2907 case 1:
2908 return (ah->sta_id1_defaults &
2909 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
2910 false;
2911 }
2912 case ATH9K_CAP_TKIP_SPLIT:
2913 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
2914 false : true;
2915 case ATH9K_CAP_MCAST_KEYSRCH:
2916 switch (capability) {
2917 case 0:
2918 return true;
2919 case 1:
2920 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
2921 return false;
2922 } else {
2923 return (ah->sta_id1_defaults &
2924 AR_STA_ID1_MCAST_KSRCH) ? true :
2925 false;
2926 }
2927 }
2928 return false;
2929 case ATH9K_CAP_TXPOW:
2930 switch (capability) {
2931 case 0:
2932 return 0;
2933 case 1:
2934 *result = regulatory->power_limit;
2935 return 0;
2936 case 2:
2937 *result = regulatory->max_power_level;
2938 return 0;
2939 case 3:
2940 *result = regulatory->tp_scale;
2941 return 0;
2942 }
2943 return false;
2944 case ATH9K_CAP_DS:
2945 return (AR_SREV_9280_20_OR_LATER(ah) &&
2946 (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
2947 ? false : true;
2948 default:
2949 return false;
2950 }
2951 }
2952 EXPORT_SYMBOL(ath9k_hw_getcapability);
2953
2954 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
2955 u32 capability, u32 setting, int *status)
2956 {
2957 switch (type) {
2958 case ATH9K_CAP_TKIP_MIC:
2959 if (setting)
2960 ah->sta_id1_defaults |=
2961 AR_STA_ID1_CRPT_MIC_ENABLE;
2962 else
2963 ah->sta_id1_defaults &=
2964 ~AR_STA_ID1_CRPT_MIC_ENABLE;
2965 return true;
2966 case ATH9K_CAP_MCAST_KEYSRCH:
2967 if (setting)
2968 ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
2969 else
2970 ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
2971 return true;
2972 default:
2973 return false;
2974 }
2975 }
2976 EXPORT_SYMBOL(ath9k_hw_setcapability);
2977
2978 /****************************/
2979 /* GPIO / RFKILL / Antennae */
2980 /****************************/
2981
2982 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
2983 u32 gpio, u32 type)
2984 {
2985 int addr;
2986 u32 gpio_shift, tmp;
2987
2988 if (gpio > 11)
2989 addr = AR_GPIO_OUTPUT_MUX3;
2990 else if (gpio > 5)
2991 addr = AR_GPIO_OUTPUT_MUX2;
2992 else
2993 addr = AR_GPIO_OUTPUT_MUX1;
2994
2995 gpio_shift = (gpio % 6) * 5;
2996
2997 if (AR_SREV_9280_20_OR_LATER(ah)
2998 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2999 REG_RMW(ah, addr, (type << gpio_shift),
3000 (0x1f << gpio_shift));
3001 } else {
3002 tmp = REG_READ(ah, addr);
3003 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3004 tmp &= ~(0x1f << gpio_shift);
3005 tmp |= (type << gpio_shift);
3006 REG_WRITE(ah, addr, tmp);
3007 }
3008 }
3009
3010 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
3011 {
3012 u32 gpio_shift;
3013
3014 BUG_ON(gpio >= ah->caps.num_gpio_pins);
3015
3016 gpio_shift = gpio << 1;
3017
3018 REG_RMW(ah,
3019 AR_GPIO_OE_OUT,
3020 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3021 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3022 }
3023 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
3024
3025 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
3026 {
3027 #define MS_REG_READ(x, y) \
3028 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3029
3030 if (gpio >= ah->caps.num_gpio_pins)
3031 return 0xffffffff;
3032
3033 if (AR_SREV_9300_20_OR_LATER(ah))
3034 return MS_REG_READ(AR9300, gpio) != 0;
3035 else if (AR_SREV_9271(ah))
3036 return MS_REG_READ(AR9271, gpio) != 0;
3037 else if (AR_SREV_9287_10_OR_LATER(ah))
3038 return MS_REG_READ(AR9287, gpio) != 0;
3039 else if (AR_SREV_9285_10_OR_LATER(ah))
3040 return MS_REG_READ(AR9285, gpio) != 0;
3041 else if (AR_SREV_9280_10_OR_LATER(ah))
3042 return MS_REG_READ(AR928X, gpio) != 0;
3043 else
3044 return MS_REG_READ(AR, gpio) != 0;
3045 }
3046 EXPORT_SYMBOL(ath9k_hw_gpio_get);
3047
3048 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
3049 u32 ah_signal_type)
3050 {
3051 u32 gpio_shift;
3052
3053 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
3054
3055 gpio_shift = 2 * gpio;
3056
3057 REG_RMW(ah,
3058 AR_GPIO_OE_OUT,
3059 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3060 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3061 }
3062 EXPORT_SYMBOL(ath9k_hw_cfg_output);
3063
3064 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
3065 {
3066 if (AR_SREV_9271(ah))
3067 val = ~val;
3068
3069 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3070 AR_GPIO_BIT(gpio));
3071 }
3072 EXPORT_SYMBOL(ath9k_hw_set_gpio);
3073
3074 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
3075 {
3076 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3077 }
3078 EXPORT_SYMBOL(ath9k_hw_getdefantenna);
3079
3080 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
3081 {
3082 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3083 }
3084 EXPORT_SYMBOL(ath9k_hw_setantenna);
3085
3086 /*********************/
3087 /* General Operation */
3088 /*********************/
3089
3090 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
3091 {
3092 u32 bits = REG_READ(ah, AR_RX_FILTER);
3093 u32 phybits = REG_READ(ah, AR_PHY_ERR);
3094
3095 if (phybits & AR_PHY_ERR_RADAR)
3096 bits |= ATH9K_RX_FILTER_PHYRADAR;
3097 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3098 bits |= ATH9K_RX_FILTER_PHYERR;
3099
3100 return bits;
3101 }
3102 EXPORT_SYMBOL(ath9k_hw_getrxfilter);
3103
3104 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
3105 {
3106 u32 phybits;
3107
3108 REG_WRITE(ah, AR_RX_FILTER, bits);
3109
3110 phybits = 0;
3111 if (bits & ATH9K_RX_FILTER_PHYRADAR)
3112 phybits |= AR_PHY_ERR_RADAR;
3113 if (bits & ATH9K_RX_FILTER_PHYERR)
3114 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3115 REG_WRITE(ah, AR_PHY_ERR, phybits);
3116
3117 if (phybits)
3118 REG_WRITE(ah, AR_RXCFG,
3119 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3120 else
3121 REG_WRITE(ah, AR_RXCFG,
3122 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3123 }
3124 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
3125
3126 bool ath9k_hw_phy_disable(struct ath_hw *ah)
3127 {
3128 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
3129 return false;
3130
3131 ath9k_hw_init_pll(ah, NULL);
3132 return true;
3133 }
3134 EXPORT_SYMBOL(ath9k_hw_phy_disable);
3135
3136 bool ath9k_hw_disable(struct ath_hw *ah)
3137 {
3138 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3139 return false;
3140
3141 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
3142 return false;
3143
3144 ath9k_hw_init_pll(ah, NULL);
3145 return true;
3146 }
3147 EXPORT_SYMBOL(ath9k_hw_disable);
3148
3149 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
3150 {
3151 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3152 struct ath9k_channel *chan = ah->curchan;
3153 struct ieee80211_channel *channel = chan->chan;
3154
3155 regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
3156
3157 ah->eep_ops->set_txpower(ah, chan,
3158 ath9k_regd_get_ctl(regulatory, chan),
3159 channel->max_antenna_gain * 2,
3160 channel->max_power * 2,
3161 min((u32) MAX_RATE_POWER,
3162 (u32) regulatory->power_limit));
3163 }
3164 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
3165
3166 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
3167 {
3168 memcpy(ath9k_hw_common(ah)->macaddr, mac, ETH_ALEN);
3169 }
3170 EXPORT_SYMBOL(ath9k_hw_setmac);
3171
3172 void ath9k_hw_setopmode(struct ath_hw *ah)
3173 {
3174 ath9k_hw_set_operating_mode(ah, ah->opmode);
3175 }
3176 EXPORT_SYMBOL(ath9k_hw_setopmode);
3177
3178 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
3179 {
3180 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3181 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
3182 }
3183 EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
3184
3185 void ath9k_hw_write_associd(struct ath_hw *ah)
3186 {
3187 struct ath_common *common = ath9k_hw_common(ah);
3188
3189 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
3190 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
3191 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
3192 }
3193 EXPORT_SYMBOL(ath9k_hw_write_associd);
3194
3195 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
3196 {
3197 u64 tsf;
3198
3199 tsf = REG_READ(ah, AR_TSF_U32);
3200 tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
3201
3202 return tsf;
3203 }
3204 EXPORT_SYMBOL(ath9k_hw_gettsf64);
3205
3206 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
3207 {
3208 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
3209 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
3210 }
3211 EXPORT_SYMBOL(ath9k_hw_settsf64);
3212
3213 void ath9k_hw_reset_tsf(struct ath_hw *ah)
3214 {
3215 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
3216 AH_TSF_WRITE_TIMEOUT))
3217 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
3218 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
3219
3220 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3221 }
3222 EXPORT_SYMBOL(ath9k_hw_reset_tsf);
3223
3224 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
3225 {
3226 if (setting)
3227 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
3228 else
3229 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
3230 }
3231 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
3232
3233 /*
3234 * Extend 15-bit time stamp from rx descriptor to
3235 * a full 64-bit TSF using the current h/w TSF.
3236 */
3237 u64 ath9k_hw_extend_tsf(struct ath_hw *ah, u32 rstamp)
3238 {
3239 u64 tsf;
3240
3241 tsf = ath9k_hw_gettsf64(ah);
3242 if ((tsf & 0x7fff) < rstamp)
3243 tsf -= 0x8000;
3244 return (tsf & ~0x7fff) | rstamp;
3245 }
3246 EXPORT_SYMBOL(ath9k_hw_extend_tsf);
3247
3248 void ath9k_hw_set11nmac2040(struct ath_hw *ah)
3249 {
3250 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
3251 u32 macmode;
3252
3253 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
3254 macmode = AR_2040_JOINED_RX_CLEAR;
3255 else
3256 macmode = 0;
3257
3258 REG_WRITE(ah, AR_2040_MODE, macmode);
3259 }
3260
3261 /* HW Generic timers configuration */
3262
3263 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
3264 {
3265 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3266 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3267 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3268 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3269 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3270 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3271 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3272 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3273 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
3274 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
3275 AR_NDP2_TIMER_MODE, 0x0002},
3276 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
3277 AR_NDP2_TIMER_MODE, 0x0004},
3278 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
3279 AR_NDP2_TIMER_MODE, 0x0008},
3280 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
3281 AR_NDP2_TIMER_MODE, 0x0010},
3282 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
3283 AR_NDP2_TIMER_MODE, 0x0020},
3284 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
3285 AR_NDP2_TIMER_MODE, 0x0040},
3286 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
3287 AR_NDP2_TIMER_MODE, 0x0080}
3288 };
3289
3290 /* HW generic timer primitives */
3291
3292 /* compute and clear index of rightmost 1 */
3293 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
3294 {
3295 u32 b;
3296
3297 b = *mask;
3298 b &= (0-b);
3299 *mask &= ~b;
3300 b *= debruijn32;
3301 b >>= 27;
3302
3303 return timer_table->gen_timer_index[b];
3304 }
3305
3306 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
3307 {
3308 return REG_READ(ah, AR_TSF_L32);
3309 }
3310 EXPORT_SYMBOL(ath9k_hw_gettsf32);
3311
3312 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
3313 void (*trigger)(void *),
3314 void (*overflow)(void *),
3315 void *arg,
3316 u8 timer_index)
3317 {
3318 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3319 struct ath_gen_timer *timer;
3320
3321 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
3322
3323 if (timer == NULL) {
3324 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
3325 "Failed to allocate memory"
3326 "for hw timer[%d]\n", timer_index);
3327 return NULL;
3328 }
3329
3330 /* allocate a hardware generic timer slot */
3331 timer_table->timers[timer_index] = timer;
3332 timer->index = timer_index;
3333 timer->trigger = trigger;
3334 timer->overflow = overflow;
3335 timer->arg = arg;
3336
3337 return timer;
3338 }
3339 EXPORT_SYMBOL(ath_gen_timer_alloc);
3340
3341 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
3342 struct ath_gen_timer *timer,
3343 u32 timer_next,
3344 u32 timer_period)
3345 {
3346 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3347 u32 tsf;
3348
3349 BUG_ON(!timer_period);
3350
3351 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
3352
3353 tsf = ath9k_hw_gettsf32(ah);
3354
3355 ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
3356 "curent tsf %x period %x"
3357 "timer_next %x\n", tsf, timer_period, timer_next);
3358
3359 /*
3360 * Pull timer_next forward if the current TSF already passed it
3361 * because of software latency
3362 */
3363 if (timer_next < tsf)
3364 timer_next = tsf + timer_period;
3365
3366 /*
3367 * Program generic timer registers
3368 */
3369 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
3370 timer_next);
3371 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
3372 timer_period);
3373 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3374 gen_tmr_configuration[timer->index].mode_mask);
3375
3376 /* Enable both trigger and thresh interrupt masks */
3377 REG_SET_BIT(ah, AR_IMR_S5,
3378 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3379 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3380 }
3381 EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
3382
3383 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
3384 {
3385 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3386
3387 if ((timer->index < AR_FIRST_NDP_TIMER) ||
3388 (timer->index >= ATH_MAX_GEN_TIMER)) {
3389 return;
3390 }
3391
3392 /* Clear generic timer enable bits. */
3393 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3394 gen_tmr_configuration[timer->index].mode_mask);
3395
3396 /* Disable both trigger and thresh interrupt masks */
3397 REG_CLR_BIT(ah, AR_IMR_S5,
3398 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3399 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3400
3401 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
3402 }
3403 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
3404
3405 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
3406 {
3407 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3408
3409 /* free the hardware generic timer slot */
3410 timer_table->timers[timer->index] = NULL;
3411 kfree(timer);
3412 }
3413 EXPORT_SYMBOL(ath_gen_timer_free);
3414
3415 /*
3416 * Generic Timer Interrupts handling
3417 */
3418 void ath_gen_timer_isr(struct ath_hw *ah)
3419 {
3420 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3421 struct ath_gen_timer *timer;
3422 struct ath_common *common = ath9k_hw_common(ah);
3423 u32 trigger_mask, thresh_mask, index;
3424
3425 /* get hardware generic timer interrupt status */
3426 trigger_mask = ah->intr_gen_timer_trigger;
3427 thresh_mask = ah->intr_gen_timer_thresh;
3428 trigger_mask &= timer_table->timer_mask.val;
3429 thresh_mask &= timer_table->timer_mask.val;
3430
3431 trigger_mask &= ~thresh_mask;
3432
3433 while (thresh_mask) {
3434 index = rightmost_index(timer_table, &thresh_mask);
3435 timer = timer_table->timers[index];
3436 BUG_ON(!timer);
3437 ath_print(common, ATH_DBG_HWTIMER,
3438 "TSF overflow for Gen timer %d\n", index);
3439 timer->overflow(timer->arg);
3440 }
3441
3442 while (trigger_mask) {
3443 index = rightmost_index(timer_table, &trigger_mask);
3444 timer = timer_table->timers[index];
3445 BUG_ON(!timer);
3446 ath_print(common, ATH_DBG_HWTIMER,
3447 "Gen timer[%d] trigger\n", index);
3448 timer->trigger(timer->arg);
3449 }
3450 }
3451 EXPORT_SYMBOL(ath_gen_timer_isr);
3452
3453 /********/
3454 /* HTC */
3455 /********/
3456
3457 void ath9k_hw_htc_resetinit(struct ath_hw *ah)
3458 {
3459 ah->htc_reset_init = true;
3460 }
3461 EXPORT_SYMBOL(ath9k_hw_htc_resetinit);
3462
3463 static struct {
3464 u32 version;
3465 const char * name;
3466 } ath_mac_bb_names[] = {
3467 /* Devices with external radios */
3468 { AR_SREV_VERSION_5416_PCI, "5416" },
3469 { AR_SREV_VERSION_5416_PCIE, "5418" },
3470 { AR_SREV_VERSION_9100, "9100" },
3471 { AR_SREV_VERSION_9160, "9160" },
3472 /* Single-chip solutions */
3473 { AR_SREV_VERSION_9280, "9280" },
3474 { AR_SREV_VERSION_9285, "9285" },
3475 { AR_SREV_VERSION_9287, "9287" },
3476 { AR_SREV_VERSION_9271, "9271" },
3477 };
3478
3479 /* For devices with external radios */
3480 static struct {
3481 u16 version;
3482 const char * name;
3483 } ath_rf_names[] = {
3484 { 0, "5133" },
3485 { AR_RAD5133_SREV_MAJOR, "5133" },
3486 { AR_RAD5122_SREV_MAJOR, "5122" },
3487 { AR_RAD2133_SREV_MAJOR, "2133" },
3488 { AR_RAD2122_SREV_MAJOR, "2122" }
3489 };
3490
3491 /*
3492 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3493 */
3494 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
3495 {
3496 int i;
3497
3498 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3499 if (ath_mac_bb_names[i].version == mac_bb_version) {
3500 return ath_mac_bb_names[i].name;
3501 }
3502 }
3503
3504 return "????";
3505 }
3506
3507 /*
3508 * Return the RF name. "????" is returned if the RF is unknown.
3509 * Used for devices with external radios.
3510 */
3511 static const char *ath9k_hw_rf_name(u16 rf_version)
3512 {
3513 int i;
3514
3515 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3516 if (ath_rf_names[i].version == rf_version) {
3517 return ath_rf_names[i].name;
3518 }
3519 }
3520
3521 return "????";
3522 }
3523
3524 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
3525 {
3526 int used;
3527
3528 /* chipsets >= AR9280 are single-chip */
3529 if (AR_SREV_9280_10_OR_LATER(ah)) {
3530 used = snprintf(hw_name, len,
3531 "Atheros AR%s Rev:%x",
3532 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3533 ah->hw_version.macRev);
3534 }
3535 else {
3536 used = snprintf(hw_name, len,
3537 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3538 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3539 ah->hw_version.macRev,
3540 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
3541 AR_RADIO_SREV_MAJOR)),
3542 ah->hw_version.phyRev);
3543 }
3544
3545 hw_name[used] = '\0';
3546 }
3547 EXPORT_SYMBOL(ath9k_hw_name);
3548
3549 /* Sets up the AR5008/AR9001/AR9002 hardware familiy callbacks */
3550 static void ar9002_hw_attach_ops(struct ath_hw *ah)
3551 {
3552 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
3553 struct ath_hw_ops *ops = ath9k_hw_ops(ah);
3554
3555 priv_ops->init_cal_settings = ar9002_hw_init_cal_settings;
3556 priv_ops->init_mode_regs = ar9002_hw_init_mode_regs;
3557 priv_ops->macversion_supported = ar9002_hw_macversion_supported;
3558
3559 ops->config_pci_powersave = ar9002_hw_configpcipowersave;
3560
3561 ar5008_hw_attach_phy_ops(ah);
3562 if (AR_SREV_9280_10_OR_LATER(ah))
3563 ar9002_hw_attach_phy_ops(ah);
3564
3565 ar9002_hw_attach_mac_ops(ah);
3566 }
3567
3568 /* Sets up the AR9003 hardware familiy callbacks */
3569 static void ar9003_hw_attach_ops(struct ath_hw *ah)
3570 {
3571 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
3572
3573 priv_ops->macversion_supported = ar9003_hw_macversion_supported;
3574
3575 ar9003_hw_attach_phy_ops(ah);
3576
3577 ar9003_hw_attach_mac_ops(ah);
3578 }
Linux kernel - Deliverables
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