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Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc-next-2.6
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / hw.c
1 /*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/io.h>
18 #include <asm/unaligned.h>
19
20 #include "hw.h"
21 #include "rc.h"
22 #include "initvals.h"
23
24 #define ATH9K_CLOCK_RATE_CCK 22
25 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
26 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
27
28 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
29 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan);
30 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
31 struct ar5416_eeprom_def *pEepData,
32 u32 reg, u32 value);
33
34 MODULE_AUTHOR("Atheros Communications");
35 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
36 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
37 MODULE_LICENSE("Dual BSD/GPL");
38
39 static int __init ath9k_init(void)
40 {
41 return 0;
42 }
43 module_init(ath9k_init);
44
45 static void __exit ath9k_exit(void)
46 {
47 return;
48 }
49 module_exit(ath9k_exit);
50
51 /********************/
52 /* Helper Functions */
53 /********************/
54
55 static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
56 {
57 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
58
59 if (!ah->curchan) /* should really check for CCK instead */
60 return usecs *ATH9K_CLOCK_RATE_CCK;
61 if (conf->channel->band == IEEE80211_BAND_2GHZ)
62 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
63 return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
64 }
65
66 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
67 {
68 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
69
70 if (conf_is_ht40(conf))
71 return ath9k_hw_mac_clks(ah, usecs) * 2;
72 else
73 return ath9k_hw_mac_clks(ah, usecs);
74 }
75
76 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
77 {
78 int i;
79
80 BUG_ON(timeout < AH_TIME_QUANTUM);
81
82 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
83 if ((REG_READ(ah, reg) & mask) == val)
84 return true;
85
86 udelay(AH_TIME_QUANTUM);
87 }
88
89 ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
90 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
91 timeout, reg, REG_READ(ah, reg), mask, val);
92
93 return false;
94 }
95 EXPORT_SYMBOL(ath9k_hw_wait);
96
97 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
98 {
99 u32 retval;
100 int i;
101
102 for (i = 0, retval = 0; i < n; i++) {
103 retval = (retval << 1) | (val & 1);
104 val >>= 1;
105 }
106 return retval;
107 }
108
109 bool ath9k_get_channel_edges(struct ath_hw *ah,
110 u16 flags, u16 *low,
111 u16 *high)
112 {
113 struct ath9k_hw_capabilities *pCap = &ah->caps;
114
115 if (flags & CHANNEL_5GHZ) {
116 *low = pCap->low_5ghz_chan;
117 *high = pCap->high_5ghz_chan;
118 return true;
119 }
120 if ((flags & CHANNEL_2GHZ)) {
121 *low = pCap->low_2ghz_chan;
122 *high = pCap->high_2ghz_chan;
123 return true;
124 }
125 return false;
126 }
127
128 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
129 u8 phy, int kbps,
130 u32 frameLen, u16 rateix,
131 bool shortPreamble)
132 {
133 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
134
135 if (kbps == 0)
136 return 0;
137
138 switch (phy) {
139 case WLAN_RC_PHY_CCK:
140 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
141 if (shortPreamble)
142 phyTime >>= 1;
143 numBits = frameLen << 3;
144 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
145 break;
146 case WLAN_RC_PHY_OFDM:
147 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
148 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
149 numBits = OFDM_PLCP_BITS + (frameLen << 3);
150 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
151 txTime = OFDM_SIFS_TIME_QUARTER
152 + OFDM_PREAMBLE_TIME_QUARTER
153 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
154 } else if (ah->curchan &&
155 IS_CHAN_HALF_RATE(ah->curchan)) {
156 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
157 numBits = OFDM_PLCP_BITS + (frameLen << 3);
158 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
159 txTime = OFDM_SIFS_TIME_HALF +
160 OFDM_PREAMBLE_TIME_HALF
161 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
162 } else {
163 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
164 numBits = OFDM_PLCP_BITS + (frameLen << 3);
165 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
166 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
167 + (numSymbols * OFDM_SYMBOL_TIME);
168 }
169 break;
170 default:
171 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
172 "Unknown phy %u (rate ix %u)\n", phy, rateix);
173 txTime = 0;
174 break;
175 }
176
177 return txTime;
178 }
179 EXPORT_SYMBOL(ath9k_hw_computetxtime);
180
181 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
182 struct ath9k_channel *chan,
183 struct chan_centers *centers)
184 {
185 int8_t extoff;
186
187 if (!IS_CHAN_HT40(chan)) {
188 centers->ctl_center = centers->ext_center =
189 centers->synth_center = chan->channel;
190 return;
191 }
192
193 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
194 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
195 centers->synth_center =
196 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
197 extoff = 1;
198 } else {
199 centers->synth_center =
200 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
201 extoff = -1;
202 }
203
204 centers->ctl_center =
205 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
206 /* 25 MHz spacing is supported by hw but not on upper layers */
207 centers->ext_center =
208 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
209 }
210
211 /******************/
212 /* Chip Revisions */
213 /******************/
214
215 static void ath9k_hw_read_revisions(struct ath_hw *ah)
216 {
217 u32 val;
218
219 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
220
221 if (val == 0xFF) {
222 val = REG_READ(ah, AR_SREV);
223 ah->hw_version.macVersion =
224 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
225 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
226 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
227 } else {
228 if (!AR_SREV_9100(ah))
229 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
230
231 ah->hw_version.macRev = val & AR_SREV_REVISION;
232
233 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
234 ah->is_pciexpress = true;
235 }
236 }
237
238 static int ath9k_hw_get_radiorev(struct ath_hw *ah)
239 {
240 u32 val;
241 int i;
242
243 REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
244
245 for (i = 0; i < 8; i++)
246 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
247 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
248 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
249
250 return ath9k_hw_reverse_bits(val, 8);
251 }
252
253 /************************************/
254 /* HW Attach, Detach, Init Routines */
255 /************************************/
256
257 static void ath9k_hw_disablepcie(struct ath_hw *ah)
258 {
259 if (AR_SREV_9100(ah))
260 return;
261
262 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
263 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
264 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
265 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
266 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
267 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
268 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
269 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
270 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
271
272 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
273 }
274
275 static bool ath9k_hw_chip_test(struct ath_hw *ah)
276 {
277 struct ath_common *common = ath9k_hw_common(ah);
278 u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
279 u32 regHold[2];
280 u32 patternData[4] = { 0x55555555,
281 0xaaaaaaaa,
282 0x66666666,
283 0x99999999 };
284 int i, j;
285
286 for (i = 0; i < 2; i++) {
287 u32 addr = regAddr[i];
288 u32 wrData, rdData;
289
290 regHold[i] = REG_READ(ah, addr);
291 for (j = 0; j < 0x100; j++) {
292 wrData = (j << 16) | j;
293 REG_WRITE(ah, addr, wrData);
294 rdData = REG_READ(ah, addr);
295 if (rdData != wrData) {
296 ath_print(common, ATH_DBG_FATAL,
297 "address test failed "
298 "addr: 0x%08x - wr:0x%08x != "
299 "rd:0x%08x\n",
300 addr, wrData, rdData);
301 return false;
302 }
303 }
304 for (j = 0; j < 4; j++) {
305 wrData = patternData[j];
306 REG_WRITE(ah, addr, wrData);
307 rdData = REG_READ(ah, addr);
308 if (wrData != rdData) {
309 ath_print(common, ATH_DBG_FATAL,
310 "address test failed "
311 "addr: 0x%08x - wr:0x%08x != "
312 "rd:0x%08x\n",
313 addr, wrData, rdData);
314 return false;
315 }
316 }
317 REG_WRITE(ah, regAddr[i], regHold[i]);
318 }
319 udelay(100);
320
321 return true;
322 }
323
324 static void ath9k_hw_init_config(struct ath_hw *ah)
325 {
326 int i;
327
328 ah->config.dma_beacon_response_time = 2;
329 ah->config.sw_beacon_response_time = 10;
330 ah->config.additional_swba_backoff = 0;
331 ah->config.ack_6mb = 0x0;
332 ah->config.cwm_ignore_extcca = 0;
333 ah->config.pcie_powersave_enable = 0;
334 ah->config.pcie_clock_req = 0;
335 ah->config.pcie_waen = 0;
336 ah->config.analog_shiftreg = 1;
337 ah->config.ofdm_trig_low = 200;
338 ah->config.ofdm_trig_high = 500;
339 ah->config.cck_trig_high = 200;
340 ah->config.cck_trig_low = 100;
341 ah->config.enable_ani = 1;
342
343 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
344 ah->config.spurchans[i][0] = AR_NO_SPUR;
345 ah->config.spurchans[i][1] = AR_NO_SPUR;
346 }
347
348 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
349 ah->config.ht_enable = 1;
350 else
351 ah->config.ht_enable = 0;
352
353 ah->config.rx_intr_mitigation = true;
354
355 /*
356 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
357 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
358 * This means we use it for all AR5416 devices, and the few
359 * minor PCI AR9280 devices out there.
360 *
361 * Serialization is required because these devices do not handle
362 * well the case of two concurrent reads/writes due to the latency
363 * involved. During one read/write another read/write can be issued
364 * on another CPU while the previous read/write may still be working
365 * on our hardware, if we hit this case the hardware poops in a loop.
366 * We prevent this by serializing reads and writes.
367 *
368 * This issue is not present on PCI-Express devices or pre-AR5416
369 * devices (legacy, 802.11abg).
370 */
371 if (num_possible_cpus() > 1)
372 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
373 }
374 EXPORT_SYMBOL(ath9k_hw_init);
375
376 static void ath9k_hw_init_defaults(struct ath_hw *ah)
377 {
378 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
379
380 regulatory->country_code = CTRY_DEFAULT;
381 regulatory->power_limit = MAX_RATE_POWER;
382 regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
383
384 ah->hw_version.magic = AR5416_MAGIC;
385 ah->hw_version.subvendorid = 0;
386
387 ah->ah_flags = 0;
388 if (ah->hw_version.devid == AR5416_AR9100_DEVID)
389 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
390 if (!AR_SREV_9100(ah))
391 ah->ah_flags = AH_USE_EEPROM;
392
393 ah->atim_window = 0;
394 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
395 ah->beacon_interval = 100;
396 ah->enable_32kHz_clock = DONT_USE_32KHZ;
397 ah->slottime = (u32) -1;
398 ah->globaltxtimeout = (u32) -1;
399 ah->power_mode = ATH9K_PM_UNDEFINED;
400 }
401
402 static int ath9k_hw_rf_claim(struct ath_hw *ah)
403 {
404 u32 val;
405
406 REG_WRITE(ah, AR_PHY(0), 0x00000007);
407
408 val = ath9k_hw_get_radiorev(ah);
409 switch (val & AR_RADIO_SREV_MAJOR) {
410 case 0:
411 val = AR_RAD5133_SREV_MAJOR;
412 break;
413 case AR_RAD5133_SREV_MAJOR:
414 case AR_RAD5122_SREV_MAJOR:
415 case AR_RAD2133_SREV_MAJOR:
416 case AR_RAD2122_SREV_MAJOR:
417 break;
418 default:
419 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
420 "Radio Chip Rev 0x%02X not supported\n",
421 val & AR_RADIO_SREV_MAJOR);
422 return -EOPNOTSUPP;
423 }
424
425 ah->hw_version.analog5GhzRev = val;
426
427 return 0;
428 }
429
430 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
431 {
432 struct ath_common *common = ath9k_hw_common(ah);
433 u32 sum;
434 int i;
435 u16 eeval;
436
437 sum = 0;
438 for (i = 0; i < 3; i++) {
439 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
440 sum += eeval;
441 common->macaddr[2 * i] = eeval >> 8;
442 common->macaddr[2 * i + 1] = eeval & 0xff;
443 }
444 if (sum == 0 || sum == 0xffff * 3)
445 return -EADDRNOTAVAIL;
446
447 return 0;
448 }
449
450 static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
451 {
452 u32 rxgain_type;
453
454 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
455 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
456
457 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
458 INIT_INI_ARRAY(&ah->iniModesRxGain,
459 ar9280Modes_backoff_13db_rxgain_9280_2,
460 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
461 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
462 INIT_INI_ARRAY(&ah->iniModesRxGain,
463 ar9280Modes_backoff_23db_rxgain_9280_2,
464 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
465 else
466 INIT_INI_ARRAY(&ah->iniModesRxGain,
467 ar9280Modes_original_rxgain_9280_2,
468 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
469 } else {
470 INIT_INI_ARRAY(&ah->iniModesRxGain,
471 ar9280Modes_original_rxgain_9280_2,
472 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
473 }
474 }
475
476 static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
477 {
478 u32 txgain_type;
479
480 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
481 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
482
483 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
484 INIT_INI_ARRAY(&ah->iniModesTxGain,
485 ar9280Modes_high_power_tx_gain_9280_2,
486 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
487 else
488 INIT_INI_ARRAY(&ah->iniModesTxGain,
489 ar9280Modes_original_tx_gain_9280_2,
490 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
491 } else {
492 INIT_INI_ARRAY(&ah->iniModesTxGain,
493 ar9280Modes_original_tx_gain_9280_2,
494 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
495 }
496 }
497
498 static int ath9k_hw_post_init(struct ath_hw *ah)
499 {
500 int ecode;
501
502 if (!ath9k_hw_chip_test(ah))
503 return -ENODEV;
504
505 ecode = ath9k_hw_rf_claim(ah);
506 if (ecode != 0)
507 return ecode;
508
509 ecode = ath9k_hw_eeprom_init(ah);
510 if (ecode != 0)
511 return ecode;
512
513 ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
514 "Eeprom VER: %d, REV: %d\n",
515 ah->eep_ops->get_eeprom_ver(ah),
516 ah->eep_ops->get_eeprom_rev(ah));
517
518 if (!AR_SREV_9280_10_OR_LATER(ah)) {
519 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
520 if (ecode) {
521 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
522 "Failed allocating banks for "
523 "external radio\n");
524 return ecode;
525 }
526 }
527
528 if (!AR_SREV_9100(ah)) {
529 ath9k_hw_ani_setup(ah);
530 ath9k_hw_ani_init(ah);
531 }
532
533 return 0;
534 }
535
536 static bool ath9k_hw_devid_supported(u16 devid)
537 {
538 switch (devid) {
539 case AR5416_DEVID_PCI:
540 case AR5416_DEVID_PCIE:
541 case AR5416_AR9100_DEVID:
542 case AR9160_DEVID_PCI:
543 case AR9280_DEVID_PCI:
544 case AR9280_DEVID_PCIE:
545 case AR9285_DEVID_PCIE:
546 case AR5416_DEVID_AR9287_PCI:
547 case AR5416_DEVID_AR9287_PCIE:
548 case AR9271_USB:
549 case AR2427_DEVID_PCIE:
550 return true;
551 default:
552 break;
553 }
554 return false;
555 }
556
557 static bool ath9k_hw_macversion_supported(u32 macversion)
558 {
559 switch (macversion) {
560 case AR_SREV_VERSION_5416_PCI:
561 case AR_SREV_VERSION_5416_PCIE:
562 case AR_SREV_VERSION_9160:
563 case AR_SREV_VERSION_9100:
564 case AR_SREV_VERSION_9280:
565 case AR_SREV_VERSION_9285:
566 case AR_SREV_VERSION_9287:
567 case AR_SREV_VERSION_9271:
568 return true;
569 default:
570 break;
571 }
572 return false;
573 }
574
575 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
576 {
577 if (AR_SREV_9160_10_OR_LATER(ah)) {
578 if (AR_SREV_9280_10_OR_LATER(ah)) {
579 ah->iq_caldata.calData = &iq_cal_single_sample;
580 ah->adcgain_caldata.calData =
581 &adc_gain_cal_single_sample;
582 ah->adcdc_caldata.calData =
583 &adc_dc_cal_single_sample;
584 ah->adcdc_calinitdata.calData =
585 &adc_init_dc_cal;
586 } else {
587 ah->iq_caldata.calData = &iq_cal_multi_sample;
588 ah->adcgain_caldata.calData =
589 &adc_gain_cal_multi_sample;
590 ah->adcdc_caldata.calData =
591 &adc_dc_cal_multi_sample;
592 ah->adcdc_calinitdata.calData =
593 &adc_init_dc_cal;
594 }
595 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
596 }
597 }
598
599 static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
600 {
601 if (AR_SREV_9271(ah)) {
602 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271,
603 ARRAY_SIZE(ar9271Modes_9271), 6);
604 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271,
605 ARRAY_SIZE(ar9271Common_9271), 2);
606 INIT_INI_ARRAY(&ah->iniModes_9271_1_0_only,
607 ar9271Modes_9271_1_0_only,
608 ARRAY_SIZE(ar9271Modes_9271_1_0_only), 6);
609 return;
610 }
611
612 if (AR_SREV_9287_11_OR_LATER(ah)) {
613 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
614 ARRAY_SIZE(ar9287Modes_9287_1_1), 6);
615 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
616 ARRAY_SIZE(ar9287Common_9287_1_1), 2);
617 if (ah->config.pcie_clock_req)
618 INIT_INI_ARRAY(&ah->iniPcieSerdes,
619 ar9287PciePhy_clkreq_off_L1_9287_1_1,
620 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2);
621 else
622 INIT_INI_ARRAY(&ah->iniPcieSerdes,
623 ar9287PciePhy_clkreq_always_on_L1_9287_1_1,
624 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1),
625 2);
626 } else if (AR_SREV_9287_10_OR_LATER(ah)) {
627 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0,
628 ARRAY_SIZE(ar9287Modes_9287_1_0), 6);
629 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0,
630 ARRAY_SIZE(ar9287Common_9287_1_0), 2);
631
632 if (ah->config.pcie_clock_req)
633 INIT_INI_ARRAY(&ah->iniPcieSerdes,
634 ar9287PciePhy_clkreq_off_L1_9287_1_0,
635 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2);
636 else
637 INIT_INI_ARRAY(&ah->iniPcieSerdes,
638 ar9287PciePhy_clkreq_always_on_L1_9287_1_0,
639 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0),
640 2);
641 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
642
643
644 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
645 ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
646 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
647 ARRAY_SIZE(ar9285Common_9285_1_2), 2);
648
649 if (ah->config.pcie_clock_req) {
650 INIT_INI_ARRAY(&ah->iniPcieSerdes,
651 ar9285PciePhy_clkreq_off_L1_9285_1_2,
652 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
653 } else {
654 INIT_INI_ARRAY(&ah->iniPcieSerdes,
655 ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
656 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
657 2);
658 }
659 } else if (AR_SREV_9285_10_OR_LATER(ah)) {
660 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
661 ARRAY_SIZE(ar9285Modes_9285), 6);
662 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
663 ARRAY_SIZE(ar9285Common_9285), 2);
664
665 if (ah->config.pcie_clock_req) {
666 INIT_INI_ARRAY(&ah->iniPcieSerdes,
667 ar9285PciePhy_clkreq_off_L1_9285,
668 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
669 } else {
670 INIT_INI_ARRAY(&ah->iniPcieSerdes,
671 ar9285PciePhy_clkreq_always_on_L1_9285,
672 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
673 }
674 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
675 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
676 ARRAY_SIZE(ar9280Modes_9280_2), 6);
677 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
678 ARRAY_SIZE(ar9280Common_9280_2), 2);
679
680 if (ah->config.pcie_clock_req) {
681 INIT_INI_ARRAY(&ah->iniPcieSerdes,
682 ar9280PciePhy_clkreq_off_L1_9280,
683 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
684 } else {
685 INIT_INI_ARRAY(&ah->iniPcieSerdes,
686 ar9280PciePhy_clkreq_always_on_L1_9280,
687 ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
688 }
689 INIT_INI_ARRAY(&ah->iniModesAdditional,
690 ar9280Modes_fast_clock_9280_2,
691 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
692 } else if (AR_SREV_9280_10_OR_LATER(ah)) {
693 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
694 ARRAY_SIZE(ar9280Modes_9280), 6);
695 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
696 ARRAY_SIZE(ar9280Common_9280), 2);
697 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
698 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
699 ARRAY_SIZE(ar5416Modes_9160), 6);
700 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
701 ARRAY_SIZE(ar5416Common_9160), 2);
702 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
703 ARRAY_SIZE(ar5416Bank0_9160), 2);
704 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
705 ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
706 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
707 ARRAY_SIZE(ar5416Bank1_9160), 2);
708 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
709 ARRAY_SIZE(ar5416Bank2_9160), 2);
710 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
711 ARRAY_SIZE(ar5416Bank3_9160), 3);
712 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
713 ARRAY_SIZE(ar5416Bank6_9160), 3);
714 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
715 ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
716 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
717 ARRAY_SIZE(ar5416Bank7_9160), 2);
718 if (AR_SREV_9160_11(ah)) {
719 INIT_INI_ARRAY(&ah->iniAddac,
720 ar5416Addac_91601_1,
721 ARRAY_SIZE(ar5416Addac_91601_1), 2);
722 } else {
723 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
724 ARRAY_SIZE(ar5416Addac_9160), 2);
725 }
726 } else if (AR_SREV_9100_OR_LATER(ah)) {
727 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
728 ARRAY_SIZE(ar5416Modes_9100), 6);
729 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
730 ARRAY_SIZE(ar5416Common_9100), 2);
731 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
732 ARRAY_SIZE(ar5416Bank0_9100), 2);
733 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
734 ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
735 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
736 ARRAY_SIZE(ar5416Bank1_9100), 2);
737 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
738 ARRAY_SIZE(ar5416Bank2_9100), 2);
739 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
740 ARRAY_SIZE(ar5416Bank3_9100), 3);
741 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
742 ARRAY_SIZE(ar5416Bank6_9100), 3);
743 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
744 ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
745 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
746 ARRAY_SIZE(ar5416Bank7_9100), 2);
747 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
748 ARRAY_SIZE(ar5416Addac_9100), 2);
749 } else {
750 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
751 ARRAY_SIZE(ar5416Modes), 6);
752 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
753 ARRAY_SIZE(ar5416Common), 2);
754 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
755 ARRAY_SIZE(ar5416Bank0), 2);
756 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
757 ARRAY_SIZE(ar5416BB_RfGain), 3);
758 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
759 ARRAY_SIZE(ar5416Bank1), 2);
760 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
761 ARRAY_SIZE(ar5416Bank2), 2);
762 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
763 ARRAY_SIZE(ar5416Bank3), 3);
764 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
765 ARRAY_SIZE(ar5416Bank6), 3);
766 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
767 ARRAY_SIZE(ar5416Bank6TPC), 3);
768 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
769 ARRAY_SIZE(ar5416Bank7), 2);
770 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
771 ARRAY_SIZE(ar5416Addac), 2);
772 }
773 }
774
775 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
776 {
777 if (AR_SREV_9287_11_OR_LATER(ah))
778 INIT_INI_ARRAY(&ah->iniModesRxGain,
779 ar9287Modes_rx_gain_9287_1_1,
780 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
781 else if (AR_SREV_9287_10(ah))
782 INIT_INI_ARRAY(&ah->iniModesRxGain,
783 ar9287Modes_rx_gain_9287_1_0,
784 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6);
785 else if (AR_SREV_9280_20(ah))
786 ath9k_hw_init_rxgain_ini(ah);
787
788 if (AR_SREV_9287_11_OR_LATER(ah)) {
789 INIT_INI_ARRAY(&ah->iniModesTxGain,
790 ar9287Modes_tx_gain_9287_1_1,
791 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
792 } else if (AR_SREV_9287_10(ah)) {
793 INIT_INI_ARRAY(&ah->iniModesTxGain,
794 ar9287Modes_tx_gain_9287_1_0,
795 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6);
796 } else if (AR_SREV_9280_20(ah)) {
797 ath9k_hw_init_txgain_ini(ah);
798 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
799 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
800
801 /* txgain table */
802 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
803 INIT_INI_ARRAY(&ah->iniModesTxGain,
804 ar9285Modes_high_power_tx_gain_9285_1_2,
805 ARRAY_SIZE(ar9285Modes_high_power_tx_gain_9285_1_2), 6);
806 } else {
807 INIT_INI_ARRAY(&ah->iniModesTxGain,
808 ar9285Modes_original_tx_gain_9285_1_2,
809 ARRAY_SIZE(ar9285Modes_original_tx_gain_9285_1_2), 6);
810 }
811
812 }
813 }
814
815 static void ath9k_hw_init_eeprom_fix(struct ath_hw *ah)
816 {
817 u32 i, j;
818
819 if (ah->hw_version.devid == AR9280_DEVID_PCI) {
820
821 /* EEPROM Fixup */
822 for (i = 0; i < ah->iniModes.ia_rows; i++) {
823 u32 reg = INI_RA(&ah->iniModes, i, 0);
824
825 for (j = 1; j < ah->iniModes.ia_columns; j++) {
826 u32 val = INI_RA(&ah->iniModes, i, j);
827
828 INI_RA(&ah->iniModes, i, j) =
829 ath9k_hw_ini_fixup(ah,
830 &ah->eeprom.def,
831 reg, val);
832 }
833 }
834 }
835 }
836
837 int ath9k_hw_init(struct ath_hw *ah)
838 {
839 struct ath_common *common = ath9k_hw_common(ah);
840 int r = 0;
841
842 if (!ath9k_hw_devid_supported(ah->hw_version.devid)) {
843 ath_print(common, ATH_DBG_FATAL,
844 "Unsupported device ID: 0x%0x\n",
845 ah->hw_version.devid);
846 return -EOPNOTSUPP;
847 }
848
849 ath9k_hw_init_defaults(ah);
850 ath9k_hw_init_config(ah);
851
852 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
853 ath_print(common, ATH_DBG_FATAL,
854 "Couldn't reset chip\n");
855 return -EIO;
856 }
857
858 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
859 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
860 return -EIO;
861 }
862
863 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
864 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
865 (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
866 ah->config.serialize_regmode =
867 SER_REG_MODE_ON;
868 } else {
869 ah->config.serialize_regmode =
870 SER_REG_MODE_OFF;
871 }
872 }
873
874 ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
875 ah->config.serialize_regmode);
876
877 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
878 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
879 else
880 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
881
882 if (!ath9k_hw_macversion_supported(ah->hw_version.macVersion)) {
883 ath_print(common, ATH_DBG_FATAL,
884 "Mac Chip Rev 0x%02x.%x is not supported by "
885 "this driver\n", ah->hw_version.macVersion,
886 ah->hw_version.macRev);
887 return -EOPNOTSUPP;
888 }
889
890 if (AR_SREV_9100(ah)) {
891 ah->iq_caldata.calData = &iq_cal_multi_sample;
892 ah->supp_cals = IQ_MISMATCH_CAL;
893 ah->is_pciexpress = false;
894 }
895
896 if (AR_SREV_9271(ah))
897 ah->is_pciexpress = false;
898
899 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
900
901 ath9k_hw_init_cal_settings(ah);
902
903 ah->ani_function = ATH9K_ANI_ALL;
904 if (AR_SREV_9280_10_OR_LATER(ah)) {
905 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
906 ah->ath9k_hw_rf_set_freq = &ath9k_hw_ar9280_set_channel;
907 ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_9280_spur_mitigate;
908 } else {
909 ah->ath9k_hw_rf_set_freq = &ath9k_hw_set_channel;
910 ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_spur_mitigate;
911 }
912
913 ath9k_hw_init_mode_regs(ah);
914
915 if (ah->is_pciexpress)
916 ath9k_hw_configpcipowersave(ah, 0, 0);
917 else
918 ath9k_hw_disablepcie(ah);
919
920 /* Support for Japan ch.14 (2484) spread */
921 if (AR_SREV_9287_11_OR_LATER(ah)) {
922 INIT_INI_ARRAY(&ah->iniCckfirNormal,
923 ar9287Common_normal_cck_fir_coeff_92871_1,
924 ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_92871_1), 2);
925 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
926 ar9287Common_japan_2484_cck_fir_coeff_92871_1,
927 ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_92871_1), 2);
928 }
929
930 r = ath9k_hw_post_init(ah);
931 if (r)
932 return r;
933
934 ath9k_hw_init_mode_gain_regs(ah);
935 r = ath9k_hw_fill_cap_info(ah);
936 if (r)
937 return r;
938
939 ath9k_hw_init_eeprom_fix(ah);
940
941 r = ath9k_hw_init_macaddr(ah);
942 if (r) {
943 ath_print(common, ATH_DBG_FATAL,
944 "Failed to initialize MAC address\n");
945 return r;
946 }
947
948 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
949 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
950 else
951 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
952
953 ath9k_init_nfcal_hist_buffer(ah);
954
955 common->state = ATH_HW_INITIALIZED;
956
957 return 0;
958 }
959
960 static void ath9k_hw_init_bb(struct ath_hw *ah,
961 struct ath9k_channel *chan)
962 {
963 u32 synthDelay;
964
965 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
966 if (IS_CHAN_B(chan))
967 synthDelay = (4 * synthDelay) / 22;
968 else
969 synthDelay /= 10;
970
971 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
972
973 udelay(synthDelay + BASE_ACTIVATE_DELAY);
974 }
975
976 static void ath9k_hw_init_qos(struct ath_hw *ah)
977 {
978 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
979 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
980
981 REG_WRITE(ah, AR_QOS_NO_ACK,
982 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
983 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
984 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
985
986 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
987 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
988 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
989 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
990 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
991 }
992
993 static void ath9k_hw_change_target_baud(struct ath_hw *ah, u32 freq, u32 baud)
994 {
995 u32 lcr;
996 u32 baud_divider = freq * 1000 * 1000 / 16 / baud;
997
998 lcr = REG_READ(ah , 0x5100c);
999 lcr |= 0x80;
1000
1001 REG_WRITE(ah, 0x5100c, lcr);
1002 REG_WRITE(ah, 0x51004, (baud_divider >> 8));
1003 REG_WRITE(ah, 0x51000, (baud_divider & 0xff));
1004
1005 lcr &= ~0x80;
1006 REG_WRITE(ah, 0x5100c, lcr);
1007 }
1008
1009 static void ath9k_hw_init_pll(struct ath_hw *ah,
1010 struct ath9k_channel *chan)
1011 {
1012 u32 pll;
1013
1014 if (AR_SREV_9100(ah)) {
1015 if (chan && IS_CHAN_5GHZ(chan))
1016 pll = 0x1450;
1017 else
1018 pll = 0x1458;
1019 } else {
1020 if (AR_SREV_9280_10_OR_LATER(ah)) {
1021 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1022
1023 if (chan && IS_CHAN_HALF_RATE(chan))
1024 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1025 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1026 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1027
1028 if (chan && IS_CHAN_5GHZ(chan)) {
1029 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
1030
1031
1032 if (AR_SREV_9280_20(ah)) {
1033 if (((chan->channel % 20) == 0)
1034 || ((chan->channel % 10) == 0))
1035 pll = 0x2850;
1036 else
1037 pll = 0x142c;
1038 }
1039 } else {
1040 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
1041 }
1042
1043 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1044
1045 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1046
1047 if (chan && IS_CHAN_HALF_RATE(chan))
1048 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1049 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1050 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1051
1052 if (chan && IS_CHAN_5GHZ(chan))
1053 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1054 else
1055 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1056 } else {
1057 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
1058
1059 if (chan && IS_CHAN_HALF_RATE(chan))
1060 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1061 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1062 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1063
1064 if (chan && IS_CHAN_5GHZ(chan))
1065 pll |= SM(0xa, AR_RTC_PLL_DIV);
1066 else
1067 pll |= SM(0xb, AR_RTC_PLL_DIV);
1068 }
1069 }
1070 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
1071
1072 /* Switch the core clock for ar9271 to 117Mhz */
1073 if (AR_SREV_9271(ah)) {
1074 if ((pll == 0x142c) || (pll == 0x2850) ) {
1075 udelay(500);
1076 /* set CLKOBS to output AHB clock */
1077 REG_WRITE(ah, 0x7020, 0xe);
1078 /*
1079 * 0x304: 117Mhz, ahb_ratio: 1x1
1080 * 0x306: 40Mhz, ahb_ratio: 1x1
1081 */
1082 REG_WRITE(ah, 0x50040, 0x304);
1083 /*
1084 * makes adjustments for the baud dividor to keep the
1085 * targetted baud rate based on the used core clock.
1086 */
1087 ath9k_hw_change_target_baud(ah, AR9271_CORE_CLOCK,
1088 AR9271_TARGET_BAUD_RATE);
1089 }
1090 }
1091
1092 udelay(RTC_PLL_SETTLE_DELAY);
1093
1094 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1095 }
1096
1097 static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
1098 {
1099 int rx_chainmask, tx_chainmask;
1100
1101 rx_chainmask = ah->rxchainmask;
1102 tx_chainmask = ah->txchainmask;
1103
1104 switch (rx_chainmask) {
1105 case 0x5:
1106 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1107 AR_PHY_SWAP_ALT_CHAIN);
1108 case 0x3:
1109 if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) {
1110 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1111 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1112 break;
1113 }
1114 case 0x1:
1115 case 0x2:
1116 case 0x7:
1117 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1118 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1119 break;
1120 default:
1121 break;
1122 }
1123
1124 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1125 if (tx_chainmask == 0x5) {
1126 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1127 AR_PHY_SWAP_ALT_CHAIN);
1128 }
1129 if (AR_SREV_9100(ah))
1130 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1131 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1132 }
1133
1134 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
1135 enum nl80211_iftype opmode)
1136 {
1137 ah->mask_reg = AR_IMR_TXERR |
1138 AR_IMR_TXURN |
1139 AR_IMR_RXERR |
1140 AR_IMR_RXORN |
1141 AR_IMR_BCNMISC;
1142
1143 if (ah->config.rx_intr_mitigation)
1144 ah->mask_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1145 else
1146 ah->mask_reg |= AR_IMR_RXOK;
1147
1148 ah->mask_reg |= AR_IMR_TXOK;
1149
1150 if (opmode == NL80211_IFTYPE_AP)
1151 ah->mask_reg |= AR_IMR_MIB;
1152
1153 REG_WRITE(ah, AR_IMR, ah->mask_reg);
1154 REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
1155
1156 if (!AR_SREV_9100(ah)) {
1157 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1158 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1159 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1160 }
1161 }
1162
1163 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
1164 {
1165 u32 val = ath9k_hw_mac_to_clks(ah, us);
1166 val = min(val, (u32) 0xFFFF);
1167 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
1168 }
1169
1170 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1171 {
1172 u32 val = ath9k_hw_mac_to_clks(ah, us);
1173 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
1174 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
1175 }
1176
1177 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1178 {
1179 u32 val = ath9k_hw_mac_to_clks(ah, us);
1180 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
1181 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
1182 }
1183
1184 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1185 {
1186 if (tu > 0xFFFF) {
1187 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
1188 "bad global tx timeout %u\n", tu);
1189 ah->globaltxtimeout = (u32) -1;
1190 return false;
1191 } else {
1192 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1193 ah->globaltxtimeout = tu;
1194 return true;
1195 }
1196 }
1197
1198 void ath9k_hw_init_global_settings(struct ath_hw *ah)
1199 {
1200 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
1201 int acktimeout;
1202 int slottime;
1203 int sifstime;
1204
1205 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
1206 ah->misc_mode);
1207
1208 if (ah->misc_mode != 0)
1209 REG_WRITE(ah, AR_PCU_MISC,
1210 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
1211
1212 if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
1213 sifstime = 16;
1214 else
1215 sifstime = 10;
1216
1217 /* As defined by IEEE 802.11-2007 17.3.8.6 */
1218 slottime = ah->slottime + 3 * ah->coverage_class;
1219 acktimeout = slottime + sifstime;
1220
1221 /*
1222 * Workaround for early ACK timeouts, add an offset to match the
1223 * initval's 64us ack timeout value.
1224 * This was initially only meant to work around an issue with delayed
1225 * BA frames in some implementations, but it has been found to fix ACK
1226 * timeout issues in other cases as well.
1227 */
1228 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
1229 acktimeout += 64 - sifstime - ah->slottime;
1230
1231 ath9k_hw_setslottime(ah, slottime);
1232 ath9k_hw_set_ack_timeout(ah, acktimeout);
1233 ath9k_hw_set_cts_timeout(ah, acktimeout);
1234 if (ah->globaltxtimeout != (u32) -1)
1235 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1236 }
1237 EXPORT_SYMBOL(ath9k_hw_init_global_settings);
1238
1239 void ath9k_hw_deinit(struct ath_hw *ah)
1240 {
1241 struct ath_common *common = ath9k_hw_common(ah);
1242
1243 if (common->state <= ATH_HW_INITIALIZED)
1244 goto free_hw;
1245
1246 if (!AR_SREV_9100(ah))
1247 ath9k_hw_ani_disable(ah);
1248
1249 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1250
1251 free_hw:
1252 if (!AR_SREV_9280_10_OR_LATER(ah))
1253 ath9k_hw_rf_free_ext_banks(ah);
1254 kfree(ah);
1255 ah = NULL;
1256 }
1257 EXPORT_SYMBOL(ath9k_hw_deinit);
1258
1259 /*******/
1260 /* INI */
1261 /*******/
1262
1263 static void ath9k_hw_override_ini(struct ath_hw *ah,
1264 struct ath9k_channel *chan)
1265 {
1266 u32 val;
1267
1268 if (AR_SREV_9271(ah)) {
1269 /*
1270 * Enable spectral scan to solution for issues with stuck
1271 * beacons on AR9271 1.0. The beacon stuck issue is not seeon on
1272 * AR9271 1.1
1273 */
1274 if (AR_SREV_9271_10(ah)) {
1275 val = REG_READ(ah, AR_PHY_SPECTRAL_SCAN) |
1276 AR_PHY_SPECTRAL_SCAN_ENABLE;
1277 REG_WRITE(ah, AR_PHY_SPECTRAL_SCAN, val);
1278 }
1279 else if (AR_SREV_9271_11(ah))
1280 /*
1281 * change AR_PHY_RF_CTL3 setting to fix MAC issue
1282 * present on AR9271 1.1
1283 */
1284 REG_WRITE(ah, AR_PHY_RF_CTL3, 0x3a020001);
1285 return;
1286 }
1287
1288 /*
1289 * Set the RX_ABORT and RX_DIS and clear if off only after
1290 * RXE is set for MAC. This prevents frames with corrupted
1291 * descriptor status.
1292 */
1293 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1294
1295 if (AR_SREV_9280_10_OR_LATER(ah)) {
1296 val = REG_READ(ah, AR_PCU_MISC_MODE2) &
1297 (~AR_PCU_MISC_MODE2_HWWAR1);
1298
1299 if (AR_SREV_9287_10_OR_LATER(ah))
1300 val = val & (~AR_PCU_MISC_MODE2_HWWAR2);
1301
1302 REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
1303 }
1304
1305 if (!AR_SREV_5416_20_OR_LATER(ah) ||
1306 AR_SREV_9280_10_OR_LATER(ah))
1307 return;
1308 /*
1309 * Disable BB clock gating
1310 * Necessary to avoid issues on AR5416 2.0
1311 */
1312 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1313
1314 /*
1315 * Disable RIFS search on some chips to avoid baseband
1316 * hang issues.
1317 */
1318 if (AR_SREV_9100(ah) || AR_SREV_9160(ah)) {
1319 val = REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS);
1320 val &= ~AR_PHY_RIFS_INIT_DELAY;
1321 REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val);
1322 }
1323 }
1324
1325 static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah,
1326 struct ar5416_eeprom_def *pEepData,
1327 u32 reg, u32 value)
1328 {
1329 struct base_eep_header *pBase = &(pEepData->baseEepHeader);
1330 struct ath_common *common = ath9k_hw_common(ah);
1331
1332 switch (ah->hw_version.devid) {
1333 case AR9280_DEVID_PCI:
1334 if (reg == 0x7894) {
1335 ath_print(common, ATH_DBG_EEPROM,
1336 "ini VAL: %x EEPROM: %x\n", value,
1337 (pBase->version & 0xff));
1338
1339 if ((pBase->version & 0xff) > 0x0a) {
1340 ath_print(common, ATH_DBG_EEPROM,
1341 "PWDCLKIND: %d\n",
1342 pBase->pwdclkind);
1343 value &= ~AR_AN_TOP2_PWDCLKIND;
1344 value |= AR_AN_TOP2_PWDCLKIND &
1345 (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1346 } else {
1347 ath_print(common, ATH_DBG_EEPROM,
1348 "PWDCLKIND Earlier Rev\n");
1349 }
1350
1351 ath_print(common, ATH_DBG_EEPROM,
1352 "final ini VAL: %x\n", value);
1353 }
1354 break;
1355 }
1356
1357 return value;
1358 }
1359
1360 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
1361 struct ar5416_eeprom_def *pEepData,
1362 u32 reg, u32 value)
1363 {
1364 if (ah->eep_map == EEP_MAP_4KBITS)
1365 return value;
1366 else
1367 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
1368 }
1369
1370 static void ath9k_olc_init(struct ath_hw *ah)
1371 {
1372 u32 i;
1373
1374 if (OLC_FOR_AR9287_10_LATER) {
1375 REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9,
1376 AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL);
1377 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TXPC0,
1378 AR9287_AN_TXPC0_TXPCMODE,
1379 AR9287_AN_TXPC0_TXPCMODE_S,
1380 AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE);
1381 udelay(100);
1382 } else {
1383 for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
1384 ah->originalGain[i] =
1385 MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
1386 AR_PHY_TX_GAIN);
1387 ah->PDADCdelta = 0;
1388 }
1389 }
1390
1391 static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg,
1392 struct ath9k_channel *chan)
1393 {
1394 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1395
1396 if (IS_CHAN_B(chan))
1397 ctl |= CTL_11B;
1398 else if (IS_CHAN_G(chan))
1399 ctl |= CTL_11G;
1400 else
1401 ctl |= CTL_11A;
1402
1403 return ctl;
1404 }
1405
1406 static int ath9k_hw_process_ini(struct ath_hw *ah,
1407 struct ath9k_channel *chan)
1408 {
1409 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1410 int i, regWrites = 0;
1411 struct ieee80211_channel *channel = chan->chan;
1412 u32 modesIndex, freqIndex;
1413
1414 switch (chan->chanmode) {
1415 case CHANNEL_A:
1416 case CHANNEL_A_HT20:
1417 modesIndex = 1;
1418 freqIndex = 1;
1419 break;
1420 case CHANNEL_A_HT40PLUS:
1421 case CHANNEL_A_HT40MINUS:
1422 modesIndex = 2;
1423 freqIndex = 1;
1424 break;
1425 case CHANNEL_G:
1426 case CHANNEL_G_HT20:
1427 case CHANNEL_B:
1428 modesIndex = 4;
1429 freqIndex = 2;
1430 break;
1431 case CHANNEL_G_HT40PLUS:
1432 case CHANNEL_G_HT40MINUS:
1433 modesIndex = 3;
1434 freqIndex = 2;
1435 break;
1436
1437 default:
1438 return -EINVAL;
1439 }
1440
1441 REG_WRITE(ah, AR_PHY(0), 0x00000007);
1442 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1443 ah->eep_ops->set_addac(ah, chan);
1444
1445 if (AR_SREV_5416_22_OR_LATER(ah)) {
1446 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
1447 } else {
1448 struct ar5416IniArray temp;
1449 u32 addacSize =
1450 sizeof(u32) * ah->iniAddac.ia_rows *
1451 ah->iniAddac.ia_columns;
1452
1453 memcpy(ah->addac5416_21,
1454 ah->iniAddac.ia_array, addacSize);
1455
1456 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
1457
1458 temp.ia_array = ah->addac5416_21;
1459 temp.ia_columns = ah->iniAddac.ia_columns;
1460 temp.ia_rows = ah->iniAddac.ia_rows;
1461 REG_WRITE_ARRAY(&temp, 1, regWrites);
1462 }
1463
1464 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1465
1466 for (i = 0; i < ah->iniModes.ia_rows; i++) {
1467 u32 reg = INI_RA(&ah->iniModes, i, 0);
1468 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
1469
1470 REG_WRITE(ah, reg, val);
1471
1472 if (reg >= 0x7800 && reg < 0x78a0
1473 && ah->config.analog_shiftreg) {
1474 udelay(100);
1475 }
1476
1477 DO_DELAY(regWrites);
1478 }
1479
1480 if (AR_SREV_9280(ah) || AR_SREV_9287_10_OR_LATER(ah))
1481 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
1482
1483 if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
1484 AR_SREV_9287_10_OR_LATER(ah))
1485 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1486
1487 for (i = 0; i < ah->iniCommon.ia_rows; i++) {
1488 u32 reg = INI_RA(&ah->iniCommon, i, 0);
1489 u32 val = INI_RA(&ah->iniCommon, i, 1);
1490
1491 REG_WRITE(ah, reg, val);
1492
1493 if (reg >= 0x7800 && reg < 0x78a0
1494 && ah->config.analog_shiftreg) {
1495 udelay(100);
1496 }
1497
1498 DO_DELAY(regWrites);
1499 }
1500
1501 ath9k_hw_write_regs(ah, freqIndex, regWrites);
1502
1503 if (AR_SREV_9271_10(ah))
1504 REG_WRITE_ARRAY(&ah->iniModes_9271_1_0_only,
1505 modesIndex, regWrites);
1506
1507 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1508 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
1509 regWrites);
1510 }
1511
1512 ath9k_hw_override_ini(ah, chan);
1513 ath9k_hw_set_regs(ah, chan);
1514 ath9k_hw_init_chain_masks(ah);
1515
1516 if (OLC_FOR_AR9280_20_LATER)
1517 ath9k_olc_init(ah);
1518
1519 ah->eep_ops->set_txpower(ah, chan,
1520 ath9k_regd_get_ctl(regulatory, chan),
1521 channel->max_antenna_gain * 2,
1522 channel->max_power * 2,
1523 min((u32) MAX_RATE_POWER,
1524 (u32) regulatory->power_limit));
1525
1526 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1527 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1528 "ar5416SetRfRegs failed\n");
1529 return -EIO;
1530 }
1531
1532 return 0;
1533 }
1534
1535 /****************************************/
1536 /* Reset and Channel Switching Routines */
1537 /****************************************/
1538
1539 static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
1540 {
1541 u32 rfMode = 0;
1542
1543 if (chan == NULL)
1544 return;
1545
1546 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1547 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1548
1549 if (!AR_SREV_9280_10_OR_LATER(ah))
1550 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1551 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1552
1553 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1554 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1555
1556 REG_WRITE(ah, AR_PHY_MODE, rfMode);
1557 }
1558
1559 static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
1560 {
1561 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1562 }
1563
1564 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1565 {
1566 u32 regval;
1567
1568 /*
1569 * set AHB_MODE not to do cacheline prefetches
1570 */
1571 regval = REG_READ(ah, AR_AHB_MODE);
1572 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1573
1574 /*
1575 * let mac dma reads be in 128 byte chunks
1576 */
1577 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1578 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1579
1580 /*
1581 * Restore TX Trigger Level to its pre-reset value.
1582 * The initial value depends on whether aggregation is enabled, and is
1583 * adjusted whenever underruns are detected.
1584 */
1585 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1586
1587 /*
1588 * let mac dma writes be in 128 byte chunks
1589 */
1590 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1591 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1592
1593 /*
1594 * Setup receive FIFO threshold to hold off TX activities
1595 */
1596 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1597
1598 /*
1599 * reduce the number of usable entries in PCU TXBUF to avoid
1600 * wrap around issues.
1601 */
1602 if (AR_SREV_9285(ah)) {
1603 /* For AR9285 the number of Fifos are reduced to half.
1604 * So set the usable tx buf size also to half to
1605 * avoid data/delimiter underruns
1606 */
1607 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1608 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1609 } else if (!AR_SREV_9271(ah)) {
1610 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1611 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1612 }
1613 }
1614
1615 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1616 {
1617 u32 val;
1618
1619 val = REG_READ(ah, AR_STA_ID1);
1620 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1621 switch (opmode) {
1622 case NL80211_IFTYPE_AP:
1623 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1624 | AR_STA_ID1_KSRCH_MODE);
1625 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1626 break;
1627 case NL80211_IFTYPE_ADHOC:
1628 case NL80211_IFTYPE_MESH_POINT:
1629 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1630 | AR_STA_ID1_KSRCH_MODE);
1631 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1632 break;
1633 case NL80211_IFTYPE_STATION:
1634 case NL80211_IFTYPE_MONITOR:
1635 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1636 break;
1637 }
1638 }
1639
1640 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
1641 u32 coef_scaled,
1642 u32 *coef_mantissa,
1643 u32 *coef_exponent)
1644 {
1645 u32 coef_exp, coef_man;
1646
1647 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1648 if ((coef_scaled >> coef_exp) & 0x1)
1649 break;
1650
1651 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1652
1653 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1654
1655 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1656 *coef_exponent = coef_exp - 16;
1657 }
1658
1659 static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
1660 struct ath9k_channel *chan)
1661 {
1662 u32 coef_scaled, ds_coef_exp, ds_coef_man;
1663 u32 clockMhzScaled = 0x64000000;
1664 struct chan_centers centers;
1665
1666 if (IS_CHAN_HALF_RATE(chan))
1667 clockMhzScaled = clockMhzScaled >> 1;
1668 else if (IS_CHAN_QUARTER_RATE(chan))
1669 clockMhzScaled = clockMhzScaled >> 2;
1670
1671 ath9k_hw_get_channel_centers(ah, chan, &centers);
1672 coef_scaled = clockMhzScaled / centers.synth_center;
1673
1674 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1675 &ds_coef_exp);
1676
1677 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1678 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1679 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1680 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1681
1682 coef_scaled = (9 * coef_scaled) / 10;
1683
1684 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1685 &ds_coef_exp);
1686
1687 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1688 AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1689 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1690 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1691 }
1692
1693 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1694 {
1695 u32 rst_flags;
1696 u32 tmpReg;
1697
1698 if (AR_SREV_9100(ah)) {
1699 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
1700 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
1701 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1702 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1703 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1704 }
1705
1706 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1707 AR_RTC_FORCE_WAKE_ON_INT);
1708
1709 if (AR_SREV_9100(ah)) {
1710 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1711 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1712 } else {
1713 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1714 if (tmpReg &
1715 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1716 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1717 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1718 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1719 } else {
1720 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1721 }
1722
1723 rst_flags = AR_RTC_RC_MAC_WARM;
1724 if (type == ATH9K_RESET_COLD)
1725 rst_flags |= AR_RTC_RC_MAC_COLD;
1726 }
1727
1728 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1729 udelay(50);
1730
1731 REG_WRITE(ah, AR_RTC_RC, 0);
1732 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1733 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1734 "RTC stuck in MAC reset\n");
1735 return false;
1736 }
1737
1738 if (!AR_SREV_9100(ah))
1739 REG_WRITE(ah, AR_RC, 0);
1740
1741 if (AR_SREV_9100(ah))
1742 udelay(50);
1743
1744 return true;
1745 }
1746
1747 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1748 {
1749 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1750 AR_RTC_FORCE_WAKE_ON_INT);
1751
1752 if (!AR_SREV_9100(ah))
1753 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1754
1755 REG_WRITE(ah, AR_RTC_RESET, 0);
1756 udelay(2);
1757
1758 if (!AR_SREV_9100(ah))
1759 REG_WRITE(ah, AR_RC, 0);
1760
1761 REG_WRITE(ah, AR_RTC_RESET, 1);
1762
1763 if (!ath9k_hw_wait(ah,
1764 AR_RTC_STATUS,
1765 AR_RTC_STATUS_M,
1766 AR_RTC_STATUS_ON,
1767 AH_WAIT_TIMEOUT)) {
1768 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1769 "RTC not waking up\n");
1770 return false;
1771 }
1772
1773 ath9k_hw_read_revisions(ah);
1774
1775 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1776 }
1777
1778 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1779 {
1780 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1781 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1782
1783 switch (type) {
1784 case ATH9K_RESET_POWER_ON:
1785 return ath9k_hw_set_reset_power_on(ah);
1786 case ATH9K_RESET_WARM:
1787 case ATH9K_RESET_COLD:
1788 return ath9k_hw_set_reset(ah, type);
1789 default:
1790 return false;
1791 }
1792 }
1793
1794 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan)
1795 {
1796 u32 phymode;
1797 u32 enableDacFifo = 0;
1798
1799 if (AR_SREV_9285_10_OR_LATER(ah))
1800 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1801 AR_PHY_FC_ENABLE_DAC_FIFO);
1802
1803 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1804 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
1805
1806 if (IS_CHAN_HT40(chan)) {
1807 phymode |= AR_PHY_FC_DYN2040_EN;
1808
1809 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1810 (chan->chanmode == CHANNEL_G_HT40PLUS))
1811 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1812
1813 }
1814 REG_WRITE(ah, AR_PHY_TURBO, phymode);
1815
1816 ath9k_hw_set11nmac2040(ah);
1817
1818 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1819 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1820 }
1821
1822 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1823 struct ath9k_channel *chan)
1824 {
1825 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
1826 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1827 return false;
1828 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1829 return false;
1830
1831 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1832 return false;
1833
1834 ah->chip_fullsleep = false;
1835 ath9k_hw_init_pll(ah, chan);
1836 ath9k_hw_set_rfmode(ah, chan);
1837
1838 return true;
1839 }
1840
1841 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1842 struct ath9k_channel *chan)
1843 {
1844 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1845 struct ath_common *common = ath9k_hw_common(ah);
1846 struct ieee80211_channel *channel = chan->chan;
1847 u32 synthDelay, qnum;
1848 int r;
1849
1850 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1851 if (ath9k_hw_numtxpending(ah, qnum)) {
1852 ath_print(common, ATH_DBG_QUEUE,
1853 "Transmit frames pending on "
1854 "queue %d\n", qnum);
1855 return false;
1856 }
1857 }
1858
1859 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1860 if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1861 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
1862 ath_print(common, ATH_DBG_FATAL,
1863 "Could not kill baseband RX\n");
1864 return false;
1865 }
1866
1867 ath9k_hw_set_regs(ah, chan);
1868
1869 r = ah->ath9k_hw_rf_set_freq(ah, chan);
1870 if (r) {
1871 ath_print(common, ATH_DBG_FATAL,
1872 "Failed to set channel\n");
1873 return false;
1874 }
1875
1876 ah->eep_ops->set_txpower(ah, chan,
1877 ath9k_regd_get_ctl(regulatory, chan),
1878 channel->max_antenna_gain * 2,
1879 channel->max_power * 2,
1880 min((u32) MAX_RATE_POWER,
1881 (u32) regulatory->power_limit));
1882
1883 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1884 if (IS_CHAN_B(chan))
1885 synthDelay = (4 * synthDelay) / 22;
1886 else
1887 synthDelay /= 10;
1888
1889 udelay(synthDelay + BASE_ACTIVATE_DELAY);
1890
1891 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1892
1893 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1894 ath9k_hw_set_delta_slope(ah, chan);
1895
1896 ah->ath9k_hw_spur_mitigate_freq(ah, chan);
1897
1898 if (!chan->oneTimeCalsDone)
1899 chan->oneTimeCalsDone = true;
1900
1901 return true;
1902 }
1903
1904 static void ath9k_enable_rfkill(struct ath_hw *ah)
1905 {
1906 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
1907 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
1908
1909 REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
1910 AR_GPIO_INPUT_MUX2_RFSILENT);
1911
1912 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
1913 REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
1914 }
1915
1916 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1917 bool bChannelChange)
1918 {
1919 struct ath_common *common = ath9k_hw_common(ah);
1920 u32 saveLedState;
1921 struct ath9k_channel *curchan = ah->curchan;
1922 u32 saveDefAntenna;
1923 u32 macStaId1;
1924 u64 tsf = 0;
1925 int i, rx_chainmask, r;
1926
1927 ah->txchainmask = common->tx_chainmask;
1928 ah->rxchainmask = common->rx_chainmask;
1929
1930 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1931 return -EIO;
1932
1933 if (curchan && !ah->chip_fullsleep)
1934 ath9k_hw_getnf(ah, curchan);
1935
1936 if (bChannelChange &&
1937 (ah->chip_fullsleep != true) &&
1938 (ah->curchan != NULL) &&
1939 (chan->channel != ah->curchan->channel) &&
1940 ((chan->channelFlags & CHANNEL_ALL) ==
1941 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
1942 !(AR_SREV_9280(ah) || IS_CHAN_A_5MHZ_SPACED(chan) ||
1943 IS_CHAN_A_5MHZ_SPACED(ah->curchan))) {
1944
1945 if (ath9k_hw_channel_change(ah, chan)) {
1946 ath9k_hw_loadnf(ah, ah->curchan);
1947 ath9k_hw_start_nfcal(ah);
1948 return 0;
1949 }
1950 }
1951
1952 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1953 if (saveDefAntenna == 0)
1954 saveDefAntenna = 1;
1955
1956 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1957
1958 /* For chips on which RTC reset is done, save TSF before it gets cleared */
1959 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1960 tsf = ath9k_hw_gettsf64(ah);
1961
1962 saveLedState = REG_READ(ah, AR_CFG_LED) &
1963 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1964 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1965
1966 ath9k_hw_mark_phy_inactive(ah);
1967
1968 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1969 REG_WRITE(ah,
1970 AR9271_RESET_POWER_DOWN_CONTROL,
1971 AR9271_RADIO_RF_RST);
1972 udelay(50);
1973 }
1974
1975 if (!ath9k_hw_chip_reset(ah, chan)) {
1976 ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n");
1977 return -EINVAL;
1978 }
1979
1980 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1981 ah->htc_reset_init = false;
1982 REG_WRITE(ah,
1983 AR9271_RESET_POWER_DOWN_CONTROL,
1984 AR9271_GATE_MAC_CTL);
1985 udelay(50);
1986 }
1987
1988 /* Restore TSF */
1989 if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1990 ath9k_hw_settsf64(ah, tsf);
1991
1992 if (AR_SREV_9280_10_OR_LATER(ah))
1993 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1994
1995 if (AR_SREV_9287_12_OR_LATER(ah)) {
1996 /* Enable ASYNC FIFO */
1997 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
1998 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
1999 REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
2000 REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2001 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
2002 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2003 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
2004 }
2005 r = ath9k_hw_process_ini(ah, chan);
2006 if (r)
2007 return r;
2008
2009 /* Setup MFP options for CCMP */
2010 if (AR_SREV_9280_20_OR_LATER(ah)) {
2011 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
2012 * frames when constructing CCMP AAD. */
2013 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
2014 0xc7ff);
2015 ah->sw_mgmt_crypto = false;
2016 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
2017 /* Disable hardware crypto for management frames */
2018 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
2019 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
2020 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2021 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
2022 ah->sw_mgmt_crypto = true;
2023 } else
2024 ah->sw_mgmt_crypto = true;
2025
2026 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2027 ath9k_hw_set_delta_slope(ah, chan);
2028
2029 ah->ath9k_hw_spur_mitigate_freq(ah, chan);
2030 ah->eep_ops->set_board_values(ah, chan);
2031
2032 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
2033 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
2034 | macStaId1
2035 | AR_STA_ID1_RTS_USE_DEF
2036 | (ah->config.
2037 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2038 | ah->sta_id1_defaults);
2039 ath9k_hw_set_operating_mode(ah, ah->opmode);
2040
2041 ath_hw_setbssidmask(common);
2042
2043 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2044
2045 ath9k_hw_write_associd(ah);
2046
2047 REG_WRITE(ah, AR_ISR, ~0);
2048
2049 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2050
2051 r = ah->ath9k_hw_rf_set_freq(ah, chan);
2052 if (r)
2053 return r;
2054
2055 for (i = 0; i < AR_NUM_DCU; i++)
2056 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2057
2058 ah->intr_txqs = 0;
2059 for (i = 0; i < ah->caps.total_queues; i++)
2060 ath9k_hw_resettxqueue(ah, i);
2061
2062 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
2063 ath9k_hw_init_qos(ah);
2064
2065 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2066 ath9k_enable_rfkill(ah);
2067
2068 ath9k_hw_init_global_settings(ah);
2069
2070 if (AR_SREV_9287_12_OR_LATER(ah)) {
2071 REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
2072 AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
2073 REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
2074 AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
2075 REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
2076 AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
2077
2078 REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
2079 REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
2080
2081 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
2082 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
2083 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
2084 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
2085 }
2086 if (AR_SREV_9287_12_OR_LATER(ah)) {
2087 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2088 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
2089 }
2090
2091 REG_WRITE(ah, AR_STA_ID1,
2092 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2093
2094 ath9k_hw_set_dma(ah);
2095
2096 REG_WRITE(ah, AR_OBS, 8);
2097
2098 if (ah->config.rx_intr_mitigation) {
2099 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2100 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2101 }
2102
2103 ath9k_hw_init_bb(ah, chan);
2104
2105 if (!ath9k_hw_init_cal(ah, chan))
2106 return -EIO;
2107
2108 rx_chainmask = ah->rxchainmask;
2109 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2110 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2111 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2112 }
2113
2114 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2115
2116 /*
2117 * For big endian systems turn on swapping for descriptors
2118 */
2119 if (AR_SREV_9100(ah)) {
2120 u32 mask;
2121 mask = REG_READ(ah, AR_CFG);
2122 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2123 ath_print(common, ATH_DBG_RESET,
2124 "CFG Byte Swap Set 0x%x\n", mask);
2125 } else {
2126 mask =
2127 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2128 REG_WRITE(ah, AR_CFG, mask);
2129 ath_print(common, ATH_DBG_RESET,
2130 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
2131 }
2132 } else {
2133 /* Configure AR9271 target WLAN */
2134 if (AR_SREV_9271(ah))
2135 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
2136 #ifdef __BIG_ENDIAN
2137 else
2138 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2139 #endif
2140 }
2141
2142 if (ah->btcoex_hw.enabled)
2143 ath9k_hw_btcoex_enable(ah);
2144
2145 return 0;
2146 }
2147 EXPORT_SYMBOL(ath9k_hw_reset);
2148
2149 /************************/
2150 /* Key Cache Management */
2151 /************************/
2152
2153 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
2154 {
2155 u32 keyType;
2156
2157 if (entry >= ah->caps.keycache_size) {
2158 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2159 "keychache entry %u out of range\n", entry);
2160 return false;
2161 }
2162
2163 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
2164
2165 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2166 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2167 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2168 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2169 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2170 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2171 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2172 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
2173
2174 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2175 u16 micentry = entry + 64;
2176
2177 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2178 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2179 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2180 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2181
2182 }
2183
2184 return true;
2185 }
2186 EXPORT_SYMBOL(ath9k_hw_keyreset);
2187
2188 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
2189 {
2190 u32 macHi, macLo;
2191
2192 if (entry >= ah->caps.keycache_size) {
2193 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2194 "keychache entry %u out of range\n", entry);
2195 return false;
2196 }
2197
2198 if (mac != NULL) {
2199 macHi = (mac[5] << 8) | mac[4];
2200 macLo = (mac[3] << 24) |
2201 (mac[2] << 16) |
2202 (mac[1] << 8) |
2203 mac[0];
2204 macLo >>= 1;
2205 macLo |= (macHi & 1) << 31;
2206 macHi >>= 1;
2207 } else {
2208 macLo = macHi = 0;
2209 }
2210 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2211 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
2212
2213 return true;
2214 }
2215 EXPORT_SYMBOL(ath9k_hw_keysetmac);
2216
2217 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2218 const struct ath9k_keyval *k,
2219 const u8 *mac)
2220 {
2221 const struct ath9k_hw_capabilities *pCap = &ah->caps;
2222 struct ath_common *common = ath9k_hw_common(ah);
2223 u32 key0, key1, key2, key3, key4;
2224 u32 keyType;
2225
2226 if (entry >= pCap->keycache_size) {
2227 ath_print(common, ATH_DBG_FATAL,
2228 "keycache entry %u out of range\n", entry);
2229 return false;
2230 }
2231
2232 switch (k->kv_type) {
2233 case ATH9K_CIPHER_AES_OCB:
2234 keyType = AR_KEYTABLE_TYPE_AES;
2235 break;
2236 case ATH9K_CIPHER_AES_CCM:
2237 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2238 ath_print(common, ATH_DBG_ANY,
2239 "AES-CCM not supported by mac rev 0x%x\n",
2240 ah->hw_version.macRev);
2241 return false;
2242 }
2243 keyType = AR_KEYTABLE_TYPE_CCM;
2244 break;
2245 case ATH9K_CIPHER_TKIP:
2246 keyType = AR_KEYTABLE_TYPE_TKIP;
2247 if (ATH9K_IS_MIC_ENABLED(ah)
2248 && entry + 64 >= pCap->keycache_size) {
2249 ath_print(common, ATH_DBG_ANY,
2250 "entry %u inappropriate for TKIP\n", entry);
2251 return false;
2252 }
2253 break;
2254 case ATH9K_CIPHER_WEP:
2255 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
2256 ath_print(common, ATH_DBG_ANY,
2257 "WEP key length %u too small\n", k->kv_len);
2258 return false;
2259 }
2260 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
2261 keyType = AR_KEYTABLE_TYPE_40;
2262 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
2263 keyType = AR_KEYTABLE_TYPE_104;
2264 else
2265 keyType = AR_KEYTABLE_TYPE_128;
2266 break;
2267 case ATH9K_CIPHER_CLR:
2268 keyType = AR_KEYTABLE_TYPE_CLR;
2269 break;
2270 default:
2271 ath_print(common, ATH_DBG_FATAL,
2272 "cipher %u not supported\n", k->kv_type);
2273 return false;
2274 }
2275
2276 key0 = get_unaligned_le32(k->kv_val + 0);
2277 key1 = get_unaligned_le16(k->kv_val + 4);
2278 key2 = get_unaligned_le32(k->kv_val + 6);
2279 key3 = get_unaligned_le16(k->kv_val + 10);
2280 key4 = get_unaligned_le32(k->kv_val + 12);
2281 if (k->kv_len <= WLAN_KEY_LEN_WEP104)
2282 key4 &= 0xff;
2283
2284 /*
2285 * Note: Key cache registers access special memory area that requires
2286 * two 32-bit writes to actually update the values in the internal
2287 * memory. Consequently, the exact order and pairs used here must be
2288 * maintained.
2289 */
2290
2291 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2292 u16 micentry = entry + 64;
2293
2294 /*
2295 * Write inverted key[47:0] first to avoid Michael MIC errors
2296 * on frames that could be sent or received at the same time.
2297 * The correct key will be written in the end once everything
2298 * else is ready.
2299 */
2300 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2301 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
2302
2303 /* Write key[95:48] */
2304 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2305 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2306
2307 /* Write key[127:96] and key type */
2308 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2309 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2310
2311 /* Write MAC address for the entry */
2312 (void) ath9k_hw_keysetmac(ah, entry, mac);
2313
2314 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
2315 /*
2316 * TKIP uses two key cache entries:
2317 * Michael MIC TX/RX keys in the same key cache entry
2318 * (idx = main index + 64):
2319 * key0 [31:0] = RX key [31:0]
2320 * key1 [15:0] = TX key [31:16]
2321 * key1 [31:16] = reserved
2322 * key2 [31:0] = RX key [63:32]
2323 * key3 [15:0] = TX key [15:0]
2324 * key3 [31:16] = reserved
2325 * key4 [31:0] = TX key [63:32]
2326 */
2327 u32 mic0, mic1, mic2, mic3, mic4;
2328
2329 mic0 = get_unaligned_le32(k->kv_mic + 0);
2330 mic2 = get_unaligned_le32(k->kv_mic + 4);
2331 mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2332 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2333 mic4 = get_unaligned_le32(k->kv_txmic + 4);
2334
2335 /* Write RX[31:0] and TX[31:16] */
2336 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2337 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2338
2339 /* Write RX[63:32] and TX[15:0] */
2340 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2341 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2342
2343 /* Write TX[63:32] and keyType(reserved) */
2344 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2345 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2346 AR_KEYTABLE_TYPE_CLR);
2347
2348 } else {
2349 /*
2350 * TKIP uses four key cache entries (two for group
2351 * keys):
2352 * Michael MIC TX/RX keys are in different key cache
2353 * entries (idx = main index + 64 for TX and
2354 * main index + 32 + 96 for RX):
2355 * key0 [31:0] = TX/RX MIC key [31:0]
2356 * key1 [31:0] = reserved
2357 * key2 [31:0] = TX/RX MIC key [63:32]
2358 * key3 [31:0] = reserved
2359 * key4 [31:0] = reserved
2360 *
2361 * Upper layer code will call this function separately
2362 * for TX and RX keys when these registers offsets are
2363 * used.
2364 */
2365 u32 mic0, mic2;
2366
2367 mic0 = get_unaligned_le32(k->kv_mic + 0);
2368 mic2 = get_unaligned_le32(k->kv_mic + 4);
2369
2370 /* Write MIC key[31:0] */
2371 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2372 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2373
2374 /* Write MIC key[63:32] */
2375 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2376 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2377
2378 /* Write TX[63:32] and keyType(reserved) */
2379 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2380 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2381 AR_KEYTABLE_TYPE_CLR);
2382 }
2383
2384 /* MAC address registers are reserved for the MIC entry */
2385 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2386 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2387
2388 /*
2389 * Write the correct (un-inverted) key[47:0] last to enable
2390 * TKIP now that all other registers are set with correct
2391 * values.
2392 */
2393 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2394 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2395 } else {
2396 /* Write key[47:0] */
2397 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2398 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2399
2400 /* Write key[95:48] */
2401 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2402 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2403
2404 /* Write key[127:96] and key type */
2405 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2406 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2407
2408 /* Write MAC address for the entry */
2409 (void) ath9k_hw_keysetmac(ah, entry, mac);
2410 }
2411
2412 return true;
2413 }
2414 EXPORT_SYMBOL(ath9k_hw_set_keycache_entry);
2415
2416 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
2417 {
2418 if (entry < ah->caps.keycache_size) {
2419 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2420 if (val & AR_KEYTABLE_VALID)
2421 return true;
2422 }
2423 return false;
2424 }
2425 EXPORT_SYMBOL(ath9k_hw_keyisvalid);
2426
2427 /******************************/
2428 /* Power Management (Chipset) */
2429 /******************************/
2430
2431 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
2432 {
2433 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2434 if (setChip) {
2435 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2436 AR_RTC_FORCE_WAKE_EN);
2437 if (!AR_SREV_9100(ah))
2438 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2439
2440 if(!AR_SREV_5416(ah))
2441 REG_CLR_BIT(ah, (AR_RTC_RESET),
2442 AR_RTC_RESET_EN);
2443 }
2444 }
2445
2446 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
2447 {
2448 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2449 if (setChip) {
2450 struct ath9k_hw_capabilities *pCap = &ah->caps;
2451
2452 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2453 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2454 AR_RTC_FORCE_WAKE_ON_INT);
2455 } else {
2456 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2457 AR_RTC_FORCE_WAKE_EN);
2458 }
2459 }
2460 }
2461
2462 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2463 {
2464 u32 val;
2465 int i;
2466
2467 if (setChip) {
2468 if ((REG_READ(ah, AR_RTC_STATUS) &
2469 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2470 if (ath9k_hw_set_reset_reg(ah,
2471 ATH9K_RESET_POWER_ON) != true) {
2472 return false;
2473 }
2474 ath9k_hw_init_pll(ah, NULL);
2475 }
2476 if (AR_SREV_9100(ah))
2477 REG_SET_BIT(ah, AR_RTC_RESET,
2478 AR_RTC_RESET_EN);
2479
2480 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2481 AR_RTC_FORCE_WAKE_EN);
2482 udelay(50);
2483
2484 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2485 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2486 if (val == AR_RTC_STATUS_ON)
2487 break;
2488 udelay(50);
2489 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2490 AR_RTC_FORCE_WAKE_EN);
2491 }
2492 if (i == 0) {
2493 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2494 "Failed to wakeup in %uus\n",
2495 POWER_UP_TIME / 20);
2496 return false;
2497 }
2498 }
2499
2500 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2501
2502 return true;
2503 }
2504
2505 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2506 {
2507 struct ath_common *common = ath9k_hw_common(ah);
2508 int status = true, setChip = true;
2509 static const char *modes[] = {
2510 "AWAKE",
2511 "FULL-SLEEP",
2512 "NETWORK SLEEP",
2513 "UNDEFINED"
2514 };
2515
2516 if (ah->power_mode == mode)
2517 return status;
2518
2519 ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
2520 modes[ah->power_mode], modes[mode]);
2521
2522 switch (mode) {
2523 case ATH9K_PM_AWAKE:
2524 status = ath9k_hw_set_power_awake(ah, setChip);
2525 break;
2526 case ATH9K_PM_FULL_SLEEP:
2527 ath9k_set_power_sleep(ah, setChip);
2528 ah->chip_fullsleep = true;
2529 break;
2530 case ATH9K_PM_NETWORK_SLEEP:
2531 ath9k_set_power_network_sleep(ah, setChip);
2532 break;
2533 default:
2534 ath_print(common, ATH_DBG_FATAL,
2535 "Unknown power mode %u\n", mode);
2536 return false;
2537 }
2538 ah->power_mode = mode;
2539
2540 return status;
2541 }
2542 EXPORT_SYMBOL(ath9k_hw_setpower);
2543
2544 /*
2545 * Helper for ASPM support.
2546 *
2547 * Disable PLL when in L0s as well as receiver clock when in L1.
2548 * This power saving option must be enabled through the SerDes.
2549 *
2550 * Programming the SerDes must go through the same 288 bit serial shift
2551 * register as the other analog registers. Hence the 9 writes.
2552 */
2553 void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off)
2554 {
2555 u8 i;
2556 u32 val;
2557
2558 if (ah->is_pciexpress != true)
2559 return;
2560
2561 /* Do not touch SerDes registers */
2562 if (ah->config.pcie_powersave_enable == 2)
2563 return;
2564
2565 /* Nothing to do on restore for 11N */
2566 if (!restore) {
2567 if (AR_SREV_9280_20_OR_LATER(ah)) {
2568 /*
2569 * AR9280 2.0 or later chips use SerDes values from the
2570 * initvals.h initialized depending on chipset during
2571 * ath9k_hw_init()
2572 */
2573 for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
2574 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
2575 INI_RA(&ah->iniPcieSerdes, i, 1));
2576 }
2577 } else if (AR_SREV_9280(ah) &&
2578 (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
2579 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2580 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2581
2582 /* RX shut off when elecidle is asserted */
2583 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2584 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2585 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2586
2587 /* Shut off CLKREQ active in L1 */
2588 if (ah->config.pcie_clock_req)
2589 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2590 else
2591 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
2592
2593 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2594 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2595 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
2596
2597 /* Load the new settings */
2598 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2599
2600 } else {
2601 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2602 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2603
2604 /* RX shut off when elecidle is asserted */
2605 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2606 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2607 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
2608
2609 /*
2610 * Ignore ah->ah_config.pcie_clock_req setting for
2611 * pre-AR9280 11n
2612 */
2613 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2614
2615 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2616 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2617 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
2618
2619 /* Load the new settings */
2620 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2621 }
2622
2623 udelay(1000);
2624
2625 /* set bit 19 to allow forcing of pcie core into L1 state */
2626 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
2627
2628 /* Several PCIe massages to ensure proper behaviour */
2629 if (ah->config.pcie_waen) {
2630 val = ah->config.pcie_waen;
2631 if (!power_off)
2632 val &= (~AR_WA_D3_L1_DISABLE);
2633 } else {
2634 if (AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
2635 AR_SREV_9287(ah)) {
2636 val = AR9285_WA_DEFAULT;
2637 if (!power_off)
2638 val &= (~AR_WA_D3_L1_DISABLE);
2639 } else if (AR_SREV_9280(ah)) {
2640 /*
2641 * On AR9280 chips bit 22 of 0x4004 needs to be
2642 * set otherwise card may disappear.
2643 */
2644 val = AR9280_WA_DEFAULT;
2645 if (!power_off)
2646 val &= (~AR_WA_D3_L1_DISABLE);
2647 } else
2648 val = AR_WA_DEFAULT;
2649 }
2650
2651 REG_WRITE(ah, AR_WA, val);
2652 }
2653
2654 if (power_off) {
2655 /*
2656 * Set PCIe workaround bits
2657 * bit 14 in WA register (disable L1) should only
2658 * be set when device enters D3 and be cleared
2659 * when device comes back to D0.
2660 */
2661 if (ah->config.pcie_waen) {
2662 if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE)
2663 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
2664 } else {
2665 if (((AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
2666 AR_SREV_9287(ah)) &&
2667 (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) ||
2668 (AR_SREV_9280(ah) &&
2669 (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) {
2670 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
2671 }
2672 }
2673 }
2674 }
2675 EXPORT_SYMBOL(ath9k_hw_configpcipowersave);
2676
2677 /**********************/
2678 /* Interrupt Handling */
2679 /**********************/
2680
2681 bool ath9k_hw_intrpend(struct ath_hw *ah)
2682 {
2683 u32 host_isr;
2684
2685 if (AR_SREV_9100(ah))
2686 return true;
2687
2688 host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
2689 if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
2690 return true;
2691
2692 host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
2693 if ((host_isr & AR_INTR_SYNC_DEFAULT)
2694 && (host_isr != AR_INTR_SPURIOUS))
2695 return true;
2696
2697 return false;
2698 }
2699 EXPORT_SYMBOL(ath9k_hw_intrpend);
2700
2701 bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
2702 {
2703 u32 isr = 0;
2704 u32 mask2 = 0;
2705 struct ath9k_hw_capabilities *pCap = &ah->caps;
2706 u32 sync_cause = 0;
2707 bool fatal_int = false;
2708 struct ath_common *common = ath9k_hw_common(ah);
2709
2710 if (!AR_SREV_9100(ah)) {
2711 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
2712 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
2713 == AR_RTC_STATUS_ON) {
2714 isr = REG_READ(ah, AR_ISR);
2715 }
2716 }
2717
2718 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
2719 AR_INTR_SYNC_DEFAULT;
2720
2721 *masked = 0;
2722
2723 if (!isr && !sync_cause)
2724 return false;
2725 } else {
2726 *masked = 0;
2727 isr = REG_READ(ah, AR_ISR);
2728 }
2729
2730 if (isr) {
2731 if (isr & AR_ISR_BCNMISC) {
2732 u32 isr2;
2733 isr2 = REG_READ(ah, AR_ISR_S2);
2734 if (isr2 & AR_ISR_S2_TIM)
2735 mask2 |= ATH9K_INT_TIM;
2736 if (isr2 & AR_ISR_S2_DTIM)
2737 mask2 |= ATH9K_INT_DTIM;
2738 if (isr2 & AR_ISR_S2_DTIMSYNC)
2739 mask2 |= ATH9K_INT_DTIMSYNC;
2740 if (isr2 & (AR_ISR_S2_CABEND))
2741 mask2 |= ATH9K_INT_CABEND;
2742 if (isr2 & AR_ISR_S2_GTT)
2743 mask2 |= ATH9K_INT_GTT;
2744 if (isr2 & AR_ISR_S2_CST)
2745 mask2 |= ATH9K_INT_CST;
2746 if (isr2 & AR_ISR_S2_TSFOOR)
2747 mask2 |= ATH9K_INT_TSFOOR;
2748 }
2749
2750 isr = REG_READ(ah, AR_ISR_RAC);
2751 if (isr == 0xffffffff) {
2752 *masked = 0;
2753 return false;
2754 }
2755
2756 *masked = isr & ATH9K_INT_COMMON;
2757
2758 if (ah->config.rx_intr_mitigation) {
2759 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
2760 *masked |= ATH9K_INT_RX;
2761 }
2762
2763 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
2764 *masked |= ATH9K_INT_RX;
2765 if (isr &
2766 (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
2767 AR_ISR_TXEOL)) {
2768 u32 s0_s, s1_s;
2769
2770 *masked |= ATH9K_INT_TX;
2771
2772 s0_s = REG_READ(ah, AR_ISR_S0_S);
2773 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
2774 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
2775
2776 s1_s = REG_READ(ah, AR_ISR_S1_S);
2777 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
2778 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
2779 }
2780
2781 if (isr & AR_ISR_RXORN) {
2782 ath_print(common, ATH_DBG_INTERRUPT,
2783 "receive FIFO overrun interrupt\n");
2784 }
2785
2786 if (!AR_SREV_9100(ah)) {
2787 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2788 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
2789 if (isr5 & AR_ISR_S5_TIM_TIMER)
2790 *masked |= ATH9K_INT_TIM_TIMER;
2791 }
2792 }
2793
2794 *masked |= mask2;
2795 }
2796
2797 if (AR_SREV_9100(ah))
2798 return true;
2799
2800 if (isr & AR_ISR_GENTMR) {
2801 u32 s5_s;
2802
2803 s5_s = REG_READ(ah, AR_ISR_S5_S);
2804 if (isr & AR_ISR_GENTMR) {
2805 ah->intr_gen_timer_trigger =
2806 MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
2807
2808 ah->intr_gen_timer_thresh =
2809 MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);
2810
2811 if (ah->intr_gen_timer_trigger)
2812 *masked |= ATH9K_INT_GENTIMER;
2813
2814 }
2815 }
2816
2817 if (sync_cause) {
2818 fatal_int =
2819 (sync_cause &
2820 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
2821 ? true : false;
2822
2823 if (fatal_int) {
2824 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
2825 ath_print(common, ATH_DBG_ANY,
2826 "received PCI FATAL interrupt\n");
2827 }
2828 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
2829 ath_print(common, ATH_DBG_ANY,
2830 "received PCI PERR interrupt\n");
2831 }
2832 *masked |= ATH9K_INT_FATAL;
2833 }
2834 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
2835 ath_print(common, ATH_DBG_INTERRUPT,
2836 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
2837 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
2838 REG_WRITE(ah, AR_RC, 0);
2839 *masked |= ATH9K_INT_FATAL;
2840 }
2841 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
2842 ath_print(common, ATH_DBG_INTERRUPT,
2843 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
2844 }
2845
2846 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
2847 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
2848 }
2849
2850 return true;
2851 }
2852 EXPORT_SYMBOL(ath9k_hw_getisr);
2853
2854 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
2855 {
2856 u32 omask = ah->mask_reg;
2857 u32 mask, mask2;
2858 struct ath9k_hw_capabilities *pCap = &ah->caps;
2859 struct ath_common *common = ath9k_hw_common(ah);
2860
2861 ath_print(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
2862
2863 if (omask & ATH9K_INT_GLOBAL) {
2864 ath_print(common, ATH_DBG_INTERRUPT, "disable IER\n");
2865 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
2866 (void) REG_READ(ah, AR_IER);
2867 if (!AR_SREV_9100(ah)) {
2868 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
2869 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
2870
2871 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
2872 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
2873 }
2874 }
2875
2876 mask = ints & ATH9K_INT_COMMON;
2877 mask2 = 0;
2878
2879 if (ints & ATH9K_INT_TX) {
2880 if (ah->txok_interrupt_mask)
2881 mask |= AR_IMR_TXOK;
2882 if (ah->txdesc_interrupt_mask)
2883 mask |= AR_IMR_TXDESC;
2884 if (ah->txerr_interrupt_mask)
2885 mask |= AR_IMR_TXERR;
2886 if (ah->txeol_interrupt_mask)
2887 mask |= AR_IMR_TXEOL;
2888 }
2889 if (ints & ATH9K_INT_RX) {
2890 mask |= AR_IMR_RXERR;
2891 if (ah->config.rx_intr_mitigation)
2892 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
2893 else
2894 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
2895 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
2896 mask |= AR_IMR_GENTMR;
2897 }
2898
2899 if (ints & (ATH9K_INT_BMISC)) {
2900 mask |= AR_IMR_BCNMISC;
2901 if (ints & ATH9K_INT_TIM)
2902 mask2 |= AR_IMR_S2_TIM;
2903 if (ints & ATH9K_INT_DTIM)
2904 mask2 |= AR_IMR_S2_DTIM;
2905 if (ints & ATH9K_INT_DTIMSYNC)
2906 mask2 |= AR_IMR_S2_DTIMSYNC;
2907 if (ints & ATH9K_INT_CABEND)
2908 mask2 |= AR_IMR_S2_CABEND;
2909 if (ints & ATH9K_INT_TSFOOR)
2910 mask2 |= AR_IMR_S2_TSFOOR;
2911 }
2912
2913 if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
2914 mask |= AR_IMR_BCNMISC;
2915 if (ints & ATH9K_INT_GTT)
2916 mask2 |= AR_IMR_S2_GTT;
2917 if (ints & ATH9K_INT_CST)
2918 mask2 |= AR_IMR_S2_CST;
2919 }
2920
2921 ath_print(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
2922 REG_WRITE(ah, AR_IMR, mask);
2923 mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
2924 AR_IMR_S2_DTIM |
2925 AR_IMR_S2_DTIMSYNC |
2926 AR_IMR_S2_CABEND |
2927 AR_IMR_S2_CABTO |
2928 AR_IMR_S2_TSFOOR |
2929 AR_IMR_S2_GTT | AR_IMR_S2_CST);
2930 REG_WRITE(ah, AR_IMR_S2, mask | mask2);
2931 ah->mask_reg = ints;
2932
2933 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2934 if (ints & ATH9K_INT_TIM_TIMER)
2935 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
2936 else
2937 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
2938 }
2939
2940 if (ints & ATH9K_INT_GLOBAL) {
2941 ath_print(common, ATH_DBG_INTERRUPT, "enable IER\n");
2942 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
2943 if (!AR_SREV_9100(ah)) {
2944 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
2945 AR_INTR_MAC_IRQ);
2946 REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
2947
2948
2949 REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
2950 AR_INTR_SYNC_DEFAULT);
2951 REG_WRITE(ah, AR_INTR_SYNC_MASK,
2952 AR_INTR_SYNC_DEFAULT);
2953 }
2954 ath_print(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
2955 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
2956 }
2957
2958 return omask;
2959 }
2960 EXPORT_SYMBOL(ath9k_hw_set_interrupts);
2961
2962 /*******************/
2963 /* Beacon Handling */
2964 /*******************/
2965
2966 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
2967 {
2968 int flags = 0;
2969
2970 ah->beacon_interval = beacon_period;
2971
2972 switch (ah->opmode) {
2973 case NL80211_IFTYPE_STATION:
2974 case NL80211_IFTYPE_MONITOR:
2975 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
2976 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
2977 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
2978 flags |= AR_TBTT_TIMER_EN;
2979 break;
2980 case NL80211_IFTYPE_ADHOC:
2981 case NL80211_IFTYPE_MESH_POINT:
2982 REG_SET_BIT(ah, AR_TXCFG,
2983 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
2984 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
2985 TU_TO_USEC(next_beacon +
2986 (ah->atim_window ? ah->
2987 atim_window : 1)));
2988 flags |= AR_NDP_TIMER_EN;
2989 case NL80211_IFTYPE_AP:
2990 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
2991 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
2992 TU_TO_USEC(next_beacon -
2993 ah->config.
2994 dma_beacon_response_time));
2995 REG_WRITE(ah, AR_NEXT_SWBA,
2996 TU_TO_USEC(next_beacon -
2997 ah->config.
2998 sw_beacon_response_time));
2999 flags |=
3000 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
3001 break;
3002 default:
3003 ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
3004 "%s: unsupported opmode: %d\n",
3005 __func__, ah->opmode);
3006 return;
3007 break;
3008 }
3009
3010 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3011 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3012 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
3013 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
3014
3015 beacon_period &= ~ATH9K_BEACON_ENA;
3016 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
3017 ath9k_hw_reset_tsf(ah);
3018 }
3019
3020 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3021 }
3022 EXPORT_SYMBOL(ath9k_hw_beaconinit);
3023
3024 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
3025 const struct ath9k_beacon_state *bs)
3026 {
3027 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
3028 struct ath9k_hw_capabilities *pCap = &ah->caps;
3029 struct ath_common *common = ath9k_hw_common(ah);
3030
3031 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3032
3033 REG_WRITE(ah, AR_BEACON_PERIOD,
3034 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3035 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3036 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3037
3038 REG_RMW_FIELD(ah, AR_RSSI_THR,
3039 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3040
3041 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3042
3043 if (bs->bs_sleepduration > beaconintval)
3044 beaconintval = bs->bs_sleepduration;
3045
3046 dtimperiod = bs->bs_dtimperiod;
3047 if (bs->bs_sleepduration > dtimperiod)
3048 dtimperiod = bs->bs_sleepduration;
3049
3050 if (beaconintval == dtimperiod)
3051 nextTbtt = bs->bs_nextdtim;
3052 else
3053 nextTbtt = bs->bs_nexttbtt;
3054
3055 ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3056 ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3057 ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3058 ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
3059
3060 REG_WRITE(ah, AR_NEXT_DTIM,
3061 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3062 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
3063
3064 REG_WRITE(ah, AR_SLEEP1,
3065 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3066 | AR_SLEEP1_ASSUME_DTIM);
3067
3068 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3069 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3070 else
3071 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
3072
3073 REG_WRITE(ah, AR_SLEEP2,
3074 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
3075
3076 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3077 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
3078
3079 REG_SET_BIT(ah, AR_TIMER_MODE,
3080 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3081 AR_DTIM_TIMER_EN);
3082
3083 /* TSF Out of Range Threshold */
3084 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
3085 }
3086 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
3087
3088 /*******************/
3089 /* HW Capabilities */
3090 /*******************/
3091
3092 int ath9k_hw_fill_cap_info(struct ath_hw *ah)
3093 {
3094 struct ath9k_hw_capabilities *pCap = &ah->caps;
3095 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3096 struct ath_common *common = ath9k_hw_common(ah);
3097 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
3098
3099 u16 capField = 0, eeval;
3100
3101 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
3102 regulatory->current_rd = eeval;
3103
3104 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
3105 if (AR_SREV_9285_10_OR_LATER(ah))
3106 eeval |= AR9285_RDEXT_DEFAULT;
3107 regulatory->current_rd_ext = eeval;
3108
3109 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
3110
3111 if (ah->opmode != NL80211_IFTYPE_AP &&
3112 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3113 if (regulatory->current_rd == 0x64 ||
3114 regulatory->current_rd == 0x65)
3115 regulatory->current_rd += 5;
3116 else if (regulatory->current_rd == 0x41)
3117 regulatory->current_rd = 0x43;
3118 ath_print(common, ATH_DBG_REGULATORY,
3119 "regdomain mapped to 0x%x\n", regulatory->current_rd);
3120 }
3121
3122 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
3123 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
3124 ath_print(common, ATH_DBG_FATAL,
3125 "no band has been marked as supported in EEPROM.\n");
3126 return -EINVAL;
3127 }
3128
3129 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
3130
3131 if (eeval & AR5416_OPFLAGS_11A) {
3132 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
3133 if (ah->config.ht_enable) {
3134 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3135 set_bit(ATH9K_MODE_11NA_HT20,
3136 pCap->wireless_modes);
3137 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3138 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3139 pCap->wireless_modes);
3140 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3141 pCap->wireless_modes);
3142 }
3143 }
3144 }
3145
3146 if (eeval & AR5416_OPFLAGS_11G) {
3147 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
3148 if (ah->config.ht_enable) {
3149 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3150 set_bit(ATH9K_MODE_11NG_HT20,
3151 pCap->wireless_modes);
3152 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3153 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3154 pCap->wireless_modes);
3155 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3156 pCap->wireless_modes);
3157 }
3158 }
3159 }
3160
3161 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
3162 /*
3163 * For AR9271 we will temporarilly uses the rx chainmax as read from
3164 * the EEPROM.
3165 */
3166 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
3167 !(eeval & AR5416_OPFLAGS_11A) &&
3168 !(AR_SREV_9271(ah)))
3169 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
3170 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
3171 else
3172 /* Use rx_chainmask from EEPROM. */
3173 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
3174
3175 if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
3176 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
3177
3178 pCap->low_2ghz_chan = 2312;
3179 pCap->high_2ghz_chan = 2732;
3180
3181 pCap->low_5ghz_chan = 4920;
3182 pCap->high_5ghz_chan = 6100;
3183
3184 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3185 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3186 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3187
3188 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3189 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3190 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3191
3192 if (ah->config.ht_enable)
3193 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3194 else
3195 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3196
3197 pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3198 pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3199 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3200 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3201
3202 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3203 pCap->total_queues =
3204 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3205 else
3206 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3207
3208 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3209 pCap->keycache_size =
3210 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3211 else
3212 pCap->keycache_size = AR_KEYTABLE_SIZE;
3213
3214 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3215
3216 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
3217 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1;
3218 else
3219 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3220
3221 if (AR_SREV_9285_10_OR_LATER(ah))
3222 pCap->num_gpio_pins = AR9285_NUM_GPIO;
3223 else if (AR_SREV_9280_10_OR_LATER(ah))
3224 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3225 else
3226 pCap->num_gpio_pins = AR_NUM_GPIO;
3227
3228 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3229 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3230 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3231 } else {
3232 pCap->rts_aggr_limit = (8 * 1024);
3233 }
3234
3235 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3236
3237 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3238 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
3239 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
3240 ah->rfkill_gpio =
3241 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
3242 ah->rfkill_polarity =
3243 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
3244
3245 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3246 }
3247 #endif
3248
3249 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3250
3251 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
3252 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3253 else
3254 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3255
3256 if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
3257 pCap->reg_cap =
3258 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3259 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3260 AR_EEPROM_EEREGCAP_EN_KK_U2 |
3261 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3262 } else {
3263 pCap->reg_cap =
3264 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3265 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3266 }
3267
3268 /* Advertise midband for AR5416 with FCC midband set in eeprom */
3269 if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
3270 AR_SREV_5416(ah))
3271 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3272
3273 pCap->num_antcfg_5ghz =
3274 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
3275 pCap->num_antcfg_2ghz =
3276 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
3277
3278 if (AR_SREV_9280_10_OR_LATER(ah) &&
3279 ath9k_hw_btcoex_supported(ah)) {
3280 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
3281 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
3282
3283 if (AR_SREV_9285(ah)) {
3284 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
3285 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
3286 } else {
3287 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
3288 }
3289 } else {
3290 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
3291 }
3292
3293 return 0;
3294 }
3295
3296 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3297 u32 capability, u32 *result)
3298 {
3299 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3300 switch (type) {
3301 case ATH9K_CAP_CIPHER:
3302 switch (capability) {
3303 case ATH9K_CIPHER_AES_CCM:
3304 case ATH9K_CIPHER_AES_OCB:
3305 case ATH9K_CIPHER_TKIP:
3306 case ATH9K_CIPHER_WEP:
3307 case ATH9K_CIPHER_MIC:
3308 case ATH9K_CIPHER_CLR:
3309 return true;
3310 default:
3311 return false;
3312 }
3313 case ATH9K_CAP_TKIP_MIC:
3314 switch (capability) {
3315 case 0:
3316 return true;
3317 case 1:
3318 return (ah->sta_id1_defaults &
3319 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3320 false;
3321 }
3322 case ATH9K_CAP_TKIP_SPLIT:
3323 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
3324 false : true;
3325 case ATH9K_CAP_DIVERSITY:
3326 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3327 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3328 true : false;
3329 case ATH9K_CAP_MCAST_KEYSRCH:
3330 switch (capability) {
3331 case 0:
3332 return true;
3333 case 1:
3334 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3335 return false;
3336 } else {
3337 return (ah->sta_id1_defaults &
3338 AR_STA_ID1_MCAST_KSRCH) ? true :
3339 false;
3340 }
3341 }
3342 return false;
3343 case ATH9K_CAP_TXPOW:
3344 switch (capability) {
3345 case 0:
3346 return 0;
3347 case 1:
3348 *result = regulatory->power_limit;
3349 return 0;
3350 case 2:
3351 *result = regulatory->max_power_level;
3352 return 0;
3353 case 3:
3354 *result = regulatory->tp_scale;
3355 return 0;
3356 }
3357 return false;
3358 case ATH9K_CAP_DS:
3359 return (AR_SREV_9280_20_OR_LATER(ah) &&
3360 (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
3361 ? false : true;
3362 default:
3363 return false;
3364 }
3365 }
3366 EXPORT_SYMBOL(ath9k_hw_getcapability);
3367
3368 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3369 u32 capability, u32 setting, int *status)
3370 {
3371 u32 v;
3372
3373 switch (type) {
3374 case ATH9K_CAP_TKIP_MIC:
3375 if (setting)
3376 ah->sta_id1_defaults |=
3377 AR_STA_ID1_CRPT_MIC_ENABLE;
3378 else
3379 ah->sta_id1_defaults &=
3380 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3381 return true;
3382 case ATH9K_CAP_DIVERSITY:
3383 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3384 if (setting)
3385 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3386 else
3387 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3388 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3389 return true;
3390 case ATH9K_CAP_MCAST_KEYSRCH:
3391 if (setting)
3392 ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
3393 else
3394 ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
3395 return true;
3396 default:
3397 return false;
3398 }
3399 }
3400 EXPORT_SYMBOL(ath9k_hw_setcapability);
3401
3402 /****************************/
3403 /* GPIO / RFKILL / Antennae */
3404 /****************************/
3405
3406 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
3407 u32 gpio, u32 type)
3408 {
3409 int addr;
3410 u32 gpio_shift, tmp;
3411
3412 if (gpio > 11)
3413 addr = AR_GPIO_OUTPUT_MUX3;
3414 else if (gpio > 5)
3415 addr = AR_GPIO_OUTPUT_MUX2;
3416 else
3417 addr = AR_GPIO_OUTPUT_MUX1;
3418
3419 gpio_shift = (gpio % 6) * 5;
3420
3421 if (AR_SREV_9280_20_OR_LATER(ah)
3422 || (addr != AR_GPIO_OUTPUT_MUX1)) {
3423 REG_RMW(ah, addr, (type << gpio_shift),
3424 (0x1f << gpio_shift));
3425 } else {
3426 tmp = REG_READ(ah, addr);
3427 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3428 tmp &= ~(0x1f << gpio_shift);
3429 tmp |= (type << gpio_shift);
3430 REG_WRITE(ah, addr, tmp);
3431 }
3432 }
3433
3434 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
3435 {
3436 u32 gpio_shift;
3437
3438 BUG_ON(gpio >= ah->caps.num_gpio_pins);
3439
3440 gpio_shift = gpio << 1;
3441
3442 REG_RMW(ah,
3443 AR_GPIO_OE_OUT,
3444 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3445 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3446 }
3447 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
3448
3449 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
3450 {
3451 #define MS_REG_READ(x, y) \
3452 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3453
3454 if (gpio >= ah->caps.num_gpio_pins)
3455 return 0xffffffff;
3456
3457 if (AR_SREV_9287_10_OR_LATER(ah))
3458 return MS_REG_READ(AR9287, gpio) != 0;
3459 else if (AR_SREV_9285_10_OR_LATER(ah))
3460 return MS_REG_READ(AR9285, gpio) != 0;
3461 else if (AR_SREV_9280_10_OR_LATER(ah))
3462 return MS_REG_READ(AR928X, gpio) != 0;
3463 else
3464 return MS_REG_READ(AR, gpio) != 0;
3465 }
3466 EXPORT_SYMBOL(ath9k_hw_gpio_get);
3467
3468 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
3469 u32 ah_signal_type)
3470 {
3471 u32 gpio_shift;
3472
3473 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
3474
3475 gpio_shift = 2 * gpio;
3476
3477 REG_RMW(ah,
3478 AR_GPIO_OE_OUT,
3479 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3480 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3481 }
3482 EXPORT_SYMBOL(ath9k_hw_cfg_output);
3483
3484 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
3485 {
3486 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3487 AR_GPIO_BIT(gpio));
3488 }
3489 EXPORT_SYMBOL(ath9k_hw_set_gpio);
3490
3491 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
3492 {
3493 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3494 }
3495 EXPORT_SYMBOL(ath9k_hw_getdefantenna);
3496
3497 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
3498 {
3499 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3500 }
3501 EXPORT_SYMBOL(ath9k_hw_setantenna);
3502
3503 /*********************/
3504 /* General Operation */
3505 /*********************/
3506
3507 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
3508 {
3509 u32 bits = REG_READ(ah, AR_RX_FILTER);
3510 u32 phybits = REG_READ(ah, AR_PHY_ERR);
3511
3512 if (phybits & AR_PHY_ERR_RADAR)
3513 bits |= ATH9K_RX_FILTER_PHYRADAR;
3514 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3515 bits |= ATH9K_RX_FILTER_PHYERR;
3516
3517 return bits;
3518 }
3519 EXPORT_SYMBOL(ath9k_hw_getrxfilter);
3520
3521 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
3522 {
3523 u32 phybits;
3524
3525 REG_WRITE(ah, AR_RX_FILTER, bits);
3526
3527 phybits = 0;
3528 if (bits & ATH9K_RX_FILTER_PHYRADAR)
3529 phybits |= AR_PHY_ERR_RADAR;
3530 if (bits & ATH9K_RX_FILTER_PHYERR)
3531 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3532 REG_WRITE(ah, AR_PHY_ERR, phybits);
3533
3534 if (phybits)
3535 REG_WRITE(ah, AR_RXCFG,
3536 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3537 else
3538 REG_WRITE(ah, AR_RXCFG,
3539 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3540 }
3541 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
3542
3543 bool ath9k_hw_phy_disable(struct ath_hw *ah)
3544 {
3545 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
3546 return false;
3547
3548 ath9k_hw_init_pll(ah, NULL);
3549 return true;
3550 }
3551 EXPORT_SYMBOL(ath9k_hw_phy_disable);
3552
3553 bool ath9k_hw_disable(struct ath_hw *ah)
3554 {
3555 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3556 return false;
3557
3558 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
3559 return false;
3560
3561 ath9k_hw_init_pll(ah, NULL);
3562 return true;
3563 }
3564 EXPORT_SYMBOL(ath9k_hw_disable);
3565
3566 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
3567 {
3568 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3569 struct ath9k_channel *chan = ah->curchan;
3570 struct ieee80211_channel *channel = chan->chan;
3571
3572 regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
3573
3574 ah->eep_ops->set_txpower(ah, chan,
3575 ath9k_regd_get_ctl(regulatory, chan),
3576 channel->max_antenna_gain * 2,
3577 channel->max_power * 2,
3578 min((u32) MAX_RATE_POWER,
3579 (u32) regulatory->power_limit));
3580 }
3581 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
3582
3583 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
3584 {
3585 memcpy(ath9k_hw_common(ah)->macaddr, mac, ETH_ALEN);
3586 }
3587 EXPORT_SYMBOL(ath9k_hw_setmac);
3588
3589 void ath9k_hw_setopmode(struct ath_hw *ah)
3590 {
3591 ath9k_hw_set_operating_mode(ah, ah->opmode);
3592 }
3593 EXPORT_SYMBOL(ath9k_hw_setopmode);
3594
3595 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
3596 {
3597 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3598 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
3599 }
3600 EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
3601
3602 void ath9k_hw_write_associd(struct ath_hw *ah)
3603 {
3604 struct ath_common *common = ath9k_hw_common(ah);
3605
3606 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
3607 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
3608 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
3609 }
3610 EXPORT_SYMBOL(ath9k_hw_write_associd);
3611
3612 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
3613 {
3614 u64 tsf;
3615
3616 tsf = REG_READ(ah, AR_TSF_U32);
3617 tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
3618
3619 return tsf;
3620 }
3621 EXPORT_SYMBOL(ath9k_hw_gettsf64);
3622
3623 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
3624 {
3625 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
3626 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
3627 }
3628 EXPORT_SYMBOL(ath9k_hw_settsf64);
3629
3630 void ath9k_hw_reset_tsf(struct ath_hw *ah)
3631 {
3632 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
3633 AH_TSF_WRITE_TIMEOUT))
3634 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
3635 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
3636
3637 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3638 }
3639 EXPORT_SYMBOL(ath9k_hw_reset_tsf);
3640
3641 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
3642 {
3643 if (setting)
3644 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
3645 else
3646 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
3647 }
3648 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
3649
3650 /*
3651 * Extend 15-bit time stamp from rx descriptor to
3652 * a full 64-bit TSF using the current h/w TSF.
3653 */
3654 u64 ath9k_hw_extend_tsf(struct ath_hw *ah, u32 rstamp)
3655 {
3656 u64 tsf;
3657
3658 tsf = ath9k_hw_gettsf64(ah);
3659 if ((tsf & 0x7fff) < rstamp)
3660 tsf -= 0x8000;
3661 return (tsf & ~0x7fff) | rstamp;
3662 }
3663 EXPORT_SYMBOL(ath9k_hw_extend_tsf);
3664
3665 void ath9k_hw_set11nmac2040(struct ath_hw *ah)
3666 {
3667 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
3668 u32 macmode;
3669
3670 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
3671 macmode = AR_2040_JOINED_RX_CLEAR;
3672 else
3673 macmode = 0;
3674
3675 REG_WRITE(ah, AR_2040_MODE, macmode);
3676 }
3677
3678 /* HW Generic timers configuration */
3679
3680 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
3681 {
3682 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3683 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3684 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3685 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3686 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3687 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3688 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3689 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3690 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
3691 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
3692 AR_NDP2_TIMER_MODE, 0x0002},
3693 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
3694 AR_NDP2_TIMER_MODE, 0x0004},
3695 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
3696 AR_NDP2_TIMER_MODE, 0x0008},
3697 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
3698 AR_NDP2_TIMER_MODE, 0x0010},
3699 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
3700 AR_NDP2_TIMER_MODE, 0x0020},
3701 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
3702 AR_NDP2_TIMER_MODE, 0x0040},
3703 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
3704 AR_NDP2_TIMER_MODE, 0x0080}
3705 };
3706
3707 /* HW generic timer primitives */
3708
3709 /* compute and clear index of rightmost 1 */
3710 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
3711 {
3712 u32 b;
3713
3714 b = *mask;
3715 b &= (0-b);
3716 *mask &= ~b;
3717 b *= debruijn32;
3718 b >>= 27;
3719
3720 return timer_table->gen_timer_index[b];
3721 }
3722
3723 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
3724 {
3725 return REG_READ(ah, AR_TSF_L32);
3726 }
3727 EXPORT_SYMBOL(ath9k_hw_gettsf32);
3728
3729 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
3730 void (*trigger)(void *),
3731 void (*overflow)(void *),
3732 void *arg,
3733 u8 timer_index)
3734 {
3735 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3736 struct ath_gen_timer *timer;
3737
3738 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
3739
3740 if (timer == NULL) {
3741 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
3742 "Failed to allocate memory"
3743 "for hw timer[%d]\n", timer_index);
3744 return NULL;
3745 }
3746
3747 /* allocate a hardware generic timer slot */
3748 timer_table->timers[timer_index] = timer;
3749 timer->index = timer_index;
3750 timer->trigger = trigger;
3751 timer->overflow = overflow;
3752 timer->arg = arg;
3753
3754 return timer;
3755 }
3756 EXPORT_SYMBOL(ath_gen_timer_alloc);
3757
3758 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
3759 struct ath_gen_timer *timer,
3760 u32 timer_next,
3761 u32 timer_period)
3762 {
3763 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3764 u32 tsf;
3765
3766 BUG_ON(!timer_period);
3767
3768 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
3769
3770 tsf = ath9k_hw_gettsf32(ah);
3771
3772 ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
3773 "curent tsf %x period %x"
3774 "timer_next %x\n", tsf, timer_period, timer_next);
3775
3776 /*
3777 * Pull timer_next forward if the current TSF already passed it
3778 * because of software latency
3779 */
3780 if (timer_next < tsf)
3781 timer_next = tsf + timer_period;
3782
3783 /*
3784 * Program generic timer registers
3785 */
3786 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
3787 timer_next);
3788 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
3789 timer_period);
3790 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3791 gen_tmr_configuration[timer->index].mode_mask);
3792
3793 /* Enable both trigger and thresh interrupt masks */
3794 REG_SET_BIT(ah, AR_IMR_S5,
3795 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3796 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3797 }
3798 EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
3799
3800 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
3801 {
3802 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3803
3804 if ((timer->index < AR_FIRST_NDP_TIMER) ||
3805 (timer->index >= ATH_MAX_GEN_TIMER)) {
3806 return;
3807 }
3808
3809 /* Clear generic timer enable bits. */
3810 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3811 gen_tmr_configuration[timer->index].mode_mask);
3812
3813 /* Disable both trigger and thresh interrupt masks */
3814 REG_CLR_BIT(ah, AR_IMR_S5,
3815 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3816 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3817
3818 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
3819 }
3820 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
3821
3822 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
3823 {
3824 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3825
3826 /* free the hardware generic timer slot */
3827 timer_table->timers[timer->index] = NULL;
3828 kfree(timer);
3829 }
3830 EXPORT_SYMBOL(ath_gen_timer_free);
3831
3832 /*
3833 * Generic Timer Interrupts handling
3834 */
3835 void ath_gen_timer_isr(struct ath_hw *ah)
3836 {
3837 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3838 struct ath_gen_timer *timer;
3839 struct ath_common *common = ath9k_hw_common(ah);
3840 u32 trigger_mask, thresh_mask, index;
3841
3842 /* get hardware generic timer interrupt status */
3843 trigger_mask = ah->intr_gen_timer_trigger;
3844 thresh_mask = ah->intr_gen_timer_thresh;
3845 trigger_mask &= timer_table->timer_mask.val;
3846 thresh_mask &= timer_table->timer_mask.val;
3847
3848 trigger_mask &= ~thresh_mask;
3849
3850 while (thresh_mask) {
3851 index = rightmost_index(timer_table, &thresh_mask);
3852 timer = timer_table->timers[index];
3853 BUG_ON(!timer);
3854 ath_print(common, ATH_DBG_HWTIMER,
3855 "TSF overflow for Gen timer %d\n", index);
3856 timer->overflow(timer->arg);
3857 }
3858
3859 while (trigger_mask) {
3860 index = rightmost_index(timer_table, &trigger_mask);
3861 timer = timer_table->timers[index];
3862 BUG_ON(!timer);
3863 ath_print(common, ATH_DBG_HWTIMER,
3864 "Gen timer[%d] trigger\n", index);
3865 timer->trigger(timer->arg);
3866 }
3867 }
3868 EXPORT_SYMBOL(ath_gen_timer_isr);
3869
3870 static struct {
3871 u32 version;
3872 const char * name;
3873 } ath_mac_bb_names[] = {
3874 /* Devices with external radios */
3875 { AR_SREV_VERSION_5416_PCI, "5416" },
3876 { AR_SREV_VERSION_5416_PCIE, "5418" },
3877 { AR_SREV_VERSION_9100, "9100" },
3878 { AR_SREV_VERSION_9160, "9160" },
3879 /* Single-chip solutions */
3880 { AR_SREV_VERSION_9280, "9280" },
3881 { AR_SREV_VERSION_9285, "9285" },
3882 { AR_SREV_VERSION_9287, "9287" },
3883 { AR_SREV_VERSION_9271, "9271" },
3884 };
3885
3886 /* For devices with external radios */
3887 static struct {
3888 u16 version;
3889 const char * name;
3890 } ath_rf_names[] = {
3891 { 0, "5133" },
3892 { AR_RAD5133_SREV_MAJOR, "5133" },
3893 { AR_RAD5122_SREV_MAJOR, "5122" },
3894 { AR_RAD2133_SREV_MAJOR, "2133" },
3895 { AR_RAD2122_SREV_MAJOR, "2122" }
3896 };
3897
3898 /*
3899 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3900 */
3901 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
3902 {
3903 int i;
3904
3905 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3906 if (ath_mac_bb_names[i].version == mac_bb_version) {
3907 return ath_mac_bb_names[i].name;
3908 }
3909 }
3910
3911 return "????";
3912 }
3913
3914 /*
3915 * Return the RF name. "????" is returned if the RF is unknown.
3916 * Used for devices with external radios.
3917 */
3918 static const char *ath9k_hw_rf_name(u16 rf_version)
3919 {
3920 int i;
3921
3922 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3923 if (ath_rf_names[i].version == rf_version) {
3924 return ath_rf_names[i].name;
3925 }
3926 }
3927
3928 return "????";
3929 }
3930
3931 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
3932 {
3933 int used;
3934
3935 /* chipsets >= AR9280 are single-chip */
3936 if (AR_SREV_9280_10_OR_LATER(ah)) {
3937 used = snprintf(hw_name, len,
3938 "Atheros AR%s Rev:%x",
3939 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3940 ah->hw_version.macRev);
3941 }
3942 else {
3943 used = snprintf(hw_name, len,
3944 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3945 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3946 ah->hw_version.macRev,
3947 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
3948 AR_RADIO_SREV_MAJOR)),
3949 ah->hw_version.phyRev);
3950 }
3951
3952 hw_name[used] = '\0';
3953 }
3954 EXPORT_SYMBOL(ath9k_hw_name);
Linux kernel - Deliverables
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