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ath9k: Load SW filtered NF values and start NF cal during full reset for AR9003
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / hw.c
1 /*
2 * Copyright (c) 2008-2010 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/io.h>
18 #include <asm/unaligned.h>
19
20 #include "hw.h"
21 #include "hw-ops.h"
22 #include "rc.h"
23
24 #define ATH9K_CLOCK_RATE_CCK 22
25 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
26 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
27
28 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
29
30 MODULE_AUTHOR("Atheros Communications");
31 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
32 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
33 MODULE_LICENSE("Dual BSD/GPL");
34
35 static int __init ath9k_init(void)
36 {
37 return 0;
38 }
39 module_init(ath9k_init);
40
41 static void __exit ath9k_exit(void)
42 {
43 return;
44 }
45 module_exit(ath9k_exit);
46
47 /* Private hardware callbacks */
48
49 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
50 {
51 ath9k_hw_private_ops(ah)->init_cal_settings(ah);
52 }
53
54 static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
55 {
56 ath9k_hw_private_ops(ah)->init_mode_regs(ah);
57 }
58
59 static bool ath9k_hw_macversion_supported(struct ath_hw *ah)
60 {
61 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
62
63 return priv_ops->macversion_supported(ah->hw_version.macVersion);
64 }
65
66 static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
67 struct ath9k_channel *chan)
68 {
69 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
70 }
71
72 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
73 {
74 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
75 return;
76
77 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
78 }
79
80 /********************/
81 /* Helper Functions */
82 /********************/
83
84 static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
85 {
86 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
87
88 if (!ah->curchan) /* should really check for CCK instead */
89 return usecs *ATH9K_CLOCK_RATE_CCK;
90 if (conf->channel->band == IEEE80211_BAND_2GHZ)
91 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
92 return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
93 }
94
95 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
96 {
97 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
98
99 if (conf_is_ht40(conf))
100 return ath9k_hw_mac_clks(ah, usecs) * 2;
101 else
102 return ath9k_hw_mac_clks(ah, usecs);
103 }
104
105 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
106 {
107 int i;
108
109 BUG_ON(timeout < AH_TIME_QUANTUM);
110
111 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
112 if ((REG_READ(ah, reg) & mask) == val)
113 return true;
114
115 udelay(AH_TIME_QUANTUM);
116 }
117
118 ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
119 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
120 timeout, reg, REG_READ(ah, reg), mask, val);
121
122 return false;
123 }
124 EXPORT_SYMBOL(ath9k_hw_wait);
125
126 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
127 {
128 u32 retval;
129 int i;
130
131 for (i = 0, retval = 0; i < n; i++) {
132 retval = (retval << 1) | (val & 1);
133 val >>= 1;
134 }
135 return retval;
136 }
137
138 bool ath9k_get_channel_edges(struct ath_hw *ah,
139 u16 flags, u16 *low,
140 u16 *high)
141 {
142 struct ath9k_hw_capabilities *pCap = &ah->caps;
143
144 if (flags & CHANNEL_5GHZ) {
145 *low = pCap->low_5ghz_chan;
146 *high = pCap->high_5ghz_chan;
147 return true;
148 }
149 if ((flags & CHANNEL_2GHZ)) {
150 *low = pCap->low_2ghz_chan;
151 *high = pCap->high_2ghz_chan;
152 return true;
153 }
154 return false;
155 }
156
157 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
158 u8 phy, int kbps,
159 u32 frameLen, u16 rateix,
160 bool shortPreamble)
161 {
162 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
163
164 if (kbps == 0)
165 return 0;
166
167 switch (phy) {
168 case WLAN_RC_PHY_CCK:
169 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
170 if (shortPreamble)
171 phyTime >>= 1;
172 numBits = frameLen << 3;
173 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
174 break;
175 case WLAN_RC_PHY_OFDM:
176 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
177 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
178 numBits = OFDM_PLCP_BITS + (frameLen << 3);
179 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
180 txTime = OFDM_SIFS_TIME_QUARTER
181 + OFDM_PREAMBLE_TIME_QUARTER
182 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
183 } else if (ah->curchan &&
184 IS_CHAN_HALF_RATE(ah->curchan)) {
185 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
186 numBits = OFDM_PLCP_BITS + (frameLen << 3);
187 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
188 txTime = OFDM_SIFS_TIME_HALF +
189 OFDM_PREAMBLE_TIME_HALF
190 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
191 } else {
192 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
193 numBits = OFDM_PLCP_BITS + (frameLen << 3);
194 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
195 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
196 + (numSymbols * OFDM_SYMBOL_TIME);
197 }
198 break;
199 default:
200 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
201 "Unknown phy %u (rate ix %u)\n", phy, rateix);
202 txTime = 0;
203 break;
204 }
205
206 return txTime;
207 }
208 EXPORT_SYMBOL(ath9k_hw_computetxtime);
209
210 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
211 struct ath9k_channel *chan,
212 struct chan_centers *centers)
213 {
214 int8_t extoff;
215
216 if (!IS_CHAN_HT40(chan)) {
217 centers->ctl_center = centers->ext_center =
218 centers->synth_center = chan->channel;
219 return;
220 }
221
222 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
223 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
224 centers->synth_center =
225 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
226 extoff = 1;
227 } else {
228 centers->synth_center =
229 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
230 extoff = -1;
231 }
232
233 centers->ctl_center =
234 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
235 /* 25 MHz spacing is supported by hw but not on upper layers */
236 centers->ext_center =
237 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
238 }
239
240 /******************/
241 /* Chip Revisions */
242 /******************/
243
244 static void ath9k_hw_read_revisions(struct ath_hw *ah)
245 {
246 u32 val;
247
248 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
249
250 if (val == 0xFF) {
251 val = REG_READ(ah, AR_SREV);
252 ah->hw_version.macVersion =
253 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
254 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
255 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
256 } else {
257 if (!AR_SREV_9100(ah))
258 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
259
260 ah->hw_version.macRev = val & AR_SREV_REVISION;
261
262 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
263 ah->is_pciexpress = true;
264 }
265 }
266
267 /************************************/
268 /* HW Attach, Detach, Init Routines */
269 /************************************/
270
271 static void ath9k_hw_disablepcie(struct ath_hw *ah)
272 {
273 if (AR_SREV_9100(ah))
274 return;
275
276 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
277 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
278 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
279 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
280 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
281 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
282 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
283 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
284 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
285
286 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
287 }
288
289 /* This should work for all families including legacy */
290 static bool ath9k_hw_chip_test(struct ath_hw *ah)
291 {
292 struct ath_common *common = ath9k_hw_common(ah);
293 u32 regAddr[2] = { AR_STA_ID0 };
294 u32 regHold[2];
295 u32 patternData[4] = { 0x55555555,
296 0xaaaaaaaa,
297 0x66666666,
298 0x99999999 };
299 int i, j, loop_max;
300
301 if (!AR_SREV_9300_20_OR_LATER(ah)) {
302 loop_max = 2;
303 regAddr[1] = AR_PHY_BASE + (8 << 2);
304 } else
305 loop_max = 1;
306
307 for (i = 0; i < loop_max; i++) {
308 u32 addr = regAddr[i];
309 u32 wrData, rdData;
310
311 regHold[i] = REG_READ(ah, addr);
312 for (j = 0; j < 0x100; j++) {
313 wrData = (j << 16) | j;
314 REG_WRITE(ah, addr, wrData);
315 rdData = REG_READ(ah, addr);
316 if (rdData != wrData) {
317 ath_print(common, ATH_DBG_FATAL,
318 "address test failed "
319 "addr: 0x%08x - wr:0x%08x != "
320 "rd:0x%08x\n",
321 addr, wrData, rdData);
322 return false;
323 }
324 }
325 for (j = 0; j < 4; j++) {
326 wrData = patternData[j];
327 REG_WRITE(ah, addr, wrData);
328 rdData = REG_READ(ah, addr);
329 if (wrData != rdData) {
330 ath_print(common, ATH_DBG_FATAL,
331 "address test failed "
332 "addr: 0x%08x - wr:0x%08x != "
333 "rd:0x%08x\n",
334 addr, wrData, rdData);
335 return false;
336 }
337 }
338 REG_WRITE(ah, regAddr[i], regHold[i]);
339 }
340 udelay(100);
341
342 return true;
343 }
344
345 static void ath9k_hw_init_config(struct ath_hw *ah)
346 {
347 int i;
348
349 ah->config.dma_beacon_response_time = 2;
350 ah->config.sw_beacon_response_time = 10;
351 ah->config.additional_swba_backoff = 0;
352 ah->config.ack_6mb = 0x0;
353 ah->config.cwm_ignore_extcca = 0;
354 ah->config.pcie_powersave_enable = 0;
355 ah->config.pcie_clock_req = 0;
356 ah->config.pcie_waen = 0;
357 ah->config.analog_shiftreg = 1;
358 ah->config.ofdm_trig_low = 200;
359 ah->config.ofdm_trig_high = 500;
360 ah->config.cck_trig_high = 200;
361 ah->config.cck_trig_low = 100;
362
363 /*
364 * For now ANI is disabled for AR9003, it is still
365 * being tested.
366 */
367 if (!AR_SREV_9300_20_OR_LATER(ah))
368 ah->config.enable_ani = 1;
369
370 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
371 ah->config.spurchans[i][0] = AR_NO_SPUR;
372 ah->config.spurchans[i][1] = AR_NO_SPUR;
373 }
374
375 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
376 ah->config.ht_enable = 1;
377 else
378 ah->config.ht_enable = 0;
379
380 ah->config.rx_intr_mitigation = true;
381
382 /*
383 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
384 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
385 * This means we use it for all AR5416 devices, and the few
386 * minor PCI AR9280 devices out there.
387 *
388 * Serialization is required because these devices do not handle
389 * well the case of two concurrent reads/writes due to the latency
390 * involved. During one read/write another read/write can be issued
391 * on another CPU while the previous read/write may still be working
392 * on our hardware, if we hit this case the hardware poops in a loop.
393 * We prevent this by serializing reads and writes.
394 *
395 * This issue is not present on PCI-Express devices or pre-AR5416
396 * devices (legacy, 802.11abg).
397 */
398 if (num_possible_cpus() > 1)
399 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
400 }
401
402 static void ath9k_hw_init_defaults(struct ath_hw *ah)
403 {
404 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
405
406 regulatory->country_code = CTRY_DEFAULT;
407 regulatory->power_limit = MAX_RATE_POWER;
408 regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
409
410 ah->hw_version.magic = AR5416_MAGIC;
411 ah->hw_version.subvendorid = 0;
412
413 ah->ah_flags = 0;
414 if (!AR_SREV_9100(ah))
415 ah->ah_flags = AH_USE_EEPROM;
416
417 ah->atim_window = 0;
418 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
419 ah->beacon_interval = 100;
420 ah->enable_32kHz_clock = DONT_USE_32KHZ;
421 ah->slottime = (u32) -1;
422 ah->globaltxtimeout = (u32) -1;
423 ah->power_mode = ATH9K_PM_UNDEFINED;
424 }
425
426 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
427 {
428 struct ath_common *common = ath9k_hw_common(ah);
429 u32 sum;
430 int i;
431 u16 eeval;
432 u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
433
434 sum = 0;
435 for (i = 0; i < 3; i++) {
436 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
437 sum += eeval;
438 common->macaddr[2 * i] = eeval >> 8;
439 common->macaddr[2 * i + 1] = eeval & 0xff;
440 }
441 if (sum == 0 || sum == 0xffff * 3)
442 return -EADDRNOTAVAIL;
443
444 return 0;
445 }
446
447 static int ath9k_hw_post_init(struct ath_hw *ah)
448 {
449 int ecode;
450
451 if (!AR_SREV_9271(ah)) {
452 if (!ath9k_hw_chip_test(ah))
453 return -ENODEV;
454 }
455
456 if (!AR_SREV_9300_20_OR_LATER(ah)) {
457 ecode = ar9002_hw_rf_claim(ah);
458 if (ecode != 0)
459 return ecode;
460 }
461
462 ecode = ath9k_hw_eeprom_init(ah);
463 if (ecode != 0)
464 return ecode;
465
466 ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
467 "Eeprom VER: %d, REV: %d\n",
468 ah->eep_ops->get_eeprom_ver(ah),
469 ah->eep_ops->get_eeprom_rev(ah));
470
471 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
472 if (ecode) {
473 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
474 "Failed allocating banks for "
475 "external radio\n");
476 return ecode;
477 }
478
479 if (!AR_SREV_9100(ah)) {
480 ath9k_hw_ani_setup(ah);
481 ath9k_hw_ani_init(ah);
482 }
483
484 return 0;
485 }
486
487 static void ath9k_hw_attach_ops(struct ath_hw *ah)
488 {
489 if (AR_SREV_9300_20_OR_LATER(ah))
490 ar9003_hw_attach_ops(ah);
491 else
492 ar9002_hw_attach_ops(ah);
493 }
494
495 /* Called for all hardware families */
496 static int __ath9k_hw_init(struct ath_hw *ah)
497 {
498 struct ath_common *common = ath9k_hw_common(ah);
499 int r = 0;
500
501 if (ah->hw_version.devid == AR5416_AR9100_DEVID)
502 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
503
504 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
505 ath_print(common, ATH_DBG_FATAL,
506 "Couldn't reset chip\n");
507 return -EIO;
508 }
509
510 ath9k_hw_init_defaults(ah);
511 ath9k_hw_init_config(ah);
512
513 ath9k_hw_attach_ops(ah);
514
515 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
516 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
517 return -EIO;
518 }
519
520 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
521 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
522 (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
523 ah->config.serialize_regmode =
524 SER_REG_MODE_ON;
525 } else {
526 ah->config.serialize_regmode =
527 SER_REG_MODE_OFF;
528 }
529 }
530
531 ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
532 ah->config.serialize_regmode);
533
534 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
535 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
536 else
537 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
538
539 if (!ath9k_hw_macversion_supported(ah)) {
540 ath_print(common, ATH_DBG_FATAL,
541 "Mac Chip Rev 0x%02x.%x is not supported by "
542 "this driver\n", ah->hw_version.macVersion,
543 ah->hw_version.macRev);
544 return -EOPNOTSUPP;
545 }
546
547 if (AR_SREV_9271(ah) || AR_SREV_9100(ah))
548 ah->is_pciexpress = false;
549
550 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
551 ath9k_hw_init_cal_settings(ah);
552
553 ah->ani_function = ATH9K_ANI_ALL;
554 if (AR_SREV_9280_10_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
555 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
556
557 ath9k_hw_init_mode_regs(ah);
558
559 if (ah->is_pciexpress)
560 ath9k_hw_configpcipowersave(ah, 0, 0);
561 else
562 ath9k_hw_disablepcie(ah);
563
564 if (!AR_SREV_9300_20_OR_LATER(ah))
565 ar9002_hw_cck_chan14_spread(ah);
566
567 r = ath9k_hw_post_init(ah);
568 if (r)
569 return r;
570
571 ath9k_hw_init_mode_gain_regs(ah);
572 r = ath9k_hw_fill_cap_info(ah);
573 if (r)
574 return r;
575
576 r = ath9k_hw_init_macaddr(ah);
577 if (r) {
578 ath_print(common, ATH_DBG_FATAL,
579 "Failed to initialize MAC address\n");
580 return r;
581 }
582
583 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
584 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
585 else
586 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
587
588 if (AR_SREV_9300_20_OR_LATER(ah))
589 ar9003_hw_set_nf_limits(ah);
590
591 ath9k_init_nfcal_hist_buffer(ah);
592
593 common->state = ATH_HW_INITIALIZED;
594
595 return 0;
596 }
597
598 int ath9k_hw_init(struct ath_hw *ah)
599 {
600 int ret;
601 struct ath_common *common = ath9k_hw_common(ah);
602
603 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
604 switch (ah->hw_version.devid) {
605 case AR5416_DEVID_PCI:
606 case AR5416_DEVID_PCIE:
607 case AR5416_AR9100_DEVID:
608 case AR9160_DEVID_PCI:
609 case AR9280_DEVID_PCI:
610 case AR9280_DEVID_PCIE:
611 case AR9285_DEVID_PCIE:
612 case AR9287_DEVID_PCI:
613 case AR9287_DEVID_PCIE:
614 case AR2427_DEVID_PCIE:
615 case AR9300_DEVID_PCIE:
616 break;
617 default:
618 if (common->bus_ops->ath_bus_type == ATH_USB)
619 break;
620 ath_print(common, ATH_DBG_FATAL,
621 "Hardware device ID 0x%04x not supported\n",
622 ah->hw_version.devid);
623 return -EOPNOTSUPP;
624 }
625
626 ret = __ath9k_hw_init(ah);
627 if (ret) {
628 ath_print(common, ATH_DBG_FATAL,
629 "Unable to initialize hardware; "
630 "initialization status: %d\n", ret);
631 return ret;
632 }
633
634 return 0;
635 }
636 EXPORT_SYMBOL(ath9k_hw_init);
637
638 static void ath9k_hw_init_qos(struct ath_hw *ah)
639 {
640 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
641 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
642
643 REG_WRITE(ah, AR_QOS_NO_ACK,
644 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
645 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
646 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
647
648 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
649 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
650 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
651 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
652 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
653 }
654
655 static void ath9k_hw_init_pll(struct ath_hw *ah,
656 struct ath9k_channel *chan)
657 {
658 u32 pll = ath9k_hw_compute_pll_control(ah, chan);
659
660 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
661
662 /* Switch the core clock for ar9271 to 117Mhz */
663 if (AR_SREV_9271(ah)) {
664 udelay(500);
665 REG_WRITE(ah, 0x50040, 0x304);
666 }
667
668 udelay(RTC_PLL_SETTLE_DELAY);
669
670 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
671 }
672
673 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
674 enum nl80211_iftype opmode)
675 {
676 u32 imr_reg = AR_IMR_TXERR |
677 AR_IMR_TXURN |
678 AR_IMR_RXERR |
679 AR_IMR_RXORN |
680 AR_IMR_BCNMISC;
681
682 if (AR_SREV_9300_20_OR_LATER(ah)) {
683 imr_reg |= AR_IMR_RXOK_HP;
684 if (ah->config.rx_intr_mitigation)
685 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
686 else
687 imr_reg |= AR_IMR_RXOK_LP;
688
689 } else {
690 if (ah->config.rx_intr_mitigation)
691 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
692 else
693 imr_reg |= AR_IMR_RXOK;
694 }
695
696 if (ah->config.tx_intr_mitigation)
697 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
698 else
699 imr_reg |= AR_IMR_TXOK;
700
701 if (opmode == NL80211_IFTYPE_AP)
702 imr_reg |= AR_IMR_MIB;
703
704 REG_WRITE(ah, AR_IMR, imr_reg);
705 ah->imrs2_reg |= AR_IMR_S2_GTT;
706 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
707
708 if (!AR_SREV_9100(ah)) {
709 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
710 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
711 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
712 }
713
714 if (AR_SREV_9300_20_OR_LATER(ah)) {
715 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
716 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
717 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
718 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
719 }
720 }
721
722 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
723 {
724 u32 val = ath9k_hw_mac_to_clks(ah, us);
725 val = min(val, (u32) 0xFFFF);
726 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
727 }
728
729 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
730 {
731 u32 val = ath9k_hw_mac_to_clks(ah, us);
732 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
733 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
734 }
735
736 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
737 {
738 u32 val = ath9k_hw_mac_to_clks(ah, us);
739 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
740 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
741 }
742
743 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
744 {
745 if (tu > 0xFFFF) {
746 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
747 "bad global tx timeout %u\n", tu);
748 ah->globaltxtimeout = (u32) -1;
749 return false;
750 } else {
751 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
752 ah->globaltxtimeout = tu;
753 return true;
754 }
755 }
756
757 void ath9k_hw_init_global_settings(struct ath_hw *ah)
758 {
759 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
760 int acktimeout;
761 int slottime;
762 int sifstime;
763
764 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
765 ah->misc_mode);
766
767 if (ah->misc_mode != 0)
768 REG_WRITE(ah, AR_PCU_MISC,
769 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
770
771 if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
772 sifstime = 16;
773 else
774 sifstime = 10;
775
776 /* As defined by IEEE 802.11-2007 17.3.8.6 */
777 slottime = ah->slottime + 3 * ah->coverage_class;
778 acktimeout = slottime + sifstime;
779
780 /*
781 * Workaround for early ACK timeouts, add an offset to match the
782 * initval's 64us ack timeout value.
783 * This was initially only meant to work around an issue with delayed
784 * BA frames in some implementations, but it has been found to fix ACK
785 * timeout issues in other cases as well.
786 */
787 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
788 acktimeout += 64 - sifstime - ah->slottime;
789
790 ath9k_hw_setslottime(ah, slottime);
791 ath9k_hw_set_ack_timeout(ah, acktimeout);
792 ath9k_hw_set_cts_timeout(ah, acktimeout);
793 if (ah->globaltxtimeout != (u32) -1)
794 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
795 }
796 EXPORT_SYMBOL(ath9k_hw_init_global_settings);
797
798 void ath9k_hw_deinit(struct ath_hw *ah)
799 {
800 struct ath_common *common = ath9k_hw_common(ah);
801
802 if (common->state < ATH_HW_INITIALIZED)
803 goto free_hw;
804
805 if (!AR_SREV_9100(ah))
806 ath9k_hw_ani_disable(ah);
807
808 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
809
810 free_hw:
811 ath9k_hw_rf_free_ext_banks(ah);
812 }
813 EXPORT_SYMBOL(ath9k_hw_deinit);
814
815 /*******/
816 /* INI */
817 /*******/
818
819 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
820 {
821 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
822
823 if (IS_CHAN_B(chan))
824 ctl |= CTL_11B;
825 else if (IS_CHAN_G(chan))
826 ctl |= CTL_11G;
827 else
828 ctl |= CTL_11A;
829
830 return ctl;
831 }
832
833 /****************************************/
834 /* Reset and Channel Switching Routines */
835 /****************************************/
836
837 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
838 {
839 struct ath_common *common = ath9k_hw_common(ah);
840 u32 regval;
841
842 /*
843 * set AHB_MODE not to do cacheline prefetches
844 */
845 if (!AR_SREV_9300_20_OR_LATER(ah)) {
846 regval = REG_READ(ah, AR_AHB_MODE);
847 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
848 }
849
850 /*
851 * let mac dma reads be in 128 byte chunks
852 */
853 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
854 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
855
856 /*
857 * Restore TX Trigger Level to its pre-reset value.
858 * The initial value depends on whether aggregation is enabled, and is
859 * adjusted whenever underruns are detected.
860 */
861 if (!AR_SREV_9300_20_OR_LATER(ah))
862 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
863
864 /*
865 * let mac dma writes be in 128 byte chunks
866 */
867 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
868 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
869
870 /*
871 * Setup receive FIFO threshold to hold off TX activities
872 */
873 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
874
875 if (AR_SREV_9300_20_OR_LATER(ah)) {
876 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
877 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
878
879 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
880 ah->caps.rx_status_len);
881 }
882
883 /*
884 * reduce the number of usable entries in PCU TXBUF to avoid
885 * wrap around issues.
886 */
887 if (AR_SREV_9285(ah)) {
888 /* For AR9285 the number of Fifos are reduced to half.
889 * So set the usable tx buf size also to half to
890 * avoid data/delimiter underruns
891 */
892 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
893 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
894 } else if (!AR_SREV_9271(ah)) {
895 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
896 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
897 }
898 }
899
900 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
901 {
902 u32 val;
903
904 val = REG_READ(ah, AR_STA_ID1);
905 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
906 switch (opmode) {
907 case NL80211_IFTYPE_AP:
908 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
909 | AR_STA_ID1_KSRCH_MODE);
910 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
911 break;
912 case NL80211_IFTYPE_ADHOC:
913 case NL80211_IFTYPE_MESH_POINT:
914 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
915 | AR_STA_ID1_KSRCH_MODE);
916 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
917 break;
918 case NL80211_IFTYPE_STATION:
919 case NL80211_IFTYPE_MONITOR:
920 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
921 break;
922 }
923 }
924
925 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
926 u32 *coef_mantissa, u32 *coef_exponent)
927 {
928 u32 coef_exp, coef_man;
929
930 for (coef_exp = 31; coef_exp > 0; coef_exp--)
931 if ((coef_scaled >> coef_exp) & 0x1)
932 break;
933
934 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
935
936 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
937
938 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
939 *coef_exponent = coef_exp - 16;
940 }
941
942 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
943 {
944 u32 rst_flags;
945 u32 tmpReg;
946
947 if (AR_SREV_9100(ah)) {
948 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
949 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
950 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
951 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
952 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
953 }
954
955 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
956 AR_RTC_FORCE_WAKE_ON_INT);
957
958 if (AR_SREV_9100(ah)) {
959 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
960 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
961 } else {
962 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
963 if (tmpReg &
964 (AR_INTR_SYNC_LOCAL_TIMEOUT |
965 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
966 u32 val;
967 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
968
969 val = AR_RC_HOSTIF;
970 if (!AR_SREV_9300_20_OR_LATER(ah))
971 val |= AR_RC_AHB;
972 REG_WRITE(ah, AR_RC, val);
973
974 } else if (!AR_SREV_9300_20_OR_LATER(ah))
975 REG_WRITE(ah, AR_RC, AR_RC_AHB);
976
977 rst_flags = AR_RTC_RC_MAC_WARM;
978 if (type == ATH9K_RESET_COLD)
979 rst_flags |= AR_RTC_RC_MAC_COLD;
980 }
981
982 REG_WRITE(ah, AR_RTC_RC, rst_flags);
983 udelay(50);
984
985 REG_WRITE(ah, AR_RTC_RC, 0);
986 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
987 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
988 "RTC stuck in MAC reset\n");
989 return false;
990 }
991
992 if (!AR_SREV_9100(ah))
993 REG_WRITE(ah, AR_RC, 0);
994
995 if (AR_SREV_9100(ah))
996 udelay(50);
997
998 return true;
999 }
1000
1001 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1002 {
1003 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1004 AR_RTC_FORCE_WAKE_ON_INT);
1005
1006 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1007 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1008
1009 REG_WRITE(ah, AR_RTC_RESET, 0);
1010
1011 if (!AR_SREV_9300_20_OR_LATER(ah))
1012 udelay(2);
1013
1014 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1015 REG_WRITE(ah, AR_RC, 0);
1016
1017 REG_WRITE(ah, AR_RTC_RESET, 1);
1018
1019 if (!ath9k_hw_wait(ah,
1020 AR_RTC_STATUS,
1021 AR_RTC_STATUS_M,
1022 AR_RTC_STATUS_ON,
1023 AH_WAIT_TIMEOUT)) {
1024 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1025 "RTC not waking up\n");
1026 return false;
1027 }
1028
1029 ath9k_hw_read_revisions(ah);
1030
1031 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1032 }
1033
1034 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1035 {
1036 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1037 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1038
1039 switch (type) {
1040 case ATH9K_RESET_POWER_ON:
1041 return ath9k_hw_set_reset_power_on(ah);
1042 case ATH9K_RESET_WARM:
1043 case ATH9K_RESET_COLD:
1044 return ath9k_hw_set_reset(ah, type);
1045 default:
1046 return false;
1047 }
1048 }
1049
1050 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1051 struct ath9k_channel *chan)
1052 {
1053 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
1054 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1055 return false;
1056 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1057 return false;
1058
1059 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1060 return false;
1061
1062 ah->chip_fullsleep = false;
1063 ath9k_hw_init_pll(ah, chan);
1064 ath9k_hw_set_rfmode(ah, chan);
1065
1066 return true;
1067 }
1068
1069 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1070 struct ath9k_channel *chan)
1071 {
1072 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1073 struct ath_common *common = ath9k_hw_common(ah);
1074 struct ieee80211_channel *channel = chan->chan;
1075 u32 qnum;
1076 int r;
1077
1078 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1079 if (ath9k_hw_numtxpending(ah, qnum)) {
1080 ath_print(common, ATH_DBG_QUEUE,
1081 "Transmit frames pending on "
1082 "queue %d\n", qnum);
1083 return false;
1084 }
1085 }
1086
1087 if (!ath9k_hw_rfbus_req(ah)) {
1088 ath_print(common, ATH_DBG_FATAL,
1089 "Could not kill baseband RX\n");
1090 return false;
1091 }
1092
1093 ath9k_hw_set_channel_regs(ah, chan);
1094
1095 r = ath9k_hw_rf_set_freq(ah, chan);
1096 if (r) {
1097 ath_print(common, ATH_DBG_FATAL,
1098 "Failed to set channel\n");
1099 return false;
1100 }
1101
1102 ah->eep_ops->set_txpower(ah, chan,
1103 ath9k_regd_get_ctl(regulatory, chan),
1104 channel->max_antenna_gain * 2,
1105 channel->max_power * 2,
1106 min((u32) MAX_RATE_POWER,
1107 (u32) regulatory->power_limit));
1108
1109 ath9k_hw_rfbus_done(ah);
1110
1111 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1112 ath9k_hw_set_delta_slope(ah, chan);
1113
1114 ath9k_hw_spur_mitigate_freq(ah, chan);
1115
1116 if (!chan->oneTimeCalsDone)
1117 chan->oneTimeCalsDone = true;
1118
1119 return true;
1120 }
1121
1122 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1123 bool bChannelChange)
1124 {
1125 struct ath_common *common = ath9k_hw_common(ah);
1126 u32 saveLedState;
1127 struct ath9k_channel *curchan = ah->curchan;
1128 u32 saveDefAntenna;
1129 u32 macStaId1;
1130 u64 tsf = 0;
1131 int i, r;
1132
1133 ah->txchainmask = common->tx_chainmask;
1134 ah->rxchainmask = common->rx_chainmask;
1135
1136 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1137 return -EIO;
1138
1139 if (curchan && !ah->chip_fullsleep)
1140 ath9k_hw_getnf(ah, curchan);
1141
1142 if (bChannelChange &&
1143 (ah->chip_fullsleep != true) &&
1144 (ah->curchan != NULL) &&
1145 (chan->channel != ah->curchan->channel) &&
1146 ((chan->channelFlags & CHANNEL_ALL) ==
1147 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
1148 !(AR_SREV_9280(ah) || IS_CHAN_A_5MHZ_SPACED(chan) ||
1149 IS_CHAN_A_5MHZ_SPACED(ah->curchan))) {
1150
1151 if (ath9k_hw_channel_change(ah, chan)) {
1152 ath9k_hw_loadnf(ah, ah->curchan);
1153 ath9k_hw_start_nfcal(ah);
1154 return 0;
1155 }
1156 }
1157
1158 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1159 if (saveDefAntenna == 0)
1160 saveDefAntenna = 1;
1161
1162 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1163
1164 /* For chips on which RTC reset is done, save TSF before it gets cleared */
1165 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1166 tsf = ath9k_hw_gettsf64(ah);
1167
1168 saveLedState = REG_READ(ah, AR_CFG_LED) &
1169 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1170 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1171
1172 ath9k_hw_mark_phy_inactive(ah);
1173
1174 /* Only required on the first reset */
1175 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1176 REG_WRITE(ah,
1177 AR9271_RESET_POWER_DOWN_CONTROL,
1178 AR9271_RADIO_RF_RST);
1179 udelay(50);
1180 }
1181
1182 if (!ath9k_hw_chip_reset(ah, chan)) {
1183 ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n");
1184 return -EINVAL;
1185 }
1186
1187 /* Only required on the first reset */
1188 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1189 ah->htc_reset_init = false;
1190 REG_WRITE(ah,
1191 AR9271_RESET_POWER_DOWN_CONTROL,
1192 AR9271_GATE_MAC_CTL);
1193 udelay(50);
1194 }
1195
1196 /* Restore TSF */
1197 if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1198 ath9k_hw_settsf64(ah, tsf);
1199
1200 if (AR_SREV_9280_10_OR_LATER(ah))
1201 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1202
1203 r = ath9k_hw_process_ini(ah, chan);
1204 if (r)
1205 return r;
1206
1207 /* Setup MFP options for CCMP */
1208 if (AR_SREV_9280_20_OR_LATER(ah)) {
1209 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1210 * frames when constructing CCMP AAD. */
1211 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1212 0xc7ff);
1213 ah->sw_mgmt_crypto = false;
1214 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1215 /* Disable hardware crypto for management frames */
1216 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1217 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1218 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1219 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1220 ah->sw_mgmt_crypto = true;
1221 } else
1222 ah->sw_mgmt_crypto = true;
1223
1224 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1225 ath9k_hw_set_delta_slope(ah, chan);
1226
1227 ath9k_hw_spur_mitigate_freq(ah, chan);
1228 ah->eep_ops->set_board_values(ah, chan);
1229
1230 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
1231 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
1232 | macStaId1
1233 | AR_STA_ID1_RTS_USE_DEF
1234 | (ah->config.
1235 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
1236 | ah->sta_id1_defaults);
1237 ath9k_hw_set_operating_mode(ah, ah->opmode);
1238
1239 ath_hw_setbssidmask(common);
1240
1241 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1242
1243 ath9k_hw_write_associd(ah);
1244
1245 REG_WRITE(ah, AR_ISR, ~0);
1246
1247 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1248
1249 r = ath9k_hw_rf_set_freq(ah, chan);
1250 if (r)
1251 return r;
1252
1253 for (i = 0; i < AR_NUM_DCU; i++)
1254 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1255
1256 ah->intr_txqs = 0;
1257 for (i = 0; i < ah->caps.total_queues; i++)
1258 ath9k_hw_resettxqueue(ah, i);
1259
1260 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
1261 ath9k_hw_init_qos(ah);
1262
1263 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1264 ath9k_enable_rfkill(ah);
1265
1266 ath9k_hw_init_global_settings(ah);
1267
1268 if (!AR_SREV_9300_20_OR_LATER(ah)) {
1269 ar9002_hw_enable_async_fifo(ah);
1270 ar9002_hw_enable_wep_aggregation(ah);
1271 }
1272
1273 REG_WRITE(ah, AR_STA_ID1,
1274 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
1275
1276 ath9k_hw_set_dma(ah);
1277
1278 REG_WRITE(ah, AR_OBS, 8);
1279
1280 if (ah->config.rx_intr_mitigation) {
1281 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
1282 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
1283 }
1284
1285 if (ah->config.tx_intr_mitigation) {
1286 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1287 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1288 }
1289
1290 ath9k_hw_init_bb(ah, chan);
1291
1292 if (!ath9k_hw_init_cal(ah, chan))
1293 return -EIO;
1294
1295 ath9k_hw_restore_chainmask(ah);
1296 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1297
1298 /*
1299 * For big endian systems turn on swapping for descriptors
1300 */
1301 if (AR_SREV_9100(ah)) {
1302 u32 mask;
1303 mask = REG_READ(ah, AR_CFG);
1304 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1305 ath_print(common, ATH_DBG_RESET,
1306 "CFG Byte Swap Set 0x%x\n", mask);
1307 } else {
1308 mask =
1309 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1310 REG_WRITE(ah, AR_CFG, mask);
1311 ath_print(common, ATH_DBG_RESET,
1312 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
1313 }
1314 } else {
1315 /* Configure AR9271 target WLAN */
1316 if (AR_SREV_9271(ah))
1317 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1318 #ifdef __BIG_ENDIAN
1319 else
1320 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1321 #endif
1322 }
1323
1324 if (ah->btcoex_hw.enabled)
1325 ath9k_hw_btcoex_enable(ah);
1326
1327 if (AR_SREV_9300_20_OR_LATER(ah)) {
1328 ath9k_hw_loadnf(ah, curchan);
1329 ath9k_hw_start_nfcal(ah);
1330 }
1331
1332 return 0;
1333 }
1334 EXPORT_SYMBOL(ath9k_hw_reset);
1335
1336 /************************/
1337 /* Key Cache Management */
1338 /************************/
1339
1340 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
1341 {
1342 u32 keyType;
1343
1344 if (entry >= ah->caps.keycache_size) {
1345 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1346 "keychache entry %u out of range\n", entry);
1347 return false;
1348 }
1349
1350 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
1351
1352 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
1353 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
1354 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
1355 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
1356 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
1357 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
1358 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
1359 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
1360
1361 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
1362 u16 micentry = entry + 64;
1363
1364 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
1365 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
1366 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
1367 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
1368
1369 }
1370
1371 return true;
1372 }
1373 EXPORT_SYMBOL(ath9k_hw_keyreset);
1374
1375 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
1376 {
1377 u32 macHi, macLo;
1378
1379 if (entry >= ah->caps.keycache_size) {
1380 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1381 "keychache entry %u out of range\n", entry);
1382 return false;
1383 }
1384
1385 if (mac != NULL) {
1386 macHi = (mac[5] << 8) | mac[4];
1387 macLo = (mac[3] << 24) |
1388 (mac[2] << 16) |
1389 (mac[1] << 8) |
1390 mac[0];
1391 macLo >>= 1;
1392 macLo |= (macHi & 1) << 31;
1393 macHi >>= 1;
1394 } else {
1395 macLo = macHi = 0;
1396 }
1397 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
1398 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
1399
1400 return true;
1401 }
1402 EXPORT_SYMBOL(ath9k_hw_keysetmac);
1403
1404 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
1405 const struct ath9k_keyval *k,
1406 const u8 *mac)
1407 {
1408 const struct ath9k_hw_capabilities *pCap = &ah->caps;
1409 struct ath_common *common = ath9k_hw_common(ah);
1410 u32 key0, key1, key2, key3, key4;
1411 u32 keyType;
1412
1413 if (entry >= pCap->keycache_size) {
1414 ath_print(common, ATH_DBG_FATAL,
1415 "keycache entry %u out of range\n", entry);
1416 return false;
1417 }
1418
1419 switch (k->kv_type) {
1420 case ATH9K_CIPHER_AES_OCB:
1421 keyType = AR_KEYTABLE_TYPE_AES;
1422 break;
1423 case ATH9K_CIPHER_AES_CCM:
1424 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
1425 ath_print(common, ATH_DBG_ANY,
1426 "AES-CCM not supported by mac rev 0x%x\n",
1427 ah->hw_version.macRev);
1428 return false;
1429 }
1430 keyType = AR_KEYTABLE_TYPE_CCM;
1431 break;
1432 case ATH9K_CIPHER_TKIP:
1433 keyType = AR_KEYTABLE_TYPE_TKIP;
1434 if (ATH9K_IS_MIC_ENABLED(ah)
1435 && entry + 64 >= pCap->keycache_size) {
1436 ath_print(common, ATH_DBG_ANY,
1437 "entry %u inappropriate for TKIP\n", entry);
1438 return false;
1439 }
1440 break;
1441 case ATH9K_CIPHER_WEP:
1442 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
1443 ath_print(common, ATH_DBG_ANY,
1444 "WEP key length %u too small\n", k->kv_len);
1445 return false;
1446 }
1447 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
1448 keyType = AR_KEYTABLE_TYPE_40;
1449 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
1450 keyType = AR_KEYTABLE_TYPE_104;
1451 else
1452 keyType = AR_KEYTABLE_TYPE_128;
1453 break;
1454 case ATH9K_CIPHER_CLR:
1455 keyType = AR_KEYTABLE_TYPE_CLR;
1456 break;
1457 default:
1458 ath_print(common, ATH_DBG_FATAL,
1459 "cipher %u not supported\n", k->kv_type);
1460 return false;
1461 }
1462
1463 key0 = get_unaligned_le32(k->kv_val + 0);
1464 key1 = get_unaligned_le16(k->kv_val + 4);
1465 key2 = get_unaligned_le32(k->kv_val + 6);
1466 key3 = get_unaligned_le16(k->kv_val + 10);
1467 key4 = get_unaligned_le32(k->kv_val + 12);
1468 if (k->kv_len <= WLAN_KEY_LEN_WEP104)
1469 key4 &= 0xff;
1470
1471 /*
1472 * Note: Key cache registers access special memory area that requires
1473 * two 32-bit writes to actually update the values in the internal
1474 * memory. Consequently, the exact order and pairs used here must be
1475 * maintained.
1476 */
1477
1478 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
1479 u16 micentry = entry + 64;
1480
1481 /*
1482 * Write inverted key[47:0] first to avoid Michael MIC errors
1483 * on frames that could be sent or received at the same time.
1484 * The correct key will be written in the end once everything
1485 * else is ready.
1486 */
1487 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
1488 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
1489
1490 /* Write key[95:48] */
1491 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
1492 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
1493
1494 /* Write key[127:96] and key type */
1495 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
1496 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
1497
1498 /* Write MAC address for the entry */
1499 (void) ath9k_hw_keysetmac(ah, entry, mac);
1500
1501 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
1502 /*
1503 * TKIP uses two key cache entries:
1504 * Michael MIC TX/RX keys in the same key cache entry
1505 * (idx = main index + 64):
1506 * key0 [31:0] = RX key [31:0]
1507 * key1 [15:0] = TX key [31:16]
1508 * key1 [31:16] = reserved
1509 * key2 [31:0] = RX key [63:32]
1510 * key3 [15:0] = TX key [15:0]
1511 * key3 [31:16] = reserved
1512 * key4 [31:0] = TX key [63:32]
1513 */
1514 u32 mic0, mic1, mic2, mic3, mic4;
1515
1516 mic0 = get_unaligned_le32(k->kv_mic + 0);
1517 mic2 = get_unaligned_le32(k->kv_mic + 4);
1518 mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
1519 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
1520 mic4 = get_unaligned_le32(k->kv_txmic + 4);
1521
1522 /* Write RX[31:0] and TX[31:16] */
1523 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
1524 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
1525
1526 /* Write RX[63:32] and TX[15:0] */
1527 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
1528 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
1529
1530 /* Write TX[63:32] and keyType(reserved) */
1531 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
1532 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
1533 AR_KEYTABLE_TYPE_CLR);
1534
1535 } else {
1536 /*
1537 * TKIP uses four key cache entries (two for group
1538 * keys):
1539 * Michael MIC TX/RX keys are in different key cache
1540 * entries (idx = main index + 64 for TX and
1541 * main index + 32 + 96 for RX):
1542 * key0 [31:0] = TX/RX MIC key [31:0]
1543 * key1 [31:0] = reserved
1544 * key2 [31:0] = TX/RX MIC key [63:32]
1545 * key3 [31:0] = reserved
1546 * key4 [31:0] = reserved
1547 *
1548 * Upper layer code will call this function separately
1549 * for TX and RX keys when these registers offsets are
1550 * used.
1551 */
1552 u32 mic0, mic2;
1553
1554 mic0 = get_unaligned_le32(k->kv_mic + 0);
1555 mic2 = get_unaligned_le32(k->kv_mic + 4);
1556
1557 /* Write MIC key[31:0] */
1558 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
1559 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
1560
1561 /* Write MIC key[63:32] */
1562 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
1563 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
1564
1565 /* Write TX[63:32] and keyType(reserved) */
1566 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
1567 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
1568 AR_KEYTABLE_TYPE_CLR);
1569 }
1570
1571 /* MAC address registers are reserved for the MIC entry */
1572 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
1573 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
1574
1575 /*
1576 * Write the correct (un-inverted) key[47:0] last to enable
1577 * TKIP now that all other registers are set with correct
1578 * values.
1579 */
1580 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
1581 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
1582 } else {
1583 /* Write key[47:0] */
1584 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
1585 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
1586
1587 /* Write key[95:48] */
1588 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
1589 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
1590
1591 /* Write key[127:96] and key type */
1592 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
1593 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
1594
1595 /* Write MAC address for the entry */
1596 (void) ath9k_hw_keysetmac(ah, entry, mac);
1597 }
1598
1599 return true;
1600 }
1601 EXPORT_SYMBOL(ath9k_hw_set_keycache_entry);
1602
1603 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
1604 {
1605 if (entry < ah->caps.keycache_size) {
1606 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
1607 if (val & AR_KEYTABLE_VALID)
1608 return true;
1609 }
1610 return false;
1611 }
1612 EXPORT_SYMBOL(ath9k_hw_keyisvalid);
1613
1614 /******************************/
1615 /* Power Management (Chipset) */
1616 /******************************/
1617
1618 /*
1619 * Notify Power Mgt is disabled in self-generated frames.
1620 * If requested, force chip to sleep.
1621 */
1622 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
1623 {
1624 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1625 if (setChip) {
1626 /*
1627 * Clear the RTC force wake bit to allow the
1628 * mac to go to sleep.
1629 */
1630 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1631 AR_RTC_FORCE_WAKE_EN);
1632 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1633 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1634
1635 /* Shutdown chip. Active low */
1636 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah))
1637 REG_CLR_BIT(ah, (AR_RTC_RESET),
1638 AR_RTC_RESET_EN);
1639 }
1640 }
1641
1642 /*
1643 * Notify Power Management is enabled in self-generating
1644 * frames. If request, set power mode of chip to
1645 * auto/normal. Duration in units of 128us (1/8 TU).
1646 */
1647 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
1648 {
1649 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1650 if (setChip) {
1651 struct ath9k_hw_capabilities *pCap = &ah->caps;
1652
1653 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1654 /* Set WakeOnInterrupt bit; clear ForceWake bit */
1655 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1656 AR_RTC_FORCE_WAKE_ON_INT);
1657 } else {
1658 /*
1659 * Clear the RTC force wake bit to allow the
1660 * mac to go to sleep.
1661 */
1662 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1663 AR_RTC_FORCE_WAKE_EN);
1664 }
1665 }
1666 }
1667
1668 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
1669 {
1670 u32 val;
1671 int i;
1672
1673 if (setChip) {
1674 if ((REG_READ(ah, AR_RTC_STATUS) &
1675 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
1676 if (ath9k_hw_set_reset_reg(ah,
1677 ATH9K_RESET_POWER_ON) != true) {
1678 return false;
1679 }
1680 if (!AR_SREV_9300_20_OR_LATER(ah))
1681 ath9k_hw_init_pll(ah, NULL);
1682 }
1683 if (AR_SREV_9100(ah))
1684 REG_SET_BIT(ah, AR_RTC_RESET,
1685 AR_RTC_RESET_EN);
1686
1687 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1688 AR_RTC_FORCE_WAKE_EN);
1689 udelay(50);
1690
1691 for (i = POWER_UP_TIME / 50; i > 0; i--) {
1692 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
1693 if (val == AR_RTC_STATUS_ON)
1694 break;
1695 udelay(50);
1696 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1697 AR_RTC_FORCE_WAKE_EN);
1698 }
1699 if (i == 0) {
1700 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1701 "Failed to wakeup in %uus\n",
1702 POWER_UP_TIME / 20);
1703 return false;
1704 }
1705 }
1706
1707 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1708
1709 return true;
1710 }
1711
1712 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
1713 {
1714 struct ath_common *common = ath9k_hw_common(ah);
1715 int status = true, setChip = true;
1716 static const char *modes[] = {
1717 "AWAKE",
1718 "FULL-SLEEP",
1719 "NETWORK SLEEP",
1720 "UNDEFINED"
1721 };
1722
1723 if (ah->power_mode == mode)
1724 return status;
1725
1726 ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
1727 modes[ah->power_mode], modes[mode]);
1728
1729 switch (mode) {
1730 case ATH9K_PM_AWAKE:
1731 status = ath9k_hw_set_power_awake(ah, setChip);
1732 break;
1733 case ATH9K_PM_FULL_SLEEP:
1734 ath9k_set_power_sleep(ah, setChip);
1735 ah->chip_fullsleep = true;
1736 break;
1737 case ATH9K_PM_NETWORK_SLEEP:
1738 ath9k_set_power_network_sleep(ah, setChip);
1739 break;
1740 default:
1741 ath_print(common, ATH_DBG_FATAL,
1742 "Unknown power mode %u\n", mode);
1743 return false;
1744 }
1745 ah->power_mode = mode;
1746
1747 return status;
1748 }
1749 EXPORT_SYMBOL(ath9k_hw_setpower);
1750
1751 /*******************/
1752 /* Beacon Handling */
1753 /*******************/
1754
1755 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
1756 {
1757 int flags = 0;
1758
1759 ah->beacon_interval = beacon_period;
1760
1761 switch (ah->opmode) {
1762 case NL80211_IFTYPE_STATION:
1763 case NL80211_IFTYPE_MONITOR:
1764 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
1765 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
1766 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
1767 flags |= AR_TBTT_TIMER_EN;
1768 break;
1769 case NL80211_IFTYPE_ADHOC:
1770 case NL80211_IFTYPE_MESH_POINT:
1771 REG_SET_BIT(ah, AR_TXCFG,
1772 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
1773 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
1774 TU_TO_USEC(next_beacon +
1775 (ah->atim_window ? ah->
1776 atim_window : 1)));
1777 flags |= AR_NDP_TIMER_EN;
1778 case NL80211_IFTYPE_AP:
1779 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
1780 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
1781 TU_TO_USEC(next_beacon -
1782 ah->config.
1783 dma_beacon_response_time));
1784 REG_WRITE(ah, AR_NEXT_SWBA,
1785 TU_TO_USEC(next_beacon -
1786 ah->config.
1787 sw_beacon_response_time));
1788 flags |=
1789 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
1790 break;
1791 default:
1792 ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
1793 "%s: unsupported opmode: %d\n",
1794 __func__, ah->opmode);
1795 return;
1796 break;
1797 }
1798
1799 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
1800 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
1801 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
1802 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
1803
1804 beacon_period &= ~ATH9K_BEACON_ENA;
1805 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
1806 ath9k_hw_reset_tsf(ah);
1807 }
1808
1809 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
1810 }
1811 EXPORT_SYMBOL(ath9k_hw_beaconinit);
1812
1813 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
1814 const struct ath9k_beacon_state *bs)
1815 {
1816 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
1817 struct ath9k_hw_capabilities *pCap = &ah->caps;
1818 struct ath_common *common = ath9k_hw_common(ah);
1819
1820 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
1821
1822 REG_WRITE(ah, AR_BEACON_PERIOD,
1823 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1824 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
1825 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1826
1827 REG_RMW_FIELD(ah, AR_RSSI_THR,
1828 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
1829
1830 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
1831
1832 if (bs->bs_sleepduration > beaconintval)
1833 beaconintval = bs->bs_sleepduration;
1834
1835 dtimperiod = bs->bs_dtimperiod;
1836 if (bs->bs_sleepduration > dtimperiod)
1837 dtimperiod = bs->bs_sleepduration;
1838
1839 if (beaconintval == dtimperiod)
1840 nextTbtt = bs->bs_nextdtim;
1841 else
1842 nextTbtt = bs->bs_nexttbtt;
1843
1844 ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
1845 ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
1846 ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
1847 ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
1848
1849 REG_WRITE(ah, AR_NEXT_DTIM,
1850 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
1851 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
1852
1853 REG_WRITE(ah, AR_SLEEP1,
1854 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
1855 | AR_SLEEP1_ASSUME_DTIM);
1856
1857 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
1858 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
1859 else
1860 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
1861
1862 REG_WRITE(ah, AR_SLEEP2,
1863 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
1864
1865 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
1866 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
1867
1868 REG_SET_BIT(ah, AR_TIMER_MODE,
1869 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
1870 AR_DTIM_TIMER_EN);
1871
1872 /* TSF Out of Range Threshold */
1873 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
1874 }
1875 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
1876
1877 /*******************/
1878 /* HW Capabilities */
1879 /*******************/
1880
1881 int ath9k_hw_fill_cap_info(struct ath_hw *ah)
1882 {
1883 struct ath9k_hw_capabilities *pCap = &ah->caps;
1884 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1885 struct ath_common *common = ath9k_hw_common(ah);
1886 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
1887
1888 u16 capField = 0, eeval;
1889
1890 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
1891 regulatory->current_rd = eeval;
1892
1893 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
1894 if (AR_SREV_9285_10_OR_LATER(ah))
1895 eeval |= AR9285_RDEXT_DEFAULT;
1896 regulatory->current_rd_ext = eeval;
1897
1898 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
1899
1900 if (ah->opmode != NL80211_IFTYPE_AP &&
1901 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
1902 if (regulatory->current_rd == 0x64 ||
1903 regulatory->current_rd == 0x65)
1904 regulatory->current_rd += 5;
1905 else if (regulatory->current_rd == 0x41)
1906 regulatory->current_rd = 0x43;
1907 ath_print(common, ATH_DBG_REGULATORY,
1908 "regdomain mapped to 0x%x\n", regulatory->current_rd);
1909 }
1910
1911 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
1912 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
1913 ath_print(common, ATH_DBG_FATAL,
1914 "no band has been marked as supported in EEPROM.\n");
1915 return -EINVAL;
1916 }
1917
1918 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
1919
1920 if (eeval & AR5416_OPFLAGS_11A) {
1921 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
1922 if (ah->config.ht_enable) {
1923 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
1924 set_bit(ATH9K_MODE_11NA_HT20,
1925 pCap->wireless_modes);
1926 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
1927 set_bit(ATH9K_MODE_11NA_HT40PLUS,
1928 pCap->wireless_modes);
1929 set_bit(ATH9K_MODE_11NA_HT40MINUS,
1930 pCap->wireless_modes);
1931 }
1932 }
1933 }
1934
1935 if (eeval & AR5416_OPFLAGS_11G) {
1936 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
1937 if (ah->config.ht_enable) {
1938 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
1939 set_bit(ATH9K_MODE_11NG_HT20,
1940 pCap->wireless_modes);
1941 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
1942 set_bit(ATH9K_MODE_11NG_HT40PLUS,
1943 pCap->wireless_modes);
1944 set_bit(ATH9K_MODE_11NG_HT40MINUS,
1945 pCap->wireless_modes);
1946 }
1947 }
1948 }
1949
1950 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
1951 /*
1952 * For AR9271 we will temporarilly uses the rx chainmax as read from
1953 * the EEPROM.
1954 */
1955 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
1956 !(eeval & AR5416_OPFLAGS_11A) &&
1957 !(AR_SREV_9271(ah)))
1958 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
1959 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
1960 else
1961 /* Use rx_chainmask from EEPROM. */
1962 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
1963
1964 if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
1965 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
1966
1967 pCap->low_2ghz_chan = 2312;
1968 pCap->high_2ghz_chan = 2732;
1969
1970 pCap->low_5ghz_chan = 4920;
1971 pCap->high_5ghz_chan = 6100;
1972
1973 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
1974 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
1975 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
1976
1977 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
1978 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
1979 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
1980
1981 if (ah->config.ht_enable)
1982 pCap->hw_caps |= ATH9K_HW_CAP_HT;
1983 else
1984 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
1985
1986 pCap->hw_caps |= ATH9K_HW_CAP_GTT;
1987 pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
1988 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
1989 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
1990
1991 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
1992 pCap->total_queues =
1993 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
1994 else
1995 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
1996
1997 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
1998 pCap->keycache_size =
1999 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
2000 else
2001 pCap->keycache_size = AR_KEYTABLE_SIZE;
2002
2003 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
2004
2005 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
2006 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1;
2007 else
2008 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
2009
2010 if (AR_SREV_9271(ah))
2011 pCap->num_gpio_pins = AR9271_NUM_GPIO;
2012 else if (AR_SREV_9285_10_OR_LATER(ah))
2013 pCap->num_gpio_pins = AR9285_NUM_GPIO;
2014 else if (AR_SREV_9280_10_OR_LATER(ah))
2015 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2016 else
2017 pCap->num_gpio_pins = AR_NUM_GPIO;
2018
2019 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
2020 pCap->hw_caps |= ATH9K_HW_CAP_CST;
2021 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
2022 } else {
2023 pCap->rts_aggr_limit = (8 * 1024);
2024 }
2025
2026 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
2027
2028 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2029 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2030 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2031 ah->rfkill_gpio =
2032 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2033 ah->rfkill_polarity =
2034 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
2035
2036 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
2037 }
2038 #endif
2039 if (AR_SREV_9271(ah))
2040 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2041 else
2042 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
2043
2044 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
2045 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2046 else
2047 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
2048
2049 if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
2050 pCap->reg_cap =
2051 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
2052 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
2053 AR_EEPROM_EEREGCAP_EN_KK_U2 |
2054 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
2055 } else {
2056 pCap->reg_cap =
2057 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
2058 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
2059 }
2060
2061 /* Advertise midband for AR5416 with FCC midband set in eeprom */
2062 if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
2063 AR_SREV_5416(ah))
2064 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
2065
2066 pCap->num_antcfg_5ghz =
2067 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
2068 pCap->num_antcfg_2ghz =
2069 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
2070
2071 if (AR_SREV_9280_10_OR_LATER(ah) &&
2072 ath9k_hw_btcoex_supported(ah)) {
2073 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
2074 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
2075
2076 if (AR_SREV_9285(ah)) {
2077 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
2078 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
2079 } else {
2080 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
2081 }
2082 } else {
2083 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
2084 }
2085
2086 if (AR_SREV_9300_20_OR_LATER(ah)) {
2087 pCap->hw_caps |= ATH9K_HW_CAP_EDMA;
2088 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2089 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2090 pCap->rx_status_len = sizeof(struct ar9003_rxs);
2091 pCap->tx_desc_len = sizeof(struct ar9003_txc);
2092 } else {
2093 pCap->tx_desc_len = sizeof(struct ath_desc);
2094 }
2095
2096 if (AR_SREV_9300_20_OR_LATER(ah))
2097 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2098
2099 return 0;
2100 }
2101
2102 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
2103 u32 capability, u32 *result)
2104 {
2105 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2106 switch (type) {
2107 case ATH9K_CAP_CIPHER:
2108 switch (capability) {
2109 case ATH9K_CIPHER_AES_CCM:
2110 case ATH9K_CIPHER_AES_OCB:
2111 case ATH9K_CIPHER_TKIP:
2112 case ATH9K_CIPHER_WEP:
2113 case ATH9K_CIPHER_MIC:
2114 case ATH9K_CIPHER_CLR:
2115 return true;
2116 default:
2117 return false;
2118 }
2119 case ATH9K_CAP_TKIP_MIC:
2120 switch (capability) {
2121 case 0:
2122 return true;
2123 case 1:
2124 return (ah->sta_id1_defaults &
2125 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
2126 false;
2127 }
2128 case ATH9K_CAP_TKIP_SPLIT:
2129 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
2130 false : true;
2131 case ATH9K_CAP_MCAST_KEYSRCH:
2132 switch (capability) {
2133 case 0:
2134 return true;
2135 case 1:
2136 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
2137 return false;
2138 } else {
2139 return (ah->sta_id1_defaults &
2140 AR_STA_ID1_MCAST_KSRCH) ? true :
2141 false;
2142 }
2143 }
2144 return false;
2145 case ATH9K_CAP_TXPOW:
2146 switch (capability) {
2147 case 0:
2148 return 0;
2149 case 1:
2150 *result = regulatory->power_limit;
2151 return 0;
2152 case 2:
2153 *result = regulatory->max_power_level;
2154 return 0;
2155 case 3:
2156 *result = regulatory->tp_scale;
2157 return 0;
2158 }
2159 return false;
2160 case ATH9K_CAP_DS:
2161 return (AR_SREV_9280_20_OR_LATER(ah) &&
2162 (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
2163 ? false : true;
2164 default:
2165 return false;
2166 }
2167 }
2168 EXPORT_SYMBOL(ath9k_hw_getcapability);
2169
2170 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
2171 u32 capability, u32 setting, int *status)
2172 {
2173 switch (type) {
2174 case ATH9K_CAP_TKIP_MIC:
2175 if (setting)
2176 ah->sta_id1_defaults |=
2177 AR_STA_ID1_CRPT_MIC_ENABLE;
2178 else
2179 ah->sta_id1_defaults &=
2180 ~AR_STA_ID1_CRPT_MIC_ENABLE;
2181 return true;
2182 case ATH9K_CAP_MCAST_KEYSRCH:
2183 if (setting)
2184 ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
2185 else
2186 ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
2187 return true;
2188 default:
2189 return false;
2190 }
2191 }
2192 EXPORT_SYMBOL(ath9k_hw_setcapability);
2193
2194 /****************************/
2195 /* GPIO / RFKILL / Antennae */
2196 /****************************/
2197
2198 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
2199 u32 gpio, u32 type)
2200 {
2201 int addr;
2202 u32 gpio_shift, tmp;
2203
2204 if (gpio > 11)
2205 addr = AR_GPIO_OUTPUT_MUX3;
2206 else if (gpio > 5)
2207 addr = AR_GPIO_OUTPUT_MUX2;
2208 else
2209 addr = AR_GPIO_OUTPUT_MUX1;
2210
2211 gpio_shift = (gpio % 6) * 5;
2212
2213 if (AR_SREV_9280_20_OR_LATER(ah)
2214 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2215 REG_RMW(ah, addr, (type << gpio_shift),
2216 (0x1f << gpio_shift));
2217 } else {
2218 tmp = REG_READ(ah, addr);
2219 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2220 tmp &= ~(0x1f << gpio_shift);
2221 tmp |= (type << gpio_shift);
2222 REG_WRITE(ah, addr, tmp);
2223 }
2224 }
2225
2226 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
2227 {
2228 u32 gpio_shift;
2229
2230 BUG_ON(gpio >= ah->caps.num_gpio_pins);
2231
2232 gpio_shift = gpio << 1;
2233
2234 REG_RMW(ah,
2235 AR_GPIO_OE_OUT,
2236 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2237 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2238 }
2239 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
2240
2241 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
2242 {
2243 #define MS_REG_READ(x, y) \
2244 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2245
2246 if (gpio >= ah->caps.num_gpio_pins)
2247 return 0xffffffff;
2248
2249 if (AR_SREV_9300_20_OR_LATER(ah))
2250 return MS_REG_READ(AR9300, gpio) != 0;
2251 else if (AR_SREV_9271(ah))
2252 return MS_REG_READ(AR9271, gpio) != 0;
2253 else if (AR_SREV_9287_10_OR_LATER(ah))
2254 return MS_REG_READ(AR9287, gpio) != 0;
2255 else if (AR_SREV_9285_10_OR_LATER(ah))
2256 return MS_REG_READ(AR9285, gpio) != 0;
2257 else if (AR_SREV_9280_10_OR_LATER(ah))
2258 return MS_REG_READ(AR928X, gpio) != 0;
2259 else
2260 return MS_REG_READ(AR, gpio) != 0;
2261 }
2262 EXPORT_SYMBOL(ath9k_hw_gpio_get);
2263
2264 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
2265 u32 ah_signal_type)
2266 {
2267 u32 gpio_shift;
2268
2269 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
2270
2271 gpio_shift = 2 * gpio;
2272
2273 REG_RMW(ah,
2274 AR_GPIO_OE_OUT,
2275 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2276 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2277 }
2278 EXPORT_SYMBOL(ath9k_hw_cfg_output);
2279
2280 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
2281 {
2282 if (AR_SREV_9271(ah))
2283 val = ~val;
2284
2285 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2286 AR_GPIO_BIT(gpio));
2287 }
2288 EXPORT_SYMBOL(ath9k_hw_set_gpio);
2289
2290 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
2291 {
2292 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
2293 }
2294 EXPORT_SYMBOL(ath9k_hw_getdefantenna);
2295
2296 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
2297 {
2298 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
2299 }
2300 EXPORT_SYMBOL(ath9k_hw_setantenna);
2301
2302 /*********************/
2303 /* General Operation */
2304 /*********************/
2305
2306 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
2307 {
2308 u32 bits = REG_READ(ah, AR_RX_FILTER);
2309 u32 phybits = REG_READ(ah, AR_PHY_ERR);
2310
2311 if (phybits & AR_PHY_ERR_RADAR)
2312 bits |= ATH9K_RX_FILTER_PHYRADAR;
2313 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2314 bits |= ATH9K_RX_FILTER_PHYERR;
2315
2316 return bits;
2317 }
2318 EXPORT_SYMBOL(ath9k_hw_getrxfilter);
2319
2320 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
2321 {
2322 u32 phybits;
2323
2324 REG_WRITE(ah, AR_RX_FILTER, bits);
2325
2326 phybits = 0;
2327 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2328 phybits |= AR_PHY_ERR_RADAR;
2329 if (bits & ATH9K_RX_FILTER_PHYERR)
2330 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2331 REG_WRITE(ah, AR_PHY_ERR, phybits);
2332
2333 if (phybits)
2334 REG_WRITE(ah, AR_RXCFG,
2335 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
2336 else
2337 REG_WRITE(ah, AR_RXCFG,
2338 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
2339 }
2340 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
2341
2342 bool ath9k_hw_phy_disable(struct ath_hw *ah)
2343 {
2344 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2345 return false;
2346
2347 ath9k_hw_init_pll(ah, NULL);
2348 return true;
2349 }
2350 EXPORT_SYMBOL(ath9k_hw_phy_disable);
2351
2352 bool ath9k_hw_disable(struct ath_hw *ah)
2353 {
2354 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2355 return false;
2356
2357 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2358 return false;
2359
2360 ath9k_hw_init_pll(ah, NULL);
2361 return true;
2362 }
2363 EXPORT_SYMBOL(ath9k_hw_disable);
2364
2365 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
2366 {
2367 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2368 struct ath9k_channel *chan = ah->curchan;
2369 struct ieee80211_channel *channel = chan->chan;
2370
2371 regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
2372
2373 ah->eep_ops->set_txpower(ah, chan,
2374 ath9k_regd_get_ctl(regulatory, chan),
2375 channel->max_antenna_gain * 2,
2376 channel->max_power * 2,
2377 min((u32) MAX_RATE_POWER,
2378 (u32) regulatory->power_limit));
2379 }
2380 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
2381
2382 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
2383 {
2384 memcpy(ath9k_hw_common(ah)->macaddr, mac, ETH_ALEN);
2385 }
2386 EXPORT_SYMBOL(ath9k_hw_setmac);
2387
2388 void ath9k_hw_setopmode(struct ath_hw *ah)
2389 {
2390 ath9k_hw_set_operating_mode(ah, ah->opmode);
2391 }
2392 EXPORT_SYMBOL(ath9k_hw_setopmode);
2393
2394 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
2395 {
2396 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2397 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
2398 }
2399 EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
2400
2401 void ath9k_hw_write_associd(struct ath_hw *ah)
2402 {
2403 struct ath_common *common = ath9k_hw_common(ah);
2404
2405 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2406 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2407 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2408 }
2409 EXPORT_SYMBOL(ath9k_hw_write_associd);
2410
2411 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
2412 {
2413 u64 tsf;
2414
2415 tsf = REG_READ(ah, AR_TSF_U32);
2416 tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
2417
2418 return tsf;
2419 }
2420 EXPORT_SYMBOL(ath9k_hw_gettsf64);
2421
2422 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
2423 {
2424 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
2425 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
2426 }
2427 EXPORT_SYMBOL(ath9k_hw_settsf64);
2428
2429 void ath9k_hw_reset_tsf(struct ath_hw *ah)
2430 {
2431 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2432 AH_TSF_WRITE_TIMEOUT))
2433 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
2434 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
2435
2436 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2437 }
2438 EXPORT_SYMBOL(ath9k_hw_reset_tsf);
2439
2440 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
2441 {
2442 if (setting)
2443 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
2444 else
2445 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
2446 }
2447 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
2448
2449 /*
2450 * Extend 15-bit time stamp from rx descriptor to
2451 * a full 64-bit TSF using the current h/w TSF.
2452 */
2453 u64 ath9k_hw_extend_tsf(struct ath_hw *ah, u32 rstamp)
2454 {
2455 u64 tsf;
2456
2457 tsf = ath9k_hw_gettsf64(ah);
2458 if ((tsf & 0x7fff) < rstamp)
2459 tsf -= 0x8000;
2460 return (tsf & ~0x7fff) | rstamp;
2461 }
2462 EXPORT_SYMBOL(ath9k_hw_extend_tsf);
2463
2464 void ath9k_hw_set11nmac2040(struct ath_hw *ah)
2465 {
2466 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
2467 u32 macmode;
2468
2469 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
2470 macmode = AR_2040_JOINED_RX_CLEAR;
2471 else
2472 macmode = 0;
2473
2474 REG_WRITE(ah, AR_2040_MODE, macmode);
2475 }
2476
2477 /* HW Generic timers configuration */
2478
2479 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2480 {
2481 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2482 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2483 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2484 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2485 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2486 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2487 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2488 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2489 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2490 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2491 AR_NDP2_TIMER_MODE, 0x0002},
2492 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2493 AR_NDP2_TIMER_MODE, 0x0004},
2494 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2495 AR_NDP2_TIMER_MODE, 0x0008},
2496 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2497 AR_NDP2_TIMER_MODE, 0x0010},
2498 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2499 AR_NDP2_TIMER_MODE, 0x0020},
2500 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2501 AR_NDP2_TIMER_MODE, 0x0040},
2502 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2503 AR_NDP2_TIMER_MODE, 0x0080}
2504 };
2505
2506 /* HW generic timer primitives */
2507
2508 /* compute and clear index of rightmost 1 */
2509 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
2510 {
2511 u32 b;
2512
2513 b = *mask;
2514 b &= (0-b);
2515 *mask &= ~b;
2516 b *= debruijn32;
2517 b >>= 27;
2518
2519 return timer_table->gen_timer_index[b];
2520 }
2521
2522 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
2523 {
2524 return REG_READ(ah, AR_TSF_L32);
2525 }
2526 EXPORT_SYMBOL(ath9k_hw_gettsf32);
2527
2528 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2529 void (*trigger)(void *),
2530 void (*overflow)(void *),
2531 void *arg,
2532 u8 timer_index)
2533 {
2534 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2535 struct ath_gen_timer *timer;
2536
2537 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
2538
2539 if (timer == NULL) {
2540 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2541 "Failed to allocate memory"
2542 "for hw timer[%d]\n", timer_index);
2543 return NULL;
2544 }
2545
2546 /* allocate a hardware generic timer slot */
2547 timer_table->timers[timer_index] = timer;
2548 timer->index = timer_index;
2549 timer->trigger = trigger;
2550 timer->overflow = overflow;
2551 timer->arg = arg;
2552
2553 return timer;
2554 }
2555 EXPORT_SYMBOL(ath_gen_timer_alloc);
2556
2557 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2558 struct ath_gen_timer *timer,
2559 u32 timer_next,
2560 u32 timer_period)
2561 {
2562 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2563 u32 tsf;
2564
2565 BUG_ON(!timer_period);
2566
2567 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
2568
2569 tsf = ath9k_hw_gettsf32(ah);
2570
2571 ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
2572 "curent tsf %x period %x"
2573 "timer_next %x\n", tsf, timer_period, timer_next);
2574
2575 /*
2576 * Pull timer_next forward if the current TSF already passed it
2577 * because of software latency
2578 */
2579 if (timer_next < tsf)
2580 timer_next = tsf + timer_period;
2581
2582 /*
2583 * Program generic timer registers
2584 */
2585 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
2586 timer_next);
2587 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
2588 timer_period);
2589 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2590 gen_tmr_configuration[timer->index].mode_mask);
2591
2592 /* Enable both trigger and thresh interrupt masks */
2593 REG_SET_BIT(ah, AR_IMR_S5,
2594 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2595 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2596 }
2597 EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
2598
2599 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
2600 {
2601 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2602
2603 if ((timer->index < AR_FIRST_NDP_TIMER) ||
2604 (timer->index >= ATH_MAX_GEN_TIMER)) {
2605 return;
2606 }
2607
2608 /* Clear generic timer enable bits. */
2609 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2610 gen_tmr_configuration[timer->index].mode_mask);
2611
2612 /* Disable both trigger and thresh interrupt masks */
2613 REG_CLR_BIT(ah, AR_IMR_S5,
2614 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2615 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2616
2617 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
2618 }
2619 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
2620
2621 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
2622 {
2623 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2624
2625 /* free the hardware generic timer slot */
2626 timer_table->timers[timer->index] = NULL;
2627 kfree(timer);
2628 }
2629 EXPORT_SYMBOL(ath_gen_timer_free);
2630
2631 /*
2632 * Generic Timer Interrupts handling
2633 */
2634 void ath_gen_timer_isr(struct ath_hw *ah)
2635 {
2636 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2637 struct ath_gen_timer *timer;
2638 struct ath_common *common = ath9k_hw_common(ah);
2639 u32 trigger_mask, thresh_mask, index;
2640
2641 /* get hardware generic timer interrupt status */
2642 trigger_mask = ah->intr_gen_timer_trigger;
2643 thresh_mask = ah->intr_gen_timer_thresh;
2644 trigger_mask &= timer_table->timer_mask.val;
2645 thresh_mask &= timer_table->timer_mask.val;
2646
2647 trigger_mask &= ~thresh_mask;
2648
2649 while (thresh_mask) {
2650 index = rightmost_index(timer_table, &thresh_mask);
2651 timer = timer_table->timers[index];
2652 BUG_ON(!timer);
2653 ath_print(common, ATH_DBG_HWTIMER,
2654 "TSF overflow for Gen timer %d\n", index);
2655 timer->overflow(timer->arg);
2656 }
2657
2658 while (trigger_mask) {
2659 index = rightmost_index(timer_table, &trigger_mask);
2660 timer = timer_table->timers[index];
2661 BUG_ON(!timer);
2662 ath_print(common, ATH_DBG_HWTIMER,
2663 "Gen timer[%d] trigger\n", index);
2664 timer->trigger(timer->arg);
2665 }
2666 }
2667 EXPORT_SYMBOL(ath_gen_timer_isr);
2668
2669 /********/
2670 /* HTC */
2671 /********/
2672
2673 void ath9k_hw_htc_resetinit(struct ath_hw *ah)
2674 {
2675 ah->htc_reset_init = true;
2676 }
2677 EXPORT_SYMBOL(ath9k_hw_htc_resetinit);
2678
2679 static struct {
2680 u32 version;
2681 const char * name;
2682 } ath_mac_bb_names[] = {
2683 /* Devices with external radios */
2684 { AR_SREV_VERSION_5416_PCI, "5416" },
2685 { AR_SREV_VERSION_5416_PCIE, "5418" },
2686 { AR_SREV_VERSION_9100, "9100" },
2687 { AR_SREV_VERSION_9160, "9160" },
2688 /* Single-chip solutions */
2689 { AR_SREV_VERSION_9280, "9280" },
2690 { AR_SREV_VERSION_9285, "9285" },
2691 { AR_SREV_VERSION_9287, "9287" },
2692 { AR_SREV_VERSION_9271, "9271" },
2693 { AR_SREV_VERSION_9300, "9300" },
2694 };
2695
2696 /* For devices with external radios */
2697 static struct {
2698 u16 version;
2699 const char * name;
2700 } ath_rf_names[] = {
2701 { 0, "5133" },
2702 { AR_RAD5133_SREV_MAJOR, "5133" },
2703 { AR_RAD5122_SREV_MAJOR, "5122" },
2704 { AR_RAD2133_SREV_MAJOR, "2133" },
2705 { AR_RAD2122_SREV_MAJOR, "2122" }
2706 };
2707
2708 /*
2709 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2710 */
2711 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
2712 {
2713 int i;
2714
2715 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2716 if (ath_mac_bb_names[i].version == mac_bb_version) {
2717 return ath_mac_bb_names[i].name;
2718 }
2719 }
2720
2721 return "????";
2722 }
2723
2724 /*
2725 * Return the RF name. "????" is returned if the RF is unknown.
2726 * Used for devices with external radios.
2727 */
2728 static const char *ath9k_hw_rf_name(u16 rf_version)
2729 {
2730 int i;
2731
2732 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2733 if (ath_rf_names[i].version == rf_version) {
2734 return ath_rf_names[i].name;
2735 }
2736 }
2737
2738 return "????";
2739 }
2740
2741 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
2742 {
2743 int used;
2744
2745 /* chipsets >= AR9280 are single-chip */
2746 if (AR_SREV_9280_10_OR_LATER(ah)) {
2747 used = snprintf(hw_name, len,
2748 "Atheros AR%s Rev:%x",
2749 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2750 ah->hw_version.macRev);
2751 }
2752 else {
2753 used = snprintf(hw_name, len,
2754 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
2755 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2756 ah->hw_version.macRev,
2757 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
2758 AR_RADIO_SREV_MAJOR)),
2759 ah->hw_version.phyRev);
2760 }
2761
2762 hw_name[used] = '\0';
2763 }
2764 EXPORT_SYMBOL(ath9k_hw_name);
Linux kernel - Deliverables
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