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ath9k_hw: move the RF claim stuff to AR9002 hardware family
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / hw.c
1 /*
2 * Copyright (c) 2008-2010 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/io.h>
18 #include <asm/unaligned.h>
19
20 #include "hw.h"
21 #include "hw-ops.h"
22 #include "rc.h"
23
24 #define ATH9K_CLOCK_RATE_CCK 22
25 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
26 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
27
28 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
29
30 MODULE_AUTHOR("Atheros Communications");
31 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
32 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
33 MODULE_LICENSE("Dual BSD/GPL");
34
35 static int __init ath9k_init(void)
36 {
37 return 0;
38 }
39 module_init(ath9k_init);
40
41 static void __exit ath9k_exit(void)
42 {
43 return;
44 }
45 module_exit(ath9k_exit);
46
47 /* Private hardware callbacks */
48
49 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
50 {
51 ath9k_hw_private_ops(ah)->init_cal_settings(ah);
52 }
53
54 static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
55 {
56 ath9k_hw_private_ops(ah)->init_mode_regs(ah);
57 }
58
59 static bool ath9k_hw_macversion_supported(struct ath_hw *ah)
60 {
61 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
62
63 return priv_ops->macversion_supported(ah->hw_version.macVersion);
64 }
65
66 static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
67 struct ath9k_channel *chan)
68 {
69 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
70 }
71
72 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
73 {
74 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
75 return;
76
77 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
78 }
79
80 /********************/
81 /* Helper Functions */
82 /********************/
83
84 static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
85 {
86 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
87
88 if (!ah->curchan) /* should really check for CCK instead */
89 return usecs *ATH9K_CLOCK_RATE_CCK;
90 if (conf->channel->band == IEEE80211_BAND_2GHZ)
91 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
92 return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
93 }
94
95 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
96 {
97 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
98
99 if (conf_is_ht40(conf))
100 return ath9k_hw_mac_clks(ah, usecs) * 2;
101 else
102 return ath9k_hw_mac_clks(ah, usecs);
103 }
104
105 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
106 {
107 int i;
108
109 BUG_ON(timeout < AH_TIME_QUANTUM);
110
111 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
112 if ((REG_READ(ah, reg) & mask) == val)
113 return true;
114
115 udelay(AH_TIME_QUANTUM);
116 }
117
118 ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
119 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
120 timeout, reg, REG_READ(ah, reg), mask, val);
121
122 return false;
123 }
124 EXPORT_SYMBOL(ath9k_hw_wait);
125
126 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
127 {
128 u32 retval;
129 int i;
130
131 for (i = 0, retval = 0; i < n; i++) {
132 retval = (retval << 1) | (val & 1);
133 val >>= 1;
134 }
135 return retval;
136 }
137
138 bool ath9k_get_channel_edges(struct ath_hw *ah,
139 u16 flags, u16 *low,
140 u16 *high)
141 {
142 struct ath9k_hw_capabilities *pCap = &ah->caps;
143
144 if (flags & CHANNEL_5GHZ) {
145 *low = pCap->low_5ghz_chan;
146 *high = pCap->high_5ghz_chan;
147 return true;
148 }
149 if ((flags & CHANNEL_2GHZ)) {
150 *low = pCap->low_2ghz_chan;
151 *high = pCap->high_2ghz_chan;
152 return true;
153 }
154 return false;
155 }
156
157 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
158 u8 phy, int kbps,
159 u32 frameLen, u16 rateix,
160 bool shortPreamble)
161 {
162 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
163
164 if (kbps == 0)
165 return 0;
166
167 switch (phy) {
168 case WLAN_RC_PHY_CCK:
169 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
170 if (shortPreamble)
171 phyTime >>= 1;
172 numBits = frameLen << 3;
173 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
174 break;
175 case WLAN_RC_PHY_OFDM:
176 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
177 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
178 numBits = OFDM_PLCP_BITS + (frameLen << 3);
179 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
180 txTime = OFDM_SIFS_TIME_QUARTER
181 + OFDM_PREAMBLE_TIME_QUARTER
182 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
183 } else if (ah->curchan &&
184 IS_CHAN_HALF_RATE(ah->curchan)) {
185 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
186 numBits = OFDM_PLCP_BITS + (frameLen << 3);
187 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
188 txTime = OFDM_SIFS_TIME_HALF +
189 OFDM_PREAMBLE_TIME_HALF
190 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
191 } else {
192 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
193 numBits = OFDM_PLCP_BITS + (frameLen << 3);
194 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
195 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
196 + (numSymbols * OFDM_SYMBOL_TIME);
197 }
198 break;
199 default:
200 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
201 "Unknown phy %u (rate ix %u)\n", phy, rateix);
202 txTime = 0;
203 break;
204 }
205
206 return txTime;
207 }
208 EXPORT_SYMBOL(ath9k_hw_computetxtime);
209
210 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
211 struct ath9k_channel *chan,
212 struct chan_centers *centers)
213 {
214 int8_t extoff;
215
216 if (!IS_CHAN_HT40(chan)) {
217 centers->ctl_center = centers->ext_center =
218 centers->synth_center = chan->channel;
219 return;
220 }
221
222 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
223 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
224 centers->synth_center =
225 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
226 extoff = 1;
227 } else {
228 centers->synth_center =
229 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
230 extoff = -1;
231 }
232
233 centers->ctl_center =
234 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
235 /* 25 MHz spacing is supported by hw but not on upper layers */
236 centers->ext_center =
237 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
238 }
239
240 /******************/
241 /* Chip Revisions */
242 /******************/
243
244 static void ath9k_hw_read_revisions(struct ath_hw *ah)
245 {
246 u32 val;
247
248 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
249
250 if (val == 0xFF) {
251 val = REG_READ(ah, AR_SREV);
252 ah->hw_version.macVersion =
253 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
254 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
255 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
256 } else {
257 if (!AR_SREV_9100(ah))
258 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
259
260 ah->hw_version.macRev = val & AR_SREV_REVISION;
261
262 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
263 ah->is_pciexpress = true;
264 }
265 }
266
267 /************************************/
268 /* HW Attach, Detach, Init Routines */
269 /************************************/
270
271 static void ath9k_hw_disablepcie(struct ath_hw *ah)
272 {
273 if (AR_SREV_9100(ah))
274 return;
275
276 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
277 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
278 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
279 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
280 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
281 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
282 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
283 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
284 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
285
286 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
287 }
288
289 /* This should work for all families including legacy */
290 static bool ath9k_hw_chip_test(struct ath_hw *ah)
291 {
292 struct ath_common *common = ath9k_hw_common(ah);
293 u32 regAddr[2] = { AR_STA_ID0 };
294 u32 regHold[2];
295 u32 patternData[4] = { 0x55555555,
296 0xaaaaaaaa,
297 0x66666666,
298 0x99999999 };
299 int i, j, loop_max;
300
301 if (!AR_SREV_9300_20_OR_LATER(ah)) {
302 loop_max = 2;
303 regAddr[1] = AR_PHY_BASE + (8 << 2);
304 } else
305 loop_max = 1;
306
307 for (i = 0; i < loop_max; i++) {
308 u32 addr = regAddr[i];
309 u32 wrData, rdData;
310
311 regHold[i] = REG_READ(ah, addr);
312 for (j = 0; j < 0x100; j++) {
313 wrData = (j << 16) | j;
314 REG_WRITE(ah, addr, wrData);
315 rdData = REG_READ(ah, addr);
316 if (rdData != wrData) {
317 ath_print(common, ATH_DBG_FATAL,
318 "address test failed "
319 "addr: 0x%08x - wr:0x%08x != "
320 "rd:0x%08x\n",
321 addr, wrData, rdData);
322 return false;
323 }
324 }
325 for (j = 0; j < 4; j++) {
326 wrData = patternData[j];
327 REG_WRITE(ah, addr, wrData);
328 rdData = REG_READ(ah, addr);
329 if (wrData != rdData) {
330 ath_print(common, ATH_DBG_FATAL,
331 "address test failed "
332 "addr: 0x%08x - wr:0x%08x != "
333 "rd:0x%08x\n",
334 addr, wrData, rdData);
335 return false;
336 }
337 }
338 REG_WRITE(ah, regAddr[i], regHold[i]);
339 }
340 udelay(100);
341
342 return true;
343 }
344
345 static void ath9k_hw_init_config(struct ath_hw *ah)
346 {
347 int i;
348
349 ah->config.dma_beacon_response_time = 2;
350 ah->config.sw_beacon_response_time = 10;
351 ah->config.additional_swba_backoff = 0;
352 ah->config.ack_6mb = 0x0;
353 ah->config.cwm_ignore_extcca = 0;
354 ah->config.pcie_powersave_enable = 0;
355 ah->config.pcie_clock_req = 0;
356 ah->config.pcie_waen = 0;
357 ah->config.analog_shiftreg = 1;
358 ah->config.ofdm_trig_low = 200;
359 ah->config.ofdm_trig_high = 500;
360 ah->config.cck_trig_high = 200;
361 ah->config.cck_trig_low = 100;
362
363 /*
364 * For now ANI is disabled for AR9003, it is still
365 * being tested.
366 */
367 if (!AR_SREV_9300_20_OR_LATER(ah))
368 ah->config.enable_ani = 1;
369
370 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
371 ah->config.spurchans[i][0] = AR_NO_SPUR;
372 ah->config.spurchans[i][1] = AR_NO_SPUR;
373 }
374
375 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
376 ah->config.ht_enable = 1;
377 else
378 ah->config.ht_enable = 0;
379
380 ah->config.rx_intr_mitigation = true;
381
382 /*
383 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
384 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
385 * This means we use it for all AR5416 devices, and the few
386 * minor PCI AR9280 devices out there.
387 *
388 * Serialization is required because these devices do not handle
389 * well the case of two concurrent reads/writes due to the latency
390 * involved. During one read/write another read/write can be issued
391 * on another CPU while the previous read/write may still be working
392 * on our hardware, if we hit this case the hardware poops in a loop.
393 * We prevent this by serializing reads and writes.
394 *
395 * This issue is not present on PCI-Express devices or pre-AR5416
396 * devices (legacy, 802.11abg).
397 */
398 if (num_possible_cpus() > 1)
399 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
400 }
401
402 static void ath9k_hw_init_defaults(struct ath_hw *ah)
403 {
404 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
405
406 regulatory->country_code = CTRY_DEFAULT;
407 regulatory->power_limit = MAX_RATE_POWER;
408 regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
409
410 ah->hw_version.magic = AR5416_MAGIC;
411 ah->hw_version.subvendorid = 0;
412
413 ah->ah_flags = 0;
414 if (!AR_SREV_9100(ah))
415 ah->ah_flags = AH_USE_EEPROM;
416
417 ah->atim_window = 0;
418 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
419 ah->beacon_interval = 100;
420 ah->enable_32kHz_clock = DONT_USE_32KHZ;
421 ah->slottime = (u32) -1;
422 ah->globaltxtimeout = (u32) -1;
423 ah->power_mode = ATH9K_PM_UNDEFINED;
424 }
425
426 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
427 {
428 struct ath_common *common = ath9k_hw_common(ah);
429 u32 sum;
430 int i;
431 u16 eeval;
432 u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
433
434 sum = 0;
435 for (i = 0; i < 3; i++) {
436 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
437 sum += eeval;
438 common->macaddr[2 * i] = eeval >> 8;
439 common->macaddr[2 * i + 1] = eeval & 0xff;
440 }
441 if (sum == 0 || sum == 0xffff * 3)
442 return -EADDRNOTAVAIL;
443
444 return 0;
445 }
446
447 static int ath9k_hw_post_init(struct ath_hw *ah)
448 {
449 int ecode;
450
451 if (!AR_SREV_9271(ah)) {
452 if (!ath9k_hw_chip_test(ah))
453 return -ENODEV;
454 }
455
456 if (!AR_SREV_9300_20_OR_LATER(ah)) {
457 ecode = ar9002_hw_rf_claim(ah);
458 if (ecode != 0)
459 return ecode;
460 }
461
462 ecode = ath9k_hw_eeprom_init(ah);
463 if (ecode != 0)
464 return ecode;
465
466 ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
467 "Eeprom VER: %d, REV: %d\n",
468 ah->eep_ops->get_eeprom_ver(ah),
469 ah->eep_ops->get_eeprom_rev(ah));
470
471 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
472 if (ecode) {
473 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
474 "Failed allocating banks for "
475 "external radio\n");
476 return ecode;
477 }
478
479 if (!AR_SREV_9100(ah)) {
480 ath9k_hw_ani_setup(ah);
481 ath9k_hw_ani_init(ah);
482 }
483
484 return 0;
485 }
486
487 static void ath9k_hw_attach_ops(struct ath_hw *ah)
488 {
489 if (AR_SREV_9300_20_OR_LATER(ah))
490 ar9003_hw_attach_ops(ah);
491 else
492 ar9002_hw_attach_ops(ah);
493 }
494
495 /* Called for all hardware families */
496 static int __ath9k_hw_init(struct ath_hw *ah)
497 {
498 struct ath_common *common = ath9k_hw_common(ah);
499 int r = 0;
500
501 if (ah->hw_version.devid == AR5416_AR9100_DEVID)
502 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
503
504 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
505 ath_print(common, ATH_DBG_FATAL,
506 "Couldn't reset chip\n");
507 return -EIO;
508 }
509
510 ath9k_hw_init_defaults(ah);
511 ath9k_hw_init_config(ah);
512
513 ath9k_hw_attach_ops(ah);
514
515 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
516 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
517 return -EIO;
518 }
519
520 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
521 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
522 (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
523 ah->config.serialize_regmode =
524 SER_REG_MODE_ON;
525 } else {
526 ah->config.serialize_regmode =
527 SER_REG_MODE_OFF;
528 }
529 }
530
531 ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
532 ah->config.serialize_regmode);
533
534 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
535 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
536 else
537 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
538
539 if (!ath9k_hw_macversion_supported(ah)) {
540 ath_print(common, ATH_DBG_FATAL,
541 "Mac Chip Rev 0x%02x.%x is not supported by "
542 "this driver\n", ah->hw_version.macVersion,
543 ah->hw_version.macRev);
544 return -EOPNOTSUPP;
545 }
546
547 if (AR_SREV_9271(ah) || AR_SREV_9100(ah))
548 ah->is_pciexpress = false;
549
550 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
551 ath9k_hw_init_cal_settings(ah);
552
553 ah->ani_function = ATH9K_ANI_ALL;
554 if (AR_SREV_9280_10_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
555 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
556
557 ath9k_hw_init_mode_regs(ah);
558
559 if (ah->is_pciexpress)
560 ath9k_hw_configpcipowersave(ah, 0, 0);
561 else
562 ath9k_hw_disablepcie(ah);
563
564 if (!AR_SREV_9300_20_OR_LATER(ah))
565 ar9002_hw_cck_chan14_spread(ah);
566
567 r = ath9k_hw_post_init(ah);
568 if (r)
569 return r;
570
571 ath9k_hw_init_mode_gain_regs(ah);
572 r = ath9k_hw_fill_cap_info(ah);
573 if (r)
574 return r;
575
576 r = ath9k_hw_init_macaddr(ah);
577 if (r) {
578 ath_print(common, ATH_DBG_FATAL,
579 "Failed to initialize MAC address\n");
580 return r;
581 }
582
583 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
584 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
585 else
586 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
587
588 if (AR_SREV_9300_20_OR_LATER(ah))
589 ar9003_hw_set_nf_limits(ah);
590
591 ath9k_init_nfcal_hist_buffer(ah);
592
593 common->state = ATH_HW_INITIALIZED;
594
595 return 0;
596 }
597
598 int ath9k_hw_init(struct ath_hw *ah)
599 {
600 int ret;
601 struct ath_common *common = ath9k_hw_common(ah);
602
603 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
604 switch (ah->hw_version.devid) {
605 case AR5416_DEVID_PCI:
606 case AR5416_DEVID_PCIE:
607 case AR5416_AR9100_DEVID:
608 case AR9160_DEVID_PCI:
609 case AR9280_DEVID_PCI:
610 case AR9280_DEVID_PCIE:
611 case AR9285_DEVID_PCIE:
612 case AR9287_DEVID_PCI:
613 case AR9287_DEVID_PCIE:
614 case AR2427_DEVID_PCIE:
615 case AR9300_DEVID_PCIE:
616 break;
617 default:
618 if (common->bus_ops->ath_bus_type == ATH_USB)
619 break;
620 ath_print(common, ATH_DBG_FATAL,
621 "Hardware device ID 0x%04x not supported\n",
622 ah->hw_version.devid);
623 return -EOPNOTSUPP;
624 }
625
626 ret = __ath9k_hw_init(ah);
627 if (ret) {
628 ath_print(common, ATH_DBG_FATAL,
629 "Unable to initialize hardware; "
630 "initialization status: %d\n", ret);
631 return ret;
632 }
633
634 return 0;
635 }
636 EXPORT_SYMBOL(ath9k_hw_init);
637
638 static void ath9k_hw_init_qos(struct ath_hw *ah)
639 {
640 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
641 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
642
643 REG_WRITE(ah, AR_QOS_NO_ACK,
644 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
645 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
646 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
647
648 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
649 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
650 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
651 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
652 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
653 }
654
655 static void ath9k_hw_init_pll(struct ath_hw *ah,
656 struct ath9k_channel *chan)
657 {
658 u32 pll = ath9k_hw_compute_pll_control(ah, chan);
659
660 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
661
662 /* Switch the core clock for ar9271 to 117Mhz */
663 if (AR_SREV_9271(ah)) {
664 udelay(500);
665 REG_WRITE(ah, 0x50040, 0x304);
666 }
667
668 udelay(RTC_PLL_SETTLE_DELAY);
669
670 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
671 }
672
673 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
674 enum nl80211_iftype opmode)
675 {
676 u32 imr_reg = AR_IMR_TXERR |
677 AR_IMR_TXURN |
678 AR_IMR_RXERR |
679 AR_IMR_RXORN |
680 AR_IMR_BCNMISC;
681
682 if (AR_SREV_9300_20_OR_LATER(ah)) {
683 imr_reg |= AR_IMR_RXOK_HP;
684 if (ah->config.rx_intr_mitigation)
685 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
686 else
687 imr_reg |= AR_IMR_RXOK_LP;
688
689 } else {
690 if (ah->config.rx_intr_mitigation)
691 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
692 else
693 imr_reg |= AR_IMR_RXOK;
694 }
695
696 if (ah->config.tx_intr_mitigation)
697 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
698 else
699 imr_reg |= AR_IMR_TXOK;
700
701 if (opmode == NL80211_IFTYPE_AP)
702 imr_reg |= AR_IMR_MIB;
703
704 REG_WRITE(ah, AR_IMR, imr_reg);
705 ah->imrs2_reg |= AR_IMR_S2_GTT;
706 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
707
708 if (!AR_SREV_9100(ah)) {
709 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
710 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
711 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
712 }
713
714 if (AR_SREV_9300_20_OR_LATER(ah)) {
715 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
716 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
717 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
718 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
719 }
720 }
721
722 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
723 {
724 u32 val = ath9k_hw_mac_to_clks(ah, us);
725 val = min(val, (u32) 0xFFFF);
726 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
727 }
728
729 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
730 {
731 u32 val = ath9k_hw_mac_to_clks(ah, us);
732 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
733 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
734 }
735
736 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
737 {
738 u32 val = ath9k_hw_mac_to_clks(ah, us);
739 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
740 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
741 }
742
743 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
744 {
745 if (tu > 0xFFFF) {
746 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
747 "bad global tx timeout %u\n", tu);
748 ah->globaltxtimeout = (u32) -1;
749 return false;
750 } else {
751 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
752 ah->globaltxtimeout = tu;
753 return true;
754 }
755 }
756
757 void ath9k_hw_init_global_settings(struct ath_hw *ah)
758 {
759 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
760 int acktimeout;
761 int slottime;
762 int sifstime;
763
764 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
765 ah->misc_mode);
766
767 if (ah->misc_mode != 0)
768 REG_WRITE(ah, AR_PCU_MISC,
769 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
770
771 if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
772 sifstime = 16;
773 else
774 sifstime = 10;
775
776 /* As defined by IEEE 802.11-2007 17.3.8.6 */
777 slottime = ah->slottime + 3 * ah->coverage_class;
778 acktimeout = slottime + sifstime;
779
780 /*
781 * Workaround for early ACK timeouts, add an offset to match the
782 * initval's 64us ack timeout value.
783 * This was initially only meant to work around an issue with delayed
784 * BA frames in some implementations, but it has been found to fix ACK
785 * timeout issues in other cases as well.
786 */
787 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
788 acktimeout += 64 - sifstime - ah->slottime;
789
790 ath9k_hw_setslottime(ah, slottime);
791 ath9k_hw_set_ack_timeout(ah, acktimeout);
792 ath9k_hw_set_cts_timeout(ah, acktimeout);
793 if (ah->globaltxtimeout != (u32) -1)
794 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
795 }
796 EXPORT_SYMBOL(ath9k_hw_init_global_settings);
797
798 void ath9k_hw_deinit(struct ath_hw *ah)
799 {
800 struct ath_common *common = ath9k_hw_common(ah);
801
802 if (common->state < ATH_HW_INITIALIZED)
803 goto free_hw;
804
805 if (!AR_SREV_9100(ah))
806 ath9k_hw_ani_disable(ah);
807
808 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
809
810 free_hw:
811 ath9k_hw_rf_free_ext_banks(ah);
812 }
813 EXPORT_SYMBOL(ath9k_hw_deinit);
814
815 /*******/
816 /* INI */
817 /*******/
818
819 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
820 {
821 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
822
823 if (IS_CHAN_B(chan))
824 ctl |= CTL_11B;
825 else if (IS_CHAN_G(chan))
826 ctl |= CTL_11G;
827 else
828 ctl |= CTL_11A;
829
830 return ctl;
831 }
832
833 /****************************************/
834 /* Reset and Channel Switching Routines */
835 /****************************************/
836
837 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
838 {
839 u32 regval;
840
841 /*
842 * set AHB_MODE not to do cacheline prefetches
843 */
844 regval = REG_READ(ah, AR_AHB_MODE);
845 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
846
847 /*
848 * let mac dma reads be in 128 byte chunks
849 */
850 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
851 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
852
853 /*
854 * Restore TX Trigger Level to its pre-reset value.
855 * The initial value depends on whether aggregation is enabled, and is
856 * adjusted whenever underruns are detected.
857 */
858 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
859
860 /*
861 * let mac dma writes be in 128 byte chunks
862 */
863 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
864 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
865
866 /*
867 * Setup receive FIFO threshold to hold off TX activities
868 */
869 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
870
871 /*
872 * reduce the number of usable entries in PCU TXBUF to avoid
873 * wrap around issues.
874 */
875 if (AR_SREV_9285(ah)) {
876 /* For AR9285 the number of Fifos are reduced to half.
877 * So set the usable tx buf size also to half to
878 * avoid data/delimiter underruns
879 */
880 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
881 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
882 } else if (!AR_SREV_9271(ah)) {
883 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
884 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
885 }
886 }
887
888 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
889 {
890 u32 val;
891
892 val = REG_READ(ah, AR_STA_ID1);
893 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
894 switch (opmode) {
895 case NL80211_IFTYPE_AP:
896 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
897 | AR_STA_ID1_KSRCH_MODE);
898 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
899 break;
900 case NL80211_IFTYPE_ADHOC:
901 case NL80211_IFTYPE_MESH_POINT:
902 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
903 | AR_STA_ID1_KSRCH_MODE);
904 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
905 break;
906 case NL80211_IFTYPE_STATION:
907 case NL80211_IFTYPE_MONITOR:
908 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
909 break;
910 }
911 }
912
913 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
914 u32 *coef_mantissa, u32 *coef_exponent)
915 {
916 u32 coef_exp, coef_man;
917
918 for (coef_exp = 31; coef_exp > 0; coef_exp--)
919 if ((coef_scaled >> coef_exp) & 0x1)
920 break;
921
922 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
923
924 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
925
926 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
927 *coef_exponent = coef_exp - 16;
928 }
929
930 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
931 {
932 u32 rst_flags;
933 u32 tmpReg;
934
935 if (AR_SREV_9100(ah)) {
936 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
937 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
938 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
939 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
940 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
941 }
942
943 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
944 AR_RTC_FORCE_WAKE_ON_INT);
945
946 if (AR_SREV_9100(ah)) {
947 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
948 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
949 } else {
950 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
951 if (tmpReg &
952 (AR_INTR_SYNC_LOCAL_TIMEOUT |
953 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
954 u32 val;
955 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
956
957 val = AR_RC_HOSTIF;
958 if (!AR_SREV_9300_20_OR_LATER(ah))
959 val |= AR_RC_AHB;
960 REG_WRITE(ah, AR_RC, val);
961
962 } else if (!AR_SREV_9300_20_OR_LATER(ah))
963 REG_WRITE(ah, AR_RC, AR_RC_AHB);
964
965 rst_flags = AR_RTC_RC_MAC_WARM;
966 if (type == ATH9K_RESET_COLD)
967 rst_flags |= AR_RTC_RC_MAC_COLD;
968 }
969
970 REG_WRITE(ah, AR_RTC_RC, rst_flags);
971 udelay(50);
972
973 REG_WRITE(ah, AR_RTC_RC, 0);
974 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
975 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
976 "RTC stuck in MAC reset\n");
977 return false;
978 }
979
980 if (!AR_SREV_9100(ah))
981 REG_WRITE(ah, AR_RC, 0);
982
983 if (AR_SREV_9100(ah))
984 udelay(50);
985
986 return true;
987 }
988
989 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
990 {
991 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
992 AR_RTC_FORCE_WAKE_ON_INT);
993
994 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
995 REG_WRITE(ah, AR_RC, AR_RC_AHB);
996
997 REG_WRITE(ah, AR_RTC_RESET, 0);
998
999 if (!AR_SREV_9300_20_OR_LATER(ah))
1000 udelay(2);
1001
1002 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1003 REG_WRITE(ah, AR_RC, 0);
1004
1005 REG_WRITE(ah, AR_RTC_RESET, 1);
1006
1007 if (!ath9k_hw_wait(ah,
1008 AR_RTC_STATUS,
1009 AR_RTC_STATUS_M,
1010 AR_RTC_STATUS_ON,
1011 AH_WAIT_TIMEOUT)) {
1012 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1013 "RTC not waking up\n");
1014 return false;
1015 }
1016
1017 ath9k_hw_read_revisions(ah);
1018
1019 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1020 }
1021
1022 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1023 {
1024 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1025 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1026
1027 switch (type) {
1028 case ATH9K_RESET_POWER_ON:
1029 return ath9k_hw_set_reset_power_on(ah);
1030 case ATH9K_RESET_WARM:
1031 case ATH9K_RESET_COLD:
1032 return ath9k_hw_set_reset(ah, type);
1033 default:
1034 return false;
1035 }
1036 }
1037
1038 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1039 struct ath9k_channel *chan)
1040 {
1041 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
1042 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1043 return false;
1044 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1045 return false;
1046
1047 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1048 return false;
1049
1050 ah->chip_fullsleep = false;
1051 ath9k_hw_init_pll(ah, chan);
1052 ath9k_hw_set_rfmode(ah, chan);
1053
1054 return true;
1055 }
1056
1057 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1058 struct ath9k_channel *chan)
1059 {
1060 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1061 struct ath_common *common = ath9k_hw_common(ah);
1062 struct ieee80211_channel *channel = chan->chan;
1063 u32 qnum;
1064 int r;
1065
1066 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1067 if (ath9k_hw_numtxpending(ah, qnum)) {
1068 ath_print(common, ATH_DBG_QUEUE,
1069 "Transmit frames pending on "
1070 "queue %d\n", qnum);
1071 return false;
1072 }
1073 }
1074
1075 if (!ath9k_hw_rfbus_req(ah)) {
1076 ath_print(common, ATH_DBG_FATAL,
1077 "Could not kill baseband RX\n");
1078 return false;
1079 }
1080
1081 ath9k_hw_set_channel_regs(ah, chan);
1082
1083 r = ath9k_hw_rf_set_freq(ah, chan);
1084 if (r) {
1085 ath_print(common, ATH_DBG_FATAL,
1086 "Failed to set channel\n");
1087 return false;
1088 }
1089
1090 ah->eep_ops->set_txpower(ah, chan,
1091 ath9k_regd_get_ctl(regulatory, chan),
1092 channel->max_antenna_gain * 2,
1093 channel->max_power * 2,
1094 min((u32) MAX_RATE_POWER,
1095 (u32) regulatory->power_limit));
1096
1097 ath9k_hw_rfbus_done(ah);
1098
1099 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1100 ath9k_hw_set_delta_slope(ah, chan);
1101
1102 ath9k_hw_spur_mitigate_freq(ah, chan);
1103
1104 if (!chan->oneTimeCalsDone)
1105 chan->oneTimeCalsDone = true;
1106
1107 return true;
1108 }
1109
1110 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1111 bool bChannelChange)
1112 {
1113 struct ath_common *common = ath9k_hw_common(ah);
1114 u32 saveLedState;
1115 struct ath9k_channel *curchan = ah->curchan;
1116 u32 saveDefAntenna;
1117 u32 macStaId1;
1118 u64 tsf = 0;
1119 int i, r;
1120
1121 ah->txchainmask = common->tx_chainmask;
1122 ah->rxchainmask = common->rx_chainmask;
1123
1124 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1125 return -EIO;
1126
1127 if (curchan && !ah->chip_fullsleep)
1128 ath9k_hw_getnf(ah, curchan);
1129
1130 if (bChannelChange &&
1131 (ah->chip_fullsleep != true) &&
1132 (ah->curchan != NULL) &&
1133 (chan->channel != ah->curchan->channel) &&
1134 ((chan->channelFlags & CHANNEL_ALL) ==
1135 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
1136 !(AR_SREV_9280(ah) || IS_CHAN_A_5MHZ_SPACED(chan) ||
1137 IS_CHAN_A_5MHZ_SPACED(ah->curchan))) {
1138
1139 if (ath9k_hw_channel_change(ah, chan)) {
1140 ath9k_hw_loadnf(ah, ah->curchan);
1141 ath9k_hw_start_nfcal(ah);
1142 return 0;
1143 }
1144 }
1145
1146 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1147 if (saveDefAntenna == 0)
1148 saveDefAntenna = 1;
1149
1150 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1151
1152 /* For chips on which RTC reset is done, save TSF before it gets cleared */
1153 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1154 tsf = ath9k_hw_gettsf64(ah);
1155
1156 saveLedState = REG_READ(ah, AR_CFG_LED) &
1157 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1158 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1159
1160 ath9k_hw_mark_phy_inactive(ah);
1161
1162 /* Only required on the first reset */
1163 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1164 REG_WRITE(ah,
1165 AR9271_RESET_POWER_DOWN_CONTROL,
1166 AR9271_RADIO_RF_RST);
1167 udelay(50);
1168 }
1169
1170 if (!ath9k_hw_chip_reset(ah, chan)) {
1171 ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n");
1172 return -EINVAL;
1173 }
1174
1175 /* Only required on the first reset */
1176 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1177 ah->htc_reset_init = false;
1178 REG_WRITE(ah,
1179 AR9271_RESET_POWER_DOWN_CONTROL,
1180 AR9271_GATE_MAC_CTL);
1181 udelay(50);
1182 }
1183
1184 /* Restore TSF */
1185 if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1186 ath9k_hw_settsf64(ah, tsf);
1187
1188 if (AR_SREV_9280_10_OR_LATER(ah))
1189 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1190
1191 r = ath9k_hw_process_ini(ah, chan);
1192 if (r)
1193 return r;
1194
1195 /* Setup MFP options for CCMP */
1196 if (AR_SREV_9280_20_OR_LATER(ah)) {
1197 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1198 * frames when constructing CCMP AAD. */
1199 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1200 0xc7ff);
1201 ah->sw_mgmt_crypto = false;
1202 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1203 /* Disable hardware crypto for management frames */
1204 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1205 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1206 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1207 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1208 ah->sw_mgmt_crypto = true;
1209 } else
1210 ah->sw_mgmt_crypto = true;
1211
1212 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1213 ath9k_hw_set_delta_slope(ah, chan);
1214
1215 ath9k_hw_spur_mitigate_freq(ah, chan);
1216 ah->eep_ops->set_board_values(ah, chan);
1217
1218 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
1219 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
1220 | macStaId1
1221 | AR_STA_ID1_RTS_USE_DEF
1222 | (ah->config.
1223 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
1224 | ah->sta_id1_defaults);
1225 ath9k_hw_set_operating_mode(ah, ah->opmode);
1226
1227 ath_hw_setbssidmask(common);
1228
1229 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1230
1231 ath9k_hw_write_associd(ah);
1232
1233 REG_WRITE(ah, AR_ISR, ~0);
1234
1235 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1236
1237 r = ath9k_hw_rf_set_freq(ah, chan);
1238 if (r)
1239 return r;
1240
1241 for (i = 0; i < AR_NUM_DCU; i++)
1242 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1243
1244 ah->intr_txqs = 0;
1245 for (i = 0; i < ah->caps.total_queues; i++)
1246 ath9k_hw_resettxqueue(ah, i);
1247
1248 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
1249 ath9k_hw_init_qos(ah);
1250
1251 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1252 ath9k_enable_rfkill(ah);
1253
1254 ath9k_hw_init_global_settings(ah);
1255
1256 if (AR_SREV_9287_12_OR_LATER(ah)) {
1257 REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
1258 AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
1259 REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
1260 AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
1261 REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
1262 AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
1263
1264 REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
1265 REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
1266
1267 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
1268 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
1269 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
1270 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
1271 }
1272 if (AR_SREV_9287_12_OR_LATER(ah)) {
1273 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1274 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
1275 }
1276
1277 REG_WRITE(ah, AR_STA_ID1,
1278 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
1279
1280 ath9k_hw_set_dma(ah);
1281
1282 REG_WRITE(ah, AR_OBS, 8);
1283
1284 if (ah->config.rx_intr_mitigation) {
1285 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
1286 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
1287 }
1288
1289 ath9k_hw_init_bb(ah, chan);
1290
1291 if (!ath9k_hw_init_cal(ah, chan))
1292 return -EIO;
1293
1294 ath9k_hw_restore_chainmask(ah);
1295 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1296
1297 /*
1298 * For big endian systems turn on swapping for descriptors
1299 */
1300 if (AR_SREV_9100(ah)) {
1301 u32 mask;
1302 mask = REG_READ(ah, AR_CFG);
1303 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1304 ath_print(common, ATH_DBG_RESET,
1305 "CFG Byte Swap Set 0x%x\n", mask);
1306 } else {
1307 mask =
1308 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1309 REG_WRITE(ah, AR_CFG, mask);
1310 ath_print(common, ATH_DBG_RESET,
1311 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
1312 }
1313 } else {
1314 /* Configure AR9271 target WLAN */
1315 if (AR_SREV_9271(ah))
1316 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1317 #ifdef __BIG_ENDIAN
1318 else
1319 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1320 #endif
1321 }
1322
1323 if (ah->btcoex_hw.enabled)
1324 ath9k_hw_btcoex_enable(ah);
1325
1326 return 0;
1327 }
1328 EXPORT_SYMBOL(ath9k_hw_reset);
1329
1330 /************************/
1331 /* Key Cache Management */
1332 /************************/
1333
1334 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
1335 {
1336 u32 keyType;
1337
1338 if (entry >= ah->caps.keycache_size) {
1339 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1340 "keychache entry %u out of range\n", entry);
1341 return false;
1342 }
1343
1344 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
1345
1346 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
1347 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
1348 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
1349 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
1350 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
1351 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
1352 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
1353 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
1354
1355 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
1356 u16 micentry = entry + 64;
1357
1358 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
1359 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
1360 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
1361 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
1362
1363 }
1364
1365 return true;
1366 }
1367 EXPORT_SYMBOL(ath9k_hw_keyreset);
1368
1369 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
1370 {
1371 u32 macHi, macLo;
1372
1373 if (entry >= ah->caps.keycache_size) {
1374 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1375 "keychache entry %u out of range\n", entry);
1376 return false;
1377 }
1378
1379 if (mac != NULL) {
1380 macHi = (mac[5] << 8) | mac[4];
1381 macLo = (mac[3] << 24) |
1382 (mac[2] << 16) |
1383 (mac[1] << 8) |
1384 mac[0];
1385 macLo >>= 1;
1386 macLo |= (macHi & 1) << 31;
1387 macHi >>= 1;
1388 } else {
1389 macLo = macHi = 0;
1390 }
1391 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
1392 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
1393
1394 return true;
1395 }
1396 EXPORT_SYMBOL(ath9k_hw_keysetmac);
1397
1398 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
1399 const struct ath9k_keyval *k,
1400 const u8 *mac)
1401 {
1402 const struct ath9k_hw_capabilities *pCap = &ah->caps;
1403 struct ath_common *common = ath9k_hw_common(ah);
1404 u32 key0, key1, key2, key3, key4;
1405 u32 keyType;
1406
1407 if (entry >= pCap->keycache_size) {
1408 ath_print(common, ATH_DBG_FATAL,
1409 "keycache entry %u out of range\n", entry);
1410 return false;
1411 }
1412
1413 switch (k->kv_type) {
1414 case ATH9K_CIPHER_AES_OCB:
1415 keyType = AR_KEYTABLE_TYPE_AES;
1416 break;
1417 case ATH9K_CIPHER_AES_CCM:
1418 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
1419 ath_print(common, ATH_DBG_ANY,
1420 "AES-CCM not supported by mac rev 0x%x\n",
1421 ah->hw_version.macRev);
1422 return false;
1423 }
1424 keyType = AR_KEYTABLE_TYPE_CCM;
1425 break;
1426 case ATH9K_CIPHER_TKIP:
1427 keyType = AR_KEYTABLE_TYPE_TKIP;
1428 if (ATH9K_IS_MIC_ENABLED(ah)
1429 && entry + 64 >= pCap->keycache_size) {
1430 ath_print(common, ATH_DBG_ANY,
1431 "entry %u inappropriate for TKIP\n", entry);
1432 return false;
1433 }
1434 break;
1435 case ATH9K_CIPHER_WEP:
1436 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
1437 ath_print(common, ATH_DBG_ANY,
1438 "WEP key length %u too small\n", k->kv_len);
1439 return false;
1440 }
1441 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
1442 keyType = AR_KEYTABLE_TYPE_40;
1443 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
1444 keyType = AR_KEYTABLE_TYPE_104;
1445 else
1446 keyType = AR_KEYTABLE_TYPE_128;
1447 break;
1448 case ATH9K_CIPHER_CLR:
1449 keyType = AR_KEYTABLE_TYPE_CLR;
1450 break;
1451 default:
1452 ath_print(common, ATH_DBG_FATAL,
1453 "cipher %u not supported\n", k->kv_type);
1454 return false;
1455 }
1456
1457 key0 = get_unaligned_le32(k->kv_val + 0);
1458 key1 = get_unaligned_le16(k->kv_val + 4);
1459 key2 = get_unaligned_le32(k->kv_val + 6);
1460 key3 = get_unaligned_le16(k->kv_val + 10);
1461 key4 = get_unaligned_le32(k->kv_val + 12);
1462 if (k->kv_len <= WLAN_KEY_LEN_WEP104)
1463 key4 &= 0xff;
1464
1465 /*
1466 * Note: Key cache registers access special memory area that requires
1467 * two 32-bit writes to actually update the values in the internal
1468 * memory. Consequently, the exact order and pairs used here must be
1469 * maintained.
1470 */
1471
1472 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
1473 u16 micentry = entry + 64;
1474
1475 /*
1476 * Write inverted key[47:0] first to avoid Michael MIC errors
1477 * on frames that could be sent or received at the same time.
1478 * The correct key will be written in the end once everything
1479 * else is ready.
1480 */
1481 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
1482 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
1483
1484 /* Write key[95:48] */
1485 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
1486 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
1487
1488 /* Write key[127:96] and key type */
1489 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
1490 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
1491
1492 /* Write MAC address for the entry */
1493 (void) ath9k_hw_keysetmac(ah, entry, mac);
1494
1495 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
1496 /*
1497 * TKIP uses two key cache entries:
1498 * Michael MIC TX/RX keys in the same key cache entry
1499 * (idx = main index + 64):
1500 * key0 [31:0] = RX key [31:0]
1501 * key1 [15:0] = TX key [31:16]
1502 * key1 [31:16] = reserved
1503 * key2 [31:0] = RX key [63:32]
1504 * key3 [15:0] = TX key [15:0]
1505 * key3 [31:16] = reserved
1506 * key4 [31:0] = TX key [63:32]
1507 */
1508 u32 mic0, mic1, mic2, mic3, mic4;
1509
1510 mic0 = get_unaligned_le32(k->kv_mic + 0);
1511 mic2 = get_unaligned_le32(k->kv_mic + 4);
1512 mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
1513 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
1514 mic4 = get_unaligned_le32(k->kv_txmic + 4);
1515
1516 /* Write RX[31:0] and TX[31:16] */
1517 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
1518 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
1519
1520 /* Write RX[63:32] and TX[15:0] */
1521 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
1522 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
1523
1524 /* Write TX[63:32] and keyType(reserved) */
1525 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
1526 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
1527 AR_KEYTABLE_TYPE_CLR);
1528
1529 } else {
1530 /*
1531 * TKIP uses four key cache entries (two for group
1532 * keys):
1533 * Michael MIC TX/RX keys are in different key cache
1534 * entries (idx = main index + 64 for TX and
1535 * main index + 32 + 96 for RX):
1536 * key0 [31:0] = TX/RX MIC key [31:0]
1537 * key1 [31:0] = reserved
1538 * key2 [31:0] = TX/RX MIC key [63:32]
1539 * key3 [31:0] = reserved
1540 * key4 [31:0] = reserved
1541 *
1542 * Upper layer code will call this function separately
1543 * for TX and RX keys when these registers offsets are
1544 * used.
1545 */
1546 u32 mic0, mic2;
1547
1548 mic0 = get_unaligned_le32(k->kv_mic + 0);
1549 mic2 = get_unaligned_le32(k->kv_mic + 4);
1550
1551 /* Write MIC key[31:0] */
1552 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
1553 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
1554
1555 /* Write MIC key[63:32] */
1556 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
1557 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
1558
1559 /* Write TX[63:32] and keyType(reserved) */
1560 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
1561 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
1562 AR_KEYTABLE_TYPE_CLR);
1563 }
1564
1565 /* MAC address registers are reserved for the MIC entry */
1566 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
1567 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
1568
1569 /*
1570 * Write the correct (un-inverted) key[47:0] last to enable
1571 * TKIP now that all other registers are set with correct
1572 * values.
1573 */
1574 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
1575 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
1576 } else {
1577 /* Write key[47:0] */
1578 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
1579 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
1580
1581 /* Write key[95:48] */
1582 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
1583 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
1584
1585 /* Write key[127:96] and key type */
1586 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
1587 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
1588
1589 /* Write MAC address for the entry */
1590 (void) ath9k_hw_keysetmac(ah, entry, mac);
1591 }
1592
1593 return true;
1594 }
1595 EXPORT_SYMBOL(ath9k_hw_set_keycache_entry);
1596
1597 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
1598 {
1599 if (entry < ah->caps.keycache_size) {
1600 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
1601 if (val & AR_KEYTABLE_VALID)
1602 return true;
1603 }
1604 return false;
1605 }
1606 EXPORT_SYMBOL(ath9k_hw_keyisvalid);
1607
1608 /******************************/
1609 /* Power Management (Chipset) */
1610 /******************************/
1611
1612 /*
1613 * Notify Power Mgt is disabled in self-generated frames.
1614 * If requested, force chip to sleep.
1615 */
1616 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
1617 {
1618 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1619 if (setChip) {
1620 /*
1621 * Clear the RTC force wake bit to allow the
1622 * mac to go to sleep.
1623 */
1624 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1625 AR_RTC_FORCE_WAKE_EN);
1626 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1627 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1628
1629 /* Shutdown chip. Active low */
1630 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah))
1631 REG_CLR_BIT(ah, (AR_RTC_RESET),
1632 AR_RTC_RESET_EN);
1633 }
1634 }
1635
1636 /*
1637 * Notify Power Management is enabled in self-generating
1638 * frames. If request, set power mode of chip to
1639 * auto/normal. Duration in units of 128us (1/8 TU).
1640 */
1641 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
1642 {
1643 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1644 if (setChip) {
1645 struct ath9k_hw_capabilities *pCap = &ah->caps;
1646
1647 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1648 /* Set WakeOnInterrupt bit; clear ForceWake bit */
1649 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1650 AR_RTC_FORCE_WAKE_ON_INT);
1651 } else {
1652 /*
1653 * Clear the RTC force wake bit to allow the
1654 * mac to go to sleep.
1655 */
1656 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1657 AR_RTC_FORCE_WAKE_EN);
1658 }
1659 }
1660 }
1661
1662 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
1663 {
1664 u32 val;
1665 int i;
1666
1667 if (setChip) {
1668 if ((REG_READ(ah, AR_RTC_STATUS) &
1669 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
1670 if (ath9k_hw_set_reset_reg(ah,
1671 ATH9K_RESET_POWER_ON) != true) {
1672 return false;
1673 }
1674 if (!AR_SREV_9300_20_OR_LATER(ah))
1675 ath9k_hw_init_pll(ah, NULL);
1676 }
1677 if (AR_SREV_9100(ah))
1678 REG_SET_BIT(ah, AR_RTC_RESET,
1679 AR_RTC_RESET_EN);
1680
1681 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1682 AR_RTC_FORCE_WAKE_EN);
1683 udelay(50);
1684
1685 for (i = POWER_UP_TIME / 50; i > 0; i--) {
1686 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
1687 if (val == AR_RTC_STATUS_ON)
1688 break;
1689 udelay(50);
1690 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1691 AR_RTC_FORCE_WAKE_EN);
1692 }
1693 if (i == 0) {
1694 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1695 "Failed to wakeup in %uus\n",
1696 POWER_UP_TIME / 20);
1697 return false;
1698 }
1699 }
1700
1701 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1702
1703 return true;
1704 }
1705
1706 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
1707 {
1708 struct ath_common *common = ath9k_hw_common(ah);
1709 int status = true, setChip = true;
1710 static const char *modes[] = {
1711 "AWAKE",
1712 "FULL-SLEEP",
1713 "NETWORK SLEEP",
1714 "UNDEFINED"
1715 };
1716
1717 if (ah->power_mode == mode)
1718 return status;
1719
1720 ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
1721 modes[ah->power_mode], modes[mode]);
1722
1723 switch (mode) {
1724 case ATH9K_PM_AWAKE:
1725 status = ath9k_hw_set_power_awake(ah, setChip);
1726 break;
1727 case ATH9K_PM_FULL_SLEEP:
1728 ath9k_set_power_sleep(ah, setChip);
1729 ah->chip_fullsleep = true;
1730 break;
1731 case ATH9K_PM_NETWORK_SLEEP:
1732 ath9k_set_power_network_sleep(ah, setChip);
1733 break;
1734 default:
1735 ath_print(common, ATH_DBG_FATAL,
1736 "Unknown power mode %u\n", mode);
1737 return false;
1738 }
1739 ah->power_mode = mode;
1740
1741 return status;
1742 }
1743 EXPORT_SYMBOL(ath9k_hw_setpower);
1744
1745 /*******************/
1746 /* Beacon Handling */
1747 /*******************/
1748
1749 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
1750 {
1751 int flags = 0;
1752
1753 ah->beacon_interval = beacon_period;
1754
1755 switch (ah->opmode) {
1756 case NL80211_IFTYPE_STATION:
1757 case NL80211_IFTYPE_MONITOR:
1758 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
1759 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
1760 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
1761 flags |= AR_TBTT_TIMER_EN;
1762 break;
1763 case NL80211_IFTYPE_ADHOC:
1764 case NL80211_IFTYPE_MESH_POINT:
1765 REG_SET_BIT(ah, AR_TXCFG,
1766 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
1767 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
1768 TU_TO_USEC(next_beacon +
1769 (ah->atim_window ? ah->
1770 atim_window : 1)));
1771 flags |= AR_NDP_TIMER_EN;
1772 case NL80211_IFTYPE_AP:
1773 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
1774 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
1775 TU_TO_USEC(next_beacon -
1776 ah->config.
1777 dma_beacon_response_time));
1778 REG_WRITE(ah, AR_NEXT_SWBA,
1779 TU_TO_USEC(next_beacon -
1780 ah->config.
1781 sw_beacon_response_time));
1782 flags |=
1783 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
1784 break;
1785 default:
1786 ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
1787 "%s: unsupported opmode: %d\n",
1788 __func__, ah->opmode);
1789 return;
1790 break;
1791 }
1792
1793 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
1794 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
1795 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
1796 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
1797
1798 beacon_period &= ~ATH9K_BEACON_ENA;
1799 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
1800 ath9k_hw_reset_tsf(ah);
1801 }
1802
1803 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
1804 }
1805 EXPORT_SYMBOL(ath9k_hw_beaconinit);
1806
1807 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
1808 const struct ath9k_beacon_state *bs)
1809 {
1810 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
1811 struct ath9k_hw_capabilities *pCap = &ah->caps;
1812 struct ath_common *common = ath9k_hw_common(ah);
1813
1814 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
1815
1816 REG_WRITE(ah, AR_BEACON_PERIOD,
1817 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1818 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
1819 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1820
1821 REG_RMW_FIELD(ah, AR_RSSI_THR,
1822 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
1823
1824 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
1825
1826 if (bs->bs_sleepduration > beaconintval)
1827 beaconintval = bs->bs_sleepduration;
1828
1829 dtimperiod = bs->bs_dtimperiod;
1830 if (bs->bs_sleepduration > dtimperiod)
1831 dtimperiod = bs->bs_sleepduration;
1832
1833 if (beaconintval == dtimperiod)
1834 nextTbtt = bs->bs_nextdtim;
1835 else
1836 nextTbtt = bs->bs_nexttbtt;
1837
1838 ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
1839 ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
1840 ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
1841 ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
1842
1843 REG_WRITE(ah, AR_NEXT_DTIM,
1844 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
1845 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
1846
1847 REG_WRITE(ah, AR_SLEEP1,
1848 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
1849 | AR_SLEEP1_ASSUME_DTIM);
1850
1851 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
1852 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
1853 else
1854 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
1855
1856 REG_WRITE(ah, AR_SLEEP2,
1857 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
1858
1859 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
1860 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
1861
1862 REG_SET_BIT(ah, AR_TIMER_MODE,
1863 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
1864 AR_DTIM_TIMER_EN);
1865
1866 /* TSF Out of Range Threshold */
1867 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
1868 }
1869 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
1870
1871 /*******************/
1872 /* HW Capabilities */
1873 /*******************/
1874
1875 int ath9k_hw_fill_cap_info(struct ath_hw *ah)
1876 {
1877 struct ath9k_hw_capabilities *pCap = &ah->caps;
1878 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1879 struct ath_common *common = ath9k_hw_common(ah);
1880 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
1881
1882 u16 capField = 0, eeval;
1883
1884 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
1885 regulatory->current_rd = eeval;
1886
1887 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
1888 if (AR_SREV_9285_10_OR_LATER(ah))
1889 eeval |= AR9285_RDEXT_DEFAULT;
1890 regulatory->current_rd_ext = eeval;
1891
1892 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
1893
1894 if (ah->opmode != NL80211_IFTYPE_AP &&
1895 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
1896 if (regulatory->current_rd == 0x64 ||
1897 regulatory->current_rd == 0x65)
1898 regulatory->current_rd += 5;
1899 else if (regulatory->current_rd == 0x41)
1900 regulatory->current_rd = 0x43;
1901 ath_print(common, ATH_DBG_REGULATORY,
1902 "regdomain mapped to 0x%x\n", regulatory->current_rd);
1903 }
1904
1905 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
1906 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
1907 ath_print(common, ATH_DBG_FATAL,
1908 "no band has been marked as supported in EEPROM.\n");
1909 return -EINVAL;
1910 }
1911
1912 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
1913
1914 if (eeval & AR5416_OPFLAGS_11A) {
1915 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
1916 if (ah->config.ht_enable) {
1917 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
1918 set_bit(ATH9K_MODE_11NA_HT20,
1919 pCap->wireless_modes);
1920 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
1921 set_bit(ATH9K_MODE_11NA_HT40PLUS,
1922 pCap->wireless_modes);
1923 set_bit(ATH9K_MODE_11NA_HT40MINUS,
1924 pCap->wireless_modes);
1925 }
1926 }
1927 }
1928
1929 if (eeval & AR5416_OPFLAGS_11G) {
1930 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
1931 if (ah->config.ht_enable) {
1932 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
1933 set_bit(ATH9K_MODE_11NG_HT20,
1934 pCap->wireless_modes);
1935 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
1936 set_bit(ATH9K_MODE_11NG_HT40PLUS,
1937 pCap->wireless_modes);
1938 set_bit(ATH9K_MODE_11NG_HT40MINUS,
1939 pCap->wireless_modes);
1940 }
1941 }
1942 }
1943
1944 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
1945 /*
1946 * For AR9271 we will temporarilly uses the rx chainmax as read from
1947 * the EEPROM.
1948 */
1949 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
1950 !(eeval & AR5416_OPFLAGS_11A) &&
1951 !(AR_SREV_9271(ah)))
1952 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
1953 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
1954 else
1955 /* Use rx_chainmask from EEPROM. */
1956 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
1957
1958 if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
1959 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
1960
1961 pCap->low_2ghz_chan = 2312;
1962 pCap->high_2ghz_chan = 2732;
1963
1964 pCap->low_5ghz_chan = 4920;
1965 pCap->high_5ghz_chan = 6100;
1966
1967 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
1968 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
1969 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
1970
1971 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
1972 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
1973 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
1974
1975 if (ah->config.ht_enable)
1976 pCap->hw_caps |= ATH9K_HW_CAP_HT;
1977 else
1978 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
1979
1980 pCap->hw_caps |= ATH9K_HW_CAP_GTT;
1981 pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
1982 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
1983 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
1984
1985 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
1986 pCap->total_queues =
1987 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
1988 else
1989 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
1990
1991 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
1992 pCap->keycache_size =
1993 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
1994 else
1995 pCap->keycache_size = AR_KEYTABLE_SIZE;
1996
1997 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
1998
1999 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
2000 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1;
2001 else
2002 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
2003
2004 if (AR_SREV_9271(ah))
2005 pCap->num_gpio_pins = AR9271_NUM_GPIO;
2006 else if (AR_SREV_9285_10_OR_LATER(ah))
2007 pCap->num_gpio_pins = AR9285_NUM_GPIO;
2008 else if (AR_SREV_9280_10_OR_LATER(ah))
2009 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2010 else
2011 pCap->num_gpio_pins = AR_NUM_GPIO;
2012
2013 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
2014 pCap->hw_caps |= ATH9K_HW_CAP_CST;
2015 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
2016 } else {
2017 pCap->rts_aggr_limit = (8 * 1024);
2018 }
2019
2020 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
2021
2022 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2023 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2024 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2025 ah->rfkill_gpio =
2026 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2027 ah->rfkill_polarity =
2028 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
2029
2030 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
2031 }
2032 #endif
2033 if (AR_SREV_9271(ah))
2034 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2035 else
2036 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
2037
2038 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
2039 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2040 else
2041 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
2042
2043 if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
2044 pCap->reg_cap =
2045 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
2046 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
2047 AR_EEPROM_EEREGCAP_EN_KK_U2 |
2048 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
2049 } else {
2050 pCap->reg_cap =
2051 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
2052 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
2053 }
2054
2055 /* Advertise midband for AR5416 with FCC midband set in eeprom */
2056 if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
2057 AR_SREV_5416(ah))
2058 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
2059
2060 pCap->num_antcfg_5ghz =
2061 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
2062 pCap->num_antcfg_2ghz =
2063 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
2064
2065 if (AR_SREV_9280_10_OR_LATER(ah) &&
2066 ath9k_hw_btcoex_supported(ah)) {
2067 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
2068 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
2069
2070 if (AR_SREV_9285(ah)) {
2071 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
2072 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
2073 } else {
2074 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
2075 }
2076 } else {
2077 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
2078 }
2079
2080 if (AR_SREV_9300_20_OR_LATER(ah)) {
2081 pCap->hw_caps |= ATH9K_HW_CAP_EDMA;
2082 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2083 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2084 pCap->rx_status_len = sizeof(struct ar9003_rxs);
2085 pCap->tx_desc_len = sizeof(struct ar9003_txc);
2086 } else {
2087 pCap->tx_desc_len = sizeof(struct ath_desc);
2088 }
2089
2090 if (AR_SREV_9300_20_OR_LATER(ah))
2091 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2092
2093 return 0;
2094 }
2095
2096 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
2097 u32 capability, u32 *result)
2098 {
2099 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2100 switch (type) {
2101 case ATH9K_CAP_CIPHER:
2102 switch (capability) {
2103 case ATH9K_CIPHER_AES_CCM:
2104 case ATH9K_CIPHER_AES_OCB:
2105 case ATH9K_CIPHER_TKIP:
2106 case ATH9K_CIPHER_WEP:
2107 case ATH9K_CIPHER_MIC:
2108 case ATH9K_CIPHER_CLR:
2109 return true;
2110 default:
2111 return false;
2112 }
2113 case ATH9K_CAP_TKIP_MIC:
2114 switch (capability) {
2115 case 0:
2116 return true;
2117 case 1:
2118 return (ah->sta_id1_defaults &
2119 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
2120 false;
2121 }
2122 case ATH9K_CAP_TKIP_SPLIT:
2123 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
2124 false : true;
2125 case ATH9K_CAP_MCAST_KEYSRCH:
2126 switch (capability) {
2127 case 0:
2128 return true;
2129 case 1:
2130 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
2131 return false;
2132 } else {
2133 return (ah->sta_id1_defaults &
2134 AR_STA_ID1_MCAST_KSRCH) ? true :
2135 false;
2136 }
2137 }
2138 return false;
2139 case ATH9K_CAP_TXPOW:
2140 switch (capability) {
2141 case 0:
2142 return 0;
2143 case 1:
2144 *result = regulatory->power_limit;
2145 return 0;
2146 case 2:
2147 *result = regulatory->max_power_level;
2148 return 0;
2149 case 3:
2150 *result = regulatory->tp_scale;
2151 return 0;
2152 }
2153 return false;
2154 case ATH9K_CAP_DS:
2155 return (AR_SREV_9280_20_OR_LATER(ah) &&
2156 (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
2157 ? false : true;
2158 default:
2159 return false;
2160 }
2161 }
2162 EXPORT_SYMBOL(ath9k_hw_getcapability);
2163
2164 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
2165 u32 capability, u32 setting, int *status)
2166 {
2167 switch (type) {
2168 case ATH9K_CAP_TKIP_MIC:
2169 if (setting)
2170 ah->sta_id1_defaults |=
2171 AR_STA_ID1_CRPT_MIC_ENABLE;
2172 else
2173 ah->sta_id1_defaults &=
2174 ~AR_STA_ID1_CRPT_MIC_ENABLE;
2175 return true;
2176 case ATH9K_CAP_MCAST_KEYSRCH:
2177 if (setting)
2178 ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
2179 else
2180 ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
2181 return true;
2182 default:
2183 return false;
2184 }
2185 }
2186 EXPORT_SYMBOL(ath9k_hw_setcapability);
2187
2188 /****************************/
2189 /* GPIO / RFKILL / Antennae */
2190 /****************************/
2191
2192 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
2193 u32 gpio, u32 type)
2194 {
2195 int addr;
2196 u32 gpio_shift, tmp;
2197
2198 if (gpio > 11)
2199 addr = AR_GPIO_OUTPUT_MUX3;
2200 else if (gpio > 5)
2201 addr = AR_GPIO_OUTPUT_MUX2;
2202 else
2203 addr = AR_GPIO_OUTPUT_MUX1;
2204
2205 gpio_shift = (gpio % 6) * 5;
2206
2207 if (AR_SREV_9280_20_OR_LATER(ah)
2208 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2209 REG_RMW(ah, addr, (type << gpio_shift),
2210 (0x1f << gpio_shift));
2211 } else {
2212 tmp = REG_READ(ah, addr);
2213 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2214 tmp &= ~(0x1f << gpio_shift);
2215 tmp |= (type << gpio_shift);
2216 REG_WRITE(ah, addr, tmp);
2217 }
2218 }
2219
2220 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
2221 {
2222 u32 gpio_shift;
2223
2224 BUG_ON(gpio >= ah->caps.num_gpio_pins);
2225
2226 gpio_shift = gpio << 1;
2227
2228 REG_RMW(ah,
2229 AR_GPIO_OE_OUT,
2230 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2231 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2232 }
2233 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
2234
2235 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
2236 {
2237 #define MS_REG_READ(x, y) \
2238 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2239
2240 if (gpio >= ah->caps.num_gpio_pins)
2241 return 0xffffffff;
2242
2243 if (AR_SREV_9300_20_OR_LATER(ah))
2244 return MS_REG_READ(AR9300, gpio) != 0;
2245 else if (AR_SREV_9271(ah))
2246 return MS_REG_READ(AR9271, gpio) != 0;
2247 else if (AR_SREV_9287_10_OR_LATER(ah))
2248 return MS_REG_READ(AR9287, gpio) != 0;
2249 else if (AR_SREV_9285_10_OR_LATER(ah))
2250 return MS_REG_READ(AR9285, gpio) != 0;
2251 else if (AR_SREV_9280_10_OR_LATER(ah))
2252 return MS_REG_READ(AR928X, gpio) != 0;
2253 else
2254 return MS_REG_READ(AR, gpio) != 0;
2255 }
2256 EXPORT_SYMBOL(ath9k_hw_gpio_get);
2257
2258 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
2259 u32 ah_signal_type)
2260 {
2261 u32 gpio_shift;
2262
2263 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
2264
2265 gpio_shift = 2 * gpio;
2266
2267 REG_RMW(ah,
2268 AR_GPIO_OE_OUT,
2269 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2270 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2271 }
2272 EXPORT_SYMBOL(ath9k_hw_cfg_output);
2273
2274 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
2275 {
2276 if (AR_SREV_9271(ah))
2277 val = ~val;
2278
2279 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2280 AR_GPIO_BIT(gpio));
2281 }
2282 EXPORT_SYMBOL(ath9k_hw_set_gpio);
2283
2284 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
2285 {
2286 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
2287 }
2288 EXPORT_SYMBOL(ath9k_hw_getdefantenna);
2289
2290 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
2291 {
2292 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
2293 }
2294 EXPORT_SYMBOL(ath9k_hw_setantenna);
2295
2296 /*********************/
2297 /* General Operation */
2298 /*********************/
2299
2300 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
2301 {
2302 u32 bits = REG_READ(ah, AR_RX_FILTER);
2303 u32 phybits = REG_READ(ah, AR_PHY_ERR);
2304
2305 if (phybits & AR_PHY_ERR_RADAR)
2306 bits |= ATH9K_RX_FILTER_PHYRADAR;
2307 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2308 bits |= ATH9K_RX_FILTER_PHYERR;
2309
2310 return bits;
2311 }
2312 EXPORT_SYMBOL(ath9k_hw_getrxfilter);
2313
2314 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
2315 {
2316 u32 phybits;
2317
2318 REG_WRITE(ah, AR_RX_FILTER, bits);
2319
2320 phybits = 0;
2321 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2322 phybits |= AR_PHY_ERR_RADAR;
2323 if (bits & ATH9K_RX_FILTER_PHYERR)
2324 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2325 REG_WRITE(ah, AR_PHY_ERR, phybits);
2326
2327 if (phybits)
2328 REG_WRITE(ah, AR_RXCFG,
2329 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
2330 else
2331 REG_WRITE(ah, AR_RXCFG,
2332 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
2333 }
2334 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
2335
2336 bool ath9k_hw_phy_disable(struct ath_hw *ah)
2337 {
2338 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2339 return false;
2340
2341 ath9k_hw_init_pll(ah, NULL);
2342 return true;
2343 }
2344 EXPORT_SYMBOL(ath9k_hw_phy_disable);
2345
2346 bool ath9k_hw_disable(struct ath_hw *ah)
2347 {
2348 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2349 return false;
2350
2351 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2352 return false;
2353
2354 ath9k_hw_init_pll(ah, NULL);
2355 return true;
2356 }
2357 EXPORT_SYMBOL(ath9k_hw_disable);
2358
2359 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
2360 {
2361 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2362 struct ath9k_channel *chan = ah->curchan;
2363 struct ieee80211_channel *channel = chan->chan;
2364
2365 regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
2366
2367 ah->eep_ops->set_txpower(ah, chan,
2368 ath9k_regd_get_ctl(regulatory, chan),
2369 channel->max_antenna_gain * 2,
2370 channel->max_power * 2,
2371 min((u32) MAX_RATE_POWER,
2372 (u32) regulatory->power_limit));
2373 }
2374 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
2375
2376 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
2377 {
2378 memcpy(ath9k_hw_common(ah)->macaddr, mac, ETH_ALEN);
2379 }
2380 EXPORT_SYMBOL(ath9k_hw_setmac);
2381
2382 void ath9k_hw_setopmode(struct ath_hw *ah)
2383 {
2384 ath9k_hw_set_operating_mode(ah, ah->opmode);
2385 }
2386 EXPORT_SYMBOL(ath9k_hw_setopmode);
2387
2388 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
2389 {
2390 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2391 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
2392 }
2393 EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
2394
2395 void ath9k_hw_write_associd(struct ath_hw *ah)
2396 {
2397 struct ath_common *common = ath9k_hw_common(ah);
2398
2399 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2400 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2401 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2402 }
2403 EXPORT_SYMBOL(ath9k_hw_write_associd);
2404
2405 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
2406 {
2407 u64 tsf;
2408
2409 tsf = REG_READ(ah, AR_TSF_U32);
2410 tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
2411
2412 return tsf;
2413 }
2414 EXPORT_SYMBOL(ath9k_hw_gettsf64);
2415
2416 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
2417 {
2418 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
2419 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
2420 }
2421 EXPORT_SYMBOL(ath9k_hw_settsf64);
2422
2423 void ath9k_hw_reset_tsf(struct ath_hw *ah)
2424 {
2425 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2426 AH_TSF_WRITE_TIMEOUT))
2427 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
2428 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
2429
2430 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2431 }
2432 EXPORT_SYMBOL(ath9k_hw_reset_tsf);
2433
2434 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
2435 {
2436 if (setting)
2437 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
2438 else
2439 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
2440 }
2441 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
2442
2443 /*
2444 * Extend 15-bit time stamp from rx descriptor to
2445 * a full 64-bit TSF using the current h/w TSF.
2446 */
2447 u64 ath9k_hw_extend_tsf(struct ath_hw *ah, u32 rstamp)
2448 {
2449 u64 tsf;
2450
2451 tsf = ath9k_hw_gettsf64(ah);
2452 if ((tsf & 0x7fff) < rstamp)
2453 tsf -= 0x8000;
2454 return (tsf & ~0x7fff) | rstamp;
2455 }
2456 EXPORT_SYMBOL(ath9k_hw_extend_tsf);
2457
2458 void ath9k_hw_set11nmac2040(struct ath_hw *ah)
2459 {
2460 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
2461 u32 macmode;
2462
2463 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
2464 macmode = AR_2040_JOINED_RX_CLEAR;
2465 else
2466 macmode = 0;
2467
2468 REG_WRITE(ah, AR_2040_MODE, macmode);
2469 }
2470
2471 /* HW Generic timers configuration */
2472
2473 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2474 {
2475 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2476 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2477 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2478 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2479 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2480 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2481 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2482 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2483 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2484 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2485 AR_NDP2_TIMER_MODE, 0x0002},
2486 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2487 AR_NDP2_TIMER_MODE, 0x0004},
2488 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2489 AR_NDP2_TIMER_MODE, 0x0008},
2490 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2491 AR_NDP2_TIMER_MODE, 0x0010},
2492 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2493 AR_NDP2_TIMER_MODE, 0x0020},
2494 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2495 AR_NDP2_TIMER_MODE, 0x0040},
2496 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2497 AR_NDP2_TIMER_MODE, 0x0080}
2498 };
2499
2500 /* HW generic timer primitives */
2501
2502 /* compute and clear index of rightmost 1 */
2503 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
2504 {
2505 u32 b;
2506
2507 b = *mask;
2508 b &= (0-b);
2509 *mask &= ~b;
2510 b *= debruijn32;
2511 b >>= 27;
2512
2513 return timer_table->gen_timer_index[b];
2514 }
2515
2516 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
2517 {
2518 return REG_READ(ah, AR_TSF_L32);
2519 }
2520 EXPORT_SYMBOL(ath9k_hw_gettsf32);
2521
2522 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2523 void (*trigger)(void *),
2524 void (*overflow)(void *),
2525 void *arg,
2526 u8 timer_index)
2527 {
2528 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2529 struct ath_gen_timer *timer;
2530
2531 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
2532
2533 if (timer == NULL) {
2534 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2535 "Failed to allocate memory"
2536 "for hw timer[%d]\n", timer_index);
2537 return NULL;
2538 }
2539
2540 /* allocate a hardware generic timer slot */
2541 timer_table->timers[timer_index] = timer;
2542 timer->index = timer_index;
2543 timer->trigger = trigger;
2544 timer->overflow = overflow;
2545 timer->arg = arg;
2546
2547 return timer;
2548 }
2549 EXPORT_SYMBOL(ath_gen_timer_alloc);
2550
2551 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2552 struct ath_gen_timer *timer,
2553 u32 timer_next,
2554 u32 timer_period)
2555 {
2556 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2557 u32 tsf;
2558
2559 BUG_ON(!timer_period);
2560
2561 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
2562
2563 tsf = ath9k_hw_gettsf32(ah);
2564
2565 ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
2566 "curent tsf %x period %x"
2567 "timer_next %x\n", tsf, timer_period, timer_next);
2568
2569 /*
2570 * Pull timer_next forward if the current TSF already passed it
2571 * because of software latency
2572 */
2573 if (timer_next < tsf)
2574 timer_next = tsf + timer_period;
2575
2576 /*
2577 * Program generic timer registers
2578 */
2579 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
2580 timer_next);
2581 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
2582 timer_period);
2583 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2584 gen_tmr_configuration[timer->index].mode_mask);
2585
2586 /* Enable both trigger and thresh interrupt masks */
2587 REG_SET_BIT(ah, AR_IMR_S5,
2588 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2589 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2590 }
2591 EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
2592
2593 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
2594 {
2595 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2596
2597 if ((timer->index < AR_FIRST_NDP_TIMER) ||
2598 (timer->index >= ATH_MAX_GEN_TIMER)) {
2599 return;
2600 }
2601
2602 /* Clear generic timer enable bits. */
2603 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2604 gen_tmr_configuration[timer->index].mode_mask);
2605
2606 /* Disable both trigger and thresh interrupt masks */
2607 REG_CLR_BIT(ah, AR_IMR_S5,
2608 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2609 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2610
2611 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
2612 }
2613 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
2614
2615 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
2616 {
2617 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2618
2619 /* free the hardware generic timer slot */
2620 timer_table->timers[timer->index] = NULL;
2621 kfree(timer);
2622 }
2623 EXPORT_SYMBOL(ath_gen_timer_free);
2624
2625 /*
2626 * Generic Timer Interrupts handling
2627 */
2628 void ath_gen_timer_isr(struct ath_hw *ah)
2629 {
2630 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2631 struct ath_gen_timer *timer;
2632 struct ath_common *common = ath9k_hw_common(ah);
2633 u32 trigger_mask, thresh_mask, index;
2634
2635 /* get hardware generic timer interrupt status */
2636 trigger_mask = ah->intr_gen_timer_trigger;
2637 thresh_mask = ah->intr_gen_timer_thresh;
2638 trigger_mask &= timer_table->timer_mask.val;
2639 thresh_mask &= timer_table->timer_mask.val;
2640
2641 trigger_mask &= ~thresh_mask;
2642
2643 while (thresh_mask) {
2644 index = rightmost_index(timer_table, &thresh_mask);
2645 timer = timer_table->timers[index];
2646 BUG_ON(!timer);
2647 ath_print(common, ATH_DBG_HWTIMER,
2648 "TSF overflow for Gen timer %d\n", index);
2649 timer->overflow(timer->arg);
2650 }
2651
2652 while (trigger_mask) {
2653 index = rightmost_index(timer_table, &trigger_mask);
2654 timer = timer_table->timers[index];
2655 BUG_ON(!timer);
2656 ath_print(common, ATH_DBG_HWTIMER,
2657 "Gen timer[%d] trigger\n", index);
2658 timer->trigger(timer->arg);
2659 }
2660 }
2661 EXPORT_SYMBOL(ath_gen_timer_isr);
2662
2663 /********/
2664 /* HTC */
2665 /********/
2666
2667 void ath9k_hw_htc_resetinit(struct ath_hw *ah)
2668 {
2669 ah->htc_reset_init = true;
2670 }
2671 EXPORT_SYMBOL(ath9k_hw_htc_resetinit);
2672
2673 static struct {
2674 u32 version;
2675 const char * name;
2676 } ath_mac_bb_names[] = {
2677 /* Devices with external radios */
2678 { AR_SREV_VERSION_5416_PCI, "5416" },
2679 { AR_SREV_VERSION_5416_PCIE, "5418" },
2680 { AR_SREV_VERSION_9100, "9100" },
2681 { AR_SREV_VERSION_9160, "9160" },
2682 /* Single-chip solutions */
2683 { AR_SREV_VERSION_9280, "9280" },
2684 { AR_SREV_VERSION_9285, "9285" },
2685 { AR_SREV_VERSION_9287, "9287" },
2686 { AR_SREV_VERSION_9271, "9271" },
2687 };
2688
2689 /* For devices with external radios */
2690 static struct {
2691 u16 version;
2692 const char * name;
2693 } ath_rf_names[] = {
2694 { 0, "5133" },
2695 { AR_RAD5133_SREV_MAJOR, "5133" },
2696 { AR_RAD5122_SREV_MAJOR, "5122" },
2697 { AR_RAD2133_SREV_MAJOR, "2133" },
2698 { AR_RAD2122_SREV_MAJOR, "2122" }
2699 };
2700
2701 /*
2702 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2703 */
2704 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
2705 {
2706 int i;
2707
2708 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2709 if (ath_mac_bb_names[i].version == mac_bb_version) {
2710 return ath_mac_bb_names[i].name;
2711 }
2712 }
2713
2714 return "????";
2715 }
2716
2717 /*
2718 * Return the RF name. "????" is returned if the RF is unknown.
2719 * Used for devices with external radios.
2720 */
2721 static const char *ath9k_hw_rf_name(u16 rf_version)
2722 {
2723 int i;
2724
2725 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2726 if (ath_rf_names[i].version == rf_version) {
2727 return ath_rf_names[i].name;
2728 }
2729 }
2730
2731 return "????";
2732 }
2733
2734 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
2735 {
2736 int used;
2737
2738 /* chipsets >= AR9280 are single-chip */
2739 if (AR_SREV_9280_10_OR_LATER(ah)) {
2740 used = snprintf(hw_name, len,
2741 "Atheros AR%s Rev:%x",
2742 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2743 ah->hw_version.macRev);
2744 }
2745 else {
2746 used = snprintf(hw_name, len,
2747 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
2748 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2749 ah->hw_version.macRev,
2750 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
2751 AR_RADIO_SREV_MAJOR)),
2752 ah->hw_version.phyRev);
2753 }
2754
2755 hw_name[used] = '\0';
2756 }
2757 EXPORT_SYMBOL(ath9k_hw_name);
Linux kernel - Deliverables
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