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Merge tag 'pm+acpi-3.13-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael...
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / hw.c
1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/io.h>
18 #include <linux/slab.h>
19 #include <linux/module.h>
20 #include <asm/unaligned.h>
21
22 #include "hw.h"
23 #include "hw-ops.h"
24 #include "rc.h"
25 #include "ar9003_mac.h"
26 #include "ar9003_mci.h"
27 #include "ar9003_phy.h"
28 #include "debug.h"
29 #include "ath9k.h"
30
31 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
32
33 MODULE_AUTHOR("Atheros Communications");
34 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
35 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
36 MODULE_LICENSE("Dual BSD/GPL");
37
38 static int __init ath9k_init(void)
39 {
40 return 0;
41 }
42 module_init(ath9k_init);
43
44 static void __exit ath9k_exit(void)
45 {
46 return;
47 }
48 module_exit(ath9k_exit);
49
50 /* Private hardware callbacks */
51
52 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
53 {
54 ath9k_hw_private_ops(ah)->init_cal_settings(ah);
55 }
56
57 static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
58 struct ath9k_channel *chan)
59 {
60 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
61 }
62
63 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
64 {
65 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
66 return;
67
68 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
69 }
70
71 static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah)
72 {
73 /* You will not have this callback if using the old ANI */
74 if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs)
75 return;
76
77 ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah);
78 }
79
80 /********************/
81 /* Helper Functions */
82 /********************/
83
84 #ifdef CONFIG_ATH9K_DEBUGFS
85
86 void ath9k_debug_sync_cause(struct ath_common *common, u32 sync_cause)
87 {
88 struct ath_softc *sc = common->priv;
89 if (sync_cause)
90 sc->debug.stats.istats.sync_cause_all++;
91 if (sync_cause & AR_INTR_SYNC_RTC_IRQ)
92 sc->debug.stats.istats.sync_rtc_irq++;
93 if (sync_cause & AR_INTR_SYNC_MAC_IRQ)
94 sc->debug.stats.istats.sync_mac_irq++;
95 if (sync_cause & AR_INTR_SYNC_EEPROM_ILLEGAL_ACCESS)
96 sc->debug.stats.istats.eeprom_illegal_access++;
97 if (sync_cause & AR_INTR_SYNC_APB_TIMEOUT)
98 sc->debug.stats.istats.apb_timeout++;
99 if (sync_cause & AR_INTR_SYNC_PCI_MODE_CONFLICT)
100 sc->debug.stats.istats.pci_mode_conflict++;
101 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL)
102 sc->debug.stats.istats.host1_fatal++;
103 if (sync_cause & AR_INTR_SYNC_HOST1_PERR)
104 sc->debug.stats.istats.host1_perr++;
105 if (sync_cause & AR_INTR_SYNC_TRCV_FIFO_PERR)
106 sc->debug.stats.istats.trcv_fifo_perr++;
107 if (sync_cause & AR_INTR_SYNC_RADM_CPL_EP)
108 sc->debug.stats.istats.radm_cpl_ep++;
109 if (sync_cause & AR_INTR_SYNC_RADM_CPL_DLLP_ABORT)
110 sc->debug.stats.istats.radm_cpl_dllp_abort++;
111 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TLP_ABORT)
112 sc->debug.stats.istats.radm_cpl_tlp_abort++;
113 if (sync_cause & AR_INTR_SYNC_RADM_CPL_ECRC_ERR)
114 sc->debug.stats.istats.radm_cpl_ecrc_err++;
115 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT)
116 sc->debug.stats.istats.radm_cpl_timeout++;
117 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT)
118 sc->debug.stats.istats.local_timeout++;
119 if (sync_cause & AR_INTR_SYNC_PM_ACCESS)
120 sc->debug.stats.istats.pm_access++;
121 if (sync_cause & AR_INTR_SYNC_MAC_AWAKE)
122 sc->debug.stats.istats.mac_awake++;
123 if (sync_cause & AR_INTR_SYNC_MAC_ASLEEP)
124 sc->debug.stats.istats.mac_asleep++;
125 if (sync_cause & AR_INTR_SYNC_MAC_SLEEP_ACCESS)
126 sc->debug.stats.istats.mac_sleep_access++;
127 }
128 #endif
129
130
131 static void ath9k_hw_set_clockrate(struct ath_hw *ah)
132 {
133 struct ath_common *common = ath9k_hw_common(ah);
134 struct ath9k_channel *chan = ah->curchan;
135 unsigned int clockrate;
136
137 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */
138 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah))
139 clockrate = 117;
140 else if (!chan) /* should really check for CCK instead */
141 clockrate = ATH9K_CLOCK_RATE_CCK;
142 else if (IS_CHAN_2GHZ(chan))
143 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
144 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
145 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
146 else
147 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
148
149 if (IS_CHAN_HT40(chan))
150 clockrate *= 2;
151
152 if (ah->curchan) {
153 if (IS_CHAN_HALF_RATE(chan))
154 clockrate /= 2;
155 if (IS_CHAN_QUARTER_RATE(chan))
156 clockrate /= 4;
157 }
158
159 common->clockrate = clockrate;
160 }
161
162 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
163 {
164 struct ath_common *common = ath9k_hw_common(ah);
165
166 return usecs * common->clockrate;
167 }
168
169 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
170 {
171 int i;
172
173 BUG_ON(timeout < AH_TIME_QUANTUM);
174
175 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
176 if ((REG_READ(ah, reg) & mask) == val)
177 return true;
178
179 udelay(AH_TIME_QUANTUM);
180 }
181
182 ath_dbg(ath9k_hw_common(ah), ANY,
183 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
184 timeout, reg, REG_READ(ah, reg), mask, val);
185
186 return false;
187 }
188 EXPORT_SYMBOL(ath9k_hw_wait);
189
190 void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan,
191 int hw_delay)
192 {
193 hw_delay /= 10;
194
195 if (IS_CHAN_HALF_RATE(chan))
196 hw_delay *= 2;
197 else if (IS_CHAN_QUARTER_RATE(chan))
198 hw_delay *= 4;
199
200 udelay(hw_delay + BASE_ACTIVATE_DELAY);
201 }
202
203 void ath9k_hw_write_array(struct ath_hw *ah, const struct ar5416IniArray *array,
204 int column, unsigned int *writecnt)
205 {
206 int r;
207
208 ENABLE_REGWRITE_BUFFER(ah);
209 for (r = 0; r < array->ia_rows; r++) {
210 REG_WRITE(ah, INI_RA(array, r, 0),
211 INI_RA(array, r, column));
212 DO_DELAY(*writecnt);
213 }
214 REGWRITE_BUFFER_FLUSH(ah);
215 }
216
217 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
218 {
219 u32 retval;
220 int i;
221
222 for (i = 0, retval = 0; i < n; i++) {
223 retval = (retval << 1) | (val & 1);
224 val >>= 1;
225 }
226 return retval;
227 }
228
229 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
230 u8 phy, int kbps,
231 u32 frameLen, u16 rateix,
232 bool shortPreamble)
233 {
234 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
235
236 if (kbps == 0)
237 return 0;
238
239 switch (phy) {
240 case WLAN_RC_PHY_CCK:
241 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
242 if (shortPreamble)
243 phyTime >>= 1;
244 numBits = frameLen << 3;
245 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
246 break;
247 case WLAN_RC_PHY_OFDM:
248 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
249 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
250 numBits = OFDM_PLCP_BITS + (frameLen << 3);
251 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
252 txTime = OFDM_SIFS_TIME_QUARTER
253 + OFDM_PREAMBLE_TIME_QUARTER
254 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
255 } else if (ah->curchan &&
256 IS_CHAN_HALF_RATE(ah->curchan)) {
257 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
258 numBits = OFDM_PLCP_BITS + (frameLen << 3);
259 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
260 txTime = OFDM_SIFS_TIME_HALF +
261 OFDM_PREAMBLE_TIME_HALF
262 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
263 } else {
264 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
265 numBits = OFDM_PLCP_BITS + (frameLen << 3);
266 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
267 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
268 + (numSymbols * OFDM_SYMBOL_TIME);
269 }
270 break;
271 default:
272 ath_err(ath9k_hw_common(ah),
273 "Unknown phy %u (rate ix %u)\n", phy, rateix);
274 txTime = 0;
275 break;
276 }
277
278 return txTime;
279 }
280 EXPORT_SYMBOL(ath9k_hw_computetxtime);
281
282 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
283 struct ath9k_channel *chan,
284 struct chan_centers *centers)
285 {
286 int8_t extoff;
287
288 if (!IS_CHAN_HT40(chan)) {
289 centers->ctl_center = centers->ext_center =
290 centers->synth_center = chan->channel;
291 return;
292 }
293
294 if (IS_CHAN_HT40PLUS(chan)) {
295 centers->synth_center =
296 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
297 extoff = 1;
298 } else {
299 centers->synth_center =
300 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
301 extoff = -1;
302 }
303
304 centers->ctl_center =
305 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
306 /* 25 MHz spacing is supported by hw but not on upper layers */
307 centers->ext_center =
308 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
309 }
310
311 /******************/
312 /* Chip Revisions */
313 /******************/
314
315 static void ath9k_hw_read_revisions(struct ath_hw *ah)
316 {
317 u32 val;
318
319 switch (ah->hw_version.devid) {
320 case AR5416_AR9100_DEVID:
321 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
322 break;
323 case AR9300_DEVID_AR9330:
324 ah->hw_version.macVersion = AR_SREV_VERSION_9330;
325 if (ah->get_mac_revision) {
326 ah->hw_version.macRev = ah->get_mac_revision();
327 } else {
328 val = REG_READ(ah, AR_SREV);
329 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
330 }
331 return;
332 case AR9300_DEVID_AR9340:
333 ah->hw_version.macVersion = AR_SREV_VERSION_9340;
334 val = REG_READ(ah, AR_SREV);
335 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
336 return;
337 case AR9300_DEVID_QCA955X:
338 ah->hw_version.macVersion = AR_SREV_VERSION_9550;
339 return;
340 }
341
342 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
343
344 if (val == 0xFF) {
345 val = REG_READ(ah, AR_SREV);
346 ah->hw_version.macVersion =
347 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
348 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
349
350 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
351 ah->is_pciexpress = true;
352 else
353 ah->is_pciexpress = (val &
354 AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
355 } else {
356 if (!AR_SREV_9100(ah))
357 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
358
359 ah->hw_version.macRev = val & AR_SREV_REVISION;
360
361 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
362 ah->is_pciexpress = true;
363 }
364 }
365
366 /************************************/
367 /* HW Attach, Detach, Init Routines */
368 /************************************/
369
370 static void ath9k_hw_disablepcie(struct ath_hw *ah)
371 {
372 if (!AR_SREV_5416(ah))
373 return;
374
375 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
376 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
377 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
378 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
379 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
380 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
381 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
382 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
383 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
384
385 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
386 }
387
388 /* This should work for all families including legacy */
389 static bool ath9k_hw_chip_test(struct ath_hw *ah)
390 {
391 struct ath_common *common = ath9k_hw_common(ah);
392 u32 regAddr[2] = { AR_STA_ID0 };
393 u32 regHold[2];
394 static const u32 patternData[4] = {
395 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
396 };
397 int i, j, loop_max;
398
399 if (!AR_SREV_9300_20_OR_LATER(ah)) {
400 loop_max = 2;
401 regAddr[1] = AR_PHY_BASE + (8 << 2);
402 } else
403 loop_max = 1;
404
405 for (i = 0; i < loop_max; i++) {
406 u32 addr = regAddr[i];
407 u32 wrData, rdData;
408
409 regHold[i] = REG_READ(ah, addr);
410 for (j = 0; j < 0x100; j++) {
411 wrData = (j << 16) | j;
412 REG_WRITE(ah, addr, wrData);
413 rdData = REG_READ(ah, addr);
414 if (rdData != wrData) {
415 ath_err(common,
416 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
417 addr, wrData, rdData);
418 return false;
419 }
420 }
421 for (j = 0; j < 4; j++) {
422 wrData = patternData[j];
423 REG_WRITE(ah, addr, wrData);
424 rdData = REG_READ(ah, addr);
425 if (wrData != rdData) {
426 ath_err(common,
427 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
428 addr, wrData, rdData);
429 return false;
430 }
431 }
432 REG_WRITE(ah, regAddr[i], regHold[i]);
433 }
434 udelay(100);
435
436 return true;
437 }
438
439 static void ath9k_hw_init_config(struct ath_hw *ah)
440 {
441 int i;
442
443 ah->config.dma_beacon_response_time = 1;
444 ah->config.sw_beacon_response_time = 6;
445 ah->config.additional_swba_backoff = 0;
446 ah->config.ack_6mb = 0x0;
447 ah->config.cwm_ignore_extcca = 0;
448 ah->config.pcie_clock_req = 0;
449 ah->config.analog_shiftreg = 1;
450
451 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
452 ah->config.spurchans[i][0] = AR_NO_SPUR;
453 ah->config.spurchans[i][1] = AR_NO_SPUR;
454 }
455
456 ah->config.rx_intr_mitigation = true;
457 ah->config.pcieSerDesWrite = true;
458
459 /*
460 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
461 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
462 * This means we use it for all AR5416 devices, and the few
463 * minor PCI AR9280 devices out there.
464 *
465 * Serialization is required because these devices do not handle
466 * well the case of two concurrent reads/writes due to the latency
467 * involved. During one read/write another read/write can be issued
468 * on another CPU while the previous read/write may still be working
469 * on our hardware, if we hit this case the hardware poops in a loop.
470 * We prevent this by serializing reads and writes.
471 *
472 * This issue is not present on PCI-Express devices or pre-AR5416
473 * devices (legacy, 802.11abg).
474 */
475 if (num_possible_cpus() > 1)
476 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
477 }
478
479 static void ath9k_hw_init_defaults(struct ath_hw *ah)
480 {
481 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
482
483 regulatory->country_code = CTRY_DEFAULT;
484 regulatory->power_limit = MAX_RATE_POWER;
485
486 ah->hw_version.magic = AR5416_MAGIC;
487 ah->hw_version.subvendorid = 0;
488
489 ah->atim_window = 0;
490 ah->sta_id1_defaults =
491 AR_STA_ID1_CRPT_MIC_ENABLE |
492 AR_STA_ID1_MCAST_KSRCH;
493 if (AR_SREV_9100(ah))
494 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX;
495 ah->slottime = ATH9K_SLOT_TIME_9;
496 ah->globaltxtimeout = (u32) -1;
497 ah->power_mode = ATH9K_PM_UNDEFINED;
498 ah->htc_reset_init = true;
499 }
500
501 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
502 {
503 struct ath_common *common = ath9k_hw_common(ah);
504 u32 sum;
505 int i;
506 u16 eeval;
507 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
508
509 sum = 0;
510 for (i = 0; i < 3; i++) {
511 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
512 sum += eeval;
513 common->macaddr[2 * i] = eeval >> 8;
514 common->macaddr[2 * i + 1] = eeval & 0xff;
515 }
516 if (sum == 0 || sum == 0xffff * 3)
517 return -EADDRNOTAVAIL;
518
519 return 0;
520 }
521
522 static int ath9k_hw_post_init(struct ath_hw *ah)
523 {
524 struct ath_common *common = ath9k_hw_common(ah);
525 int ecode;
526
527 if (common->bus_ops->ath_bus_type != ATH_USB) {
528 if (!ath9k_hw_chip_test(ah))
529 return -ENODEV;
530 }
531
532 if (!AR_SREV_9300_20_OR_LATER(ah)) {
533 ecode = ar9002_hw_rf_claim(ah);
534 if (ecode != 0)
535 return ecode;
536 }
537
538 ecode = ath9k_hw_eeprom_init(ah);
539 if (ecode != 0)
540 return ecode;
541
542 ath_dbg(ath9k_hw_common(ah), CONFIG, "Eeprom VER: %d, REV: %d\n",
543 ah->eep_ops->get_eeprom_ver(ah),
544 ah->eep_ops->get_eeprom_rev(ah));
545
546 ath9k_hw_ani_init(ah);
547
548 /*
549 * EEPROM needs to be initialized before we do this.
550 * This is required for regulatory compliance.
551 */
552 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
553 u16 regdmn = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
554 if ((regdmn & 0xF0) == CTL_FCC) {
555 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9462_FCC_2GHZ;
556 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9462_FCC_5GHZ;
557 }
558 }
559
560 return 0;
561 }
562
563 static int ath9k_hw_attach_ops(struct ath_hw *ah)
564 {
565 if (!AR_SREV_9300_20_OR_LATER(ah))
566 return ar9002_hw_attach_ops(ah);
567
568 ar9003_hw_attach_ops(ah);
569 return 0;
570 }
571
572 /* Called for all hardware families */
573 static int __ath9k_hw_init(struct ath_hw *ah)
574 {
575 struct ath_common *common = ath9k_hw_common(ah);
576 int r = 0;
577
578 ath9k_hw_read_revisions(ah);
579
580 /*
581 * Read back AR_WA into a permanent copy and set bits 14 and 17.
582 * We need to do this to avoid RMW of this register. We cannot
583 * read the reg when chip is asleep.
584 */
585 if (AR_SREV_9300_20_OR_LATER(ah)) {
586 ah->WARegVal = REG_READ(ah, AR_WA);
587 ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
588 AR_WA_ASPM_TIMER_BASED_DISABLE);
589 }
590
591 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
592 ath_err(common, "Couldn't reset chip\n");
593 return -EIO;
594 }
595
596 if (AR_SREV_9565(ah)) {
597 ah->WARegVal |= AR_WA_BIT22;
598 REG_WRITE(ah, AR_WA, ah->WARegVal);
599 }
600
601 ath9k_hw_init_defaults(ah);
602 ath9k_hw_init_config(ah);
603
604 r = ath9k_hw_attach_ops(ah);
605 if (r)
606 return r;
607
608 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
609 ath_err(common, "Couldn't wakeup chip\n");
610 return -EIO;
611 }
612
613 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
614 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
615 ((AR_SREV_9160(ah) || AR_SREV_9280(ah) || AR_SREV_9287(ah)) &&
616 !ah->is_pciexpress)) {
617 ah->config.serialize_regmode =
618 SER_REG_MODE_ON;
619 } else {
620 ah->config.serialize_regmode =
621 SER_REG_MODE_OFF;
622 }
623 }
624
625 ath_dbg(common, RESET, "serialize_regmode is %d\n",
626 ah->config.serialize_regmode);
627
628 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
629 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
630 else
631 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
632
633 switch (ah->hw_version.macVersion) {
634 case AR_SREV_VERSION_5416_PCI:
635 case AR_SREV_VERSION_5416_PCIE:
636 case AR_SREV_VERSION_9160:
637 case AR_SREV_VERSION_9100:
638 case AR_SREV_VERSION_9280:
639 case AR_SREV_VERSION_9285:
640 case AR_SREV_VERSION_9287:
641 case AR_SREV_VERSION_9271:
642 case AR_SREV_VERSION_9300:
643 case AR_SREV_VERSION_9330:
644 case AR_SREV_VERSION_9485:
645 case AR_SREV_VERSION_9340:
646 case AR_SREV_VERSION_9462:
647 case AR_SREV_VERSION_9550:
648 case AR_SREV_VERSION_9565:
649 break;
650 default:
651 ath_err(common,
652 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
653 ah->hw_version.macVersion, ah->hw_version.macRev);
654 return -EOPNOTSUPP;
655 }
656
657 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) ||
658 AR_SREV_9330(ah) || AR_SREV_9550(ah))
659 ah->is_pciexpress = false;
660
661 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
662 ath9k_hw_init_cal_settings(ah);
663
664 ah->ani_function = ATH9K_ANI_ALL;
665 if (!AR_SREV_9300_20_OR_LATER(ah))
666 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
667
668 if (!ah->is_pciexpress)
669 ath9k_hw_disablepcie(ah);
670
671 r = ath9k_hw_post_init(ah);
672 if (r)
673 return r;
674
675 ath9k_hw_init_mode_gain_regs(ah);
676 r = ath9k_hw_fill_cap_info(ah);
677 if (r)
678 return r;
679
680 r = ath9k_hw_init_macaddr(ah);
681 if (r) {
682 ath_err(common, "Failed to initialize MAC address\n");
683 return r;
684 }
685
686 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
687 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
688 else
689 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
690
691 if (AR_SREV_9330(ah))
692 ah->bb_watchdog_timeout_ms = 85;
693 else
694 ah->bb_watchdog_timeout_ms = 25;
695
696 common->state = ATH_HW_INITIALIZED;
697
698 return 0;
699 }
700
701 int ath9k_hw_init(struct ath_hw *ah)
702 {
703 int ret;
704 struct ath_common *common = ath9k_hw_common(ah);
705
706 /* These are all the AR5008/AR9001/AR9002/AR9003 hardware family of chipsets */
707 switch (ah->hw_version.devid) {
708 case AR5416_DEVID_PCI:
709 case AR5416_DEVID_PCIE:
710 case AR5416_AR9100_DEVID:
711 case AR9160_DEVID_PCI:
712 case AR9280_DEVID_PCI:
713 case AR9280_DEVID_PCIE:
714 case AR9285_DEVID_PCIE:
715 case AR9287_DEVID_PCI:
716 case AR9287_DEVID_PCIE:
717 case AR2427_DEVID_PCIE:
718 case AR9300_DEVID_PCIE:
719 case AR9300_DEVID_AR9485_PCIE:
720 case AR9300_DEVID_AR9330:
721 case AR9300_DEVID_AR9340:
722 case AR9300_DEVID_QCA955X:
723 case AR9300_DEVID_AR9580:
724 case AR9300_DEVID_AR9462:
725 case AR9485_DEVID_AR1111:
726 case AR9300_DEVID_AR9565:
727 break;
728 default:
729 if (common->bus_ops->ath_bus_type == ATH_USB)
730 break;
731 ath_err(common, "Hardware device ID 0x%04x not supported\n",
732 ah->hw_version.devid);
733 return -EOPNOTSUPP;
734 }
735
736 ret = __ath9k_hw_init(ah);
737 if (ret) {
738 ath_err(common,
739 "Unable to initialize hardware; initialization status: %d\n",
740 ret);
741 return ret;
742 }
743
744 return 0;
745 }
746 EXPORT_SYMBOL(ath9k_hw_init);
747
748 static void ath9k_hw_init_qos(struct ath_hw *ah)
749 {
750 ENABLE_REGWRITE_BUFFER(ah);
751
752 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
753 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
754
755 REG_WRITE(ah, AR_QOS_NO_ACK,
756 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
757 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
758 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
759
760 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
761 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
762 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
763 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
764 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
765
766 REGWRITE_BUFFER_FLUSH(ah);
767 }
768
769 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
770 {
771 struct ath_common *common = ath9k_hw_common(ah);
772 int i = 0;
773
774 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
775 udelay(100);
776 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
777
778 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) {
779
780 udelay(100);
781
782 if (WARN_ON_ONCE(i >= 100)) {
783 ath_err(common, "PLL4 meaurement not done\n");
784 break;
785 }
786
787 i++;
788 }
789
790 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
791 }
792 EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc);
793
794 static void ath9k_hw_init_pll(struct ath_hw *ah,
795 struct ath9k_channel *chan)
796 {
797 u32 pll;
798
799 if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
800 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */
801 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
802 AR_CH0_BB_DPLL2_PLL_PWD, 0x1);
803 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
804 AR_CH0_DPLL2_KD, 0x40);
805 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
806 AR_CH0_DPLL2_KI, 0x4);
807
808 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
809 AR_CH0_BB_DPLL1_REFDIV, 0x5);
810 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
811 AR_CH0_BB_DPLL1_NINI, 0x58);
812 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
813 AR_CH0_BB_DPLL1_NFRAC, 0x0);
814
815 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
816 AR_CH0_BB_DPLL2_OUTDIV, 0x1);
817 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
818 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1);
819 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
820 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1);
821
822 /* program BB PLL phase_shift to 0x6 */
823 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
824 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6);
825
826 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
827 AR_CH0_BB_DPLL2_PLL_PWD, 0x0);
828 udelay(1000);
829 } else if (AR_SREV_9330(ah)) {
830 u32 ddr_dpll2, pll_control2, kd;
831
832 if (ah->is_clk_25mhz) {
833 ddr_dpll2 = 0x18e82f01;
834 pll_control2 = 0xe04a3d;
835 kd = 0x1d;
836 } else {
837 ddr_dpll2 = 0x19e82f01;
838 pll_control2 = 0x886666;
839 kd = 0x3d;
840 }
841
842 /* program DDR PLL ki and kd value */
843 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2);
844
845 /* program DDR PLL phase_shift */
846 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3,
847 AR_CH0_DPLL3_PHASE_SHIFT, 0x1);
848
849 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
850 udelay(1000);
851
852 /* program refdiv, nint, frac to RTC register */
853 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2);
854
855 /* program BB PLL kd and ki value */
856 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd);
857 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06);
858
859 /* program BB PLL phase_shift */
860 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
861 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1);
862 } else if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) {
863 u32 regval, pll2_divint, pll2_divfrac, refdiv;
864
865 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
866 udelay(1000);
867
868 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16);
869 udelay(100);
870
871 if (ah->is_clk_25mhz) {
872 pll2_divint = 0x54;
873 pll2_divfrac = 0x1eb85;
874 refdiv = 3;
875 } else {
876 if (AR_SREV_9340(ah)) {
877 pll2_divint = 88;
878 pll2_divfrac = 0;
879 refdiv = 5;
880 } else {
881 pll2_divint = 0x11;
882 pll2_divfrac = 0x26666;
883 refdiv = 1;
884 }
885 }
886
887 regval = REG_READ(ah, AR_PHY_PLL_MODE);
888 regval |= (0x1 << 16);
889 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
890 udelay(100);
891
892 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) |
893 (pll2_divint << 18) | pll2_divfrac);
894 udelay(100);
895
896 regval = REG_READ(ah, AR_PHY_PLL_MODE);
897 if (AR_SREV_9340(ah))
898 regval = (regval & 0x80071fff) | (0x1 << 30) |
899 (0x1 << 13) | (0x4 << 26) | (0x18 << 19);
900 else
901 regval = (regval & 0x80071fff) | (0x3 << 30) |
902 (0x1 << 13) | (0x4 << 26) | (0x60 << 19);
903 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
904 REG_WRITE(ah, AR_PHY_PLL_MODE,
905 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff);
906 udelay(1000);
907 }
908
909 pll = ath9k_hw_compute_pll_control(ah, chan);
910 if (AR_SREV_9565(ah))
911 pll |= 0x40000;
912 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
913
914 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
915 AR_SREV_9550(ah))
916 udelay(1000);
917
918 /* Switch the core clock for ar9271 to 117Mhz */
919 if (AR_SREV_9271(ah)) {
920 udelay(500);
921 REG_WRITE(ah, 0x50040, 0x304);
922 }
923
924 udelay(RTC_PLL_SETTLE_DELAY);
925
926 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
927
928 if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) {
929 if (ah->is_clk_25mhz) {
930 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1);
931 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);
932 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae);
933 } else {
934 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1);
935 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400);
936 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800);
937 }
938 udelay(100);
939 }
940 }
941
942 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
943 enum nl80211_iftype opmode)
944 {
945 u32 sync_default = AR_INTR_SYNC_DEFAULT;
946 u32 imr_reg = AR_IMR_TXERR |
947 AR_IMR_TXURN |
948 AR_IMR_RXERR |
949 AR_IMR_RXORN |
950 AR_IMR_BCNMISC;
951
952 if (AR_SREV_9340(ah) || AR_SREV_9550(ah))
953 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
954
955 if (AR_SREV_9300_20_OR_LATER(ah)) {
956 imr_reg |= AR_IMR_RXOK_HP;
957 if (ah->config.rx_intr_mitigation)
958 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
959 else
960 imr_reg |= AR_IMR_RXOK_LP;
961
962 } else {
963 if (ah->config.rx_intr_mitigation)
964 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
965 else
966 imr_reg |= AR_IMR_RXOK;
967 }
968
969 if (ah->config.tx_intr_mitigation)
970 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
971 else
972 imr_reg |= AR_IMR_TXOK;
973
974 ENABLE_REGWRITE_BUFFER(ah);
975
976 REG_WRITE(ah, AR_IMR, imr_reg);
977 ah->imrs2_reg |= AR_IMR_S2_GTT;
978 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
979
980 if (!AR_SREV_9100(ah)) {
981 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
982 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
983 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
984 }
985
986 REGWRITE_BUFFER_FLUSH(ah);
987
988 if (AR_SREV_9300_20_OR_LATER(ah)) {
989 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
990 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
991 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
992 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
993 }
994 }
995
996 static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us)
997 {
998 u32 val = ath9k_hw_mac_to_clks(ah, us - 2);
999 val = min(val, (u32) 0xFFFF);
1000 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val);
1001 }
1002
1003 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
1004 {
1005 u32 val = ath9k_hw_mac_to_clks(ah, us);
1006 val = min(val, (u32) 0xFFFF);
1007 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
1008 }
1009
1010 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1011 {
1012 u32 val = ath9k_hw_mac_to_clks(ah, us);
1013 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
1014 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
1015 }
1016
1017 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1018 {
1019 u32 val = ath9k_hw_mac_to_clks(ah, us);
1020 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
1021 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
1022 }
1023
1024 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1025 {
1026 if (tu > 0xFFFF) {
1027 ath_dbg(ath9k_hw_common(ah), XMIT, "bad global tx timeout %u\n",
1028 tu);
1029 ah->globaltxtimeout = (u32) -1;
1030 return false;
1031 } else {
1032 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1033 ah->globaltxtimeout = tu;
1034 return true;
1035 }
1036 }
1037
1038 void ath9k_hw_init_global_settings(struct ath_hw *ah)
1039 {
1040 struct ath_common *common = ath9k_hw_common(ah);
1041 const struct ath9k_channel *chan = ah->curchan;
1042 int acktimeout, ctstimeout, ack_offset = 0;
1043 int slottime;
1044 int sifstime;
1045 int rx_lat = 0, tx_lat = 0, eifs = 0;
1046 u32 reg;
1047
1048 ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n",
1049 ah->misc_mode);
1050
1051 if (!chan)
1052 return;
1053
1054 if (ah->misc_mode != 0)
1055 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode);
1056
1057 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1058 rx_lat = 41;
1059 else
1060 rx_lat = 37;
1061 tx_lat = 54;
1062
1063 if (IS_CHAN_5GHZ(chan))
1064 sifstime = 16;
1065 else
1066 sifstime = 10;
1067
1068 if (IS_CHAN_HALF_RATE(chan)) {
1069 eifs = 175;
1070 rx_lat *= 2;
1071 tx_lat *= 2;
1072 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1073 tx_lat += 11;
1074
1075 sifstime = 32;
1076 ack_offset = 16;
1077 slottime = 13;
1078 } else if (IS_CHAN_QUARTER_RATE(chan)) {
1079 eifs = 340;
1080 rx_lat = (rx_lat * 4) - 1;
1081 tx_lat *= 4;
1082 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1083 tx_lat += 22;
1084
1085 sifstime = 64;
1086 ack_offset = 32;
1087 slottime = 21;
1088 } else {
1089 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1090 eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO;
1091 reg = AR_USEC_ASYNC_FIFO;
1092 } else {
1093 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/
1094 common->clockrate;
1095 reg = REG_READ(ah, AR_USEC);
1096 }
1097 rx_lat = MS(reg, AR_USEC_RX_LAT);
1098 tx_lat = MS(reg, AR_USEC_TX_LAT);
1099
1100 slottime = ah->slottime;
1101 }
1102
1103 /* As defined by IEEE 802.11-2007 17.3.8.6 */
1104 slottime += 3 * ah->coverage_class;
1105 acktimeout = slottime + sifstime + ack_offset;
1106 ctstimeout = acktimeout;
1107
1108 /*
1109 * Workaround for early ACK timeouts, add an offset to match the
1110 * initval's 64us ack timeout value. Use 48us for the CTS timeout.
1111 * This was initially only meant to work around an issue with delayed
1112 * BA frames in some implementations, but it has been found to fix ACK
1113 * timeout issues in other cases as well.
1114 */
1115 if (IS_CHAN_2GHZ(chan) &&
1116 !IS_CHAN_HALF_RATE(chan) && !IS_CHAN_QUARTER_RATE(chan)) {
1117 acktimeout += 64 - sifstime - ah->slottime;
1118 ctstimeout += 48 - sifstime - ah->slottime;
1119 }
1120
1121 ath9k_hw_set_sifs_time(ah, sifstime);
1122 ath9k_hw_setslottime(ah, slottime);
1123 ath9k_hw_set_ack_timeout(ah, acktimeout);
1124 ath9k_hw_set_cts_timeout(ah, ctstimeout);
1125 if (ah->globaltxtimeout != (u32) -1)
1126 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1127
1128 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs));
1129 REG_RMW(ah, AR_USEC,
1130 (common->clockrate - 1) |
1131 SM(rx_lat, AR_USEC_RX_LAT) |
1132 SM(tx_lat, AR_USEC_TX_LAT),
1133 AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC);
1134
1135 }
1136 EXPORT_SYMBOL(ath9k_hw_init_global_settings);
1137
1138 void ath9k_hw_deinit(struct ath_hw *ah)
1139 {
1140 struct ath_common *common = ath9k_hw_common(ah);
1141
1142 if (common->state < ATH_HW_INITIALIZED)
1143 return;
1144
1145 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1146 }
1147 EXPORT_SYMBOL(ath9k_hw_deinit);
1148
1149 /*******/
1150 /* INI */
1151 /*******/
1152
1153 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
1154 {
1155 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1156
1157 if (IS_CHAN_2GHZ(chan))
1158 ctl |= CTL_11G;
1159 else
1160 ctl |= CTL_11A;
1161
1162 return ctl;
1163 }
1164
1165 /****************************************/
1166 /* Reset and Channel Switching Routines */
1167 /****************************************/
1168
1169 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1170 {
1171 struct ath_common *common = ath9k_hw_common(ah);
1172 int txbuf_size;
1173
1174 ENABLE_REGWRITE_BUFFER(ah);
1175
1176 /*
1177 * set AHB_MODE not to do cacheline prefetches
1178 */
1179 if (!AR_SREV_9300_20_OR_LATER(ah))
1180 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
1181
1182 /*
1183 * let mac dma reads be in 128 byte chunks
1184 */
1185 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK);
1186
1187 REGWRITE_BUFFER_FLUSH(ah);
1188
1189 /*
1190 * Restore TX Trigger Level to its pre-reset value.
1191 * The initial value depends on whether aggregation is enabled, and is
1192 * adjusted whenever underruns are detected.
1193 */
1194 if (!AR_SREV_9300_20_OR_LATER(ah))
1195 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1196
1197 ENABLE_REGWRITE_BUFFER(ah);
1198
1199 /*
1200 * let mac dma writes be in 128 byte chunks
1201 */
1202 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK);
1203
1204 /*
1205 * Setup receive FIFO threshold to hold off TX activities
1206 */
1207 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1208
1209 if (AR_SREV_9300_20_OR_LATER(ah)) {
1210 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
1211 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
1212
1213 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
1214 ah->caps.rx_status_len);
1215 }
1216
1217 /*
1218 * reduce the number of usable entries in PCU TXBUF to avoid
1219 * wrap around issues.
1220 */
1221 if (AR_SREV_9285(ah)) {
1222 /* For AR9285 the number of Fifos are reduced to half.
1223 * So set the usable tx buf size also to half to
1224 * avoid data/delimiter underruns
1225 */
1226 txbuf_size = AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE;
1227 } else if (AR_SREV_9340_13_OR_LATER(ah)) {
1228 /* Uses fewer entries for AR934x v1.3+ to prevent rx overruns */
1229 txbuf_size = AR_9340_PCU_TXBUF_CTRL_USABLE_SIZE;
1230 } else {
1231 txbuf_size = AR_PCU_TXBUF_CTRL_USABLE_SIZE;
1232 }
1233
1234 if (!AR_SREV_9271(ah))
1235 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, txbuf_size);
1236
1237 REGWRITE_BUFFER_FLUSH(ah);
1238
1239 if (AR_SREV_9300_20_OR_LATER(ah))
1240 ath9k_hw_reset_txstatus_ring(ah);
1241 }
1242
1243 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1244 {
1245 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC;
1246 u32 set = AR_STA_ID1_KSRCH_MODE;
1247
1248 switch (opmode) {
1249 case NL80211_IFTYPE_ADHOC:
1250 set |= AR_STA_ID1_ADHOC;
1251 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1252 break;
1253 case NL80211_IFTYPE_MESH_POINT:
1254 case NL80211_IFTYPE_AP:
1255 set |= AR_STA_ID1_STA_AP;
1256 /* fall through */
1257 case NL80211_IFTYPE_STATION:
1258 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1259 break;
1260 default:
1261 if (!ah->is_monitoring)
1262 set = 0;
1263 break;
1264 }
1265 REG_RMW(ah, AR_STA_ID1, set, mask);
1266 }
1267
1268 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1269 u32 *coef_mantissa, u32 *coef_exponent)
1270 {
1271 u32 coef_exp, coef_man;
1272
1273 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1274 if ((coef_scaled >> coef_exp) & 0x1)
1275 break;
1276
1277 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1278
1279 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1280
1281 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1282 *coef_exponent = coef_exp - 16;
1283 }
1284
1285 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1286 {
1287 u32 rst_flags;
1288 u32 tmpReg;
1289
1290 if (AR_SREV_9100(ah)) {
1291 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK,
1292 AR_RTC_DERIVED_CLK_PERIOD, 1);
1293 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1294 }
1295
1296 ENABLE_REGWRITE_BUFFER(ah);
1297
1298 if (AR_SREV_9300_20_OR_LATER(ah)) {
1299 REG_WRITE(ah, AR_WA, ah->WARegVal);
1300 udelay(10);
1301 }
1302
1303 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1304 AR_RTC_FORCE_WAKE_ON_INT);
1305
1306 if (AR_SREV_9100(ah)) {
1307 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1308 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1309 } else {
1310 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1311 if (AR_SREV_9340(ah))
1312 tmpReg &= AR9340_INTR_SYNC_LOCAL_TIMEOUT;
1313 else
1314 tmpReg &= AR_INTR_SYNC_LOCAL_TIMEOUT |
1315 AR_INTR_SYNC_RADM_CPL_TIMEOUT;
1316
1317 if (tmpReg) {
1318 u32 val;
1319 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1320
1321 val = AR_RC_HOSTIF;
1322 if (!AR_SREV_9300_20_OR_LATER(ah))
1323 val |= AR_RC_AHB;
1324 REG_WRITE(ah, AR_RC, val);
1325
1326 } else if (!AR_SREV_9300_20_OR_LATER(ah))
1327 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1328
1329 rst_flags = AR_RTC_RC_MAC_WARM;
1330 if (type == ATH9K_RESET_COLD)
1331 rst_flags |= AR_RTC_RC_MAC_COLD;
1332 }
1333
1334 if (AR_SREV_9330(ah)) {
1335 int npend = 0;
1336 int i;
1337
1338 /* AR9330 WAR:
1339 * call external reset function to reset WMAC if:
1340 * - doing a cold reset
1341 * - we have pending frames in the TX queues
1342 */
1343
1344 for (i = 0; i < AR_NUM_QCU; i++) {
1345 npend = ath9k_hw_numtxpending(ah, i);
1346 if (npend)
1347 break;
1348 }
1349
1350 if (ah->external_reset &&
1351 (npend || type == ATH9K_RESET_COLD)) {
1352 int reset_err = 0;
1353
1354 ath_dbg(ath9k_hw_common(ah), RESET,
1355 "reset MAC via external reset\n");
1356
1357 reset_err = ah->external_reset();
1358 if (reset_err) {
1359 ath_err(ath9k_hw_common(ah),
1360 "External reset failed, err=%d\n",
1361 reset_err);
1362 return false;
1363 }
1364
1365 REG_WRITE(ah, AR_RTC_RESET, 1);
1366 }
1367 }
1368
1369 if (ath9k_hw_mci_is_enabled(ah))
1370 ar9003_mci_check_gpm_offset(ah);
1371
1372 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1373
1374 REGWRITE_BUFFER_FLUSH(ah);
1375
1376 udelay(50);
1377
1378 REG_WRITE(ah, AR_RTC_RC, 0);
1379 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1380 ath_dbg(ath9k_hw_common(ah), RESET, "RTC stuck in MAC reset\n");
1381 return false;
1382 }
1383
1384 if (!AR_SREV_9100(ah))
1385 REG_WRITE(ah, AR_RC, 0);
1386
1387 if (AR_SREV_9100(ah))
1388 udelay(50);
1389
1390 return true;
1391 }
1392
1393 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1394 {
1395 ENABLE_REGWRITE_BUFFER(ah);
1396
1397 if (AR_SREV_9300_20_OR_LATER(ah)) {
1398 REG_WRITE(ah, AR_WA, ah->WARegVal);
1399 udelay(10);
1400 }
1401
1402 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1403 AR_RTC_FORCE_WAKE_ON_INT);
1404
1405 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1406 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1407
1408 REG_WRITE(ah, AR_RTC_RESET, 0);
1409
1410 REGWRITE_BUFFER_FLUSH(ah);
1411
1412 if (!AR_SREV_9300_20_OR_LATER(ah))
1413 udelay(2);
1414
1415 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1416 REG_WRITE(ah, AR_RC, 0);
1417
1418 REG_WRITE(ah, AR_RTC_RESET, 1);
1419
1420 if (!ath9k_hw_wait(ah,
1421 AR_RTC_STATUS,
1422 AR_RTC_STATUS_M,
1423 AR_RTC_STATUS_ON,
1424 AH_WAIT_TIMEOUT)) {
1425 ath_dbg(ath9k_hw_common(ah), RESET, "RTC not waking up\n");
1426 return false;
1427 }
1428
1429 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1430 }
1431
1432 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1433 {
1434 bool ret = false;
1435
1436 if (AR_SREV_9300_20_OR_LATER(ah)) {
1437 REG_WRITE(ah, AR_WA, ah->WARegVal);
1438 udelay(10);
1439 }
1440
1441 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1442 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1443
1444 if (!ah->reset_power_on)
1445 type = ATH9K_RESET_POWER_ON;
1446
1447 switch (type) {
1448 case ATH9K_RESET_POWER_ON:
1449 ret = ath9k_hw_set_reset_power_on(ah);
1450 if (ret)
1451 ah->reset_power_on = true;
1452 break;
1453 case ATH9K_RESET_WARM:
1454 case ATH9K_RESET_COLD:
1455 ret = ath9k_hw_set_reset(ah, type);
1456 break;
1457 default:
1458 break;
1459 }
1460
1461 return ret;
1462 }
1463
1464 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1465 struct ath9k_channel *chan)
1466 {
1467 int reset_type = ATH9K_RESET_WARM;
1468
1469 if (AR_SREV_9280(ah)) {
1470 if (ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1471 reset_type = ATH9K_RESET_POWER_ON;
1472 else
1473 reset_type = ATH9K_RESET_COLD;
1474 } else if (ah->chip_fullsleep || REG_READ(ah, AR_Q_TXE) ||
1475 (REG_READ(ah, AR_CR) & AR_CR_RXE))
1476 reset_type = ATH9K_RESET_COLD;
1477
1478 if (!ath9k_hw_set_reset_reg(ah, reset_type))
1479 return false;
1480
1481 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1482 return false;
1483
1484 ah->chip_fullsleep = false;
1485
1486 if (AR_SREV_9330(ah))
1487 ar9003_hw_internal_regulator_apply(ah);
1488 ath9k_hw_init_pll(ah, chan);
1489 ath9k_hw_set_rfmode(ah, chan);
1490
1491 return true;
1492 }
1493
1494 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1495 struct ath9k_channel *chan)
1496 {
1497 struct ath_common *common = ath9k_hw_common(ah);
1498 struct ath9k_hw_capabilities *pCap = &ah->caps;
1499 bool band_switch = false, mode_diff = false;
1500 u8 ini_reloaded = 0;
1501 u32 qnum;
1502 int r;
1503
1504 if (pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) {
1505 band_switch = IS_CHAN_5GHZ(ah->curchan) != IS_CHAN_5GHZ(chan);
1506 mode_diff = (chan->channelFlags != ah->curchan->channelFlags);
1507 }
1508
1509 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1510 if (ath9k_hw_numtxpending(ah, qnum)) {
1511 ath_dbg(common, QUEUE,
1512 "Transmit frames pending on queue %d\n", qnum);
1513 return false;
1514 }
1515 }
1516
1517 if (!ath9k_hw_rfbus_req(ah)) {
1518 ath_err(common, "Could not kill baseband RX\n");
1519 return false;
1520 }
1521
1522 if (band_switch || mode_diff) {
1523 ath9k_hw_mark_phy_inactive(ah);
1524 udelay(5);
1525
1526 if (band_switch)
1527 ath9k_hw_init_pll(ah, chan);
1528
1529 if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) {
1530 ath_err(common, "Failed to do fast channel change\n");
1531 return false;
1532 }
1533 }
1534
1535 ath9k_hw_set_channel_regs(ah, chan);
1536
1537 r = ath9k_hw_rf_set_freq(ah, chan);
1538 if (r) {
1539 ath_err(common, "Failed to set channel\n");
1540 return false;
1541 }
1542 ath9k_hw_set_clockrate(ah);
1543 ath9k_hw_apply_txpower(ah, chan, false);
1544
1545 ath9k_hw_set_delta_slope(ah, chan);
1546 ath9k_hw_spur_mitigate_freq(ah, chan);
1547
1548 if (band_switch || ini_reloaded)
1549 ah->eep_ops->set_board_values(ah, chan);
1550
1551 ath9k_hw_init_bb(ah, chan);
1552 ath9k_hw_rfbus_done(ah);
1553
1554 if (band_switch || ini_reloaded) {
1555 ah->ah_flags |= AH_FASTCC;
1556 ath9k_hw_init_cal(ah, chan);
1557 ah->ah_flags &= ~AH_FASTCC;
1558 }
1559
1560 return true;
1561 }
1562
1563 static void ath9k_hw_apply_gpio_override(struct ath_hw *ah)
1564 {
1565 u32 gpio_mask = ah->gpio_mask;
1566 int i;
1567
1568 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) {
1569 if (!(gpio_mask & 1))
1570 continue;
1571
1572 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1573 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i)));
1574 }
1575 }
1576
1577 static bool ath9k_hw_check_dcs(u32 dma_dbg, u32 num_dcu_states,
1578 int *hang_state, int *hang_pos)
1579 {
1580 static u32 dcu_chain_state[] = {5, 6, 9}; /* DCU chain stuck states */
1581 u32 chain_state, dcs_pos, i;
1582
1583 for (dcs_pos = 0; dcs_pos < num_dcu_states; dcs_pos++) {
1584 chain_state = (dma_dbg >> (5 * dcs_pos)) & 0x1f;
1585 for (i = 0; i < 3; i++) {
1586 if (chain_state == dcu_chain_state[i]) {
1587 *hang_state = chain_state;
1588 *hang_pos = dcs_pos;
1589 return true;
1590 }
1591 }
1592 }
1593 return false;
1594 }
1595
1596 #define DCU_COMPLETE_STATE 1
1597 #define DCU_COMPLETE_STATE_MASK 0x3
1598 #define NUM_STATUS_READS 50
1599 static bool ath9k_hw_detect_mac_hang(struct ath_hw *ah)
1600 {
1601 u32 chain_state, comp_state, dcs_reg = AR_DMADBG_4;
1602 u32 i, hang_pos, hang_state, num_state = 6;
1603
1604 comp_state = REG_READ(ah, AR_DMADBG_6);
1605
1606 if ((comp_state & DCU_COMPLETE_STATE_MASK) != DCU_COMPLETE_STATE) {
1607 ath_dbg(ath9k_hw_common(ah), RESET,
1608 "MAC Hang signature not found at DCU complete\n");
1609 return false;
1610 }
1611
1612 chain_state = REG_READ(ah, dcs_reg);
1613 if (ath9k_hw_check_dcs(chain_state, num_state, &hang_state, &hang_pos))
1614 goto hang_check_iter;
1615
1616 dcs_reg = AR_DMADBG_5;
1617 num_state = 4;
1618 chain_state = REG_READ(ah, dcs_reg);
1619 if (ath9k_hw_check_dcs(chain_state, num_state, &hang_state, &hang_pos))
1620 goto hang_check_iter;
1621
1622 ath_dbg(ath9k_hw_common(ah), RESET,
1623 "MAC Hang signature 1 not found\n");
1624 return false;
1625
1626 hang_check_iter:
1627 ath_dbg(ath9k_hw_common(ah), RESET,
1628 "DCU registers: chain %08x complete %08x Hang: state %d pos %d\n",
1629 chain_state, comp_state, hang_state, hang_pos);
1630
1631 for (i = 0; i < NUM_STATUS_READS; i++) {
1632 chain_state = REG_READ(ah, dcs_reg);
1633 chain_state = (chain_state >> (5 * hang_pos)) & 0x1f;
1634 comp_state = REG_READ(ah, AR_DMADBG_6);
1635
1636 if (((comp_state & DCU_COMPLETE_STATE_MASK) !=
1637 DCU_COMPLETE_STATE) ||
1638 (chain_state != hang_state))
1639 return false;
1640 }
1641
1642 ath_dbg(ath9k_hw_common(ah), RESET, "MAC Hang signature 1 found\n");
1643
1644 return true;
1645 }
1646
1647 void ath9k_hw_check_nav(struct ath_hw *ah)
1648 {
1649 struct ath_common *common = ath9k_hw_common(ah);
1650 u32 val;
1651
1652 val = REG_READ(ah, AR_NAV);
1653 if (val != 0xdeadbeef && val > 0x7fff) {
1654 ath_dbg(common, BSTUCK, "Abnormal NAV: 0x%x\n", val);
1655 REG_WRITE(ah, AR_NAV, 0);
1656 }
1657 }
1658 EXPORT_SYMBOL(ath9k_hw_check_nav);
1659
1660 bool ath9k_hw_check_alive(struct ath_hw *ah)
1661 {
1662 int count = 50;
1663 u32 reg;
1664
1665 if (AR_SREV_9300(ah))
1666 return !ath9k_hw_detect_mac_hang(ah);
1667
1668 if (AR_SREV_9285_12_OR_LATER(ah))
1669 return true;
1670
1671 do {
1672 reg = REG_READ(ah, AR_OBS_BUS_1);
1673
1674 if ((reg & 0x7E7FFFEF) == 0x00702400)
1675 continue;
1676
1677 switch (reg & 0x7E000B00) {
1678 case 0x1E000000:
1679 case 0x52000B00:
1680 case 0x18000B00:
1681 continue;
1682 default:
1683 return true;
1684 }
1685 } while (count-- > 0);
1686
1687 return false;
1688 }
1689 EXPORT_SYMBOL(ath9k_hw_check_alive);
1690
1691 static void ath9k_hw_init_mfp(struct ath_hw *ah)
1692 {
1693 /* Setup MFP options for CCMP */
1694 if (AR_SREV_9280_20_OR_LATER(ah)) {
1695 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1696 * frames when constructing CCMP AAD. */
1697 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1698 0xc7ff);
1699 ah->sw_mgmt_crypto = false;
1700 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1701 /* Disable hardware crypto for management frames */
1702 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1703 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1704 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1705 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1706 ah->sw_mgmt_crypto = true;
1707 } else {
1708 ah->sw_mgmt_crypto = true;
1709 }
1710 }
1711
1712 static void ath9k_hw_reset_opmode(struct ath_hw *ah,
1713 u32 macStaId1, u32 saveDefAntenna)
1714 {
1715 struct ath_common *common = ath9k_hw_common(ah);
1716
1717 ENABLE_REGWRITE_BUFFER(ah);
1718
1719 REG_RMW(ah, AR_STA_ID1, macStaId1
1720 | AR_STA_ID1_RTS_USE_DEF
1721 | (ah->config.ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
1722 | ah->sta_id1_defaults,
1723 ~AR_STA_ID1_SADH_MASK);
1724 ath_hw_setbssidmask(common);
1725 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1726 ath9k_hw_write_associd(ah);
1727 REG_WRITE(ah, AR_ISR, ~0);
1728 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1729
1730 REGWRITE_BUFFER_FLUSH(ah);
1731
1732 ath9k_hw_set_operating_mode(ah, ah->opmode);
1733 }
1734
1735 static void ath9k_hw_init_queues(struct ath_hw *ah)
1736 {
1737 int i;
1738
1739 ENABLE_REGWRITE_BUFFER(ah);
1740
1741 for (i = 0; i < AR_NUM_DCU; i++)
1742 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1743
1744 REGWRITE_BUFFER_FLUSH(ah);
1745
1746 ah->intr_txqs = 0;
1747 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1748 ath9k_hw_resettxqueue(ah, i);
1749 }
1750
1751 /*
1752 * For big endian systems turn on swapping for descriptors
1753 */
1754 static void ath9k_hw_init_desc(struct ath_hw *ah)
1755 {
1756 struct ath_common *common = ath9k_hw_common(ah);
1757
1758 if (AR_SREV_9100(ah)) {
1759 u32 mask;
1760 mask = REG_READ(ah, AR_CFG);
1761 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1762 ath_dbg(common, RESET, "CFG Byte Swap Set 0x%x\n",
1763 mask);
1764 } else {
1765 mask = INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1766 REG_WRITE(ah, AR_CFG, mask);
1767 ath_dbg(common, RESET, "Setting CFG 0x%x\n",
1768 REG_READ(ah, AR_CFG));
1769 }
1770 } else {
1771 if (common->bus_ops->ath_bus_type == ATH_USB) {
1772 /* Configure AR9271 target WLAN */
1773 if (AR_SREV_9271(ah))
1774 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1775 else
1776 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1777 }
1778 #ifdef __BIG_ENDIAN
1779 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah) ||
1780 AR_SREV_9550(ah))
1781 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0);
1782 else
1783 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1784 #endif
1785 }
1786 }
1787
1788 /*
1789 * Fast channel change:
1790 * (Change synthesizer based on channel freq without resetting chip)
1791 */
1792 static int ath9k_hw_do_fastcc(struct ath_hw *ah, struct ath9k_channel *chan)
1793 {
1794 struct ath_common *common = ath9k_hw_common(ah);
1795 struct ath9k_hw_capabilities *pCap = &ah->caps;
1796 int ret;
1797
1798 if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI)
1799 goto fail;
1800
1801 if (ah->chip_fullsleep)
1802 goto fail;
1803
1804 if (!ah->curchan)
1805 goto fail;
1806
1807 if (chan->channel == ah->curchan->channel)
1808 goto fail;
1809
1810 if ((ah->curchan->channelFlags | chan->channelFlags) &
1811 (CHANNEL_HALF | CHANNEL_QUARTER))
1812 goto fail;
1813
1814 /*
1815 * If cross-band fcc is not supoprted, bail out if channelFlags differ.
1816 */
1817 if (!(pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) &&
1818 chan->channelFlags != ah->curchan->channelFlags)
1819 goto fail;
1820
1821 if (!ath9k_hw_check_alive(ah))
1822 goto fail;
1823
1824 /*
1825 * For AR9462, make sure that calibration data for
1826 * re-using are present.
1827 */
1828 if (AR_SREV_9462(ah) && (ah->caldata &&
1829 (!test_bit(TXIQCAL_DONE, &ah->caldata->cal_flags) ||
1830 !test_bit(TXCLCAL_DONE, &ah->caldata->cal_flags) ||
1831 !test_bit(RTT_DONE, &ah->caldata->cal_flags))))
1832 goto fail;
1833
1834 ath_dbg(common, RESET, "FastChannelChange for %d -> %d\n",
1835 ah->curchan->channel, chan->channel);
1836
1837 ret = ath9k_hw_channel_change(ah, chan);
1838 if (!ret)
1839 goto fail;
1840
1841 if (ath9k_hw_mci_is_enabled(ah))
1842 ar9003_mci_2g5g_switch(ah, false);
1843
1844 ath9k_hw_loadnf(ah, ah->curchan);
1845 ath9k_hw_start_nfcal(ah, true);
1846
1847 if (AR_SREV_9271(ah))
1848 ar9002_hw_load_ani_reg(ah, chan);
1849
1850 return 0;
1851 fail:
1852 return -EINVAL;
1853 }
1854
1855 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1856 struct ath9k_hw_cal_data *caldata, bool fastcc)
1857 {
1858 struct ath_common *common = ath9k_hw_common(ah);
1859 u32 saveLedState;
1860 u32 saveDefAntenna;
1861 u32 macStaId1;
1862 u64 tsf = 0;
1863 int r;
1864 bool start_mci_reset = false;
1865 bool save_fullsleep = ah->chip_fullsleep;
1866
1867 if (ath9k_hw_mci_is_enabled(ah)) {
1868 start_mci_reset = ar9003_mci_start_reset(ah, chan);
1869 if (start_mci_reset)
1870 return 0;
1871 }
1872
1873 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1874 return -EIO;
1875
1876 if (ah->curchan && !ah->chip_fullsleep)
1877 ath9k_hw_getnf(ah, ah->curchan);
1878
1879 ah->caldata = caldata;
1880 if (caldata && (chan->channel != caldata->channel ||
1881 chan->channelFlags != caldata->channelFlags)) {
1882 /* Operating channel changed, reset channel calibration data */
1883 memset(caldata, 0, sizeof(*caldata));
1884 ath9k_init_nfcal_hist_buffer(ah, chan);
1885 } else if (caldata) {
1886 clear_bit(PAPRD_PACKET_SENT, &caldata->cal_flags);
1887 }
1888 ah->noise = ath9k_hw_getchan_noise(ah, chan, chan->noisefloor);
1889
1890 if (fastcc) {
1891 r = ath9k_hw_do_fastcc(ah, chan);
1892 if (!r)
1893 return r;
1894 }
1895
1896 if (ath9k_hw_mci_is_enabled(ah))
1897 ar9003_mci_stop_bt(ah, save_fullsleep);
1898
1899 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1900 if (saveDefAntenna == 0)
1901 saveDefAntenna = 1;
1902
1903 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1904
1905 /* For chips on which RTC reset is done, save TSF before it gets cleared */
1906 if (AR_SREV_9100(ah) ||
1907 (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)))
1908 tsf = ath9k_hw_gettsf64(ah);
1909
1910 saveLedState = REG_READ(ah, AR_CFG_LED) &
1911 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1912 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1913
1914 ath9k_hw_mark_phy_inactive(ah);
1915
1916 ah->paprd_table_write_done = false;
1917
1918 /* Only required on the first reset */
1919 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1920 REG_WRITE(ah,
1921 AR9271_RESET_POWER_DOWN_CONTROL,
1922 AR9271_RADIO_RF_RST);
1923 udelay(50);
1924 }
1925
1926 if (!ath9k_hw_chip_reset(ah, chan)) {
1927 ath_err(common, "Chip reset failed\n");
1928 return -EINVAL;
1929 }
1930
1931 /* Only required on the first reset */
1932 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1933 ah->htc_reset_init = false;
1934 REG_WRITE(ah,
1935 AR9271_RESET_POWER_DOWN_CONTROL,
1936 AR9271_GATE_MAC_CTL);
1937 udelay(50);
1938 }
1939
1940 /* Restore TSF */
1941 if (tsf)
1942 ath9k_hw_settsf64(ah, tsf);
1943
1944 if (AR_SREV_9280_20_OR_LATER(ah))
1945 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1946
1947 if (!AR_SREV_9300_20_OR_LATER(ah))
1948 ar9002_hw_enable_async_fifo(ah);
1949
1950 r = ath9k_hw_process_ini(ah, chan);
1951 if (r)
1952 return r;
1953
1954 if (ath9k_hw_mci_is_enabled(ah))
1955 ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep);
1956
1957 /*
1958 * Some AR91xx SoC devices frequently fail to accept TSF writes
1959 * right after the chip reset. When that happens, write a new
1960 * value after the initvals have been applied, with an offset
1961 * based on measured time difference
1962 */
1963 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
1964 tsf += 1500;
1965 ath9k_hw_settsf64(ah, tsf);
1966 }
1967
1968 ath9k_hw_init_mfp(ah);
1969
1970 ath9k_hw_set_delta_slope(ah, chan);
1971 ath9k_hw_spur_mitigate_freq(ah, chan);
1972 ah->eep_ops->set_board_values(ah, chan);
1973
1974 ath9k_hw_reset_opmode(ah, macStaId1, saveDefAntenna);
1975
1976 r = ath9k_hw_rf_set_freq(ah, chan);
1977 if (r)
1978 return r;
1979
1980 ath9k_hw_set_clockrate(ah);
1981
1982 ath9k_hw_init_queues(ah);
1983 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
1984 ath9k_hw_ani_cache_ini_regs(ah);
1985 ath9k_hw_init_qos(ah);
1986
1987 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1988 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
1989
1990 ath9k_hw_init_global_settings(ah);
1991
1992 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1993 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
1994 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
1995 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
1996 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
1997 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1998 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
1999 }
2000
2001 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
2002
2003 ath9k_hw_set_dma(ah);
2004
2005 if (!ath9k_hw_mci_is_enabled(ah))
2006 REG_WRITE(ah, AR_OBS, 8);
2007
2008 if (ah->config.rx_intr_mitigation) {
2009 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2010 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2011 }
2012
2013 if (ah->config.tx_intr_mitigation) {
2014 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
2015 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
2016 }
2017
2018 ath9k_hw_init_bb(ah, chan);
2019
2020 if (caldata) {
2021 clear_bit(TXIQCAL_DONE, &caldata->cal_flags);
2022 clear_bit(TXCLCAL_DONE, &caldata->cal_flags);
2023 }
2024 if (!ath9k_hw_init_cal(ah, chan))
2025 return -EIO;
2026
2027 if (ath9k_hw_mci_is_enabled(ah) && ar9003_mci_end_reset(ah, chan, caldata))
2028 return -EIO;
2029
2030 ENABLE_REGWRITE_BUFFER(ah);
2031
2032 ath9k_hw_restore_chainmask(ah);
2033 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2034
2035 REGWRITE_BUFFER_FLUSH(ah);
2036
2037 ath9k_hw_init_desc(ah);
2038
2039 if (ath9k_hw_btcoex_is_enabled(ah))
2040 ath9k_hw_btcoex_enable(ah);
2041
2042 if (ath9k_hw_mci_is_enabled(ah))
2043 ar9003_mci_check_bt(ah);
2044
2045 ath9k_hw_loadnf(ah, chan);
2046 ath9k_hw_start_nfcal(ah, true);
2047
2048 if (AR_SREV_9300_20_OR_LATER(ah)) {
2049 ar9003_hw_bb_watchdog_config(ah);
2050 ar9003_hw_disable_phy_restart(ah);
2051 }
2052
2053 ath9k_hw_apply_gpio_override(ah);
2054
2055 if (AR_SREV_9565(ah) && common->bt_ant_diversity)
2056 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, AR_BTCOEX_WL_LNADIV_FORCE_ON);
2057
2058 return 0;
2059 }
2060 EXPORT_SYMBOL(ath9k_hw_reset);
2061
2062 /******************************/
2063 /* Power Management (Chipset) */
2064 /******************************/
2065
2066 /*
2067 * Notify Power Mgt is disabled in self-generated frames.
2068 * If requested, force chip to sleep.
2069 */
2070 static void ath9k_set_power_sleep(struct ath_hw *ah)
2071 {
2072 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2073
2074 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
2075 REG_CLR_BIT(ah, AR_TIMER_MODE, 0xff);
2076 REG_CLR_BIT(ah, AR_NDP2_TIMER_MODE, 0xff);
2077 REG_CLR_BIT(ah, AR_SLP32_INC, 0xfffff);
2078 /* xxx Required for WLAN only case ? */
2079 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0);
2080 udelay(100);
2081 }
2082
2083 /*
2084 * Clear the RTC force wake bit to allow the
2085 * mac to go to sleep.
2086 */
2087 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
2088
2089 if (ath9k_hw_mci_is_enabled(ah))
2090 udelay(100);
2091
2092 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
2093 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2094
2095 /* Shutdown chip. Active low */
2096 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) {
2097 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN);
2098 udelay(2);
2099 }
2100
2101 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
2102 if (AR_SREV_9300_20_OR_LATER(ah))
2103 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
2104 }
2105
2106 /*
2107 * Notify Power Management is enabled in self-generating
2108 * frames. If request, set power mode of chip to
2109 * auto/normal. Duration in units of 128us (1/8 TU).
2110 */
2111 static void ath9k_set_power_network_sleep(struct ath_hw *ah)
2112 {
2113 struct ath9k_hw_capabilities *pCap = &ah->caps;
2114
2115 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2116
2117 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2118 /* Set WakeOnInterrupt bit; clear ForceWake bit */
2119 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2120 AR_RTC_FORCE_WAKE_ON_INT);
2121 } else {
2122
2123 /* When chip goes into network sleep, it could be waken
2124 * up by MCI_INT interrupt caused by BT's HW messages
2125 * (LNA_xxx, CONT_xxx) which chould be in a very fast
2126 * rate (~100us). This will cause chip to leave and
2127 * re-enter network sleep mode frequently, which in
2128 * consequence will have WLAN MCI HW to generate lots of
2129 * SYS_WAKING and SYS_SLEEPING messages which will make
2130 * BT CPU to busy to process.
2131 */
2132 if (ath9k_hw_mci_is_enabled(ah))
2133 REG_CLR_BIT(ah, AR_MCI_INTERRUPT_RX_MSG_EN,
2134 AR_MCI_INTERRUPT_RX_HW_MSG_MASK);
2135 /*
2136 * Clear the RTC force wake bit to allow the
2137 * mac to go to sleep.
2138 */
2139 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
2140
2141 if (ath9k_hw_mci_is_enabled(ah))
2142 udelay(30);
2143 }
2144
2145 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
2146 if (AR_SREV_9300_20_OR_LATER(ah))
2147 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
2148 }
2149
2150 static bool ath9k_hw_set_power_awake(struct ath_hw *ah)
2151 {
2152 u32 val;
2153 int i;
2154
2155 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */
2156 if (AR_SREV_9300_20_OR_LATER(ah)) {
2157 REG_WRITE(ah, AR_WA, ah->WARegVal);
2158 udelay(10);
2159 }
2160
2161 if ((REG_READ(ah, AR_RTC_STATUS) &
2162 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2163 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
2164 return false;
2165 }
2166 if (!AR_SREV_9300_20_OR_LATER(ah))
2167 ath9k_hw_init_pll(ah, NULL);
2168 }
2169 if (AR_SREV_9100(ah))
2170 REG_SET_BIT(ah, AR_RTC_RESET,
2171 AR_RTC_RESET_EN);
2172
2173 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2174 AR_RTC_FORCE_WAKE_EN);
2175 udelay(50);
2176
2177 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2178 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2179 if (val == AR_RTC_STATUS_ON)
2180 break;
2181 udelay(50);
2182 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2183 AR_RTC_FORCE_WAKE_EN);
2184 }
2185 if (i == 0) {
2186 ath_err(ath9k_hw_common(ah),
2187 "Failed to wakeup in %uus\n",
2188 POWER_UP_TIME / 20);
2189 return false;
2190 }
2191
2192 if (ath9k_hw_mci_is_enabled(ah))
2193 ar9003_mci_set_power_awake(ah);
2194
2195 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2196
2197 return true;
2198 }
2199
2200 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2201 {
2202 struct ath_common *common = ath9k_hw_common(ah);
2203 int status = true;
2204 static const char *modes[] = {
2205 "AWAKE",
2206 "FULL-SLEEP",
2207 "NETWORK SLEEP",
2208 "UNDEFINED"
2209 };
2210
2211 if (ah->power_mode == mode)
2212 return status;
2213
2214 ath_dbg(common, RESET, "%s -> %s\n",
2215 modes[ah->power_mode], modes[mode]);
2216
2217 switch (mode) {
2218 case ATH9K_PM_AWAKE:
2219 status = ath9k_hw_set_power_awake(ah);
2220 break;
2221 case ATH9K_PM_FULL_SLEEP:
2222 if (ath9k_hw_mci_is_enabled(ah))
2223 ar9003_mci_set_full_sleep(ah);
2224
2225 ath9k_set_power_sleep(ah);
2226 ah->chip_fullsleep = true;
2227 break;
2228 case ATH9K_PM_NETWORK_SLEEP:
2229 ath9k_set_power_network_sleep(ah);
2230 break;
2231 default:
2232 ath_err(common, "Unknown power mode %u\n", mode);
2233 return false;
2234 }
2235 ah->power_mode = mode;
2236
2237 /*
2238 * XXX: If this warning never comes up after a while then
2239 * simply keep the ATH_DBG_WARN_ON_ONCE() but make
2240 * ath9k_hw_setpower() return type void.
2241 */
2242
2243 if (!(ah->ah_flags & AH_UNPLUGGED))
2244 ATH_DBG_WARN_ON_ONCE(!status);
2245
2246 return status;
2247 }
2248 EXPORT_SYMBOL(ath9k_hw_setpower);
2249
2250 /*******************/
2251 /* Beacon Handling */
2252 /*******************/
2253
2254 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
2255 {
2256 int flags = 0;
2257
2258 ENABLE_REGWRITE_BUFFER(ah);
2259
2260 switch (ah->opmode) {
2261 case NL80211_IFTYPE_ADHOC:
2262 REG_SET_BIT(ah, AR_TXCFG,
2263 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
2264 REG_WRITE(ah, AR_NEXT_NDP_TIMER, next_beacon +
2265 TU_TO_USEC(ah->atim_window ? ah->atim_window : 1));
2266 flags |= AR_NDP_TIMER_EN;
2267 case NL80211_IFTYPE_MESH_POINT:
2268 case NL80211_IFTYPE_AP:
2269 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon);
2270 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon -
2271 TU_TO_USEC(ah->config.dma_beacon_response_time));
2272 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon -
2273 TU_TO_USEC(ah->config.sw_beacon_response_time));
2274 flags |=
2275 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
2276 break;
2277 default:
2278 ath_dbg(ath9k_hw_common(ah), BEACON,
2279 "%s: unsupported opmode: %d\n", __func__, ah->opmode);
2280 return;
2281 break;
2282 }
2283
2284 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period);
2285 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period);
2286 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period);
2287 REG_WRITE(ah, AR_NDP_PERIOD, beacon_period);
2288
2289 REGWRITE_BUFFER_FLUSH(ah);
2290
2291 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
2292 }
2293 EXPORT_SYMBOL(ath9k_hw_beaconinit);
2294
2295 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
2296 const struct ath9k_beacon_state *bs)
2297 {
2298 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
2299 struct ath9k_hw_capabilities *pCap = &ah->caps;
2300 struct ath_common *common = ath9k_hw_common(ah);
2301
2302 ENABLE_REGWRITE_BUFFER(ah);
2303
2304 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
2305
2306 REG_WRITE(ah, AR_BEACON_PERIOD,
2307 TU_TO_USEC(bs->bs_intval));
2308 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
2309 TU_TO_USEC(bs->bs_intval));
2310
2311 REGWRITE_BUFFER_FLUSH(ah);
2312
2313 REG_RMW_FIELD(ah, AR_RSSI_THR,
2314 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
2315
2316 beaconintval = bs->bs_intval;
2317
2318 if (bs->bs_sleepduration > beaconintval)
2319 beaconintval = bs->bs_sleepduration;
2320
2321 dtimperiod = bs->bs_dtimperiod;
2322 if (bs->bs_sleepduration > dtimperiod)
2323 dtimperiod = bs->bs_sleepduration;
2324
2325 if (beaconintval == dtimperiod)
2326 nextTbtt = bs->bs_nextdtim;
2327 else
2328 nextTbtt = bs->bs_nexttbtt;
2329
2330 ath_dbg(common, BEACON, "next DTIM %d\n", bs->bs_nextdtim);
2331 ath_dbg(common, BEACON, "next beacon %d\n", nextTbtt);
2332 ath_dbg(common, BEACON, "beacon period %d\n", beaconintval);
2333 ath_dbg(common, BEACON, "DTIM period %d\n", dtimperiod);
2334
2335 ENABLE_REGWRITE_BUFFER(ah);
2336
2337 REG_WRITE(ah, AR_NEXT_DTIM,
2338 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
2339 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
2340
2341 REG_WRITE(ah, AR_SLEEP1,
2342 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
2343 | AR_SLEEP1_ASSUME_DTIM);
2344
2345 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
2346 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
2347 else
2348 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
2349
2350 REG_WRITE(ah, AR_SLEEP2,
2351 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
2352
2353 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
2354 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
2355
2356 REGWRITE_BUFFER_FLUSH(ah);
2357
2358 REG_SET_BIT(ah, AR_TIMER_MODE,
2359 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
2360 AR_DTIM_TIMER_EN);
2361
2362 /* TSF Out of Range Threshold */
2363 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
2364 }
2365 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
2366
2367 /*******************/
2368 /* HW Capabilities */
2369 /*******************/
2370
2371 static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask)
2372 {
2373 eeprom_chainmask &= chip_chainmask;
2374 if (eeprom_chainmask)
2375 return eeprom_chainmask;
2376 else
2377 return chip_chainmask;
2378 }
2379
2380 /**
2381 * ath9k_hw_dfs_tested - checks if DFS has been tested with used chipset
2382 * @ah: the atheros hardware data structure
2383 *
2384 * We enable DFS support upstream on chipsets which have passed a series
2385 * of tests. The testing requirements are going to be documented. Desired
2386 * test requirements are documented at:
2387 *
2388 * http://wireless.kernel.org/en/users/Drivers/ath9k/dfs
2389 *
2390 * Once a new chipset gets properly tested an individual commit can be used
2391 * to document the testing for DFS for that chipset.
2392 */
2393 static bool ath9k_hw_dfs_tested(struct ath_hw *ah)
2394 {
2395
2396 switch (ah->hw_version.macVersion) {
2397 /* for temporary testing DFS with 9280 */
2398 case AR_SREV_VERSION_9280:
2399 /* AR9580 will likely be our first target to get testing on */
2400 case AR_SREV_VERSION_9580:
2401 return true;
2402 default:
2403 return false;
2404 }
2405 }
2406
2407 int ath9k_hw_fill_cap_info(struct ath_hw *ah)
2408 {
2409 struct ath9k_hw_capabilities *pCap = &ah->caps;
2410 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2411 struct ath_common *common = ath9k_hw_common(ah);
2412 unsigned int chip_chainmask;
2413
2414 u16 eeval;
2415 u8 ant_div_ctl1, tx_chainmask, rx_chainmask;
2416
2417 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
2418 regulatory->current_rd = eeval;
2419
2420 if (ah->opmode != NL80211_IFTYPE_AP &&
2421 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
2422 if (regulatory->current_rd == 0x64 ||
2423 regulatory->current_rd == 0x65)
2424 regulatory->current_rd += 5;
2425 else if (regulatory->current_rd == 0x41)
2426 regulatory->current_rd = 0x43;
2427 ath_dbg(common, REGULATORY, "regdomain mapped to 0x%x\n",
2428 regulatory->current_rd);
2429 }
2430
2431 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
2432 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
2433 ath_err(common,
2434 "no band has been marked as supported in EEPROM\n");
2435 return -EINVAL;
2436 }
2437
2438 if (eeval & AR5416_OPFLAGS_11A)
2439 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
2440
2441 if (eeval & AR5416_OPFLAGS_11G)
2442 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
2443
2444 if (AR_SREV_9485(ah) ||
2445 AR_SREV_9285(ah) ||
2446 AR_SREV_9330(ah) ||
2447 AR_SREV_9565(ah))
2448 chip_chainmask = 1;
2449 else if (AR_SREV_9462(ah))
2450 chip_chainmask = 3;
2451 else if (!AR_SREV_9280_20_OR_LATER(ah))
2452 chip_chainmask = 7;
2453 else if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9340(ah))
2454 chip_chainmask = 3;
2455 else
2456 chip_chainmask = 7;
2457
2458 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
2459 /*
2460 * For AR9271 we will temporarilly uses the rx chainmax as read from
2461 * the EEPROM.
2462 */
2463 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
2464 !(eeval & AR5416_OPFLAGS_11A) &&
2465 !(AR_SREV_9271(ah)))
2466 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
2467 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
2468 else if (AR_SREV_9100(ah))
2469 pCap->rx_chainmask = 0x7;
2470 else
2471 /* Use rx_chainmask from EEPROM. */
2472 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
2473
2474 pCap->tx_chainmask = fixup_chainmask(chip_chainmask, pCap->tx_chainmask);
2475 pCap->rx_chainmask = fixup_chainmask(chip_chainmask, pCap->rx_chainmask);
2476 ah->txchainmask = pCap->tx_chainmask;
2477 ah->rxchainmask = pCap->rx_chainmask;
2478
2479 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
2480
2481 /* enable key search for every frame in an aggregate */
2482 if (AR_SREV_9300_20_OR_LATER(ah))
2483 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
2484
2485 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
2486
2487 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
2488 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2489 else
2490 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
2491
2492 if (AR_SREV_9271(ah))
2493 pCap->num_gpio_pins = AR9271_NUM_GPIO;
2494 else if (AR_DEVID_7010(ah))
2495 pCap->num_gpio_pins = AR7010_NUM_GPIO;
2496 else if (AR_SREV_9300_20_OR_LATER(ah))
2497 pCap->num_gpio_pins = AR9300_NUM_GPIO;
2498 else if (AR_SREV_9287_11_OR_LATER(ah))
2499 pCap->num_gpio_pins = AR9287_NUM_GPIO;
2500 else if (AR_SREV_9285_12_OR_LATER(ah))
2501 pCap->num_gpio_pins = AR9285_NUM_GPIO;
2502 else if (AR_SREV_9280_20_OR_LATER(ah))
2503 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2504 else
2505 pCap->num_gpio_pins = AR_NUM_GPIO;
2506
2507 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah))
2508 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
2509 else
2510 pCap->rts_aggr_limit = (8 * 1024);
2511
2512 #ifdef CONFIG_ATH9K_RFKILL
2513 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2514 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2515 ah->rfkill_gpio =
2516 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2517 ah->rfkill_polarity =
2518 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
2519
2520 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
2521 }
2522 #endif
2523 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
2524 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2525 else
2526 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
2527
2528 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
2529 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2530 else
2531 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
2532
2533 if (AR_SREV_9300_20_OR_LATER(ah)) {
2534 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
2535 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah) && !AR_SREV_9565(ah))
2536 pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
2537
2538 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2539 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2540 pCap->rx_status_len = sizeof(struct ar9003_rxs);
2541 pCap->tx_desc_len = sizeof(struct ar9003_txc);
2542 pCap->txs_len = sizeof(struct ar9003_txs);
2543 } else {
2544 pCap->tx_desc_len = sizeof(struct ath_desc);
2545 if (AR_SREV_9280_20(ah))
2546 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
2547 }
2548
2549 if (AR_SREV_9300_20_OR_LATER(ah))
2550 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2551
2552 if (AR_SREV_9300_20_OR_LATER(ah))
2553 ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
2554
2555 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
2556 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
2557
2558 if (AR_SREV_9285(ah)) {
2559 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
2560 ant_div_ctl1 =
2561 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2562 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1)) {
2563 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2564 ath_info(common, "Enable LNA combining\n");
2565 }
2566 }
2567 }
2568
2569 if (AR_SREV_9300_20_OR_LATER(ah)) {
2570 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
2571 pCap->hw_caps |= ATH9K_HW_CAP_APM;
2572 }
2573
2574 if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
2575 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2576 if ((ant_div_ctl1 >> 0x6) == 0x3) {
2577 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2578 ath_info(common, "Enable LNA combining\n");
2579 }
2580 }
2581
2582 if (ath9k_hw_dfs_tested(ah))
2583 pCap->hw_caps |= ATH9K_HW_CAP_DFS;
2584
2585 tx_chainmask = pCap->tx_chainmask;
2586 rx_chainmask = pCap->rx_chainmask;
2587 while (tx_chainmask || rx_chainmask) {
2588 if (tx_chainmask & BIT(0))
2589 pCap->max_txchains++;
2590 if (rx_chainmask & BIT(0))
2591 pCap->max_rxchains++;
2592
2593 tx_chainmask >>= 1;
2594 rx_chainmask >>= 1;
2595 }
2596
2597 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
2598 if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE))
2599 pCap->hw_caps |= ATH9K_HW_CAP_MCI;
2600
2601 if (AR_SREV_9462_20_OR_LATER(ah))
2602 pCap->hw_caps |= ATH9K_HW_CAP_RTT;
2603 }
2604
2605 if (AR_SREV_9462(ah))
2606 pCap->hw_caps |= ATH9K_HW_WOW_DEVICE_CAPABLE;
2607
2608 if (AR_SREV_9300_20_OR_LATER(ah) &&
2609 ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
2610 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
2611
2612 /*
2613 * Fast channel change across bands is available
2614 * only for AR9462 and AR9565.
2615 */
2616 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
2617 pCap->hw_caps |= ATH9K_HW_CAP_FCC_BAND_SWITCH;
2618
2619 return 0;
2620 }
2621
2622 /****************************/
2623 /* GPIO / RFKILL / Antennae */
2624 /****************************/
2625
2626 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
2627 u32 gpio, u32 type)
2628 {
2629 int addr;
2630 u32 gpio_shift, tmp;
2631
2632 if (gpio > 11)
2633 addr = AR_GPIO_OUTPUT_MUX3;
2634 else if (gpio > 5)
2635 addr = AR_GPIO_OUTPUT_MUX2;
2636 else
2637 addr = AR_GPIO_OUTPUT_MUX1;
2638
2639 gpio_shift = (gpio % 6) * 5;
2640
2641 if (AR_SREV_9280_20_OR_LATER(ah)
2642 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2643 REG_RMW(ah, addr, (type << gpio_shift),
2644 (0x1f << gpio_shift));
2645 } else {
2646 tmp = REG_READ(ah, addr);
2647 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2648 tmp &= ~(0x1f << gpio_shift);
2649 tmp |= (type << gpio_shift);
2650 REG_WRITE(ah, addr, tmp);
2651 }
2652 }
2653
2654 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
2655 {
2656 u32 gpio_shift;
2657
2658 BUG_ON(gpio >= ah->caps.num_gpio_pins);
2659
2660 if (AR_DEVID_7010(ah)) {
2661 gpio_shift = gpio;
2662 REG_RMW(ah, AR7010_GPIO_OE,
2663 (AR7010_GPIO_OE_AS_INPUT << gpio_shift),
2664 (AR7010_GPIO_OE_MASK << gpio_shift));
2665 return;
2666 }
2667
2668 gpio_shift = gpio << 1;
2669 REG_RMW(ah,
2670 AR_GPIO_OE_OUT,
2671 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2672 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2673 }
2674 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
2675
2676 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
2677 {
2678 #define MS_REG_READ(x, y) \
2679 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2680
2681 if (gpio >= ah->caps.num_gpio_pins)
2682 return 0xffffffff;
2683
2684 if (AR_DEVID_7010(ah)) {
2685 u32 val;
2686 val = REG_READ(ah, AR7010_GPIO_IN);
2687 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0;
2688 } else if (AR_SREV_9300_20_OR_LATER(ah))
2689 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) &
2690 AR_GPIO_BIT(gpio)) != 0;
2691 else if (AR_SREV_9271(ah))
2692 return MS_REG_READ(AR9271, gpio) != 0;
2693 else if (AR_SREV_9287_11_OR_LATER(ah))
2694 return MS_REG_READ(AR9287, gpio) != 0;
2695 else if (AR_SREV_9285_12_OR_LATER(ah))
2696 return MS_REG_READ(AR9285, gpio) != 0;
2697 else if (AR_SREV_9280_20_OR_LATER(ah))
2698 return MS_REG_READ(AR928X, gpio) != 0;
2699 else
2700 return MS_REG_READ(AR, gpio) != 0;
2701 }
2702 EXPORT_SYMBOL(ath9k_hw_gpio_get);
2703
2704 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
2705 u32 ah_signal_type)
2706 {
2707 u32 gpio_shift;
2708
2709 if (AR_DEVID_7010(ah)) {
2710 gpio_shift = gpio;
2711 REG_RMW(ah, AR7010_GPIO_OE,
2712 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift),
2713 (AR7010_GPIO_OE_MASK << gpio_shift));
2714 return;
2715 }
2716
2717 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
2718 gpio_shift = 2 * gpio;
2719 REG_RMW(ah,
2720 AR_GPIO_OE_OUT,
2721 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2722 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2723 }
2724 EXPORT_SYMBOL(ath9k_hw_cfg_output);
2725
2726 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
2727 {
2728 if (AR_DEVID_7010(ah)) {
2729 val = val ? 0 : 1;
2730 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio),
2731 AR_GPIO_BIT(gpio));
2732 return;
2733 }
2734
2735 if (AR_SREV_9271(ah))
2736 val = ~val;
2737
2738 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2739 AR_GPIO_BIT(gpio));
2740 }
2741 EXPORT_SYMBOL(ath9k_hw_set_gpio);
2742
2743 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
2744 {
2745 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
2746 }
2747 EXPORT_SYMBOL(ath9k_hw_setantenna);
2748
2749 /*********************/
2750 /* General Operation */
2751 /*********************/
2752
2753 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
2754 {
2755 u32 bits = REG_READ(ah, AR_RX_FILTER);
2756 u32 phybits = REG_READ(ah, AR_PHY_ERR);
2757
2758 if (phybits & AR_PHY_ERR_RADAR)
2759 bits |= ATH9K_RX_FILTER_PHYRADAR;
2760 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2761 bits |= ATH9K_RX_FILTER_PHYERR;
2762
2763 return bits;
2764 }
2765 EXPORT_SYMBOL(ath9k_hw_getrxfilter);
2766
2767 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
2768 {
2769 u32 phybits;
2770
2771 ENABLE_REGWRITE_BUFFER(ah);
2772
2773 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
2774 bits |= ATH9K_RX_FILTER_CONTROL_WRAPPER;
2775
2776 REG_WRITE(ah, AR_RX_FILTER, bits);
2777
2778 phybits = 0;
2779 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2780 phybits |= AR_PHY_ERR_RADAR;
2781 if (bits & ATH9K_RX_FILTER_PHYERR)
2782 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2783 REG_WRITE(ah, AR_PHY_ERR, phybits);
2784
2785 if (phybits)
2786 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
2787 else
2788 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
2789
2790 REGWRITE_BUFFER_FLUSH(ah);
2791 }
2792 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
2793
2794 bool ath9k_hw_phy_disable(struct ath_hw *ah)
2795 {
2796 if (ath9k_hw_mci_is_enabled(ah))
2797 ar9003_mci_bt_gain_ctrl(ah);
2798
2799 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2800 return false;
2801
2802 ath9k_hw_init_pll(ah, NULL);
2803 ah->htc_reset_init = true;
2804 return true;
2805 }
2806 EXPORT_SYMBOL(ath9k_hw_phy_disable);
2807
2808 bool ath9k_hw_disable(struct ath_hw *ah)
2809 {
2810 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2811 return false;
2812
2813 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2814 return false;
2815
2816 ath9k_hw_init_pll(ah, NULL);
2817 return true;
2818 }
2819 EXPORT_SYMBOL(ath9k_hw_disable);
2820
2821 static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan)
2822 {
2823 enum eeprom_param gain_param;
2824
2825 if (IS_CHAN_2GHZ(chan))
2826 gain_param = EEP_ANTENNA_GAIN_2G;
2827 else
2828 gain_param = EEP_ANTENNA_GAIN_5G;
2829
2830 return ah->eep_ops->get_eeprom(ah, gain_param);
2831 }
2832
2833 void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan,
2834 bool test)
2835 {
2836 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2837 struct ieee80211_channel *channel;
2838 int chan_pwr, new_pwr, max_gain;
2839 int ant_gain, ant_reduction = 0;
2840
2841 if (!chan)
2842 return;
2843
2844 channel = chan->chan;
2845 chan_pwr = min_t(int, channel->max_power * 2, MAX_RATE_POWER);
2846 new_pwr = min_t(int, chan_pwr, reg->power_limit);
2847 max_gain = chan_pwr - new_pwr + channel->max_antenna_gain * 2;
2848
2849 ant_gain = get_antenna_gain(ah, chan);
2850 if (ant_gain > max_gain)
2851 ant_reduction = ant_gain - max_gain;
2852
2853 ah->eep_ops->set_txpower(ah, chan,
2854 ath9k_regd_get_ctl(reg, chan),
2855 ant_reduction, new_pwr, test);
2856 }
2857
2858 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
2859 {
2860 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2861 struct ath9k_channel *chan = ah->curchan;
2862 struct ieee80211_channel *channel = chan->chan;
2863
2864 reg->power_limit = min_t(u32, limit, MAX_RATE_POWER);
2865 if (test)
2866 channel->max_power = MAX_RATE_POWER / 2;
2867
2868 ath9k_hw_apply_txpower(ah, chan, test);
2869
2870 if (test)
2871 channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2);
2872 }
2873 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
2874
2875 void ath9k_hw_setopmode(struct ath_hw *ah)
2876 {
2877 ath9k_hw_set_operating_mode(ah, ah->opmode);
2878 }
2879 EXPORT_SYMBOL(ath9k_hw_setopmode);
2880
2881 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
2882 {
2883 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2884 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
2885 }
2886 EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
2887
2888 void ath9k_hw_write_associd(struct ath_hw *ah)
2889 {
2890 struct ath_common *common = ath9k_hw_common(ah);
2891
2892 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2893 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2894 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2895 }
2896 EXPORT_SYMBOL(ath9k_hw_write_associd);
2897
2898 #define ATH9K_MAX_TSF_READ 10
2899
2900 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
2901 {
2902 u32 tsf_lower, tsf_upper1, tsf_upper2;
2903 int i;
2904
2905 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2906 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2907 tsf_lower = REG_READ(ah, AR_TSF_L32);
2908 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2909 if (tsf_upper2 == tsf_upper1)
2910 break;
2911 tsf_upper1 = tsf_upper2;
2912 }
2913
2914 WARN_ON( i == ATH9K_MAX_TSF_READ );
2915
2916 return (((u64)tsf_upper1 << 32) | tsf_lower);
2917 }
2918 EXPORT_SYMBOL(ath9k_hw_gettsf64);
2919
2920 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
2921 {
2922 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
2923 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
2924 }
2925 EXPORT_SYMBOL(ath9k_hw_settsf64);
2926
2927 void ath9k_hw_reset_tsf(struct ath_hw *ah)
2928 {
2929 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2930 AH_TSF_WRITE_TIMEOUT))
2931 ath_dbg(ath9k_hw_common(ah), RESET,
2932 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
2933
2934 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2935 }
2936 EXPORT_SYMBOL(ath9k_hw_reset_tsf);
2937
2938 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set)
2939 {
2940 if (set)
2941 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
2942 else
2943 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
2944 }
2945 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
2946
2947 void ath9k_hw_set11nmac2040(struct ath_hw *ah, struct ath9k_channel *chan)
2948 {
2949 u32 macmode;
2950
2951 if (IS_CHAN_HT40(chan) && !ah->config.cwm_ignore_extcca)
2952 macmode = AR_2040_JOINED_RX_CLEAR;
2953 else
2954 macmode = 0;
2955
2956 REG_WRITE(ah, AR_2040_MODE, macmode);
2957 }
2958
2959 /* HW Generic timers configuration */
2960
2961 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2962 {
2963 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2964 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2965 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2966 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2967 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2968 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2969 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2970 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2971 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2972 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2973 AR_NDP2_TIMER_MODE, 0x0002},
2974 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2975 AR_NDP2_TIMER_MODE, 0x0004},
2976 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2977 AR_NDP2_TIMER_MODE, 0x0008},
2978 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2979 AR_NDP2_TIMER_MODE, 0x0010},
2980 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2981 AR_NDP2_TIMER_MODE, 0x0020},
2982 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2983 AR_NDP2_TIMER_MODE, 0x0040},
2984 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2985 AR_NDP2_TIMER_MODE, 0x0080}
2986 };
2987
2988 /* HW generic timer primitives */
2989
2990 /* compute and clear index of rightmost 1 */
2991 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
2992 {
2993 u32 b;
2994
2995 b = *mask;
2996 b &= (0-b);
2997 *mask &= ~b;
2998 b *= debruijn32;
2999 b >>= 27;
3000
3001 return timer_table->gen_timer_index[b];
3002 }
3003
3004 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
3005 {
3006 return REG_READ(ah, AR_TSF_L32);
3007 }
3008 EXPORT_SYMBOL(ath9k_hw_gettsf32);
3009
3010 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
3011 void (*trigger)(void *),
3012 void (*overflow)(void *),
3013 void *arg,
3014 u8 timer_index)
3015 {
3016 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3017 struct ath_gen_timer *timer;
3018
3019 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
3020 if (timer == NULL)
3021 return NULL;
3022
3023 /* allocate a hardware generic timer slot */
3024 timer_table->timers[timer_index] = timer;
3025 timer->index = timer_index;
3026 timer->trigger = trigger;
3027 timer->overflow = overflow;
3028 timer->arg = arg;
3029
3030 return timer;
3031 }
3032 EXPORT_SYMBOL(ath_gen_timer_alloc);
3033
3034 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
3035 struct ath_gen_timer *timer,
3036 u32 trig_timeout,
3037 u32 timer_period)
3038 {
3039 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3040 u32 tsf, timer_next;
3041
3042 BUG_ON(!timer_period);
3043
3044 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
3045
3046 tsf = ath9k_hw_gettsf32(ah);
3047
3048 timer_next = tsf + trig_timeout;
3049
3050 ath_dbg(ath9k_hw_common(ah), BTCOEX,
3051 "current tsf %x period %x timer_next %x\n",
3052 tsf, timer_period, timer_next);
3053
3054 /*
3055 * Program generic timer registers
3056 */
3057 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
3058 timer_next);
3059 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
3060 timer_period);
3061 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3062 gen_tmr_configuration[timer->index].mode_mask);
3063
3064 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
3065 /*
3066 * Starting from AR9462, each generic timer can select which tsf
3067 * to use. But we still follow the old rule, 0 - 7 use tsf and
3068 * 8 - 15 use tsf2.
3069 */
3070 if ((timer->index < AR_GEN_TIMER_BANK_1_LEN))
3071 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3072 (1 << timer->index));
3073 else
3074 REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3075 (1 << timer->index));
3076 }
3077
3078 /* Enable both trigger and thresh interrupt masks */
3079 REG_SET_BIT(ah, AR_IMR_S5,
3080 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3081 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3082 }
3083 EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
3084
3085 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
3086 {
3087 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3088
3089 if ((timer->index < AR_FIRST_NDP_TIMER) ||
3090 (timer->index >= ATH_MAX_GEN_TIMER)) {
3091 return;
3092 }
3093
3094 /* Clear generic timer enable bits. */
3095 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3096 gen_tmr_configuration[timer->index].mode_mask);
3097
3098 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
3099 /*
3100 * Need to switch back to TSF if it was using TSF2.
3101 */
3102 if ((timer->index >= AR_GEN_TIMER_BANK_1_LEN)) {
3103 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3104 (1 << timer->index));
3105 }
3106 }
3107
3108 /* Disable both trigger and thresh interrupt masks */
3109 REG_CLR_BIT(ah, AR_IMR_S5,
3110 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3111 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3112
3113 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
3114 }
3115 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
3116
3117 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
3118 {
3119 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3120
3121 /* free the hardware generic timer slot */
3122 timer_table->timers[timer->index] = NULL;
3123 kfree(timer);
3124 }
3125 EXPORT_SYMBOL(ath_gen_timer_free);
3126
3127 /*
3128 * Generic Timer Interrupts handling
3129 */
3130 void ath_gen_timer_isr(struct ath_hw *ah)
3131 {
3132 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3133 struct ath_gen_timer *timer;
3134 struct ath_common *common = ath9k_hw_common(ah);
3135 u32 trigger_mask, thresh_mask, index;
3136
3137 /* get hardware generic timer interrupt status */
3138 trigger_mask = ah->intr_gen_timer_trigger;
3139 thresh_mask = ah->intr_gen_timer_thresh;
3140 trigger_mask &= timer_table->timer_mask.val;
3141 thresh_mask &= timer_table->timer_mask.val;
3142
3143 trigger_mask &= ~thresh_mask;
3144
3145 while (thresh_mask) {
3146 index = rightmost_index(timer_table, &thresh_mask);
3147 timer = timer_table->timers[index];
3148 BUG_ON(!timer);
3149 ath_dbg(common, BTCOEX, "TSF overflow for Gen timer %d\n",
3150 index);
3151 timer->overflow(timer->arg);
3152 }
3153
3154 while (trigger_mask) {
3155 index = rightmost_index(timer_table, &trigger_mask);
3156 timer = timer_table->timers[index];
3157 BUG_ON(!timer);
3158 ath_dbg(common, BTCOEX,
3159 "Gen timer[%d] trigger\n", index);
3160 timer->trigger(timer->arg);
3161 }
3162 }
3163 EXPORT_SYMBOL(ath_gen_timer_isr);
3164
3165 /********/
3166 /* HTC */
3167 /********/
3168
3169 static struct {
3170 u32 version;
3171 const char * name;
3172 } ath_mac_bb_names[] = {
3173 /* Devices with external radios */
3174 { AR_SREV_VERSION_5416_PCI, "5416" },
3175 { AR_SREV_VERSION_5416_PCIE, "5418" },
3176 { AR_SREV_VERSION_9100, "9100" },
3177 { AR_SREV_VERSION_9160, "9160" },
3178 /* Single-chip solutions */
3179 { AR_SREV_VERSION_9280, "9280" },
3180 { AR_SREV_VERSION_9285, "9285" },
3181 { AR_SREV_VERSION_9287, "9287" },
3182 { AR_SREV_VERSION_9271, "9271" },
3183 { AR_SREV_VERSION_9300, "9300" },
3184 { AR_SREV_VERSION_9330, "9330" },
3185 { AR_SREV_VERSION_9340, "9340" },
3186 { AR_SREV_VERSION_9485, "9485" },
3187 { AR_SREV_VERSION_9462, "9462" },
3188 { AR_SREV_VERSION_9550, "9550" },
3189 { AR_SREV_VERSION_9565, "9565" },
3190 };
3191
3192 /* For devices with external radios */
3193 static struct {
3194 u16 version;
3195 const char * name;
3196 } ath_rf_names[] = {
3197 { 0, "5133" },
3198 { AR_RAD5133_SREV_MAJOR, "5133" },
3199 { AR_RAD5122_SREV_MAJOR, "5122" },
3200 { AR_RAD2133_SREV_MAJOR, "2133" },
3201 { AR_RAD2122_SREV_MAJOR, "2122" }
3202 };
3203
3204 /*
3205 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3206 */
3207 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
3208 {
3209 int i;
3210
3211 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3212 if (ath_mac_bb_names[i].version == mac_bb_version) {
3213 return ath_mac_bb_names[i].name;
3214 }
3215 }
3216
3217 return "????";
3218 }
3219
3220 /*
3221 * Return the RF name. "????" is returned if the RF is unknown.
3222 * Used for devices with external radios.
3223 */
3224 static const char *ath9k_hw_rf_name(u16 rf_version)
3225 {
3226 int i;
3227
3228 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3229 if (ath_rf_names[i].version == rf_version) {
3230 return ath_rf_names[i].name;
3231 }
3232 }
3233
3234 return "????";
3235 }
3236
3237 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
3238 {
3239 int used;
3240
3241 /* chipsets >= AR9280 are single-chip */
3242 if (AR_SREV_9280_20_OR_LATER(ah)) {
3243 used = scnprintf(hw_name, len,
3244 "Atheros AR%s Rev:%x",
3245 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3246 ah->hw_version.macRev);
3247 }
3248 else {
3249 used = scnprintf(hw_name, len,
3250 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3251 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3252 ah->hw_version.macRev,
3253 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev
3254 & AR_RADIO_SREV_MAJOR)),
3255 ah->hw_version.phyRev);
3256 }
3257
3258 hw_name[used] = '\0';
3259 }
3260 EXPORT_SYMBOL(ath9k_hw_name);
Linux kernel - Deliverables
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