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[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / hw.h
1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #ifndef HW_H
18 #define HW_H
19
20 #include <linux/if_ether.h>
21 #include <linux/delay.h>
22 #include <linux/io.h>
23
24 #include "mac.h"
25 #include "ani.h"
26 #include "eeprom.h"
27 #include "calib.h"
28 #include "reg.h"
29 #include "phy.h"
30 #include "btcoex.h"
31
32 #include "../regd.h"
33
34 #define ATHEROS_VENDOR_ID 0x168c
35
36 #define AR5416_DEVID_PCI 0x0023
37 #define AR5416_DEVID_PCIE 0x0024
38 #define AR9160_DEVID_PCI 0x0027
39 #define AR9280_DEVID_PCI 0x0029
40 #define AR9280_DEVID_PCIE 0x002a
41 #define AR9285_DEVID_PCIE 0x002b
42 #define AR2427_DEVID_PCIE 0x002c
43 #define AR9287_DEVID_PCI 0x002d
44 #define AR9287_DEVID_PCIE 0x002e
45 #define AR9300_DEVID_PCIE 0x0030
46 #define AR9300_DEVID_AR9340 0x0031
47 #define AR9300_DEVID_AR9485_PCIE 0x0032
48 #define AR9300_DEVID_AR9580 0x0033
49 #define AR9300_DEVID_AR9462 0x0034
50 #define AR9300_DEVID_AR9330 0x0035
51
52 #define AR5416_AR9100_DEVID 0x000b
53
54 #define AR_SUBVENDOR_ID_NOG 0x0e11
55 #define AR_SUBVENDOR_ID_NEW_A 0x7065
56 #define AR5416_MAGIC 0x19641014
57
58 #define AR9280_COEX2WIRE_SUBSYSID 0x309b
59 #define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa
60 #define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab
61
62 #define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1)
63
64 #define ATH_DEFAULT_NOISE_FLOOR -95
65
66 #define ATH9K_RSSI_BAD -128
67
68 #define ATH9K_NUM_CHANNELS 38
69
70 /* Register read/write primitives */
71 #define REG_WRITE(_ah, _reg, _val) \
72 (_ah)->reg_ops.write((_ah), (_val), (_reg))
73
74 #define REG_READ(_ah, _reg) \
75 (_ah)->reg_ops.read((_ah), (_reg))
76
77 #define REG_READ_MULTI(_ah, _addr, _val, _cnt) \
78 (_ah)->reg_ops.multi_read((_ah), (_addr), (_val), (_cnt))
79
80 #define REG_RMW(_ah, _reg, _set, _clr) \
81 (_ah)->reg_ops.rmw((_ah), (_reg), (_set), (_clr))
82
83 #define ENABLE_REGWRITE_BUFFER(_ah) \
84 do { \
85 if ((_ah)->reg_ops.enable_write_buffer) \
86 (_ah)->reg_ops.enable_write_buffer((_ah)); \
87 } while (0)
88
89 #define REGWRITE_BUFFER_FLUSH(_ah) \
90 do { \
91 if ((_ah)->reg_ops.write_flush) \
92 (_ah)->reg_ops.write_flush((_ah)); \
93 } while (0)
94
95 #define PR_EEP(_s, _val) \
96 do { \
97 len += snprintf(buf + len, size - len, "%20s : %10d\n", \
98 _s, (_val)); \
99 } while (0)
100
101 #define SM(_v, _f) (((_v) << _f##_S) & _f)
102 #define MS(_v, _f) (((_v) & _f) >> _f##_S)
103 #define REG_RMW_FIELD(_a, _r, _f, _v) \
104 REG_RMW(_a, _r, (((_v) << _f##_S) & _f), (_f))
105 #define REG_READ_FIELD(_a, _r, _f) \
106 (((REG_READ(_a, _r) & _f) >> _f##_S))
107 #define REG_SET_BIT(_a, _r, _f) \
108 REG_RMW(_a, _r, (_f), 0)
109 #define REG_CLR_BIT(_a, _r, _f) \
110 REG_RMW(_a, _r, 0, (_f))
111
112 #define DO_DELAY(x) do { \
113 if (((++(x) % 64) == 0) && \
114 (ath9k_hw_common(ah)->bus_ops->ath_bus_type \
115 != ATH_USB)) \
116 udelay(1); \
117 } while (0)
118
119 #define REG_WRITE_ARRAY(iniarray, column, regWr) \
120 ath9k_hw_write_array(ah, iniarray, column, &(regWr))
121
122 #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
123 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
124 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
125 #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3
126 #define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4
127 #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
128 #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
129 #define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_DATA 0x16
130 #define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_CLK 0x17
131 #define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA 0x18
132 #define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK 0x19
133 #define AR_GPIO_OUTPUT_MUX_AS_WL_IN_TX 0x14
134 #define AR_GPIO_OUTPUT_MUX_AS_WL_IN_RX 0x13
135 #define AR_GPIO_OUTPUT_MUX_AS_BT_IN_TX 9
136 #define AR_GPIO_OUTPUT_MUX_AS_BT_IN_RX 8
137 #define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_STROBE 0x1d
138 #define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_DATA 0x1e
139
140 #define AR_GPIOD_MASK 0x00001FFF
141 #define AR_GPIO_BIT(_gpio) (1 << (_gpio))
142
143 #define BASE_ACTIVATE_DELAY 100
144 #define RTC_PLL_SETTLE_DELAY (AR_SREV_9340(ah) ? 1000 : 100)
145 #define COEF_SCALE_S 24
146 #define HT40_CHANNEL_CENTER_SHIFT 10
147
148 #define ATH9K_ANTENNA0_CHAINMASK 0x1
149 #define ATH9K_ANTENNA1_CHAINMASK 0x2
150
151 #define ATH9K_NUM_DMA_DEBUG_REGS 8
152 #define ATH9K_NUM_QUEUES 10
153
154 #define MAX_RATE_POWER 63
155 #define AH_WAIT_TIMEOUT 100000 /* (us) */
156 #define AH_TSF_WRITE_TIMEOUT 100 /* (us) */
157 #define AH_TIME_QUANTUM 10
158 #define AR_KEYTABLE_SIZE 128
159 #define POWER_UP_TIME 10000
160 #define SPUR_RSSI_THRESH 40
161 #define UPPER_5G_SUB_BAND_START 5700
162 #define MID_5G_SUB_BAND_START 5400
163
164 #define CAB_TIMEOUT_VAL 10
165 #define BEACON_TIMEOUT_VAL 10
166 #define MIN_BEACON_TIMEOUT_VAL 1
167 #define SLEEP_SLOP 3
168
169 #define INIT_CONFIG_STATUS 0x00000000
170 #define INIT_RSSI_THR 0x00000700
171 #define INIT_BCON_CNTRL_REG 0x00000000
172
173 #define TU_TO_USEC(_tu) ((_tu) << 10)
174
175 #define ATH9K_HW_RX_HP_QDEPTH 16
176 #define ATH9K_HW_RX_LP_QDEPTH 128
177
178 #define PAPRD_GAIN_TABLE_ENTRIES 32
179 #define PAPRD_TABLE_SZ 24
180 #define PAPRD_IDEAL_AGC2_PWR_RANGE 0xe0
181
182 enum ath_hw_txq_subtype {
183 ATH_TXQ_AC_BE = 0,
184 ATH_TXQ_AC_BK = 1,
185 ATH_TXQ_AC_VI = 2,
186 ATH_TXQ_AC_VO = 3,
187 };
188
189 enum ath_ini_subsys {
190 ATH_INI_PRE = 0,
191 ATH_INI_CORE,
192 ATH_INI_POST,
193 ATH_INI_NUM_SPLIT,
194 };
195
196 enum ath9k_hw_caps {
197 ATH9K_HW_CAP_HT = BIT(0),
198 ATH9K_HW_CAP_RFSILENT = BIT(1),
199 ATH9K_HW_CAP_CST = BIT(2),
200 ATH9K_HW_CAP_AUTOSLEEP = BIT(4),
201 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(5),
202 ATH9K_HW_CAP_EDMA = BIT(6),
203 ATH9K_HW_CAP_RAC_SUPPORTED = BIT(7),
204 ATH9K_HW_CAP_LDPC = BIT(8),
205 ATH9K_HW_CAP_FASTCLOCK = BIT(9),
206 ATH9K_HW_CAP_SGI_20 = BIT(10),
207 ATH9K_HW_CAP_PAPRD = BIT(11),
208 ATH9K_HW_CAP_ANT_DIV_COMB = BIT(12),
209 ATH9K_HW_CAP_2GHZ = BIT(13),
210 ATH9K_HW_CAP_5GHZ = BIT(14),
211 ATH9K_HW_CAP_APM = BIT(15),
212 ATH9K_HW_CAP_RTT = BIT(16),
213 ATH9K_HW_CAP_MCI = BIT(17),
214 ATH9K_HW_CAP_DFS = BIT(18),
215 };
216
217 struct ath9k_hw_capabilities {
218 u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
219 u16 rts_aggr_limit;
220 u8 tx_chainmask;
221 u8 rx_chainmask;
222 u8 max_txchains;
223 u8 max_rxchains;
224 u8 num_gpio_pins;
225 u8 rx_hp_qdepth;
226 u8 rx_lp_qdepth;
227 u8 rx_status_len;
228 u8 tx_desc_len;
229 u8 txs_len;
230 u16 pcie_lcr_offset;
231 bool pcie_lcr_extsync_en;
232 };
233
234 struct ath9k_ops_config {
235 int dma_beacon_response_time;
236 int sw_beacon_response_time;
237 int additional_swba_backoff;
238 int ack_6mb;
239 u32 cwm_ignore_extcca;
240 bool pcieSerDesWrite;
241 u8 pcie_clock_req;
242 u32 pcie_waen;
243 u8 analog_shiftreg;
244 u8 paprd_disable;
245 u32 ofdm_trig_low;
246 u32 ofdm_trig_high;
247 u32 cck_trig_high;
248 u32 cck_trig_low;
249 u32 enable_ani;
250 int serialize_regmode;
251 bool rx_intr_mitigation;
252 bool tx_intr_mitigation;
253 #define SPUR_DISABLE 0
254 #define SPUR_ENABLE_IOCTL 1
255 #define SPUR_ENABLE_EEPROM 2
256 #define AR_SPUR_5413_1 1640
257 #define AR_SPUR_5413_2 1200
258 #define AR_NO_SPUR 0x8000
259 #define AR_BASE_FREQ_2GHZ 2300
260 #define AR_BASE_FREQ_5GHZ 4900
261 #define AR_SPUR_FEEQ_BOUND_HT40 19
262 #define AR_SPUR_FEEQ_BOUND_HT20 10
263 int spurmode;
264 u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
265 u8 max_txtrig_level;
266 u16 ani_poll_interval; /* ANI poll interval in ms */
267 };
268
269 enum ath9k_int {
270 ATH9K_INT_RX = 0x00000001,
271 ATH9K_INT_RXDESC = 0x00000002,
272 ATH9K_INT_RXHP = 0x00000001,
273 ATH9K_INT_RXLP = 0x00000002,
274 ATH9K_INT_RXNOFRM = 0x00000008,
275 ATH9K_INT_RXEOL = 0x00000010,
276 ATH9K_INT_RXORN = 0x00000020,
277 ATH9K_INT_TX = 0x00000040,
278 ATH9K_INT_TXDESC = 0x00000080,
279 ATH9K_INT_TIM_TIMER = 0x00000100,
280 ATH9K_INT_MCI = 0x00000200,
281 ATH9K_INT_BB_WATCHDOG = 0x00000400,
282 ATH9K_INT_TXURN = 0x00000800,
283 ATH9K_INT_MIB = 0x00001000,
284 ATH9K_INT_RXPHY = 0x00004000,
285 ATH9K_INT_RXKCM = 0x00008000,
286 ATH9K_INT_SWBA = 0x00010000,
287 ATH9K_INT_BMISS = 0x00040000,
288 ATH9K_INT_BNR = 0x00100000,
289 ATH9K_INT_TIM = 0x00200000,
290 ATH9K_INT_DTIM = 0x00400000,
291 ATH9K_INT_DTIMSYNC = 0x00800000,
292 ATH9K_INT_GPIO = 0x01000000,
293 ATH9K_INT_CABEND = 0x02000000,
294 ATH9K_INT_TSFOOR = 0x04000000,
295 ATH9K_INT_GENTIMER = 0x08000000,
296 ATH9K_INT_CST = 0x10000000,
297 ATH9K_INT_GTT = 0x20000000,
298 ATH9K_INT_FATAL = 0x40000000,
299 ATH9K_INT_GLOBAL = 0x80000000,
300 ATH9K_INT_BMISC = ATH9K_INT_TIM |
301 ATH9K_INT_DTIM |
302 ATH9K_INT_DTIMSYNC |
303 ATH9K_INT_TSFOOR |
304 ATH9K_INT_CABEND,
305 ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
306 ATH9K_INT_RXDESC |
307 ATH9K_INT_RXEOL |
308 ATH9K_INT_RXORN |
309 ATH9K_INT_TXURN |
310 ATH9K_INT_TXDESC |
311 ATH9K_INT_MIB |
312 ATH9K_INT_RXPHY |
313 ATH9K_INT_RXKCM |
314 ATH9K_INT_SWBA |
315 ATH9K_INT_BMISS |
316 ATH9K_INT_GPIO,
317 ATH9K_INT_NOCARD = 0xffffffff
318 };
319
320 #define CHANNEL_CW_INT 0x00002
321 #define CHANNEL_CCK 0x00020
322 #define CHANNEL_OFDM 0x00040
323 #define CHANNEL_2GHZ 0x00080
324 #define CHANNEL_5GHZ 0x00100
325 #define CHANNEL_PASSIVE 0x00200
326 #define CHANNEL_DYN 0x00400
327 #define CHANNEL_HALF 0x04000
328 #define CHANNEL_QUARTER 0x08000
329 #define CHANNEL_HT20 0x10000
330 #define CHANNEL_HT40PLUS 0x20000
331 #define CHANNEL_HT40MINUS 0x40000
332
333 #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
334 #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
335 #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
336 #define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20)
337 #define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20)
338 #define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
339 #define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
340 #define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
341 #define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
342 #define CHANNEL_ALL \
343 (CHANNEL_OFDM| \
344 CHANNEL_CCK| \
345 CHANNEL_2GHZ | \
346 CHANNEL_5GHZ | \
347 CHANNEL_HT20 | \
348 CHANNEL_HT40PLUS | \
349 CHANNEL_HT40MINUS)
350
351 #define MAX_RTT_TABLE_ENTRY 6
352 #define RTT_HIST_MAX 3
353 struct ath9k_rtt_hist {
354 u32 table[AR9300_MAX_CHAINS][RTT_HIST_MAX][MAX_RTT_TABLE_ENTRY];
355 u8 num_readings;
356 };
357
358 #define MAX_IQCAL_MEASUREMENT 8
359 #define MAX_CL_TAB_ENTRY 16
360
361 struct ath9k_hw_cal_data {
362 u16 channel;
363 u32 channelFlags;
364 int32_t CalValid;
365 int8_t iCoff;
366 int8_t qCoff;
367 bool paprd_done;
368 bool nfcal_pending;
369 bool nfcal_interference;
370 bool done_txiqcal_once;
371 bool done_txclcal_once;
372 u16 small_signal_gain[AR9300_MAX_CHAINS];
373 u32 pa_table[AR9300_MAX_CHAINS][PAPRD_TABLE_SZ];
374 u32 num_measures[AR9300_MAX_CHAINS];
375 int tx_corr_coeff[MAX_IQCAL_MEASUREMENT][AR9300_MAX_CHAINS];
376 u32 tx_clcal[AR9300_MAX_CHAINS][MAX_CL_TAB_ENTRY];
377 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
378 struct ath9k_rtt_hist rtt_hist;
379 };
380
381 struct ath9k_channel {
382 struct ieee80211_channel *chan;
383 struct ar5416AniState ani;
384 u16 channel;
385 u32 channelFlags;
386 u32 chanmode;
387 s16 noisefloor;
388 };
389
390 #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
391 (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
392 (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
393 (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
394 #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
395 #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
396 #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
397 #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
398 #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
399 #define IS_CHAN_A_FAST_CLOCK(_ah, _c) \
400 ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \
401 ((_ah)->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK))
402
403 /* These macros check chanmode and not channelFlags */
404 #define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B)
405 #define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \
406 ((_c)->chanmode == CHANNEL_G_HT20))
407 #define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \
408 ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \
409 ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \
410 ((_c)->chanmode == CHANNEL_G_HT40MINUS))
411 #define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
412
413 enum ath9k_power_mode {
414 ATH9K_PM_AWAKE = 0,
415 ATH9K_PM_FULL_SLEEP,
416 ATH9K_PM_NETWORK_SLEEP,
417 ATH9K_PM_UNDEFINED
418 };
419
420 enum ser_reg_mode {
421 SER_REG_MODE_OFF = 0,
422 SER_REG_MODE_ON = 1,
423 SER_REG_MODE_AUTO = 2,
424 };
425
426 enum ath9k_rx_qtype {
427 ATH9K_RX_QUEUE_HP,
428 ATH9K_RX_QUEUE_LP,
429 ATH9K_RX_QUEUE_MAX,
430 };
431
432 enum mci_message_header { /* length of payload */
433 MCI_LNA_CTRL = 0x10, /* len = 0 */
434 MCI_CONT_NACK = 0x20, /* len = 0 */
435 MCI_CONT_INFO = 0x30, /* len = 4 */
436 MCI_CONT_RST = 0x40, /* len = 0 */
437 MCI_SCHD_INFO = 0x50, /* len = 16 */
438 MCI_CPU_INT = 0x60, /* len = 4 */
439 MCI_SYS_WAKING = 0x70, /* len = 0 */
440 MCI_GPM = 0x80, /* len = 16 */
441 MCI_LNA_INFO = 0x90, /* len = 1 */
442 MCI_LNA_STATE = 0x94,
443 MCI_LNA_TAKE = 0x98,
444 MCI_LNA_TRANS = 0x9c,
445 MCI_SYS_SLEEPING = 0xa0, /* len = 0 */
446 MCI_REQ_WAKE = 0xc0, /* len = 0 */
447 MCI_DEBUG_16 = 0xfe, /* len = 2 */
448 MCI_REMOTE_RESET = 0xff /* len = 16 */
449 };
450
451 enum ath_mci_gpm_coex_profile_type {
452 MCI_GPM_COEX_PROFILE_UNKNOWN,
453 MCI_GPM_COEX_PROFILE_RFCOMM,
454 MCI_GPM_COEX_PROFILE_A2DP,
455 MCI_GPM_COEX_PROFILE_HID,
456 MCI_GPM_COEX_PROFILE_BNEP,
457 MCI_GPM_COEX_PROFILE_VOICE,
458 MCI_GPM_COEX_PROFILE_MAX
459 };
460
461 /* MCI GPM/Coex opcode/type definitions */
462 enum {
463 MCI_GPM_COEX_W_GPM_PAYLOAD = 1,
464 MCI_GPM_COEX_B_GPM_TYPE = 4,
465 MCI_GPM_COEX_B_GPM_OPCODE = 5,
466 /* MCI_GPM_WLAN_CAL_REQ, MCI_GPM_WLAN_CAL_DONE */
467 MCI_GPM_WLAN_CAL_W_SEQUENCE = 2,
468
469 /* MCI_GPM_COEX_VERSION_QUERY */
470 /* MCI_GPM_COEX_VERSION_RESPONSE */
471 MCI_GPM_COEX_B_MAJOR_VERSION = 6,
472 MCI_GPM_COEX_B_MINOR_VERSION = 7,
473 /* MCI_GPM_COEX_STATUS_QUERY */
474 MCI_GPM_COEX_B_BT_BITMAP = 6,
475 MCI_GPM_COEX_B_WLAN_BITMAP = 7,
476 /* MCI_GPM_COEX_HALT_BT_GPM */
477 MCI_GPM_COEX_B_HALT_STATE = 6,
478 /* MCI_GPM_COEX_WLAN_CHANNELS */
479 MCI_GPM_COEX_B_CHANNEL_MAP = 6,
480 /* MCI_GPM_COEX_BT_PROFILE_INFO */
481 MCI_GPM_COEX_B_PROFILE_TYPE = 6,
482 MCI_GPM_COEX_B_PROFILE_LINKID = 7,
483 MCI_GPM_COEX_B_PROFILE_STATE = 8,
484 MCI_GPM_COEX_B_PROFILE_ROLE = 9,
485 MCI_GPM_COEX_B_PROFILE_RATE = 10,
486 MCI_GPM_COEX_B_PROFILE_VOTYPE = 11,
487 MCI_GPM_COEX_H_PROFILE_T = 12,
488 MCI_GPM_COEX_B_PROFILE_W = 14,
489 MCI_GPM_COEX_B_PROFILE_A = 15,
490 /* MCI_GPM_COEX_BT_STATUS_UPDATE */
491 MCI_GPM_COEX_B_STATUS_TYPE = 6,
492 MCI_GPM_COEX_B_STATUS_LINKID = 7,
493 MCI_GPM_COEX_B_STATUS_STATE = 8,
494 /* MCI_GPM_COEX_BT_UPDATE_FLAGS */
495 MCI_GPM_COEX_W_BT_FLAGS = 6,
496 MCI_GPM_COEX_B_BT_FLAGS_OP = 10
497 };
498
499 enum mci_gpm_subtype {
500 MCI_GPM_BT_CAL_REQ = 0,
501 MCI_GPM_BT_CAL_GRANT = 1,
502 MCI_GPM_BT_CAL_DONE = 2,
503 MCI_GPM_WLAN_CAL_REQ = 3,
504 MCI_GPM_WLAN_CAL_GRANT = 4,
505 MCI_GPM_WLAN_CAL_DONE = 5,
506 MCI_GPM_COEX_AGENT = 0x0c,
507 MCI_GPM_RSVD_PATTERN = 0xfe,
508 MCI_GPM_RSVD_PATTERN32 = 0xfefefefe,
509 MCI_GPM_BT_DEBUG = 0xff
510 };
511
512 enum mci_bt_state {
513 MCI_BT_SLEEP,
514 MCI_BT_AWAKE,
515 MCI_BT_CAL_START,
516 MCI_BT_CAL
517 };
518
519 /* Type of state query */
520 enum mci_state_type {
521 MCI_STATE_ENABLE,
522 MCI_STATE_INIT_GPM_OFFSET,
523 MCI_STATE_NEXT_GPM_OFFSET,
524 MCI_STATE_LAST_GPM_OFFSET,
525 MCI_STATE_BT,
526 MCI_STATE_SET_BT_SLEEP,
527 MCI_STATE_SET_BT_AWAKE,
528 MCI_STATE_SET_BT_CAL_START,
529 MCI_STATE_SET_BT_CAL,
530 MCI_STATE_LAST_SCHD_MSG_OFFSET,
531 MCI_STATE_REMOTE_SLEEP,
532 MCI_STATE_CONT_RSSI_POWER,
533 MCI_STATE_CONT_PRIORITY,
534 MCI_STATE_CONT_TXRX,
535 MCI_STATE_RESET_REQ_WAKE,
536 MCI_STATE_SEND_WLAN_COEX_VERSION,
537 MCI_STATE_SET_BT_COEX_VERSION,
538 MCI_STATE_SEND_WLAN_CHANNELS,
539 MCI_STATE_SEND_VERSION_QUERY,
540 MCI_STATE_SEND_STATUS_QUERY,
541 MCI_STATE_NEED_FLUSH_BT_INFO,
542 MCI_STATE_SET_CONCUR_TX_PRI,
543 MCI_STATE_RECOVER_RX,
544 MCI_STATE_NEED_FTP_STOMP,
545 MCI_STATE_NEED_TUNING,
546 MCI_STATE_DEBUG,
547 MCI_STATE_MAX
548 };
549
550 enum mci_gpm_coex_opcode {
551 MCI_GPM_COEX_VERSION_QUERY,
552 MCI_GPM_COEX_VERSION_RESPONSE,
553 MCI_GPM_COEX_STATUS_QUERY,
554 MCI_GPM_COEX_HALT_BT_GPM,
555 MCI_GPM_COEX_WLAN_CHANNELS,
556 MCI_GPM_COEX_BT_PROFILE_INFO,
557 MCI_GPM_COEX_BT_STATUS_UPDATE,
558 MCI_GPM_COEX_BT_UPDATE_FLAGS
559 };
560
561 #define MCI_GPM_NOMORE 0
562 #define MCI_GPM_MORE 1
563 #define MCI_GPM_INVALID 0xffffffff
564
565 #define MCI_GPM_RECYCLE(_p_gpm) do { \
566 *(((u32 *)_p_gpm) + MCI_GPM_COEX_W_GPM_PAYLOAD) = \
567 MCI_GPM_RSVD_PATTERN32; \
568 } while (0)
569
570 #define MCI_GPM_TYPE(_p_gpm) \
571 (*(((u8 *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_TYPE) & 0xff)
572
573 #define MCI_GPM_OPCODE(_p_gpm) \
574 (*(((u8 *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_OPCODE) & 0xff)
575
576 #define MCI_GPM_SET_CAL_TYPE(_p_gpm, _cal_type) do { \
577 *(((u8 *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_TYPE) = (_cal_type) & 0xff;\
578 } while (0)
579
580 #define MCI_GPM_SET_TYPE_OPCODE(_p_gpm, _type, _opcode) do { \
581 *(((u8 *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_TYPE) = (_type) & 0xff; \
582 *(((u8 *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_OPCODE) = (_opcode) & 0xff;\
583 } while (0)
584
585 #define MCI_GPM_IS_CAL_TYPE(_type) ((_type) <= MCI_GPM_WLAN_CAL_DONE)
586
587 struct ath9k_beacon_state {
588 u32 bs_nexttbtt;
589 u32 bs_nextdtim;
590 u32 bs_intval;
591 #define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */
592 u32 bs_dtimperiod;
593 u16 bs_cfpperiod;
594 u16 bs_cfpmaxduration;
595 u32 bs_cfpnext;
596 u16 bs_timoffset;
597 u16 bs_bmissthreshold;
598 u32 bs_sleepduration;
599 u32 bs_tsfoor_threshold;
600 };
601
602 struct chan_centers {
603 u16 synth_center;
604 u16 ctl_center;
605 u16 ext_center;
606 };
607
608 enum {
609 ATH9K_RESET_POWER_ON,
610 ATH9K_RESET_WARM,
611 ATH9K_RESET_COLD,
612 };
613
614 struct ath9k_hw_version {
615 u32 magic;
616 u16 devid;
617 u16 subvendorid;
618 u32 macVersion;
619 u16 macRev;
620 u16 phyRev;
621 u16 analog5GhzRev;
622 u16 analog2GhzRev;
623 enum ath_usb_dev usbdev;
624 };
625
626 /* Generic TSF timer definitions */
627
628 #define ATH_MAX_GEN_TIMER 16
629
630 #define AR_GENTMR_BIT(_index) (1 << (_index))
631
632 /*
633 * Using de Bruijin sequence to look up 1's index in a 32 bit number
634 * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001
635 */
636 #define debruijn32 0x077CB531U
637
638 struct ath_gen_timer_configuration {
639 u32 next_addr;
640 u32 period_addr;
641 u32 mode_addr;
642 u32 mode_mask;
643 };
644
645 struct ath_gen_timer {
646 void (*trigger)(void *arg);
647 void (*overflow)(void *arg);
648 void *arg;
649 u8 index;
650 };
651
652 struct ath_gen_timer_table {
653 u32 gen_timer_index[32];
654 struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER];
655 union {
656 unsigned long timer_bits;
657 u16 val;
658 } timer_mask;
659 };
660
661 struct ath_hw_antcomb_conf {
662 u8 main_lna_conf;
663 u8 alt_lna_conf;
664 u8 fast_div_bias;
665 u8 main_gaintb;
666 u8 alt_gaintb;
667 int lna1_lna2_delta;
668 u8 div_group;
669 };
670
671 /**
672 * struct ath_hw_radar_conf - radar detection initialization parameters
673 *
674 * @pulse_inband: threshold for checking the ratio of in-band power
675 * to total power for short radar pulses (half dB steps)
676 * @pulse_inband_step: threshold for checking an in-band power to total
677 * power ratio increase for short radar pulses (half dB steps)
678 * @pulse_height: threshold for detecting the beginning of a short
679 * radar pulse (dB step)
680 * @pulse_rssi: threshold for detecting if a short radar pulse is
681 * gone (dB step)
682 * @pulse_maxlen: maximum pulse length (0.8 us steps)
683 *
684 * @radar_rssi: RSSI threshold for starting long radar detection (dB steps)
685 * @radar_inband: threshold for checking the ratio of in-band power
686 * to total power for long radar pulses (half dB steps)
687 * @fir_power: threshold for detecting the end of a long radar pulse (dB)
688 *
689 * @ext_channel: enable extension channel radar detection
690 */
691 struct ath_hw_radar_conf {
692 unsigned int pulse_inband;
693 unsigned int pulse_inband_step;
694 unsigned int pulse_height;
695 unsigned int pulse_rssi;
696 unsigned int pulse_maxlen;
697
698 unsigned int radar_rssi;
699 unsigned int radar_inband;
700 int fir_power;
701
702 bool ext_channel;
703 };
704
705 /**
706 * struct ath_hw_private_ops - callbacks used internally by hardware code
707 *
708 * This structure contains private callbacks designed to only be used internally
709 * by the hardware core.
710 *
711 * @init_cal_settings: setup types of calibrations supported
712 * @init_cal: starts actual calibration
713 *
714 * @init_mode_regs: Initializes mode registers
715 * @init_mode_gain_regs: Initialize TX/RX gain registers
716 *
717 * @rf_set_freq: change frequency
718 * @spur_mitigate_freq: spur mitigation
719 * @rf_alloc_ext_banks:
720 * @rf_free_ext_banks:
721 * @set_rf_regs:
722 * @compute_pll_control: compute the PLL control value to use for
723 * AR_RTC_PLL_CONTROL for a given channel
724 * @setup_calibration: set up calibration
725 * @iscal_supported: used to query if a type of calibration is supported
726 *
727 * @ani_cache_ini_regs: cache the values for ANI from the initial
728 * register settings through the register initialization.
729 */
730 struct ath_hw_private_ops {
731 /* Calibration ops */
732 void (*init_cal_settings)(struct ath_hw *ah);
733 bool (*init_cal)(struct ath_hw *ah, struct ath9k_channel *chan);
734
735 void (*init_mode_regs)(struct ath_hw *ah);
736 void (*init_mode_gain_regs)(struct ath_hw *ah);
737 void (*setup_calibration)(struct ath_hw *ah,
738 struct ath9k_cal_list *currCal);
739
740 /* PHY ops */
741 int (*rf_set_freq)(struct ath_hw *ah,
742 struct ath9k_channel *chan);
743 void (*spur_mitigate_freq)(struct ath_hw *ah,
744 struct ath9k_channel *chan);
745 int (*rf_alloc_ext_banks)(struct ath_hw *ah);
746 void (*rf_free_ext_banks)(struct ath_hw *ah);
747 bool (*set_rf_regs)(struct ath_hw *ah,
748 struct ath9k_channel *chan,
749 u16 modesIndex);
750 void (*set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan);
751 void (*init_bb)(struct ath_hw *ah,
752 struct ath9k_channel *chan);
753 int (*process_ini)(struct ath_hw *ah, struct ath9k_channel *chan);
754 void (*olc_init)(struct ath_hw *ah);
755 void (*set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan);
756 void (*mark_phy_inactive)(struct ath_hw *ah);
757 void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan);
758 bool (*rfbus_req)(struct ath_hw *ah);
759 void (*rfbus_done)(struct ath_hw *ah);
760 void (*restore_chainmask)(struct ath_hw *ah);
761 u32 (*compute_pll_control)(struct ath_hw *ah,
762 struct ath9k_channel *chan);
763 bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd,
764 int param);
765 void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]);
766 void (*set_radar_params)(struct ath_hw *ah,
767 struct ath_hw_radar_conf *conf);
768 int (*fast_chan_change)(struct ath_hw *ah, struct ath9k_channel *chan,
769 u8 *ini_reloaded);
770
771 /* ANI */
772 void (*ani_cache_ini_regs)(struct ath_hw *ah);
773 };
774
775 /**
776 * struct ath_hw_ops - callbacks used by hardware code and driver code
777 *
778 * This structure contains callbacks designed to to be used internally by
779 * hardware code and also by the lower level driver.
780 *
781 * @config_pci_powersave:
782 * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC
783 */
784 struct ath_hw_ops {
785 void (*config_pci_powersave)(struct ath_hw *ah,
786 bool power_off);
787 void (*rx_enable)(struct ath_hw *ah);
788 void (*set_desc_link)(void *ds, u32 link);
789 bool (*calibrate)(struct ath_hw *ah,
790 struct ath9k_channel *chan,
791 u8 rxchainmask,
792 bool longcal);
793 bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked);
794 void (*set_txdesc)(struct ath_hw *ah, void *ds,
795 struct ath_tx_info *i);
796 int (*proc_txdesc)(struct ath_hw *ah, void *ds,
797 struct ath_tx_status *ts);
798 void (*antdiv_comb_conf_get)(struct ath_hw *ah,
799 struct ath_hw_antcomb_conf *antconf);
800 void (*antdiv_comb_conf_set)(struct ath_hw *ah,
801 struct ath_hw_antcomb_conf *antconf);
802
803 };
804
805 struct ath_nf_limits {
806 s16 max;
807 s16 min;
808 s16 nominal;
809 };
810
811 enum ath_cal_list {
812 TX_IQ_CAL = BIT(0),
813 TX_IQ_ON_AGC_CAL = BIT(1),
814 TX_CL_CAL = BIT(2),
815 };
816
817 /* ah_flags */
818 #define AH_USE_EEPROM 0x1
819 #define AH_UNPLUGGED 0x2 /* The card has been physically removed. */
820 #define AH_FASTCC 0x4
821
822 struct ath_hw {
823 struct ath_ops reg_ops;
824
825 struct ieee80211_hw *hw;
826 struct ath_common common;
827 struct ath9k_hw_version hw_version;
828 struct ath9k_ops_config config;
829 struct ath9k_hw_capabilities caps;
830 struct ath9k_channel channels[ATH9K_NUM_CHANNELS];
831 struct ath9k_channel *curchan;
832
833 union {
834 struct ar5416_eeprom_def def;
835 struct ar5416_eeprom_4k map4k;
836 struct ar9287_eeprom map9287;
837 struct ar9300_eeprom ar9300_eep;
838 } eeprom;
839 const struct eeprom_ops *eep_ops;
840
841 bool sw_mgmt_crypto;
842 bool is_pciexpress;
843 bool aspm_enabled;
844 bool is_monitoring;
845 bool need_an_top2_fixup;
846 u16 tx_trig_level;
847
848 u32 nf_regs[6];
849 struct ath_nf_limits nf_2g;
850 struct ath_nf_limits nf_5g;
851 u16 rfsilent;
852 u32 rfkill_gpio;
853 u32 rfkill_polarity;
854 u32 ah_flags;
855
856 bool htc_reset_init;
857
858 enum nl80211_iftype opmode;
859 enum ath9k_power_mode power_mode;
860
861 s8 noise;
862 struct ath9k_hw_cal_data *caldata;
863 struct ath9k_pacal_info pacal_info;
864 struct ar5416Stats stats;
865 struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES];
866
867 int16_t curchan_rad_index;
868 enum ath9k_int imask;
869 u32 imrs2_reg;
870 u32 txok_interrupt_mask;
871 u32 txerr_interrupt_mask;
872 u32 txdesc_interrupt_mask;
873 u32 txeol_interrupt_mask;
874 u32 txurn_interrupt_mask;
875 atomic_t intr_ref_cnt;
876 bool chip_fullsleep;
877 u32 atim_window;
878 u32 modes_index;
879
880 /* Calibration */
881 u32 supp_cals;
882 struct ath9k_cal_list iq_caldata;
883 struct ath9k_cal_list adcgain_caldata;
884 struct ath9k_cal_list adcdc_caldata;
885 struct ath9k_cal_list tempCompCalData;
886 struct ath9k_cal_list *cal_list;
887 struct ath9k_cal_list *cal_list_last;
888 struct ath9k_cal_list *cal_list_curr;
889 #define totalPowerMeasI meas0.unsign
890 #define totalPowerMeasQ meas1.unsign
891 #define totalIqCorrMeas meas2.sign
892 #define totalAdcIOddPhase meas0.unsign
893 #define totalAdcIEvenPhase meas1.unsign
894 #define totalAdcQOddPhase meas2.unsign
895 #define totalAdcQEvenPhase meas3.unsign
896 #define totalAdcDcOffsetIOddPhase meas0.sign
897 #define totalAdcDcOffsetIEvenPhase meas1.sign
898 #define totalAdcDcOffsetQOddPhase meas2.sign
899 #define totalAdcDcOffsetQEvenPhase meas3.sign
900 union {
901 u32 unsign[AR5416_MAX_CHAINS];
902 int32_t sign[AR5416_MAX_CHAINS];
903 } meas0;
904 union {
905 u32 unsign[AR5416_MAX_CHAINS];
906 int32_t sign[AR5416_MAX_CHAINS];
907 } meas1;
908 union {
909 u32 unsign[AR5416_MAX_CHAINS];
910 int32_t sign[AR5416_MAX_CHAINS];
911 } meas2;
912 union {
913 u32 unsign[AR5416_MAX_CHAINS];
914 int32_t sign[AR5416_MAX_CHAINS];
915 } meas3;
916 u16 cal_samples;
917 u8 enabled_cals;
918
919 u32 sta_id1_defaults;
920 u32 misc_mode;
921 enum {
922 AUTO_32KHZ,
923 USE_32KHZ,
924 DONT_USE_32KHZ,
925 } enable_32kHz_clock;
926
927 /* Private to hardware code */
928 struct ath_hw_private_ops private_ops;
929 /* Accessed by the lower level driver */
930 struct ath_hw_ops ops;
931
932 /* Used to program the radio on non single-chip devices */
933 u32 *analogBank0Data;
934 u32 *analogBank1Data;
935 u32 *analogBank2Data;
936 u32 *analogBank3Data;
937 u32 *analogBank6Data;
938 u32 *analogBank6TPCData;
939 u32 *analogBank7Data;
940 u32 *addac5416_21;
941 u32 *bank6Temp;
942
943 u8 txpower_limit;
944 int coverage_class;
945 u32 slottime;
946 u32 globaltxtimeout;
947
948 /* ANI */
949 u32 proc_phyerr;
950 u32 aniperiod;
951 int totalSizeDesired[5];
952 int coarse_high[5];
953 int coarse_low[5];
954 int firpwr[5];
955 enum ath9k_ani_cmd ani_function;
956
957 /* Bluetooth coexistance */
958 struct ath_btcoex_hw btcoex_hw;
959
960 u32 intr_txqs;
961 u8 txchainmask;
962 u8 rxchainmask;
963
964 struct ath_hw_radar_conf radar_conf;
965
966 u32 originalGain[22];
967 int initPDADC;
968 int PDADCdelta;
969 int led_pin;
970 u32 gpio_mask;
971 u32 gpio_val;
972
973 struct ar5416IniArray iniModes;
974 struct ar5416IniArray iniCommon;
975 struct ar5416IniArray iniBank0;
976 struct ar5416IniArray iniBB_RfGain;
977 struct ar5416IniArray iniBank1;
978 struct ar5416IniArray iniBank2;
979 struct ar5416IniArray iniBank3;
980 struct ar5416IniArray iniBank6;
981 struct ar5416IniArray iniBank6TPC;
982 struct ar5416IniArray iniBank7;
983 struct ar5416IniArray iniAddac;
984 struct ar5416IniArray iniPcieSerdes;
985 struct ar5416IniArray iniPcieSerdesLowPower;
986 struct ar5416IniArray iniModesAdditional;
987 struct ar5416IniArray iniModesAdditional_40M;
988 struct ar5416IniArray iniModesRxGain;
989 struct ar5416IniArray iniModesTxGain;
990 struct ar5416IniArray iniModes_9271_1_0_only;
991 struct ar5416IniArray iniCckfirNormal;
992 struct ar5416IniArray iniCckfirJapan2484;
993 struct ar5416IniArray ini_japan2484;
994 struct ar5416IniArray iniCommon_normal_cck_fir_coeff_9271;
995 struct ar5416IniArray iniCommon_japan_2484_cck_fir_coeff_9271;
996 struct ar5416IniArray iniModes_9271_ANI_reg;
997 struct ar5416IniArray iniModes_high_power_tx_gain_9271;
998 struct ar5416IniArray iniModes_normal_power_tx_gain_9271;
999 struct ar5416IniArray ini_radio_post_sys2ant;
1000 struct ar5416IniArray ini_BTCOEX_MAX_TXPWR;
1001
1002 struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT];
1003 struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT];
1004 struct ar5416IniArray iniRadio[ATH_INI_NUM_SPLIT];
1005 struct ar5416IniArray iniSOC[ATH_INI_NUM_SPLIT];
1006
1007 u32 intr_gen_timer_trigger;
1008 u32 intr_gen_timer_thresh;
1009 struct ath_gen_timer_table hw_gen_timers;
1010
1011 struct ar9003_txs *ts_ring;
1012 void *ts_start;
1013 u32 ts_paddr_start;
1014 u32 ts_paddr_end;
1015 u16 ts_tail;
1016 u8 ts_size;
1017
1018 u32 bb_watchdog_last_status;
1019 u32 bb_watchdog_timeout_ms; /* in ms, 0 to disable */
1020 u8 bb_hang_rx_ofdm; /* true if bb hang due to rx_ofdm */
1021
1022 unsigned int paprd_target_power;
1023 unsigned int paprd_training_power;
1024 unsigned int paprd_ratemask;
1025 unsigned int paprd_ratemask_ht40;
1026 bool paprd_table_write_done;
1027 u32 paprd_gain_table_entries[PAPRD_GAIN_TABLE_ENTRIES];
1028 u8 paprd_gain_table_index[PAPRD_GAIN_TABLE_ENTRIES];
1029 /*
1030 * Store the permanent value of Reg 0x4004in WARegVal
1031 * so we dont have to R/M/W. We should not be reading
1032 * this register when in sleep states.
1033 */
1034 u32 WARegVal;
1035
1036 /* Enterprise mode cap */
1037 u32 ent_mode;
1038
1039 bool is_clk_25mhz;
1040 int (*get_mac_revision)(void);
1041 int (*external_reset)(void);
1042 };
1043
1044 struct ath_bus_ops {
1045 enum ath_bus_type ath_bus_type;
1046 void (*read_cachesize)(struct ath_common *common, int *csz);
1047 bool (*eeprom_read)(struct ath_common *common, u32 off, u16 *data);
1048 void (*bt_coex_prep)(struct ath_common *common);
1049 void (*extn_synch_en)(struct ath_common *common);
1050 void (*aspm_init)(struct ath_common *common);
1051 };
1052
1053 static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
1054 {
1055 return &ah->common;
1056 }
1057
1058 static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah)
1059 {
1060 return &(ath9k_hw_common(ah)->regulatory);
1061 }
1062
1063 static inline struct ath_hw_private_ops *ath9k_hw_private_ops(struct ath_hw *ah)
1064 {
1065 return &ah->private_ops;
1066 }
1067
1068 static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah)
1069 {
1070 return &ah->ops;
1071 }
1072
1073 static inline u8 get_streams(int mask)
1074 {
1075 return !!(mask & BIT(0)) + !!(mask & BIT(1)) + !!(mask & BIT(2));
1076 }
1077
1078 /* Initialization, Detach, Reset */
1079 const char *ath9k_hw_probe(u16 vendorid, u16 devid);
1080 void ath9k_hw_deinit(struct ath_hw *ah);
1081 int ath9k_hw_init(struct ath_hw *ah);
1082 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1083 struct ath9k_hw_cal_data *caldata, bool bChannelChange);
1084 int ath9k_hw_fill_cap_info(struct ath_hw *ah);
1085 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan);
1086
1087 /* GPIO / RFKILL / Antennae */
1088 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio);
1089 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio);
1090 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
1091 u32 ah_signal_type);
1092 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val);
1093 u32 ath9k_hw_getdefantenna(struct ath_hw *ah);
1094 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna);
1095
1096 /* General Operation */
1097 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout);
1098 void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array,
1099 int column, unsigned int *writecnt);
1100 u32 ath9k_hw_reverse_bits(u32 val, u32 n);
1101 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
1102 u8 phy, int kbps,
1103 u32 frameLen, u16 rateix, bool shortPreamble);
1104 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
1105 struct ath9k_channel *chan,
1106 struct chan_centers *centers);
1107 u32 ath9k_hw_getrxfilter(struct ath_hw *ah);
1108 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits);
1109 bool ath9k_hw_phy_disable(struct ath_hw *ah);
1110 bool ath9k_hw_disable(struct ath_hw *ah);
1111 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test);
1112 void ath9k_hw_setopmode(struct ath_hw *ah);
1113 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1);
1114 void ath9k_hw_write_associd(struct ath_hw *ah);
1115 u32 ath9k_hw_gettsf32(struct ath_hw *ah);
1116 u64 ath9k_hw_gettsf64(struct ath_hw *ah);
1117 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64);
1118 void ath9k_hw_reset_tsf(struct ath_hw *ah);
1119 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting);
1120 void ath9k_hw_init_global_settings(struct ath_hw *ah);
1121 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah);
1122 void ath9k_hw_set11nmac2040(struct ath_hw *ah);
1123 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period);
1124 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
1125 const struct ath9k_beacon_state *bs);
1126 bool ath9k_hw_check_alive(struct ath_hw *ah);
1127
1128 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode);
1129
1130 /* Generic hw timer primitives */
1131 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
1132 void (*trigger)(void *),
1133 void (*overflow)(void *),
1134 void *arg,
1135 u8 timer_index);
1136 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
1137 struct ath_gen_timer *timer,
1138 u32 timer_next,
1139 u32 timer_period);
1140 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer);
1141
1142 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer);
1143 void ath_gen_timer_isr(struct ath_hw *hw);
1144
1145 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len);
1146
1147 /* HTC */
1148 void ath9k_hw_htc_resetinit(struct ath_hw *ah);
1149
1150 /* PHY */
1151 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1152 u32 *coef_mantissa, u32 *coef_exponent);
1153 void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan);
1154
1155 /*
1156 * Code Specific to AR5008, AR9001 or AR9002,
1157 * we stuff these here to avoid callbacks for AR9003.
1158 */
1159 void ar9002_hw_cck_chan14_spread(struct ath_hw *ah);
1160 int ar9002_hw_rf_claim(struct ath_hw *ah);
1161 void ar9002_hw_enable_async_fifo(struct ath_hw *ah);
1162
1163 /*
1164 * Code specific to AR9003, we stuff these here to avoid callbacks
1165 * for older families
1166 */
1167 void ar9003_hw_bb_watchdog_config(struct ath_hw *ah);
1168 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah);
1169 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah);
1170 void ar9003_hw_disable_phy_restart(struct ath_hw *ah);
1171 void ar9003_paprd_enable(struct ath_hw *ah, bool val);
1172 void ar9003_paprd_populate_single_table(struct ath_hw *ah,
1173 struct ath9k_hw_cal_data *caldata,
1174 int chain);
1175 int ar9003_paprd_create_curve(struct ath_hw *ah,
1176 struct ath9k_hw_cal_data *caldata, int chain);
1177 int ar9003_paprd_setup_gain_table(struct ath_hw *ah, int chain);
1178 int ar9003_paprd_init_table(struct ath_hw *ah);
1179 bool ar9003_paprd_is_done(struct ath_hw *ah);
1180 void ar9003_hw_set_paprd_txdesc(struct ath_hw *ah, void *ds, u8 chains);
1181
1182 /* Hardware family op attach helpers */
1183 void ar5008_hw_attach_phy_ops(struct ath_hw *ah);
1184 void ar9002_hw_attach_phy_ops(struct ath_hw *ah);
1185 void ar9003_hw_attach_phy_ops(struct ath_hw *ah);
1186
1187 void ar9002_hw_attach_calib_ops(struct ath_hw *ah);
1188 void ar9003_hw_attach_calib_ops(struct ath_hw *ah);
1189
1190 void ar9002_hw_attach_ops(struct ath_hw *ah);
1191 void ar9003_hw_attach_ops(struct ath_hw *ah);
1192
1193 void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan);
1194 /*
1195 * ANI work can be shared between all families but a next
1196 * generation implementation of ANI will be used only for AR9003 only
1197 * for now as the other families still need to be tested with the same
1198 * next generation ANI. Feel free to start testing it though for the
1199 * older families (AR5008, AR9001, AR9002) by using modparam_force_new_ani.
1200 */
1201 extern int modparam_force_new_ani;
1202 void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning);
1203 void ath9k_hw_proc_mib_event(struct ath_hw *ah);
1204 void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan);
1205
1206 bool ar9003_mci_send_message(struct ath_hw *ah, u8 header, u32 flag,
1207 u32 *payload, u8 len, bool wait_done,
1208 bool check_bt);
1209 void ar9003_mci_mute_bt(struct ath_hw *ah);
1210 u32 ar9003_mci_state(struct ath_hw *ah, u32 state_type, u32 *p_data);
1211 void ar9003_mci_setup(struct ath_hw *ah, u32 gpm_addr, void *gpm_buf,
1212 u16 len, u32 sched_addr);
1213 void ar9003_mci_cleanup(struct ath_hw *ah);
1214 void ar9003_mci_send_coex_halt_bt_gpm(struct ath_hw *ah, bool halt,
1215 bool wait_done);
1216 u32 ar9003_mci_wait_for_gpm(struct ath_hw *ah, u8 gpm_type,
1217 u8 gpm_opcode, int time_out);
1218 void ar9003_mci_2g5g_changed(struct ath_hw *ah, bool is_2g);
1219 void ar9003_mci_disable_interrupt(struct ath_hw *ah);
1220 void ar9003_mci_enable_interrupt(struct ath_hw *ah);
1221 void ar9003_mci_2g5g_switch(struct ath_hw *ah, bool wait_done);
1222 void ar9003_mci_reset(struct ath_hw *ah, bool en_int, bool is_2g,
1223 bool is_full_sleep);
1224 bool ar9003_mci_check_int(struct ath_hw *ah, u32 ints);
1225 void ar9003_mci_remote_reset(struct ath_hw *ah, bool wait_done);
1226 void ar9003_mci_send_sys_waking(struct ath_hw *ah, bool wait_done);
1227 void ar9003_mci_send_lna_transfer(struct ath_hw *ah, bool wait_done);
1228 void ar9003_mci_sync_bt_state(struct ath_hw *ah);
1229 void ar9003_mci_get_interrupt(struct ath_hw *ah, u32 *raw_intr,
1230 u32 *rx_msg_intr);
1231
1232 #define ATH9K_CLOCK_RATE_CCK 22
1233 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
1234 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
1235 #define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44
1236
1237 #endif
Linux kernel - Deliverables
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