2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include <linux/if_ether.h>
21 #include <linux/delay.h>
34 #define ATHEROS_VENDOR_ID 0x168c
36 #define AR5416_DEVID_PCI 0x0023
37 #define AR5416_DEVID_PCIE 0x0024
38 #define AR9160_DEVID_PCI 0x0027
39 #define AR9280_DEVID_PCI 0x0029
40 #define AR9280_DEVID_PCIE 0x002a
41 #define AR9285_DEVID_PCIE 0x002b
42 #define AR2427_DEVID_PCIE 0x002c
43 #define AR9287_DEVID_PCI 0x002d
44 #define AR9287_DEVID_PCIE 0x002e
45 #define AR9300_DEVID_PCIE 0x0030
46 #define AR9300_DEVID_AR9340 0x0031
47 #define AR9300_DEVID_AR9485_PCIE 0x0032
48 #define AR9300_DEVID_AR9580 0x0033
49 #define AR9300_DEVID_AR9462 0x0034
50 #define AR9300_DEVID_AR9330 0x0035
51 #define AR9300_DEVID_QCA955X 0x0038
52 #define AR9485_DEVID_AR1111 0x0037
54 #define AR5416_AR9100_DEVID 0x000b
56 #define AR_SUBVENDOR_ID_NOG 0x0e11
57 #define AR_SUBVENDOR_ID_NEW_A 0x7065
58 #define AR5416_MAGIC 0x19641014
60 #define AR9280_COEX2WIRE_SUBSYSID 0x309b
61 #define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa
62 #define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab
64 #define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1)
66 #define ATH_DEFAULT_NOISE_FLOOR -95
68 #define ATH9K_RSSI_BAD -128
70 #define ATH9K_NUM_CHANNELS 38
72 /* Register read/write primitives */
73 #define REG_WRITE(_ah, _reg, _val) \
74 (_ah)->reg_ops.write((_ah), (_val), (_reg))
76 #define REG_READ(_ah, _reg) \
77 (_ah)->reg_ops.read((_ah), (_reg))
79 #define REG_READ_MULTI(_ah, _addr, _val, _cnt) \
80 (_ah)->reg_ops.multi_read((_ah), (_addr), (_val), (_cnt))
82 #define REG_RMW(_ah, _reg, _set, _clr) \
83 (_ah)->reg_ops.rmw((_ah), (_reg), (_set), (_clr))
85 #define ENABLE_REGWRITE_BUFFER(_ah) \
87 if ((_ah)->reg_ops.enable_write_buffer) \
88 (_ah)->reg_ops.enable_write_buffer((_ah)); \
91 #define REGWRITE_BUFFER_FLUSH(_ah) \
93 if ((_ah)->reg_ops.write_flush) \
94 (_ah)->reg_ops.write_flush((_ah)); \
97 #define PR_EEP(_s, _val) \
99 len += snprintf(buf + len, size - len, "%20s : %10d\n", \
103 #define SM(_v, _f) (((_v) << _f##_S) & _f)
104 #define MS(_v, _f) (((_v) & _f) >> _f##_S)
105 #define REG_RMW_FIELD(_a, _r, _f, _v) \
106 REG_RMW(_a, _r, (((_v) << _f##_S) & _f), (_f))
107 #define REG_READ_FIELD(_a, _r, _f) \
108 (((REG_READ(_a, _r) & _f) >> _f##_S))
109 #define REG_SET_BIT(_a, _r, _f) \
110 REG_RMW(_a, _r, (_f), 0)
111 #define REG_CLR_BIT(_a, _r, _f) \
112 REG_RMW(_a, _r, 0, (_f))
114 #define DO_DELAY(x) do { \
115 if (((++(x) % 64) == 0) && \
116 (ath9k_hw_common(ah)->bus_ops->ath_bus_type \
121 #define REG_WRITE_ARRAY(iniarray, column, regWr) \
122 ath9k_hw_write_array(ah, iniarray, column, &(regWr))
124 #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
125 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
126 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
127 #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3
128 #define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4
129 #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
130 #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
131 #define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_DATA 0x16
132 #define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_CLK 0x17
133 #define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA 0x18
134 #define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK 0x19
135 #define AR_GPIO_OUTPUT_MUX_AS_WL_IN_TX 0x14
136 #define AR_GPIO_OUTPUT_MUX_AS_WL_IN_RX 0x13
137 #define AR_GPIO_OUTPUT_MUX_AS_BT_IN_TX 9
138 #define AR_GPIO_OUTPUT_MUX_AS_BT_IN_RX 8
139 #define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_STROBE 0x1d
140 #define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_DATA 0x1e
142 #define AR_GPIOD_MASK 0x00001FFF
143 #define AR_GPIO_BIT(_gpio) (1 << (_gpio))
145 #define BASE_ACTIVATE_DELAY 100
146 #define RTC_PLL_SETTLE_DELAY (AR_SREV_9340(ah) ? 1000 : 100)
147 #define COEF_SCALE_S 24
148 #define HT40_CHANNEL_CENTER_SHIFT 10
150 #define ATH9K_ANTENNA0_CHAINMASK 0x1
151 #define ATH9K_ANTENNA1_CHAINMASK 0x2
153 #define ATH9K_NUM_DMA_DEBUG_REGS 8
154 #define ATH9K_NUM_QUEUES 10
156 #define MAX_RATE_POWER 63
157 #define AH_WAIT_TIMEOUT 100000 /* (us) */
158 #define AH_TSF_WRITE_TIMEOUT 100 /* (us) */
159 #define AH_TIME_QUANTUM 10
160 #define AR_KEYTABLE_SIZE 128
161 #define POWER_UP_TIME 10000
162 #define SPUR_RSSI_THRESH 40
163 #define UPPER_5G_SUB_BAND_START 5700
164 #define MID_5G_SUB_BAND_START 5400
166 #define CAB_TIMEOUT_VAL 10
167 #define BEACON_TIMEOUT_VAL 10
168 #define MIN_BEACON_TIMEOUT_VAL 1
171 #define INIT_CONFIG_STATUS 0x00000000
172 #define INIT_RSSI_THR 0x00000700
173 #define INIT_BCON_CNTRL_REG 0x00000000
175 #define TU_TO_USEC(_tu) ((_tu) << 10)
177 #define ATH9K_HW_RX_HP_QDEPTH 16
178 #define ATH9K_HW_RX_LP_QDEPTH 128
180 #define PAPRD_GAIN_TABLE_ENTRIES 32
181 #define PAPRD_TABLE_SZ 24
182 #define PAPRD_IDEAL_AGC2_PWR_RANGE 0xe0
188 /* Keep Alive Frame */
189 #define KAL_FRAME_LEN 28
190 #define KAL_FRAME_TYPE 0x2 /* data frame */
191 #define KAL_FRAME_SUB_TYPE 0x4 /* null data frame */
192 #define KAL_DURATION_ID 0x3d
193 #define KAL_NUM_DATA_WORDS 6
194 #define KAL_NUM_DESC_WORDS 12
195 #define KAL_ANTENNA_MODE 1
197 #define KAL_DELAY 4 /*delay of 4ms between 2 KAL frames */
198 #define KAL_TIMEOUT 900
200 #define MAX_PATTERN_SIZE 256
201 #define MAX_PATTERN_MASK_SIZE 32
202 #define MAX_NUM_PATTERN 8
203 #define MAX_NUM_USER_PATTERN 6 /* deducting the disassociate and
204 deauthenticate packets */
207 * WoW trigger mapping to hardware code
210 #define AH_WOW_USER_PATTERN_EN BIT(0)
211 #define AH_WOW_MAGIC_PATTERN_EN BIT(1)
212 #define AH_WOW_LINK_CHANGE BIT(2)
213 #define AH_WOW_BEACON_MISS BIT(3)
215 enum ath_hw_txq_subtype
{
222 enum ath_ini_subsys
{
230 ATH9K_HW_CAP_HT
= BIT(0),
231 ATH9K_HW_CAP_RFSILENT
= BIT(1),
232 ATH9K_HW_CAP_AUTOSLEEP
= BIT(2),
233 ATH9K_HW_CAP_4KB_SPLITTRANS
= BIT(3),
234 ATH9K_HW_CAP_EDMA
= BIT(4),
235 ATH9K_HW_CAP_RAC_SUPPORTED
= BIT(5),
236 ATH9K_HW_CAP_LDPC
= BIT(6),
237 ATH9K_HW_CAP_FASTCLOCK
= BIT(7),
238 ATH9K_HW_CAP_SGI_20
= BIT(8),
239 ATH9K_HW_CAP_PAPRD
= BIT(9),
240 ATH9K_HW_CAP_ANT_DIV_COMB
= BIT(10),
241 ATH9K_HW_CAP_2GHZ
= BIT(11),
242 ATH9K_HW_CAP_5GHZ
= BIT(12),
243 ATH9K_HW_CAP_APM
= BIT(13),
244 ATH9K_HW_CAP_RTT
= BIT(14),
245 ATH9K_HW_CAP_MCI
= BIT(15),
246 ATH9K_HW_CAP_DFS
= BIT(16),
247 ATH9K_HW_WOW_DEVICE_CAPABLE
= BIT(17),
248 ATH9K_HW_WOW_PATTERN_MATCH_EXACT
= BIT(18),
249 ATH9K_HW_WOW_PATTERN_MATCH_DWORD
= BIT(19),
253 * WoW device capabilities
254 * @ATH9K_HW_WOW_DEVICE_CAPABLE: device revision is capable of WoW.
255 * @ATH9K_HW_WOW_PATTERN_MATCH_EXACT: device is capable of matching
256 * an exact user defined pattern or de-authentication/disassoc pattern.
257 * @ATH9K_HW_WOW_PATTERN_MATCH_DWORD: device requires the first four
258 * bytes of the pattern for user defined pattern, de-authentication and
259 * disassociation patterns for all types of possible frames recieved
263 struct ath9k_hw_capabilities
{
264 u32 hw_caps
; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
277 bool pcie_lcr_extsync_en
;
280 struct ath9k_ops_config
{
281 int dma_beacon_response_time
;
282 int sw_beacon_response_time
;
283 int additional_swba_backoff
;
285 u32 cwm_ignore_extcca
;
286 bool pcieSerDesWrite
;
296 int serialize_regmode
;
297 bool rx_intr_mitigation
;
298 bool tx_intr_mitigation
;
299 #define SPUR_DISABLE 0
300 #define SPUR_ENABLE_IOCTL 1
301 #define SPUR_ENABLE_EEPROM 2
302 #define AR_SPUR_5413_1 1640
303 #define AR_SPUR_5413_2 1200
304 #define AR_NO_SPUR 0x8000
305 #define AR_BASE_FREQ_2GHZ 2300
306 #define AR_BASE_FREQ_5GHZ 4900
307 #define AR_SPUR_FEEQ_BOUND_HT40 19
308 #define AR_SPUR_FEEQ_BOUND_HT20 10
310 u16 spurchans
[AR_EEPROM_MODAL_SPURS
][2];
312 u16 ani_poll_interval
; /* ANI poll interval in ms */
316 ATH9K_INT_RX
= 0x00000001,
317 ATH9K_INT_RXDESC
= 0x00000002,
318 ATH9K_INT_RXHP
= 0x00000001,
319 ATH9K_INT_RXLP
= 0x00000002,
320 ATH9K_INT_RXNOFRM
= 0x00000008,
321 ATH9K_INT_RXEOL
= 0x00000010,
322 ATH9K_INT_RXORN
= 0x00000020,
323 ATH9K_INT_TX
= 0x00000040,
324 ATH9K_INT_TXDESC
= 0x00000080,
325 ATH9K_INT_TIM_TIMER
= 0x00000100,
326 ATH9K_INT_MCI
= 0x00000200,
327 ATH9K_INT_BB_WATCHDOG
= 0x00000400,
328 ATH9K_INT_TXURN
= 0x00000800,
329 ATH9K_INT_MIB
= 0x00001000,
330 ATH9K_INT_RXPHY
= 0x00004000,
331 ATH9K_INT_RXKCM
= 0x00008000,
332 ATH9K_INT_SWBA
= 0x00010000,
333 ATH9K_INT_BMISS
= 0x00040000,
334 ATH9K_INT_BNR
= 0x00100000,
335 ATH9K_INT_TIM
= 0x00200000,
336 ATH9K_INT_DTIM
= 0x00400000,
337 ATH9K_INT_DTIMSYNC
= 0x00800000,
338 ATH9K_INT_GPIO
= 0x01000000,
339 ATH9K_INT_CABEND
= 0x02000000,
340 ATH9K_INT_TSFOOR
= 0x04000000,
341 ATH9K_INT_GENTIMER
= 0x08000000,
342 ATH9K_INT_CST
= 0x10000000,
343 ATH9K_INT_GTT
= 0x20000000,
344 ATH9K_INT_FATAL
= 0x40000000,
345 ATH9K_INT_GLOBAL
= 0x80000000,
346 ATH9K_INT_BMISC
= ATH9K_INT_TIM
|
351 ATH9K_INT_COMMON
= ATH9K_INT_RXNOFRM
|
363 ATH9K_INT_NOCARD
= 0xffffffff
366 #define CHANNEL_CW_INT 0x00002
367 #define CHANNEL_CCK 0x00020
368 #define CHANNEL_OFDM 0x00040
369 #define CHANNEL_2GHZ 0x00080
370 #define CHANNEL_5GHZ 0x00100
371 #define CHANNEL_PASSIVE 0x00200
372 #define CHANNEL_DYN 0x00400
373 #define CHANNEL_HALF 0x04000
374 #define CHANNEL_QUARTER 0x08000
375 #define CHANNEL_HT20 0x10000
376 #define CHANNEL_HT40PLUS 0x20000
377 #define CHANNEL_HT40MINUS 0x40000
379 #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
380 #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
381 #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
382 #define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20)
383 #define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20)
384 #define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
385 #define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
386 #define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
387 #define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
388 #define CHANNEL_ALL \
397 #define MAX_RTT_TABLE_ENTRY 6
398 #define MAX_IQCAL_MEASUREMENT 8
399 #define MAX_CL_TAB_ENTRY 16
401 struct ath9k_hw_cal_data
{
410 bool nfcal_interference
;
411 bool done_txiqcal_once
;
412 bool done_txclcal_once
;
413 u16 small_signal_gain
[AR9300_MAX_CHAINS
];
414 u32 pa_table
[AR9300_MAX_CHAINS
][PAPRD_TABLE_SZ
];
415 u32 num_measures
[AR9300_MAX_CHAINS
];
416 int tx_corr_coeff
[MAX_IQCAL_MEASUREMENT
][AR9300_MAX_CHAINS
];
417 u32 tx_clcal
[AR9300_MAX_CHAINS
][MAX_CL_TAB_ENTRY
];
418 u32 rtt_table
[AR9300_MAX_CHAINS
][MAX_RTT_TABLE_ENTRY
];
419 struct ath9k_nfcal_hist nfCalHist
[NUM_NF_READINGS
];
422 struct ath9k_channel
{
423 struct ieee80211_channel
*chan
;
424 struct ar5416AniState ani
;
431 #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
432 (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
433 (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
434 (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
435 #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
436 #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
437 #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
438 #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
439 #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
440 #define IS_CHAN_A_FAST_CLOCK(_ah, _c) \
441 ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \
442 ((_ah)->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK))
444 /* These macros check chanmode and not channelFlags */
445 #define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B)
446 #define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \
447 ((_c)->chanmode == CHANNEL_G_HT20))
448 #define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \
449 ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \
450 ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \
451 ((_c)->chanmode == CHANNEL_G_HT40MINUS))
452 #define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
454 enum ath9k_power_mode
{
457 ATH9K_PM_NETWORK_SLEEP
,
462 SER_REG_MODE_OFF
= 0,
464 SER_REG_MODE_AUTO
= 2,
467 enum ath9k_rx_qtype
{
473 struct ath9k_beacon_state
{
477 #define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */
480 u16 bs_cfpmaxduration
;
483 u16 bs_bmissthreshold
;
484 u32 bs_sleepduration
;
485 u32 bs_tsfoor_threshold
;
488 struct chan_centers
{
495 ATH9K_RESET_POWER_ON
,
500 struct ath9k_hw_version
{
509 enum ath_usb_dev usbdev
;
512 /* Generic TSF timer definitions */
514 #define ATH_MAX_GEN_TIMER 16
516 #define AR_GENTMR_BIT(_index) (1 << (_index))
519 * Using de Bruijin sequence to look up 1's index in a 32 bit number
520 * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001
522 #define debruijn32 0x077CB531U
524 struct ath_gen_timer_configuration
{
531 struct ath_gen_timer
{
532 void (*trigger
)(void *arg
);
533 void (*overflow
)(void *arg
);
538 struct ath_gen_timer_table
{
539 u32 gen_timer_index
[32];
540 struct ath_gen_timer
*timers
[ATH_MAX_GEN_TIMER
];
542 unsigned long timer_bits
;
547 struct ath_hw_antcomb_conf
{
558 * struct ath_hw_radar_conf - radar detection initialization parameters
560 * @pulse_inband: threshold for checking the ratio of in-band power
561 * to total power for short radar pulses (half dB steps)
562 * @pulse_inband_step: threshold for checking an in-band power to total
563 * power ratio increase for short radar pulses (half dB steps)
564 * @pulse_height: threshold for detecting the beginning of a short
565 * radar pulse (dB step)
566 * @pulse_rssi: threshold for detecting if a short radar pulse is
568 * @pulse_maxlen: maximum pulse length (0.8 us steps)
570 * @radar_rssi: RSSI threshold for starting long radar detection (dB steps)
571 * @radar_inband: threshold for checking the ratio of in-band power
572 * to total power for long radar pulses (half dB steps)
573 * @fir_power: threshold for detecting the end of a long radar pulse (dB)
575 * @ext_channel: enable extension channel radar detection
577 struct ath_hw_radar_conf
{
578 unsigned int pulse_inband
;
579 unsigned int pulse_inband_step
;
580 unsigned int pulse_height
;
581 unsigned int pulse_rssi
;
582 unsigned int pulse_maxlen
;
584 unsigned int radar_rssi
;
585 unsigned int radar_inband
;
592 * struct ath_hw_private_ops - callbacks used internally by hardware code
594 * This structure contains private callbacks designed to only be used internally
595 * by the hardware core.
597 * @init_cal_settings: setup types of calibrations supported
598 * @init_cal: starts actual calibration
600 * @init_mode_regs: Initializes mode registers
601 * @init_mode_gain_regs: Initialize TX/RX gain registers
603 * @rf_set_freq: change frequency
604 * @spur_mitigate_freq: spur mitigation
605 * @rf_alloc_ext_banks:
606 * @rf_free_ext_banks:
608 * @compute_pll_control: compute the PLL control value to use for
609 * AR_RTC_PLL_CONTROL for a given channel
610 * @setup_calibration: set up calibration
611 * @iscal_supported: used to query if a type of calibration is supported
613 * @ani_cache_ini_regs: cache the values for ANI from the initial
614 * register settings through the register initialization.
616 struct ath_hw_private_ops
{
617 /* Calibration ops */
618 void (*init_cal_settings
)(struct ath_hw
*ah
);
619 bool (*init_cal
)(struct ath_hw
*ah
, struct ath9k_channel
*chan
);
621 void (*init_mode_regs
)(struct ath_hw
*ah
);
622 void (*init_mode_gain_regs
)(struct ath_hw
*ah
);
623 void (*setup_calibration
)(struct ath_hw
*ah
,
624 struct ath9k_cal_list
*currCal
);
627 int (*rf_set_freq
)(struct ath_hw
*ah
,
628 struct ath9k_channel
*chan
);
629 void (*spur_mitigate_freq
)(struct ath_hw
*ah
,
630 struct ath9k_channel
*chan
);
631 int (*rf_alloc_ext_banks
)(struct ath_hw
*ah
);
632 void (*rf_free_ext_banks
)(struct ath_hw
*ah
);
633 bool (*set_rf_regs
)(struct ath_hw
*ah
,
634 struct ath9k_channel
*chan
,
636 void (*set_channel_regs
)(struct ath_hw
*ah
, struct ath9k_channel
*chan
);
637 void (*init_bb
)(struct ath_hw
*ah
,
638 struct ath9k_channel
*chan
);
639 int (*process_ini
)(struct ath_hw
*ah
, struct ath9k_channel
*chan
);
640 void (*olc_init
)(struct ath_hw
*ah
);
641 void (*set_rfmode
)(struct ath_hw
*ah
, struct ath9k_channel
*chan
);
642 void (*mark_phy_inactive
)(struct ath_hw
*ah
);
643 void (*set_delta_slope
)(struct ath_hw
*ah
, struct ath9k_channel
*chan
);
644 bool (*rfbus_req
)(struct ath_hw
*ah
);
645 void (*rfbus_done
)(struct ath_hw
*ah
);
646 void (*restore_chainmask
)(struct ath_hw
*ah
);
647 u32 (*compute_pll_control
)(struct ath_hw
*ah
,
648 struct ath9k_channel
*chan
);
649 bool (*ani_control
)(struct ath_hw
*ah
, enum ath9k_ani_cmd cmd
,
651 void (*do_getnf
)(struct ath_hw
*ah
, int16_t nfarray
[NUM_NF_READINGS
]);
652 void (*set_radar_params
)(struct ath_hw
*ah
,
653 struct ath_hw_radar_conf
*conf
);
654 int (*fast_chan_change
)(struct ath_hw
*ah
, struct ath9k_channel
*chan
,
658 void (*ani_cache_ini_regs
)(struct ath_hw
*ah
);
662 * struct ath_hw_ops - callbacks used by hardware code and driver code
664 * This structure contains callbacks designed to to be used internally by
665 * hardware code and also by the lower level driver.
667 * @config_pci_powersave:
668 * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC
671 void (*config_pci_powersave
)(struct ath_hw
*ah
,
673 void (*rx_enable
)(struct ath_hw
*ah
);
674 void (*set_desc_link
)(void *ds
, u32 link
);
675 bool (*calibrate
)(struct ath_hw
*ah
,
676 struct ath9k_channel
*chan
,
679 bool (*get_isr
)(struct ath_hw
*ah
, enum ath9k_int
*masked
);
680 void (*set_txdesc
)(struct ath_hw
*ah
, void *ds
,
681 struct ath_tx_info
*i
);
682 int (*proc_txdesc
)(struct ath_hw
*ah
, void *ds
,
683 struct ath_tx_status
*ts
);
684 void (*antdiv_comb_conf_get
)(struct ath_hw
*ah
,
685 struct ath_hw_antcomb_conf
*antconf
);
686 void (*antdiv_comb_conf_set
)(struct ath_hw
*ah
,
687 struct ath_hw_antcomb_conf
*antconf
);
691 struct ath_nf_limits
{
699 TX_IQ_ON_AGC_CAL
= BIT(1),
704 #define AH_USE_EEPROM 0x1
705 #define AH_UNPLUGGED 0x2 /* The card has been physically removed. */
706 #define AH_FASTCC 0x4
709 struct ath_ops reg_ops
;
711 struct ieee80211_hw
*hw
;
712 struct ath_common common
;
713 struct ath9k_hw_version hw_version
;
714 struct ath9k_ops_config config
;
715 struct ath9k_hw_capabilities caps
;
716 struct ath9k_channel channels
[ATH9K_NUM_CHANNELS
];
717 struct ath9k_channel
*curchan
;
720 struct ar5416_eeprom_def def
;
721 struct ar5416_eeprom_4k map4k
;
722 struct ar9287_eeprom map9287
;
723 struct ar9300_eeprom ar9300_eep
;
725 const struct eeprom_ops
*eep_ops
;
731 bool need_an_top2_fixup
;
735 struct ath_nf_limits nf_2g
;
736 struct ath_nf_limits nf_5g
;
744 enum nl80211_iftype opmode
;
745 enum ath9k_power_mode power_mode
;
748 struct ath9k_hw_cal_data
*caldata
;
749 struct ath9k_pacal_info pacal_info
;
750 struct ar5416Stats stats
;
751 struct ath9k_tx_queue_info txq
[ATH9K_NUM_TX_QUEUES
];
753 enum ath9k_int imask
;
755 u32 txok_interrupt_mask
;
756 u32 txerr_interrupt_mask
;
757 u32 txdesc_interrupt_mask
;
758 u32 txeol_interrupt_mask
;
759 u32 txurn_interrupt_mask
;
760 atomic_t intr_ref_cnt
;
767 struct ath9k_cal_list iq_caldata
;
768 struct ath9k_cal_list adcgain_caldata
;
769 struct ath9k_cal_list adcdc_caldata
;
770 struct ath9k_cal_list tempCompCalData
;
771 struct ath9k_cal_list
*cal_list
;
772 struct ath9k_cal_list
*cal_list_last
;
773 struct ath9k_cal_list
*cal_list_curr
;
774 #define totalPowerMeasI meas0.unsign
775 #define totalPowerMeasQ meas1.unsign
776 #define totalIqCorrMeas meas2.sign
777 #define totalAdcIOddPhase meas0.unsign
778 #define totalAdcIEvenPhase meas1.unsign
779 #define totalAdcQOddPhase meas2.unsign
780 #define totalAdcQEvenPhase meas3.unsign
781 #define totalAdcDcOffsetIOddPhase meas0.sign
782 #define totalAdcDcOffsetIEvenPhase meas1.sign
783 #define totalAdcDcOffsetQOddPhase meas2.sign
784 #define totalAdcDcOffsetQEvenPhase meas3.sign
786 u32 unsign
[AR5416_MAX_CHAINS
];
787 int32_t sign
[AR5416_MAX_CHAINS
];
790 u32 unsign
[AR5416_MAX_CHAINS
];
791 int32_t sign
[AR5416_MAX_CHAINS
];
794 u32 unsign
[AR5416_MAX_CHAINS
];
795 int32_t sign
[AR5416_MAX_CHAINS
];
798 u32 unsign
[AR5416_MAX_CHAINS
];
799 int32_t sign
[AR5416_MAX_CHAINS
];
804 u32 sta_id1_defaults
;
807 /* Private to hardware code */
808 struct ath_hw_private_ops private_ops
;
809 /* Accessed by the lower level driver */
810 struct ath_hw_ops ops
;
812 /* Used to program the radio on non single-chip devices */
813 u32
*analogBank0Data
;
814 u32
*analogBank1Data
;
815 u32
*analogBank2Data
;
816 u32
*analogBank3Data
;
817 u32
*analogBank6Data
;
818 u32
*analogBank6TPCData
;
819 u32
*analogBank7Data
;
829 int totalSizeDesired
[5];
833 enum ath9k_ani_cmd ani_function
;
835 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
836 struct ath_btcoex_hw btcoex_hw
;
843 struct ath_hw_radar_conf radar_conf
;
845 u32 originalGain
[22];
852 struct ar5416IniArray iniModes
;
853 struct ar5416IniArray iniCommon
;
854 struct ar5416IniArray iniBank0
;
855 struct ar5416IniArray iniBB_RfGain
;
856 struct ar5416IniArray iniBank1
;
857 struct ar5416IniArray iniBank2
;
858 struct ar5416IniArray iniBank3
;
859 struct ar5416IniArray iniBank6
;
860 struct ar5416IniArray iniBank6TPC
;
861 struct ar5416IniArray iniBank7
;
862 struct ar5416IniArray iniAddac
;
863 struct ar5416IniArray iniPcieSerdes
;
864 #ifdef CONFIG_PM_SLEEP
865 struct ar5416IniArray iniPcieSerdesWow
;
867 struct ar5416IniArray iniPcieSerdesLowPower
;
868 struct ar5416IniArray iniModesFastClock
;
869 struct ar5416IniArray iniAdditional
;
870 struct ar5416IniArray iniModesRxGain
;
871 struct ar5416IniArray ini_modes_rx_gain_bounds
;
872 struct ar5416IniArray iniModesTxGain
;
873 struct ar5416IniArray iniCckfirNormal
;
874 struct ar5416IniArray iniCckfirJapan2484
;
875 struct ar5416IniArray ini_japan2484
;
876 struct ar5416IniArray iniModes_9271_ANI_reg
;
877 struct ar5416IniArray ini_radio_post_sys2ant
;
879 struct ar5416IniArray iniMac
[ATH_INI_NUM_SPLIT
];
880 struct ar5416IniArray iniBB
[ATH_INI_NUM_SPLIT
];
881 struct ar5416IniArray iniRadio
[ATH_INI_NUM_SPLIT
];
882 struct ar5416IniArray iniSOC
[ATH_INI_NUM_SPLIT
];
884 u32 intr_gen_timer_trigger
;
885 u32 intr_gen_timer_thresh
;
886 struct ath_gen_timer_table hw_gen_timers
;
888 struct ar9003_txs
*ts_ring
;
894 u32 bb_watchdog_last_status
;
895 u32 bb_watchdog_timeout_ms
; /* in ms, 0 to disable */
896 u8 bb_hang_rx_ofdm
; /* true if bb hang due to rx_ofdm */
898 unsigned int paprd_target_power
;
899 unsigned int paprd_training_power
;
900 unsigned int paprd_ratemask
;
901 unsigned int paprd_ratemask_ht40
;
902 bool paprd_table_write_done
;
903 u32 paprd_gain_table_entries
[PAPRD_GAIN_TABLE_ENTRIES
];
904 u8 paprd_gain_table_index
[PAPRD_GAIN_TABLE_ENTRIES
];
906 * Store the permanent value of Reg 0x4004in WARegVal
907 * so we dont have to R/M/W. We should not be reading
908 * this register when in sleep states.
912 /* Enterprise mode cap */
915 #ifdef CONFIG_PM_SLEEP
919 int (*get_mac_revision
)(void);
920 int (*external_reset
)(void);
924 enum ath_bus_type ath_bus_type
;
925 void (*read_cachesize
)(struct ath_common
*common
, int *csz
);
926 bool (*eeprom_read
)(struct ath_common
*common
, u32 off
, u16
*data
);
927 void (*bt_coex_prep
)(struct ath_common
*common
);
928 void (*extn_synch_en
)(struct ath_common
*common
);
929 void (*aspm_init
)(struct ath_common
*common
);
932 static inline struct ath_common
*ath9k_hw_common(struct ath_hw
*ah
)
937 static inline struct ath_regulatory
*ath9k_hw_regulatory(struct ath_hw
*ah
)
939 return &(ath9k_hw_common(ah
)->regulatory
);
942 static inline struct ath_hw_private_ops
*ath9k_hw_private_ops(struct ath_hw
*ah
)
944 return &ah
->private_ops
;
947 static inline struct ath_hw_ops
*ath9k_hw_ops(struct ath_hw
*ah
)
952 static inline u8
get_streams(int mask
)
954 return !!(mask
& BIT(0)) + !!(mask
& BIT(1)) + !!(mask
& BIT(2));
957 /* Initialization, Detach, Reset */
958 void ath9k_hw_deinit(struct ath_hw
*ah
);
959 int ath9k_hw_init(struct ath_hw
*ah
);
960 int ath9k_hw_reset(struct ath_hw
*ah
, struct ath9k_channel
*chan
,
961 struct ath9k_hw_cal_data
*caldata
, bool fastcc
);
962 int ath9k_hw_fill_cap_info(struct ath_hw
*ah
);
963 u32
ath9k_regd_get_ctl(struct ath_regulatory
*reg
, struct ath9k_channel
*chan
);
965 /* GPIO / RFKILL / Antennae */
966 void ath9k_hw_cfg_gpio_input(struct ath_hw
*ah
, u32 gpio
);
967 u32
ath9k_hw_gpio_get(struct ath_hw
*ah
, u32 gpio
);
968 void ath9k_hw_cfg_output(struct ath_hw
*ah
, u32 gpio
,
970 void ath9k_hw_set_gpio(struct ath_hw
*ah
, u32 gpio
, u32 val
);
971 void ath9k_hw_setantenna(struct ath_hw
*ah
, u32 antenna
);
973 /* General Operation */
974 void ath9k_hw_synth_delay(struct ath_hw
*ah
, struct ath9k_channel
*chan
,
976 bool ath9k_hw_wait(struct ath_hw
*ah
, u32 reg
, u32 mask
, u32 val
, u32 timeout
);
977 void ath9k_hw_write_array(struct ath_hw
*ah
, struct ar5416IniArray
*array
,
978 int column
, unsigned int *writecnt
);
979 u32
ath9k_hw_reverse_bits(u32 val
, u32 n
);
980 u16
ath9k_hw_computetxtime(struct ath_hw
*ah
,
982 u32 frameLen
, u16 rateix
, bool shortPreamble
);
983 void ath9k_hw_get_channel_centers(struct ath_hw
*ah
,
984 struct ath9k_channel
*chan
,
985 struct chan_centers
*centers
);
986 u32
ath9k_hw_getrxfilter(struct ath_hw
*ah
);
987 void ath9k_hw_setrxfilter(struct ath_hw
*ah
, u32 bits
);
988 bool ath9k_hw_phy_disable(struct ath_hw
*ah
);
989 bool ath9k_hw_disable(struct ath_hw
*ah
);
990 void ath9k_hw_set_txpowerlimit(struct ath_hw
*ah
, u32 limit
, bool test
);
991 void ath9k_hw_setopmode(struct ath_hw
*ah
);
992 void ath9k_hw_setmcastfilter(struct ath_hw
*ah
, u32 filter0
, u32 filter1
);
993 void ath9k_hw_write_associd(struct ath_hw
*ah
);
994 u32
ath9k_hw_gettsf32(struct ath_hw
*ah
);
995 u64
ath9k_hw_gettsf64(struct ath_hw
*ah
);
996 void ath9k_hw_settsf64(struct ath_hw
*ah
, u64 tsf64
);
997 void ath9k_hw_reset_tsf(struct ath_hw
*ah
);
998 void ath9k_hw_set_tsfadjust(struct ath_hw
*ah
, bool set
);
999 void ath9k_hw_init_global_settings(struct ath_hw
*ah
);
1000 u32
ar9003_get_pll_sqsum_dvc(struct ath_hw
*ah
);
1001 void ath9k_hw_set11nmac2040(struct ath_hw
*ah
);
1002 void ath9k_hw_beaconinit(struct ath_hw
*ah
, u32 next_beacon
, u32 beacon_period
);
1003 void ath9k_hw_set_sta_beacon_timers(struct ath_hw
*ah
,
1004 const struct ath9k_beacon_state
*bs
);
1005 bool ath9k_hw_check_alive(struct ath_hw
*ah
);
1007 bool ath9k_hw_setpower(struct ath_hw
*ah
, enum ath9k_power_mode mode
);
1009 #ifdef CONFIG_ATH9K_DEBUGFS
1010 void ath9k_debug_sync_cause(struct ath_common
*common
, u32 sync_cause
);
1012 static inline void ath9k_debug_sync_cause(struct ath_common
*common
,
1016 /* Generic hw timer primitives */
1017 struct ath_gen_timer
*ath_gen_timer_alloc(struct ath_hw
*ah
,
1018 void (*trigger
)(void *),
1019 void (*overflow
)(void *),
1022 void ath9k_hw_gen_timer_start(struct ath_hw
*ah
,
1023 struct ath_gen_timer
*timer
,
1026 void ath9k_hw_gen_timer_stop(struct ath_hw
*ah
, struct ath_gen_timer
*timer
);
1028 void ath_gen_timer_free(struct ath_hw
*ah
, struct ath_gen_timer
*timer
);
1029 void ath_gen_timer_isr(struct ath_hw
*hw
);
1031 void ath9k_hw_name(struct ath_hw
*ah
, char *hw_name
, size_t len
);
1034 void ath9k_hw_get_delta_slope_vals(struct ath_hw
*ah
, u32 coef_scaled
,
1035 u32
*coef_mantissa
, u32
*coef_exponent
);
1036 void ath9k_hw_apply_txpower(struct ath_hw
*ah
, struct ath9k_channel
*chan
,
1040 * Code Specific to AR5008, AR9001 or AR9002,
1041 * we stuff these here to avoid callbacks for AR9003.
1043 int ar9002_hw_rf_claim(struct ath_hw
*ah
);
1044 void ar9002_hw_enable_async_fifo(struct ath_hw
*ah
);
1047 * Code specific to AR9003, we stuff these here to avoid callbacks
1048 * for older families
1050 void ar9003_hw_bb_watchdog_config(struct ath_hw
*ah
);
1051 void ar9003_hw_bb_watchdog_read(struct ath_hw
*ah
);
1052 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw
*ah
);
1053 void ar9003_hw_disable_phy_restart(struct ath_hw
*ah
);
1054 void ar9003_paprd_enable(struct ath_hw
*ah
, bool val
);
1055 void ar9003_paprd_populate_single_table(struct ath_hw
*ah
,
1056 struct ath9k_hw_cal_data
*caldata
,
1058 int ar9003_paprd_create_curve(struct ath_hw
*ah
,
1059 struct ath9k_hw_cal_data
*caldata
, int chain
);
1060 int ar9003_paprd_setup_gain_table(struct ath_hw
*ah
, int chain
);
1061 int ar9003_paprd_init_table(struct ath_hw
*ah
);
1062 bool ar9003_paprd_is_done(struct ath_hw
*ah
);
1064 /* Hardware family op attach helpers */
1065 void ar5008_hw_attach_phy_ops(struct ath_hw
*ah
);
1066 void ar9002_hw_attach_phy_ops(struct ath_hw
*ah
);
1067 void ar9003_hw_attach_phy_ops(struct ath_hw
*ah
);
1069 void ar9002_hw_attach_calib_ops(struct ath_hw
*ah
);
1070 void ar9003_hw_attach_calib_ops(struct ath_hw
*ah
);
1072 void ar9002_hw_attach_ops(struct ath_hw
*ah
);
1073 void ar9003_hw_attach_ops(struct ath_hw
*ah
);
1075 void ar9002_hw_load_ani_reg(struct ath_hw
*ah
, struct ath9k_channel
*chan
);
1077 void ath9k_ani_reset(struct ath_hw
*ah
, bool is_scanning
);
1078 void ath9k_hw_ani_monitor(struct ath_hw
*ah
, struct ath9k_channel
*chan
);
1080 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
1081 static inline bool ath9k_hw_btcoex_is_enabled(struct ath_hw
*ah
)
1083 return ah
->btcoex_hw
.enabled
;
1085 static inline bool ath9k_hw_mci_is_enabled(struct ath_hw
*ah
)
1087 return ah
->common
.btcoex_enabled
&&
1088 (ah
->caps
.hw_caps
& ATH9K_HW_CAP_MCI
);
1091 void ath9k_hw_btcoex_enable(struct ath_hw
*ah
);
1092 static inline enum ath_btcoex_scheme
1093 ath9k_hw_get_btcoex_scheme(struct ath_hw
*ah
)
1095 return ah
->btcoex_hw
.scheme
;
1098 static inline bool ath9k_hw_btcoex_is_enabled(struct ath_hw
*ah
)
1102 static inline bool ath9k_hw_mci_is_enabled(struct ath_hw
*ah
)
1106 static inline void ath9k_hw_btcoex_enable(struct ath_hw
*ah
)
1109 static inline enum ath_btcoex_scheme
1110 ath9k_hw_get_btcoex_scheme(struct ath_hw
*ah
)
1112 return ATH_BTCOEX_CFG_NONE
;
1114 #endif /* CONFIG_ATH9K_BTCOEX_SUPPORT */
1117 #ifdef CONFIG_PM_SLEEP
1118 const char *ath9k_hw_wow_event_to_string(u32 wow_event
);
1119 void ath9k_hw_wow_apply_pattern(struct ath_hw
*ah
, u8
*user_pattern
,
1120 u8
*user_mask
, int pattern_count
,
1122 u32
ath9k_hw_wow_wakeup(struct ath_hw
*ah
);
1123 void ath9k_hw_wow_enable(struct ath_hw
*ah
, u32 pattern_enable
);
1125 static inline const char *ath9k_hw_wow_event_to_string(u32 wow_event
)
1129 static inline void ath9k_hw_wow_apply_pattern(struct ath_hw
*ah
,
1136 static inline u32
ath9k_hw_wow_wakeup(struct ath_hw
*ah
)
1140 static inline void ath9k_hw_wow_enable(struct ath_hw
*ah
, u32 pattern_enable
)
1147 #define ATH9K_CLOCK_RATE_CCK 22
1148 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
1149 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
1150 #define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44