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ath9k_hw: Add hw cap flag for EDMA for the AR9003 family
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / hw.h
1 /*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #ifndef HW_H
18 #define HW_H
19
20 #include <linux/if_ether.h>
21 #include <linux/delay.h>
22 #include <linux/io.h>
23
24 #include "mac.h"
25 #include "ani.h"
26 #include "eeprom.h"
27 #include "calib.h"
28 #include "reg.h"
29 #include "phy.h"
30 #include "btcoex.h"
31
32 #include "../regd.h"
33 #include "../debug.h"
34
35 #define ATHEROS_VENDOR_ID 0x168c
36
37 #define AR5416_DEVID_PCI 0x0023
38 #define AR5416_DEVID_PCIE 0x0024
39 #define AR9160_DEVID_PCI 0x0027
40 #define AR9280_DEVID_PCI 0x0029
41 #define AR9280_DEVID_PCIE 0x002a
42 #define AR9285_DEVID_PCIE 0x002b
43 #define AR2427_DEVID_PCIE 0x002c
44 #define AR9287_DEVID_PCI 0x002d
45 #define AR9287_DEVID_PCIE 0x002e
46 #define AR9300_DEVID_PCIE 0x0030
47
48 #define AR5416_AR9100_DEVID 0x000b
49
50 #define AR_SUBVENDOR_ID_NOG 0x0e11
51 #define AR_SUBVENDOR_ID_NEW_A 0x7065
52 #define AR5416_MAGIC 0x19641014
53
54 #define AR9280_COEX2WIRE_SUBSYSID 0x309b
55 #define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa
56 #define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab
57
58 #define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1)
59
60 #define ATH_DEFAULT_NOISE_FLOOR -95
61
62 #define ATH9K_RSSI_BAD -128
63
64 /* Register read/write primitives */
65 #define REG_WRITE(_ah, _reg, _val) \
66 ath9k_hw_common(_ah)->ops->write((_ah), (_val), (_reg))
67
68 #define REG_READ(_ah, _reg) \
69 ath9k_hw_common(_ah)->ops->read((_ah), (_reg))
70
71 #define SM(_v, _f) (((_v) << _f##_S) & _f)
72 #define MS(_v, _f) (((_v) & _f) >> _f##_S)
73 #define REG_RMW(_a, _r, _set, _clr) \
74 REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set))
75 #define REG_RMW_FIELD(_a, _r, _f, _v) \
76 REG_WRITE(_a, _r, \
77 (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f))
78 #define REG_SET_BIT(_a, _r, _f) \
79 REG_WRITE(_a, _r, REG_READ(_a, _r) | _f)
80 #define REG_CLR_BIT(_a, _r, _f) \
81 REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f)
82
83 #define DO_DELAY(x) do { \
84 if ((++(x) % 64) == 0) \
85 udelay(1); \
86 } while (0)
87
88 #define REG_WRITE_ARRAY(iniarray, column, regWr) do { \
89 int r; \
90 for (r = 0; r < ((iniarray)->ia_rows); r++) { \
91 REG_WRITE(ah, INI_RA((iniarray), (r), 0), \
92 INI_RA((iniarray), r, (column))); \
93 DO_DELAY(regWr); \
94 } \
95 } while (0)
96
97 #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
98 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
99 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
100 #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3
101 #define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4
102 #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
103 #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
104
105 #define AR_GPIOD_MASK 0x00001FFF
106 #define AR_GPIO_BIT(_gpio) (1 << (_gpio))
107
108 #define BASE_ACTIVATE_DELAY 100
109 #define RTC_PLL_SETTLE_DELAY 100
110 #define COEF_SCALE_S 24
111 #define HT40_CHANNEL_CENTER_SHIFT 10
112
113 #define ATH9K_ANTENNA0_CHAINMASK 0x1
114 #define ATH9K_ANTENNA1_CHAINMASK 0x2
115
116 #define ATH9K_NUM_DMA_DEBUG_REGS 8
117 #define ATH9K_NUM_QUEUES 10
118
119 #define MAX_RATE_POWER 63
120 #define AH_WAIT_TIMEOUT 100000 /* (us) */
121 #define AH_TSF_WRITE_TIMEOUT 100 /* (us) */
122 #define AH_TIME_QUANTUM 10
123 #define AR_KEYTABLE_SIZE 128
124 #define POWER_UP_TIME 10000
125 #define SPUR_RSSI_THRESH 40
126
127 #define CAB_TIMEOUT_VAL 10
128 #define BEACON_TIMEOUT_VAL 10
129 #define MIN_BEACON_TIMEOUT_VAL 1
130 #define SLEEP_SLOP 3
131
132 #define INIT_CONFIG_STATUS 0x00000000
133 #define INIT_RSSI_THR 0x00000700
134 #define INIT_BCON_CNTRL_REG 0x00000000
135
136 #define TU_TO_USEC(_tu) ((_tu) << 10)
137
138 enum wireless_mode {
139 ATH9K_MODE_11A = 0,
140 ATH9K_MODE_11G,
141 ATH9K_MODE_11NA_HT20,
142 ATH9K_MODE_11NG_HT20,
143 ATH9K_MODE_11NA_HT40PLUS,
144 ATH9K_MODE_11NA_HT40MINUS,
145 ATH9K_MODE_11NG_HT40PLUS,
146 ATH9K_MODE_11NG_HT40MINUS,
147 ATH9K_MODE_MAX,
148 };
149
150 enum ath9k_hw_caps {
151 ATH9K_HW_CAP_MIC_AESCCM = BIT(0),
152 ATH9K_HW_CAP_MIC_CKIP = BIT(1),
153 ATH9K_HW_CAP_MIC_TKIP = BIT(2),
154 ATH9K_HW_CAP_CIPHER_AESCCM = BIT(3),
155 ATH9K_HW_CAP_CIPHER_CKIP = BIT(4),
156 ATH9K_HW_CAP_CIPHER_TKIP = BIT(5),
157 ATH9K_HW_CAP_VEOL = BIT(6),
158 ATH9K_HW_CAP_BSSIDMASK = BIT(7),
159 ATH9K_HW_CAP_MCAST_KEYSEARCH = BIT(8),
160 ATH9K_HW_CAP_HT = BIT(9),
161 ATH9K_HW_CAP_GTT = BIT(10),
162 ATH9K_HW_CAP_FASTCC = BIT(11),
163 ATH9K_HW_CAP_RFSILENT = BIT(12),
164 ATH9K_HW_CAP_CST = BIT(13),
165 ATH9K_HW_CAP_ENHANCEDPM = BIT(14),
166 ATH9K_HW_CAP_AUTOSLEEP = BIT(15),
167 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(16),
168 ATH9K_HW_CAP_EDMA = BIT(17),
169 };
170
171 enum ath9k_capability_type {
172 ATH9K_CAP_CIPHER = 0,
173 ATH9K_CAP_TKIP_MIC,
174 ATH9K_CAP_TKIP_SPLIT,
175 ATH9K_CAP_TXPOW,
176 ATH9K_CAP_MCAST_KEYSRCH,
177 ATH9K_CAP_DS
178 };
179
180 struct ath9k_hw_capabilities {
181 u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
182 DECLARE_BITMAP(wireless_modes, ATH9K_MODE_MAX); /* ATH9K_MODE_* */
183 u16 total_queues;
184 u16 keycache_size;
185 u16 low_5ghz_chan, high_5ghz_chan;
186 u16 low_2ghz_chan, high_2ghz_chan;
187 u16 rts_aggr_limit;
188 u8 tx_chainmask;
189 u8 rx_chainmask;
190 u16 tx_triglevel_max;
191 u16 reg_cap;
192 u8 num_gpio_pins;
193 u8 num_antcfg_2ghz;
194 u8 num_antcfg_5ghz;
195 };
196
197 struct ath9k_ops_config {
198 int dma_beacon_response_time;
199 int sw_beacon_response_time;
200 int additional_swba_backoff;
201 int ack_6mb;
202 int cwm_ignore_extcca;
203 u8 pcie_powersave_enable;
204 u8 pcie_clock_req;
205 u32 pcie_waen;
206 u8 analog_shiftreg;
207 u8 ht_enable;
208 u32 ofdm_trig_low;
209 u32 ofdm_trig_high;
210 u32 cck_trig_high;
211 u32 cck_trig_low;
212 u32 enable_ani;
213 int serialize_regmode;
214 bool rx_intr_mitigation;
215 #define SPUR_DISABLE 0
216 #define SPUR_ENABLE_IOCTL 1
217 #define SPUR_ENABLE_EEPROM 2
218 #define AR_EEPROM_MODAL_SPURS 5
219 #define AR_SPUR_5413_1 1640
220 #define AR_SPUR_5413_2 1200
221 #define AR_NO_SPUR 0x8000
222 #define AR_BASE_FREQ_2GHZ 2300
223 #define AR_BASE_FREQ_5GHZ 4900
224 #define AR_SPUR_FEEQ_BOUND_HT40 19
225 #define AR_SPUR_FEEQ_BOUND_HT20 10
226 int spurmode;
227 u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
228 u8 max_txtrig_level;
229 };
230
231 enum ath9k_int {
232 ATH9K_INT_RX = 0x00000001,
233 ATH9K_INT_RXDESC = 0x00000002,
234 ATH9K_INT_RXNOFRM = 0x00000008,
235 ATH9K_INT_RXEOL = 0x00000010,
236 ATH9K_INT_RXORN = 0x00000020,
237 ATH9K_INT_TX = 0x00000040,
238 ATH9K_INT_TXDESC = 0x00000080,
239 ATH9K_INT_TIM_TIMER = 0x00000100,
240 ATH9K_INT_TXURN = 0x00000800,
241 ATH9K_INT_MIB = 0x00001000,
242 ATH9K_INT_RXPHY = 0x00004000,
243 ATH9K_INT_RXKCM = 0x00008000,
244 ATH9K_INT_SWBA = 0x00010000,
245 ATH9K_INT_BMISS = 0x00040000,
246 ATH9K_INT_BNR = 0x00100000,
247 ATH9K_INT_TIM = 0x00200000,
248 ATH9K_INT_DTIM = 0x00400000,
249 ATH9K_INT_DTIMSYNC = 0x00800000,
250 ATH9K_INT_GPIO = 0x01000000,
251 ATH9K_INT_CABEND = 0x02000000,
252 ATH9K_INT_TSFOOR = 0x04000000,
253 ATH9K_INT_GENTIMER = 0x08000000,
254 ATH9K_INT_CST = 0x10000000,
255 ATH9K_INT_GTT = 0x20000000,
256 ATH9K_INT_FATAL = 0x40000000,
257 ATH9K_INT_GLOBAL = 0x80000000,
258 ATH9K_INT_BMISC = ATH9K_INT_TIM |
259 ATH9K_INT_DTIM |
260 ATH9K_INT_DTIMSYNC |
261 ATH9K_INT_TSFOOR |
262 ATH9K_INT_CABEND,
263 ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
264 ATH9K_INT_RXDESC |
265 ATH9K_INT_RXEOL |
266 ATH9K_INT_RXORN |
267 ATH9K_INT_TXURN |
268 ATH9K_INT_TXDESC |
269 ATH9K_INT_MIB |
270 ATH9K_INT_RXPHY |
271 ATH9K_INT_RXKCM |
272 ATH9K_INT_SWBA |
273 ATH9K_INT_BMISS |
274 ATH9K_INT_GPIO,
275 ATH9K_INT_NOCARD = 0xffffffff
276 };
277
278 #define CHANNEL_CW_INT 0x00002
279 #define CHANNEL_CCK 0x00020
280 #define CHANNEL_OFDM 0x00040
281 #define CHANNEL_2GHZ 0x00080
282 #define CHANNEL_5GHZ 0x00100
283 #define CHANNEL_PASSIVE 0x00200
284 #define CHANNEL_DYN 0x00400
285 #define CHANNEL_HALF 0x04000
286 #define CHANNEL_QUARTER 0x08000
287 #define CHANNEL_HT20 0x10000
288 #define CHANNEL_HT40PLUS 0x20000
289 #define CHANNEL_HT40MINUS 0x40000
290
291 #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
292 #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
293 #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
294 #define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20)
295 #define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20)
296 #define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
297 #define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
298 #define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
299 #define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
300 #define CHANNEL_ALL \
301 (CHANNEL_OFDM| \
302 CHANNEL_CCK| \
303 CHANNEL_2GHZ | \
304 CHANNEL_5GHZ | \
305 CHANNEL_HT20 | \
306 CHANNEL_HT40PLUS | \
307 CHANNEL_HT40MINUS)
308
309 struct ath9k_channel {
310 struct ieee80211_channel *chan;
311 u16 channel;
312 u32 channelFlags;
313 u32 chanmode;
314 int32_t CalValid;
315 bool oneTimeCalsDone;
316 int8_t iCoff;
317 int8_t qCoff;
318 int16_t rawNoiseFloor;
319 };
320
321 #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
322 (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
323 (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
324 (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
325 #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
326 #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
327 #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
328 #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
329 #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
330 #define IS_CHAN_A_5MHZ_SPACED(_c) \
331 ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \
332 (((_c)->channel % 20) != 0) && \
333 (((_c)->channel % 10) != 0))
334
335 /* These macros check chanmode and not channelFlags */
336 #define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B)
337 #define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \
338 ((_c)->chanmode == CHANNEL_G_HT20))
339 #define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \
340 ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \
341 ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \
342 ((_c)->chanmode == CHANNEL_G_HT40MINUS))
343 #define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
344
345 enum ath9k_power_mode {
346 ATH9K_PM_AWAKE = 0,
347 ATH9K_PM_FULL_SLEEP,
348 ATH9K_PM_NETWORK_SLEEP,
349 ATH9K_PM_UNDEFINED
350 };
351
352 enum ath9k_tp_scale {
353 ATH9K_TP_SCALE_MAX = 0,
354 ATH9K_TP_SCALE_50,
355 ATH9K_TP_SCALE_25,
356 ATH9K_TP_SCALE_12,
357 ATH9K_TP_SCALE_MIN
358 };
359
360 enum ser_reg_mode {
361 SER_REG_MODE_OFF = 0,
362 SER_REG_MODE_ON = 1,
363 SER_REG_MODE_AUTO = 2,
364 };
365
366 struct ath9k_beacon_state {
367 u32 bs_nexttbtt;
368 u32 bs_nextdtim;
369 u32 bs_intval;
370 #define ATH9K_BEACON_PERIOD 0x0000ffff
371 #define ATH9K_BEACON_ENA 0x00800000
372 #define ATH9K_BEACON_RESET_TSF 0x01000000
373 #define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */
374 u32 bs_dtimperiod;
375 u16 bs_cfpperiod;
376 u16 bs_cfpmaxduration;
377 u32 bs_cfpnext;
378 u16 bs_timoffset;
379 u16 bs_bmissthreshold;
380 u32 bs_sleepduration;
381 u32 bs_tsfoor_threshold;
382 };
383
384 struct chan_centers {
385 u16 synth_center;
386 u16 ctl_center;
387 u16 ext_center;
388 };
389
390 enum {
391 ATH9K_RESET_POWER_ON,
392 ATH9K_RESET_WARM,
393 ATH9K_RESET_COLD,
394 };
395
396 struct ath9k_hw_version {
397 u32 magic;
398 u16 devid;
399 u16 subvendorid;
400 u32 macVersion;
401 u16 macRev;
402 u16 phyRev;
403 u16 analog5GhzRev;
404 u16 analog2GhzRev;
405 u16 subsysid;
406 };
407
408 /* Generic TSF timer definitions */
409
410 #define ATH_MAX_GEN_TIMER 16
411
412 #define AR_GENTMR_BIT(_index) (1 << (_index))
413
414 /*
415 * Using de Bruijin sequence to to look up 1's index in a 32 bit number
416 * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001
417 */
418 #define debruijn32 0x077CB531U
419
420 struct ath_gen_timer_configuration {
421 u32 next_addr;
422 u32 period_addr;
423 u32 mode_addr;
424 u32 mode_mask;
425 };
426
427 struct ath_gen_timer {
428 void (*trigger)(void *arg);
429 void (*overflow)(void *arg);
430 void *arg;
431 u8 index;
432 };
433
434 struct ath_gen_timer_table {
435 u32 gen_timer_index[32];
436 struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER];
437 union {
438 unsigned long timer_bits;
439 u16 val;
440 } timer_mask;
441 };
442
443 /**
444 * struct ath_hw_private_ops - callbacks used internally by hardware code
445 *
446 * This structure contains private callbacks designed to only be used internally
447 * by the hardware core.
448 *
449 * @init_cal_settings: Initializes calibration settings
450 * @init_mode_regs: Initializes mode registers
451 * @macversion_supported: If this specific mac revision is supported
452 *
453 * @rf_set_freq: change frequency
454 * @spur_mitigate_freq: spur mitigation
455 * @rf_alloc_ext_banks:
456 * @rf_free_ext_banks:
457 * @set_rf_regs:
458 * @compute_pll_control: compute the PLL control value to use for
459 * AR_RTC_PLL_CONTROL for a given channel
460 */
461 struct ath_hw_private_ops {
462 void (*init_cal_settings)(struct ath_hw *ah);
463 void (*init_mode_regs)(struct ath_hw *ah);
464 bool (*macversion_supported)(u32 macversion);
465
466 /* PHY ops */
467 int (*rf_set_freq)(struct ath_hw *ah,
468 struct ath9k_channel *chan);
469 void (*spur_mitigate_freq)(struct ath_hw *ah,
470 struct ath9k_channel *chan);
471 int (*rf_alloc_ext_banks)(struct ath_hw *ah);
472 void (*rf_free_ext_banks)(struct ath_hw *ah);
473 bool (*set_rf_regs)(struct ath_hw *ah,
474 struct ath9k_channel *chan,
475 u16 modesIndex);
476 void (*set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan);
477 void (*init_bb)(struct ath_hw *ah,
478 struct ath9k_channel *chan);
479 int (*process_ini)(struct ath_hw *ah, struct ath9k_channel *chan);
480 void (*olc_init)(struct ath_hw *ah);
481 void (*set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan);
482 void (*mark_phy_inactive)(struct ath_hw *ah);
483 void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan);
484 bool (*rfbus_req)(struct ath_hw *ah);
485 void (*rfbus_done)(struct ath_hw *ah);
486 void (*enable_rfkill)(struct ath_hw *ah);
487 void (*restore_chainmask)(struct ath_hw *ah);
488 void (*set_diversity)(struct ath_hw *ah, bool value);
489 u32 (*compute_pll_control)(struct ath_hw *ah,
490 struct ath9k_channel *chan);
491 };
492
493 /**
494 * struct ath_hw_ops - callbacks used by hardware code and driver code
495 *
496 * This structure contains callbacks designed to to be used internally by
497 * hardware code and also by the lower level driver.
498 *
499 * @config_pci_powersave:
500 */
501 struct ath_hw_ops {
502 void (*config_pci_powersave)(struct ath_hw *ah,
503 int restore,
504 int power_off);
505 };
506
507 struct ath_hw {
508 struct ieee80211_hw *hw;
509 struct ath_common common;
510 struct ath9k_hw_version hw_version;
511 struct ath9k_ops_config config;
512 struct ath9k_hw_capabilities caps;
513 struct ath9k_channel channels[38];
514 struct ath9k_channel *curchan;
515
516 union {
517 struct ar5416_eeprom_def def;
518 struct ar5416_eeprom_4k map4k;
519 struct ar9287_eeprom map9287;
520 } eeprom;
521 const struct eeprom_ops *eep_ops;
522 enum ath9k_eep_map eep_map;
523
524 bool sw_mgmt_crypto;
525 bool is_pciexpress;
526 bool need_an_top2_fixup;
527 u16 tx_trig_level;
528 u16 rfsilent;
529 u32 rfkill_gpio;
530 u32 rfkill_polarity;
531 u32 ah_flags;
532
533 bool htc_reset_init;
534
535 enum nl80211_iftype opmode;
536 enum ath9k_power_mode power_mode;
537
538 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
539 struct ath9k_pacal_info pacal_info;
540 struct ar5416Stats stats;
541 struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES];
542
543 int16_t curchan_rad_index;
544 enum ath9k_int imask;
545 u32 imrs2_reg;
546 u32 txok_interrupt_mask;
547 u32 txerr_interrupt_mask;
548 u32 txdesc_interrupt_mask;
549 u32 txeol_interrupt_mask;
550 u32 txurn_interrupt_mask;
551 bool chip_fullsleep;
552 u32 atim_window;
553
554 /* Calibration */
555 enum ath9k_cal_types supp_cals;
556 struct ath9k_cal_list iq_caldata;
557 struct ath9k_cal_list adcgain_caldata;
558 struct ath9k_cal_list adcdc_calinitdata;
559 struct ath9k_cal_list adcdc_caldata;
560 struct ath9k_cal_list *cal_list;
561 struct ath9k_cal_list *cal_list_last;
562 struct ath9k_cal_list *cal_list_curr;
563 #define totalPowerMeasI meas0.unsign
564 #define totalPowerMeasQ meas1.unsign
565 #define totalIqCorrMeas meas2.sign
566 #define totalAdcIOddPhase meas0.unsign
567 #define totalAdcIEvenPhase meas1.unsign
568 #define totalAdcQOddPhase meas2.unsign
569 #define totalAdcQEvenPhase meas3.unsign
570 #define totalAdcDcOffsetIOddPhase meas0.sign
571 #define totalAdcDcOffsetIEvenPhase meas1.sign
572 #define totalAdcDcOffsetQOddPhase meas2.sign
573 #define totalAdcDcOffsetQEvenPhase meas3.sign
574 union {
575 u32 unsign[AR5416_MAX_CHAINS];
576 int32_t sign[AR5416_MAX_CHAINS];
577 } meas0;
578 union {
579 u32 unsign[AR5416_MAX_CHAINS];
580 int32_t sign[AR5416_MAX_CHAINS];
581 } meas1;
582 union {
583 u32 unsign[AR5416_MAX_CHAINS];
584 int32_t sign[AR5416_MAX_CHAINS];
585 } meas2;
586 union {
587 u32 unsign[AR5416_MAX_CHAINS];
588 int32_t sign[AR5416_MAX_CHAINS];
589 } meas3;
590 u16 cal_samples;
591
592 u32 sta_id1_defaults;
593 u32 misc_mode;
594 enum {
595 AUTO_32KHZ,
596 USE_32KHZ,
597 DONT_USE_32KHZ,
598 } enable_32kHz_clock;
599
600 /* Private to hardware code */
601 struct ath_hw_private_ops private_ops;
602 /* Accessed by the lower level driver */
603 struct ath_hw_ops ops;
604
605 /* Used to program the radio on non single-chip devices */
606 u32 *analogBank0Data;
607 u32 *analogBank1Data;
608 u32 *analogBank2Data;
609 u32 *analogBank3Data;
610 u32 *analogBank6Data;
611 u32 *analogBank6TPCData;
612 u32 *analogBank7Data;
613 u32 *addac5416_21;
614 u32 *bank6Temp;
615
616 int16_t txpower_indexoffset;
617 int coverage_class;
618 u32 beacon_interval;
619 u32 slottime;
620 u32 globaltxtimeout;
621
622 /* ANI */
623 u32 proc_phyerr;
624 u32 aniperiod;
625 struct ar5416AniState *curani;
626 struct ar5416AniState ani[255];
627 int totalSizeDesired[5];
628 int coarse_high[5];
629 int coarse_low[5];
630 int firpwr[5];
631 enum ath9k_ani_cmd ani_function;
632
633 /* Bluetooth coexistance */
634 struct ath_btcoex_hw btcoex_hw;
635
636 u32 intr_txqs;
637 u8 txchainmask;
638 u8 rxchainmask;
639
640 u32 originalGain[22];
641 int initPDADC;
642 int PDADCdelta;
643 u8 led_pin;
644
645 struct ar5416IniArray iniModes;
646 struct ar5416IniArray iniCommon;
647 struct ar5416IniArray iniBank0;
648 struct ar5416IniArray iniBB_RfGain;
649 struct ar5416IniArray iniBank1;
650 struct ar5416IniArray iniBank2;
651 struct ar5416IniArray iniBank3;
652 struct ar5416IniArray iniBank6;
653 struct ar5416IniArray iniBank6TPC;
654 struct ar5416IniArray iniBank7;
655 struct ar5416IniArray iniAddac;
656 struct ar5416IniArray iniPcieSerdes;
657 struct ar5416IniArray iniModesAdditional;
658 struct ar5416IniArray iniModesRxGain;
659 struct ar5416IniArray iniModesTxGain;
660 struct ar5416IniArray iniModes_9271_1_0_only;
661 struct ar5416IniArray iniCckfirNormal;
662 struct ar5416IniArray iniCckfirJapan2484;
663 struct ar5416IniArray iniCommon_normal_cck_fir_coeff_9271;
664 struct ar5416IniArray iniCommon_japan_2484_cck_fir_coeff_9271;
665 struct ar5416IniArray iniModes_9271_ANI_reg;
666 struct ar5416IniArray iniModes_high_power_tx_gain_9271;
667 struct ar5416IniArray iniModes_normal_power_tx_gain_9271;
668
669 u32 intr_gen_timer_trigger;
670 u32 intr_gen_timer_thresh;
671 struct ath_gen_timer_table hw_gen_timers;
672 };
673
674 static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
675 {
676 return &ah->common;
677 }
678
679 static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah)
680 {
681 return &(ath9k_hw_common(ah)->regulatory);
682 }
683
684 static inline struct ath_hw_private_ops *ath9k_hw_private_ops(struct ath_hw *ah)
685 {
686 return &ah->private_ops;
687 }
688
689 static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah)
690 {
691 return &ah->ops;
692 }
693
694 /* Initialization, Detach, Reset */
695 const char *ath9k_hw_probe(u16 vendorid, u16 devid);
696 void ath9k_hw_deinit(struct ath_hw *ah);
697 int ath9k_hw_init(struct ath_hw *ah);
698 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
699 bool bChannelChange);
700 int ath9k_hw_fill_cap_info(struct ath_hw *ah);
701 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
702 u32 capability, u32 *result);
703 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
704 u32 capability, u32 setting, int *status);
705 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan);
706
707 /* Key Cache Management */
708 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry);
709 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac);
710 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
711 const struct ath9k_keyval *k,
712 const u8 *mac);
713 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry);
714
715 /* GPIO / RFKILL / Antennae */
716 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio);
717 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio);
718 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
719 u32 ah_signal_type);
720 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val);
721 u32 ath9k_hw_getdefantenna(struct ath_hw *ah);
722 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna);
723
724 /* General Operation */
725 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout);
726 u32 ath9k_hw_reverse_bits(u32 val, u32 n);
727 bool ath9k_get_channel_edges(struct ath_hw *ah, u16 flags, u16 *low, u16 *high);
728 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
729 u8 phy, int kbps,
730 u32 frameLen, u16 rateix, bool shortPreamble);
731 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
732 struct ath9k_channel *chan,
733 struct chan_centers *centers);
734 u32 ath9k_hw_getrxfilter(struct ath_hw *ah);
735 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits);
736 bool ath9k_hw_phy_disable(struct ath_hw *ah);
737 bool ath9k_hw_disable(struct ath_hw *ah);
738 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit);
739 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac);
740 void ath9k_hw_setopmode(struct ath_hw *ah);
741 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1);
742 void ath9k_hw_setbssidmask(struct ath_hw *ah);
743 void ath9k_hw_write_associd(struct ath_hw *ah);
744 u64 ath9k_hw_gettsf64(struct ath_hw *ah);
745 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64);
746 void ath9k_hw_reset_tsf(struct ath_hw *ah);
747 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting);
748 u64 ath9k_hw_extend_tsf(struct ath_hw *ah, u32 rstamp);
749 void ath9k_hw_init_global_settings(struct ath_hw *ah);
750 void ath9k_hw_set11nmac2040(struct ath_hw *ah);
751 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period);
752 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
753 const struct ath9k_beacon_state *bs);
754
755 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode);
756
757 /* Interrupt Handling */
758 bool ath9k_hw_intrpend(struct ath_hw *ah);
759 bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked);
760 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints);
761
762 /* Generic hw timer primitives */
763 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
764 void (*trigger)(void *),
765 void (*overflow)(void *),
766 void *arg,
767 u8 timer_index);
768 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
769 struct ath_gen_timer *timer,
770 u32 timer_next,
771 u32 timer_period);
772 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer);
773
774 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer);
775 void ath_gen_timer_isr(struct ath_hw *hw);
776 u32 ath9k_hw_gettsf32(struct ath_hw *ah);
777
778 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len);
779
780 /* HTC */
781 void ath9k_hw_htc_resetinit(struct ath_hw *ah);
782
783 /* PHY */
784 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
785 u32 *coef_mantissa, u32 *coef_exponent);
786
787 void ar5008_hw_attach_phy_ops(struct ath_hw *ah);
788 void ar9002_hw_attach_phy_ops(struct ath_hw *ah);
789 void ar9003_hw_attach_phy_ops(struct ath_hw *ah);
790
791 #define ATH_PCIE_CAP_LINK_CTRL 0x70
792 #define ATH_PCIE_CAP_LINK_L0S 1
793 #define ATH_PCIE_CAP_LINK_L1 2
794
795 #endif
Linux kernel - Deliverables
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