2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include <linux/if_ether.h>
21 #include <linux/delay.h>
35 #define ATHEROS_VENDOR_ID 0x168c
37 #define AR5416_DEVID_PCI 0x0023
38 #define AR5416_DEVID_PCIE 0x0024
39 #define AR9160_DEVID_PCI 0x0027
40 #define AR9280_DEVID_PCI 0x0029
41 #define AR9280_DEVID_PCIE 0x002a
42 #define AR9285_DEVID_PCIE 0x002b
43 #define AR2427_DEVID_PCIE 0x002c
45 #define AR5416_AR9100_DEVID 0x000b
47 #define AR9271_USB 0x9271
49 #define AR_SUBVENDOR_ID_NOG 0x0e11
50 #define AR_SUBVENDOR_ID_NEW_A 0x7065
51 #define AR5416_MAGIC 0x19641014
53 #define AR5416_DEVID_AR9287_PCI 0x002D
54 #define AR5416_DEVID_AR9287_PCIE 0x002E
56 #define AR9280_COEX2WIRE_SUBSYSID 0x309b
57 #define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa
58 #define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab
60 #define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1)
62 #define ATH_DEFAULT_NOISE_FLOOR -95
64 #define ATH9K_RSSI_BAD -128
66 /* Register read/write primitives */
67 #define REG_WRITE(_ah, _reg, _val) \
68 ath9k_hw_common(_ah)->ops->write((_ah), (_val), (_reg))
70 #define REG_READ(_ah, _reg) \
71 ath9k_hw_common(_ah)->ops->read((_ah), (_reg))
73 #define SM(_v, _f) (((_v) << _f##_S) & _f)
74 #define MS(_v, _f) (((_v) & _f) >> _f##_S)
75 #define REG_RMW(_a, _r, _set, _clr) \
76 REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set))
77 #define REG_RMW_FIELD(_a, _r, _f, _v) \
79 (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f))
80 #define REG_SET_BIT(_a, _r, _f) \
81 REG_WRITE(_a, _r, REG_READ(_a, _r) | _f)
82 #define REG_CLR_BIT(_a, _r, _f) \
83 REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f)
85 #define DO_DELAY(x) do { \
86 if ((++(x) % 64) == 0) \
90 #define REG_WRITE_ARRAY(iniarray, column, regWr) do { \
92 for (r = 0; r < ((iniarray)->ia_rows); r++) { \
93 REG_WRITE(ah, INI_RA((iniarray), (r), 0), \
94 INI_RA((iniarray), r, (column))); \
99 #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
100 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
101 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
102 #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3
103 #define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4
104 #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
105 #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
107 #define AR_GPIOD_MASK 0x00001FFF
108 #define AR_GPIO_BIT(_gpio) (1 << (_gpio))
110 #define BASE_ACTIVATE_DELAY 100
111 #define RTC_PLL_SETTLE_DELAY 100
112 #define COEF_SCALE_S 24
113 #define HT40_CHANNEL_CENTER_SHIFT 10
115 #define ATH9K_ANTENNA0_CHAINMASK 0x1
116 #define ATH9K_ANTENNA1_CHAINMASK 0x2
118 #define ATH9K_NUM_DMA_DEBUG_REGS 8
119 #define ATH9K_NUM_QUEUES 10
121 #define MAX_RATE_POWER 63
122 #define AH_WAIT_TIMEOUT 100000 /* (us) */
123 #define AH_TSF_WRITE_TIMEOUT 100 /* (us) */
124 #define AH_TIME_QUANTUM 10
125 #define AR_KEYTABLE_SIZE 128
126 #define POWER_UP_TIME 10000
127 #define SPUR_RSSI_THRESH 40
129 #define CAB_TIMEOUT_VAL 10
130 #define BEACON_TIMEOUT_VAL 10
131 #define MIN_BEACON_TIMEOUT_VAL 1
134 #define INIT_CONFIG_STATUS 0x00000000
135 #define INIT_RSSI_THR 0x00000700
136 #define INIT_BCON_CNTRL_REG 0x00000000
138 #define TU_TO_USEC(_tu) ((_tu) << 10)
143 ATH9K_MODE_11NA_HT20
,
144 ATH9K_MODE_11NG_HT20
,
145 ATH9K_MODE_11NA_HT40PLUS
,
146 ATH9K_MODE_11NA_HT40MINUS
,
147 ATH9K_MODE_11NG_HT40PLUS
,
148 ATH9K_MODE_11NG_HT40MINUS
,
153 ATH9K_HW_CAP_MIC_AESCCM
= BIT(0),
154 ATH9K_HW_CAP_MIC_CKIP
= BIT(1),
155 ATH9K_HW_CAP_MIC_TKIP
= BIT(2),
156 ATH9K_HW_CAP_CIPHER_AESCCM
= BIT(3),
157 ATH9K_HW_CAP_CIPHER_CKIP
= BIT(4),
158 ATH9K_HW_CAP_CIPHER_TKIP
= BIT(5),
159 ATH9K_HW_CAP_VEOL
= BIT(6),
160 ATH9K_HW_CAP_BSSIDMASK
= BIT(7),
161 ATH9K_HW_CAP_MCAST_KEYSEARCH
= BIT(8),
162 ATH9K_HW_CAP_HT
= BIT(9),
163 ATH9K_HW_CAP_GTT
= BIT(10),
164 ATH9K_HW_CAP_FASTCC
= BIT(11),
165 ATH9K_HW_CAP_RFSILENT
= BIT(12),
166 ATH9K_HW_CAP_CST
= BIT(13),
167 ATH9K_HW_CAP_ENHANCEDPM
= BIT(14),
168 ATH9K_HW_CAP_AUTOSLEEP
= BIT(15),
169 ATH9K_HW_CAP_4KB_SPLITTRANS
= BIT(16),
172 enum ath9k_capability_type
{
173 ATH9K_CAP_CIPHER
= 0,
175 ATH9K_CAP_TKIP_SPLIT
,
178 ATH9K_CAP_MCAST_KEYSRCH
,
182 struct ath9k_hw_capabilities
{
183 u32 hw_caps
; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
184 DECLARE_BITMAP(wireless_modes
, ATH9K_MODE_MAX
); /* ATH9K_MODE_* */
187 u16 low_5ghz_chan
, high_5ghz_chan
;
188 u16 low_2ghz_chan
, high_2ghz_chan
;
192 u16 tx_triglevel_max
;
199 struct ath9k_ops_config
{
200 int dma_beacon_response_time
;
201 int sw_beacon_response_time
;
202 int additional_swba_backoff
;
204 int cwm_ignore_extcca
;
205 u8 pcie_powersave_enable
;
215 int serialize_regmode
;
216 bool rx_intr_mitigation
;
217 #define SPUR_DISABLE 0
218 #define SPUR_ENABLE_IOCTL 1
219 #define SPUR_ENABLE_EEPROM 2
220 #define AR_EEPROM_MODAL_SPURS 5
221 #define AR_SPUR_5413_1 1640
222 #define AR_SPUR_5413_2 1200
223 #define AR_NO_SPUR 0x8000
224 #define AR_BASE_FREQ_2GHZ 2300
225 #define AR_BASE_FREQ_5GHZ 4900
226 #define AR_SPUR_FEEQ_BOUND_HT40 19
227 #define AR_SPUR_FEEQ_BOUND_HT20 10
229 u16 spurchans
[AR_EEPROM_MODAL_SPURS
][2];
234 ATH9K_INT_RX
= 0x00000001,
235 ATH9K_INT_RXDESC
= 0x00000002,
236 ATH9K_INT_RXNOFRM
= 0x00000008,
237 ATH9K_INT_RXEOL
= 0x00000010,
238 ATH9K_INT_RXORN
= 0x00000020,
239 ATH9K_INT_TX
= 0x00000040,
240 ATH9K_INT_TXDESC
= 0x00000080,
241 ATH9K_INT_TIM_TIMER
= 0x00000100,
242 ATH9K_INT_TXURN
= 0x00000800,
243 ATH9K_INT_MIB
= 0x00001000,
244 ATH9K_INT_RXPHY
= 0x00004000,
245 ATH9K_INT_RXKCM
= 0x00008000,
246 ATH9K_INT_SWBA
= 0x00010000,
247 ATH9K_INT_BMISS
= 0x00040000,
248 ATH9K_INT_BNR
= 0x00100000,
249 ATH9K_INT_TIM
= 0x00200000,
250 ATH9K_INT_DTIM
= 0x00400000,
251 ATH9K_INT_DTIMSYNC
= 0x00800000,
252 ATH9K_INT_GPIO
= 0x01000000,
253 ATH9K_INT_CABEND
= 0x02000000,
254 ATH9K_INT_TSFOOR
= 0x04000000,
255 ATH9K_INT_GENTIMER
= 0x08000000,
256 ATH9K_INT_CST
= 0x10000000,
257 ATH9K_INT_GTT
= 0x20000000,
258 ATH9K_INT_FATAL
= 0x40000000,
259 ATH9K_INT_GLOBAL
= 0x80000000,
260 ATH9K_INT_BMISC
= ATH9K_INT_TIM
|
265 ATH9K_INT_COMMON
= ATH9K_INT_RXNOFRM
|
277 ATH9K_INT_NOCARD
= 0xffffffff
280 #define CHANNEL_CW_INT 0x00002
281 #define CHANNEL_CCK 0x00020
282 #define CHANNEL_OFDM 0x00040
283 #define CHANNEL_2GHZ 0x00080
284 #define CHANNEL_5GHZ 0x00100
285 #define CHANNEL_PASSIVE 0x00200
286 #define CHANNEL_DYN 0x00400
287 #define CHANNEL_HALF 0x04000
288 #define CHANNEL_QUARTER 0x08000
289 #define CHANNEL_HT20 0x10000
290 #define CHANNEL_HT40PLUS 0x20000
291 #define CHANNEL_HT40MINUS 0x40000
293 #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
294 #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
295 #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
296 #define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20)
297 #define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20)
298 #define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
299 #define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
300 #define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
301 #define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
302 #define CHANNEL_ALL \
311 struct ath9k_channel
{
312 struct ieee80211_channel
*chan
;
317 bool oneTimeCalsDone
;
320 int16_t rawNoiseFloor
;
323 #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
324 (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
325 (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
326 (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
327 #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
328 #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
329 #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
330 #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
331 #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
332 #define IS_CHAN_A_5MHZ_SPACED(_c) \
333 ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \
334 (((_c)->channel % 20) != 0) && \
335 (((_c)->channel % 10) != 0))
337 /* These macros check chanmode and not channelFlags */
338 #define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B)
339 #define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \
340 ((_c)->chanmode == CHANNEL_G_HT20))
341 #define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \
342 ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \
343 ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \
344 ((_c)->chanmode == CHANNEL_G_HT40MINUS))
345 #define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
347 enum ath9k_power_mode
{
350 ATH9K_PM_NETWORK_SLEEP
,
354 enum ath9k_tp_scale
{
355 ATH9K_TP_SCALE_MAX
= 0,
363 SER_REG_MODE_OFF
= 0,
365 SER_REG_MODE_AUTO
= 2,
368 struct ath9k_beacon_state
{
372 #define ATH9K_BEACON_PERIOD 0x0000ffff
373 #define ATH9K_BEACON_ENA 0x00800000
374 #define ATH9K_BEACON_RESET_TSF 0x01000000
375 #define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */
378 u16 bs_cfpmaxduration
;
381 u16 bs_bmissthreshold
;
382 u32 bs_sleepduration
;
383 u32 bs_tsfoor_threshold
;
386 struct chan_centers
{
393 ATH9K_RESET_POWER_ON
,
398 struct ath9k_hw_version
{
410 /* Generic TSF timer definitions */
412 #define ATH_MAX_GEN_TIMER 16
414 #define AR_GENTMR_BIT(_index) (1 << (_index))
417 * Using de Bruijin sequence to to look up 1's index in a 32 bit number
418 * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001
420 #define debruijn32 0x077CB531U
422 struct ath_gen_timer_configuration
{
429 struct ath_gen_timer
{
430 void (*trigger
)(void *arg
);
431 void (*overflow
)(void *arg
);
436 struct ath_gen_timer_table
{
437 u32 gen_timer_index
[32];
438 struct ath_gen_timer
*timers
[ATH_MAX_GEN_TIMER
];
440 unsigned long timer_bits
;
446 struct ieee80211_hw
*hw
;
447 struct ath_common common
;
448 struct ath9k_hw_version hw_version
;
449 struct ath9k_ops_config config
;
450 struct ath9k_hw_capabilities caps
;
451 struct ath9k_channel channels
[38];
452 struct ath9k_channel
*curchan
;
455 struct ar5416_eeprom_def def
;
456 struct ar5416_eeprom_4k map4k
;
457 struct ar9287_eeprom map9287
;
459 const struct eeprom_ops
*eep_ops
;
460 enum ath9k_eep_map eep_map
;
472 enum nl80211_iftype opmode
;
473 enum ath9k_power_mode power_mode
;
475 struct ath9k_nfcal_hist nfCalHist
[NUM_NF_READINGS
];
476 struct ath9k_pacal_info pacal_info
;
477 struct ar5416Stats stats
;
478 struct ath9k_tx_queue_info txq
[ATH9K_NUM_TX_QUEUES
];
480 int16_t curchan_rad_index
;
482 u32 txok_interrupt_mask
;
483 u32 txerr_interrupt_mask
;
484 u32 txdesc_interrupt_mask
;
485 u32 txeol_interrupt_mask
;
486 u32 txurn_interrupt_mask
;
491 enum ath9k_cal_types supp_cals
;
492 struct ath9k_cal_list iq_caldata
;
493 struct ath9k_cal_list adcgain_caldata
;
494 struct ath9k_cal_list adcdc_calinitdata
;
495 struct ath9k_cal_list adcdc_caldata
;
496 struct ath9k_cal_list
*cal_list
;
497 struct ath9k_cal_list
*cal_list_last
;
498 struct ath9k_cal_list
*cal_list_curr
;
499 #define totalPowerMeasI meas0.unsign
500 #define totalPowerMeasQ meas1.unsign
501 #define totalIqCorrMeas meas2.sign
502 #define totalAdcIOddPhase meas0.unsign
503 #define totalAdcIEvenPhase meas1.unsign
504 #define totalAdcQOddPhase meas2.unsign
505 #define totalAdcQEvenPhase meas3.unsign
506 #define totalAdcDcOffsetIOddPhase meas0.sign
507 #define totalAdcDcOffsetIEvenPhase meas1.sign
508 #define totalAdcDcOffsetQOddPhase meas2.sign
509 #define totalAdcDcOffsetQEvenPhase meas3.sign
511 u32 unsign
[AR5416_MAX_CHAINS
];
512 int32_t sign
[AR5416_MAX_CHAINS
];
515 u32 unsign
[AR5416_MAX_CHAINS
];
516 int32_t sign
[AR5416_MAX_CHAINS
];
519 u32 unsign
[AR5416_MAX_CHAINS
];
520 int32_t sign
[AR5416_MAX_CHAINS
];
523 u32 unsign
[AR5416_MAX_CHAINS
];
524 int32_t sign
[AR5416_MAX_CHAINS
];
528 u32 sta_id1_defaults
;
534 } enable_32kHz_clock
;
536 /* Callback for radio frequency change */
537 int (*ath9k_hw_rf_set_freq
)(struct ath_hw
*ah
, struct ath9k_channel
*chan
);
539 /* Callback for baseband spur frequency */
540 void (*ath9k_hw_spur_mitigate_freq
)(struct ath_hw
*ah
,
541 struct ath9k_channel
*chan
);
543 /* Used to program the radio on non single-chip devices */
544 u32
*analogBank0Data
;
545 u32
*analogBank1Data
;
546 u32
*analogBank2Data
;
547 u32
*analogBank3Data
;
548 u32
*analogBank6Data
;
549 u32
*analogBank6TPCData
;
550 u32
*analogBank7Data
;
554 int16_t txpower_indexoffset
;
563 struct ar5416AniState
*curani
;
564 struct ar5416AniState ani
[255];
565 int totalSizeDesired
[5];
569 enum ath9k_ani_cmd ani_function
;
571 /* Bluetooth coexistance */
572 struct ath_btcoex_hw btcoex_hw
;
578 u32 originalGain
[22];
583 struct ar5416IniArray iniModes
;
584 struct ar5416IniArray iniCommon
;
585 struct ar5416IniArray iniBank0
;
586 struct ar5416IniArray iniBB_RfGain
;
587 struct ar5416IniArray iniBank1
;
588 struct ar5416IniArray iniBank2
;
589 struct ar5416IniArray iniBank3
;
590 struct ar5416IniArray iniBank6
;
591 struct ar5416IniArray iniBank6TPC
;
592 struct ar5416IniArray iniBank7
;
593 struct ar5416IniArray iniAddac
;
594 struct ar5416IniArray iniPcieSerdes
;
595 struct ar5416IniArray iniModesAdditional
;
596 struct ar5416IniArray iniModesRxGain
;
597 struct ar5416IniArray iniModesTxGain
;
598 struct ar5416IniArray iniModes_9271_1_0_only
;
599 struct ar5416IniArray iniCckfirNormal
;
600 struct ar5416IniArray iniCckfirJapan2484
;
602 u32 intr_gen_timer_trigger
;
603 u32 intr_gen_timer_thresh
;
604 struct ath_gen_timer_table hw_gen_timers
;
607 static inline struct ath_common
*ath9k_hw_common(struct ath_hw
*ah
)
612 static inline struct ath_regulatory
*ath9k_hw_regulatory(struct ath_hw
*ah
)
614 return &(ath9k_hw_common(ah
)->regulatory
);
617 /* Initialization, Detach, Reset */
618 const char *ath9k_hw_probe(u16 vendorid
, u16 devid
);
619 void ath9k_hw_deinit(struct ath_hw
*ah
);
620 int ath9k_hw_init(struct ath_hw
*ah
);
621 int ath9k_hw_reset(struct ath_hw
*ah
, struct ath9k_channel
*chan
,
622 bool bChannelChange
);
623 int ath9k_hw_fill_cap_info(struct ath_hw
*ah
);
624 bool ath9k_hw_getcapability(struct ath_hw
*ah
, enum ath9k_capability_type type
,
625 u32 capability
, u32
*result
);
626 bool ath9k_hw_setcapability(struct ath_hw
*ah
, enum ath9k_capability_type type
,
627 u32 capability
, u32 setting
, int *status
);
629 /* Key Cache Management */
630 bool ath9k_hw_keyreset(struct ath_hw
*ah
, u16 entry
);
631 bool ath9k_hw_keysetmac(struct ath_hw
*ah
, u16 entry
, const u8
*mac
);
632 bool ath9k_hw_set_keycache_entry(struct ath_hw
*ah
, u16 entry
,
633 const struct ath9k_keyval
*k
,
635 bool ath9k_hw_keyisvalid(struct ath_hw
*ah
, u16 entry
);
637 /* GPIO / RFKILL / Antennae */
638 void ath9k_hw_cfg_gpio_input(struct ath_hw
*ah
, u32 gpio
);
639 u32
ath9k_hw_gpio_get(struct ath_hw
*ah
, u32 gpio
);
640 void ath9k_hw_cfg_output(struct ath_hw
*ah
, u32 gpio
,
642 void ath9k_hw_set_gpio(struct ath_hw
*ah
, u32 gpio
, u32 val
);
643 u32
ath9k_hw_getdefantenna(struct ath_hw
*ah
);
644 void ath9k_hw_setantenna(struct ath_hw
*ah
, u32 antenna
);
646 /* General Operation */
647 bool ath9k_hw_wait(struct ath_hw
*ah
, u32 reg
, u32 mask
, u32 val
, u32 timeout
);
648 u32
ath9k_hw_reverse_bits(u32 val
, u32 n
);
649 bool ath9k_get_channel_edges(struct ath_hw
*ah
, u16 flags
, u16
*low
, u16
*high
);
650 u16
ath9k_hw_computetxtime(struct ath_hw
*ah
,
652 u32 frameLen
, u16 rateix
, bool shortPreamble
);
653 void ath9k_hw_get_channel_centers(struct ath_hw
*ah
,
654 struct ath9k_channel
*chan
,
655 struct chan_centers
*centers
);
656 u32
ath9k_hw_getrxfilter(struct ath_hw
*ah
);
657 void ath9k_hw_setrxfilter(struct ath_hw
*ah
, u32 bits
);
658 bool ath9k_hw_phy_disable(struct ath_hw
*ah
);
659 bool ath9k_hw_disable(struct ath_hw
*ah
);
660 void ath9k_hw_set_txpowerlimit(struct ath_hw
*ah
, u32 limit
);
661 void ath9k_hw_setmac(struct ath_hw
*ah
, const u8
*mac
);
662 void ath9k_hw_setopmode(struct ath_hw
*ah
);
663 void ath9k_hw_setmcastfilter(struct ath_hw
*ah
, u32 filter0
, u32 filter1
);
664 void ath9k_hw_setbssidmask(struct ath_hw
*ah
);
665 void ath9k_hw_write_associd(struct ath_hw
*ah
);
666 u64
ath9k_hw_gettsf64(struct ath_hw
*ah
);
667 void ath9k_hw_settsf64(struct ath_hw
*ah
, u64 tsf64
);
668 void ath9k_hw_reset_tsf(struct ath_hw
*ah
);
669 void ath9k_hw_set_tsfadjust(struct ath_hw
*ah
, u32 setting
);
670 u64
ath9k_hw_extend_tsf(struct ath_hw
*ah
, u32 rstamp
);
671 void ath9k_hw_init_global_settings(struct ath_hw
*ah
);
672 void ath9k_hw_set11nmac2040(struct ath_hw
*ah
);
673 void ath9k_hw_beaconinit(struct ath_hw
*ah
, u32 next_beacon
, u32 beacon_period
);
674 void ath9k_hw_set_sta_beacon_timers(struct ath_hw
*ah
,
675 const struct ath9k_beacon_state
*bs
);
677 bool ath9k_hw_setpower(struct ath_hw
*ah
, enum ath9k_power_mode mode
);
679 void ath9k_hw_configpcipowersave(struct ath_hw
*ah
, int restore
, int power_off
);
681 /* Interrupt Handling */
682 bool ath9k_hw_intrpend(struct ath_hw
*ah
);
683 bool ath9k_hw_getisr(struct ath_hw
*ah
, enum ath9k_int
*masked
);
684 enum ath9k_int
ath9k_hw_set_interrupts(struct ath_hw
*ah
, enum ath9k_int ints
);
686 /* Generic hw timer primitives */
687 struct ath_gen_timer
*ath_gen_timer_alloc(struct ath_hw
*ah
,
688 void (*trigger
)(void *),
689 void (*overflow
)(void *),
692 void ath9k_hw_gen_timer_start(struct ath_hw
*ah
,
693 struct ath_gen_timer
*timer
,
696 void ath9k_hw_gen_timer_stop(struct ath_hw
*ah
, struct ath_gen_timer
*timer
);
698 void ath_gen_timer_free(struct ath_hw
*ah
, struct ath_gen_timer
*timer
);
699 void ath_gen_timer_isr(struct ath_hw
*hw
);
700 u32
ath9k_hw_gettsf32(struct ath_hw
*ah
);
702 void ath9k_hw_name(struct ath_hw
*ah
, char *hw_name
, size_t len
);
704 #define ATH_PCIE_CAP_LINK_CTRL 0x70
705 #define ATH_PCIE_CAP_LINK_L0S 1
706 #define ATH_PCIE_CAP_LINK_L1 2