2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include <linux/if_ether.h>
21 #include <linux/delay.h>
34 #define ATHEROS_VENDOR_ID 0x168c
36 #define AR5416_DEVID_PCI 0x0023
37 #define AR5416_DEVID_PCIE 0x0024
38 #define AR9160_DEVID_PCI 0x0027
39 #define AR9280_DEVID_PCI 0x0029
40 #define AR9280_DEVID_PCIE 0x002a
41 #define AR9285_DEVID_PCIE 0x002b
42 #define AR2427_DEVID_PCIE 0x002c
43 #define AR9287_DEVID_PCI 0x002d
44 #define AR9287_DEVID_PCIE 0x002e
45 #define AR9300_DEVID_PCIE 0x0030
46 #define AR9300_DEVID_AR9340 0x0031
47 #define AR9300_DEVID_AR9485_PCIE 0x0032
48 #define AR9300_DEVID_AR9580 0x0033
49 #define AR9300_DEVID_AR9462 0x0034
50 #define AR9300_DEVID_AR9330 0x0035
52 #define AR5416_AR9100_DEVID 0x000b
54 #define AR_SUBVENDOR_ID_NOG 0x0e11
55 #define AR_SUBVENDOR_ID_NEW_A 0x7065
56 #define AR5416_MAGIC 0x19641014
58 #define AR9280_COEX2WIRE_SUBSYSID 0x309b
59 #define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa
60 #define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab
62 #define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1)
64 #define ATH_DEFAULT_NOISE_FLOOR -95
66 #define ATH9K_RSSI_BAD -128
68 #define ATH9K_NUM_CHANNELS 38
70 /* Register read/write primitives */
71 #define REG_WRITE(_ah, _reg, _val) \
72 (_ah)->reg_ops.write((_ah), (_val), (_reg))
74 #define REG_READ(_ah, _reg) \
75 (_ah)->reg_ops.read((_ah), (_reg))
77 #define REG_READ_MULTI(_ah, _addr, _val, _cnt) \
78 (_ah)->reg_ops.multi_read((_ah), (_addr), (_val), (_cnt))
80 #define REG_RMW(_ah, _reg, _set, _clr) \
81 (_ah)->reg_ops.rmw((_ah), (_reg), (_set), (_clr))
83 #define ENABLE_REGWRITE_BUFFER(_ah) \
85 if ((_ah)->reg_ops.enable_write_buffer) \
86 (_ah)->reg_ops.enable_write_buffer((_ah)); \
89 #define REGWRITE_BUFFER_FLUSH(_ah) \
91 if ((_ah)->reg_ops.write_flush) \
92 (_ah)->reg_ops.write_flush((_ah)); \
95 #define PR_EEP(_s, _val) \
97 len += snprintf(buf + len, size - len, "%20s : %10d\n", \
101 #define SM(_v, _f) (((_v) << _f##_S) & _f)
102 #define MS(_v, _f) (((_v) & _f) >> _f##_S)
103 #define REG_RMW_FIELD(_a, _r, _f, _v) \
104 REG_RMW(_a, _r, (((_v) << _f##_S) & _f), (_f))
105 #define REG_READ_FIELD(_a, _r, _f) \
106 (((REG_READ(_a, _r) & _f) >> _f##_S))
107 #define REG_SET_BIT(_a, _r, _f) \
108 REG_RMW(_a, _r, (_f), 0)
109 #define REG_CLR_BIT(_a, _r, _f) \
110 REG_RMW(_a, _r, 0, (_f))
112 #define DO_DELAY(x) do { \
113 if (((++(x) % 64) == 0) && \
114 (ath9k_hw_common(ah)->bus_ops->ath_bus_type \
119 #define REG_WRITE_ARRAY(iniarray, column, regWr) \
120 ath9k_hw_write_array(ah, iniarray, column, &(regWr))
122 #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
123 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
124 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
125 #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3
126 #define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4
127 #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
128 #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
129 #define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_DATA 0x16
130 #define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_CLK 0x17
131 #define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA 0x18
132 #define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK 0x19
133 #define AR_GPIO_OUTPUT_MUX_AS_WL_IN_TX 0x14
134 #define AR_GPIO_OUTPUT_MUX_AS_WL_IN_RX 0x13
135 #define AR_GPIO_OUTPUT_MUX_AS_BT_IN_TX 9
136 #define AR_GPIO_OUTPUT_MUX_AS_BT_IN_RX 8
137 #define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_STROBE 0x1d
138 #define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_DATA 0x1e
140 #define AR_GPIOD_MASK 0x00001FFF
141 #define AR_GPIO_BIT(_gpio) (1 << (_gpio))
143 #define BASE_ACTIVATE_DELAY 100
144 #define RTC_PLL_SETTLE_DELAY (AR_SREV_9340(ah) ? 1000 : 100)
145 #define COEF_SCALE_S 24
146 #define HT40_CHANNEL_CENTER_SHIFT 10
148 #define ATH9K_ANTENNA0_CHAINMASK 0x1
149 #define ATH9K_ANTENNA1_CHAINMASK 0x2
151 #define ATH9K_NUM_DMA_DEBUG_REGS 8
152 #define ATH9K_NUM_QUEUES 10
154 #define MAX_RATE_POWER 63
155 #define AH_WAIT_TIMEOUT 100000 /* (us) */
156 #define AH_TSF_WRITE_TIMEOUT 100 /* (us) */
157 #define AH_TIME_QUANTUM 10
158 #define AR_KEYTABLE_SIZE 128
159 #define POWER_UP_TIME 10000
160 #define SPUR_RSSI_THRESH 40
161 #define UPPER_5G_SUB_BAND_START 5700
162 #define MID_5G_SUB_BAND_START 5400
164 #define CAB_TIMEOUT_VAL 10
165 #define BEACON_TIMEOUT_VAL 10
166 #define MIN_BEACON_TIMEOUT_VAL 1
169 #define INIT_CONFIG_STATUS 0x00000000
170 #define INIT_RSSI_THR 0x00000700
171 #define INIT_BCON_CNTRL_REG 0x00000000
173 #define TU_TO_USEC(_tu) ((_tu) << 10)
175 #define ATH9K_HW_RX_HP_QDEPTH 16
176 #define ATH9K_HW_RX_LP_QDEPTH 128
178 #define PAPRD_GAIN_TABLE_ENTRIES 32
179 #define PAPRD_TABLE_SZ 24
180 #define PAPRD_IDEAL_AGC2_PWR_RANGE 0xe0
182 enum ath_hw_txq_subtype
{
189 enum ath_ini_subsys
{
197 ATH9K_HW_CAP_HT
= BIT(0),
198 ATH9K_HW_CAP_RFSILENT
= BIT(1),
199 ATH9K_HW_CAP_AUTOSLEEP
= BIT(2),
200 ATH9K_HW_CAP_4KB_SPLITTRANS
= BIT(3),
201 ATH9K_HW_CAP_EDMA
= BIT(4),
202 ATH9K_HW_CAP_RAC_SUPPORTED
= BIT(5),
203 ATH9K_HW_CAP_LDPC
= BIT(6),
204 ATH9K_HW_CAP_FASTCLOCK
= BIT(7),
205 ATH9K_HW_CAP_SGI_20
= BIT(8),
206 ATH9K_HW_CAP_PAPRD
= BIT(9),
207 ATH9K_HW_CAP_ANT_DIV_COMB
= BIT(10),
208 ATH9K_HW_CAP_2GHZ
= BIT(11),
209 ATH9K_HW_CAP_5GHZ
= BIT(12),
210 ATH9K_HW_CAP_APM
= BIT(13),
211 ATH9K_HW_CAP_RTT
= BIT(14),
212 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
213 ATH9K_HW_CAP_MCI
= BIT(15),
215 ATH9K_HW_CAP_MCI
= 0,
217 ATH9K_HW_CAP_DFS
= BIT(16),
220 struct ath9k_hw_capabilities
{
221 u32 hw_caps
; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
234 bool pcie_lcr_extsync_en
;
237 struct ath9k_ops_config
{
238 int dma_beacon_response_time
;
239 int sw_beacon_response_time
;
240 int additional_swba_backoff
;
242 u32 cwm_ignore_extcca
;
243 bool pcieSerDesWrite
;
253 int serialize_regmode
;
254 bool rx_intr_mitigation
;
255 bool tx_intr_mitigation
;
256 #define SPUR_DISABLE 0
257 #define SPUR_ENABLE_IOCTL 1
258 #define SPUR_ENABLE_EEPROM 2
259 #define AR_SPUR_5413_1 1640
260 #define AR_SPUR_5413_2 1200
261 #define AR_NO_SPUR 0x8000
262 #define AR_BASE_FREQ_2GHZ 2300
263 #define AR_BASE_FREQ_5GHZ 4900
264 #define AR_SPUR_FEEQ_BOUND_HT40 19
265 #define AR_SPUR_FEEQ_BOUND_HT20 10
267 u16 spurchans
[AR_EEPROM_MODAL_SPURS
][2];
269 u16 ani_poll_interval
; /* ANI poll interval in ms */
273 ATH9K_INT_RX
= 0x00000001,
274 ATH9K_INT_RXDESC
= 0x00000002,
275 ATH9K_INT_RXHP
= 0x00000001,
276 ATH9K_INT_RXLP
= 0x00000002,
277 ATH9K_INT_RXNOFRM
= 0x00000008,
278 ATH9K_INT_RXEOL
= 0x00000010,
279 ATH9K_INT_RXORN
= 0x00000020,
280 ATH9K_INT_TX
= 0x00000040,
281 ATH9K_INT_TXDESC
= 0x00000080,
282 ATH9K_INT_TIM_TIMER
= 0x00000100,
283 ATH9K_INT_MCI
= 0x00000200,
284 ATH9K_INT_BB_WATCHDOG
= 0x00000400,
285 ATH9K_INT_TXURN
= 0x00000800,
286 ATH9K_INT_MIB
= 0x00001000,
287 ATH9K_INT_RXPHY
= 0x00004000,
288 ATH9K_INT_RXKCM
= 0x00008000,
289 ATH9K_INT_SWBA
= 0x00010000,
290 ATH9K_INT_BMISS
= 0x00040000,
291 ATH9K_INT_BNR
= 0x00100000,
292 ATH9K_INT_TIM
= 0x00200000,
293 ATH9K_INT_DTIM
= 0x00400000,
294 ATH9K_INT_DTIMSYNC
= 0x00800000,
295 ATH9K_INT_GPIO
= 0x01000000,
296 ATH9K_INT_CABEND
= 0x02000000,
297 ATH9K_INT_TSFOOR
= 0x04000000,
298 ATH9K_INT_GENTIMER
= 0x08000000,
299 ATH9K_INT_CST
= 0x10000000,
300 ATH9K_INT_GTT
= 0x20000000,
301 ATH9K_INT_FATAL
= 0x40000000,
302 ATH9K_INT_GLOBAL
= 0x80000000,
303 ATH9K_INT_BMISC
= ATH9K_INT_TIM
|
308 ATH9K_INT_COMMON
= ATH9K_INT_RXNOFRM
|
320 ATH9K_INT_NOCARD
= 0xffffffff
323 #define CHANNEL_CW_INT 0x00002
324 #define CHANNEL_CCK 0x00020
325 #define CHANNEL_OFDM 0x00040
326 #define CHANNEL_2GHZ 0x00080
327 #define CHANNEL_5GHZ 0x00100
328 #define CHANNEL_PASSIVE 0x00200
329 #define CHANNEL_DYN 0x00400
330 #define CHANNEL_HALF 0x04000
331 #define CHANNEL_QUARTER 0x08000
332 #define CHANNEL_HT20 0x10000
333 #define CHANNEL_HT40PLUS 0x20000
334 #define CHANNEL_HT40MINUS 0x40000
336 #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
337 #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
338 #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
339 #define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20)
340 #define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20)
341 #define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
342 #define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
343 #define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
344 #define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
345 #define CHANNEL_ALL \
354 #define MAX_RTT_TABLE_ENTRY 6
355 #define RTT_HIST_MAX 3
356 struct ath9k_rtt_hist
{
357 u32 table
[AR9300_MAX_CHAINS
][RTT_HIST_MAX
][MAX_RTT_TABLE_ENTRY
];
361 #define MAX_IQCAL_MEASUREMENT 8
362 #define MAX_CL_TAB_ENTRY 16
364 struct ath9k_hw_cal_data
{
372 bool nfcal_interference
;
373 bool done_txiqcal_once
;
374 bool done_txclcal_once
;
375 u16 small_signal_gain
[AR9300_MAX_CHAINS
];
376 u32 pa_table
[AR9300_MAX_CHAINS
][PAPRD_TABLE_SZ
];
377 u32 num_measures
[AR9300_MAX_CHAINS
];
378 int tx_corr_coeff
[MAX_IQCAL_MEASUREMENT
][AR9300_MAX_CHAINS
];
379 u32 tx_clcal
[AR9300_MAX_CHAINS
][MAX_CL_TAB_ENTRY
];
380 struct ath9k_nfcal_hist nfCalHist
[NUM_NF_READINGS
];
381 struct ath9k_rtt_hist rtt_hist
;
384 struct ath9k_channel
{
385 struct ieee80211_channel
*chan
;
386 struct ar5416AniState ani
;
393 #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
394 (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
395 (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
396 (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
397 #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
398 #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
399 #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
400 #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
401 #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
402 #define IS_CHAN_A_FAST_CLOCK(_ah, _c) \
403 ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \
404 ((_ah)->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK))
406 /* These macros check chanmode and not channelFlags */
407 #define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B)
408 #define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \
409 ((_c)->chanmode == CHANNEL_G_HT20))
410 #define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \
411 ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \
412 ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \
413 ((_c)->chanmode == CHANNEL_G_HT40MINUS))
414 #define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
416 enum ath9k_power_mode
{
419 ATH9K_PM_NETWORK_SLEEP
,
424 SER_REG_MODE_OFF
= 0,
426 SER_REG_MODE_AUTO
= 2,
429 enum ath9k_rx_qtype
{
435 struct ath9k_beacon_state
{
439 #define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */
442 u16 bs_cfpmaxduration
;
445 u16 bs_bmissthreshold
;
446 u32 bs_sleepduration
;
447 u32 bs_tsfoor_threshold
;
450 struct chan_centers
{
457 ATH9K_RESET_POWER_ON
,
462 struct ath9k_hw_version
{
471 enum ath_usb_dev usbdev
;
474 /* Generic TSF timer definitions */
476 #define ATH_MAX_GEN_TIMER 16
478 #define AR_GENTMR_BIT(_index) (1 << (_index))
481 * Using de Bruijin sequence to look up 1's index in a 32 bit number
482 * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001
484 #define debruijn32 0x077CB531U
486 struct ath_gen_timer_configuration
{
493 struct ath_gen_timer
{
494 void (*trigger
)(void *arg
);
495 void (*overflow
)(void *arg
);
500 struct ath_gen_timer_table
{
501 u32 gen_timer_index
[32];
502 struct ath_gen_timer
*timers
[ATH_MAX_GEN_TIMER
];
504 unsigned long timer_bits
;
509 struct ath_hw_antcomb_conf
{
520 * struct ath_hw_radar_conf - radar detection initialization parameters
522 * @pulse_inband: threshold for checking the ratio of in-band power
523 * to total power for short radar pulses (half dB steps)
524 * @pulse_inband_step: threshold for checking an in-band power to total
525 * power ratio increase for short radar pulses (half dB steps)
526 * @pulse_height: threshold for detecting the beginning of a short
527 * radar pulse (dB step)
528 * @pulse_rssi: threshold for detecting if a short radar pulse is
530 * @pulse_maxlen: maximum pulse length (0.8 us steps)
532 * @radar_rssi: RSSI threshold for starting long radar detection (dB steps)
533 * @radar_inband: threshold for checking the ratio of in-band power
534 * to total power for long radar pulses (half dB steps)
535 * @fir_power: threshold for detecting the end of a long radar pulse (dB)
537 * @ext_channel: enable extension channel radar detection
539 struct ath_hw_radar_conf
{
540 unsigned int pulse_inband
;
541 unsigned int pulse_inband_step
;
542 unsigned int pulse_height
;
543 unsigned int pulse_rssi
;
544 unsigned int pulse_maxlen
;
546 unsigned int radar_rssi
;
547 unsigned int radar_inband
;
554 * struct ath_hw_private_ops - callbacks used internally by hardware code
556 * This structure contains private callbacks designed to only be used internally
557 * by the hardware core.
559 * @init_cal_settings: setup types of calibrations supported
560 * @init_cal: starts actual calibration
562 * @init_mode_regs: Initializes mode registers
563 * @init_mode_gain_regs: Initialize TX/RX gain registers
565 * @rf_set_freq: change frequency
566 * @spur_mitigate_freq: spur mitigation
567 * @rf_alloc_ext_banks:
568 * @rf_free_ext_banks:
570 * @compute_pll_control: compute the PLL control value to use for
571 * AR_RTC_PLL_CONTROL for a given channel
572 * @setup_calibration: set up calibration
573 * @iscal_supported: used to query if a type of calibration is supported
575 * @ani_cache_ini_regs: cache the values for ANI from the initial
576 * register settings through the register initialization.
578 struct ath_hw_private_ops
{
579 /* Calibration ops */
580 void (*init_cal_settings
)(struct ath_hw
*ah
);
581 bool (*init_cal
)(struct ath_hw
*ah
, struct ath9k_channel
*chan
);
583 void (*init_mode_regs
)(struct ath_hw
*ah
);
584 void (*init_mode_gain_regs
)(struct ath_hw
*ah
);
585 void (*setup_calibration
)(struct ath_hw
*ah
,
586 struct ath9k_cal_list
*currCal
);
589 int (*rf_set_freq
)(struct ath_hw
*ah
,
590 struct ath9k_channel
*chan
);
591 void (*spur_mitigate_freq
)(struct ath_hw
*ah
,
592 struct ath9k_channel
*chan
);
593 int (*rf_alloc_ext_banks
)(struct ath_hw
*ah
);
594 void (*rf_free_ext_banks
)(struct ath_hw
*ah
);
595 bool (*set_rf_regs
)(struct ath_hw
*ah
,
596 struct ath9k_channel
*chan
,
598 void (*set_channel_regs
)(struct ath_hw
*ah
, struct ath9k_channel
*chan
);
599 void (*init_bb
)(struct ath_hw
*ah
,
600 struct ath9k_channel
*chan
);
601 int (*process_ini
)(struct ath_hw
*ah
, struct ath9k_channel
*chan
);
602 void (*olc_init
)(struct ath_hw
*ah
);
603 void (*set_rfmode
)(struct ath_hw
*ah
, struct ath9k_channel
*chan
);
604 void (*mark_phy_inactive
)(struct ath_hw
*ah
);
605 void (*set_delta_slope
)(struct ath_hw
*ah
, struct ath9k_channel
*chan
);
606 bool (*rfbus_req
)(struct ath_hw
*ah
);
607 void (*rfbus_done
)(struct ath_hw
*ah
);
608 void (*restore_chainmask
)(struct ath_hw
*ah
);
609 u32 (*compute_pll_control
)(struct ath_hw
*ah
,
610 struct ath9k_channel
*chan
);
611 bool (*ani_control
)(struct ath_hw
*ah
, enum ath9k_ani_cmd cmd
,
613 void (*do_getnf
)(struct ath_hw
*ah
, int16_t nfarray
[NUM_NF_READINGS
]);
614 void (*set_radar_params
)(struct ath_hw
*ah
,
615 struct ath_hw_radar_conf
*conf
);
616 int (*fast_chan_change
)(struct ath_hw
*ah
, struct ath9k_channel
*chan
,
620 void (*ani_cache_ini_regs
)(struct ath_hw
*ah
);
624 * struct ath_hw_ops - callbacks used by hardware code and driver code
626 * This structure contains callbacks designed to to be used internally by
627 * hardware code and also by the lower level driver.
629 * @config_pci_powersave:
630 * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC
633 void (*config_pci_powersave
)(struct ath_hw
*ah
,
635 void (*rx_enable
)(struct ath_hw
*ah
);
636 void (*set_desc_link
)(void *ds
, u32 link
);
637 bool (*calibrate
)(struct ath_hw
*ah
,
638 struct ath9k_channel
*chan
,
641 bool (*get_isr
)(struct ath_hw
*ah
, enum ath9k_int
*masked
);
642 void (*set_txdesc
)(struct ath_hw
*ah
, void *ds
,
643 struct ath_tx_info
*i
);
644 int (*proc_txdesc
)(struct ath_hw
*ah
, void *ds
,
645 struct ath_tx_status
*ts
);
646 void (*antdiv_comb_conf_get
)(struct ath_hw
*ah
,
647 struct ath_hw_antcomb_conf
*antconf
);
648 void (*antdiv_comb_conf_set
)(struct ath_hw
*ah
,
649 struct ath_hw_antcomb_conf
*antconf
);
653 struct ath_nf_limits
{
661 TX_IQ_ON_AGC_CAL
= BIT(1),
666 #define AH_USE_EEPROM 0x1
667 #define AH_UNPLUGGED 0x2 /* The card has been physically removed. */
668 #define AH_FASTCC 0x4
671 struct ath_ops reg_ops
;
673 struct ieee80211_hw
*hw
;
674 struct ath_common common
;
675 struct ath9k_hw_version hw_version
;
676 struct ath9k_ops_config config
;
677 struct ath9k_hw_capabilities caps
;
678 struct ath9k_channel channels
[ATH9K_NUM_CHANNELS
];
679 struct ath9k_channel
*curchan
;
682 struct ar5416_eeprom_def def
;
683 struct ar5416_eeprom_4k map4k
;
684 struct ar9287_eeprom map9287
;
685 struct ar9300_eeprom ar9300_eep
;
687 const struct eeprom_ops
*eep_ops
;
693 bool need_an_top2_fixup
;
697 struct ath_nf_limits nf_2g
;
698 struct ath_nf_limits nf_5g
;
706 enum nl80211_iftype opmode
;
707 enum ath9k_power_mode power_mode
;
710 struct ath9k_hw_cal_data
*caldata
;
711 struct ath9k_pacal_info pacal_info
;
712 struct ar5416Stats stats
;
713 struct ath9k_tx_queue_info txq
[ATH9K_NUM_TX_QUEUES
];
715 int16_t curchan_rad_index
;
716 enum ath9k_int imask
;
718 u32 txok_interrupt_mask
;
719 u32 txerr_interrupt_mask
;
720 u32 txdesc_interrupt_mask
;
721 u32 txeol_interrupt_mask
;
722 u32 txurn_interrupt_mask
;
723 atomic_t intr_ref_cnt
;
730 struct ath9k_cal_list iq_caldata
;
731 struct ath9k_cal_list adcgain_caldata
;
732 struct ath9k_cal_list adcdc_caldata
;
733 struct ath9k_cal_list tempCompCalData
;
734 struct ath9k_cal_list
*cal_list
;
735 struct ath9k_cal_list
*cal_list_last
;
736 struct ath9k_cal_list
*cal_list_curr
;
737 #define totalPowerMeasI meas0.unsign
738 #define totalPowerMeasQ meas1.unsign
739 #define totalIqCorrMeas meas2.sign
740 #define totalAdcIOddPhase meas0.unsign
741 #define totalAdcIEvenPhase meas1.unsign
742 #define totalAdcQOddPhase meas2.unsign
743 #define totalAdcQEvenPhase meas3.unsign
744 #define totalAdcDcOffsetIOddPhase meas0.sign
745 #define totalAdcDcOffsetIEvenPhase meas1.sign
746 #define totalAdcDcOffsetQOddPhase meas2.sign
747 #define totalAdcDcOffsetQEvenPhase meas3.sign
749 u32 unsign
[AR5416_MAX_CHAINS
];
750 int32_t sign
[AR5416_MAX_CHAINS
];
753 u32 unsign
[AR5416_MAX_CHAINS
];
754 int32_t sign
[AR5416_MAX_CHAINS
];
757 u32 unsign
[AR5416_MAX_CHAINS
];
758 int32_t sign
[AR5416_MAX_CHAINS
];
761 u32 unsign
[AR5416_MAX_CHAINS
];
762 int32_t sign
[AR5416_MAX_CHAINS
];
767 u32 sta_id1_defaults
;
773 } enable_32kHz_clock
;
775 /* Private to hardware code */
776 struct ath_hw_private_ops private_ops
;
777 /* Accessed by the lower level driver */
778 struct ath_hw_ops ops
;
780 /* Used to program the radio on non single-chip devices */
781 u32
*analogBank0Data
;
782 u32
*analogBank1Data
;
783 u32
*analogBank2Data
;
784 u32
*analogBank3Data
;
785 u32
*analogBank6Data
;
786 u32
*analogBank6TPCData
;
787 u32
*analogBank7Data
;
799 int totalSizeDesired
[5];
803 enum ath9k_ani_cmd ani_function
;
805 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
806 struct ath_btcoex_hw btcoex_hw
;
813 struct ath_hw_radar_conf radar_conf
;
815 u32 originalGain
[22];
822 struct ar5416IniArray iniModes
;
823 struct ar5416IniArray iniCommon
;
824 struct ar5416IniArray iniBank0
;
825 struct ar5416IniArray iniBB_RfGain
;
826 struct ar5416IniArray iniBank1
;
827 struct ar5416IniArray iniBank2
;
828 struct ar5416IniArray iniBank3
;
829 struct ar5416IniArray iniBank6
;
830 struct ar5416IniArray iniBank6TPC
;
831 struct ar5416IniArray iniBank7
;
832 struct ar5416IniArray iniAddac
;
833 struct ar5416IniArray iniPcieSerdes
;
834 struct ar5416IniArray iniPcieSerdesLowPower
;
835 struct ar5416IniArray iniModesAdditional
;
836 struct ar5416IniArray iniModesAdditional_40M
;
837 struct ar5416IniArray iniModesRxGain
;
838 struct ar5416IniArray iniModesTxGain
;
839 struct ar5416IniArray iniModes_9271_1_0_only
;
840 struct ar5416IniArray iniCckfirNormal
;
841 struct ar5416IniArray iniCckfirJapan2484
;
842 struct ar5416IniArray ini_japan2484
;
843 struct ar5416IniArray iniCommon_normal_cck_fir_coeff_9271
;
844 struct ar5416IniArray iniCommon_japan_2484_cck_fir_coeff_9271
;
845 struct ar5416IniArray iniModes_9271_ANI_reg
;
846 struct ar5416IniArray iniModes_high_power_tx_gain_9271
;
847 struct ar5416IniArray iniModes_normal_power_tx_gain_9271
;
848 struct ar5416IniArray ini_radio_post_sys2ant
;
849 struct ar5416IniArray ini_BTCOEX_MAX_TXPWR
;
851 struct ar5416IniArray iniMac
[ATH_INI_NUM_SPLIT
];
852 struct ar5416IniArray iniBB
[ATH_INI_NUM_SPLIT
];
853 struct ar5416IniArray iniRadio
[ATH_INI_NUM_SPLIT
];
854 struct ar5416IniArray iniSOC
[ATH_INI_NUM_SPLIT
];
856 u32 intr_gen_timer_trigger
;
857 u32 intr_gen_timer_thresh
;
858 struct ath_gen_timer_table hw_gen_timers
;
860 struct ar9003_txs
*ts_ring
;
867 u32 bb_watchdog_last_status
;
868 u32 bb_watchdog_timeout_ms
; /* in ms, 0 to disable */
869 u8 bb_hang_rx_ofdm
; /* true if bb hang due to rx_ofdm */
871 unsigned int paprd_target_power
;
872 unsigned int paprd_training_power
;
873 unsigned int paprd_ratemask
;
874 unsigned int paprd_ratemask_ht40
;
875 bool paprd_table_write_done
;
876 u32 paprd_gain_table_entries
[PAPRD_GAIN_TABLE_ENTRIES
];
877 u8 paprd_gain_table_index
[PAPRD_GAIN_TABLE_ENTRIES
];
879 * Store the permanent value of Reg 0x4004in WARegVal
880 * so we dont have to R/M/W. We should not be reading
881 * this register when in sleep states.
885 /* Enterprise mode cap */
889 int (*get_mac_revision
)(void);
890 int (*external_reset
)(void);
894 enum ath_bus_type ath_bus_type
;
895 void (*read_cachesize
)(struct ath_common
*common
, int *csz
);
896 bool (*eeprom_read
)(struct ath_common
*common
, u32 off
, u16
*data
);
897 void (*bt_coex_prep
)(struct ath_common
*common
);
898 void (*extn_synch_en
)(struct ath_common
*common
);
899 void (*aspm_init
)(struct ath_common
*common
);
902 static inline struct ath_common
*ath9k_hw_common(struct ath_hw
*ah
)
907 static inline struct ath_regulatory
*ath9k_hw_regulatory(struct ath_hw
*ah
)
909 return &(ath9k_hw_common(ah
)->regulatory
);
912 static inline struct ath_hw_private_ops
*ath9k_hw_private_ops(struct ath_hw
*ah
)
914 return &ah
->private_ops
;
917 static inline struct ath_hw_ops
*ath9k_hw_ops(struct ath_hw
*ah
)
922 static inline u8
get_streams(int mask
)
924 return !!(mask
& BIT(0)) + !!(mask
& BIT(1)) + !!(mask
& BIT(2));
927 /* Initialization, Detach, Reset */
928 const char *ath9k_hw_probe(u16 vendorid
, u16 devid
);
929 void ath9k_hw_deinit(struct ath_hw
*ah
);
930 int ath9k_hw_init(struct ath_hw
*ah
);
931 int ath9k_hw_reset(struct ath_hw
*ah
, struct ath9k_channel
*chan
,
932 struct ath9k_hw_cal_data
*caldata
, bool bChannelChange
);
933 int ath9k_hw_fill_cap_info(struct ath_hw
*ah
);
934 u32
ath9k_regd_get_ctl(struct ath_regulatory
*reg
, struct ath9k_channel
*chan
);
936 /* GPIO / RFKILL / Antennae */
937 void ath9k_hw_cfg_gpio_input(struct ath_hw
*ah
, u32 gpio
);
938 u32
ath9k_hw_gpio_get(struct ath_hw
*ah
, u32 gpio
);
939 void ath9k_hw_cfg_output(struct ath_hw
*ah
, u32 gpio
,
941 void ath9k_hw_set_gpio(struct ath_hw
*ah
, u32 gpio
, u32 val
);
942 u32
ath9k_hw_getdefantenna(struct ath_hw
*ah
);
943 void ath9k_hw_setantenna(struct ath_hw
*ah
, u32 antenna
);
945 /* General Operation */
946 bool ath9k_hw_wait(struct ath_hw
*ah
, u32 reg
, u32 mask
, u32 val
, u32 timeout
);
947 void ath9k_hw_write_array(struct ath_hw
*ah
, struct ar5416IniArray
*array
,
948 int column
, unsigned int *writecnt
);
949 u32
ath9k_hw_reverse_bits(u32 val
, u32 n
);
950 u16
ath9k_hw_computetxtime(struct ath_hw
*ah
,
952 u32 frameLen
, u16 rateix
, bool shortPreamble
);
953 void ath9k_hw_get_channel_centers(struct ath_hw
*ah
,
954 struct ath9k_channel
*chan
,
955 struct chan_centers
*centers
);
956 u32
ath9k_hw_getrxfilter(struct ath_hw
*ah
);
957 void ath9k_hw_setrxfilter(struct ath_hw
*ah
, u32 bits
);
958 bool ath9k_hw_phy_disable(struct ath_hw
*ah
);
959 bool ath9k_hw_disable(struct ath_hw
*ah
);
960 void ath9k_hw_set_txpowerlimit(struct ath_hw
*ah
, u32 limit
, bool test
);
961 void ath9k_hw_setopmode(struct ath_hw
*ah
);
962 void ath9k_hw_setmcastfilter(struct ath_hw
*ah
, u32 filter0
, u32 filter1
);
963 void ath9k_hw_write_associd(struct ath_hw
*ah
);
964 u32
ath9k_hw_gettsf32(struct ath_hw
*ah
);
965 u64
ath9k_hw_gettsf64(struct ath_hw
*ah
);
966 void ath9k_hw_settsf64(struct ath_hw
*ah
, u64 tsf64
);
967 void ath9k_hw_reset_tsf(struct ath_hw
*ah
);
968 void ath9k_hw_set_tsfadjust(struct ath_hw
*ah
, u32 setting
);
969 void ath9k_hw_init_global_settings(struct ath_hw
*ah
);
970 u32
ar9003_get_pll_sqsum_dvc(struct ath_hw
*ah
);
971 void ath9k_hw_set11nmac2040(struct ath_hw
*ah
);
972 void ath9k_hw_beaconinit(struct ath_hw
*ah
, u32 next_beacon
, u32 beacon_period
);
973 void ath9k_hw_set_sta_beacon_timers(struct ath_hw
*ah
,
974 const struct ath9k_beacon_state
*bs
);
975 bool ath9k_hw_check_alive(struct ath_hw
*ah
);
977 bool ath9k_hw_setpower(struct ath_hw
*ah
, enum ath9k_power_mode mode
);
979 /* Generic hw timer primitives */
980 struct ath_gen_timer
*ath_gen_timer_alloc(struct ath_hw
*ah
,
981 void (*trigger
)(void *),
982 void (*overflow
)(void *),
985 void ath9k_hw_gen_timer_start(struct ath_hw
*ah
,
986 struct ath_gen_timer
*timer
,
989 void ath9k_hw_gen_timer_stop(struct ath_hw
*ah
, struct ath_gen_timer
*timer
);
991 void ath_gen_timer_free(struct ath_hw
*ah
, struct ath_gen_timer
*timer
);
992 void ath_gen_timer_isr(struct ath_hw
*hw
);
994 void ath9k_hw_name(struct ath_hw
*ah
, char *hw_name
, size_t len
);
997 void ath9k_hw_htc_resetinit(struct ath_hw
*ah
);
1000 void ath9k_hw_get_delta_slope_vals(struct ath_hw
*ah
, u32 coef_scaled
,
1001 u32
*coef_mantissa
, u32
*coef_exponent
);
1002 void ath9k_hw_apply_txpower(struct ath_hw
*ah
, struct ath9k_channel
*chan
);
1005 * Code Specific to AR5008, AR9001 or AR9002,
1006 * we stuff these here to avoid callbacks for AR9003.
1008 void ar9002_hw_cck_chan14_spread(struct ath_hw
*ah
);
1009 int ar9002_hw_rf_claim(struct ath_hw
*ah
);
1010 void ar9002_hw_enable_async_fifo(struct ath_hw
*ah
);
1013 * Code specific to AR9003, we stuff these here to avoid callbacks
1014 * for older families
1016 void ar9003_hw_bb_watchdog_config(struct ath_hw
*ah
);
1017 void ar9003_hw_bb_watchdog_read(struct ath_hw
*ah
);
1018 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw
*ah
);
1019 void ar9003_hw_disable_phy_restart(struct ath_hw
*ah
);
1020 void ar9003_paprd_enable(struct ath_hw
*ah
, bool val
);
1021 void ar9003_paprd_populate_single_table(struct ath_hw
*ah
,
1022 struct ath9k_hw_cal_data
*caldata
,
1024 int ar9003_paprd_create_curve(struct ath_hw
*ah
,
1025 struct ath9k_hw_cal_data
*caldata
, int chain
);
1026 int ar9003_paprd_setup_gain_table(struct ath_hw
*ah
, int chain
);
1027 int ar9003_paprd_init_table(struct ath_hw
*ah
);
1028 bool ar9003_paprd_is_done(struct ath_hw
*ah
);
1029 void ar9003_hw_set_paprd_txdesc(struct ath_hw
*ah
, void *ds
, u8 chains
);
1031 /* Hardware family op attach helpers */
1032 void ar5008_hw_attach_phy_ops(struct ath_hw
*ah
);
1033 void ar9002_hw_attach_phy_ops(struct ath_hw
*ah
);
1034 void ar9003_hw_attach_phy_ops(struct ath_hw
*ah
);
1036 void ar9002_hw_attach_calib_ops(struct ath_hw
*ah
);
1037 void ar9003_hw_attach_calib_ops(struct ath_hw
*ah
);
1039 void ar9002_hw_attach_ops(struct ath_hw
*ah
);
1040 void ar9003_hw_attach_ops(struct ath_hw
*ah
);
1042 void ar9002_hw_load_ani_reg(struct ath_hw
*ah
, struct ath9k_channel
*chan
);
1044 * ANI work can be shared between all families but a next
1045 * generation implementation of ANI will be used only for AR9003 only
1046 * for now as the other families still need to be tested with the same
1047 * next generation ANI. Feel free to start testing it though for the
1048 * older families (AR5008, AR9001, AR9002) by using modparam_force_new_ani.
1050 extern int modparam_force_new_ani
;
1051 void ath9k_ani_reset(struct ath_hw
*ah
, bool is_scanning
);
1052 void ath9k_hw_proc_mib_event(struct ath_hw
*ah
);
1053 void ath9k_hw_ani_monitor(struct ath_hw
*ah
, struct ath9k_channel
*chan
);
1055 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
1056 static inline bool ath9k_hw_btcoex_is_enabled(struct ath_hw
*ah
)
1058 return ah
->btcoex_hw
.enabled
;
1060 void ath9k_hw_btcoex_enable(struct ath_hw
*ah
);
1061 static inline enum ath_btcoex_scheme
1062 ath9k_hw_get_btcoex_scheme(struct ath_hw
*ah
)
1064 return ah
->btcoex_hw
.scheme
;
1067 static inline bool ath9k_hw_btcoex_is_enabled(struct ath_hw
*ah
)
1071 static inline void ath9k_hw_btcoex_enable(struct ath_hw
*ah
)
1074 static inline enum ath_btcoex_scheme
1075 ath9k_hw_get_btcoex_scheme(struct ath_hw
*ah
)
1077 return ATH_BTCOEX_CFG_NONE
;
1079 #endif /* CONFIG_ATH9K_BTCOEX_SUPPORT */
1081 #define ATH9K_CLOCK_RATE_CCK 22
1082 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
1083 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
1084 #define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44