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ath9k_hw: Define abstraction for tx desc access
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / hw.h
1 /*
2 * Copyright (c) 2008-2010 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #ifndef HW_H
18 #define HW_H
19
20 #include <linux/if_ether.h>
21 #include <linux/delay.h>
22 #include <linux/io.h>
23
24 #include "mac.h"
25 #include "ani.h"
26 #include "eeprom.h"
27 #include "calib.h"
28 #include "reg.h"
29 #include "phy.h"
30 #include "btcoex.h"
31 #include "ar9003_mac.h"
32
33 #include "../regd.h"
34 #include "../debug.h"
35
36 #define ATHEROS_VENDOR_ID 0x168c
37
38 #define AR5416_DEVID_PCI 0x0023
39 #define AR5416_DEVID_PCIE 0x0024
40 #define AR9160_DEVID_PCI 0x0027
41 #define AR9280_DEVID_PCI 0x0029
42 #define AR9280_DEVID_PCIE 0x002a
43 #define AR9285_DEVID_PCIE 0x002b
44 #define AR2427_DEVID_PCIE 0x002c
45 #define AR9287_DEVID_PCI 0x002d
46 #define AR9287_DEVID_PCIE 0x002e
47 #define AR9300_DEVID_PCIE 0x0030
48
49 #define AR5416_AR9100_DEVID 0x000b
50
51 #define AR_SUBVENDOR_ID_NOG 0x0e11
52 #define AR_SUBVENDOR_ID_NEW_A 0x7065
53 #define AR5416_MAGIC 0x19641014
54
55 #define AR9280_COEX2WIRE_SUBSYSID 0x309b
56 #define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa
57 #define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab
58
59 #define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1)
60
61 #define ATH_DEFAULT_NOISE_FLOOR -95
62
63 #define ATH9K_RSSI_BAD -128
64
65 /* Register read/write primitives */
66 #define REG_WRITE(_ah, _reg, _val) \
67 ath9k_hw_common(_ah)->ops->write((_ah), (_val), (_reg))
68
69 #define REG_READ(_ah, _reg) \
70 ath9k_hw_common(_ah)->ops->read((_ah), (_reg))
71
72 #define SM(_v, _f) (((_v) << _f##_S) & _f)
73 #define MS(_v, _f) (((_v) & _f) >> _f##_S)
74 #define REG_RMW(_a, _r, _set, _clr) \
75 REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set))
76 #define REG_RMW_FIELD(_a, _r, _f, _v) \
77 REG_WRITE(_a, _r, \
78 (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f))
79 #define REG_READ_FIELD(_a, _r, _f) \
80 (((REG_READ(_a, _r) & _f) >> _f##_S))
81 #define REG_SET_BIT(_a, _r, _f) \
82 REG_WRITE(_a, _r, REG_READ(_a, _r) | _f)
83 #define REG_CLR_BIT(_a, _r, _f) \
84 REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f)
85
86 #define DO_DELAY(x) do { \
87 if ((++(x) % 64) == 0) \
88 udelay(1); \
89 } while (0)
90
91 #define REG_WRITE_ARRAY(iniarray, column, regWr) do { \
92 int r; \
93 for (r = 0; r < ((iniarray)->ia_rows); r++) { \
94 REG_WRITE(ah, INI_RA((iniarray), (r), 0), \
95 INI_RA((iniarray), r, (column))); \
96 DO_DELAY(regWr); \
97 } \
98 } while (0)
99
100 #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
101 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
102 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
103 #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3
104 #define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4
105 #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
106 #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
107
108 #define AR_GPIOD_MASK 0x00001FFF
109 #define AR_GPIO_BIT(_gpio) (1 << (_gpio))
110
111 #define BASE_ACTIVATE_DELAY 100
112 #define RTC_PLL_SETTLE_DELAY 100
113 #define COEF_SCALE_S 24
114 #define HT40_CHANNEL_CENTER_SHIFT 10
115
116 #define ATH9K_ANTENNA0_CHAINMASK 0x1
117 #define ATH9K_ANTENNA1_CHAINMASK 0x2
118
119 #define ATH9K_NUM_DMA_DEBUG_REGS 8
120 #define ATH9K_NUM_QUEUES 10
121
122 #define MAX_RATE_POWER 63
123 #define AH_WAIT_TIMEOUT 100000 /* (us) */
124 #define AH_TSF_WRITE_TIMEOUT 100 /* (us) */
125 #define AH_TIME_QUANTUM 10
126 #define AR_KEYTABLE_SIZE 128
127 #define POWER_UP_TIME 10000
128 #define SPUR_RSSI_THRESH 40
129
130 #define CAB_TIMEOUT_VAL 10
131 #define BEACON_TIMEOUT_VAL 10
132 #define MIN_BEACON_TIMEOUT_VAL 1
133 #define SLEEP_SLOP 3
134
135 #define INIT_CONFIG_STATUS 0x00000000
136 #define INIT_RSSI_THR 0x00000700
137 #define INIT_BCON_CNTRL_REG 0x00000000
138
139 #define TU_TO_USEC(_tu) ((_tu) << 10)
140
141 #define ATH9K_HW_RX_HP_QDEPTH 16
142 #define ATH9K_HW_RX_LP_QDEPTH 128
143
144 enum ath_ini_subsys {
145 ATH_INI_PRE = 0,
146 ATH_INI_CORE,
147 ATH_INI_POST,
148 ATH_INI_NUM_SPLIT,
149 };
150
151 enum wireless_mode {
152 ATH9K_MODE_11A = 0,
153 ATH9K_MODE_11G,
154 ATH9K_MODE_11NA_HT20,
155 ATH9K_MODE_11NG_HT20,
156 ATH9K_MODE_11NA_HT40PLUS,
157 ATH9K_MODE_11NA_HT40MINUS,
158 ATH9K_MODE_11NG_HT40PLUS,
159 ATH9K_MODE_11NG_HT40MINUS,
160 ATH9K_MODE_MAX,
161 };
162
163 enum ath9k_hw_caps {
164 ATH9K_HW_CAP_MIC_AESCCM = BIT(0),
165 ATH9K_HW_CAP_MIC_CKIP = BIT(1),
166 ATH9K_HW_CAP_MIC_TKIP = BIT(2),
167 ATH9K_HW_CAP_CIPHER_AESCCM = BIT(3),
168 ATH9K_HW_CAP_CIPHER_CKIP = BIT(4),
169 ATH9K_HW_CAP_CIPHER_TKIP = BIT(5),
170 ATH9K_HW_CAP_VEOL = BIT(6),
171 ATH9K_HW_CAP_BSSIDMASK = BIT(7),
172 ATH9K_HW_CAP_MCAST_KEYSEARCH = BIT(8),
173 ATH9K_HW_CAP_HT = BIT(9),
174 ATH9K_HW_CAP_GTT = BIT(10),
175 ATH9K_HW_CAP_FASTCC = BIT(11),
176 ATH9K_HW_CAP_RFSILENT = BIT(12),
177 ATH9K_HW_CAP_CST = BIT(13),
178 ATH9K_HW_CAP_ENHANCEDPM = BIT(14),
179 ATH9K_HW_CAP_AUTOSLEEP = BIT(15),
180 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(16),
181 ATH9K_HW_CAP_EDMA = BIT(17),
182 ATH9K_HW_CAP_RAC_SUPPORTED = BIT(18),
183 };
184
185 enum ath9k_capability_type {
186 ATH9K_CAP_CIPHER = 0,
187 ATH9K_CAP_TKIP_MIC,
188 ATH9K_CAP_TKIP_SPLIT,
189 ATH9K_CAP_TXPOW,
190 ATH9K_CAP_MCAST_KEYSRCH,
191 ATH9K_CAP_DS
192 };
193
194 struct ath9k_hw_capabilities {
195 u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
196 DECLARE_BITMAP(wireless_modes, ATH9K_MODE_MAX); /* ATH9K_MODE_* */
197 u16 total_queues;
198 u16 keycache_size;
199 u16 low_5ghz_chan, high_5ghz_chan;
200 u16 low_2ghz_chan, high_2ghz_chan;
201 u16 rts_aggr_limit;
202 u8 tx_chainmask;
203 u8 rx_chainmask;
204 u16 tx_triglevel_max;
205 u16 reg_cap;
206 u8 num_gpio_pins;
207 u8 num_antcfg_2ghz;
208 u8 num_antcfg_5ghz;
209 u8 rx_hp_qdepth;
210 u8 rx_lp_qdepth;
211 u8 rx_status_len;
212 u8 tx_desc_len;
213 };
214
215 struct ath9k_ops_config {
216 int dma_beacon_response_time;
217 int sw_beacon_response_time;
218 int additional_swba_backoff;
219 int ack_6mb;
220 int cwm_ignore_extcca;
221 u8 pcie_powersave_enable;
222 u8 pcie_clock_req;
223 u32 pcie_waen;
224 u8 analog_shiftreg;
225 u8 ht_enable;
226 u32 ofdm_trig_low;
227 u32 ofdm_trig_high;
228 u32 cck_trig_high;
229 u32 cck_trig_low;
230 u32 enable_ani;
231 int serialize_regmode;
232 bool rx_intr_mitigation;
233 bool tx_intr_mitigation;
234 #define SPUR_DISABLE 0
235 #define SPUR_ENABLE_IOCTL 1
236 #define SPUR_ENABLE_EEPROM 2
237 #define AR_EEPROM_MODAL_SPURS 5
238 #define AR_SPUR_5413_1 1640
239 #define AR_SPUR_5413_2 1200
240 #define AR_NO_SPUR 0x8000
241 #define AR_BASE_FREQ_2GHZ 2300
242 #define AR_BASE_FREQ_5GHZ 4900
243 #define AR_SPUR_FEEQ_BOUND_HT40 19
244 #define AR_SPUR_FEEQ_BOUND_HT20 10
245 int spurmode;
246 u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
247 u8 max_txtrig_level;
248 };
249
250 enum ath9k_int {
251 ATH9K_INT_RX = 0x00000001,
252 ATH9K_INT_RXDESC = 0x00000002,
253 ATH9K_INT_RXHP = 0x00000001,
254 ATH9K_INT_RXLP = 0x00000002,
255 ATH9K_INT_RXNOFRM = 0x00000008,
256 ATH9K_INT_RXEOL = 0x00000010,
257 ATH9K_INT_RXORN = 0x00000020,
258 ATH9K_INT_TX = 0x00000040,
259 ATH9K_INT_TXDESC = 0x00000080,
260 ATH9K_INT_TIM_TIMER = 0x00000100,
261 ATH9K_INT_TXURN = 0x00000800,
262 ATH9K_INT_MIB = 0x00001000,
263 ATH9K_INT_RXPHY = 0x00004000,
264 ATH9K_INT_RXKCM = 0x00008000,
265 ATH9K_INT_SWBA = 0x00010000,
266 ATH9K_INT_BMISS = 0x00040000,
267 ATH9K_INT_BNR = 0x00100000,
268 ATH9K_INT_TIM = 0x00200000,
269 ATH9K_INT_DTIM = 0x00400000,
270 ATH9K_INT_DTIMSYNC = 0x00800000,
271 ATH9K_INT_GPIO = 0x01000000,
272 ATH9K_INT_CABEND = 0x02000000,
273 ATH9K_INT_TSFOOR = 0x04000000,
274 ATH9K_INT_GENTIMER = 0x08000000,
275 ATH9K_INT_CST = 0x10000000,
276 ATH9K_INT_GTT = 0x20000000,
277 ATH9K_INT_FATAL = 0x40000000,
278 ATH9K_INT_GLOBAL = 0x80000000,
279 ATH9K_INT_BMISC = ATH9K_INT_TIM |
280 ATH9K_INT_DTIM |
281 ATH9K_INT_DTIMSYNC |
282 ATH9K_INT_TSFOOR |
283 ATH9K_INT_CABEND,
284 ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
285 ATH9K_INT_RXDESC |
286 ATH9K_INT_RXEOL |
287 ATH9K_INT_RXORN |
288 ATH9K_INT_TXURN |
289 ATH9K_INT_TXDESC |
290 ATH9K_INT_MIB |
291 ATH9K_INT_RXPHY |
292 ATH9K_INT_RXKCM |
293 ATH9K_INT_SWBA |
294 ATH9K_INT_BMISS |
295 ATH9K_INT_GPIO,
296 ATH9K_INT_NOCARD = 0xffffffff
297 };
298
299 #define CHANNEL_CW_INT 0x00002
300 #define CHANNEL_CCK 0x00020
301 #define CHANNEL_OFDM 0x00040
302 #define CHANNEL_2GHZ 0x00080
303 #define CHANNEL_5GHZ 0x00100
304 #define CHANNEL_PASSIVE 0x00200
305 #define CHANNEL_DYN 0x00400
306 #define CHANNEL_HALF 0x04000
307 #define CHANNEL_QUARTER 0x08000
308 #define CHANNEL_HT20 0x10000
309 #define CHANNEL_HT40PLUS 0x20000
310 #define CHANNEL_HT40MINUS 0x40000
311
312 #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
313 #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
314 #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
315 #define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20)
316 #define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20)
317 #define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
318 #define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
319 #define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
320 #define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
321 #define CHANNEL_ALL \
322 (CHANNEL_OFDM| \
323 CHANNEL_CCK| \
324 CHANNEL_2GHZ | \
325 CHANNEL_5GHZ | \
326 CHANNEL_HT20 | \
327 CHANNEL_HT40PLUS | \
328 CHANNEL_HT40MINUS)
329
330 struct ath9k_channel {
331 struct ieee80211_channel *chan;
332 u16 channel;
333 u32 channelFlags;
334 u32 chanmode;
335 int32_t CalValid;
336 bool oneTimeCalsDone;
337 int8_t iCoff;
338 int8_t qCoff;
339 int16_t rawNoiseFloor;
340 };
341
342 #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
343 (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
344 (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
345 (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
346 #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
347 #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
348 #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
349 #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
350 #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
351 #define IS_CHAN_A_5MHZ_SPACED(_c) \
352 ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \
353 (((_c)->channel % 20) != 0) && \
354 (((_c)->channel % 10) != 0))
355
356 /* These macros check chanmode and not channelFlags */
357 #define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B)
358 #define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \
359 ((_c)->chanmode == CHANNEL_G_HT20))
360 #define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \
361 ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \
362 ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \
363 ((_c)->chanmode == CHANNEL_G_HT40MINUS))
364 #define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
365
366 enum ath9k_power_mode {
367 ATH9K_PM_AWAKE = 0,
368 ATH9K_PM_FULL_SLEEP,
369 ATH9K_PM_NETWORK_SLEEP,
370 ATH9K_PM_UNDEFINED
371 };
372
373 enum ath9k_tp_scale {
374 ATH9K_TP_SCALE_MAX = 0,
375 ATH9K_TP_SCALE_50,
376 ATH9K_TP_SCALE_25,
377 ATH9K_TP_SCALE_12,
378 ATH9K_TP_SCALE_MIN
379 };
380
381 enum ser_reg_mode {
382 SER_REG_MODE_OFF = 0,
383 SER_REG_MODE_ON = 1,
384 SER_REG_MODE_AUTO = 2,
385 };
386
387 enum ath9k_rx_qtype {
388 ATH9K_RX_QUEUE_HP,
389 ATH9K_RX_QUEUE_LP,
390 ATH9K_RX_QUEUE_MAX,
391 };
392
393 struct ath9k_beacon_state {
394 u32 bs_nexttbtt;
395 u32 bs_nextdtim;
396 u32 bs_intval;
397 #define ATH9K_BEACON_PERIOD 0x0000ffff
398 #define ATH9K_BEACON_ENA 0x00800000
399 #define ATH9K_BEACON_RESET_TSF 0x01000000
400 #define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */
401 u32 bs_dtimperiod;
402 u16 bs_cfpperiod;
403 u16 bs_cfpmaxduration;
404 u32 bs_cfpnext;
405 u16 bs_timoffset;
406 u16 bs_bmissthreshold;
407 u32 bs_sleepduration;
408 u32 bs_tsfoor_threshold;
409 };
410
411 struct chan_centers {
412 u16 synth_center;
413 u16 ctl_center;
414 u16 ext_center;
415 };
416
417 enum {
418 ATH9K_RESET_POWER_ON,
419 ATH9K_RESET_WARM,
420 ATH9K_RESET_COLD,
421 };
422
423 struct ath9k_hw_version {
424 u32 magic;
425 u16 devid;
426 u16 subvendorid;
427 u32 macVersion;
428 u16 macRev;
429 u16 phyRev;
430 u16 analog5GhzRev;
431 u16 analog2GhzRev;
432 u16 subsysid;
433 };
434
435 /* Generic TSF timer definitions */
436
437 #define ATH_MAX_GEN_TIMER 16
438
439 #define AR_GENTMR_BIT(_index) (1 << (_index))
440
441 /*
442 * Using de Bruijin sequence to to look up 1's index in a 32 bit number
443 * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001
444 */
445 #define debruijn32 0x077CB531U
446
447 struct ath_gen_timer_configuration {
448 u32 next_addr;
449 u32 period_addr;
450 u32 mode_addr;
451 u32 mode_mask;
452 };
453
454 struct ath_gen_timer {
455 void (*trigger)(void *arg);
456 void (*overflow)(void *arg);
457 void *arg;
458 u8 index;
459 };
460
461 struct ath_gen_timer_table {
462 u32 gen_timer_index[32];
463 struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER];
464 union {
465 unsigned long timer_bits;
466 u16 val;
467 } timer_mask;
468 };
469
470 /**
471 * struct ath_hw_private_ops - callbacks used internally by hardware code
472 *
473 * This structure contains private callbacks designed to only be used internally
474 * by the hardware core.
475 *
476 * @init_cal_settings: setup types of calibrations supported
477 * @init_cal: starts actual calibration
478 *
479 * @init_mode_regs: Initializes mode registers
480 * @init_mode_gain_regs: Initialize TX/RX gain registers
481 * @macversion_supported: If this specific mac revision is supported
482 *
483 * @rf_set_freq: change frequency
484 * @spur_mitigate_freq: spur mitigation
485 * @rf_alloc_ext_banks:
486 * @rf_free_ext_banks:
487 * @set_rf_regs:
488 * @compute_pll_control: compute the PLL control value to use for
489 * AR_RTC_PLL_CONTROL for a given channel
490 * @setup_calibration: set up calibration
491 * @iscal_supported: used to query if a type of calibration is supported
492 * @loadnf: load noise floor read from each chain on the CCA registers
493 */
494 struct ath_hw_private_ops {
495 /* Calibration ops */
496 void (*init_cal_settings)(struct ath_hw *ah);
497 bool (*init_cal)(struct ath_hw *ah, struct ath9k_channel *chan);
498
499 void (*init_mode_regs)(struct ath_hw *ah);
500 void (*init_mode_gain_regs)(struct ath_hw *ah);
501 bool (*macversion_supported)(u32 macversion);
502 void (*setup_calibration)(struct ath_hw *ah,
503 struct ath9k_cal_list *currCal);
504 bool (*iscal_supported)(struct ath_hw *ah,
505 enum ath9k_cal_types calType);
506
507 /* PHY ops */
508 int (*rf_set_freq)(struct ath_hw *ah,
509 struct ath9k_channel *chan);
510 void (*spur_mitigate_freq)(struct ath_hw *ah,
511 struct ath9k_channel *chan);
512 int (*rf_alloc_ext_banks)(struct ath_hw *ah);
513 void (*rf_free_ext_banks)(struct ath_hw *ah);
514 bool (*set_rf_regs)(struct ath_hw *ah,
515 struct ath9k_channel *chan,
516 u16 modesIndex);
517 void (*set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan);
518 void (*init_bb)(struct ath_hw *ah,
519 struct ath9k_channel *chan);
520 int (*process_ini)(struct ath_hw *ah, struct ath9k_channel *chan);
521 void (*olc_init)(struct ath_hw *ah);
522 void (*set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan);
523 void (*mark_phy_inactive)(struct ath_hw *ah);
524 void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan);
525 bool (*rfbus_req)(struct ath_hw *ah);
526 void (*rfbus_done)(struct ath_hw *ah);
527 void (*enable_rfkill)(struct ath_hw *ah);
528 void (*restore_chainmask)(struct ath_hw *ah);
529 void (*set_diversity)(struct ath_hw *ah, bool value);
530 u32 (*compute_pll_control)(struct ath_hw *ah,
531 struct ath9k_channel *chan);
532 bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd,
533 int param);
534 void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]);
535 void (*loadnf)(struct ath_hw *ah, struct ath9k_channel *chan);
536 };
537
538 /**
539 * struct ath_hw_ops - callbacks used by hardware code and driver code
540 *
541 * This structure contains callbacks designed to to be used internally by
542 * hardware code and also by the lower level driver.
543 *
544 * @config_pci_powersave:
545 * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC
546 */
547 struct ath_hw_ops {
548 void (*config_pci_powersave)(struct ath_hw *ah,
549 int restore,
550 int power_off);
551 void (*rx_enable)(struct ath_hw *ah);
552 void (*set_desc_link)(void *ds, u32 link);
553 void (*get_desc_link)(void *ds, u32 **link);
554 bool (*calibrate)(struct ath_hw *ah,
555 struct ath9k_channel *chan,
556 u8 rxchainmask,
557 bool longcal);
558 bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked);
559 void (*fill_txdesc)(struct ath_hw *ah, void *ds, u32 seglen,
560 bool is_firstseg, bool is_is_lastseg,
561 const void *ds0, dma_addr_t buf_addr,
562 unsigned int qcu);
563 int (*proc_txdesc)(struct ath_hw *ah, void *ds,
564 struct ath_tx_status *ts);
565 void (*set11n_txdesc)(struct ath_hw *ah, void *ds,
566 u32 pktLen, enum ath9k_pkt_type type,
567 u32 txPower, u32 keyIx,
568 enum ath9k_key_type keyType,
569 u32 flags);
570 void (*set11n_ratescenario)(struct ath_hw *ah, void *ds,
571 void *lastds,
572 u32 durUpdateEn, u32 rtsctsRate,
573 u32 rtsctsDuration,
574 struct ath9k_11n_rate_series series[],
575 u32 nseries, u32 flags);
576 void (*set11n_aggr_first)(struct ath_hw *ah, void *ds,
577 u32 aggrLen);
578 void (*set11n_aggr_middle)(struct ath_hw *ah, void *ds,
579 u32 numDelims);
580 void (*set11n_aggr_last)(struct ath_hw *ah, void *ds);
581 void (*clr11n_aggr)(struct ath_hw *ah, void *ds);
582 void (*set11n_burstduration)(struct ath_hw *ah, void *ds,
583 u32 burstDuration);
584 void (*set11n_virtualmorefrag)(struct ath_hw *ah, void *ds,
585 u32 vmf);
586 };
587
588 struct ath_hw {
589 struct ieee80211_hw *hw;
590 struct ath_common common;
591 struct ath9k_hw_version hw_version;
592 struct ath9k_ops_config config;
593 struct ath9k_hw_capabilities caps;
594 struct ath9k_channel channels[38];
595 struct ath9k_channel *curchan;
596
597 union {
598 struct ar5416_eeprom_def def;
599 struct ar5416_eeprom_4k map4k;
600 struct ar9287_eeprom map9287;
601 struct ar9300_eeprom ar9300_eep;
602 } eeprom;
603 const struct eeprom_ops *eep_ops;
604
605 bool sw_mgmt_crypto;
606 bool is_pciexpress;
607 bool need_an_top2_fixup;
608 u16 tx_trig_level;
609 s16 nf_2g_max;
610 s16 nf_2g_min;
611 s16 nf_5g_max;
612 s16 nf_5g_min;
613 u16 rfsilent;
614 u32 rfkill_gpio;
615 u32 rfkill_polarity;
616 u32 ah_flags;
617
618 bool htc_reset_init;
619
620 enum nl80211_iftype opmode;
621 enum ath9k_power_mode power_mode;
622
623 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
624 struct ath9k_pacal_info pacal_info;
625 struct ar5416Stats stats;
626 struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES];
627
628 int16_t curchan_rad_index;
629 enum ath9k_int imask;
630 u32 imrs2_reg;
631 u32 txok_interrupt_mask;
632 u32 txerr_interrupt_mask;
633 u32 txdesc_interrupt_mask;
634 u32 txeol_interrupt_mask;
635 u32 txurn_interrupt_mask;
636 bool chip_fullsleep;
637 u32 atim_window;
638
639 /* Calibration */
640 enum ath9k_cal_types supp_cals;
641 struct ath9k_cal_list iq_caldata;
642 struct ath9k_cal_list adcgain_caldata;
643 struct ath9k_cal_list adcdc_calinitdata;
644 struct ath9k_cal_list adcdc_caldata;
645 struct ath9k_cal_list tempCompCalData;
646 struct ath9k_cal_list *cal_list;
647 struct ath9k_cal_list *cal_list_last;
648 struct ath9k_cal_list *cal_list_curr;
649 #define totalPowerMeasI meas0.unsign
650 #define totalPowerMeasQ meas1.unsign
651 #define totalIqCorrMeas meas2.sign
652 #define totalAdcIOddPhase meas0.unsign
653 #define totalAdcIEvenPhase meas1.unsign
654 #define totalAdcQOddPhase meas2.unsign
655 #define totalAdcQEvenPhase meas3.unsign
656 #define totalAdcDcOffsetIOddPhase meas0.sign
657 #define totalAdcDcOffsetIEvenPhase meas1.sign
658 #define totalAdcDcOffsetQOddPhase meas2.sign
659 #define totalAdcDcOffsetQEvenPhase meas3.sign
660 union {
661 u32 unsign[AR5416_MAX_CHAINS];
662 int32_t sign[AR5416_MAX_CHAINS];
663 } meas0;
664 union {
665 u32 unsign[AR5416_MAX_CHAINS];
666 int32_t sign[AR5416_MAX_CHAINS];
667 } meas1;
668 union {
669 u32 unsign[AR5416_MAX_CHAINS];
670 int32_t sign[AR5416_MAX_CHAINS];
671 } meas2;
672 union {
673 u32 unsign[AR5416_MAX_CHAINS];
674 int32_t sign[AR5416_MAX_CHAINS];
675 } meas3;
676 u16 cal_samples;
677
678 u32 sta_id1_defaults;
679 u32 misc_mode;
680 enum {
681 AUTO_32KHZ,
682 USE_32KHZ,
683 DONT_USE_32KHZ,
684 } enable_32kHz_clock;
685
686 /* Private to hardware code */
687 struct ath_hw_private_ops private_ops;
688 /* Accessed by the lower level driver */
689 struct ath_hw_ops ops;
690
691 /* Used to program the radio on non single-chip devices */
692 u32 *analogBank0Data;
693 u32 *analogBank1Data;
694 u32 *analogBank2Data;
695 u32 *analogBank3Data;
696 u32 *analogBank6Data;
697 u32 *analogBank6TPCData;
698 u32 *analogBank7Data;
699 u32 *addac5416_21;
700 u32 *bank6Temp;
701
702 int16_t txpower_indexoffset;
703 int coverage_class;
704 u32 beacon_interval;
705 u32 slottime;
706 u32 globaltxtimeout;
707
708 /* ANI */
709 u32 proc_phyerr;
710 u32 aniperiod;
711 struct ar5416AniState *curani;
712 struct ar5416AniState ani[255];
713 int totalSizeDesired[5];
714 int coarse_high[5];
715 int coarse_low[5];
716 int firpwr[5];
717 enum ath9k_ani_cmd ani_function;
718
719 /* Bluetooth coexistance */
720 struct ath_btcoex_hw btcoex_hw;
721
722 u32 intr_txqs;
723 u8 txchainmask;
724 u8 rxchainmask;
725
726 u32 originalGain[22];
727 int initPDADC;
728 int PDADCdelta;
729 u8 led_pin;
730
731 struct ar5416IniArray iniModes;
732 struct ar5416IniArray iniCommon;
733 struct ar5416IniArray iniBank0;
734 struct ar5416IniArray iniBB_RfGain;
735 struct ar5416IniArray iniBank1;
736 struct ar5416IniArray iniBank2;
737 struct ar5416IniArray iniBank3;
738 struct ar5416IniArray iniBank6;
739 struct ar5416IniArray iniBank6TPC;
740 struct ar5416IniArray iniBank7;
741 struct ar5416IniArray iniAddac;
742 struct ar5416IniArray iniPcieSerdes;
743 struct ar5416IniArray iniPcieSerdesLowPower;
744 struct ar5416IniArray iniModesAdditional;
745 struct ar5416IniArray iniModesRxGain;
746 struct ar5416IniArray iniModesTxGain;
747 struct ar5416IniArray iniModes_9271_1_0_only;
748 struct ar5416IniArray iniCckfirNormal;
749 struct ar5416IniArray iniCckfirJapan2484;
750 struct ar5416IniArray iniCommon_normal_cck_fir_coeff_9271;
751 struct ar5416IniArray iniCommon_japan_2484_cck_fir_coeff_9271;
752 struct ar5416IniArray iniModes_9271_ANI_reg;
753 struct ar5416IniArray iniModes_high_power_tx_gain_9271;
754 struct ar5416IniArray iniModes_normal_power_tx_gain_9271;
755
756 struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT];
757 struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT];
758 struct ar5416IniArray iniRadio[ATH_INI_NUM_SPLIT];
759 struct ar5416IniArray iniSOC[ATH_INI_NUM_SPLIT];
760
761 u32 intr_gen_timer_trigger;
762 u32 intr_gen_timer_thresh;
763 struct ath_gen_timer_table hw_gen_timers;
764 };
765
766 static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
767 {
768 return &ah->common;
769 }
770
771 static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah)
772 {
773 return &(ath9k_hw_common(ah)->regulatory);
774 }
775
776 static inline struct ath_hw_private_ops *ath9k_hw_private_ops(struct ath_hw *ah)
777 {
778 return &ah->private_ops;
779 }
780
781 static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah)
782 {
783 return &ah->ops;
784 }
785
786 /* Initialization, Detach, Reset */
787 const char *ath9k_hw_probe(u16 vendorid, u16 devid);
788 void ath9k_hw_deinit(struct ath_hw *ah);
789 int ath9k_hw_init(struct ath_hw *ah);
790 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
791 bool bChannelChange);
792 int ath9k_hw_fill_cap_info(struct ath_hw *ah);
793 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
794 u32 capability, u32 *result);
795 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
796 u32 capability, u32 setting, int *status);
797 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan);
798
799 /* Key Cache Management */
800 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry);
801 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac);
802 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
803 const struct ath9k_keyval *k,
804 const u8 *mac);
805 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry);
806
807 /* GPIO / RFKILL / Antennae */
808 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio);
809 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio);
810 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
811 u32 ah_signal_type);
812 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val);
813 u32 ath9k_hw_getdefantenna(struct ath_hw *ah);
814 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna);
815
816 /* General Operation */
817 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout);
818 u32 ath9k_hw_reverse_bits(u32 val, u32 n);
819 bool ath9k_get_channel_edges(struct ath_hw *ah, u16 flags, u16 *low, u16 *high);
820 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
821 u8 phy, int kbps,
822 u32 frameLen, u16 rateix, bool shortPreamble);
823 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
824 struct ath9k_channel *chan,
825 struct chan_centers *centers);
826 u32 ath9k_hw_getrxfilter(struct ath_hw *ah);
827 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits);
828 bool ath9k_hw_phy_disable(struct ath_hw *ah);
829 bool ath9k_hw_disable(struct ath_hw *ah);
830 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit);
831 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac);
832 void ath9k_hw_setopmode(struct ath_hw *ah);
833 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1);
834 void ath9k_hw_setbssidmask(struct ath_hw *ah);
835 void ath9k_hw_write_associd(struct ath_hw *ah);
836 u64 ath9k_hw_gettsf64(struct ath_hw *ah);
837 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64);
838 void ath9k_hw_reset_tsf(struct ath_hw *ah);
839 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting);
840 u64 ath9k_hw_extend_tsf(struct ath_hw *ah, u32 rstamp);
841 void ath9k_hw_init_global_settings(struct ath_hw *ah);
842 void ath9k_hw_set11nmac2040(struct ath_hw *ah);
843 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period);
844 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
845 const struct ath9k_beacon_state *bs);
846
847 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode);
848
849 /* Generic hw timer primitives */
850 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
851 void (*trigger)(void *),
852 void (*overflow)(void *),
853 void *arg,
854 u8 timer_index);
855 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
856 struct ath_gen_timer *timer,
857 u32 timer_next,
858 u32 timer_period);
859 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer);
860
861 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer);
862 void ath_gen_timer_isr(struct ath_hw *hw);
863 u32 ath9k_hw_gettsf32(struct ath_hw *ah);
864
865 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len);
866
867 /* HTC */
868 void ath9k_hw_htc_resetinit(struct ath_hw *ah);
869
870 /* PHY */
871 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
872 u32 *coef_mantissa, u32 *coef_exponent);
873
874 /*
875 * Code Specific to AR5008, AR9001 or AR9002,
876 * we stuff these here to avoid callbacks for AR9003.
877 */
878 void ar9002_hw_cck_chan14_spread(struct ath_hw *ah);
879 int ar9002_hw_rf_claim(struct ath_hw *ah);
880 void ar9002_hw_enable_async_fifo(struct ath_hw *ah);
881 void ar9002_hw_enable_wep_aggregation(struct ath_hw *ah);
882
883 /*
884 * Code specifric to AR9003, we stuff these here to avoid callbacks
885 * for older families
886 */
887 void ar9003_hw_set_nf_limits(struct ath_hw *ah);
888
889 /* Hardware family op attach helpers */
890 void ar5008_hw_attach_phy_ops(struct ath_hw *ah);
891 void ar9002_hw_attach_phy_ops(struct ath_hw *ah);
892 void ar9003_hw_attach_phy_ops(struct ath_hw *ah);
893
894 void ar9002_hw_attach_calib_ops(struct ath_hw *ah);
895 void ar9003_hw_attach_calib_ops(struct ath_hw *ah);
896
897 void ar9002_hw_attach_ops(struct ath_hw *ah);
898 void ar9003_hw_attach_ops(struct ath_hw *ah);
899
900 #define ATH_PCIE_CAP_LINK_CTRL 0x70
901 #define ATH_PCIE_CAP_LINK_L0S 1
902 #define ATH_PCIE_CAP_LINK_L1 2
903
904 #endif
Linux kernel - Deliverables
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