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ath9k_hw: complete AR9003 calibration
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / hw.h
1 /*
2 * Copyright (c) 2008-2010 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #ifndef HW_H
18 #define HW_H
19
20 #include <linux/if_ether.h>
21 #include <linux/delay.h>
22 #include <linux/io.h>
23
24 #include "mac.h"
25 #include "ani.h"
26 #include "eeprom.h"
27 #include "calib.h"
28 #include "reg.h"
29 #include "phy.h"
30 #include "btcoex.h"
31 #include "ar9003_mac.h"
32
33 #include "../regd.h"
34 #include "../debug.h"
35
36 #define ATHEROS_VENDOR_ID 0x168c
37
38 #define AR5416_DEVID_PCI 0x0023
39 #define AR5416_DEVID_PCIE 0x0024
40 #define AR9160_DEVID_PCI 0x0027
41 #define AR9280_DEVID_PCI 0x0029
42 #define AR9280_DEVID_PCIE 0x002a
43 #define AR9285_DEVID_PCIE 0x002b
44 #define AR2427_DEVID_PCIE 0x002c
45 #define AR9287_DEVID_PCI 0x002d
46 #define AR9287_DEVID_PCIE 0x002e
47 #define AR9300_DEVID_PCIE 0x0030
48
49 #define AR5416_AR9100_DEVID 0x000b
50
51 #define AR_SUBVENDOR_ID_NOG 0x0e11
52 #define AR_SUBVENDOR_ID_NEW_A 0x7065
53 #define AR5416_MAGIC 0x19641014
54
55 #define AR9280_COEX2WIRE_SUBSYSID 0x309b
56 #define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa
57 #define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab
58
59 #define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1)
60
61 #define ATH_DEFAULT_NOISE_FLOOR -95
62
63 #define ATH9K_RSSI_BAD -128
64
65 /* Register read/write primitives */
66 #define REG_WRITE(_ah, _reg, _val) \
67 ath9k_hw_common(_ah)->ops->write((_ah), (_val), (_reg))
68
69 #define REG_READ(_ah, _reg) \
70 ath9k_hw_common(_ah)->ops->read((_ah), (_reg))
71
72 #define SM(_v, _f) (((_v) << _f##_S) & _f)
73 #define MS(_v, _f) (((_v) & _f) >> _f##_S)
74 #define REG_RMW(_a, _r, _set, _clr) \
75 REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set))
76 #define REG_RMW_FIELD(_a, _r, _f, _v) \
77 REG_WRITE(_a, _r, \
78 (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f))
79 #define REG_SET_BIT(_a, _r, _f) \
80 REG_WRITE(_a, _r, REG_READ(_a, _r) | _f)
81 #define REG_CLR_BIT(_a, _r, _f) \
82 REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f)
83
84 #define DO_DELAY(x) do { \
85 if ((++(x) % 64) == 0) \
86 udelay(1); \
87 } while (0)
88
89 #define REG_WRITE_ARRAY(iniarray, column, regWr) do { \
90 int r; \
91 for (r = 0; r < ((iniarray)->ia_rows); r++) { \
92 REG_WRITE(ah, INI_RA((iniarray), (r), 0), \
93 INI_RA((iniarray), r, (column))); \
94 DO_DELAY(regWr); \
95 } \
96 } while (0)
97
98 #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
99 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
100 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
101 #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3
102 #define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4
103 #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
104 #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
105
106 #define AR_GPIOD_MASK 0x00001FFF
107 #define AR_GPIO_BIT(_gpio) (1 << (_gpio))
108
109 #define BASE_ACTIVATE_DELAY 100
110 #define RTC_PLL_SETTLE_DELAY 100
111 #define COEF_SCALE_S 24
112 #define HT40_CHANNEL_CENTER_SHIFT 10
113
114 #define ATH9K_ANTENNA0_CHAINMASK 0x1
115 #define ATH9K_ANTENNA1_CHAINMASK 0x2
116
117 #define ATH9K_NUM_DMA_DEBUG_REGS 8
118 #define ATH9K_NUM_QUEUES 10
119
120 #define MAX_RATE_POWER 63
121 #define AH_WAIT_TIMEOUT 100000 /* (us) */
122 #define AH_TSF_WRITE_TIMEOUT 100 /* (us) */
123 #define AH_TIME_QUANTUM 10
124 #define AR_KEYTABLE_SIZE 128
125 #define POWER_UP_TIME 10000
126 #define SPUR_RSSI_THRESH 40
127
128 #define CAB_TIMEOUT_VAL 10
129 #define BEACON_TIMEOUT_VAL 10
130 #define MIN_BEACON_TIMEOUT_VAL 1
131 #define SLEEP_SLOP 3
132
133 #define INIT_CONFIG_STATUS 0x00000000
134 #define INIT_RSSI_THR 0x00000700
135 #define INIT_BCON_CNTRL_REG 0x00000000
136
137 #define TU_TO_USEC(_tu) ((_tu) << 10)
138
139 #define ATH9K_HW_RX_HP_QDEPTH 16
140 #define ATH9K_HW_RX_LP_QDEPTH 128
141
142 enum ath_ini_subsys {
143 ATH_INI_PRE = 0,
144 ATH_INI_CORE,
145 ATH_INI_POST,
146 ATH_INI_NUM_SPLIT,
147 };
148
149 enum wireless_mode {
150 ATH9K_MODE_11A = 0,
151 ATH9K_MODE_11G,
152 ATH9K_MODE_11NA_HT20,
153 ATH9K_MODE_11NG_HT20,
154 ATH9K_MODE_11NA_HT40PLUS,
155 ATH9K_MODE_11NA_HT40MINUS,
156 ATH9K_MODE_11NG_HT40PLUS,
157 ATH9K_MODE_11NG_HT40MINUS,
158 ATH9K_MODE_MAX,
159 };
160
161 enum ath9k_hw_caps {
162 ATH9K_HW_CAP_MIC_AESCCM = BIT(0),
163 ATH9K_HW_CAP_MIC_CKIP = BIT(1),
164 ATH9K_HW_CAP_MIC_TKIP = BIT(2),
165 ATH9K_HW_CAP_CIPHER_AESCCM = BIT(3),
166 ATH9K_HW_CAP_CIPHER_CKIP = BIT(4),
167 ATH9K_HW_CAP_CIPHER_TKIP = BIT(5),
168 ATH9K_HW_CAP_VEOL = BIT(6),
169 ATH9K_HW_CAP_BSSIDMASK = BIT(7),
170 ATH9K_HW_CAP_MCAST_KEYSEARCH = BIT(8),
171 ATH9K_HW_CAP_HT = BIT(9),
172 ATH9K_HW_CAP_GTT = BIT(10),
173 ATH9K_HW_CAP_FASTCC = BIT(11),
174 ATH9K_HW_CAP_RFSILENT = BIT(12),
175 ATH9K_HW_CAP_CST = BIT(13),
176 ATH9K_HW_CAP_ENHANCEDPM = BIT(14),
177 ATH9K_HW_CAP_AUTOSLEEP = BIT(15),
178 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(16),
179 ATH9K_HW_CAP_EDMA = BIT(17),
180 };
181
182 enum ath9k_capability_type {
183 ATH9K_CAP_CIPHER = 0,
184 ATH9K_CAP_TKIP_MIC,
185 ATH9K_CAP_TKIP_SPLIT,
186 ATH9K_CAP_TXPOW,
187 ATH9K_CAP_MCAST_KEYSRCH,
188 ATH9K_CAP_DS
189 };
190
191 struct ath9k_hw_capabilities {
192 u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
193 DECLARE_BITMAP(wireless_modes, ATH9K_MODE_MAX); /* ATH9K_MODE_* */
194 u16 total_queues;
195 u16 keycache_size;
196 u16 low_5ghz_chan, high_5ghz_chan;
197 u16 low_2ghz_chan, high_2ghz_chan;
198 u16 rts_aggr_limit;
199 u8 tx_chainmask;
200 u8 rx_chainmask;
201 u16 tx_triglevel_max;
202 u16 reg_cap;
203 u8 num_gpio_pins;
204 u8 num_antcfg_2ghz;
205 u8 num_antcfg_5ghz;
206 u8 rx_hp_qdepth;
207 u8 rx_lp_qdepth;
208 u8 rx_status_len;
209 u8 tx_desc_len;
210 };
211
212 struct ath9k_ops_config {
213 int dma_beacon_response_time;
214 int sw_beacon_response_time;
215 int additional_swba_backoff;
216 int ack_6mb;
217 int cwm_ignore_extcca;
218 u8 pcie_powersave_enable;
219 u8 pcie_clock_req;
220 u32 pcie_waen;
221 u8 analog_shiftreg;
222 u8 ht_enable;
223 u32 ofdm_trig_low;
224 u32 ofdm_trig_high;
225 u32 cck_trig_high;
226 u32 cck_trig_low;
227 u32 enable_ani;
228 int serialize_regmode;
229 bool rx_intr_mitigation;
230 bool tx_intr_mitigation;
231 #define SPUR_DISABLE 0
232 #define SPUR_ENABLE_IOCTL 1
233 #define SPUR_ENABLE_EEPROM 2
234 #define AR_EEPROM_MODAL_SPURS 5
235 #define AR_SPUR_5413_1 1640
236 #define AR_SPUR_5413_2 1200
237 #define AR_NO_SPUR 0x8000
238 #define AR_BASE_FREQ_2GHZ 2300
239 #define AR_BASE_FREQ_5GHZ 4900
240 #define AR_SPUR_FEEQ_BOUND_HT40 19
241 #define AR_SPUR_FEEQ_BOUND_HT20 10
242 int spurmode;
243 u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
244 u8 max_txtrig_level;
245 };
246
247 enum ath9k_int {
248 ATH9K_INT_RX = 0x00000001,
249 ATH9K_INT_RXDESC = 0x00000002,
250 ATH9K_INT_RXHP = 0x00000001,
251 ATH9K_INT_RXLP = 0x00000002,
252 ATH9K_INT_RXNOFRM = 0x00000008,
253 ATH9K_INT_RXEOL = 0x00000010,
254 ATH9K_INT_RXORN = 0x00000020,
255 ATH9K_INT_TX = 0x00000040,
256 ATH9K_INT_TXDESC = 0x00000080,
257 ATH9K_INT_TIM_TIMER = 0x00000100,
258 ATH9K_INT_TXURN = 0x00000800,
259 ATH9K_INT_MIB = 0x00001000,
260 ATH9K_INT_RXPHY = 0x00004000,
261 ATH9K_INT_RXKCM = 0x00008000,
262 ATH9K_INT_SWBA = 0x00010000,
263 ATH9K_INT_BMISS = 0x00040000,
264 ATH9K_INT_BNR = 0x00100000,
265 ATH9K_INT_TIM = 0x00200000,
266 ATH9K_INT_DTIM = 0x00400000,
267 ATH9K_INT_DTIMSYNC = 0x00800000,
268 ATH9K_INT_GPIO = 0x01000000,
269 ATH9K_INT_CABEND = 0x02000000,
270 ATH9K_INT_TSFOOR = 0x04000000,
271 ATH9K_INT_GENTIMER = 0x08000000,
272 ATH9K_INT_CST = 0x10000000,
273 ATH9K_INT_GTT = 0x20000000,
274 ATH9K_INT_FATAL = 0x40000000,
275 ATH9K_INT_GLOBAL = 0x80000000,
276 ATH9K_INT_BMISC = ATH9K_INT_TIM |
277 ATH9K_INT_DTIM |
278 ATH9K_INT_DTIMSYNC |
279 ATH9K_INT_TSFOOR |
280 ATH9K_INT_CABEND,
281 ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
282 ATH9K_INT_RXDESC |
283 ATH9K_INT_RXEOL |
284 ATH9K_INT_RXORN |
285 ATH9K_INT_TXURN |
286 ATH9K_INT_TXDESC |
287 ATH9K_INT_MIB |
288 ATH9K_INT_RXPHY |
289 ATH9K_INT_RXKCM |
290 ATH9K_INT_SWBA |
291 ATH9K_INT_BMISS |
292 ATH9K_INT_GPIO,
293 ATH9K_INT_NOCARD = 0xffffffff
294 };
295
296 #define CHANNEL_CW_INT 0x00002
297 #define CHANNEL_CCK 0x00020
298 #define CHANNEL_OFDM 0x00040
299 #define CHANNEL_2GHZ 0x00080
300 #define CHANNEL_5GHZ 0x00100
301 #define CHANNEL_PASSIVE 0x00200
302 #define CHANNEL_DYN 0x00400
303 #define CHANNEL_HALF 0x04000
304 #define CHANNEL_QUARTER 0x08000
305 #define CHANNEL_HT20 0x10000
306 #define CHANNEL_HT40PLUS 0x20000
307 #define CHANNEL_HT40MINUS 0x40000
308
309 #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
310 #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
311 #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
312 #define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20)
313 #define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20)
314 #define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
315 #define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
316 #define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
317 #define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
318 #define CHANNEL_ALL \
319 (CHANNEL_OFDM| \
320 CHANNEL_CCK| \
321 CHANNEL_2GHZ | \
322 CHANNEL_5GHZ | \
323 CHANNEL_HT20 | \
324 CHANNEL_HT40PLUS | \
325 CHANNEL_HT40MINUS)
326
327 struct ath9k_channel {
328 struct ieee80211_channel *chan;
329 u16 channel;
330 u32 channelFlags;
331 u32 chanmode;
332 int32_t CalValid;
333 bool oneTimeCalsDone;
334 int8_t iCoff;
335 int8_t qCoff;
336 int16_t rawNoiseFloor;
337 };
338
339 #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
340 (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
341 (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
342 (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
343 #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
344 #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
345 #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
346 #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
347 #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
348 #define IS_CHAN_A_5MHZ_SPACED(_c) \
349 ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \
350 (((_c)->channel % 20) != 0) && \
351 (((_c)->channel % 10) != 0))
352
353 /* These macros check chanmode and not channelFlags */
354 #define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B)
355 #define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \
356 ((_c)->chanmode == CHANNEL_G_HT20))
357 #define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \
358 ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \
359 ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \
360 ((_c)->chanmode == CHANNEL_G_HT40MINUS))
361 #define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
362
363 enum ath9k_power_mode {
364 ATH9K_PM_AWAKE = 0,
365 ATH9K_PM_FULL_SLEEP,
366 ATH9K_PM_NETWORK_SLEEP,
367 ATH9K_PM_UNDEFINED
368 };
369
370 enum ath9k_tp_scale {
371 ATH9K_TP_SCALE_MAX = 0,
372 ATH9K_TP_SCALE_50,
373 ATH9K_TP_SCALE_25,
374 ATH9K_TP_SCALE_12,
375 ATH9K_TP_SCALE_MIN
376 };
377
378 enum ser_reg_mode {
379 SER_REG_MODE_OFF = 0,
380 SER_REG_MODE_ON = 1,
381 SER_REG_MODE_AUTO = 2,
382 };
383
384 enum ath9k_rx_qtype {
385 ATH9K_RX_QUEUE_HP,
386 ATH9K_RX_QUEUE_LP,
387 ATH9K_RX_QUEUE_MAX,
388 };
389
390 struct ath9k_beacon_state {
391 u32 bs_nexttbtt;
392 u32 bs_nextdtim;
393 u32 bs_intval;
394 #define ATH9K_BEACON_PERIOD 0x0000ffff
395 #define ATH9K_BEACON_ENA 0x00800000
396 #define ATH9K_BEACON_RESET_TSF 0x01000000
397 #define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */
398 u32 bs_dtimperiod;
399 u16 bs_cfpperiod;
400 u16 bs_cfpmaxduration;
401 u32 bs_cfpnext;
402 u16 bs_timoffset;
403 u16 bs_bmissthreshold;
404 u32 bs_sleepduration;
405 u32 bs_tsfoor_threshold;
406 };
407
408 struct chan_centers {
409 u16 synth_center;
410 u16 ctl_center;
411 u16 ext_center;
412 };
413
414 enum {
415 ATH9K_RESET_POWER_ON,
416 ATH9K_RESET_WARM,
417 ATH9K_RESET_COLD,
418 };
419
420 struct ath9k_hw_version {
421 u32 magic;
422 u16 devid;
423 u16 subvendorid;
424 u32 macVersion;
425 u16 macRev;
426 u16 phyRev;
427 u16 analog5GhzRev;
428 u16 analog2GhzRev;
429 u16 subsysid;
430 };
431
432 /* Generic TSF timer definitions */
433
434 #define ATH_MAX_GEN_TIMER 16
435
436 #define AR_GENTMR_BIT(_index) (1 << (_index))
437
438 /*
439 * Using de Bruijin sequence to to look up 1's index in a 32 bit number
440 * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001
441 */
442 #define debruijn32 0x077CB531U
443
444 struct ath_gen_timer_configuration {
445 u32 next_addr;
446 u32 period_addr;
447 u32 mode_addr;
448 u32 mode_mask;
449 };
450
451 struct ath_gen_timer {
452 void (*trigger)(void *arg);
453 void (*overflow)(void *arg);
454 void *arg;
455 u8 index;
456 };
457
458 struct ath_gen_timer_table {
459 u32 gen_timer_index[32];
460 struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER];
461 union {
462 unsigned long timer_bits;
463 u16 val;
464 } timer_mask;
465 };
466
467 /**
468 * struct ath_hw_private_ops - callbacks used internally by hardware code
469 *
470 * This structure contains private callbacks designed to only be used internally
471 * by the hardware core.
472 *
473 * @init_cal_settings: setup types of calibrations supported
474 * @init_cal: starts actual calibration
475 *
476 * @init_mode_regs: Initializes mode registers
477 * @init_mode_gain_regs: Initialize TX/RX gain registers
478 * @macversion_supported: If this specific mac revision is supported
479 *
480 * @rf_set_freq: change frequency
481 * @spur_mitigate_freq: spur mitigation
482 * @rf_alloc_ext_banks:
483 * @rf_free_ext_banks:
484 * @set_rf_regs:
485 * @compute_pll_control: compute the PLL control value to use for
486 * AR_RTC_PLL_CONTROL for a given channel
487 * @setup_calibration: set up calibration
488 * @iscal_supported: used to query if a type of calibration is supported
489 * @loadnf: load noise floor read from each chain on the CCA registers
490 */
491 struct ath_hw_private_ops {
492 /* Calibration ops */
493 void (*init_cal_settings)(struct ath_hw *ah);
494 bool (*init_cal)(struct ath_hw *ah, struct ath9k_channel *chan);
495
496 void (*init_mode_regs)(struct ath_hw *ah);
497 void (*init_mode_gain_regs)(struct ath_hw *ah);
498 bool (*macversion_supported)(u32 macversion);
499 void (*setup_calibration)(struct ath_hw *ah,
500 struct ath9k_cal_list *currCal);
501 bool (*iscal_supported)(struct ath_hw *ah,
502 enum ath9k_cal_types calType);
503
504 /* PHY ops */
505 int (*rf_set_freq)(struct ath_hw *ah,
506 struct ath9k_channel *chan);
507 void (*spur_mitigate_freq)(struct ath_hw *ah,
508 struct ath9k_channel *chan);
509 int (*rf_alloc_ext_banks)(struct ath_hw *ah);
510 void (*rf_free_ext_banks)(struct ath_hw *ah);
511 bool (*set_rf_regs)(struct ath_hw *ah,
512 struct ath9k_channel *chan,
513 u16 modesIndex);
514 void (*set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan);
515 void (*init_bb)(struct ath_hw *ah,
516 struct ath9k_channel *chan);
517 int (*process_ini)(struct ath_hw *ah, struct ath9k_channel *chan);
518 void (*olc_init)(struct ath_hw *ah);
519 void (*set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan);
520 void (*mark_phy_inactive)(struct ath_hw *ah);
521 void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan);
522 bool (*rfbus_req)(struct ath_hw *ah);
523 void (*rfbus_done)(struct ath_hw *ah);
524 void (*enable_rfkill)(struct ath_hw *ah);
525 void (*restore_chainmask)(struct ath_hw *ah);
526 void (*set_diversity)(struct ath_hw *ah, bool value);
527 u32 (*compute_pll_control)(struct ath_hw *ah,
528 struct ath9k_channel *chan);
529 bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd,
530 int param);
531 void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]);
532 void (*loadnf)(struct ath_hw *ah, struct ath9k_channel *chan);
533 };
534
535 /**
536 * struct ath_hw_ops - callbacks used by hardware code and driver code
537 *
538 * This structure contains callbacks designed to to be used internally by
539 * hardware code and also by the lower level driver.
540 *
541 * @config_pci_powersave:
542 * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC
543 */
544 struct ath_hw_ops {
545 void (*config_pci_powersave)(struct ath_hw *ah,
546 int restore,
547 int power_off);
548 void (*rx_enable)(struct ath_hw *ah);
549 void (*set_desc_link)(void *ds, u32 link);
550 void (*get_desc_link)(void *ds, u32 **link);
551 bool (*calibrate)(struct ath_hw *ah,
552 struct ath9k_channel *chan,
553 u8 rxchainmask,
554 bool longcal);
555 bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked);
556 };
557
558 struct ath_hw {
559 struct ieee80211_hw *hw;
560 struct ath_common common;
561 struct ath9k_hw_version hw_version;
562 struct ath9k_ops_config config;
563 struct ath9k_hw_capabilities caps;
564 struct ath9k_channel channels[38];
565 struct ath9k_channel *curchan;
566
567 union {
568 struct ar5416_eeprom_def def;
569 struct ar5416_eeprom_4k map4k;
570 struct ar9287_eeprom map9287;
571 } eeprom;
572 const struct eeprom_ops *eep_ops;
573
574 bool sw_mgmt_crypto;
575 bool is_pciexpress;
576 bool need_an_top2_fixup;
577 u16 tx_trig_level;
578 s16 nf_2g_max;
579 s16 nf_2g_min;
580 s16 nf_5g_max;
581 s16 nf_5g_min;
582 u16 rfsilent;
583 u32 rfkill_gpio;
584 u32 rfkill_polarity;
585 u32 ah_flags;
586
587 bool htc_reset_init;
588
589 enum nl80211_iftype opmode;
590 enum ath9k_power_mode power_mode;
591
592 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
593 struct ath9k_pacal_info pacal_info;
594 struct ar5416Stats stats;
595 struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES];
596
597 int16_t curchan_rad_index;
598 enum ath9k_int imask;
599 u32 imrs2_reg;
600 u32 txok_interrupt_mask;
601 u32 txerr_interrupt_mask;
602 u32 txdesc_interrupt_mask;
603 u32 txeol_interrupt_mask;
604 u32 txurn_interrupt_mask;
605 bool chip_fullsleep;
606 u32 atim_window;
607
608 /* Calibration */
609 enum ath9k_cal_types supp_cals;
610 struct ath9k_cal_list iq_caldata;
611 struct ath9k_cal_list adcgain_caldata;
612 struct ath9k_cal_list adcdc_calinitdata;
613 struct ath9k_cal_list adcdc_caldata;
614 struct ath9k_cal_list tempCompCalData;
615 struct ath9k_cal_list *cal_list;
616 struct ath9k_cal_list *cal_list_last;
617 struct ath9k_cal_list *cal_list_curr;
618 #define totalPowerMeasI meas0.unsign
619 #define totalPowerMeasQ meas1.unsign
620 #define totalIqCorrMeas meas2.sign
621 #define totalAdcIOddPhase meas0.unsign
622 #define totalAdcIEvenPhase meas1.unsign
623 #define totalAdcQOddPhase meas2.unsign
624 #define totalAdcQEvenPhase meas3.unsign
625 #define totalAdcDcOffsetIOddPhase meas0.sign
626 #define totalAdcDcOffsetIEvenPhase meas1.sign
627 #define totalAdcDcOffsetQOddPhase meas2.sign
628 #define totalAdcDcOffsetQEvenPhase meas3.sign
629 union {
630 u32 unsign[AR5416_MAX_CHAINS];
631 int32_t sign[AR5416_MAX_CHAINS];
632 } meas0;
633 union {
634 u32 unsign[AR5416_MAX_CHAINS];
635 int32_t sign[AR5416_MAX_CHAINS];
636 } meas1;
637 union {
638 u32 unsign[AR5416_MAX_CHAINS];
639 int32_t sign[AR5416_MAX_CHAINS];
640 } meas2;
641 union {
642 u32 unsign[AR5416_MAX_CHAINS];
643 int32_t sign[AR5416_MAX_CHAINS];
644 } meas3;
645 u16 cal_samples;
646
647 u32 sta_id1_defaults;
648 u32 misc_mode;
649 enum {
650 AUTO_32KHZ,
651 USE_32KHZ,
652 DONT_USE_32KHZ,
653 } enable_32kHz_clock;
654
655 /* Private to hardware code */
656 struct ath_hw_private_ops private_ops;
657 /* Accessed by the lower level driver */
658 struct ath_hw_ops ops;
659
660 /* Used to program the radio on non single-chip devices */
661 u32 *analogBank0Data;
662 u32 *analogBank1Data;
663 u32 *analogBank2Data;
664 u32 *analogBank3Data;
665 u32 *analogBank6Data;
666 u32 *analogBank6TPCData;
667 u32 *analogBank7Data;
668 u32 *addac5416_21;
669 u32 *bank6Temp;
670
671 int16_t txpower_indexoffset;
672 int coverage_class;
673 u32 beacon_interval;
674 u32 slottime;
675 u32 globaltxtimeout;
676
677 /* ANI */
678 u32 proc_phyerr;
679 u32 aniperiod;
680 struct ar5416AniState *curani;
681 struct ar5416AniState ani[255];
682 int totalSizeDesired[5];
683 int coarse_high[5];
684 int coarse_low[5];
685 int firpwr[5];
686 enum ath9k_ani_cmd ani_function;
687
688 /* Bluetooth coexistance */
689 struct ath_btcoex_hw btcoex_hw;
690
691 u32 intr_txqs;
692 u8 txchainmask;
693 u8 rxchainmask;
694
695 u32 originalGain[22];
696 int initPDADC;
697 int PDADCdelta;
698 u8 led_pin;
699
700 struct ar5416IniArray iniModes;
701 struct ar5416IniArray iniCommon;
702 struct ar5416IniArray iniBank0;
703 struct ar5416IniArray iniBB_RfGain;
704 struct ar5416IniArray iniBank1;
705 struct ar5416IniArray iniBank2;
706 struct ar5416IniArray iniBank3;
707 struct ar5416IniArray iniBank6;
708 struct ar5416IniArray iniBank6TPC;
709 struct ar5416IniArray iniBank7;
710 struct ar5416IniArray iniAddac;
711 struct ar5416IniArray iniPcieSerdes;
712 struct ar5416IniArray iniPcieSerdesLowPower;
713 struct ar5416IniArray iniModesAdditional;
714 struct ar5416IniArray iniModesRxGain;
715 struct ar5416IniArray iniModesTxGain;
716 struct ar5416IniArray iniModes_9271_1_0_only;
717 struct ar5416IniArray iniCckfirNormal;
718 struct ar5416IniArray iniCckfirJapan2484;
719 struct ar5416IniArray iniCommon_normal_cck_fir_coeff_9271;
720 struct ar5416IniArray iniCommon_japan_2484_cck_fir_coeff_9271;
721 struct ar5416IniArray iniModes_9271_ANI_reg;
722 struct ar5416IniArray iniModes_high_power_tx_gain_9271;
723 struct ar5416IniArray iniModes_normal_power_tx_gain_9271;
724
725 struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT];
726 struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT];
727 struct ar5416IniArray iniRadio[ATH_INI_NUM_SPLIT];
728 struct ar5416IniArray iniSOC[ATH_INI_NUM_SPLIT];
729
730 u32 intr_gen_timer_trigger;
731 u32 intr_gen_timer_thresh;
732 struct ath_gen_timer_table hw_gen_timers;
733 };
734
735 static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
736 {
737 return &ah->common;
738 }
739
740 static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah)
741 {
742 return &(ath9k_hw_common(ah)->regulatory);
743 }
744
745 static inline struct ath_hw_private_ops *ath9k_hw_private_ops(struct ath_hw *ah)
746 {
747 return &ah->private_ops;
748 }
749
750 static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah)
751 {
752 return &ah->ops;
753 }
754
755 /* Initialization, Detach, Reset */
756 const char *ath9k_hw_probe(u16 vendorid, u16 devid);
757 void ath9k_hw_deinit(struct ath_hw *ah);
758 int ath9k_hw_init(struct ath_hw *ah);
759 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
760 bool bChannelChange);
761 int ath9k_hw_fill_cap_info(struct ath_hw *ah);
762 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
763 u32 capability, u32 *result);
764 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
765 u32 capability, u32 setting, int *status);
766 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan);
767
768 /* Key Cache Management */
769 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry);
770 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac);
771 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
772 const struct ath9k_keyval *k,
773 const u8 *mac);
774 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry);
775
776 /* GPIO / RFKILL / Antennae */
777 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio);
778 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio);
779 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
780 u32 ah_signal_type);
781 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val);
782 u32 ath9k_hw_getdefantenna(struct ath_hw *ah);
783 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna);
784
785 /* General Operation */
786 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout);
787 u32 ath9k_hw_reverse_bits(u32 val, u32 n);
788 bool ath9k_get_channel_edges(struct ath_hw *ah, u16 flags, u16 *low, u16 *high);
789 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
790 u8 phy, int kbps,
791 u32 frameLen, u16 rateix, bool shortPreamble);
792 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
793 struct ath9k_channel *chan,
794 struct chan_centers *centers);
795 u32 ath9k_hw_getrxfilter(struct ath_hw *ah);
796 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits);
797 bool ath9k_hw_phy_disable(struct ath_hw *ah);
798 bool ath9k_hw_disable(struct ath_hw *ah);
799 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit);
800 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac);
801 void ath9k_hw_setopmode(struct ath_hw *ah);
802 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1);
803 void ath9k_hw_setbssidmask(struct ath_hw *ah);
804 void ath9k_hw_write_associd(struct ath_hw *ah);
805 u64 ath9k_hw_gettsf64(struct ath_hw *ah);
806 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64);
807 void ath9k_hw_reset_tsf(struct ath_hw *ah);
808 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting);
809 u64 ath9k_hw_extend_tsf(struct ath_hw *ah, u32 rstamp);
810 void ath9k_hw_init_global_settings(struct ath_hw *ah);
811 void ath9k_hw_set11nmac2040(struct ath_hw *ah);
812 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period);
813 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
814 const struct ath9k_beacon_state *bs);
815
816 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode);
817
818 /* Generic hw timer primitives */
819 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
820 void (*trigger)(void *),
821 void (*overflow)(void *),
822 void *arg,
823 u8 timer_index);
824 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
825 struct ath_gen_timer *timer,
826 u32 timer_next,
827 u32 timer_period);
828 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer);
829
830 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer);
831 void ath_gen_timer_isr(struct ath_hw *hw);
832 u32 ath9k_hw_gettsf32(struct ath_hw *ah);
833
834 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len);
835
836 /* HTC */
837 void ath9k_hw_htc_resetinit(struct ath_hw *ah);
838
839 /* PHY */
840 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
841 u32 *coef_mantissa, u32 *coef_exponent);
842
843 void ar9002_hw_cck_chan14_spread(struct ath_hw *ah);
844
845 /*
846 * Code specifric to AR9003, we stuff these here to avoid callbacks
847 * for older families
848 */
849 void ar9003_hw_set_nf_limits(struct ath_hw *ah);
850
851 /* Hardware family op attach helpers */
852 void ar5008_hw_attach_phy_ops(struct ath_hw *ah);
853 void ar9002_hw_attach_phy_ops(struct ath_hw *ah);
854 void ar9003_hw_attach_phy_ops(struct ath_hw *ah);
855
856 void ar9002_hw_attach_calib_ops(struct ath_hw *ah);
857 void ar9003_hw_attach_calib_ops(struct ath_hw *ah);
858
859 void ar9002_hw_attach_ops(struct ath_hw *ah);
860 void ar9003_hw_attach_ops(struct ath_hw *ah);
861
862 #define ATH_PCIE_CAP_LINK_CTRL 0x70
863 #define ATH_PCIE_CAP_LINK_L0S 1
864 #define ATH_PCIE_CAP_LINK_L1 2
865
866 #endif
Linux kernel - Deliverables
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