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ath9k: Add support for AR9565 v1.0.1 LNA diversity
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / hw.h
1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #ifndef HW_H
18 #define HW_H
19
20 #include <linux/if_ether.h>
21 #include <linux/delay.h>
22 #include <linux/io.h>
23 #include <linux/firmware.h>
24
25 #include "mac.h"
26 #include "ani.h"
27 #include "eeprom.h"
28 #include "calib.h"
29 #include "reg.h"
30 #include "phy.h"
31 #include "btcoex.h"
32
33 #include "../regd.h"
34
35 #define ATHEROS_VENDOR_ID 0x168c
36
37 #define AR5416_DEVID_PCI 0x0023
38 #define AR5416_DEVID_PCIE 0x0024
39 #define AR9160_DEVID_PCI 0x0027
40 #define AR9280_DEVID_PCI 0x0029
41 #define AR9280_DEVID_PCIE 0x002a
42 #define AR9285_DEVID_PCIE 0x002b
43 #define AR2427_DEVID_PCIE 0x002c
44 #define AR9287_DEVID_PCI 0x002d
45 #define AR9287_DEVID_PCIE 0x002e
46 #define AR9300_DEVID_PCIE 0x0030
47 #define AR9300_DEVID_AR9340 0x0031
48 #define AR9300_DEVID_AR9485_PCIE 0x0032
49 #define AR9300_DEVID_AR9580 0x0033
50 #define AR9300_DEVID_AR9462 0x0034
51 #define AR9300_DEVID_AR9330 0x0035
52 #define AR9300_DEVID_QCA955X 0x0038
53 #define AR9485_DEVID_AR1111 0x0037
54 #define AR9300_DEVID_AR9565 0x0036
55
56 #define AR5416_AR9100_DEVID 0x000b
57
58 #define AR_SUBVENDOR_ID_NOG 0x0e11
59 #define AR_SUBVENDOR_ID_NEW_A 0x7065
60 #define AR5416_MAGIC 0x19641014
61
62 #define AR9280_COEX2WIRE_SUBSYSID 0x309b
63 #define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa
64 #define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab
65
66 #define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1)
67
68 #define ATH_DEFAULT_NOISE_FLOOR -95
69
70 #define ATH9K_RSSI_BAD -128
71
72 #define ATH9K_NUM_CHANNELS 38
73
74 /* Register read/write primitives */
75 #define REG_WRITE(_ah, _reg, _val) \
76 (_ah)->reg_ops.write((_ah), (_val), (_reg))
77
78 #define REG_READ(_ah, _reg) \
79 (_ah)->reg_ops.read((_ah), (_reg))
80
81 #define REG_READ_MULTI(_ah, _addr, _val, _cnt) \
82 (_ah)->reg_ops.multi_read((_ah), (_addr), (_val), (_cnt))
83
84 #define REG_RMW(_ah, _reg, _set, _clr) \
85 (_ah)->reg_ops.rmw((_ah), (_reg), (_set), (_clr))
86
87 #define ENABLE_REGWRITE_BUFFER(_ah) \
88 do { \
89 if ((_ah)->reg_ops.enable_write_buffer) \
90 (_ah)->reg_ops.enable_write_buffer((_ah)); \
91 } while (0)
92
93 #define REGWRITE_BUFFER_FLUSH(_ah) \
94 do { \
95 if ((_ah)->reg_ops.write_flush) \
96 (_ah)->reg_ops.write_flush((_ah)); \
97 } while (0)
98
99 #define PR_EEP(_s, _val) \
100 do { \
101 len += snprintf(buf + len, size - len, "%20s : %10d\n", \
102 _s, (_val)); \
103 } while (0)
104
105 #define SM(_v, _f) (((_v) << _f##_S) & _f)
106 #define MS(_v, _f) (((_v) & _f) >> _f##_S)
107 #define REG_RMW_FIELD(_a, _r, _f, _v) \
108 REG_RMW(_a, _r, (((_v) << _f##_S) & _f), (_f))
109 #define REG_READ_FIELD(_a, _r, _f) \
110 (((REG_READ(_a, _r) & _f) >> _f##_S))
111 #define REG_SET_BIT(_a, _r, _f) \
112 REG_RMW(_a, _r, (_f), 0)
113 #define REG_CLR_BIT(_a, _r, _f) \
114 REG_RMW(_a, _r, 0, (_f))
115
116 #define DO_DELAY(x) do { \
117 if (((++(x) % 64) == 0) && \
118 (ath9k_hw_common(ah)->bus_ops->ath_bus_type \
119 != ATH_USB)) \
120 udelay(1); \
121 } while (0)
122
123 #define REG_WRITE_ARRAY(iniarray, column, regWr) \
124 ath9k_hw_write_array(ah, iniarray, column, &(regWr))
125
126 #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
127 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
128 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
129 #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3
130 #define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4
131 #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
132 #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
133 #define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_DATA 0x16
134 #define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_CLK 0x17
135 #define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA 0x18
136 #define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK 0x19
137 #define AR_GPIO_OUTPUT_MUX_AS_WL_IN_TX 0x14
138 #define AR_GPIO_OUTPUT_MUX_AS_WL_IN_RX 0x13
139 #define AR_GPIO_OUTPUT_MUX_AS_BT_IN_TX 9
140 #define AR_GPIO_OUTPUT_MUX_AS_BT_IN_RX 8
141 #define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_STROBE 0x1d
142 #define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_DATA 0x1e
143
144 #define AR_GPIOD_MASK 0x00001FFF
145 #define AR_GPIO_BIT(_gpio) (1 << (_gpio))
146
147 #define BASE_ACTIVATE_DELAY 100
148 #define RTC_PLL_SETTLE_DELAY (AR_SREV_9340(ah) ? 1000 : 100)
149 #define COEF_SCALE_S 24
150 #define HT40_CHANNEL_CENTER_SHIFT 10
151
152 #define ATH9K_ANTENNA0_CHAINMASK 0x1
153 #define ATH9K_ANTENNA1_CHAINMASK 0x2
154
155 #define ATH9K_NUM_DMA_DEBUG_REGS 8
156 #define ATH9K_NUM_QUEUES 10
157
158 #define MAX_RATE_POWER 63
159 #define AH_WAIT_TIMEOUT 100000 /* (us) */
160 #define AH_TSF_WRITE_TIMEOUT 100 /* (us) */
161 #define AH_TIME_QUANTUM 10
162 #define AR_KEYTABLE_SIZE 128
163 #define POWER_UP_TIME 10000
164 #define SPUR_RSSI_THRESH 40
165 #define UPPER_5G_SUB_BAND_START 5700
166 #define MID_5G_SUB_BAND_START 5400
167
168 #define CAB_TIMEOUT_VAL 10
169 #define BEACON_TIMEOUT_VAL 10
170 #define MIN_BEACON_TIMEOUT_VAL 1
171 #define SLEEP_SLOP 3
172
173 #define INIT_CONFIG_STATUS 0x00000000
174 #define INIT_RSSI_THR 0x00000700
175 #define INIT_BCON_CNTRL_REG 0x00000000
176
177 #define TU_TO_USEC(_tu) ((_tu) << 10)
178
179 #define ATH9K_HW_RX_HP_QDEPTH 16
180 #define ATH9K_HW_RX_LP_QDEPTH 128
181
182 #define PAPRD_GAIN_TABLE_ENTRIES 32
183 #define PAPRD_TABLE_SZ 24
184 #define PAPRD_IDEAL_AGC2_PWR_RANGE 0xe0
185
186 /*
187 * Wake on Wireless
188 */
189
190 /* Keep Alive Frame */
191 #define KAL_FRAME_LEN 28
192 #define KAL_FRAME_TYPE 0x2 /* data frame */
193 #define KAL_FRAME_SUB_TYPE 0x4 /* null data frame */
194 #define KAL_DURATION_ID 0x3d
195 #define KAL_NUM_DATA_WORDS 6
196 #define KAL_NUM_DESC_WORDS 12
197 #define KAL_ANTENNA_MODE 1
198 #define KAL_TO_DS 1
199 #define KAL_DELAY 4 /*delay of 4ms between 2 KAL frames */
200 #define KAL_TIMEOUT 900
201
202 #define MAX_PATTERN_SIZE 256
203 #define MAX_PATTERN_MASK_SIZE 32
204 #define MAX_NUM_PATTERN 8
205 #define MAX_NUM_USER_PATTERN 6 /* deducting the disassociate and
206 deauthenticate packets */
207
208 /*
209 * WoW trigger mapping to hardware code
210 */
211
212 #define AH_WOW_USER_PATTERN_EN BIT(0)
213 #define AH_WOW_MAGIC_PATTERN_EN BIT(1)
214 #define AH_WOW_LINK_CHANGE BIT(2)
215 #define AH_WOW_BEACON_MISS BIT(3)
216
217 enum ath_hw_txq_subtype {
218 ATH_TXQ_AC_BE = 0,
219 ATH_TXQ_AC_BK = 1,
220 ATH_TXQ_AC_VI = 2,
221 ATH_TXQ_AC_VO = 3,
222 };
223
224 enum ath_ini_subsys {
225 ATH_INI_PRE = 0,
226 ATH_INI_CORE,
227 ATH_INI_POST,
228 ATH_INI_NUM_SPLIT,
229 };
230
231 enum ath9k_hw_caps {
232 ATH9K_HW_CAP_HT = BIT(0),
233 ATH9K_HW_CAP_RFSILENT = BIT(1),
234 ATH9K_HW_CAP_AUTOSLEEP = BIT(2),
235 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(3),
236 ATH9K_HW_CAP_EDMA = BIT(4),
237 ATH9K_HW_CAP_RAC_SUPPORTED = BIT(5),
238 ATH9K_HW_CAP_LDPC = BIT(6),
239 ATH9K_HW_CAP_FASTCLOCK = BIT(7),
240 ATH9K_HW_CAP_SGI_20 = BIT(8),
241 ATH9K_HW_CAP_ANT_DIV_COMB = BIT(10),
242 ATH9K_HW_CAP_2GHZ = BIT(11),
243 ATH9K_HW_CAP_5GHZ = BIT(12),
244 ATH9K_HW_CAP_APM = BIT(13),
245 ATH9K_HW_CAP_RTT = BIT(14),
246 ATH9K_HW_CAP_MCI = BIT(15),
247 ATH9K_HW_CAP_DFS = BIT(16),
248 ATH9K_HW_WOW_DEVICE_CAPABLE = BIT(17),
249 ATH9K_HW_CAP_PAPRD = BIT(18),
250 ATH9K_HW_CAP_FCC_BAND_SWITCH = BIT(19),
251 ATH9K_HW_CAP_BT_ANT_DIV = BIT(20),
252 };
253
254 /*
255 * WoW device capabilities
256 * @ATH9K_HW_WOW_DEVICE_CAPABLE: device revision is capable of WoW.
257 * @ATH9K_HW_WOW_PATTERN_MATCH_EXACT: device is capable of matching
258 * an exact user defined pattern or de-authentication/disassoc pattern.
259 * @ATH9K_HW_WOW_PATTERN_MATCH_DWORD: device requires the first four
260 * bytes of the pattern for user defined pattern, de-authentication and
261 * disassociation patterns for all types of possible frames recieved
262 * of those types.
263 */
264
265 struct ath9k_hw_capabilities {
266 u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
267 u16 rts_aggr_limit;
268 u8 tx_chainmask;
269 u8 rx_chainmask;
270 u8 max_txchains;
271 u8 max_rxchains;
272 u8 num_gpio_pins;
273 u8 rx_hp_qdepth;
274 u8 rx_lp_qdepth;
275 u8 rx_status_len;
276 u8 tx_desc_len;
277 u8 txs_len;
278 };
279
280 struct ath9k_ops_config {
281 int dma_beacon_response_time;
282 int sw_beacon_response_time;
283 int additional_swba_backoff;
284 int ack_6mb;
285 u32 cwm_ignore_extcca;
286 bool pcieSerDesWrite;
287 u8 pcie_clock_req;
288 u32 pcie_waen;
289 u8 analog_shiftreg;
290 u32 ofdm_trig_low;
291 u32 ofdm_trig_high;
292 u32 cck_trig_high;
293 u32 cck_trig_low;
294 u32 enable_paprd;
295 int serialize_regmode;
296 bool rx_intr_mitigation;
297 bool tx_intr_mitigation;
298 #define SPUR_DISABLE 0
299 #define SPUR_ENABLE_IOCTL 1
300 #define SPUR_ENABLE_EEPROM 2
301 #define AR_SPUR_5413_1 1640
302 #define AR_SPUR_5413_2 1200
303 #define AR_NO_SPUR 0x8000
304 #define AR_BASE_FREQ_2GHZ 2300
305 #define AR_BASE_FREQ_5GHZ 4900
306 #define AR_SPUR_FEEQ_BOUND_HT40 19
307 #define AR_SPUR_FEEQ_BOUND_HT20 10
308 int spurmode;
309 u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
310 u8 max_txtrig_level;
311 u16 ani_poll_interval; /* ANI poll interval in ms */
312
313 /* Platform specific config */
314 u32 aspm_l1_fix;
315 u32 xlna_gpio;
316 u32 ant_ctrl_comm2g_switch_enable;
317 bool xatten_margin_cfg;
318 bool alt_mingainidx;
319 };
320
321 enum ath9k_int {
322 ATH9K_INT_RX = 0x00000001,
323 ATH9K_INT_RXDESC = 0x00000002,
324 ATH9K_INT_RXHP = 0x00000001,
325 ATH9K_INT_RXLP = 0x00000002,
326 ATH9K_INT_RXNOFRM = 0x00000008,
327 ATH9K_INT_RXEOL = 0x00000010,
328 ATH9K_INT_RXORN = 0x00000020,
329 ATH9K_INT_TX = 0x00000040,
330 ATH9K_INT_TXDESC = 0x00000080,
331 ATH9K_INT_TIM_TIMER = 0x00000100,
332 ATH9K_INT_MCI = 0x00000200,
333 ATH9K_INT_BB_WATCHDOG = 0x00000400,
334 ATH9K_INT_TXURN = 0x00000800,
335 ATH9K_INT_MIB = 0x00001000,
336 ATH9K_INT_RXPHY = 0x00004000,
337 ATH9K_INT_RXKCM = 0x00008000,
338 ATH9K_INT_SWBA = 0x00010000,
339 ATH9K_INT_BMISS = 0x00040000,
340 ATH9K_INT_BNR = 0x00100000,
341 ATH9K_INT_TIM = 0x00200000,
342 ATH9K_INT_DTIM = 0x00400000,
343 ATH9K_INT_DTIMSYNC = 0x00800000,
344 ATH9K_INT_GPIO = 0x01000000,
345 ATH9K_INT_CABEND = 0x02000000,
346 ATH9K_INT_TSFOOR = 0x04000000,
347 ATH9K_INT_GENTIMER = 0x08000000,
348 ATH9K_INT_CST = 0x10000000,
349 ATH9K_INT_GTT = 0x20000000,
350 ATH9K_INT_FATAL = 0x40000000,
351 ATH9K_INT_GLOBAL = 0x80000000,
352 ATH9K_INT_BMISC = ATH9K_INT_TIM |
353 ATH9K_INT_DTIM |
354 ATH9K_INT_DTIMSYNC |
355 ATH9K_INT_TSFOOR |
356 ATH9K_INT_CABEND,
357 ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
358 ATH9K_INT_RXDESC |
359 ATH9K_INT_RXEOL |
360 ATH9K_INT_RXORN |
361 ATH9K_INT_TXURN |
362 ATH9K_INT_TXDESC |
363 ATH9K_INT_MIB |
364 ATH9K_INT_RXPHY |
365 ATH9K_INT_RXKCM |
366 ATH9K_INT_SWBA |
367 ATH9K_INT_BMISS |
368 ATH9K_INT_GPIO,
369 ATH9K_INT_NOCARD = 0xffffffff
370 };
371
372 #define CHANNEL_CCK 0x00020
373 #define CHANNEL_OFDM 0x00040
374 #define CHANNEL_2GHZ 0x00080
375 #define CHANNEL_5GHZ 0x00100
376 #define CHANNEL_PASSIVE 0x00200
377 #define CHANNEL_DYN 0x00400
378 #define CHANNEL_HALF 0x04000
379 #define CHANNEL_QUARTER 0x08000
380 #define CHANNEL_HT20 0x10000
381 #define CHANNEL_HT40PLUS 0x20000
382 #define CHANNEL_HT40MINUS 0x40000
383
384 #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
385 #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
386 #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
387 #define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20)
388 #define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20)
389 #define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
390 #define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
391 #define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
392 #define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
393 #define CHANNEL_ALL \
394 (CHANNEL_OFDM| \
395 CHANNEL_CCK| \
396 CHANNEL_2GHZ | \
397 CHANNEL_5GHZ | \
398 CHANNEL_HT20 | \
399 CHANNEL_HT40PLUS | \
400 CHANNEL_HT40MINUS)
401
402 #define MAX_RTT_TABLE_ENTRY 6
403 #define MAX_IQCAL_MEASUREMENT 8
404 #define MAX_CL_TAB_ENTRY 16
405 #define CL_TAB_ENTRY(reg_base) (reg_base + (4 * j))
406
407 struct ath9k_hw_cal_data {
408 u16 channel;
409 u32 channelFlags;
410 u32 chanmode;
411 int32_t CalValid;
412 int8_t iCoff;
413 int8_t qCoff;
414 bool rtt_done;
415 bool paprd_packet_sent;
416 bool paprd_done;
417 bool nfcal_pending;
418 bool nfcal_interference;
419 bool done_txiqcal_once;
420 bool done_txclcal_once;
421 u16 small_signal_gain[AR9300_MAX_CHAINS];
422 u32 pa_table[AR9300_MAX_CHAINS][PAPRD_TABLE_SZ];
423 u32 num_measures[AR9300_MAX_CHAINS];
424 int tx_corr_coeff[MAX_IQCAL_MEASUREMENT][AR9300_MAX_CHAINS];
425 u32 tx_clcal[AR9300_MAX_CHAINS][MAX_CL_TAB_ENTRY];
426 u32 rtt_table[AR9300_MAX_CHAINS][MAX_RTT_TABLE_ENTRY];
427 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
428 };
429
430 struct ath9k_channel {
431 struct ieee80211_channel *chan;
432 u16 channel;
433 u32 channelFlags;
434 u32 chanmode;
435 s16 noisefloor;
436 };
437
438 #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
439 (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
440 (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
441 (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
442 #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
443 #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
444 #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
445 #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
446 #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
447 #define IS_CHAN_A_FAST_CLOCK(_ah, _c) \
448 ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \
449 ((_ah)->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK))
450
451 /* These macros check chanmode and not channelFlags */
452 #define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B)
453 #define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \
454 ((_c)->chanmode == CHANNEL_G_HT20))
455 #define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \
456 ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \
457 ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \
458 ((_c)->chanmode == CHANNEL_G_HT40MINUS))
459 #define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
460
461 enum ath9k_power_mode {
462 ATH9K_PM_AWAKE = 0,
463 ATH9K_PM_FULL_SLEEP,
464 ATH9K_PM_NETWORK_SLEEP,
465 ATH9K_PM_UNDEFINED
466 };
467
468 enum ser_reg_mode {
469 SER_REG_MODE_OFF = 0,
470 SER_REG_MODE_ON = 1,
471 SER_REG_MODE_AUTO = 2,
472 };
473
474 enum ath9k_rx_qtype {
475 ATH9K_RX_QUEUE_HP,
476 ATH9K_RX_QUEUE_LP,
477 ATH9K_RX_QUEUE_MAX,
478 };
479
480 struct ath9k_beacon_state {
481 u32 bs_nexttbtt;
482 u32 bs_nextdtim;
483 u32 bs_intval;
484 #define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */
485 u32 bs_dtimperiod;
486 u16 bs_cfpperiod;
487 u16 bs_cfpmaxduration;
488 u32 bs_cfpnext;
489 u16 bs_timoffset;
490 u16 bs_bmissthreshold;
491 u32 bs_sleepduration;
492 u32 bs_tsfoor_threshold;
493 };
494
495 struct chan_centers {
496 u16 synth_center;
497 u16 ctl_center;
498 u16 ext_center;
499 };
500
501 enum {
502 ATH9K_RESET_POWER_ON,
503 ATH9K_RESET_WARM,
504 ATH9K_RESET_COLD,
505 };
506
507 struct ath9k_hw_version {
508 u32 magic;
509 u16 devid;
510 u16 subvendorid;
511 u32 macVersion;
512 u16 macRev;
513 u16 phyRev;
514 u16 analog5GhzRev;
515 u16 analog2GhzRev;
516 enum ath_usb_dev usbdev;
517 };
518
519 /* Generic TSF timer definitions */
520
521 #define ATH_MAX_GEN_TIMER 16
522
523 #define AR_GENTMR_BIT(_index) (1 << (_index))
524
525 /*
526 * Using de Bruijin sequence to look up 1's index in a 32 bit number
527 * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001
528 */
529 #define debruijn32 0x077CB531U
530
531 struct ath_gen_timer_configuration {
532 u32 next_addr;
533 u32 period_addr;
534 u32 mode_addr;
535 u32 mode_mask;
536 };
537
538 struct ath_gen_timer {
539 void (*trigger)(void *arg);
540 void (*overflow)(void *arg);
541 void *arg;
542 u8 index;
543 };
544
545 struct ath_gen_timer_table {
546 u32 gen_timer_index[32];
547 struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER];
548 union {
549 unsigned long timer_bits;
550 u16 val;
551 } timer_mask;
552 };
553
554 struct ath_hw_antcomb_conf {
555 u8 main_lna_conf;
556 u8 alt_lna_conf;
557 u8 fast_div_bias;
558 u8 main_gaintb;
559 u8 alt_gaintb;
560 int lna1_lna2_delta;
561 int lna1_lna2_switch_delta;
562 u8 div_group;
563 };
564
565 /**
566 * struct ath_hw_radar_conf - radar detection initialization parameters
567 *
568 * @pulse_inband: threshold for checking the ratio of in-band power
569 * to total power for short radar pulses (half dB steps)
570 * @pulse_inband_step: threshold for checking an in-band power to total
571 * power ratio increase for short radar pulses (half dB steps)
572 * @pulse_height: threshold for detecting the beginning of a short
573 * radar pulse (dB step)
574 * @pulse_rssi: threshold for detecting if a short radar pulse is
575 * gone (dB step)
576 * @pulse_maxlen: maximum pulse length (0.8 us steps)
577 *
578 * @radar_rssi: RSSI threshold for starting long radar detection (dB steps)
579 * @radar_inband: threshold for checking the ratio of in-band power
580 * to total power for long radar pulses (half dB steps)
581 * @fir_power: threshold for detecting the end of a long radar pulse (dB)
582 *
583 * @ext_channel: enable extension channel radar detection
584 */
585 struct ath_hw_radar_conf {
586 unsigned int pulse_inband;
587 unsigned int pulse_inband_step;
588 unsigned int pulse_height;
589 unsigned int pulse_rssi;
590 unsigned int pulse_maxlen;
591
592 unsigned int radar_rssi;
593 unsigned int radar_inband;
594 int fir_power;
595
596 bool ext_channel;
597 };
598
599 /**
600 * struct ath_hw_private_ops - callbacks used internally by hardware code
601 *
602 * This structure contains private callbacks designed to only be used internally
603 * by the hardware core.
604 *
605 * @init_cal_settings: setup types of calibrations supported
606 * @init_cal: starts actual calibration
607 *
608 * @init_mode_gain_regs: Initialize TX/RX gain registers
609 *
610 * @rf_set_freq: change frequency
611 * @spur_mitigate_freq: spur mitigation
612 * @set_rf_regs:
613 * @compute_pll_control: compute the PLL control value to use for
614 * AR_RTC_PLL_CONTROL for a given channel
615 * @setup_calibration: set up calibration
616 * @iscal_supported: used to query if a type of calibration is supported
617 *
618 * @ani_cache_ini_regs: cache the values for ANI from the initial
619 * register settings through the register initialization.
620 */
621 struct ath_hw_private_ops {
622 /* Calibration ops */
623 void (*init_cal_settings)(struct ath_hw *ah);
624 bool (*init_cal)(struct ath_hw *ah, struct ath9k_channel *chan);
625
626 void (*init_mode_gain_regs)(struct ath_hw *ah);
627 void (*setup_calibration)(struct ath_hw *ah,
628 struct ath9k_cal_list *currCal);
629
630 /* PHY ops */
631 int (*rf_set_freq)(struct ath_hw *ah,
632 struct ath9k_channel *chan);
633 void (*spur_mitigate_freq)(struct ath_hw *ah,
634 struct ath9k_channel *chan);
635 bool (*set_rf_regs)(struct ath_hw *ah,
636 struct ath9k_channel *chan,
637 u16 modesIndex);
638 void (*set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan);
639 void (*init_bb)(struct ath_hw *ah,
640 struct ath9k_channel *chan);
641 int (*process_ini)(struct ath_hw *ah, struct ath9k_channel *chan);
642 void (*olc_init)(struct ath_hw *ah);
643 void (*set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan);
644 void (*mark_phy_inactive)(struct ath_hw *ah);
645 void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan);
646 bool (*rfbus_req)(struct ath_hw *ah);
647 void (*rfbus_done)(struct ath_hw *ah);
648 void (*restore_chainmask)(struct ath_hw *ah);
649 u32 (*compute_pll_control)(struct ath_hw *ah,
650 struct ath9k_channel *chan);
651 bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd,
652 int param);
653 void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]);
654 void (*set_radar_params)(struct ath_hw *ah,
655 struct ath_hw_radar_conf *conf);
656 int (*fast_chan_change)(struct ath_hw *ah, struct ath9k_channel *chan,
657 u8 *ini_reloaded);
658
659 /* ANI */
660 void (*ani_cache_ini_regs)(struct ath_hw *ah);
661 };
662
663 /**
664 * struct ath_spec_scan - parameters for Atheros spectral scan
665 *
666 * @enabled: enable/disable spectral scan
667 * @short_repeat: controls whether the chip is in spectral scan mode
668 * for 4 usec (enabled) or 204 usec (disabled)
669 * @count: number of scan results requested. There are special meanings
670 * in some chip revisions:
671 * AR92xx: highest bit set (>=128) for endless mode
672 * (spectral scan won't stopped until explicitly disabled)
673 * AR9300 and newer: 0 for endless mode
674 * @endless: true if endless mode is intended. Otherwise, count value is
675 * corrected to the next possible value.
676 * @period: time duration between successive spectral scan entry points
677 * (period*256*Tclk). Tclk = ath_common->clockrate
678 * @fft_period: PHY passes FFT frames to MAC every (fft_period+1)*4uS
679 *
680 * Note: Tclk = 40MHz or 44MHz depending upon operating mode.
681 * Typically it's 44MHz in 2/5GHz on later chips, but there's
682 * a "fast clock" check for this in 5GHz.
683 *
684 */
685 struct ath_spec_scan {
686 bool enabled;
687 bool short_repeat;
688 bool endless;
689 u8 count;
690 u8 period;
691 u8 fft_period;
692 };
693
694 /**
695 * struct ath_hw_ops - callbacks used by hardware code and driver code
696 *
697 * This structure contains callbacks designed to to be used internally by
698 * hardware code and also by the lower level driver.
699 *
700 * @config_pci_powersave:
701 * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC
702 *
703 * @spectral_scan_config: set parameters for spectral scan and enable/disable it
704 * @spectral_scan_trigger: trigger a spectral scan run
705 * @spectral_scan_wait: wait for a spectral scan run to finish
706 */
707 struct ath_hw_ops {
708 void (*config_pci_powersave)(struct ath_hw *ah,
709 bool power_off);
710 void (*rx_enable)(struct ath_hw *ah);
711 void (*set_desc_link)(void *ds, u32 link);
712 bool (*calibrate)(struct ath_hw *ah,
713 struct ath9k_channel *chan,
714 u8 rxchainmask,
715 bool longcal);
716 bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked);
717 void (*set_txdesc)(struct ath_hw *ah, void *ds,
718 struct ath_tx_info *i);
719 int (*proc_txdesc)(struct ath_hw *ah, void *ds,
720 struct ath_tx_status *ts);
721 void (*antdiv_comb_conf_get)(struct ath_hw *ah,
722 struct ath_hw_antcomb_conf *antconf);
723 void (*antdiv_comb_conf_set)(struct ath_hw *ah,
724 struct ath_hw_antcomb_conf *antconf);
725 void (*spectral_scan_config)(struct ath_hw *ah,
726 struct ath_spec_scan *param);
727 void (*spectral_scan_trigger)(struct ath_hw *ah);
728 void (*spectral_scan_wait)(struct ath_hw *ah);
729
730 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
731 void (*set_bt_ant_diversity)(struct ath_hw *hw, bool enable);
732 #endif
733 };
734
735 struct ath_nf_limits {
736 s16 max;
737 s16 min;
738 s16 nominal;
739 };
740
741 enum ath_cal_list {
742 TX_IQ_CAL = BIT(0),
743 TX_IQ_ON_AGC_CAL = BIT(1),
744 TX_CL_CAL = BIT(2),
745 };
746
747 /* ah_flags */
748 #define AH_USE_EEPROM 0x1
749 #define AH_UNPLUGGED 0x2 /* The card has been physically removed. */
750 #define AH_FASTCC 0x4
751
752 struct ath_hw {
753 struct ath_ops reg_ops;
754
755 struct device *dev;
756 struct ieee80211_hw *hw;
757 struct ath_common common;
758 struct ath9k_hw_version hw_version;
759 struct ath9k_ops_config config;
760 struct ath9k_hw_capabilities caps;
761 struct ath9k_channel channels[ATH9K_NUM_CHANNELS];
762 struct ath9k_channel *curchan;
763
764 union {
765 struct ar5416_eeprom_def def;
766 struct ar5416_eeprom_4k map4k;
767 struct ar9287_eeprom map9287;
768 struct ar9300_eeprom ar9300_eep;
769 } eeprom;
770 const struct eeprom_ops *eep_ops;
771
772 bool sw_mgmt_crypto;
773 bool is_pciexpress;
774 bool aspm_enabled;
775 bool is_monitoring;
776 bool need_an_top2_fixup;
777 u16 tx_trig_level;
778
779 u32 nf_regs[6];
780 struct ath_nf_limits nf_2g;
781 struct ath_nf_limits nf_5g;
782 u16 rfsilent;
783 u32 rfkill_gpio;
784 u32 rfkill_polarity;
785 u32 ah_flags;
786
787 bool reset_power_on;
788 bool htc_reset_init;
789
790 enum nl80211_iftype opmode;
791 enum ath9k_power_mode power_mode;
792
793 s8 noise;
794 struct ath9k_hw_cal_data *caldata;
795 struct ath9k_pacal_info pacal_info;
796 struct ar5416Stats stats;
797 struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES];
798
799 enum ath9k_int imask;
800 u32 imrs2_reg;
801 u32 txok_interrupt_mask;
802 u32 txerr_interrupt_mask;
803 u32 txdesc_interrupt_mask;
804 u32 txeol_interrupt_mask;
805 u32 txurn_interrupt_mask;
806 atomic_t intr_ref_cnt;
807 bool chip_fullsleep;
808 u32 atim_window;
809 u32 modes_index;
810
811 /* Calibration */
812 u32 supp_cals;
813 struct ath9k_cal_list iq_caldata;
814 struct ath9k_cal_list adcgain_caldata;
815 struct ath9k_cal_list adcdc_caldata;
816 struct ath9k_cal_list *cal_list;
817 struct ath9k_cal_list *cal_list_last;
818 struct ath9k_cal_list *cal_list_curr;
819 #define totalPowerMeasI meas0.unsign
820 #define totalPowerMeasQ meas1.unsign
821 #define totalIqCorrMeas meas2.sign
822 #define totalAdcIOddPhase meas0.unsign
823 #define totalAdcIEvenPhase meas1.unsign
824 #define totalAdcQOddPhase meas2.unsign
825 #define totalAdcQEvenPhase meas3.unsign
826 #define totalAdcDcOffsetIOddPhase meas0.sign
827 #define totalAdcDcOffsetIEvenPhase meas1.sign
828 #define totalAdcDcOffsetQOddPhase meas2.sign
829 #define totalAdcDcOffsetQEvenPhase meas3.sign
830 union {
831 u32 unsign[AR5416_MAX_CHAINS];
832 int32_t sign[AR5416_MAX_CHAINS];
833 } meas0;
834 union {
835 u32 unsign[AR5416_MAX_CHAINS];
836 int32_t sign[AR5416_MAX_CHAINS];
837 } meas1;
838 union {
839 u32 unsign[AR5416_MAX_CHAINS];
840 int32_t sign[AR5416_MAX_CHAINS];
841 } meas2;
842 union {
843 u32 unsign[AR5416_MAX_CHAINS];
844 int32_t sign[AR5416_MAX_CHAINS];
845 } meas3;
846 u16 cal_samples;
847 u8 enabled_cals;
848
849 u32 sta_id1_defaults;
850 u32 misc_mode;
851
852 /* Private to hardware code */
853 struct ath_hw_private_ops private_ops;
854 /* Accessed by the lower level driver */
855 struct ath_hw_ops ops;
856
857 /* Used to program the radio on non single-chip devices */
858 u32 *analogBank6Data;
859
860 int coverage_class;
861 u32 slottime;
862 u32 globaltxtimeout;
863
864 /* ANI */
865 u32 aniperiod;
866 enum ath9k_ani_cmd ani_function;
867 u32 ani_skip_count;
868 struct ar5416AniState ani;
869
870 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
871 struct ath_btcoex_hw btcoex_hw;
872 #endif
873
874 u32 intr_txqs;
875 u8 txchainmask;
876 u8 rxchainmask;
877
878 struct ath_hw_radar_conf radar_conf;
879
880 u32 originalGain[22];
881 int initPDADC;
882 int PDADCdelta;
883 int led_pin;
884 u32 gpio_mask;
885 u32 gpio_val;
886
887 struct ar5416IniArray iniModes;
888 struct ar5416IniArray iniCommon;
889 struct ar5416IniArray iniBB_RfGain;
890 struct ar5416IniArray iniBank6;
891 struct ar5416IniArray iniAddac;
892 struct ar5416IniArray iniPcieSerdes;
893 struct ar5416IniArray iniPcieSerdesLowPower;
894 struct ar5416IniArray iniModesFastClock;
895 struct ar5416IniArray iniAdditional;
896 struct ar5416IniArray iniModesRxGain;
897 struct ar5416IniArray ini_modes_rx_gain_bounds;
898 struct ar5416IniArray iniModesTxGain;
899 struct ar5416IniArray iniCckfirNormal;
900 struct ar5416IniArray iniCckfirJapan2484;
901 struct ar5416IniArray iniModes_9271_ANI_reg;
902 struct ar5416IniArray ini_radio_post_sys2ant;
903 struct ar5416IniArray ini_modes_rxgain_5g_xlna;
904 struct ar5416IniArray ini_modes_rxgain_bb_core;
905 struct ar5416IniArray ini_modes_rxgain_bb_postamble;
906
907 struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT];
908 struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT];
909 struct ar5416IniArray iniRadio[ATH_INI_NUM_SPLIT];
910 struct ar5416IniArray iniSOC[ATH_INI_NUM_SPLIT];
911
912 u32 intr_gen_timer_trigger;
913 u32 intr_gen_timer_thresh;
914 struct ath_gen_timer_table hw_gen_timers;
915
916 struct ar9003_txs *ts_ring;
917 u32 ts_paddr_start;
918 u32 ts_paddr_end;
919 u16 ts_tail;
920 u16 ts_size;
921
922 u32 bb_watchdog_last_status;
923 u32 bb_watchdog_timeout_ms; /* in ms, 0 to disable */
924 u8 bb_hang_rx_ofdm; /* true if bb hang due to rx_ofdm */
925
926 unsigned int paprd_target_power;
927 unsigned int paprd_training_power;
928 unsigned int paprd_ratemask;
929 unsigned int paprd_ratemask_ht40;
930 bool paprd_table_write_done;
931 u32 paprd_gain_table_entries[PAPRD_GAIN_TABLE_ENTRIES];
932 u8 paprd_gain_table_index[PAPRD_GAIN_TABLE_ENTRIES];
933 /*
934 * Store the permanent value of Reg 0x4004in WARegVal
935 * so we dont have to R/M/W. We should not be reading
936 * this register when in sleep states.
937 */
938 u32 WARegVal;
939
940 /* Enterprise mode cap */
941 u32 ent_mode;
942
943 #ifdef CONFIG_PM_SLEEP
944 u32 wow_event_mask;
945 #endif
946 bool is_clk_25mhz;
947 int (*get_mac_revision)(void);
948 int (*external_reset)(void);
949
950 const struct firmware *eeprom_blob;
951 };
952
953 struct ath_bus_ops {
954 enum ath_bus_type ath_bus_type;
955 void (*read_cachesize)(struct ath_common *common, int *csz);
956 bool (*eeprom_read)(struct ath_common *common, u32 off, u16 *data);
957 void (*bt_coex_prep)(struct ath_common *common);
958 void (*aspm_init)(struct ath_common *common);
959 };
960
961 static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
962 {
963 return &ah->common;
964 }
965
966 static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah)
967 {
968 return &(ath9k_hw_common(ah)->regulatory);
969 }
970
971 static inline struct ath_hw_private_ops *ath9k_hw_private_ops(struct ath_hw *ah)
972 {
973 return &ah->private_ops;
974 }
975
976 static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah)
977 {
978 return &ah->ops;
979 }
980
981 static inline u8 get_streams(int mask)
982 {
983 return !!(mask & BIT(0)) + !!(mask & BIT(1)) + !!(mask & BIT(2));
984 }
985
986 /* Initialization, Detach, Reset */
987 void ath9k_hw_deinit(struct ath_hw *ah);
988 int ath9k_hw_init(struct ath_hw *ah);
989 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
990 struct ath9k_hw_cal_data *caldata, bool fastcc);
991 int ath9k_hw_fill_cap_info(struct ath_hw *ah);
992 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan);
993
994 /* GPIO / RFKILL / Antennae */
995 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio);
996 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio);
997 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
998 u32 ah_signal_type);
999 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val);
1000 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna);
1001
1002 /* General Operation */
1003 void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan,
1004 int hw_delay);
1005 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout);
1006 void ath9k_hw_write_array(struct ath_hw *ah, const struct ar5416IniArray *array,
1007 int column, unsigned int *writecnt);
1008 u32 ath9k_hw_reverse_bits(u32 val, u32 n);
1009 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
1010 u8 phy, int kbps,
1011 u32 frameLen, u16 rateix, bool shortPreamble);
1012 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
1013 struct ath9k_channel *chan,
1014 struct chan_centers *centers);
1015 u32 ath9k_hw_getrxfilter(struct ath_hw *ah);
1016 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits);
1017 bool ath9k_hw_phy_disable(struct ath_hw *ah);
1018 bool ath9k_hw_disable(struct ath_hw *ah);
1019 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test);
1020 void ath9k_hw_setopmode(struct ath_hw *ah);
1021 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1);
1022 void ath9k_hw_write_associd(struct ath_hw *ah);
1023 u32 ath9k_hw_gettsf32(struct ath_hw *ah);
1024 u64 ath9k_hw_gettsf64(struct ath_hw *ah);
1025 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64);
1026 void ath9k_hw_reset_tsf(struct ath_hw *ah);
1027 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set);
1028 void ath9k_hw_init_global_settings(struct ath_hw *ah);
1029 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah);
1030 void ath9k_hw_set11nmac2040(struct ath_hw *ah);
1031 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period);
1032 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
1033 const struct ath9k_beacon_state *bs);
1034 bool ath9k_hw_check_alive(struct ath_hw *ah);
1035
1036 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode);
1037
1038 #ifdef CONFIG_ATH9K_DEBUGFS
1039 void ath9k_debug_sync_cause(struct ath_common *common, u32 sync_cause);
1040 #else
1041 static inline void ath9k_debug_sync_cause(struct ath_common *common,
1042 u32 sync_cause) {}
1043 #endif
1044
1045 /* Generic hw timer primitives */
1046 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
1047 void (*trigger)(void *),
1048 void (*overflow)(void *),
1049 void *arg,
1050 u8 timer_index);
1051 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
1052 struct ath_gen_timer *timer,
1053 u32 timer_next,
1054 u32 timer_period);
1055 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer);
1056
1057 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer);
1058 void ath_gen_timer_isr(struct ath_hw *hw);
1059
1060 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len);
1061
1062 /* PHY */
1063 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1064 u32 *coef_mantissa, u32 *coef_exponent);
1065 void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan,
1066 bool test);
1067
1068 /*
1069 * Code Specific to AR5008, AR9001 or AR9002,
1070 * we stuff these here to avoid callbacks for AR9003.
1071 */
1072 int ar9002_hw_rf_claim(struct ath_hw *ah);
1073 void ar9002_hw_enable_async_fifo(struct ath_hw *ah);
1074
1075 /*
1076 * Code specific to AR9003, we stuff these here to avoid callbacks
1077 * for older families
1078 */
1079 void ar9003_hw_bb_watchdog_config(struct ath_hw *ah);
1080 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah);
1081 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah);
1082 void ar9003_hw_disable_phy_restart(struct ath_hw *ah);
1083 void ar9003_paprd_enable(struct ath_hw *ah, bool val);
1084 void ar9003_paprd_populate_single_table(struct ath_hw *ah,
1085 struct ath9k_hw_cal_data *caldata,
1086 int chain);
1087 int ar9003_paprd_create_curve(struct ath_hw *ah,
1088 struct ath9k_hw_cal_data *caldata, int chain);
1089 void ar9003_paprd_setup_gain_table(struct ath_hw *ah, int chain);
1090 int ar9003_paprd_init_table(struct ath_hw *ah);
1091 bool ar9003_paprd_is_done(struct ath_hw *ah);
1092 bool ar9003_is_paprd_enabled(struct ath_hw *ah);
1093 void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx);
1094
1095 /* Hardware family op attach helpers */
1096 int ar5008_hw_attach_phy_ops(struct ath_hw *ah);
1097 void ar9002_hw_attach_phy_ops(struct ath_hw *ah);
1098 void ar9003_hw_attach_phy_ops(struct ath_hw *ah);
1099
1100 void ar9002_hw_attach_calib_ops(struct ath_hw *ah);
1101 void ar9003_hw_attach_calib_ops(struct ath_hw *ah);
1102
1103 int ar9002_hw_attach_ops(struct ath_hw *ah);
1104 void ar9003_hw_attach_ops(struct ath_hw *ah);
1105
1106 void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan);
1107
1108 void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning);
1109 void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan);
1110
1111 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
1112 static inline bool ath9k_hw_btcoex_is_enabled(struct ath_hw *ah)
1113 {
1114 return ah->btcoex_hw.enabled;
1115 }
1116 static inline bool ath9k_hw_mci_is_enabled(struct ath_hw *ah)
1117 {
1118 return ah->common.btcoex_enabled &&
1119 (ah->caps.hw_caps & ATH9K_HW_CAP_MCI);
1120
1121 }
1122 void ath9k_hw_btcoex_enable(struct ath_hw *ah);
1123 static inline enum ath_btcoex_scheme
1124 ath9k_hw_get_btcoex_scheme(struct ath_hw *ah)
1125 {
1126 return ah->btcoex_hw.scheme;
1127 }
1128 #else
1129 static inline bool ath9k_hw_btcoex_is_enabled(struct ath_hw *ah)
1130 {
1131 return false;
1132 }
1133 static inline bool ath9k_hw_mci_is_enabled(struct ath_hw *ah)
1134 {
1135 return false;
1136 }
1137 static inline void ath9k_hw_btcoex_enable(struct ath_hw *ah)
1138 {
1139 }
1140 static inline enum ath_btcoex_scheme
1141 ath9k_hw_get_btcoex_scheme(struct ath_hw *ah)
1142 {
1143 return ATH_BTCOEX_CFG_NONE;
1144 }
1145 #endif /* CONFIG_ATH9K_BTCOEX_SUPPORT */
1146
1147
1148 #ifdef CONFIG_PM_SLEEP
1149 const char *ath9k_hw_wow_event_to_string(u32 wow_event);
1150 void ath9k_hw_wow_apply_pattern(struct ath_hw *ah, u8 *user_pattern,
1151 u8 *user_mask, int pattern_count,
1152 int pattern_len);
1153 u32 ath9k_hw_wow_wakeup(struct ath_hw *ah);
1154 void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable);
1155 #else
1156 static inline const char *ath9k_hw_wow_event_to_string(u32 wow_event)
1157 {
1158 return NULL;
1159 }
1160 static inline void ath9k_hw_wow_apply_pattern(struct ath_hw *ah,
1161 u8 *user_pattern,
1162 u8 *user_mask,
1163 int pattern_count,
1164 int pattern_len)
1165 {
1166 }
1167 static inline u32 ath9k_hw_wow_wakeup(struct ath_hw *ah)
1168 {
1169 return 0;
1170 }
1171 static inline void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable)
1172 {
1173 }
1174 #endif
1175
1176 #define ATH9K_CLOCK_RATE_CCK 22
1177 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
1178 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
1179 #define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44
1180
1181 #endif
Linux kernel - Deliverables
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