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ath9k: use the devres API for allocations/mappings
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / init.c
1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
18
19 #include <linux/dma-mapping.h>
20 #include <linux/slab.h>
21 #include <linux/ath9k_platform.h>
22 #include <linux/module.h>
23
24 #include "ath9k.h"
25
26 struct ath9k_eeprom_ctx {
27 struct completion complete;
28 struct ath_hw *ah;
29 };
30
31 static char *dev_info = "ath9k";
32
33 MODULE_AUTHOR("Atheros Communications");
34 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
35 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
36 MODULE_LICENSE("Dual BSD/GPL");
37
38 static unsigned int ath9k_debug = ATH_DBG_DEFAULT;
39 module_param_named(debug, ath9k_debug, uint, 0);
40 MODULE_PARM_DESC(debug, "Debugging mask");
41
42 int ath9k_modparam_nohwcrypt;
43 module_param_named(nohwcrypt, ath9k_modparam_nohwcrypt, int, 0444);
44 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
45
46 int led_blink;
47 module_param_named(blink, led_blink, int, 0444);
48 MODULE_PARM_DESC(blink, "Enable LED blink on activity");
49
50 static int ath9k_btcoex_enable;
51 module_param_named(btcoex_enable, ath9k_btcoex_enable, int, 0444);
52 MODULE_PARM_DESC(btcoex_enable, "Enable wifi-BT coexistence");
53
54 static int ath9k_enable_diversity;
55 module_param_named(enable_diversity, ath9k_enable_diversity, int, 0444);
56 MODULE_PARM_DESC(enable_diversity, "Enable Antenna diversity for AR9565");
57
58 bool is_ath9k_unloaded;
59 /* We use the hw_value as an index into our private channel structure */
60
61 #define CHAN2G(_freq, _idx) { \
62 .band = IEEE80211_BAND_2GHZ, \
63 .center_freq = (_freq), \
64 .hw_value = (_idx), \
65 .max_power = 20, \
66 }
67
68 #define CHAN5G(_freq, _idx) { \
69 .band = IEEE80211_BAND_5GHZ, \
70 .center_freq = (_freq), \
71 .hw_value = (_idx), \
72 .max_power = 20, \
73 }
74
75 /* Some 2 GHz radios are actually tunable on 2312-2732
76 * on 5 MHz steps, we support the channels which we know
77 * we have calibration data for all cards though to make
78 * this static */
79 static const struct ieee80211_channel ath9k_2ghz_chantable[] = {
80 CHAN2G(2412, 0), /* Channel 1 */
81 CHAN2G(2417, 1), /* Channel 2 */
82 CHAN2G(2422, 2), /* Channel 3 */
83 CHAN2G(2427, 3), /* Channel 4 */
84 CHAN2G(2432, 4), /* Channel 5 */
85 CHAN2G(2437, 5), /* Channel 6 */
86 CHAN2G(2442, 6), /* Channel 7 */
87 CHAN2G(2447, 7), /* Channel 8 */
88 CHAN2G(2452, 8), /* Channel 9 */
89 CHAN2G(2457, 9), /* Channel 10 */
90 CHAN2G(2462, 10), /* Channel 11 */
91 CHAN2G(2467, 11), /* Channel 12 */
92 CHAN2G(2472, 12), /* Channel 13 */
93 CHAN2G(2484, 13), /* Channel 14 */
94 };
95
96 /* Some 5 GHz radios are actually tunable on XXXX-YYYY
97 * on 5 MHz steps, we support the channels which we know
98 * we have calibration data for all cards though to make
99 * this static */
100 static const struct ieee80211_channel ath9k_5ghz_chantable[] = {
101 /* _We_ call this UNII 1 */
102 CHAN5G(5180, 14), /* Channel 36 */
103 CHAN5G(5200, 15), /* Channel 40 */
104 CHAN5G(5220, 16), /* Channel 44 */
105 CHAN5G(5240, 17), /* Channel 48 */
106 /* _We_ call this UNII 2 */
107 CHAN5G(5260, 18), /* Channel 52 */
108 CHAN5G(5280, 19), /* Channel 56 */
109 CHAN5G(5300, 20), /* Channel 60 */
110 CHAN5G(5320, 21), /* Channel 64 */
111 /* _We_ call this "Middle band" */
112 CHAN5G(5500, 22), /* Channel 100 */
113 CHAN5G(5520, 23), /* Channel 104 */
114 CHAN5G(5540, 24), /* Channel 108 */
115 CHAN5G(5560, 25), /* Channel 112 */
116 CHAN5G(5580, 26), /* Channel 116 */
117 CHAN5G(5600, 27), /* Channel 120 */
118 CHAN5G(5620, 28), /* Channel 124 */
119 CHAN5G(5640, 29), /* Channel 128 */
120 CHAN5G(5660, 30), /* Channel 132 */
121 CHAN5G(5680, 31), /* Channel 136 */
122 CHAN5G(5700, 32), /* Channel 140 */
123 /* _We_ call this UNII 3 */
124 CHAN5G(5745, 33), /* Channel 149 */
125 CHAN5G(5765, 34), /* Channel 153 */
126 CHAN5G(5785, 35), /* Channel 157 */
127 CHAN5G(5805, 36), /* Channel 161 */
128 CHAN5G(5825, 37), /* Channel 165 */
129 };
130
131 /* Atheros hardware rate code addition for short premble */
132 #define SHPCHECK(__hw_rate, __flags) \
133 ((__flags & IEEE80211_RATE_SHORT_PREAMBLE) ? (__hw_rate | 0x04 ) : 0)
134
135 #define RATE(_bitrate, _hw_rate, _flags) { \
136 .bitrate = (_bitrate), \
137 .flags = (_flags), \
138 .hw_value = (_hw_rate), \
139 .hw_value_short = (SHPCHECK(_hw_rate, _flags)) \
140 }
141
142 static struct ieee80211_rate ath9k_legacy_rates[] = {
143 RATE(10, 0x1b, 0),
144 RATE(20, 0x1a, IEEE80211_RATE_SHORT_PREAMBLE),
145 RATE(55, 0x19, IEEE80211_RATE_SHORT_PREAMBLE),
146 RATE(110, 0x18, IEEE80211_RATE_SHORT_PREAMBLE),
147 RATE(60, 0x0b, 0),
148 RATE(90, 0x0f, 0),
149 RATE(120, 0x0a, 0),
150 RATE(180, 0x0e, 0),
151 RATE(240, 0x09, 0),
152 RATE(360, 0x0d, 0),
153 RATE(480, 0x08, 0),
154 RATE(540, 0x0c, 0),
155 };
156
157 #ifdef CONFIG_MAC80211_LEDS
158 static const struct ieee80211_tpt_blink ath9k_tpt_blink[] = {
159 { .throughput = 0 * 1024, .blink_time = 334 },
160 { .throughput = 1 * 1024, .blink_time = 260 },
161 { .throughput = 5 * 1024, .blink_time = 220 },
162 { .throughput = 10 * 1024, .blink_time = 190 },
163 { .throughput = 20 * 1024, .blink_time = 170 },
164 { .throughput = 50 * 1024, .blink_time = 150 },
165 { .throughput = 70 * 1024, .blink_time = 130 },
166 { .throughput = 100 * 1024, .blink_time = 110 },
167 { .throughput = 200 * 1024, .blink_time = 80 },
168 { .throughput = 300 * 1024, .blink_time = 50 },
169 };
170 #endif
171
172 static void ath9k_deinit_softc(struct ath_softc *sc);
173
174 /*
175 * Read and write, they both share the same lock. We do this to serialize
176 * reads and writes on Atheros 802.11n PCI devices only. This is required
177 * as the FIFO on these devices can only accept sanely 2 requests.
178 */
179
180 static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
181 {
182 struct ath_hw *ah = (struct ath_hw *) hw_priv;
183 struct ath_common *common = ath9k_hw_common(ah);
184 struct ath_softc *sc = (struct ath_softc *) common->priv;
185
186 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) {
187 unsigned long flags;
188 spin_lock_irqsave(&sc->sc_serial_rw, flags);
189 iowrite32(val, sc->mem + reg_offset);
190 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
191 } else
192 iowrite32(val, sc->mem + reg_offset);
193 }
194
195 static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset)
196 {
197 struct ath_hw *ah = (struct ath_hw *) hw_priv;
198 struct ath_common *common = ath9k_hw_common(ah);
199 struct ath_softc *sc = (struct ath_softc *) common->priv;
200 u32 val;
201
202 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) {
203 unsigned long flags;
204 spin_lock_irqsave(&sc->sc_serial_rw, flags);
205 val = ioread32(sc->mem + reg_offset);
206 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
207 } else
208 val = ioread32(sc->mem + reg_offset);
209 return val;
210 }
211
212 static unsigned int __ath9k_reg_rmw(struct ath_softc *sc, u32 reg_offset,
213 u32 set, u32 clr)
214 {
215 u32 val;
216
217 val = ioread32(sc->mem + reg_offset);
218 val &= ~clr;
219 val |= set;
220 iowrite32(val, sc->mem + reg_offset);
221
222 return val;
223 }
224
225 static unsigned int ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr)
226 {
227 struct ath_hw *ah = (struct ath_hw *) hw_priv;
228 struct ath_common *common = ath9k_hw_common(ah);
229 struct ath_softc *sc = (struct ath_softc *) common->priv;
230 unsigned long uninitialized_var(flags);
231 u32 val;
232
233 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) {
234 spin_lock_irqsave(&sc->sc_serial_rw, flags);
235 val = __ath9k_reg_rmw(sc, reg_offset, set, clr);
236 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
237 } else
238 val = __ath9k_reg_rmw(sc, reg_offset, set, clr);
239
240 return val;
241 }
242
243 /**************************/
244 /* Initialization */
245 /**************************/
246
247 static void setup_ht_cap(struct ath_softc *sc,
248 struct ieee80211_sta_ht_cap *ht_info)
249 {
250 struct ath_hw *ah = sc->sc_ah;
251 struct ath_common *common = ath9k_hw_common(ah);
252 u8 tx_streams, rx_streams;
253 int i, max_streams;
254
255 ht_info->ht_supported = true;
256 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
257 IEEE80211_HT_CAP_SM_PS |
258 IEEE80211_HT_CAP_SGI_40 |
259 IEEE80211_HT_CAP_DSSSCCK40;
260
261 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_LDPC)
262 ht_info->cap |= IEEE80211_HT_CAP_LDPC_CODING;
263
264 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_SGI_20)
265 ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
266
267 ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
268 ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
269
270 if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah))
271 max_streams = 1;
272 else if (AR_SREV_9462(ah))
273 max_streams = 2;
274 else if (AR_SREV_9300_20_OR_LATER(ah))
275 max_streams = 3;
276 else
277 max_streams = 2;
278
279 if (AR_SREV_9280_20_OR_LATER(ah)) {
280 if (max_streams >= 2)
281 ht_info->cap |= IEEE80211_HT_CAP_TX_STBC;
282 ht_info->cap |= (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT);
283 }
284
285 /* set up supported mcs set */
286 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
287 tx_streams = ath9k_cmn_count_streams(ah->txchainmask, max_streams);
288 rx_streams = ath9k_cmn_count_streams(ah->rxchainmask, max_streams);
289
290 ath_dbg(common, CONFIG, "TX streams %d, RX streams: %d\n",
291 tx_streams, rx_streams);
292
293 if (tx_streams != rx_streams) {
294 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
295 ht_info->mcs.tx_params |= ((tx_streams - 1) <<
296 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
297 }
298
299 for (i = 0; i < rx_streams; i++)
300 ht_info->mcs.rx_mask[i] = 0xff;
301
302 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
303 }
304
305 static int ath9k_reg_notifier(struct wiphy *wiphy,
306 struct regulatory_request *request)
307 {
308 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
309 struct ath_softc *sc = hw->priv;
310 struct ath_hw *ah = sc->sc_ah;
311 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
312 int ret;
313
314 ret = ath_reg_notifier_apply(wiphy, request, reg);
315
316 /* Set tx power */
317 if (ah->curchan) {
318 sc->config.txpowlimit = 2 * ah->curchan->chan->max_power;
319 ath9k_ps_wakeup(sc);
320 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit, false);
321 sc->curtxpow = ath9k_hw_regulatory(ah)->power_limit;
322 ath9k_ps_restore(sc);
323 }
324
325 return ret;
326 }
327
328 /*
329 * This function will allocate both the DMA descriptor structure, and the
330 * buffers it contains. These are used to contain the descriptors used
331 * by the system.
332 */
333 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
334 struct list_head *head, const char *name,
335 int nbuf, int ndesc, bool is_tx)
336 {
337 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
338 u8 *ds;
339 struct ath_buf *bf;
340 int i, bsize, desc_len;
341
342 ath_dbg(common, CONFIG, "%s DMA: %u buffers %u desc/buf\n",
343 name, nbuf, ndesc);
344
345 INIT_LIST_HEAD(head);
346
347 if (is_tx)
348 desc_len = sc->sc_ah->caps.tx_desc_len;
349 else
350 desc_len = sizeof(struct ath_desc);
351
352 /* ath_desc must be a multiple of DWORDs */
353 if ((desc_len % 4) != 0) {
354 ath_err(common, "ath_desc not DWORD aligned\n");
355 BUG_ON((desc_len % 4) != 0);
356 return -ENOMEM;
357 }
358
359 dd->dd_desc_len = desc_len * nbuf * ndesc;
360
361 /*
362 * Need additional DMA memory because we can't use
363 * descriptors that cross the 4K page boundary. Assume
364 * one skipped descriptor per 4K page.
365 */
366 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
367 u32 ndesc_skipped =
368 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
369 u32 dma_len;
370
371 while (ndesc_skipped) {
372 dma_len = ndesc_skipped * desc_len;
373 dd->dd_desc_len += dma_len;
374
375 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
376 }
377 }
378
379 /* allocate descriptors */
380 dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len,
381 &dd->dd_desc_paddr, GFP_KERNEL);
382 if (!dd->dd_desc)
383 return -ENOMEM;
384
385 ds = (u8 *) dd->dd_desc;
386 ath_dbg(common, CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
387 name, ds, (u32) dd->dd_desc_len,
388 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
389
390 /* allocate buffers */
391 bsize = sizeof(struct ath_buf) * nbuf;
392 bf = devm_kzalloc(sc->dev, bsize, GFP_KERNEL);
393 if (!bf)
394 return -ENOMEM;
395
396 for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) {
397 bf->bf_desc = ds;
398 bf->bf_daddr = DS2PHYS(dd, ds);
399
400 if (!(sc->sc_ah->caps.hw_caps &
401 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
402 /*
403 * Skip descriptor addresses which can cause 4KB
404 * boundary crossing (addr + length) with a 32 dword
405 * descriptor fetch.
406 */
407 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
408 BUG_ON((caddr_t) bf->bf_desc >=
409 ((caddr_t) dd->dd_desc +
410 dd->dd_desc_len));
411
412 ds += (desc_len * ndesc);
413 bf->bf_desc = ds;
414 bf->bf_daddr = DS2PHYS(dd, ds);
415 }
416 }
417 list_add_tail(&bf->list, head);
418 }
419 return 0;
420 }
421
422 static int ath9k_init_queues(struct ath_softc *sc)
423 {
424 int i = 0;
425
426 sc->beacon.beaconq = ath9k_hw_beaconq_setup(sc->sc_ah);
427 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
428
429 sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
430 ath_cabq_update(sc);
431
432 for (i = 0; i < IEEE80211_NUM_ACS; i++) {
433 sc->tx.txq_map[i] = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, i);
434 sc->tx.txq_map[i]->mac80211_qnum = i;
435 sc->tx.txq_max_pending[i] = ATH_MAX_QDEPTH;
436 }
437 return 0;
438 }
439
440 static int ath9k_init_channels_rates(struct ath_softc *sc)
441 {
442 void *channels;
443
444 BUILD_BUG_ON(ARRAY_SIZE(ath9k_2ghz_chantable) +
445 ARRAY_SIZE(ath9k_5ghz_chantable) !=
446 ATH9K_NUM_CHANNELS);
447
448 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) {
449 channels = devm_kzalloc(sc->dev,
450 sizeof(ath9k_2ghz_chantable), GFP_KERNEL);
451 if (!channels)
452 return -ENOMEM;
453
454 memcpy(channels, ath9k_2ghz_chantable,
455 sizeof(ath9k_2ghz_chantable));
456 sc->sbands[IEEE80211_BAND_2GHZ].channels = channels;
457 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
458 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
459 ARRAY_SIZE(ath9k_2ghz_chantable);
460 sc->sbands[IEEE80211_BAND_2GHZ].bitrates = ath9k_legacy_rates;
461 sc->sbands[IEEE80211_BAND_2GHZ].n_bitrates =
462 ARRAY_SIZE(ath9k_legacy_rates);
463 }
464
465 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) {
466 channels = devm_kzalloc(sc->dev,
467 sizeof(ath9k_5ghz_chantable), GFP_KERNEL);
468 if (!channels)
469 return -ENOMEM;
470
471 memcpy(channels, ath9k_5ghz_chantable,
472 sizeof(ath9k_5ghz_chantable));
473 sc->sbands[IEEE80211_BAND_5GHZ].channels = channels;
474 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
475 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
476 ARRAY_SIZE(ath9k_5ghz_chantable);
477 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
478 ath9k_legacy_rates + 4;
479 sc->sbands[IEEE80211_BAND_5GHZ].n_bitrates =
480 ARRAY_SIZE(ath9k_legacy_rates) - 4;
481 }
482 return 0;
483 }
484
485 static void ath9k_init_misc(struct ath_softc *sc)
486 {
487 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
488 int i = 0;
489
490 setup_timer(&common->ani.timer, ath_ani_calibrate, (unsigned long)sc);
491
492 sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
493 sc->config.txpowlimit = ATH_TXPOWER_MAX;
494 memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN);
495 sc->beacon.slottime = ATH9K_SLOT_TIME_9;
496
497 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++)
498 sc->beacon.bslot[i] = NULL;
499
500 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB)
501 sc->ant_comb.count = ATH_ANT_DIV_COMB_INIT_COUNT;
502 }
503
504 static void ath9k_eeprom_request_cb(const struct firmware *eeprom_blob,
505 void *ctx)
506 {
507 struct ath9k_eeprom_ctx *ec = ctx;
508
509 if (eeprom_blob)
510 ec->ah->eeprom_blob = eeprom_blob;
511
512 complete(&ec->complete);
513 }
514
515 static int ath9k_eeprom_request(struct ath_softc *sc, const char *name)
516 {
517 struct ath9k_eeprom_ctx ec;
518 struct ath_hw *ah = ah = sc->sc_ah;
519 int err;
520
521 /* try to load the EEPROM content asynchronously */
522 init_completion(&ec.complete);
523 ec.ah = sc->sc_ah;
524
525 err = request_firmware_nowait(THIS_MODULE, 1, name, sc->dev, GFP_KERNEL,
526 &ec, ath9k_eeprom_request_cb);
527 if (err < 0) {
528 ath_err(ath9k_hw_common(ah),
529 "EEPROM request failed\n");
530 return err;
531 }
532
533 wait_for_completion(&ec.complete);
534
535 if (!ah->eeprom_blob) {
536 ath_err(ath9k_hw_common(ah),
537 "Unable to load EEPROM file %s\n", name);
538 return -EINVAL;
539 }
540
541 return 0;
542 }
543
544 static void ath9k_eeprom_release(struct ath_softc *sc)
545 {
546 release_firmware(sc->sc_ah->eeprom_blob);
547 }
548
549 static int ath9k_init_softc(u16 devid, struct ath_softc *sc,
550 const struct ath_bus_ops *bus_ops)
551 {
552 struct ath9k_platform_data *pdata = sc->dev->platform_data;
553 struct ath_hw *ah = NULL;
554 struct ath_common *common;
555 int ret = 0, i;
556 int csz = 0;
557
558 ah = devm_kzalloc(sc->dev, sizeof(struct ath_hw), GFP_KERNEL);
559 if (!ah)
560 return -ENOMEM;
561
562 ah->hw = sc->hw;
563 ah->hw_version.devid = devid;
564 ah->reg_ops.read = ath9k_ioread32;
565 ah->reg_ops.write = ath9k_iowrite32;
566 ah->reg_ops.rmw = ath9k_reg_rmw;
567 atomic_set(&ah->intr_ref_cnt, -1);
568 sc->sc_ah = ah;
569
570 sc->dfs_detector = dfs_pattern_detector_init(NL80211_DFS_UNSET);
571
572 if (!pdata) {
573 ah->ah_flags |= AH_USE_EEPROM;
574 sc->sc_ah->led_pin = -1;
575 } else {
576 sc->sc_ah->gpio_mask = pdata->gpio_mask;
577 sc->sc_ah->gpio_val = pdata->gpio_val;
578 sc->sc_ah->led_pin = pdata->led_pin;
579 ah->is_clk_25mhz = pdata->is_clk_25mhz;
580 ah->get_mac_revision = pdata->get_mac_revision;
581 ah->external_reset = pdata->external_reset;
582 }
583
584 common = ath9k_hw_common(ah);
585 common->ops = &ah->reg_ops;
586 common->bus_ops = bus_ops;
587 common->ah = ah;
588 common->hw = sc->hw;
589 common->priv = sc;
590 common->debug_mask = ath9k_debug;
591 common->btcoex_enabled = ath9k_btcoex_enable == 1;
592 common->disable_ani = false;
593
594 /*
595 * Enable Antenna diversity only when BTCOEX is disabled
596 * and the user manually requests the feature.
597 */
598 if (!common->btcoex_enabled && ath9k_enable_diversity)
599 common->antenna_diversity = 1;
600
601 spin_lock_init(&common->cc_lock);
602
603 spin_lock_init(&sc->sc_serial_rw);
604 spin_lock_init(&sc->sc_pm_lock);
605 mutex_init(&sc->mutex);
606 #ifdef CONFIG_ATH9K_MAC_DEBUG
607 spin_lock_init(&sc->debug.samp_lock);
608 #endif
609 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
610 tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet,
611 (unsigned long)sc);
612
613 INIT_WORK(&sc->hw_reset_work, ath_reset_work);
614 INIT_WORK(&sc->hw_check_work, ath_hw_check);
615 INIT_WORK(&sc->paprd_work, ath_paprd_calibrate);
616 INIT_DELAYED_WORK(&sc->hw_pll_work, ath_hw_pll_work);
617 setup_timer(&sc->rx_poll_timer, ath_rx_poll, (unsigned long)sc);
618
619 /*
620 * Cache line size is used to size and align various
621 * structures used to communicate with the hardware.
622 */
623 ath_read_cachesize(common, &csz);
624 common->cachelsz = csz << 2; /* convert to bytes */
625
626 if (pdata && pdata->eeprom_name) {
627 ret = ath9k_eeprom_request(sc, pdata->eeprom_name);
628 if (ret)
629 return ret;
630 }
631
632 /* Initializes the hardware for all supported chipsets */
633 ret = ath9k_hw_init(ah);
634 if (ret)
635 goto err_hw;
636
637 if (pdata && pdata->macaddr)
638 memcpy(common->macaddr, pdata->macaddr, ETH_ALEN);
639
640 ret = ath9k_init_queues(sc);
641 if (ret)
642 goto err_queues;
643
644 ret = ath9k_init_btcoex(sc);
645 if (ret)
646 goto err_btcoex;
647
648 ret = ath9k_init_channels_rates(sc);
649 if (ret)
650 goto err_btcoex;
651
652 ath9k_cmn_init_crypto(sc->sc_ah);
653 ath9k_init_misc(sc);
654 ath_fill_led_pin(sc);
655
656 if (common->bus_ops->aspm_init)
657 common->bus_ops->aspm_init(common);
658
659 return 0;
660
661 err_btcoex:
662 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
663 if (ATH_TXQ_SETUP(sc, i))
664 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
665 err_queues:
666 ath9k_hw_deinit(ah);
667 err_hw:
668 ath9k_eeprom_release(sc);
669 return ret;
670 }
671
672 static void ath9k_init_band_txpower(struct ath_softc *sc, int band)
673 {
674 struct ieee80211_supported_band *sband;
675 struct ieee80211_channel *chan;
676 struct ath_hw *ah = sc->sc_ah;
677 int i;
678
679 sband = &sc->sbands[band];
680 for (i = 0; i < sband->n_channels; i++) {
681 chan = &sband->channels[i];
682 ah->curchan = &ah->channels[chan->hw_value];
683 ath9k_cmn_update_ichannel(ah->curchan, chan, NL80211_CHAN_HT20);
684 ath9k_hw_set_txpowerlimit(ah, MAX_RATE_POWER, true);
685 }
686 }
687
688 static void ath9k_init_txpower_limits(struct ath_softc *sc)
689 {
690 struct ath_hw *ah = sc->sc_ah;
691 struct ath9k_channel *curchan = ah->curchan;
692
693 if (ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
694 ath9k_init_band_txpower(sc, IEEE80211_BAND_2GHZ);
695 if (ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
696 ath9k_init_band_txpower(sc, IEEE80211_BAND_5GHZ);
697
698 ah->curchan = curchan;
699 }
700
701 void ath9k_reload_chainmask_settings(struct ath_softc *sc)
702 {
703 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT))
704 return;
705
706 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
707 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
708 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
709 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
710 }
711
712 static const struct ieee80211_iface_limit if_limits[] = {
713 { .max = 2048, .types = BIT(NL80211_IFTYPE_STATION) |
714 BIT(NL80211_IFTYPE_P2P_CLIENT) |
715 BIT(NL80211_IFTYPE_WDS) },
716 { .max = 8, .types =
717 #ifdef CONFIG_MAC80211_MESH
718 BIT(NL80211_IFTYPE_MESH_POINT) |
719 #endif
720 BIT(NL80211_IFTYPE_AP) |
721 BIT(NL80211_IFTYPE_P2P_GO) },
722 };
723
724 static const struct ieee80211_iface_combination if_comb = {
725 .limits = if_limits,
726 .n_limits = ARRAY_SIZE(if_limits),
727 .max_interfaces = 2048,
728 .num_different_channels = 1,
729 .beacon_int_infra_match = true,
730 };
731
732 void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
733 {
734 struct ath_hw *ah = sc->sc_ah;
735 struct ath_common *common = ath9k_hw_common(ah);
736
737 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
738 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
739 IEEE80211_HW_SIGNAL_DBM |
740 IEEE80211_HW_SUPPORTS_PS |
741 IEEE80211_HW_PS_NULLFUNC_STACK |
742 IEEE80211_HW_SPECTRUM_MGMT |
743 IEEE80211_HW_REPORTS_TX_ACK_STATUS;
744
745 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
746 hw->flags |= IEEE80211_HW_AMPDU_AGGREGATION;
747
748 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || ath9k_modparam_nohwcrypt)
749 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
750
751 hw->wiphy->interface_modes =
752 BIT(NL80211_IFTYPE_P2P_GO) |
753 BIT(NL80211_IFTYPE_P2P_CLIENT) |
754 BIT(NL80211_IFTYPE_AP) |
755 BIT(NL80211_IFTYPE_WDS) |
756 BIT(NL80211_IFTYPE_STATION) |
757 BIT(NL80211_IFTYPE_ADHOC) |
758 BIT(NL80211_IFTYPE_MESH_POINT);
759
760 hw->wiphy->iface_combinations = &if_comb;
761 hw->wiphy->n_iface_combinations = 1;
762
763 if (AR_SREV_5416(sc->sc_ah))
764 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
765
766 hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN;
767 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS;
768 hw->wiphy->flags |= WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL;
769
770 #ifdef CONFIG_PM_SLEEP
771
772 if ((ah->caps.hw_caps & ATH9K_HW_WOW_DEVICE_CAPABLE) &&
773 device_can_wakeup(sc->dev)) {
774
775 hw->wiphy->wowlan.flags = WIPHY_WOWLAN_MAGIC_PKT |
776 WIPHY_WOWLAN_DISCONNECT;
777 hw->wiphy->wowlan.n_patterns = MAX_NUM_USER_PATTERN;
778 hw->wiphy->wowlan.pattern_min_len = 1;
779 hw->wiphy->wowlan.pattern_max_len = MAX_PATTERN_SIZE;
780
781 }
782
783 atomic_set(&sc->wow_sleep_proc_intr, -1);
784 atomic_set(&sc->wow_got_bmiss_intr, -1);
785
786 #endif
787
788 hw->queues = 4;
789 hw->max_rates = 4;
790 hw->channel_change_time = 5000;
791 hw->max_listen_interval = 1;
792 hw->max_rate_tries = 10;
793 hw->sta_data_size = sizeof(struct ath_node);
794 hw->vif_data_size = sizeof(struct ath_vif);
795
796 hw->wiphy->available_antennas_rx = BIT(ah->caps.max_rxchains) - 1;
797 hw->wiphy->available_antennas_tx = BIT(ah->caps.max_txchains) - 1;
798
799 /* single chain devices with rx diversity */
800 if (ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB)
801 hw->wiphy->available_antennas_rx = BIT(0) | BIT(1);
802
803 sc->ant_rx = hw->wiphy->available_antennas_rx;
804 sc->ant_tx = hw->wiphy->available_antennas_tx;
805
806 #ifdef CONFIG_ATH9K_RATE_CONTROL
807 hw->rate_control_algorithm = "ath9k_rate_control";
808 #endif
809
810 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
811 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
812 &sc->sbands[IEEE80211_BAND_2GHZ];
813 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
814 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
815 &sc->sbands[IEEE80211_BAND_5GHZ];
816
817 ath9k_reload_chainmask_settings(sc);
818
819 SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
820 }
821
822 int ath9k_init_device(u16 devid, struct ath_softc *sc,
823 const struct ath_bus_ops *bus_ops)
824 {
825 struct ieee80211_hw *hw = sc->hw;
826 struct ath_common *common;
827 struct ath_hw *ah;
828 int error = 0;
829 struct ath_regulatory *reg;
830
831 /* Bring up device */
832 error = ath9k_init_softc(devid, sc, bus_ops);
833 if (error)
834 return error;
835
836 ah = sc->sc_ah;
837 common = ath9k_hw_common(ah);
838 ath9k_set_hw_capab(sc, hw);
839
840 /* Initialize regulatory */
841 error = ath_regd_init(&common->regulatory, sc->hw->wiphy,
842 ath9k_reg_notifier);
843 if (error)
844 goto deinit;
845
846 reg = &common->regulatory;
847
848 /* Setup TX DMA */
849 error = ath_tx_init(sc, ATH_TXBUF);
850 if (error != 0)
851 goto deinit;
852
853 /* Setup RX DMA */
854 error = ath_rx_init(sc, ATH_RXBUF);
855 if (error != 0)
856 goto deinit;
857
858 ath9k_init_txpower_limits(sc);
859
860 #ifdef CONFIG_MAC80211_LEDS
861 /* must be initialized before ieee80211_register_hw */
862 sc->led_cdev.default_trigger = ieee80211_create_tpt_led_trigger(sc->hw,
863 IEEE80211_TPT_LEDTRIG_FL_RADIO, ath9k_tpt_blink,
864 ARRAY_SIZE(ath9k_tpt_blink));
865 #endif
866
867 /* Register with mac80211 */
868 error = ieee80211_register_hw(hw);
869 if (error)
870 goto rx_cleanup;
871
872 error = ath9k_init_debug(ah);
873 if (error) {
874 ath_err(common, "Unable to create debugfs files\n");
875 goto unregister;
876 }
877
878 /* Handle world regulatory */
879 if (!ath_is_world_regd(reg)) {
880 error = regulatory_hint(hw->wiphy, reg->alpha2);
881 if (error)
882 goto unregister;
883 }
884
885 ath_init_leds(sc);
886 ath_start_rfkill_poll(sc);
887
888 return 0;
889
890 unregister:
891 ieee80211_unregister_hw(hw);
892 rx_cleanup:
893 ath_rx_cleanup(sc);
894 deinit:
895 ath9k_deinit_softc(sc);
896 return error;
897 }
898
899 /*****************************/
900 /* De-Initialization */
901 /*****************************/
902
903 static void ath9k_deinit_softc(struct ath_softc *sc)
904 {
905 int i = 0;
906
907 ath9k_deinit_btcoex(sc);
908
909 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
910 if (ATH_TXQ_SETUP(sc, i))
911 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
912
913 ath9k_hw_deinit(sc->sc_ah);
914 if (sc->dfs_detector != NULL)
915 sc->dfs_detector->exit(sc->dfs_detector);
916
917 ath9k_eeprom_release(sc);
918 }
919
920 void ath9k_deinit_device(struct ath_softc *sc)
921 {
922 struct ieee80211_hw *hw = sc->hw;
923
924 ath9k_ps_wakeup(sc);
925
926 wiphy_rfkill_stop_polling(sc->hw->wiphy);
927 ath_deinit_leds(sc);
928
929 ath9k_ps_restore(sc);
930
931 ieee80211_unregister_hw(hw);
932 ath_rx_cleanup(sc);
933 ath9k_deinit_softc(sc);
934 }
935
936 /************************/
937 /* Module Hooks */
938 /************************/
939
940 static int __init ath9k_init(void)
941 {
942 int error;
943
944 /* Register rate control algorithm */
945 error = ath_rate_control_register();
946 if (error != 0) {
947 pr_err("Unable to register rate control algorithm: %d\n",
948 error);
949 goto err_out;
950 }
951
952 error = ath_pci_init();
953 if (error < 0) {
954 pr_err("No PCI devices found, driver not installed\n");
955 error = -ENODEV;
956 goto err_rate_unregister;
957 }
958
959 error = ath_ahb_init();
960 if (error < 0) {
961 error = -ENODEV;
962 goto err_pci_exit;
963 }
964
965 return 0;
966
967 err_pci_exit:
968 ath_pci_exit();
969
970 err_rate_unregister:
971 ath_rate_control_unregister();
972 err_out:
973 return error;
974 }
975 module_init(ath9k_init);
976
977 static void __exit ath9k_exit(void)
978 {
979 is_ath9k_unloaded = true;
980 ath_ahb_exit();
981 ath_pci_exit();
982 ath_rate_control_unregister();
983 pr_info("%s: Driver unloaded\n", dev_info);
984 }
985 module_exit(ath9k_exit);
Linux kernel - Deliverables
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