2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19 #include <linux/dma-mapping.h>
20 #include <linux/slab.h>
21 #include <linux/ath9k_platform.h>
22 #include <linux/module.h>
26 static char *dev_info
= "ath9k";
28 MODULE_AUTHOR("Atheros Communications");
29 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
30 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
31 MODULE_LICENSE("Dual BSD/GPL");
33 static unsigned int ath9k_debug
= ATH_DBG_DEFAULT
;
34 module_param_named(debug
, ath9k_debug
, uint
, 0);
35 MODULE_PARM_DESC(debug
, "Debugging mask");
37 int ath9k_modparam_nohwcrypt
;
38 module_param_named(nohwcrypt
, ath9k_modparam_nohwcrypt
, int, 0444);
39 MODULE_PARM_DESC(nohwcrypt
, "Disable hardware encryption");
42 module_param_named(blink
, led_blink
, int, 0444);
43 MODULE_PARM_DESC(blink
, "Enable LED blink on activity");
45 static int ath9k_btcoex_enable
;
46 module_param_named(btcoex_enable
, ath9k_btcoex_enable
, int, 0444);
47 MODULE_PARM_DESC(btcoex_enable
, "Enable wifi-BT coexistence");
49 bool is_ath9k_unloaded
;
50 /* We use the hw_value as an index into our private channel structure */
52 #define CHAN2G(_freq, _idx) { \
53 .band = IEEE80211_BAND_2GHZ, \
54 .center_freq = (_freq), \
59 #define CHAN5G(_freq, _idx) { \
60 .band = IEEE80211_BAND_5GHZ, \
61 .center_freq = (_freq), \
66 /* Some 2 GHz radios are actually tunable on 2312-2732
67 * on 5 MHz steps, we support the channels which we know
68 * we have calibration data for all cards though to make
70 static const struct ieee80211_channel ath9k_2ghz_chantable
[] = {
71 CHAN2G(2412, 0), /* Channel 1 */
72 CHAN2G(2417, 1), /* Channel 2 */
73 CHAN2G(2422, 2), /* Channel 3 */
74 CHAN2G(2427, 3), /* Channel 4 */
75 CHAN2G(2432, 4), /* Channel 5 */
76 CHAN2G(2437, 5), /* Channel 6 */
77 CHAN2G(2442, 6), /* Channel 7 */
78 CHAN2G(2447, 7), /* Channel 8 */
79 CHAN2G(2452, 8), /* Channel 9 */
80 CHAN2G(2457, 9), /* Channel 10 */
81 CHAN2G(2462, 10), /* Channel 11 */
82 CHAN2G(2467, 11), /* Channel 12 */
83 CHAN2G(2472, 12), /* Channel 13 */
84 CHAN2G(2484, 13), /* Channel 14 */
87 /* Some 5 GHz radios are actually tunable on XXXX-YYYY
88 * on 5 MHz steps, we support the channels which we know
89 * we have calibration data for all cards though to make
91 static const struct ieee80211_channel ath9k_5ghz_chantable
[] = {
92 /* _We_ call this UNII 1 */
93 CHAN5G(5180, 14), /* Channel 36 */
94 CHAN5G(5200, 15), /* Channel 40 */
95 CHAN5G(5220, 16), /* Channel 44 */
96 CHAN5G(5240, 17), /* Channel 48 */
97 /* _We_ call this UNII 2 */
98 CHAN5G(5260, 18), /* Channel 52 */
99 CHAN5G(5280, 19), /* Channel 56 */
100 CHAN5G(5300, 20), /* Channel 60 */
101 CHAN5G(5320, 21), /* Channel 64 */
102 /* _We_ call this "Middle band" */
103 CHAN5G(5500, 22), /* Channel 100 */
104 CHAN5G(5520, 23), /* Channel 104 */
105 CHAN5G(5540, 24), /* Channel 108 */
106 CHAN5G(5560, 25), /* Channel 112 */
107 CHAN5G(5580, 26), /* Channel 116 */
108 CHAN5G(5600, 27), /* Channel 120 */
109 CHAN5G(5620, 28), /* Channel 124 */
110 CHAN5G(5640, 29), /* Channel 128 */
111 CHAN5G(5660, 30), /* Channel 132 */
112 CHAN5G(5680, 31), /* Channel 136 */
113 CHAN5G(5700, 32), /* Channel 140 */
114 /* _We_ call this UNII 3 */
115 CHAN5G(5745, 33), /* Channel 149 */
116 CHAN5G(5765, 34), /* Channel 153 */
117 CHAN5G(5785, 35), /* Channel 157 */
118 CHAN5G(5805, 36), /* Channel 161 */
119 CHAN5G(5825, 37), /* Channel 165 */
122 /* Atheros hardware rate code addition for short premble */
123 #define SHPCHECK(__hw_rate, __flags) \
124 ((__flags & IEEE80211_RATE_SHORT_PREAMBLE) ? (__hw_rate | 0x04 ) : 0)
126 #define RATE(_bitrate, _hw_rate, _flags) { \
127 .bitrate = (_bitrate), \
129 .hw_value = (_hw_rate), \
130 .hw_value_short = (SHPCHECK(_hw_rate, _flags)) \
133 static struct ieee80211_rate ath9k_legacy_rates
[] = {
135 RATE(20, 0x1a, IEEE80211_RATE_SHORT_PREAMBLE
),
136 RATE(55, 0x19, IEEE80211_RATE_SHORT_PREAMBLE
),
137 RATE(110, 0x18, IEEE80211_RATE_SHORT_PREAMBLE
),
148 #ifdef CONFIG_MAC80211_LEDS
149 static const struct ieee80211_tpt_blink ath9k_tpt_blink
[] = {
150 { .throughput
= 0 * 1024, .blink_time
= 334 },
151 { .throughput
= 1 * 1024, .blink_time
= 260 },
152 { .throughput
= 5 * 1024, .blink_time
= 220 },
153 { .throughput
= 10 * 1024, .blink_time
= 190 },
154 { .throughput
= 20 * 1024, .blink_time
= 170 },
155 { .throughput
= 50 * 1024, .blink_time
= 150 },
156 { .throughput
= 70 * 1024, .blink_time
= 130 },
157 { .throughput
= 100 * 1024, .blink_time
= 110 },
158 { .throughput
= 200 * 1024, .blink_time
= 80 },
159 { .throughput
= 300 * 1024, .blink_time
= 50 },
163 static void ath9k_deinit_softc(struct ath_softc
*sc
);
166 * Read and write, they both share the same lock. We do this to serialize
167 * reads and writes on Atheros 802.11n PCI devices only. This is required
168 * as the FIFO on these devices can only accept sanely 2 requests.
171 static void ath9k_iowrite32(void *hw_priv
, u32 val
, u32 reg_offset
)
173 struct ath_hw
*ah
= (struct ath_hw
*) hw_priv
;
174 struct ath_common
*common
= ath9k_hw_common(ah
);
175 struct ath_softc
*sc
= (struct ath_softc
*) common
->priv
;
177 if (NR_CPUS
> 1 && ah
->config
.serialize_regmode
== SER_REG_MODE_ON
) {
179 spin_lock_irqsave(&sc
->sc_serial_rw
, flags
);
180 iowrite32(val
, sc
->mem
+ reg_offset
);
181 spin_unlock_irqrestore(&sc
->sc_serial_rw
, flags
);
183 iowrite32(val
, sc
->mem
+ reg_offset
);
186 static unsigned int ath9k_ioread32(void *hw_priv
, u32 reg_offset
)
188 struct ath_hw
*ah
= (struct ath_hw
*) hw_priv
;
189 struct ath_common
*common
= ath9k_hw_common(ah
);
190 struct ath_softc
*sc
= (struct ath_softc
*) common
->priv
;
193 if (NR_CPUS
> 1 && ah
->config
.serialize_regmode
== SER_REG_MODE_ON
) {
195 spin_lock_irqsave(&sc
->sc_serial_rw
, flags
);
196 val
= ioread32(sc
->mem
+ reg_offset
);
197 spin_unlock_irqrestore(&sc
->sc_serial_rw
, flags
);
199 val
= ioread32(sc
->mem
+ reg_offset
);
203 static unsigned int __ath9k_reg_rmw(struct ath_softc
*sc
, u32 reg_offset
,
208 val
= ioread32(sc
->mem
+ reg_offset
);
211 iowrite32(val
, sc
->mem
+ reg_offset
);
216 static unsigned int ath9k_reg_rmw(void *hw_priv
, u32 reg_offset
, u32 set
, u32 clr
)
218 struct ath_hw
*ah
= (struct ath_hw
*) hw_priv
;
219 struct ath_common
*common
= ath9k_hw_common(ah
);
220 struct ath_softc
*sc
= (struct ath_softc
*) common
->priv
;
221 unsigned long uninitialized_var(flags
);
224 if (NR_CPUS
> 1 && ah
->config
.serialize_regmode
== SER_REG_MODE_ON
) {
225 spin_lock_irqsave(&sc
->sc_serial_rw
, flags
);
226 val
= __ath9k_reg_rmw(sc
, reg_offset
, set
, clr
);
227 spin_unlock_irqrestore(&sc
->sc_serial_rw
, flags
);
229 val
= __ath9k_reg_rmw(sc
, reg_offset
, set
, clr
);
234 /**************************/
236 /**************************/
238 static void setup_ht_cap(struct ath_softc
*sc
,
239 struct ieee80211_sta_ht_cap
*ht_info
)
241 struct ath_hw
*ah
= sc
->sc_ah
;
242 struct ath_common
*common
= ath9k_hw_common(ah
);
243 u8 tx_streams
, rx_streams
;
246 ht_info
->ht_supported
= true;
247 ht_info
->cap
= IEEE80211_HT_CAP_SUP_WIDTH_20_40
|
248 IEEE80211_HT_CAP_SM_PS
|
249 IEEE80211_HT_CAP_SGI_40
|
250 IEEE80211_HT_CAP_DSSSCCK40
;
252 if (sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_LDPC
)
253 ht_info
->cap
|= IEEE80211_HT_CAP_LDPC_CODING
;
255 if (sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_SGI_20
)
256 ht_info
->cap
|= IEEE80211_HT_CAP_SGI_20
;
258 ht_info
->ampdu_factor
= IEEE80211_HT_MAX_AMPDU_64K
;
259 ht_info
->ampdu_density
= IEEE80211_HT_MPDU_DENSITY_8
;
261 if (AR_SREV_9330(ah
) || AR_SREV_9485(ah
))
263 else if (AR_SREV_9462(ah
))
265 else if (AR_SREV_9300_20_OR_LATER(ah
))
270 if (AR_SREV_9280_20_OR_LATER(ah
)) {
271 if (max_streams
>= 2)
272 ht_info
->cap
|= IEEE80211_HT_CAP_TX_STBC
;
273 ht_info
->cap
|= (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT
);
276 /* set up supported mcs set */
277 memset(&ht_info
->mcs
, 0, sizeof(ht_info
->mcs
));
278 tx_streams
= ath9k_cmn_count_streams(ah
->txchainmask
, max_streams
);
279 rx_streams
= ath9k_cmn_count_streams(ah
->rxchainmask
, max_streams
);
281 ath_dbg(common
, CONFIG
, "TX streams %d, RX streams: %d\n",
282 tx_streams
, rx_streams
);
284 if (tx_streams
!= rx_streams
) {
285 ht_info
->mcs
.tx_params
|= IEEE80211_HT_MCS_TX_RX_DIFF
;
286 ht_info
->mcs
.tx_params
|= ((tx_streams
- 1) <<
287 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT
);
290 for (i
= 0; i
< rx_streams
; i
++)
291 ht_info
->mcs
.rx_mask
[i
] = 0xff;
293 ht_info
->mcs
.tx_params
|= IEEE80211_HT_MCS_TX_DEFINED
;
296 static int ath9k_reg_notifier(struct wiphy
*wiphy
,
297 struct regulatory_request
*request
)
299 struct ieee80211_hw
*hw
= wiphy_to_ieee80211_hw(wiphy
);
300 struct ath_softc
*sc
= hw
->priv
;
301 struct ath_hw
*ah
= sc
->sc_ah
;
302 struct ath_regulatory
*reg
= ath9k_hw_regulatory(ah
);
305 ret
= ath_reg_notifier_apply(wiphy
, request
, reg
);
309 sc
->config
.txpowlimit
= 2 * ah
->curchan
->chan
->max_power
;
311 ath9k_hw_set_txpowerlimit(ah
, sc
->config
.txpowlimit
, false);
312 sc
->curtxpow
= ath9k_hw_regulatory(ah
)->power_limit
;
313 ath9k_ps_restore(sc
);
320 * This function will allocate both the DMA descriptor structure, and the
321 * buffers it contains. These are used to contain the descriptors used
324 int ath_descdma_setup(struct ath_softc
*sc
, struct ath_descdma
*dd
,
325 struct list_head
*head
, const char *name
,
326 int nbuf
, int ndesc
, bool is_tx
)
328 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
331 int i
, bsize
, error
, desc_len
;
333 ath_dbg(common
, CONFIG
, "%s DMA: %u buffers %u desc/buf\n",
336 INIT_LIST_HEAD(head
);
339 desc_len
= sc
->sc_ah
->caps
.tx_desc_len
;
341 desc_len
= sizeof(struct ath_desc
);
343 /* ath_desc must be a multiple of DWORDs */
344 if ((desc_len
% 4) != 0) {
345 ath_err(common
, "ath_desc not DWORD aligned\n");
346 BUG_ON((desc_len
% 4) != 0);
351 dd
->dd_desc_len
= desc_len
* nbuf
* ndesc
;
354 * Need additional DMA memory because we can't use
355 * descriptors that cross the 4K page boundary. Assume
356 * one skipped descriptor per 4K page.
358 if (!(sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_4KB_SPLITTRANS
)) {
360 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd
->dd_desc_len
);
363 while (ndesc_skipped
) {
364 dma_len
= ndesc_skipped
* desc_len
;
365 dd
->dd_desc_len
+= dma_len
;
367 ndesc_skipped
= ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len
);
371 /* allocate descriptors */
372 dd
->dd_desc
= dma_alloc_coherent(sc
->dev
, dd
->dd_desc_len
,
373 &dd
->dd_desc_paddr
, GFP_KERNEL
);
374 if (dd
->dd_desc
== NULL
) {
378 ds
= (u8
*) dd
->dd_desc
;
379 ath_dbg(common
, CONFIG
, "%s DMA map: %p (%u) -> %llx (%u)\n",
380 name
, ds
, (u32
) dd
->dd_desc_len
,
381 ito64(dd
->dd_desc_paddr
), /*XXX*/(u32
) dd
->dd_desc_len
);
383 /* allocate buffers */
384 bsize
= sizeof(struct ath_buf
) * nbuf
;
385 bf
= kzalloc(bsize
, GFP_KERNEL
);
392 for (i
= 0; i
< nbuf
; i
++, bf
++, ds
+= (desc_len
* ndesc
)) {
394 bf
->bf_daddr
= DS2PHYS(dd
, ds
);
396 if (!(sc
->sc_ah
->caps
.hw_caps
&
397 ATH9K_HW_CAP_4KB_SPLITTRANS
)) {
399 * Skip descriptor addresses which can cause 4KB
400 * boundary crossing (addr + length) with a 32 dword
403 while (ATH_DESC_4KB_BOUND_CHECK(bf
->bf_daddr
)) {
404 BUG_ON((caddr_t
) bf
->bf_desc
>=
405 ((caddr_t
) dd
->dd_desc
+
408 ds
+= (desc_len
* ndesc
);
410 bf
->bf_daddr
= DS2PHYS(dd
, ds
);
413 list_add_tail(&bf
->list
, head
);
417 dma_free_coherent(sc
->dev
, dd
->dd_desc_len
, dd
->dd_desc
,
420 memset(dd
, 0, sizeof(*dd
));
424 static int ath9k_init_queues(struct ath_softc
*sc
)
428 sc
->beacon
.beaconq
= ath9k_hw_beaconq_setup(sc
->sc_ah
);
429 sc
->beacon
.cabq
= ath_txq_setup(sc
, ATH9K_TX_QUEUE_CAB
, 0);
431 sc
->config
.cabqReadytime
= ATH_CABQ_READY_TIME
;
434 for (i
= 0; i
< WME_NUM_AC
; i
++) {
435 sc
->tx
.txq_map
[i
] = ath_txq_setup(sc
, ATH9K_TX_QUEUE_DATA
, i
);
436 sc
->tx
.txq_map
[i
]->mac80211_qnum
= i
;
437 sc
->tx
.txq_max_pending
[i
] = ATH_MAX_QDEPTH
;
442 static int ath9k_init_channels_rates(struct ath_softc
*sc
)
446 BUILD_BUG_ON(ARRAY_SIZE(ath9k_2ghz_chantable
) +
447 ARRAY_SIZE(ath9k_5ghz_chantable
) !=
450 if (sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_2GHZ
) {
451 channels
= kmemdup(ath9k_2ghz_chantable
,
452 sizeof(ath9k_2ghz_chantable
), GFP_KERNEL
);
456 sc
->sbands
[IEEE80211_BAND_2GHZ
].channels
= channels
;
457 sc
->sbands
[IEEE80211_BAND_2GHZ
].band
= IEEE80211_BAND_2GHZ
;
458 sc
->sbands
[IEEE80211_BAND_2GHZ
].n_channels
=
459 ARRAY_SIZE(ath9k_2ghz_chantable
);
460 sc
->sbands
[IEEE80211_BAND_2GHZ
].bitrates
= ath9k_legacy_rates
;
461 sc
->sbands
[IEEE80211_BAND_2GHZ
].n_bitrates
=
462 ARRAY_SIZE(ath9k_legacy_rates
);
465 if (sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_5GHZ
) {
466 channels
= kmemdup(ath9k_5ghz_chantable
,
467 sizeof(ath9k_5ghz_chantable
), GFP_KERNEL
);
469 if (sc
->sbands
[IEEE80211_BAND_2GHZ
].channels
)
470 kfree(sc
->sbands
[IEEE80211_BAND_2GHZ
].channels
);
474 sc
->sbands
[IEEE80211_BAND_5GHZ
].channels
= channels
;
475 sc
->sbands
[IEEE80211_BAND_5GHZ
].band
= IEEE80211_BAND_5GHZ
;
476 sc
->sbands
[IEEE80211_BAND_5GHZ
].n_channels
=
477 ARRAY_SIZE(ath9k_5ghz_chantable
);
478 sc
->sbands
[IEEE80211_BAND_5GHZ
].bitrates
=
479 ath9k_legacy_rates
+ 4;
480 sc
->sbands
[IEEE80211_BAND_5GHZ
].n_bitrates
=
481 ARRAY_SIZE(ath9k_legacy_rates
) - 4;
486 static void ath9k_init_misc(struct ath_softc
*sc
)
488 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
491 setup_timer(&common
->ani
.timer
, ath_ani_calibrate
, (unsigned long)sc
);
493 sc
->last_rssi
= ATH_RSSI_DUMMY_MARKER
;
494 sc
->config
.txpowlimit
= ATH_TXPOWER_MAX
;
495 memcpy(common
->bssidmask
, ath_bcast_mac
, ETH_ALEN
);
496 sc
->beacon
.slottime
= ATH9K_SLOT_TIME_9
;
498 for (i
= 0; i
< ARRAY_SIZE(sc
->beacon
.bslot
); i
++)
499 sc
->beacon
.bslot
[i
] = NULL
;
501 if (sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_ANT_DIV_COMB
)
502 sc
->ant_comb
.count
= ATH_ANT_DIV_COMB_INIT_COUNT
;
505 static int ath9k_init_softc(u16 devid
, struct ath_softc
*sc
,
506 const struct ath_bus_ops
*bus_ops
)
508 struct ath9k_platform_data
*pdata
= sc
->dev
->platform_data
;
509 struct ath_hw
*ah
= NULL
;
510 struct ath_common
*common
;
514 ah
= kzalloc(sizeof(struct ath_hw
), GFP_KERNEL
);
519 ah
->hw_version
.devid
= devid
;
520 ah
->reg_ops
.read
= ath9k_ioread32
;
521 ah
->reg_ops
.write
= ath9k_iowrite32
;
522 ah
->reg_ops
.rmw
= ath9k_reg_rmw
;
523 atomic_set(&ah
->intr_ref_cnt
, -1);
526 sc
->dfs_detector
= dfs_pattern_detector_init(NL80211_DFS_UNSET
);
529 ah
->ah_flags
|= AH_USE_EEPROM
;
530 sc
->sc_ah
->led_pin
= -1;
532 sc
->sc_ah
->gpio_mask
= pdata
->gpio_mask
;
533 sc
->sc_ah
->gpio_val
= pdata
->gpio_val
;
534 sc
->sc_ah
->led_pin
= pdata
->led_pin
;
535 ah
->is_clk_25mhz
= pdata
->is_clk_25mhz
;
536 ah
->get_mac_revision
= pdata
->get_mac_revision
;
537 ah
->external_reset
= pdata
->external_reset
;
540 common
= ath9k_hw_common(ah
);
541 common
->ops
= &ah
->reg_ops
;
542 common
->bus_ops
= bus_ops
;
546 common
->debug_mask
= ath9k_debug
;
547 common
->btcoex_enabled
= ath9k_btcoex_enable
== 1;
548 common
->disable_ani
= false;
549 spin_lock_init(&common
->cc_lock
);
551 spin_lock_init(&sc
->sc_serial_rw
);
552 spin_lock_init(&sc
->sc_pm_lock
);
553 mutex_init(&sc
->mutex
);
554 #ifdef CONFIG_ATH9K_DEBUGFS
555 spin_lock_init(&sc
->nodes_lock
);
556 INIT_LIST_HEAD(&sc
->nodes
);
558 #ifdef CONFIG_ATH9K_MAC_DEBUG
559 spin_lock_init(&sc
->debug
.samp_lock
);
561 tasklet_init(&sc
->intr_tq
, ath9k_tasklet
, (unsigned long)sc
);
562 tasklet_init(&sc
->bcon_tasklet
, ath_beacon_tasklet
,
565 INIT_WORK(&sc
->hw_reset_work
, ath_reset_work
);
566 INIT_WORK(&sc
->hw_check_work
, ath_hw_check
);
567 INIT_WORK(&sc
->paprd_work
, ath_paprd_calibrate
);
568 INIT_DELAYED_WORK(&sc
->hw_pll_work
, ath_hw_pll_work
);
569 setup_timer(&sc
->rx_poll_timer
, ath_rx_poll
, (unsigned long)sc
);
572 * Cache line size is used to size and align various
573 * structures used to communicate with the hardware.
575 ath_read_cachesize(common
, &csz
);
576 common
->cachelsz
= csz
<< 2; /* convert to bytes */
578 /* Initializes the hardware for all supported chipsets */
579 ret
= ath9k_hw_init(ah
);
583 if (pdata
&& pdata
->macaddr
)
584 memcpy(common
->macaddr
, pdata
->macaddr
, ETH_ALEN
);
586 ret
= ath9k_init_queues(sc
);
590 ret
= ath9k_init_btcoex(sc
);
594 ret
= ath9k_init_channels_rates(sc
);
598 ath9k_cmn_init_crypto(sc
->sc_ah
);
601 if (common
->bus_ops
->aspm_init
)
602 common
->bus_ops
->aspm_init(common
);
607 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++)
608 if (ATH_TXQ_SETUP(sc
, i
))
609 ath_tx_cleanupq(sc
, &sc
->tx
.txq
[i
]);
620 static void ath9k_init_band_txpower(struct ath_softc
*sc
, int band
)
622 struct ieee80211_supported_band
*sband
;
623 struct ieee80211_channel
*chan
;
624 struct ath_hw
*ah
= sc
->sc_ah
;
627 sband
= &sc
->sbands
[band
];
628 for (i
= 0; i
< sband
->n_channels
; i
++) {
629 chan
= &sband
->channels
[i
];
630 ah
->curchan
= &ah
->channels
[chan
->hw_value
];
631 ath9k_cmn_update_ichannel(ah
->curchan
, chan
, NL80211_CHAN_HT20
);
632 ath9k_hw_set_txpowerlimit(ah
, MAX_RATE_POWER
, true);
636 static void ath9k_init_txpower_limits(struct ath_softc
*sc
)
638 struct ath_hw
*ah
= sc
->sc_ah
;
639 struct ath9k_channel
*curchan
= ah
->curchan
;
641 if (ah
->caps
.hw_caps
& ATH9K_HW_CAP_2GHZ
)
642 ath9k_init_band_txpower(sc
, IEEE80211_BAND_2GHZ
);
643 if (ah
->caps
.hw_caps
& ATH9K_HW_CAP_5GHZ
)
644 ath9k_init_band_txpower(sc
, IEEE80211_BAND_5GHZ
);
646 ah
->curchan
= curchan
;
649 void ath9k_reload_chainmask_settings(struct ath_softc
*sc
)
651 if (!(sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_HT
))
654 if (sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_2GHZ
)
655 setup_ht_cap(sc
, &sc
->sbands
[IEEE80211_BAND_2GHZ
].ht_cap
);
656 if (sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_5GHZ
)
657 setup_ht_cap(sc
, &sc
->sbands
[IEEE80211_BAND_5GHZ
].ht_cap
);
660 static const struct ieee80211_iface_limit if_limits
[] = {
661 { .max
= 2048, .types
= BIT(NL80211_IFTYPE_STATION
) |
662 BIT(NL80211_IFTYPE_P2P_CLIENT
) |
663 BIT(NL80211_IFTYPE_WDS
) },
665 #ifdef CONFIG_MAC80211_MESH
666 BIT(NL80211_IFTYPE_MESH_POINT
) |
668 BIT(NL80211_IFTYPE_AP
) |
669 BIT(NL80211_IFTYPE_P2P_GO
) },
672 static const struct ieee80211_iface_combination if_comb
= {
674 .n_limits
= ARRAY_SIZE(if_limits
),
675 .max_interfaces
= 2048,
676 .num_different_channels
= 1,
679 void ath9k_set_hw_capab(struct ath_softc
*sc
, struct ieee80211_hw
*hw
)
681 struct ath_hw
*ah
= sc
->sc_ah
;
682 struct ath_common
*common
= ath9k_hw_common(ah
);
684 hw
->flags
= IEEE80211_HW_RX_INCLUDES_FCS
|
685 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING
|
686 IEEE80211_HW_SIGNAL_DBM
|
687 IEEE80211_HW_SUPPORTS_PS
|
688 IEEE80211_HW_PS_NULLFUNC_STACK
|
689 IEEE80211_HW_SPECTRUM_MGMT
|
690 IEEE80211_HW_REPORTS_TX_ACK_STATUS
;
692 if (sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_HT
)
693 hw
->flags
|= IEEE80211_HW_AMPDU_AGGREGATION
;
695 if (AR_SREV_9160_10_OR_LATER(sc
->sc_ah
) || ath9k_modparam_nohwcrypt
)
696 hw
->flags
|= IEEE80211_HW_MFP_CAPABLE
;
698 hw
->wiphy
->interface_modes
=
699 BIT(NL80211_IFTYPE_P2P_GO
) |
700 BIT(NL80211_IFTYPE_P2P_CLIENT
) |
701 BIT(NL80211_IFTYPE_AP
) |
702 BIT(NL80211_IFTYPE_WDS
) |
703 BIT(NL80211_IFTYPE_STATION
) |
704 BIT(NL80211_IFTYPE_ADHOC
) |
705 BIT(NL80211_IFTYPE_MESH_POINT
);
707 hw
->wiphy
->iface_combinations
= &if_comb
;
708 hw
->wiphy
->n_iface_combinations
= 1;
710 if (AR_SREV_5416(sc
->sc_ah
))
711 hw
->wiphy
->flags
&= ~WIPHY_FLAG_PS_ON_BY_DEFAULT
;
713 hw
->wiphy
->flags
|= WIPHY_FLAG_IBSS_RSN
;
714 hw
->wiphy
->flags
|= WIPHY_FLAG_SUPPORTS_TDLS
;
715 hw
->wiphy
->flags
|= WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL
;
717 #ifdef CONFIG_PM_SLEEP
719 if ((ah
->caps
.hw_caps
& ATH9K_HW_WOW_DEVICE_CAPABLE
) &&
720 device_can_wakeup(sc
->dev
)) {
722 hw
->wiphy
->wowlan
.flags
= WIPHY_WOWLAN_MAGIC_PKT
|
723 WIPHY_WOWLAN_DISCONNECT
;
724 hw
->wiphy
->wowlan
.n_patterns
= MAX_NUM_USER_PATTERN
;
725 hw
->wiphy
->wowlan
.pattern_min_len
= 1;
726 hw
->wiphy
->wowlan
.pattern_max_len
= MAX_PATTERN_SIZE
;
730 atomic_set(&sc
->wow_sleep_proc_intr
, -1);
731 atomic_set(&sc
->wow_got_bmiss_intr
, -1);
737 hw
->channel_change_time
= 5000;
738 hw
->max_listen_interval
= 1;
739 hw
->max_rate_tries
= 10;
740 hw
->sta_data_size
= sizeof(struct ath_node
);
741 hw
->vif_data_size
= sizeof(struct ath_vif
);
743 hw
->wiphy
->available_antennas_rx
= BIT(ah
->caps
.max_rxchains
) - 1;
744 hw
->wiphy
->available_antennas_tx
= BIT(ah
->caps
.max_txchains
) - 1;
746 /* single chain devices with rx diversity */
747 if (ah
->caps
.hw_caps
& ATH9K_HW_CAP_ANT_DIV_COMB
)
748 hw
->wiphy
->available_antennas_rx
= BIT(0) | BIT(1);
750 sc
->ant_rx
= hw
->wiphy
->available_antennas_rx
;
751 sc
->ant_tx
= hw
->wiphy
->available_antennas_tx
;
753 #ifdef CONFIG_ATH9K_RATE_CONTROL
754 hw
->rate_control_algorithm
= "ath9k_rate_control";
757 if (sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_2GHZ
)
758 hw
->wiphy
->bands
[IEEE80211_BAND_2GHZ
] =
759 &sc
->sbands
[IEEE80211_BAND_2GHZ
];
760 if (sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_5GHZ
)
761 hw
->wiphy
->bands
[IEEE80211_BAND_5GHZ
] =
762 &sc
->sbands
[IEEE80211_BAND_5GHZ
];
764 ath9k_reload_chainmask_settings(sc
);
766 SET_IEEE80211_PERM_ADDR(hw
, common
->macaddr
);
769 int ath9k_init_device(u16 devid
, struct ath_softc
*sc
,
770 const struct ath_bus_ops
*bus_ops
)
772 struct ieee80211_hw
*hw
= sc
->hw
;
773 struct ath_common
*common
;
776 struct ath_regulatory
*reg
;
778 /* Bring up device */
779 error
= ath9k_init_softc(devid
, sc
, bus_ops
);
784 common
= ath9k_hw_common(ah
);
785 ath9k_set_hw_capab(sc
, hw
);
787 /* Initialize regulatory */
788 error
= ath_regd_init(&common
->regulatory
, sc
->hw
->wiphy
,
793 reg
= &common
->regulatory
;
796 error
= ath_tx_init(sc
, ATH_TXBUF
);
801 error
= ath_rx_init(sc
, ATH_RXBUF
);
805 ath9k_init_txpower_limits(sc
);
807 #ifdef CONFIG_MAC80211_LEDS
808 /* must be initialized before ieee80211_register_hw */
809 sc
->led_cdev
.default_trigger
= ieee80211_create_tpt_led_trigger(sc
->hw
,
810 IEEE80211_TPT_LEDTRIG_FL_RADIO
, ath9k_tpt_blink
,
811 ARRAY_SIZE(ath9k_tpt_blink
));
814 /* Register with mac80211 */
815 error
= ieee80211_register_hw(hw
);
819 error
= ath9k_init_debug(ah
);
821 ath_err(common
, "Unable to create debugfs files\n");
825 /* Handle world regulatory */
826 if (!ath_is_world_regd(reg
)) {
827 error
= regulatory_hint(hw
->wiphy
, reg
->alpha2
);
833 ath_start_rfkill_poll(sc
);
838 ieee80211_unregister_hw(hw
);
846 ath9k_deinit_softc(sc
);
851 /*****************************/
852 /* De-Initialization */
853 /*****************************/
855 static void ath9k_deinit_softc(struct ath_softc
*sc
)
859 if (sc
->sbands
[IEEE80211_BAND_2GHZ
].channels
)
860 kfree(sc
->sbands
[IEEE80211_BAND_2GHZ
].channels
);
862 if (sc
->sbands
[IEEE80211_BAND_5GHZ
].channels
)
863 kfree(sc
->sbands
[IEEE80211_BAND_5GHZ
].channels
);
865 ath9k_deinit_btcoex(sc
);
867 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++)
868 if (ATH_TXQ_SETUP(sc
, i
))
869 ath_tx_cleanupq(sc
, &sc
->tx
.txq
[i
]);
871 ath9k_hw_deinit(sc
->sc_ah
);
872 if (sc
->dfs_detector
!= NULL
)
873 sc
->dfs_detector
->exit(sc
->dfs_detector
);
879 void ath9k_deinit_device(struct ath_softc
*sc
)
881 struct ieee80211_hw
*hw
= sc
->hw
;
885 wiphy_rfkill_stop_polling(sc
->hw
->wiphy
);
888 ath9k_ps_restore(sc
);
890 ieee80211_unregister_hw(hw
);
893 ath9k_deinit_softc(sc
);
896 void ath_descdma_cleanup(struct ath_softc
*sc
,
897 struct ath_descdma
*dd
,
898 struct list_head
*head
)
900 dma_free_coherent(sc
->dev
, dd
->dd_desc_len
, dd
->dd_desc
,
903 INIT_LIST_HEAD(head
);
904 kfree(dd
->dd_bufptr
);
905 memset(dd
, 0, sizeof(*dd
));
908 /************************/
910 /************************/
912 static int __init
ath9k_init(void)
916 /* Register rate control algorithm */
917 error
= ath_rate_control_register();
919 pr_err("Unable to register rate control algorithm: %d\n",
924 error
= ath_pci_init();
926 pr_err("No PCI devices found, driver not installed\n");
928 goto err_rate_unregister
;
931 error
= ath_ahb_init();
943 ath_rate_control_unregister();
947 module_init(ath9k_init
);
949 static void __exit
ath9k_exit(void)
951 is_ath9k_unloaded
= true;
954 ath_rate_control_unregister();
955 pr_info("%s: Driver unloaded\n", dev_info
);
957 module_exit(ath9k_exit
);