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Merge branch 'pm-cpufreq'
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / init.c
1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
18
19 #include <linux/dma-mapping.h>
20 #include <linux/slab.h>
21 #include <linux/ath9k_platform.h>
22 #include <linux/module.h>
23 #include <linux/relay.h>
24 #include <net/ieee80211_radiotap.h>
25
26 #include "ath9k.h"
27
28 struct ath9k_eeprom_ctx {
29 struct completion complete;
30 struct ath_hw *ah;
31 };
32
33 static char *dev_info = "ath9k";
34
35 MODULE_AUTHOR("Atheros Communications");
36 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
37 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
38 MODULE_LICENSE("Dual BSD/GPL");
39
40 static unsigned int ath9k_debug = ATH_DBG_DEFAULT;
41 module_param_named(debug, ath9k_debug, uint, 0);
42 MODULE_PARM_DESC(debug, "Debugging mask");
43
44 int ath9k_modparam_nohwcrypt;
45 module_param_named(nohwcrypt, ath9k_modparam_nohwcrypt, int, 0444);
46 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
47
48 int led_blink;
49 module_param_named(blink, led_blink, int, 0444);
50 MODULE_PARM_DESC(blink, "Enable LED blink on activity");
51
52 static int ath9k_btcoex_enable;
53 module_param_named(btcoex_enable, ath9k_btcoex_enable, int, 0444);
54 MODULE_PARM_DESC(btcoex_enable, "Enable wifi-BT coexistence");
55
56 static int ath9k_enable_diversity;
57 module_param_named(enable_diversity, ath9k_enable_diversity, int, 0444);
58 MODULE_PARM_DESC(enable_diversity, "Enable Antenna diversity for AR9565");
59
60 bool is_ath9k_unloaded;
61 /* We use the hw_value as an index into our private channel structure */
62
63 #define CHAN2G(_freq, _idx) { \
64 .band = IEEE80211_BAND_2GHZ, \
65 .center_freq = (_freq), \
66 .hw_value = (_idx), \
67 .max_power = 20, \
68 }
69
70 #define CHAN5G(_freq, _idx) { \
71 .band = IEEE80211_BAND_5GHZ, \
72 .center_freq = (_freq), \
73 .hw_value = (_idx), \
74 .max_power = 20, \
75 }
76
77 /* Some 2 GHz radios are actually tunable on 2312-2732
78 * on 5 MHz steps, we support the channels which we know
79 * we have calibration data for all cards though to make
80 * this static */
81 static const struct ieee80211_channel ath9k_2ghz_chantable[] = {
82 CHAN2G(2412, 0), /* Channel 1 */
83 CHAN2G(2417, 1), /* Channel 2 */
84 CHAN2G(2422, 2), /* Channel 3 */
85 CHAN2G(2427, 3), /* Channel 4 */
86 CHAN2G(2432, 4), /* Channel 5 */
87 CHAN2G(2437, 5), /* Channel 6 */
88 CHAN2G(2442, 6), /* Channel 7 */
89 CHAN2G(2447, 7), /* Channel 8 */
90 CHAN2G(2452, 8), /* Channel 9 */
91 CHAN2G(2457, 9), /* Channel 10 */
92 CHAN2G(2462, 10), /* Channel 11 */
93 CHAN2G(2467, 11), /* Channel 12 */
94 CHAN2G(2472, 12), /* Channel 13 */
95 CHAN2G(2484, 13), /* Channel 14 */
96 };
97
98 /* Some 5 GHz radios are actually tunable on XXXX-YYYY
99 * on 5 MHz steps, we support the channels which we know
100 * we have calibration data for all cards though to make
101 * this static */
102 static const struct ieee80211_channel ath9k_5ghz_chantable[] = {
103 /* _We_ call this UNII 1 */
104 CHAN5G(5180, 14), /* Channel 36 */
105 CHAN5G(5200, 15), /* Channel 40 */
106 CHAN5G(5220, 16), /* Channel 44 */
107 CHAN5G(5240, 17), /* Channel 48 */
108 /* _We_ call this UNII 2 */
109 CHAN5G(5260, 18), /* Channel 52 */
110 CHAN5G(5280, 19), /* Channel 56 */
111 CHAN5G(5300, 20), /* Channel 60 */
112 CHAN5G(5320, 21), /* Channel 64 */
113 /* _We_ call this "Middle band" */
114 CHAN5G(5500, 22), /* Channel 100 */
115 CHAN5G(5520, 23), /* Channel 104 */
116 CHAN5G(5540, 24), /* Channel 108 */
117 CHAN5G(5560, 25), /* Channel 112 */
118 CHAN5G(5580, 26), /* Channel 116 */
119 CHAN5G(5600, 27), /* Channel 120 */
120 CHAN5G(5620, 28), /* Channel 124 */
121 CHAN5G(5640, 29), /* Channel 128 */
122 CHAN5G(5660, 30), /* Channel 132 */
123 CHAN5G(5680, 31), /* Channel 136 */
124 CHAN5G(5700, 32), /* Channel 140 */
125 /* _We_ call this UNII 3 */
126 CHAN5G(5745, 33), /* Channel 149 */
127 CHAN5G(5765, 34), /* Channel 153 */
128 CHAN5G(5785, 35), /* Channel 157 */
129 CHAN5G(5805, 36), /* Channel 161 */
130 CHAN5G(5825, 37), /* Channel 165 */
131 };
132
133 /* Atheros hardware rate code addition for short premble */
134 #define SHPCHECK(__hw_rate, __flags) \
135 ((__flags & IEEE80211_RATE_SHORT_PREAMBLE) ? (__hw_rate | 0x04 ) : 0)
136
137 #define RATE(_bitrate, _hw_rate, _flags) { \
138 .bitrate = (_bitrate), \
139 .flags = (_flags), \
140 .hw_value = (_hw_rate), \
141 .hw_value_short = (SHPCHECK(_hw_rate, _flags)) \
142 }
143
144 static struct ieee80211_rate ath9k_legacy_rates[] = {
145 RATE(10, 0x1b, 0),
146 RATE(20, 0x1a, IEEE80211_RATE_SHORT_PREAMBLE),
147 RATE(55, 0x19, IEEE80211_RATE_SHORT_PREAMBLE),
148 RATE(110, 0x18, IEEE80211_RATE_SHORT_PREAMBLE),
149 RATE(60, 0x0b, 0),
150 RATE(90, 0x0f, 0),
151 RATE(120, 0x0a, 0),
152 RATE(180, 0x0e, 0),
153 RATE(240, 0x09, 0),
154 RATE(360, 0x0d, 0),
155 RATE(480, 0x08, 0),
156 RATE(540, 0x0c, 0),
157 };
158
159 #ifdef CONFIG_MAC80211_LEDS
160 static const struct ieee80211_tpt_blink ath9k_tpt_blink[] = {
161 { .throughput = 0 * 1024, .blink_time = 334 },
162 { .throughput = 1 * 1024, .blink_time = 260 },
163 { .throughput = 5 * 1024, .blink_time = 220 },
164 { .throughput = 10 * 1024, .blink_time = 190 },
165 { .throughput = 20 * 1024, .blink_time = 170 },
166 { .throughput = 50 * 1024, .blink_time = 150 },
167 { .throughput = 70 * 1024, .blink_time = 130 },
168 { .throughput = 100 * 1024, .blink_time = 110 },
169 { .throughput = 200 * 1024, .blink_time = 80 },
170 { .throughput = 300 * 1024, .blink_time = 50 },
171 };
172 #endif
173
174 static void ath9k_deinit_softc(struct ath_softc *sc);
175
176 /*
177 * Read and write, they both share the same lock. We do this to serialize
178 * reads and writes on Atheros 802.11n PCI devices only. This is required
179 * as the FIFO on these devices can only accept sanely 2 requests.
180 */
181
182 static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
183 {
184 struct ath_hw *ah = (struct ath_hw *) hw_priv;
185 struct ath_common *common = ath9k_hw_common(ah);
186 struct ath_softc *sc = (struct ath_softc *) common->priv;
187
188 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) {
189 unsigned long flags;
190 spin_lock_irqsave(&sc->sc_serial_rw, flags);
191 iowrite32(val, sc->mem + reg_offset);
192 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
193 } else
194 iowrite32(val, sc->mem + reg_offset);
195 }
196
197 static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset)
198 {
199 struct ath_hw *ah = (struct ath_hw *) hw_priv;
200 struct ath_common *common = ath9k_hw_common(ah);
201 struct ath_softc *sc = (struct ath_softc *) common->priv;
202 u32 val;
203
204 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) {
205 unsigned long flags;
206 spin_lock_irqsave(&sc->sc_serial_rw, flags);
207 val = ioread32(sc->mem + reg_offset);
208 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
209 } else
210 val = ioread32(sc->mem + reg_offset);
211 return val;
212 }
213
214 static unsigned int __ath9k_reg_rmw(struct ath_softc *sc, u32 reg_offset,
215 u32 set, u32 clr)
216 {
217 u32 val;
218
219 val = ioread32(sc->mem + reg_offset);
220 val &= ~clr;
221 val |= set;
222 iowrite32(val, sc->mem + reg_offset);
223
224 return val;
225 }
226
227 static unsigned int ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr)
228 {
229 struct ath_hw *ah = (struct ath_hw *) hw_priv;
230 struct ath_common *common = ath9k_hw_common(ah);
231 struct ath_softc *sc = (struct ath_softc *) common->priv;
232 unsigned long uninitialized_var(flags);
233 u32 val;
234
235 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) {
236 spin_lock_irqsave(&sc->sc_serial_rw, flags);
237 val = __ath9k_reg_rmw(sc, reg_offset, set, clr);
238 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
239 } else
240 val = __ath9k_reg_rmw(sc, reg_offset, set, clr);
241
242 return val;
243 }
244
245 /**************************/
246 /* Initialization */
247 /**************************/
248
249 static void setup_ht_cap(struct ath_softc *sc,
250 struct ieee80211_sta_ht_cap *ht_info)
251 {
252 struct ath_hw *ah = sc->sc_ah;
253 struct ath_common *common = ath9k_hw_common(ah);
254 u8 tx_streams, rx_streams;
255 int i, max_streams;
256
257 ht_info->ht_supported = true;
258 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
259 IEEE80211_HT_CAP_SM_PS |
260 IEEE80211_HT_CAP_SGI_40 |
261 IEEE80211_HT_CAP_DSSSCCK40;
262
263 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_LDPC)
264 ht_info->cap |= IEEE80211_HT_CAP_LDPC_CODING;
265
266 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_SGI_20)
267 ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
268
269 ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
270 ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
271
272 if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah))
273 max_streams = 1;
274 else if (AR_SREV_9462(ah))
275 max_streams = 2;
276 else if (AR_SREV_9300_20_OR_LATER(ah))
277 max_streams = 3;
278 else
279 max_streams = 2;
280
281 if (AR_SREV_9280_20_OR_LATER(ah)) {
282 if (max_streams >= 2)
283 ht_info->cap |= IEEE80211_HT_CAP_TX_STBC;
284 ht_info->cap |= (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT);
285 }
286
287 /* set up supported mcs set */
288 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
289 tx_streams = ath9k_cmn_count_streams(ah->txchainmask, max_streams);
290 rx_streams = ath9k_cmn_count_streams(ah->rxchainmask, max_streams);
291
292 ath_dbg(common, CONFIG, "TX streams %d, RX streams: %d\n",
293 tx_streams, rx_streams);
294
295 if (tx_streams != rx_streams) {
296 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
297 ht_info->mcs.tx_params |= ((tx_streams - 1) <<
298 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
299 }
300
301 for (i = 0; i < rx_streams; i++)
302 ht_info->mcs.rx_mask[i] = 0xff;
303
304 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
305 }
306
307 static void ath9k_reg_notifier(struct wiphy *wiphy,
308 struct regulatory_request *request)
309 {
310 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
311 struct ath_softc *sc = hw->priv;
312 struct ath_hw *ah = sc->sc_ah;
313 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
314
315 ath_reg_notifier_apply(wiphy, request, reg);
316
317 /* Set tx power */
318 if (ah->curchan) {
319 sc->config.txpowlimit = 2 * ah->curchan->chan->max_power;
320 ath9k_ps_wakeup(sc);
321 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit, false);
322 sc->curtxpow = ath9k_hw_regulatory(ah)->power_limit;
323 /* synchronize DFS detector if regulatory domain changed */
324 if (sc->dfs_detector != NULL)
325 sc->dfs_detector->set_dfs_domain(sc->dfs_detector,
326 request->dfs_region);
327 ath9k_ps_restore(sc);
328 }
329 }
330
331 /*
332 * This function will allocate both the DMA descriptor structure, and the
333 * buffers it contains. These are used to contain the descriptors used
334 * by the system.
335 */
336 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
337 struct list_head *head, const char *name,
338 int nbuf, int ndesc, bool is_tx)
339 {
340 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
341 u8 *ds;
342 struct ath_buf *bf;
343 int i, bsize, desc_len;
344
345 ath_dbg(common, CONFIG, "%s DMA: %u buffers %u desc/buf\n",
346 name, nbuf, ndesc);
347
348 INIT_LIST_HEAD(head);
349
350 if (is_tx)
351 desc_len = sc->sc_ah->caps.tx_desc_len;
352 else
353 desc_len = sizeof(struct ath_desc);
354
355 /* ath_desc must be a multiple of DWORDs */
356 if ((desc_len % 4) != 0) {
357 ath_err(common, "ath_desc not DWORD aligned\n");
358 BUG_ON((desc_len % 4) != 0);
359 return -ENOMEM;
360 }
361
362 dd->dd_desc_len = desc_len * nbuf * ndesc;
363
364 /*
365 * Need additional DMA memory because we can't use
366 * descriptors that cross the 4K page boundary. Assume
367 * one skipped descriptor per 4K page.
368 */
369 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
370 u32 ndesc_skipped =
371 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
372 u32 dma_len;
373
374 while (ndesc_skipped) {
375 dma_len = ndesc_skipped * desc_len;
376 dd->dd_desc_len += dma_len;
377
378 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
379 }
380 }
381
382 /* allocate descriptors */
383 dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len,
384 &dd->dd_desc_paddr, GFP_KERNEL);
385 if (!dd->dd_desc)
386 return -ENOMEM;
387
388 ds = (u8 *) dd->dd_desc;
389 ath_dbg(common, CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
390 name, ds, (u32) dd->dd_desc_len,
391 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
392
393 /* allocate buffers */
394 bsize = sizeof(struct ath_buf) * nbuf;
395 bf = devm_kzalloc(sc->dev, bsize, GFP_KERNEL);
396 if (!bf)
397 return -ENOMEM;
398
399 for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) {
400 bf->bf_desc = ds;
401 bf->bf_daddr = DS2PHYS(dd, ds);
402
403 if (!(sc->sc_ah->caps.hw_caps &
404 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
405 /*
406 * Skip descriptor addresses which can cause 4KB
407 * boundary crossing (addr + length) with a 32 dword
408 * descriptor fetch.
409 */
410 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
411 BUG_ON((caddr_t) bf->bf_desc >=
412 ((caddr_t) dd->dd_desc +
413 dd->dd_desc_len));
414
415 ds += (desc_len * ndesc);
416 bf->bf_desc = ds;
417 bf->bf_daddr = DS2PHYS(dd, ds);
418 }
419 }
420 list_add_tail(&bf->list, head);
421 }
422 return 0;
423 }
424
425 static int ath9k_init_queues(struct ath_softc *sc)
426 {
427 int i = 0;
428
429 sc->beacon.beaconq = ath9k_hw_beaconq_setup(sc->sc_ah);
430 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
431
432 sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
433 ath_cabq_update(sc);
434
435 sc->tx.uapsdq = ath_txq_setup(sc, ATH9K_TX_QUEUE_UAPSD, 0);
436
437 for (i = 0; i < IEEE80211_NUM_ACS; i++) {
438 sc->tx.txq_map[i] = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, i);
439 sc->tx.txq_map[i]->mac80211_qnum = i;
440 sc->tx.txq_max_pending[i] = ATH_MAX_QDEPTH;
441 }
442 return 0;
443 }
444
445 static int ath9k_init_channels_rates(struct ath_softc *sc)
446 {
447 void *channels;
448
449 BUILD_BUG_ON(ARRAY_SIZE(ath9k_2ghz_chantable) +
450 ARRAY_SIZE(ath9k_5ghz_chantable) !=
451 ATH9K_NUM_CHANNELS);
452
453 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) {
454 channels = devm_kzalloc(sc->dev,
455 sizeof(ath9k_2ghz_chantable), GFP_KERNEL);
456 if (!channels)
457 return -ENOMEM;
458
459 memcpy(channels, ath9k_2ghz_chantable,
460 sizeof(ath9k_2ghz_chantable));
461 sc->sbands[IEEE80211_BAND_2GHZ].channels = channels;
462 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
463 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
464 ARRAY_SIZE(ath9k_2ghz_chantable);
465 sc->sbands[IEEE80211_BAND_2GHZ].bitrates = ath9k_legacy_rates;
466 sc->sbands[IEEE80211_BAND_2GHZ].n_bitrates =
467 ARRAY_SIZE(ath9k_legacy_rates);
468 }
469
470 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) {
471 channels = devm_kzalloc(sc->dev,
472 sizeof(ath9k_5ghz_chantable), GFP_KERNEL);
473 if (!channels)
474 return -ENOMEM;
475
476 memcpy(channels, ath9k_5ghz_chantable,
477 sizeof(ath9k_5ghz_chantable));
478 sc->sbands[IEEE80211_BAND_5GHZ].channels = channels;
479 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
480 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
481 ARRAY_SIZE(ath9k_5ghz_chantable);
482 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
483 ath9k_legacy_rates + 4;
484 sc->sbands[IEEE80211_BAND_5GHZ].n_bitrates =
485 ARRAY_SIZE(ath9k_legacy_rates) - 4;
486 }
487 return 0;
488 }
489
490 static void ath9k_init_misc(struct ath_softc *sc)
491 {
492 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
493 int i = 0;
494
495 setup_timer(&common->ani.timer, ath_ani_calibrate, (unsigned long)sc);
496
497 sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
498 sc->config.txpowlimit = ATH_TXPOWER_MAX;
499 memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN);
500 sc->beacon.slottime = ATH9K_SLOT_TIME_9;
501
502 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++)
503 sc->beacon.bslot[i] = NULL;
504
505 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB)
506 sc->ant_comb.count = ATH_ANT_DIV_COMB_INIT_COUNT;
507
508 sc->spec_config.enabled = 0;
509 sc->spec_config.short_repeat = true;
510 sc->spec_config.count = 8;
511 sc->spec_config.endless = false;
512 sc->spec_config.period = 0xFF;
513 sc->spec_config.fft_period = 0xF;
514 }
515
516 static void ath9k_init_platform(struct ath_softc *sc)
517 {
518 struct ath_hw *ah = sc->sc_ah;
519 struct ath_common *common = ath9k_hw_common(ah);
520
521 if (common->bus_ops->ath_bus_type != ATH_PCI)
522 return;
523
524 if (sc->driver_data & (ATH9K_PCI_CUS198 |
525 ATH9K_PCI_CUS230)) {
526 ah->config.xlna_gpio = 9;
527 ah->config.xatten_margin_cfg = true;
528
529 ath_info(common, "Set parameters for %s\n",
530 (sc->driver_data & ATH9K_PCI_CUS198) ?
531 "CUS198" : "CUS230");
532 } else if (sc->driver_data & ATH9K_PCI_CUS217) {
533 ath_info(common, "CUS217 card detected\n");
534 }
535 }
536
537 static void ath9k_eeprom_request_cb(const struct firmware *eeprom_blob,
538 void *ctx)
539 {
540 struct ath9k_eeprom_ctx *ec = ctx;
541
542 if (eeprom_blob)
543 ec->ah->eeprom_blob = eeprom_blob;
544
545 complete(&ec->complete);
546 }
547
548 static int ath9k_eeprom_request(struct ath_softc *sc, const char *name)
549 {
550 struct ath9k_eeprom_ctx ec;
551 struct ath_hw *ah = ah = sc->sc_ah;
552 int err;
553
554 /* try to load the EEPROM content asynchronously */
555 init_completion(&ec.complete);
556 ec.ah = sc->sc_ah;
557
558 err = request_firmware_nowait(THIS_MODULE, 1, name, sc->dev, GFP_KERNEL,
559 &ec, ath9k_eeprom_request_cb);
560 if (err < 0) {
561 ath_err(ath9k_hw_common(ah),
562 "EEPROM request failed\n");
563 return err;
564 }
565
566 wait_for_completion(&ec.complete);
567
568 if (!ah->eeprom_blob) {
569 ath_err(ath9k_hw_common(ah),
570 "Unable to load EEPROM file %s\n", name);
571 return -EINVAL;
572 }
573
574 return 0;
575 }
576
577 static void ath9k_eeprom_release(struct ath_softc *sc)
578 {
579 release_firmware(sc->sc_ah->eeprom_blob);
580 }
581
582 static int ath9k_init_softc(u16 devid, struct ath_softc *sc,
583 const struct ath_bus_ops *bus_ops)
584 {
585 struct ath9k_platform_data *pdata = sc->dev->platform_data;
586 struct ath_hw *ah = NULL;
587 struct ath_common *common;
588 int ret = 0, i;
589 int csz = 0;
590
591 ah = devm_kzalloc(sc->dev, sizeof(struct ath_hw), GFP_KERNEL);
592 if (!ah)
593 return -ENOMEM;
594
595 ah->dev = sc->dev;
596 ah->hw = sc->hw;
597 ah->hw_version.devid = devid;
598 ah->reg_ops.read = ath9k_ioread32;
599 ah->reg_ops.write = ath9k_iowrite32;
600 ah->reg_ops.rmw = ath9k_reg_rmw;
601 atomic_set(&ah->intr_ref_cnt, -1);
602 sc->sc_ah = ah;
603
604 sc->dfs_detector = dfs_pattern_detector_init(ah, NL80211_DFS_UNSET);
605
606 if (!pdata) {
607 ah->ah_flags |= AH_USE_EEPROM;
608 sc->sc_ah->led_pin = -1;
609 } else {
610 sc->sc_ah->gpio_mask = pdata->gpio_mask;
611 sc->sc_ah->gpio_val = pdata->gpio_val;
612 sc->sc_ah->led_pin = pdata->led_pin;
613 ah->is_clk_25mhz = pdata->is_clk_25mhz;
614 ah->get_mac_revision = pdata->get_mac_revision;
615 ah->external_reset = pdata->external_reset;
616 }
617
618 common = ath9k_hw_common(ah);
619 common->ops = &ah->reg_ops;
620 common->bus_ops = bus_ops;
621 common->ah = ah;
622 common->hw = sc->hw;
623 common->priv = sc;
624 common->debug_mask = ath9k_debug;
625 common->btcoex_enabled = ath9k_btcoex_enable == 1;
626 common->disable_ani = false;
627
628 /*
629 * Platform quirks.
630 */
631 ath9k_init_platform(sc);
632
633 /*
634 * Enable Antenna diversity only when BTCOEX is disabled
635 * and the user manually requests the feature.
636 */
637 if (!common->btcoex_enabled && ath9k_enable_diversity)
638 common->antenna_diversity = 1;
639
640 spin_lock_init(&common->cc_lock);
641
642 spin_lock_init(&sc->sc_serial_rw);
643 spin_lock_init(&sc->sc_pm_lock);
644 mutex_init(&sc->mutex);
645 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
646 tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet,
647 (unsigned long)sc);
648
649 INIT_WORK(&sc->hw_reset_work, ath_reset_work);
650 INIT_WORK(&sc->hw_check_work, ath_hw_check);
651 INIT_WORK(&sc->paprd_work, ath_paprd_calibrate);
652 INIT_DELAYED_WORK(&sc->hw_pll_work, ath_hw_pll_work);
653 setup_timer(&sc->rx_poll_timer, ath_rx_poll, (unsigned long)sc);
654
655 /*
656 * Cache line size is used to size and align various
657 * structures used to communicate with the hardware.
658 */
659 ath_read_cachesize(common, &csz);
660 common->cachelsz = csz << 2; /* convert to bytes */
661
662 if (pdata && pdata->eeprom_name) {
663 ret = ath9k_eeprom_request(sc, pdata->eeprom_name);
664 if (ret)
665 return ret;
666 }
667
668 /* Initializes the hardware for all supported chipsets */
669 ret = ath9k_hw_init(ah);
670 if (ret)
671 goto err_hw;
672
673 if (pdata && pdata->macaddr)
674 memcpy(common->macaddr, pdata->macaddr, ETH_ALEN);
675
676 ret = ath9k_init_queues(sc);
677 if (ret)
678 goto err_queues;
679
680 ret = ath9k_init_btcoex(sc);
681 if (ret)
682 goto err_btcoex;
683
684 ret = ath9k_init_channels_rates(sc);
685 if (ret)
686 goto err_btcoex;
687
688 ath9k_cmn_init_crypto(sc->sc_ah);
689 ath9k_init_misc(sc);
690 ath_fill_led_pin(sc);
691
692 if (common->bus_ops->aspm_init)
693 common->bus_ops->aspm_init(common);
694
695 return 0;
696
697 err_btcoex:
698 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
699 if (ATH_TXQ_SETUP(sc, i))
700 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
701 err_queues:
702 ath9k_hw_deinit(ah);
703 err_hw:
704 ath9k_eeprom_release(sc);
705 return ret;
706 }
707
708 static void ath9k_init_band_txpower(struct ath_softc *sc, int band)
709 {
710 struct ieee80211_supported_band *sband;
711 struct ieee80211_channel *chan;
712 struct ath_hw *ah = sc->sc_ah;
713 int i;
714
715 sband = &sc->sbands[band];
716 for (i = 0; i < sband->n_channels; i++) {
717 chan = &sband->channels[i];
718 ah->curchan = &ah->channels[chan->hw_value];
719 ath9k_cmn_update_ichannel(ah->curchan, chan, NL80211_CHAN_HT20);
720 ath9k_hw_set_txpowerlimit(ah, MAX_RATE_POWER, true);
721 }
722 }
723
724 static void ath9k_init_txpower_limits(struct ath_softc *sc)
725 {
726 struct ath_hw *ah = sc->sc_ah;
727 struct ath9k_channel *curchan = ah->curchan;
728
729 if (ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
730 ath9k_init_band_txpower(sc, IEEE80211_BAND_2GHZ);
731 if (ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
732 ath9k_init_band_txpower(sc, IEEE80211_BAND_5GHZ);
733
734 ah->curchan = curchan;
735 }
736
737 void ath9k_reload_chainmask_settings(struct ath_softc *sc)
738 {
739 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT))
740 return;
741
742 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
743 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
744 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
745 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
746 }
747
748 static const struct ieee80211_iface_limit if_limits[] = {
749 { .max = 2048, .types = BIT(NL80211_IFTYPE_STATION) |
750 BIT(NL80211_IFTYPE_P2P_CLIENT) |
751 BIT(NL80211_IFTYPE_WDS) },
752 { .max = 8, .types =
753 #ifdef CONFIG_MAC80211_MESH
754 BIT(NL80211_IFTYPE_MESH_POINT) |
755 #endif
756 BIT(NL80211_IFTYPE_AP) |
757 BIT(NL80211_IFTYPE_P2P_GO) },
758 };
759
760
761 static const struct ieee80211_iface_limit if_dfs_limits[] = {
762 { .max = 1, .types = BIT(NL80211_IFTYPE_AP) },
763 };
764
765 static const struct ieee80211_iface_combination if_comb[] = {
766 {
767 .limits = if_limits,
768 .n_limits = ARRAY_SIZE(if_limits),
769 .max_interfaces = 2048,
770 .num_different_channels = 1,
771 .beacon_int_infra_match = true,
772 },
773 {
774 .limits = if_dfs_limits,
775 .n_limits = ARRAY_SIZE(if_dfs_limits),
776 .max_interfaces = 1,
777 .num_different_channels = 1,
778 .beacon_int_infra_match = true,
779 .radar_detect_widths = BIT(NL80211_CHAN_NO_HT) |
780 BIT(NL80211_CHAN_HT20),
781 }
782 };
783
784 #ifdef CONFIG_PM
785 static const struct wiphy_wowlan_support ath9k_wowlan_support = {
786 .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_DISCONNECT,
787 .n_patterns = MAX_NUM_USER_PATTERN,
788 .pattern_min_len = 1,
789 .pattern_max_len = MAX_PATTERN_SIZE,
790 };
791 #endif
792
793 void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
794 {
795 struct ath_hw *ah = sc->sc_ah;
796 struct ath_common *common = ath9k_hw_common(ah);
797
798 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
799 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
800 IEEE80211_HW_SIGNAL_DBM |
801 IEEE80211_HW_SUPPORTS_PS |
802 IEEE80211_HW_PS_NULLFUNC_STACK |
803 IEEE80211_HW_SPECTRUM_MGMT |
804 IEEE80211_HW_REPORTS_TX_ACK_STATUS |
805 IEEE80211_HW_SUPPORTS_RC_TABLE |
806 IEEE80211_HW_SUPPORTS_HT_CCK_RATES;
807
808 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
809 hw->flags |= IEEE80211_HW_AMPDU_AGGREGATION;
810
811 if (AR_SREV_9280_20_OR_LATER(ah))
812 hw->radiotap_mcs_details |=
813 IEEE80211_RADIOTAP_MCS_HAVE_STBC;
814 }
815
816 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || ath9k_modparam_nohwcrypt)
817 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
818
819 hw->wiphy->features |= NL80211_FEATURE_ACTIVE_MONITOR;
820
821 hw->wiphy->interface_modes =
822 BIT(NL80211_IFTYPE_P2P_GO) |
823 BIT(NL80211_IFTYPE_P2P_CLIENT) |
824 BIT(NL80211_IFTYPE_AP) |
825 BIT(NL80211_IFTYPE_WDS) |
826 BIT(NL80211_IFTYPE_STATION) |
827 BIT(NL80211_IFTYPE_ADHOC) |
828 BIT(NL80211_IFTYPE_MESH_POINT);
829
830 hw->wiphy->iface_combinations = if_comb;
831 hw->wiphy->n_iface_combinations = ARRAY_SIZE(if_comb);
832
833 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
834
835 hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN;
836 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS;
837 hw->wiphy->flags |= WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL;
838
839 #ifdef CONFIG_PM_SLEEP
840 if ((ah->caps.hw_caps & ATH9K_HW_WOW_DEVICE_CAPABLE) &&
841 (sc->driver_data & ATH9K_PCI_WOW) &&
842 device_can_wakeup(sc->dev))
843 hw->wiphy->wowlan = &ath9k_wowlan_support;
844
845 atomic_set(&sc->wow_sleep_proc_intr, -1);
846 atomic_set(&sc->wow_got_bmiss_intr, -1);
847 #endif
848
849 hw->queues = 4;
850 hw->max_rates = 4;
851 hw->channel_change_time = 5000;
852 hw->max_listen_interval = 1;
853 hw->max_rate_tries = 10;
854 hw->sta_data_size = sizeof(struct ath_node);
855 hw->vif_data_size = sizeof(struct ath_vif);
856
857 hw->wiphy->available_antennas_rx = BIT(ah->caps.max_rxchains) - 1;
858 hw->wiphy->available_antennas_tx = BIT(ah->caps.max_txchains) - 1;
859
860 /* single chain devices with rx diversity */
861 if (ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB)
862 hw->wiphy->available_antennas_rx = BIT(0) | BIT(1);
863
864 sc->ant_rx = hw->wiphy->available_antennas_rx;
865 sc->ant_tx = hw->wiphy->available_antennas_tx;
866
867 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
868 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
869 &sc->sbands[IEEE80211_BAND_2GHZ];
870 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
871 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
872 &sc->sbands[IEEE80211_BAND_5GHZ];
873
874 ath9k_reload_chainmask_settings(sc);
875
876 SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
877 }
878
879 int ath9k_init_device(u16 devid, struct ath_softc *sc,
880 const struct ath_bus_ops *bus_ops)
881 {
882 struct ieee80211_hw *hw = sc->hw;
883 struct ath_common *common;
884 struct ath_hw *ah;
885 int error = 0;
886 struct ath_regulatory *reg;
887
888 /* Bring up device */
889 error = ath9k_init_softc(devid, sc, bus_ops);
890 if (error)
891 return error;
892
893 ah = sc->sc_ah;
894 common = ath9k_hw_common(ah);
895 ath9k_set_hw_capab(sc, hw);
896
897 /* Initialize regulatory */
898 error = ath_regd_init(&common->regulatory, sc->hw->wiphy,
899 ath9k_reg_notifier);
900 if (error)
901 goto deinit;
902
903 reg = &common->regulatory;
904
905 /* Setup TX DMA */
906 error = ath_tx_init(sc, ATH_TXBUF);
907 if (error != 0)
908 goto deinit;
909
910 /* Setup RX DMA */
911 error = ath_rx_init(sc, ATH_RXBUF);
912 if (error != 0)
913 goto deinit;
914
915 ath9k_init_txpower_limits(sc);
916
917 #ifdef CONFIG_MAC80211_LEDS
918 /* must be initialized before ieee80211_register_hw */
919 sc->led_cdev.default_trigger = ieee80211_create_tpt_led_trigger(sc->hw,
920 IEEE80211_TPT_LEDTRIG_FL_RADIO, ath9k_tpt_blink,
921 ARRAY_SIZE(ath9k_tpt_blink));
922 #endif
923
924 /* Register with mac80211 */
925 error = ieee80211_register_hw(hw);
926 if (error)
927 goto rx_cleanup;
928
929 error = ath9k_init_debug(ah);
930 if (error) {
931 ath_err(common, "Unable to create debugfs files\n");
932 goto unregister;
933 }
934
935 /* Handle world regulatory */
936 if (!ath_is_world_regd(reg)) {
937 error = regulatory_hint(hw->wiphy, reg->alpha2);
938 if (error)
939 goto debug_cleanup;
940 }
941
942 ath_init_leds(sc);
943 ath_start_rfkill_poll(sc);
944
945 return 0;
946
947 debug_cleanup:
948 ath9k_deinit_debug(sc);
949 unregister:
950 ieee80211_unregister_hw(hw);
951 rx_cleanup:
952 ath_rx_cleanup(sc);
953 deinit:
954 ath9k_deinit_softc(sc);
955 return error;
956 }
957
958 /*****************************/
959 /* De-Initialization */
960 /*****************************/
961
962 static void ath9k_deinit_softc(struct ath_softc *sc)
963 {
964 int i = 0;
965
966 ath9k_deinit_btcoex(sc);
967
968 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
969 if (ATH_TXQ_SETUP(sc, i))
970 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
971
972 ath9k_hw_deinit(sc->sc_ah);
973 if (sc->dfs_detector != NULL)
974 sc->dfs_detector->exit(sc->dfs_detector);
975
976 ath9k_eeprom_release(sc);
977 }
978
979 void ath9k_deinit_device(struct ath_softc *sc)
980 {
981 struct ieee80211_hw *hw = sc->hw;
982
983 ath9k_ps_wakeup(sc);
984
985 wiphy_rfkill_stop_polling(sc->hw->wiphy);
986 ath_deinit_leds(sc);
987
988 ath9k_ps_restore(sc);
989
990 ath9k_deinit_debug(sc);
991 ieee80211_unregister_hw(hw);
992 ath_rx_cleanup(sc);
993 ath9k_deinit_softc(sc);
994 }
995
996 /************************/
997 /* Module Hooks */
998 /************************/
999
1000 static int __init ath9k_init(void)
1001 {
1002 int error;
1003
1004 /* Register rate control algorithm */
1005 error = ath_rate_control_register();
1006 if (error != 0) {
1007 pr_err("Unable to register rate control algorithm: %d\n",
1008 error);
1009 goto err_out;
1010 }
1011
1012 error = ath_pci_init();
1013 if (error < 0) {
1014 pr_err("No PCI devices found, driver not installed\n");
1015 error = -ENODEV;
1016 goto err_rate_unregister;
1017 }
1018
1019 error = ath_ahb_init();
1020 if (error < 0) {
1021 error = -ENODEV;
1022 goto err_pci_exit;
1023 }
1024
1025 return 0;
1026
1027 err_pci_exit:
1028 ath_pci_exit();
1029
1030 err_rate_unregister:
1031 ath_rate_control_unregister();
1032 err_out:
1033 return error;
1034 }
1035 module_init(ath9k_init);
1036
1037 static void __exit ath9k_exit(void)
1038 {
1039 is_ath9k_unloaded = true;
1040 ath_ahb_exit();
1041 ath_pci_exit();
1042 ath_rate_control_unregister();
1043 pr_info("%s: Driver unloaded\n", dev_info);
1044 }
1045 module_exit(ath9k_exit);
Linux kernel - Deliverables
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