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ath9k: make rfkill configurable
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / main.c
1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/nl80211.h>
18 #include <linux/delay.h>
19 #include "ath9k.h"
20 #include "btcoex.h"
21
22 static void ath9k_set_assoc_state(struct ath_softc *sc,
23 struct ieee80211_vif *vif);
24
25 u8 ath9k_parse_mpdudensity(u8 mpdudensity)
26 {
27 /*
28 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
29 * 0 for no restriction
30 * 1 for 1/4 us
31 * 2 for 1/2 us
32 * 3 for 1 us
33 * 4 for 2 us
34 * 5 for 4 us
35 * 6 for 8 us
36 * 7 for 16 us
37 */
38 switch (mpdudensity) {
39 case 0:
40 return 0;
41 case 1:
42 case 2:
43 case 3:
44 /* Our lower layer calculations limit our precision to
45 1 microsecond */
46 return 1;
47 case 4:
48 return 2;
49 case 5:
50 return 4;
51 case 6:
52 return 8;
53 case 7:
54 return 16;
55 default:
56 return 0;
57 }
58 }
59
60 static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq)
61 {
62 bool pending = false;
63
64 spin_lock_bh(&txq->axq_lock);
65
66 if (txq->axq_depth || !list_empty(&txq->axq_acq))
67 pending = true;
68
69 spin_unlock_bh(&txq->axq_lock);
70 return pending;
71 }
72
73 static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
74 {
75 unsigned long flags;
76 bool ret;
77
78 spin_lock_irqsave(&sc->sc_pm_lock, flags);
79 ret = ath9k_hw_setpower(sc->sc_ah, mode);
80 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
81
82 return ret;
83 }
84
85 void ath9k_ps_wakeup(struct ath_softc *sc)
86 {
87 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
88 unsigned long flags;
89 enum ath9k_power_mode power_mode;
90
91 spin_lock_irqsave(&sc->sc_pm_lock, flags);
92 if (++sc->ps_usecount != 1)
93 goto unlock;
94
95 power_mode = sc->sc_ah->power_mode;
96 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
97
98 /*
99 * While the hardware is asleep, the cycle counters contain no
100 * useful data. Better clear them now so that they don't mess up
101 * survey data results.
102 */
103 if (power_mode != ATH9K_PM_AWAKE) {
104 spin_lock(&common->cc_lock);
105 ath_hw_cycle_counters_update(common);
106 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
107 memset(&common->cc_ani, 0, sizeof(common->cc_ani));
108 spin_unlock(&common->cc_lock);
109 }
110
111 unlock:
112 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
113 }
114
115 void ath9k_ps_restore(struct ath_softc *sc)
116 {
117 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
118 enum ath9k_power_mode mode;
119 unsigned long flags;
120 bool reset;
121
122 spin_lock_irqsave(&sc->sc_pm_lock, flags);
123 if (--sc->ps_usecount != 0)
124 goto unlock;
125
126 if (sc->ps_idle) {
127 ath9k_hw_setrxabort(sc->sc_ah, 1);
128 ath9k_hw_stopdmarecv(sc->sc_ah, &reset);
129 mode = ATH9K_PM_FULL_SLEEP;
130 } else if (sc->ps_enabled &&
131 !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
132 PS_WAIT_FOR_CAB |
133 PS_WAIT_FOR_PSPOLL_DATA |
134 PS_WAIT_FOR_TX_ACK |
135 PS_WAIT_FOR_ANI))) {
136 mode = ATH9K_PM_NETWORK_SLEEP;
137 if (ath9k_hw_btcoex_is_enabled(sc->sc_ah))
138 ath9k_btcoex_stop_gen_timer(sc);
139 } else {
140 goto unlock;
141 }
142
143 spin_lock(&common->cc_lock);
144 ath_hw_cycle_counters_update(common);
145 spin_unlock(&common->cc_lock);
146
147 ath9k_hw_setpower(sc->sc_ah, mode);
148
149 unlock:
150 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
151 }
152
153 static void __ath_cancel_work(struct ath_softc *sc)
154 {
155 cancel_work_sync(&sc->paprd_work);
156 cancel_work_sync(&sc->hw_check_work);
157 cancel_delayed_work_sync(&sc->tx_complete_work);
158 cancel_delayed_work_sync(&sc->hw_pll_work);
159
160 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
161 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
162 cancel_work_sync(&sc->mci_work);
163 #endif
164 }
165
166 static void ath_cancel_work(struct ath_softc *sc)
167 {
168 __ath_cancel_work(sc);
169 cancel_work_sync(&sc->hw_reset_work);
170 }
171
172 static void ath_restart_work(struct ath_softc *sc)
173 {
174 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
175
176 if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9485(sc->sc_ah) ||
177 AR_SREV_9550(sc->sc_ah))
178 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work,
179 msecs_to_jiffies(ATH_PLL_WORK_INTERVAL));
180
181 ath_start_rx_poll(sc, 3);
182 ath_start_ani(sc);
183 }
184
185 static bool ath_prepare_reset(struct ath_softc *sc)
186 {
187 struct ath_hw *ah = sc->sc_ah;
188 bool ret = true;
189
190 ieee80211_stop_queues(sc->hw);
191
192 sc->hw_busy_count = 0;
193 ath_stop_ani(sc);
194 del_timer_sync(&sc->rx_poll_timer);
195
196 ath9k_hw_disable_interrupts(ah);
197
198 if (!ath_drain_all_txq(sc))
199 ret = false;
200
201 if (!ath_stoprecv(sc))
202 ret = false;
203
204 return ret;
205 }
206
207 static bool ath_complete_reset(struct ath_softc *sc, bool start)
208 {
209 struct ath_hw *ah = sc->sc_ah;
210 struct ath_common *common = ath9k_hw_common(ah);
211 unsigned long flags;
212
213 if (ath_startrecv(sc) != 0) {
214 ath_err(common, "Unable to restart recv logic\n");
215 return false;
216 }
217
218 ath9k_cmn_update_txpow(ah, sc->curtxpow,
219 sc->config.txpowlimit, &sc->curtxpow);
220
221 clear_bit(SC_OP_HW_RESET, &sc->sc_flags);
222 ath9k_hw_set_interrupts(ah);
223 ath9k_hw_enable_interrupts(ah);
224
225 if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) && start) {
226 if (!test_bit(SC_OP_BEACONS, &sc->sc_flags))
227 goto work;
228
229 if (ah->opmode == NL80211_IFTYPE_STATION &&
230 test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
231 spin_lock_irqsave(&sc->sc_pm_lock, flags);
232 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
233 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
234 } else {
235 ath9k_set_beacon(sc);
236 }
237 work:
238 ath_restart_work(sc);
239 }
240
241 if ((ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) && sc->ant_rx != 3)
242 ath_ant_comb_update(sc);
243
244 ieee80211_wake_queues(sc->hw);
245
246 return true;
247 }
248
249 static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan)
250 {
251 struct ath_hw *ah = sc->sc_ah;
252 struct ath_common *common = ath9k_hw_common(ah);
253 struct ath9k_hw_cal_data *caldata = NULL;
254 bool fastcc = true;
255 int r;
256
257 __ath_cancel_work(sc);
258
259 tasklet_disable(&sc->intr_tq);
260 spin_lock_bh(&sc->sc_pcu_lock);
261
262 if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) {
263 fastcc = false;
264 caldata = &sc->caldata;
265 }
266
267 if (!hchan) {
268 fastcc = false;
269 hchan = ah->curchan;
270 }
271
272 if (!ath_prepare_reset(sc))
273 fastcc = false;
274
275 ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n",
276 hchan->channel, IS_CHAN_HT40(hchan), fastcc);
277
278 r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
279 if (r) {
280 ath_err(common,
281 "Unable to reset channel, reset status %d\n", r);
282
283 ath9k_hw_enable_interrupts(ah);
284 ath9k_queue_reset(sc, RESET_TYPE_BB_HANG);
285
286 goto out;
287 }
288
289 if (ath9k_hw_mci_is_enabled(sc->sc_ah) &&
290 (sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
291 ath9k_mci_set_txpower(sc, true, false);
292
293 if (!ath_complete_reset(sc, true))
294 r = -EIO;
295
296 out:
297 spin_unlock_bh(&sc->sc_pcu_lock);
298 tasklet_enable(&sc->intr_tq);
299
300 return r;
301 }
302
303
304 /*
305 * Set/change channels. If the channel is really being changed, it's done
306 * by reseting the chip. To accomplish this we must first cleanup any pending
307 * DMA, then restart stuff.
308 */
309 static int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
310 struct ath9k_channel *hchan)
311 {
312 int r;
313
314 if (test_bit(SC_OP_INVALID, &sc->sc_flags))
315 return -EIO;
316
317 r = ath_reset_internal(sc, hchan);
318
319 return r;
320 }
321
322 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
323 struct ieee80211_vif *vif)
324 {
325 struct ath_node *an;
326 an = (struct ath_node *)sta->drv_priv;
327
328 an->sc = sc;
329 an->sta = sta;
330 an->vif = vif;
331
332 ath_tx_node_init(sc, an);
333
334 if (sta->ht_cap.ht_supported) {
335 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
336 sta->ht_cap.ampdu_factor);
337 an->mpdudensity = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density);
338 }
339 }
340
341 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
342 {
343 struct ath_node *an = (struct ath_node *)sta->drv_priv;
344 ath_tx_node_cleanup(sc, an);
345 }
346
347 void ath9k_tasklet(unsigned long data)
348 {
349 struct ath_softc *sc = (struct ath_softc *)data;
350 struct ath_hw *ah = sc->sc_ah;
351 struct ath_common *common = ath9k_hw_common(ah);
352 enum ath_reset_type type;
353 unsigned long flags;
354 u32 status = sc->intrstatus;
355 u32 rxmask;
356
357 ath9k_ps_wakeup(sc);
358 spin_lock(&sc->sc_pcu_lock);
359
360 if ((status & ATH9K_INT_FATAL) ||
361 (status & ATH9K_INT_BB_WATCHDOG)) {
362
363 if (status & ATH9K_INT_FATAL)
364 type = RESET_TYPE_FATAL_INT;
365 else
366 type = RESET_TYPE_BB_WATCHDOG;
367
368 ath9k_queue_reset(sc, type);
369 goto out;
370 }
371
372 spin_lock_irqsave(&sc->sc_pm_lock, flags);
373 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
374 /*
375 * TSF sync does not look correct; remain awake to sync with
376 * the next Beacon.
377 */
378 ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n");
379 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
380 }
381 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
382
383 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
384 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
385 ATH9K_INT_RXORN);
386 else
387 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
388
389 if (status & rxmask) {
390 /* Check for high priority Rx first */
391 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
392 (status & ATH9K_INT_RXHP))
393 ath_rx_tasklet(sc, 0, true);
394
395 ath_rx_tasklet(sc, 0, false);
396 }
397
398 if (status & ATH9K_INT_TX) {
399 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
400 ath_tx_edma_tasklet(sc);
401 else
402 ath_tx_tasklet(sc);
403 }
404
405 ath9k_btcoex_handle_interrupt(sc, status);
406
407 out:
408 /* re-enable hardware interrupt */
409 ath9k_hw_enable_interrupts(ah);
410
411 spin_unlock(&sc->sc_pcu_lock);
412 ath9k_ps_restore(sc);
413 }
414
415 irqreturn_t ath_isr(int irq, void *dev)
416 {
417 #define SCHED_INTR ( \
418 ATH9K_INT_FATAL | \
419 ATH9K_INT_BB_WATCHDOG | \
420 ATH9K_INT_RXORN | \
421 ATH9K_INT_RXEOL | \
422 ATH9K_INT_RX | \
423 ATH9K_INT_RXLP | \
424 ATH9K_INT_RXHP | \
425 ATH9K_INT_TX | \
426 ATH9K_INT_BMISS | \
427 ATH9K_INT_CST | \
428 ATH9K_INT_TSFOOR | \
429 ATH9K_INT_GENTIMER | \
430 ATH9K_INT_MCI)
431
432 struct ath_softc *sc = dev;
433 struct ath_hw *ah = sc->sc_ah;
434 struct ath_common *common = ath9k_hw_common(ah);
435 enum ath9k_int status;
436 bool sched = false;
437
438 /*
439 * The hardware is not ready/present, don't
440 * touch anything. Note this can happen early
441 * on if the IRQ is shared.
442 */
443 if (test_bit(SC_OP_INVALID, &sc->sc_flags))
444 return IRQ_NONE;
445
446 /* shared irq, not for us */
447
448 if (!ath9k_hw_intrpend(ah))
449 return IRQ_NONE;
450
451 if (test_bit(SC_OP_HW_RESET, &sc->sc_flags)) {
452 ath9k_hw_kill_interrupts(ah);
453 return IRQ_HANDLED;
454 }
455
456 /*
457 * Figure out the reason(s) for the interrupt. Note
458 * that the hal returns a pseudo-ISR that may include
459 * bits we haven't explicitly enabled so we mask the
460 * value to insure we only process bits we requested.
461 */
462 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
463 status &= ah->imask; /* discard unasked-for bits */
464
465 /*
466 * If there are no status bits set, then this interrupt was not
467 * for me (should have been caught above).
468 */
469 if (!status)
470 return IRQ_NONE;
471
472 /* Cache the status */
473 sc->intrstatus = status;
474
475 if (status & SCHED_INTR)
476 sched = true;
477
478 /*
479 * If a FATAL or RXORN interrupt is received, we have to reset the
480 * chip immediately.
481 */
482 if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
483 !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
484 goto chip_reset;
485
486 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
487 (status & ATH9K_INT_BB_WATCHDOG)) {
488
489 spin_lock(&common->cc_lock);
490 ath_hw_cycle_counters_update(common);
491 ar9003_hw_bb_watchdog_dbg_info(ah);
492 spin_unlock(&common->cc_lock);
493
494 goto chip_reset;
495 }
496 #ifdef CONFIG_PM_SLEEP
497 if (status & ATH9K_INT_BMISS) {
498 if (atomic_read(&sc->wow_sleep_proc_intr) == 0) {
499 ath_dbg(common, ANY, "during WoW we got a BMISS\n");
500 atomic_inc(&sc->wow_got_bmiss_intr);
501 atomic_dec(&sc->wow_sleep_proc_intr);
502 }
503 }
504 #endif
505 if (status & ATH9K_INT_SWBA)
506 tasklet_schedule(&sc->bcon_tasklet);
507
508 if (status & ATH9K_INT_TXURN)
509 ath9k_hw_updatetxtriglevel(ah, true);
510
511 if (status & ATH9K_INT_RXEOL) {
512 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
513 ath9k_hw_set_interrupts(ah);
514 }
515
516 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
517 if (status & ATH9K_INT_TIM_TIMER) {
518 if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
519 goto chip_reset;
520 /* Clear RxAbort bit so that we can
521 * receive frames */
522 ath9k_setpower(sc, ATH9K_PM_AWAKE);
523 spin_lock(&sc->sc_pm_lock);
524 ath9k_hw_setrxabort(sc->sc_ah, 0);
525 sc->ps_flags |= PS_WAIT_FOR_BEACON;
526 spin_unlock(&sc->sc_pm_lock);
527 }
528
529 chip_reset:
530
531 ath_debug_stat_interrupt(sc, status);
532
533 if (sched) {
534 /* turn off every interrupt */
535 ath9k_hw_disable_interrupts(ah);
536 tasklet_schedule(&sc->intr_tq);
537 }
538
539 return IRQ_HANDLED;
540
541 #undef SCHED_INTR
542 }
543
544 static int ath_reset(struct ath_softc *sc)
545 {
546 int i, r;
547
548 ath9k_ps_wakeup(sc);
549
550 r = ath_reset_internal(sc, NULL);
551
552 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
553 if (!ATH_TXQ_SETUP(sc, i))
554 continue;
555
556 spin_lock_bh(&sc->tx.txq[i].axq_lock);
557 ath_txq_schedule(sc, &sc->tx.txq[i]);
558 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
559 }
560
561 ath9k_ps_restore(sc);
562
563 return r;
564 }
565
566 void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type)
567 {
568 #ifdef CONFIG_ATH9K_DEBUGFS
569 RESET_STAT_INC(sc, type);
570 #endif
571 set_bit(SC_OP_HW_RESET, &sc->sc_flags);
572 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
573 }
574
575 void ath_reset_work(struct work_struct *work)
576 {
577 struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work);
578
579 ath_reset(sc);
580 }
581
582 /**********************/
583 /* mac80211 callbacks */
584 /**********************/
585
586 static int ath9k_start(struct ieee80211_hw *hw)
587 {
588 struct ath_softc *sc = hw->priv;
589 struct ath_hw *ah = sc->sc_ah;
590 struct ath_common *common = ath9k_hw_common(ah);
591 struct ieee80211_channel *curchan = hw->conf.chandef.chan;
592 struct ath9k_channel *init_channel;
593 int r;
594
595 ath_dbg(common, CONFIG,
596 "Starting driver with initial channel: %d MHz\n",
597 curchan->center_freq);
598
599 ath9k_ps_wakeup(sc);
600 mutex_lock(&sc->mutex);
601
602 init_channel = ath9k_cmn_get_curchannel(hw, ah);
603
604 /* Reset SERDES registers */
605 ath9k_hw_configpcipowersave(ah, false);
606
607 /*
608 * The basic interface to setting the hardware in a good
609 * state is ``reset''. On return the hardware is known to
610 * be powered up and with interrupts disabled. This must
611 * be followed by initialization of the appropriate bits
612 * and then setup of the interrupt mask.
613 */
614 spin_lock_bh(&sc->sc_pcu_lock);
615
616 atomic_set(&ah->intr_ref_cnt, -1);
617
618 r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
619 if (r) {
620 ath_err(common,
621 "Unable to reset hardware; reset status %d (freq %u MHz)\n",
622 r, curchan->center_freq);
623 ah->reset_power_on = false;
624 }
625
626 /* Setup our intr mask. */
627 ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
628 ATH9K_INT_RXORN | ATH9K_INT_FATAL |
629 ATH9K_INT_GLOBAL;
630
631 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
632 ah->imask |= ATH9K_INT_RXHP |
633 ATH9K_INT_RXLP |
634 ATH9K_INT_BB_WATCHDOG;
635 else
636 ah->imask |= ATH9K_INT_RX;
637
638 ah->imask |= ATH9K_INT_GTT;
639
640 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
641 ah->imask |= ATH9K_INT_CST;
642
643 ath_mci_enable(sc);
644
645 clear_bit(SC_OP_INVALID, &sc->sc_flags);
646 sc->sc_ah->is_monitoring = false;
647
648 if (!ath_complete_reset(sc, false))
649 ah->reset_power_on = false;
650
651 if (ah->led_pin >= 0) {
652 ath9k_hw_cfg_output(ah, ah->led_pin,
653 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
654 ath9k_hw_set_gpio(ah, ah->led_pin, 0);
655 }
656
657 /*
658 * Reset key cache to sane defaults (all entries cleared) instead of
659 * semi-random values after suspend/resume.
660 */
661 ath9k_cmn_init_crypto(sc->sc_ah);
662
663 spin_unlock_bh(&sc->sc_pcu_lock);
664
665 mutex_unlock(&sc->mutex);
666
667 ath9k_ps_restore(sc);
668
669 return 0;
670 }
671
672 static void ath9k_tx(struct ieee80211_hw *hw,
673 struct ieee80211_tx_control *control,
674 struct sk_buff *skb)
675 {
676 struct ath_softc *sc = hw->priv;
677 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
678 struct ath_tx_control txctl;
679 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
680 unsigned long flags;
681
682 if (sc->ps_enabled) {
683 /*
684 * mac80211 does not set PM field for normal data frames, so we
685 * need to update that based on the current PS mode.
686 */
687 if (ieee80211_is_data(hdr->frame_control) &&
688 !ieee80211_is_nullfunc(hdr->frame_control) &&
689 !ieee80211_has_pm(hdr->frame_control)) {
690 ath_dbg(common, PS,
691 "Add PM=1 for a TX frame while in PS mode\n");
692 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
693 }
694 }
695
696 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) {
697 /*
698 * We are using PS-Poll and mac80211 can request TX while in
699 * power save mode. Need to wake up hardware for the TX to be
700 * completed and if needed, also for RX of buffered frames.
701 */
702 ath9k_ps_wakeup(sc);
703 spin_lock_irqsave(&sc->sc_pm_lock, flags);
704 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
705 ath9k_hw_setrxabort(sc->sc_ah, 0);
706 if (ieee80211_is_pspoll(hdr->frame_control)) {
707 ath_dbg(common, PS,
708 "Sending PS-Poll to pick a buffered frame\n");
709 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
710 } else {
711 ath_dbg(common, PS, "Wake up to complete TX\n");
712 sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
713 }
714 /*
715 * The actual restore operation will happen only after
716 * the ps_flags bit is cleared. We are just dropping
717 * the ps_usecount here.
718 */
719 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
720 ath9k_ps_restore(sc);
721 }
722
723 /*
724 * Cannot tx while the hardware is in full sleep, it first needs a full
725 * chip reset to recover from that
726 */
727 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) {
728 ath_err(common, "TX while HW is in FULL_SLEEP mode\n");
729 goto exit;
730 }
731
732 memset(&txctl, 0, sizeof(struct ath_tx_control));
733 txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
734 txctl.sta = control->sta;
735
736 ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb);
737
738 if (ath_tx_start(hw, skb, &txctl) != 0) {
739 ath_dbg(common, XMIT, "TX failed\n");
740 TX_STAT_INC(txctl.txq->axq_qnum, txfailed);
741 goto exit;
742 }
743
744 return;
745 exit:
746 ieee80211_free_txskb(hw, skb);
747 }
748
749 static void ath9k_stop(struct ieee80211_hw *hw)
750 {
751 struct ath_softc *sc = hw->priv;
752 struct ath_hw *ah = sc->sc_ah;
753 struct ath_common *common = ath9k_hw_common(ah);
754 bool prev_idle;
755
756 mutex_lock(&sc->mutex);
757
758 ath_cancel_work(sc);
759 del_timer_sync(&sc->rx_poll_timer);
760
761 if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
762 ath_dbg(common, ANY, "Device not present\n");
763 mutex_unlock(&sc->mutex);
764 return;
765 }
766
767 /* Ensure HW is awake when we try to shut it down. */
768 ath9k_ps_wakeup(sc);
769
770 spin_lock_bh(&sc->sc_pcu_lock);
771
772 /* prevent tasklets to enable interrupts once we disable them */
773 ah->imask &= ~ATH9K_INT_GLOBAL;
774
775 /* make sure h/w will not generate any interrupt
776 * before setting the invalid flag. */
777 ath9k_hw_disable_interrupts(ah);
778
779 spin_unlock_bh(&sc->sc_pcu_lock);
780
781 /* we can now sync irq and kill any running tasklets, since we already
782 * disabled interrupts and not holding a spin lock */
783 synchronize_irq(sc->irq);
784 tasklet_kill(&sc->intr_tq);
785 tasklet_kill(&sc->bcon_tasklet);
786
787 prev_idle = sc->ps_idle;
788 sc->ps_idle = true;
789
790 spin_lock_bh(&sc->sc_pcu_lock);
791
792 if (ah->led_pin >= 0) {
793 ath9k_hw_set_gpio(ah, ah->led_pin, 1);
794 ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
795 }
796
797 ath_prepare_reset(sc);
798
799 if (sc->rx.frag) {
800 dev_kfree_skb_any(sc->rx.frag);
801 sc->rx.frag = NULL;
802 }
803
804 if (!ah->curchan)
805 ah->curchan = ath9k_cmn_get_curchannel(hw, ah);
806
807 ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
808 ath9k_hw_phy_disable(ah);
809
810 ath9k_hw_configpcipowersave(ah, true);
811
812 spin_unlock_bh(&sc->sc_pcu_lock);
813
814 ath9k_ps_restore(sc);
815
816 set_bit(SC_OP_INVALID, &sc->sc_flags);
817 sc->ps_idle = prev_idle;
818
819 mutex_unlock(&sc->mutex);
820
821 ath_dbg(common, CONFIG, "Driver halt\n");
822 }
823
824 bool ath9k_uses_beacons(int type)
825 {
826 switch (type) {
827 case NL80211_IFTYPE_AP:
828 case NL80211_IFTYPE_ADHOC:
829 case NL80211_IFTYPE_MESH_POINT:
830 return true;
831 default:
832 return false;
833 }
834 }
835
836 static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
837 {
838 struct ath9k_vif_iter_data *iter_data = data;
839 int i;
840
841 if (iter_data->has_hw_macaddr) {
842 for (i = 0; i < ETH_ALEN; i++)
843 iter_data->mask[i] &=
844 ~(iter_data->hw_macaddr[i] ^ mac[i]);
845 } else {
846 memcpy(iter_data->hw_macaddr, mac, ETH_ALEN);
847 iter_data->has_hw_macaddr = true;
848 }
849
850 switch (vif->type) {
851 case NL80211_IFTYPE_AP:
852 iter_data->naps++;
853 break;
854 case NL80211_IFTYPE_STATION:
855 iter_data->nstations++;
856 break;
857 case NL80211_IFTYPE_ADHOC:
858 iter_data->nadhocs++;
859 break;
860 case NL80211_IFTYPE_MESH_POINT:
861 iter_data->nmeshes++;
862 break;
863 case NL80211_IFTYPE_WDS:
864 iter_data->nwds++;
865 break;
866 default:
867 break;
868 }
869 }
870
871 static void ath9k_sta_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
872 {
873 struct ath_softc *sc = data;
874 struct ath_vif *avp = (void *)vif->drv_priv;
875
876 if (vif->type != NL80211_IFTYPE_STATION)
877 return;
878
879 if (avp->primary_sta_vif)
880 ath9k_set_assoc_state(sc, vif);
881 }
882
883 /* Called with sc->mutex held. */
884 void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
885 struct ieee80211_vif *vif,
886 struct ath9k_vif_iter_data *iter_data)
887 {
888 struct ath_softc *sc = hw->priv;
889 struct ath_hw *ah = sc->sc_ah;
890 struct ath_common *common = ath9k_hw_common(ah);
891
892 /*
893 * Use the hardware MAC address as reference, the hardware uses it
894 * together with the BSSID mask when matching addresses.
895 */
896 memset(iter_data, 0, sizeof(*iter_data));
897 memset(&iter_data->mask, 0xff, ETH_ALEN);
898
899 if (vif)
900 ath9k_vif_iter(iter_data, vif->addr, vif);
901
902 /* Get list of all active MAC addresses */
903 ieee80211_iterate_active_interfaces_atomic(
904 sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
905 ath9k_vif_iter, iter_data);
906
907 memcpy(common->macaddr, iter_data->hw_macaddr, ETH_ALEN);
908 }
909
910 /* Called with sc->mutex held. */
911 static void ath9k_calculate_summary_state(struct ieee80211_hw *hw,
912 struct ieee80211_vif *vif)
913 {
914 struct ath_softc *sc = hw->priv;
915 struct ath_hw *ah = sc->sc_ah;
916 struct ath_common *common = ath9k_hw_common(ah);
917 struct ath9k_vif_iter_data iter_data;
918 enum nl80211_iftype old_opmode = ah->opmode;
919
920 ath9k_calculate_iter_data(hw, vif, &iter_data);
921
922 memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
923 ath_hw_setbssidmask(common);
924
925 if (iter_data.naps > 0) {
926 ath9k_hw_set_tsfadjust(ah, true);
927 ah->opmode = NL80211_IFTYPE_AP;
928 } else {
929 ath9k_hw_set_tsfadjust(ah, false);
930
931 if (iter_data.nmeshes)
932 ah->opmode = NL80211_IFTYPE_MESH_POINT;
933 else if (iter_data.nwds)
934 ah->opmode = NL80211_IFTYPE_AP;
935 else if (iter_data.nadhocs)
936 ah->opmode = NL80211_IFTYPE_ADHOC;
937 else
938 ah->opmode = NL80211_IFTYPE_STATION;
939 }
940
941 ath9k_hw_setopmode(ah);
942
943 if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0)
944 ah->imask |= ATH9K_INT_TSFOOR;
945 else
946 ah->imask &= ~ATH9K_INT_TSFOOR;
947
948 ath9k_hw_set_interrupts(ah);
949
950 /*
951 * If we are changing the opmode to STATION,
952 * a beacon sync needs to be done.
953 */
954 if (ah->opmode == NL80211_IFTYPE_STATION &&
955 old_opmode == NL80211_IFTYPE_AP &&
956 test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
957 ieee80211_iterate_active_interfaces_atomic(
958 sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
959 ath9k_sta_vif_iter, sc);
960 }
961 }
962
963 static int ath9k_add_interface(struct ieee80211_hw *hw,
964 struct ieee80211_vif *vif)
965 {
966 struct ath_softc *sc = hw->priv;
967 struct ath_hw *ah = sc->sc_ah;
968 struct ath_common *common = ath9k_hw_common(ah);
969
970 mutex_lock(&sc->mutex);
971
972 ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type);
973 sc->nvifs++;
974
975 ath9k_ps_wakeup(sc);
976 ath9k_calculate_summary_state(hw, vif);
977 ath9k_ps_restore(sc);
978
979 if (ath9k_uses_beacons(vif->type))
980 ath9k_beacon_assign_slot(sc, vif);
981
982 mutex_unlock(&sc->mutex);
983 return 0;
984 }
985
986 static int ath9k_change_interface(struct ieee80211_hw *hw,
987 struct ieee80211_vif *vif,
988 enum nl80211_iftype new_type,
989 bool p2p)
990 {
991 struct ath_softc *sc = hw->priv;
992 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
993
994 ath_dbg(common, CONFIG, "Change Interface\n");
995 mutex_lock(&sc->mutex);
996
997 if (ath9k_uses_beacons(vif->type))
998 ath9k_beacon_remove_slot(sc, vif);
999
1000 vif->type = new_type;
1001 vif->p2p = p2p;
1002
1003 ath9k_ps_wakeup(sc);
1004 ath9k_calculate_summary_state(hw, vif);
1005 ath9k_ps_restore(sc);
1006
1007 if (ath9k_uses_beacons(vif->type))
1008 ath9k_beacon_assign_slot(sc, vif);
1009
1010 mutex_unlock(&sc->mutex);
1011 return 0;
1012 }
1013
1014 static void ath9k_remove_interface(struct ieee80211_hw *hw,
1015 struct ieee80211_vif *vif)
1016 {
1017 struct ath_softc *sc = hw->priv;
1018 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1019
1020 ath_dbg(common, CONFIG, "Detach Interface\n");
1021
1022 mutex_lock(&sc->mutex);
1023
1024 sc->nvifs--;
1025
1026 if (ath9k_uses_beacons(vif->type))
1027 ath9k_beacon_remove_slot(sc, vif);
1028
1029 ath9k_ps_wakeup(sc);
1030 ath9k_calculate_summary_state(hw, NULL);
1031 ath9k_ps_restore(sc);
1032
1033 mutex_unlock(&sc->mutex);
1034 }
1035
1036 static void ath9k_enable_ps(struct ath_softc *sc)
1037 {
1038 struct ath_hw *ah = sc->sc_ah;
1039 struct ath_common *common = ath9k_hw_common(ah);
1040
1041 sc->ps_enabled = true;
1042 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1043 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
1044 ah->imask |= ATH9K_INT_TIM_TIMER;
1045 ath9k_hw_set_interrupts(ah);
1046 }
1047 ath9k_hw_setrxabort(ah, 1);
1048 }
1049 ath_dbg(common, PS, "PowerSave enabled\n");
1050 }
1051
1052 static void ath9k_disable_ps(struct ath_softc *sc)
1053 {
1054 struct ath_hw *ah = sc->sc_ah;
1055 struct ath_common *common = ath9k_hw_common(ah);
1056
1057 sc->ps_enabled = false;
1058 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
1059 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1060 ath9k_hw_setrxabort(ah, 0);
1061 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
1062 PS_WAIT_FOR_CAB |
1063 PS_WAIT_FOR_PSPOLL_DATA |
1064 PS_WAIT_FOR_TX_ACK);
1065 if (ah->imask & ATH9K_INT_TIM_TIMER) {
1066 ah->imask &= ~ATH9K_INT_TIM_TIMER;
1067 ath9k_hw_set_interrupts(ah);
1068 }
1069 }
1070 ath_dbg(common, PS, "PowerSave disabled\n");
1071 }
1072
1073 void ath9k_spectral_scan_trigger(struct ieee80211_hw *hw)
1074 {
1075 struct ath_softc *sc = hw->priv;
1076 struct ath_hw *ah = sc->sc_ah;
1077 struct ath_common *common = ath9k_hw_common(ah);
1078 u32 rxfilter;
1079
1080 if (!ath9k_hw_ops(ah)->spectral_scan_trigger) {
1081 ath_err(common, "spectrum analyzer not implemented on this hardware\n");
1082 return;
1083 }
1084
1085 ath9k_ps_wakeup(sc);
1086 rxfilter = ath9k_hw_getrxfilter(ah);
1087 ath9k_hw_setrxfilter(ah, rxfilter |
1088 ATH9K_RX_FILTER_PHYRADAR |
1089 ATH9K_RX_FILTER_PHYERR);
1090
1091 /* TODO: usually this should not be neccesary, but for some reason
1092 * (or in some mode?) the trigger must be called after the
1093 * configuration, otherwise the register will have its values reset
1094 * (on my ar9220 to value 0x01002310)
1095 */
1096 ath9k_spectral_scan_config(hw, sc->spectral_mode);
1097 ath9k_hw_ops(ah)->spectral_scan_trigger(ah);
1098 ath9k_ps_restore(sc);
1099 }
1100
1101 int ath9k_spectral_scan_config(struct ieee80211_hw *hw,
1102 enum spectral_mode spectral_mode)
1103 {
1104 struct ath_softc *sc = hw->priv;
1105 struct ath_hw *ah = sc->sc_ah;
1106 struct ath_common *common = ath9k_hw_common(ah);
1107
1108 if (!ath9k_hw_ops(ah)->spectral_scan_trigger) {
1109 ath_err(common, "spectrum analyzer not implemented on this hardware\n");
1110 return -1;
1111 }
1112
1113 switch (spectral_mode) {
1114 case SPECTRAL_DISABLED:
1115 sc->spec_config.enabled = 0;
1116 break;
1117 case SPECTRAL_BACKGROUND:
1118 /* send endless samples.
1119 * TODO: is this really useful for "background"?
1120 */
1121 sc->spec_config.endless = 1;
1122 sc->spec_config.enabled = 1;
1123 break;
1124 case SPECTRAL_CHANSCAN:
1125 case SPECTRAL_MANUAL:
1126 sc->spec_config.endless = 0;
1127 sc->spec_config.enabled = 1;
1128 break;
1129 default:
1130 return -1;
1131 }
1132
1133 ath9k_ps_wakeup(sc);
1134 ath9k_hw_ops(ah)->spectral_scan_config(ah, &sc->spec_config);
1135 ath9k_ps_restore(sc);
1136
1137 sc->spectral_mode = spectral_mode;
1138
1139 return 0;
1140 }
1141
1142 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
1143 {
1144 struct ath_softc *sc = hw->priv;
1145 struct ath_hw *ah = sc->sc_ah;
1146 struct ath_common *common = ath9k_hw_common(ah);
1147 struct ieee80211_conf *conf = &hw->conf;
1148 bool reset_channel = false;
1149
1150 ath9k_ps_wakeup(sc);
1151 mutex_lock(&sc->mutex);
1152
1153 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
1154 sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
1155 if (sc->ps_idle) {
1156 ath_cancel_work(sc);
1157 ath9k_stop_btcoex(sc);
1158 } else {
1159 ath9k_start_btcoex(sc);
1160 /*
1161 * The chip needs a reset to properly wake up from
1162 * full sleep
1163 */
1164 reset_channel = ah->chip_fullsleep;
1165 }
1166 }
1167
1168 /*
1169 * We just prepare to enable PS. We have to wait until our AP has
1170 * ACK'd our null data frame to disable RX otherwise we'll ignore
1171 * those ACKs and end up retransmitting the same null data frames.
1172 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
1173 */
1174 if (changed & IEEE80211_CONF_CHANGE_PS) {
1175 unsigned long flags;
1176 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1177 if (conf->flags & IEEE80211_CONF_PS)
1178 ath9k_enable_ps(sc);
1179 else
1180 ath9k_disable_ps(sc);
1181 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1182 }
1183
1184 if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
1185 if (conf->flags & IEEE80211_CONF_MONITOR) {
1186 ath_dbg(common, CONFIG, "Monitor mode is enabled\n");
1187 sc->sc_ah->is_monitoring = true;
1188 } else {
1189 ath_dbg(common, CONFIG, "Monitor mode is disabled\n");
1190 sc->sc_ah->is_monitoring = false;
1191 }
1192 }
1193
1194 if ((changed & IEEE80211_CONF_CHANGE_CHANNEL) || reset_channel) {
1195 struct ieee80211_channel *curchan = hw->conf.chandef.chan;
1196 enum nl80211_channel_type channel_type =
1197 cfg80211_get_chandef_type(&conf->chandef);
1198 int pos = curchan->hw_value;
1199 int old_pos = -1;
1200 unsigned long flags;
1201
1202 if (ah->curchan)
1203 old_pos = ah->curchan - &ah->channels[0];
1204
1205 ath_dbg(common, CONFIG, "Set channel: %d MHz type: %d\n",
1206 curchan->center_freq, channel_type);
1207
1208 /* update survey stats for the old channel before switching */
1209 spin_lock_irqsave(&common->cc_lock, flags);
1210 ath_update_survey_stats(sc);
1211 spin_unlock_irqrestore(&common->cc_lock, flags);
1212
1213 ath9k_cmn_update_ichannel(&sc->sc_ah->channels[pos],
1214 curchan, channel_type);
1215
1216 /*
1217 * If the operating channel changes, change the survey in-use flags
1218 * along with it.
1219 * Reset the survey data for the new channel, unless we're switching
1220 * back to the operating channel from an off-channel operation.
1221 */
1222 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) &&
1223 sc->cur_survey != &sc->survey[pos]) {
1224
1225 if (sc->cur_survey)
1226 sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE;
1227
1228 sc->cur_survey = &sc->survey[pos];
1229
1230 memset(sc->cur_survey, 0, sizeof(struct survey_info));
1231 sc->cur_survey->filled |= SURVEY_INFO_IN_USE;
1232 } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) {
1233 memset(&sc->survey[pos], 0, sizeof(struct survey_info));
1234 }
1235
1236 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
1237 ath_err(common, "Unable to set channel\n");
1238 mutex_unlock(&sc->mutex);
1239 ath9k_ps_restore(sc);
1240 return -EINVAL;
1241 }
1242
1243 /*
1244 * The most recent snapshot of channel->noisefloor for the old
1245 * channel is only available after the hardware reset. Copy it to
1246 * the survey stats now.
1247 */
1248 if (old_pos >= 0)
1249 ath_update_survey_nf(sc, old_pos);
1250
1251 /*
1252 * Enable radar pulse detection if on a DFS channel. Spectral
1253 * scanning and radar detection can not be used concurrently.
1254 */
1255 if (hw->conf.radar_enabled) {
1256 u32 rxfilter;
1257
1258 /* set HW specific DFS configuration */
1259 ath9k_hw_set_radar_params(ah);
1260 rxfilter = ath9k_hw_getrxfilter(ah);
1261 rxfilter |= ATH9K_RX_FILTER_PHYRADAR |
1262 ATH9K_RX_FILTER_PHYERR;
1263 ath9k_hw_setrxfilter(ah, rxfilter);
1264 ath_dbg(common, DFS, "DFS enabled at freq %d\n",
1265 curchan->center_freq);
1266 } else {
1267 /* perform spectral scan if requested. */
1268 if (test_bit(SC_OP_SCANNING, &sc->sc_flags) &&
1269 sc->spectral_mode == SPECTRAL_CHANSCAN)
1270 ath9k_spectral_scan_trigger(hw);
1271 }
1272 }
1273
1274 if (changed & IEEE80211_CONF_CHANGE_POWER) {
1275 ath_dbg(common, CONFIG, "Set power: %d\n", conf->power_level);
1276 sc->config.txpowlimit = 2 * conf->power_level;
1277 ath9k_cmn_update_txpow(ah, sc->curtxpow,
1278 sc->config.txpowlimit, &sc->curtxpow);
1279 }
1280
1281 mutex_unlock(&sc->mutex);
1282 ath9k_ps_restore(sc);
1283
1284 return 0;
1285 }
1286
1287 #define SUPPORTED_FILTERS \
1288 (FIF_PROMISC_IN_BSS | \
1289 FIF_ALLMULTI | \
1290 FIF_CONTROL | \
1291 FIF_PSPOLL | \
1292 FIF_OTHER_BSS | \
1293 FIF_BCN_PRBRESP_PROMISC | \
1294 FIF_PROBE_REQ | \
1295 FIF_FCSFAIL)
1296
1297 /* FIXME: sc->sc_full_reset ? */
1298 static void ath9k_configure_filter(struct ieee80211_hw *hw,
1299 unsigned int changed_flags,
1300 unsigned int *total_flags,
1301 u64 multicast)
1302 {
1303 struct ath_softc *sc = hw->priv;
1304 u32 rfilt;
1305
1306 changed_flags &= SUPPORTED_FILTERS;
1307 *total_flags &= SUPPORTED_FILTERS;
1308
1309 sc->rx.rxfilter = *total_flags;
1310 ath9k_ps_wakeup(sc);
1311 rfilt = ath_calcrxfilter(sc);
1312 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
1313 ath9k_ps_restore(sc);
1314
1315 ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n",
1316 rfilt);
1317 }
1318
1319 static int ath9k_sta_add(struct ieee80211_hw *hw,
1320 struct ieee80211_vif *vif,
1321 struct ieee80211_sta *sta)
1322 {
1323 struct ath_softc *sc = hw->priv;
1324 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1325 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1326 struct ieee80211_key_conf ps_key = { };
1327 int key;
1328
1329 ath_node_attach(sc, sta, vif);
1330
1331 if (vif->type != NL80211_IFTYPE_AP &&
1332 vif->type != NL80211_IFTYPE_AP_VLAN)
1333 return 0;
1334
1335 key = ath_key_config(common, vif, sta, &ps_key);
1336 if (key > 0)
1337 an->ps_key = key;
1338
1339 return 0;
1340 }
1341
1342 static void ath9k_del_ps_key(struct ath_softc *sc,
1343 struct ieee80211_vif *vif,
1344 struct ieee80211_sta *sta)
1345 {
1346 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1347 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1348 struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key };
1349
1350 if (!an->ps_key)
1351 return;
1352
1353 ath_key_delete(common, &ps_key);
1354 an->ps_key = 0;
1355 }
1356
1357 static int ath9k_sta_remove(struct ieee80211_hw *hw,
1358 struct ieee80211_vif *vif,
1359 struct ieee80211_sta *sta)
1360 {
1361 struct ath_softc *sc = hw->priv;
1362
1363 ath9k_del_ps_key(sc, vif, sta);
1364 ath_node_detach(sc, sta);
1365
1366 return 0;
1367 }
1368
1369 static void ath9k_sta_notify(struct ieee80211_hw *hw,
1370 struct ieee80211_vif *vif,
1371 enum sta_notify_cmd cmd,
1372 struct ieee80211_sta *sta)
1373 {
1374 struct ath_softc *sc = hw->priv;
1375 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1376
1377 if (!sta->ht_cap.ht_supported)
1378 return;
1379
1380 switch (cmd) {
1381 case STA_NOTIFY_SLEEP:
1382 an->sleeping = true;
1383 ath_tx_aggr_sleep(sta, sc, an);
1384 break;
1385 case STA_NOTIFY_AWAKE:
1386 an->sleeping = false;
1387 ath_tx_aggr_wakeup(sc, an);
1388 break;
1389 }
1390 }
1391
1392 static int ath9k_conf_tx(struct ieee80211_hw *hw,
1393 struct ieee80211_vif *vif, u16 queue,
1394 const struct ieee80211_tx_queue_params *params)
1395 {
1396 struct ath_softc *sc = hw->priv;
1397 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1398 struct ath_txq *txq;
1399 struct ath9k_tx_queue_info qi;
1400 int ret = 0;
1401
1402 if (queue >= IEEE80211_NUM_ACS)
1403 return 0;
1404
1405 txq = sc->tx.txq_map[queue];
1406
1407 ath9k_ps_wakeup(sc);
1408 mutex_lock(&sc->mutex);
1409
1410 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
1411
1412 qi.tqi_aifs = params->aifs;
1413 qi.tqi_cwmin = params->cw_min;
1414 qi.tqi_cwmax = params->cw_max;
1415 qi.tqi_burstTime = params->txop * 32;
1416
1417 ath_dbg(common, CONFIG,
1418 "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
1419 queue, txq->axq_qnum, params->aifs, params->cw_min,
1420 params->cw_max, params->txop);
1421
1422 ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime);
1423 ret = ath_txq_update(sc, txq->axq_qnum, &qi);
1424 if (ret)
1425 ath_err(common, "TXQ Update failed\n");
1426
1427 mutex_unlock(&sc->mutex);
1428 ath9k_ps_restore(sc);
1429
1430 return ret;
1431 }
1432
1433 static int ath9k_set_key(struct ieee80211_hw *hw,
1434 enum set_key_cmd cmd,
1435 struct ieee80211_vif *vif,
1436 struct ieee80211_sta *sta,
1437 struct ieee80211_key_conf *key)
1438 {
1439 struct ath_softc *sc = hw->priv;
1440 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1441 int ret = 0;
1442
1443 if (ath9k_modparam_nohwcrypt)
1444 return -ENOSPC;
1445
1446 if ((vif->type == NL80211_IFTYPE_ADHOC ||
1447 vif->type == NL80211_IFTYPE_MESH_POINT) &&
1448 (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
1449 key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
1450 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
1451 /*
1452 * For now, disable hw crypto for the RSN IBSS group keys. This
1453 * could be optimized in the future to use a modified key cache
1454 * design to support per-STA RX GTK, but until that gets
1455 * implemented, use of software crypto for group addressed
1456 * frames is a acceptable to allow RSN IBSS to be used.
1457 */
1458 return -EOPNOTSUPP;
1459 }
1460
1461 mutex_lock(&sc->mutex);
1462 ath9k_ps_wakeup(sc);
1463 ath_dbg(common, CONFIG, "Set HW Key\n");
1464
1465 switch (cmd) {
1466 case SET_KEY:
1467 if (sta)
1468 ath9k_del_ps_key(sc, vif, sta);
1469
1470 ret = ath_key_config(common, vif, sta, key);
1471 if (ret >= 0) {
1472 key->hw_key_idx = ret;
1473 /* push IV and Michael MIC generation to stack */
1474 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
1475 if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
1476 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
1477 if (sc->sc_ah->sw_mgmt_crypto &&
1478 key->cipher == WLAN_CIPHER_SUITE_CCMP)
1479 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
1480 ret = 0;
1481 }
1482 break;
1483 case DISABLE_KEY:
1484 ath_key_delete(common, key);
1485 break;
1486 default:
1487 ret = -EINVAL;
1488 }
1489
1490 ath9k_ps_restore(sc);
1491 mutex_unlock(&sc->mutex);
1492
1493 return ret;
1494 }
1495
1496 static void ath9k_set_assoc_state(struct ath_softc *sc,
1497 struct ieee80211_vif *vif)
1498 {
1499 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1500 struct ath_vif *avp = (void *)vif->drv_priv;
1501 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
1502 unsigned long flags;
1503
1504 set_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags);
1505 avp->primary_sta_vif = true;
1506
1507 /*
1508 * Set the AID, BSSID and do beacon-sync only when
1509 * the HW opmode is STATION.
1510 *
1511 * But the primary bit is set above in any case.
1512 */
1513 if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION)
1514 return;
1515
1516 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1517 common->curaid = bss_conf->aid;
1518 ath9k_hw_write_associd(sc->sc_ah);
1519
1520 sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
1521 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
1522
1523 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1524 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
1525 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1526
1527 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
1528 ath9k_mci_update_wlan_channels(sc, false);
1529
1530 ath_dbg(common, CONFIG,
1531 "Primary Station interface: %pM, BSSID: %pM\n",
1532 vif->addr, common->curbssid);
1533 }
1534
1535 static void ath9k_bss_assoc_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
1536 {
1537 struct ath_softc *sc = data;
1538 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
1539
1540 if (test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags))
1541 return;
1542
1543 if (bss_conf->assoc)
1544 ath9k_set_assoc_state(sc, vif);
1545 }
1546
1547 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
1548 struct ieee80211_vif *vif,
1549 struct ieee80211_bss_conf *bss_conf,
1550 u32 changed)
1551 {
1552 #define CHECK_ANI \
1553 (BSS_CHANGED_ASSOC | \
1554 BSS_CHANGED_IBSS | \
1555 BSS_CHANGED_BEACON_ENABLED)
1556
1557 struct ath_softc *sc = hw->priv;
1558 struct ath_hw *ah = sc->sc_ah;
1559 struct ath_common *common = ath9k_hw_common(ah);
1560 struct ath_vif *avp = (void *)vif->drv_priv;
1561 int slottime;
1562
1563 ath9k_ps_wakeup(sc);
1564 mutex_lock(&sc->mutex);
1565
1566 if (changed & BSS_CHANGED_ASSOC) {
1567 ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n",
1568 bss_conf->bssid, bss_conf->assoc);
1569
1570 if (avp->primary_sta_vif && !bss_conf->assoc) {
1571 clear_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags);
1572 avp->primary_sta_vif = false;
1573
1574 if (ah->opmode == NL80211_IFTYPE_STATION)
1575 clear_bit(SC_OP_BEACONS, &sc->sc_flags);
1576 }
1577
1578 ieee80211_iterate_active_interfaces_atomic(
1579 sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
1580 ath9k_bss_assoc_iter, sc);
1581
1582 if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags) &&
1583 ah->opmode == NL80211_IFTYPE_STATION) {
1584 memset(common->curbssid, 0, ETH_ALEN);
1585 common->curaid = 0;
1586 ath9k_hw_write_associd(sc->sc_ah);
1587 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
1588 ath9k_mci_update_wlan_channels(sc, true);
1589 }
1590 }
1591
1592 if (changed & BSS_CHANGED_IBSS) {
1593 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1594 common->curaid = bss_conf->aid;
1595 ath9k_hw_write_associd(sc->sc_ah);
1596 }
1597
1598 if ((changed & BSS_CHANGED_BEACON_ENABLED) ||
1599 (changed & BSS_CHANGED_BEACON_INT)) {
1600 if (ah->opmode == NL80211_IFTYPE_AP &&
1601 bss_conf->enable_beacon)
1602 ath9k_set_tsfadjust(sc, vif);
1603 if (ath9k_allow_beacon_config(sc, vif))
1604 ath9k_beacon_config(sc, vif, changed);
1605 }
1606
1607 if (changed & BSS_CHANGED_ERP_SLOT) {
1608 if (bss_conf->use_short_slot)
1609 slottime = 9;
1610 else
1611 slottime = 20;
1612 if (vif->type == NL80211_IFTYPE_AP) {
1613 /*
1614 * Defer update, so that connected stations can adjust
1615 * their settings at the same time.
1616 * See beacon.c for more details
1617 */
1618 sc->beacon.slottime = slottime;
1619 sc->beacon.updateslot = UPDATE;
1620 } else {
1621 ah->slottime = slottime;
1622 ath9k_hw_init_global_settings(ah);
1623 }
1624 }
1625
1626 if (changed & CHECK_ANI)
1627 ath_check_ani(sc);
1628
1629 mutex_unlock(&sc->mutex);
1630 ath9k_ps_restore(sc);
1631
1632 #undef CHECK_ANI
1633 }
1634
1635 static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1636 {
1637 struct ath_softc *sc = hw->priv;
1638 u64 tsf;
1639
1640 mutex_lock(&sc->mutex);
1641 ath9k_ps_wakeup(sc);
1642 tsf = ath9k_hw_gettsf64(sc->sc_ah);
1643 ath9k_ps_restore(sc);
1644 mutex_unlock(&sc->mutex);
1645
1646 return tsf;
1647 }
1648
1649 static void ath9k_set_tsf(struct ieee80211_hw *hw,
1650 struct ieee80211_vif *vif,
1651 u64 tsf)
1652 {
1653 struct ath_softc *sc = hw->priv;
1654
1655 mutex_lock(&sc->mutex);
1656 ath9k_ps_wakeup(sc);
1657 ath9k_hw_settsf64(sc->sc_ah, tsf);
1658 ath9k_ps_restore(sc);
1659 mutex_unlock(&sc->mutex);
1660 }
1661
1662 static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1663 {
1664 struct ath_softc *sc = hw->priv;
1665
1666 mutex_lock(&sc->mutex);
1667
1668 ath9k_ps_wakeup(sc);
1669 ath9k_hw_reset_tsf(sc->sc_ah);
1670 ath9k_ps_restore(sc);
1671
1672 mutex_unlock(&sc->mutex);
1673 }
1674
1675 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
1676 struct ieee80211_vif *vif,
1677 enum ieee80211_ampdu_mlme_action action,
1678 struct ieee80211_sta *sta,
1679 u16 tid, u16 *ssn, u8 buf_size)
1680 {
1681 struct ath_softc *sc = hw->priv;
1682 bool flush = false;
1683 int ret = 0;
1684
1685 mutex_lock(&sc->mutex);
1686
1687 switch (action) {
1688 case IEEE80211_AMPDU_RX_START:
1689 break;
1690 case IEEE80211_AMPDU_RX_STOP:
1691 break;
1692 case IEEE80211_AMPDU_TX_START:
1693 ath9k_ps_wakeup(sc);
1694 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
1695 if (!ret)
1696 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
1697 ath9k_ps_restore(sc);
1698 break;
1699 case IEEE80211_AMPDU_TX_STOP_FLUSH:
1700 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
1701 flush = true;
1702 case IEEE80211_AMPDU_TX_STOP_CONT:
1703 ath9k_ps_wakeup(sc);
1704 ath_tx_aggr_stop(sc, sta, tid);
1705 if (!flush)
1706 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
1707 ath9k_ps_restore(sc);
1708 break;
1709 case IEEE80211_AMPDU_TX_OPERATIONAL:
1710 ath9k_ps_wakeup(sc);
1711 ath_tx_aggr_resume(sc, sta, tid);
1712 ath9k_ps_restore(sc);
1713 break;
1714 default:
1715 ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
1716 }
1717
1718 mutex_unlock(&sc->mutex);
1719
1720 return ret;
1721 }
1722
1723 static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
1724 struct survey_info *survey)
1725 {
1726 struct ath_softc *sc = hw->priv;
1727 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1728 struct ieee80211_supported_band *sband;
1729 struct ieee80211_channel *chan;
1730 unsigned long flags;
1731 int pos;
1732
1733 spin_lock_irqsave(&common->cc_lock, flags);
1734 if (idx == 0)
1735 ath_update_survey_stats(sc);
1736
1737 sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
1738 if (sband && idx >= sband->n_channels) {
1739 idx -= sband->n_channels;
1740 sband = NULL;
1741 }
1742
1743 if (!sband)
1744 sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
1745
1746 if (!sband || idx >= sband->n_channels) {
1747 spin_unlock_irqrestore(&common->cc_lock, flags);
1748 return -ENOENT;
1749 }
1750
1751 chan = &sband->channels[idx];
1752 pos = chan->hw_value;
1753 memcpy(survey, &sc->survey[pos], sizeof(*survey));
1754 survey->channel = chan;
1755 spin_unlock_irqrestore(&common->cc_lock, flags);
1756
1757 return 0;
1758 }
1759
1760 static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
1761 {
1762 struct ath_softc *sc = hw->priv;
1763 struct ath_hw *ah = sc->sc_ah;
1764
1765 mutex_lock(&sc->mutex);
1766 ah->coverage_class = coverage_class;
1767
1768 ath9k_ps_wakeup(sc);
1769 ath9k_hw_init_global_settings(ah);
1770 ath9k_ps_restore(sc);
1771
1772 mutex_unlock(&sc->mutex);
1773 }
1774
1775 static void ath9k_flush(struct ieee80211_hw *hw, u32 queues, bool drop)
1776 {
1777 struct ath_softc *sc = hw->priv;
1778 struct ath_hw *ah = sc->sc_ah;
1779 struct ath_common *common = ath9k_hw_common(ah);
1780 int timeout = 200; /* ms */
1781 int i, j;
1782 bool drain_txq;
1783
1784 mutex_lock(&sc->mutex);
1785 cancel_delayed_work_sync(&sc->tx_complete_work);
1786
1787 if (ah->ah_flags & AH_UNPLUGGED) {
1788 ath_dbg(common, ANY, "Device has been unplugged!\n");
1789 mutex_unlock(&sc->mutex);
1790 return;
1791 }
1792
1793 if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
1794 ath_dbg(common, ANY, "Device not present\n");
1795 mutex_unlock(&sc->mutex);
1796 return;
1797 }
1798
1799 for (j = 0; j < timeout; j++) {
1800 bool npend = false;
1801
1802 if (j)
1803 usleep_range(1000, 2000);
1804
1805 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1806 if (!ATH_TXQ_SETUP(sc, i))
1807 continue;
1808
1809 npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]);
1810
1811 if (npend)
1812 break;
1813 }
1814
1815 if (!npend)
1816 break;
1817 }
1818
1819 if (drop) {
1820 ath9k_ps_wakeup(sc);
1821 spin_lock_bh(&sc->sc_pcu_lock);
1822 drain_txq = ath_drain_all_txq(sc);
1823 spin_unlock_bh(&sc->sc_pcu_lock);
1824
1825 if (!drain_txq)
1826 ath_reset(sc);
1827
1828 ath9k_ps_restore(sc);
1829 ieee80211_wake_queues(hw);
1830 }
1831
1832 ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0);
1833 mutex_unlock(&sc->mutex);
1834 }
1835
1836 static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
1837 {
1838 struct ath_softc *sc = hw->priv;
1839 int i;
1840
1841 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1842 if (!ATH_TXQ_SETUP(sc, i))
1843 continue;
1844
1845 if (ath9k_has_pending_frames(sc, &sc->tx.txq[i]))
1846 return true;
1847 }
1848 return false;
1849 }
1850
1851 static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
1852 {
1853 struct ath_softc *sc = hw->priv;
1854 struct ath_hw *ah = sc->sc_ah;
1855 struct ieee80211_vif *vif;
1856 struct ath_vif *avp;
1857 struct ath_buf *bf;
1858 struct ath_tx_status ts;
1859 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1860 int status;
1861
1862 vif = sc->beacon.bslot[0];
1863 if (!vif)
1864 return 0;
1865
1866 if (!vif->bss_conf.enable_beacon)
1867 return 0;
1868
1869 avp = (void *)vif->drv_priv;
1870
1871 if (!sc->beacon.tx_processed && !edma) {
1872 tasklet_disable(&sc->bcon_tasklet);
1873
1874 bf = avp->av_bcbuf;
1875 if (!bf || !bf->bf_mpdu)
1876 goto skip;
1877
1878 status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
1879 if (status == -EINPROGRESS)
1880 goto skip;
1881
1882 sc->beacon.tx_processed = true;
1883 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
1884
1885 skip:
1886 tasklet_enable(&sc->bcon_tasklet);
1887 }
1888
1889 return sc->beacon.tx_last;
1890 }
1891
1892 static int ath9k_get_stats(struct ieee80211_hw *hw,
1893 struct ieee80211_low_level_stats *stats)
1894 {
1895 struct ath_softc *sc = hw->priv;
1896 struct ath_hw *ah = sc->sc_ah;
1897 struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats;
1898
1899 stats->dot11ACKFailureCount = mib_stats->ackrcv_bad;
1900 stats->dot11RTSFailureCount = mib_stats->rts_bad;
1901 stats->dot11FCSErrorCount = mib_stats->fcs_bad;
1902 stats->dot11RTSSuccessCount = mib_stats->rts_good;
1903 return 0;
1904 }
1905
1906 static u32 fill_chainmask(u32 cap, u32 new)
1907 {
1908 u32 filled = 0;
1909 int i;
1910
1911 for (i = 0; cap && new; i++, cap >>= 1) {
1912 if (!(cap & BIT(0)))
1913 continue;
1914
1915 if (new & BIT(0))
1916 filled |= BIT(i);
1917
1918 new >>= 1;
1919 }
1920
1921 return filled;
1922 }
1923
1924 static bool validate_antenna_mask(struct ath_hw *ah, u32 val)
1925 {
1926 if (AR_SREV_9300_20_OR_LATER(ah))
1927 return true;
1928
1929 switch (val & 0x7) {
1930 case 0x1:
1931 case 0x3:
1932 case 0x7:
1933 return true;
1934 case 0x2:
1935 return (ah->caps.rx_chainmask == 1);
1936 default:
1937 return false;
1938 }
1939 }
1940
1941 static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
1942 {
1943 struct ath_softc *sc = hw->priv;
1944 struct ath_hw *ah = sc->sc_ah;
1945
1946 if (ah->caps.rx_chainmask != 1)
1947 rx_ant |= tx_ant;
1948
1949 if (!validate_antenna_mask(ah, rx_ant) || !tx_ant)
1950 return -EINVAL;
1951
1952 sc->ant_rx = rx_ant;
1953 sc->ant_tx = tx_ant;
1954
1955 if (ah->caps.rx_chainmask == 1)
1956 return 0;
1957
1958 /* AR9100 runs into calibration issues if not all rx chains are enabled */
1959 if (AR_SREV_9100(ah))
1960 ah->rxchainmask = 0x7;
1961 else
1962 ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant);
1963
1964 ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant);
1965 ath9k_reload_chainmask_settings(sc);
1966
1967 return 0;
1968 }
1969
1970 static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
1971 {
1972 struct ath_softc *sc = hw->priv;
1973
1974 *tx_ant = sc->ant_tx;
1975 *rx_ant = sc->ant_rx;
1976 return 0;
1977 }
1978
1979 #ifdef CONFIG_PM_SLEEP
1980
1981 static void ath9k_wow_map_triggers(struct ath_softc *sc,
1982 struct cfg80211_wowlan *wowlan,
1983 u32 *wow_triggers)
1984 {
1985 if (wowlan->disconnect)
1986 *wow_triggers |= AH_WOW_LINK_CHANGE |
1987 AH_WOW_BEACON_MISS;
1988 if (wowlan->magic_pkt)
1989 *wow_triggers |= AH_WOW_MAGIC_PATTERN_EN;
1990
1991 if (wowlan->n_patterns)
1992 *wow_triggers |= AH_WOW_USER_PATTERN_EN;
1993
1994 sc->wow_enabled = *wow_triggers;
1995
1996 }
1997
1998 static void ath9k_wow_add_disassoc_deauth_pattern(struct ath_softc *sc)
1999 {
2000 struct ath_hw *ah = sc->sc_ah;
2001 struct ath_common *common = ath9k_hw_common(ah);
2002 int pattern_count = 0;
2003 int i, byte_cnt;
2004 u8 dis_deauth_pattern[MAX_PATTERN_SIZE];
2005 u8 dis_deauth_mask[MAX_PATTERN_SIZE];
2006
2007 memset(dis_deauth_pattern, 0, MAX_PATTERN_SIZE);
2008 memset(dis_deauth_mask, 0, MAX_PATTERN_SIZE);
2009
2010 /*
2011 * Create Dissassociate / Deauthenticate packet filter
2012 *
2013 * 2 bytes 2 byte 6 bytes 6 bytes 6 bytes
2014 * +--------------+----------+---------+--------+--------+----
2015 * + Frame Control+ Duration + DA + SA + BSSID +
2016 * +--------------+----------+---------+--------+--------+----
2017 *
2018 * The above is the management frame format for disassociate/
2019 * deauthenticate pattern, from this we need to match the first byte
2020 * of 'Frame Control' and DA, SA, and BSSID fields
2021 * (skipping 2nd byte of FC and Duration feild.
2022 *
2023 * Disassociate pattern
2024 * --------------------
2025 * Frame control = 00 00 1010
2026 * DA, SA, BSSID = x:x:x:x:x:x
2027 * Pattern will be A0000000 | x:x:x:x:x:x | x:x:x:x:x:x
2028 * | x:x:x:x:x:x -- 22 bytes
2029 *
2030 * Deauthenticate pattern
2031 * ----------------------
2032 * Frame control = 00 00 1100
2033 * DA, SA, BSSID = x:x:x:x:x:x
2034 * Pattern will be C0000000 | x:x:x:x:x:x | x:x:x:x:x:x
2035 * | x:x:x:x:x:x -- 22 bytes
2036 */
2037
2038 /* Create Disassociate Pattern first */
2039
2040 byte_cnt = 0;
2041
2042 /* Fill out the mask with all FF's */
2043
2044 for (i = 0; i < MAX_PATTERN_MASK_SIZE; i++)
2045 dis_deauth_mask[i] = 0xff;
2046
2047 /* copy the first byte of frame control field */
2048 dis_deauth_pattern[byte_cnt] = 0xa0;
2049 byte_cnt++;
2050
2051 /* skip 2nd byte of frame control and Duration field */
2052 byte_cnt += 3;
2053
2054 /*
2055 * need not match the destination mac address, it can be a broadcast
2056 * mac address or an unicast to this station
2057 */
2058 byte_cnt += 6;
2059
2060 /* copy the source mac address */
2061 memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
2062
2063 byte_cnt += 6;
2064
2065 /* copy the bssid, its same as the source mac address */
2066
2067 memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
2068
2069 /* Create Disassociate pattern mask */
2070
2071 dis_deauth_mask[0] = 0xfe;
2072 dis_deauth_mask[1] = 0x03;
2073 dis_deauth_mask[2] = 0xc0;
2074
2075 ath_dbg(common, WOW, "Adding disassoc/deauth patterns for WoW\n");
2076
2077 ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
2078 pattern_count, byte_cnt);
2079
2080 pattern_count++;
2081 /*
2082 * for de-authenticate pattern, only the first byte of the frame
2083 * control field gets changed from 0xA0 to 0xC0
2084 */
2085 dis_deauth_pattern[0] = 0xC0;
2086
2087 ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
2088 pattern_count, byte_cnt);
2089
2090 }
2091
2092 static void ath9k_wow_add_pattern(struct ath_softc *sc,
2093 struct cfg80211_wowlan *wowlan)
2094 {
2095 struct ath_hw *ah = sc->sc_ah;
2096 struct ath9k_wow_pattern *wow_pattern = NULL;
2097 struct cfg80211_wowlan_trig_pkt_pattern *patterns = wowlan->patterns;
2098 int mask_len;
2099 s8 i = 0;
2100
2101 if (!wowlan->n_patterns)
2102 return;
2103
2104 /*
2105 * Add the new user configured patterns
2106 */
2107 for (i = 0; i < wowlan->n_patterns; i++) {
2108
2109 wow_pattern = kzalloc(sizeof(*wow_pattern), GFP_KERNEL);
2110
2111 if (!wow_pattern)
2112 return;
2113
2114 /*
2115 * TODO: convert the generic user space pattern to
2116 * appropriate chip specific/802.11 pattern.
2117 */
2118
2119 mask_len = DIV_ROUND_UP(wowlan->patterns[i].pattern_len, 8);
2120 memset(wow_pattern->pattern_bytes, 0, MAX_PATTERN_SIZE);
2121 memset(wow_pattern->mask_bytes, 0, MAX_PATTERN_SIZE);
2122 memcpy(wow_pattern->pattern_bytes, patterns[i].pattern,
2123 patterns[i].pattern_len);
2124 memcpy(wow_pattern->mask_bytes, patterns[i].mask, mask_len);
2125 wow_pattern->pattern_len = patterns[i].pattern_len;
2126
2127 /*
2128 * just need to take care of deauth and disssoc pattern,
2129 * make sure we don't overwrite them.
2130 */
2131
2132 ath9k_hw_wow_apply_pattern(ah, wow_pattern->pattern_bytes,
2133 wow_pattern->mask_bytes,
2134 i + 2,
2135 wow_pattern->pattern_len);
2136 kfree(wow_pattern);
2137
2138 }
2139
2140 }
2141
2142 static int ath9k_suspend(struct ieee80211_hw *hw,
2143 struct cfg80211_wowlan *wowlan)
2144 {
2145 struct ath_softc *sc = hw->priv;
2146 struct ath_hw *ah = sc->sc_ah;
2147 struct ath_common *common = ath9k_hw_common(ah);
2148 u32 wow_triggers_enabled = 0;
2149 int ret = 0;
2150
2151 mutex_lock(&sc->mutex);
2152
2153 ath_cancel_work(sc);
2154 ath_stop_ani(sc);
2155 del_timer_sync(&sc->rx_poll_timer);
2156
2157 if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
2158 ath_dbg(common, ANY, "Device not present\n");
2159 ret = -EINVAL;
2160 goto fail_wow;
2161 }
2162
2163 if (WARN_ON(!wowlan)) {
2164 ath_dbg(common, WOW, "None of the WoW triggers enabled\n");
2165 ret = -EINVAL;
2166 goto fail_wow;
2167 }
2168
2169 if (!device_can_wakeup(sc->dev)) {
2170 ath_dbg(common, WOW, "device_can_wakeup failed, WoW is not enabled\n");
2171 ret = 1;
2172 goto fail_wow;
2173 }
2174
2175 /*
2176 * none of the sta vifs are associated
2177 * and we are not currently handling multivif
2178 * cases, for instance we have to seperately
2179 * configure 'keep alive frame' for each
2180 * STA.
2181 */
2182
2183 if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
2184 ath_dbg(common, WOW, "None of the STA vifs are associated\n");
2185 ret = 1;
2186 goto fail_wow;
2187 }
2188
2189 if (sc->nvifs > 1) {
2190 ath_dbg(common, WOW, "WoW for multivif is not yet supported\n");
2191 ret = 1;
2192 goto fail_wow;
2193 }
2194
2195 ath9k_wow_map_triggers(sc, wowlan, &wow_triggers_enabled);
2196
2197 ath_dbg(common, WOW, "WoW triggers enabled 0x%x\n",
2198 wow_triggers_enabled);
2199
2200 ath9k_ps_wakeup(sc);
2201
2202 ath9k_stop_btcoex(sc);
2203
2204 /*
2205 * Enable wake up on recieving disassoc/deauth
2206 * frame by default.
2207 */
2208 ath9k_wow_add_disassoc_deauth_pattern(sc);
2209
2210 if (wow_triggers_enabled & AH_WOW_USER_PATTERN_EN)
2211 ath9k_wow_add_pattern(sc, wowlan);
2212
2213 spin_lock_bh(&sc->sc_pcu_lock);
2214 /*
2215 * To avoid false wake, we enable beacon miss interrupt only
2216 * when we go to sleep. We save the current interrupt mask
2217 * so we can restore it after the system wakes up
2218 */
2219 sc->wow_intr_before_sleep = ah->imask;
2220 ah->imask &= ~ATH9K_INT_GLOBAL;
2221 ath9k_hw_disable_interrupts(ah);
2222 ah->imask = ATH9K_INT_BMISS | ATH9K_INT_GLOBAL;
2223 ath9k_hw_set_interrupts(ah);
2224 ath9k_hw_enable_interrupts(ah);
2225
2226 spin_unlock_bh(&sc->sc_pcu_lock);
2227
2228 /*
2229 * we can now sync irq and kill any running tasklets, since we already
2230 * disabled interrupts and not holding a spin lock
2231 */
2232 synchronize_irq(sc->irq);
2233 tasklet_kill(&sc->intr_tq);
2234
2235 ath9k_hw_wow_enable(ah, wow_triggers_enabled);
2236
2237 ath9k_ps_restore(sc);
2238 ath_dbg(common, ANY, "WoW enabled in ath9k\n");
2239 atomic_inc(&sc->wow_sleep_proc_intr);
2240
2241 fail_wow:
2242 mutex_unlock(&sc->mutex);
2243 return ret;
2244 }
2245
2246 static int ath9k_resume(struct ieee80211_hw *hw)
2247 {
2248 struct ath_softc *sc = hw->priv;
2249 struct ath_hw *ah = sc->sc_ah;
2250 struct ath_common *common = ath9k_hw_common(ah);
2251 u32 wow_status;
2252
2253 mutex_lock(&sc->mutex);
2254
2255 ath9k_ps_wakeup(sc);
2256
2257 spin_lock_bh(&sc->sc_pcu_lock);
2258
2259 ath9k_hw_disable_interrupts(ah);
2260 ah->imask = sc->wow_intr_before_sleep;
2261 ath9k_hw_set_interrupts(ah);
2262 ath9k_hw_enable_interrupts(ah);
2263
2264 spin_unlock_bh(&sc->sc_pcu_lock);
2265
2266 wow_status = ath9k_hw_wow_wakeup(ah);
2267
2268 if (atomic_read(&sc->wow_got_bmiss_intr) == 0) {
2269 /*
2270 * some devices may not pick beacon miss
2271 * as the reason they woke up so we add
2272 * that here for that shortcoming.
2273 */
2274 wow_status |= AH_WOW_BEACON_MISS;
2275 atomic_dec(&sc->wow_got_bmiss_intr);
2276 ath_dbg(common, ANY, "Beacon miss interrupt picked up during WoW sleep\n");
2277 }
2278
2279 atomic_dec(&sc->wow_sleep_proc_intr);
2280
2281 if (wow_status) {
2282 ath_dbg(common, ANY, "Waking up due to WoW triggers %s with WoW status = %x\n",
2283 ath9k_hw_wow_event_to_string(wow_status), wow_status);
2284 }
2285
2286 ath_restart_work(sc);
2287 ath9k_start_btcoex(sc);
2288
2289 ath9k_ps_restore(sc);
2290 mutex_unlock(&sc->mutex);
2291
2292 return 0;
2293 }
2294
2295 static void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled)
2296 {
2297 struct ath_softc *sc = hw->priv;
2298
2299 mutex_lock(&sc->mutex);
2300 device_init_wakeup(sc->dev, 1);
2301 device_set_wakeup_enable(sc->dev, enabled);
2302 mutex_unlock(&sc->mutex);
2303 }
2304
2305 #endif
2306 static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
2307 {
2308 struct ath_softc *sc = hw->priv;
2309 set_bit(SC_OP_SCANNING, &sc->sc_flags);
2310 }
2311
2312 static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
2313 {
2314 struct ath_softc *sc = hw->priv;
2315 clear_bit(SC_OP_SCANNING, &sc->sc_flags);
2316 }
2317
2318 struct ieee80211_ops ath9k_ops = {
2319 .tx = ath9k_tx,
2320 .start = ath9k_start,
2321 .stop = ath9k_stop,
2322 .add_interface = ath9k_add_interface,
2323 .change_interface = ath9k_change_interface,
2324 .remove_interface = ath9k_remove_interface,
2325 .config = ath9k_config,
2326 .configure_filter = ath9k_configure_filter,
2327 .sta_add = ath9k_sta_add,
2328 .sta_remove = ath9k_sta_remove,
2329 .sta_notify = ath9k_sta_notify,
2330 .conf_tx = ath9k_conf_tx,
2331 .bss_info_changed = ath9k_bss_info_changed,
2332 .set_key = ath9k_set_key,
2333 .get_tsf = ath9k_get_tsf,
2334 .set_tsf = ath9k_set_tsf,
2335 .reset_tsf = ath9k_reset_tsf,
2336 .ampdu_action = ath9k_ampdu_action,
2337 .get_survey = ath9k_get_survey,
2338 .rfkill_poll = ath9k_rfkill_poll_state,
2339 .set_coverage_class = ath9k_set_coverage_class,
2340 .flush = ath9k_flush,
2341 .tx_frames_pending = ath9k_tx_frames_pending,
2342 .tx_last_beacon = ath9k_tx_last_beacon,
2343 .release_buffered_frames = ath9k_release_buffered_frames,
2344 .get_stats = ath9k_get_stats,
2345 .set_antenna = ath9k_set_antenna,
2346 .get_antenna = ath9k_get_antenna,
2347
2348 #ifdef CONFIG_PM_SLEEP
2349 .suspend = ath9k_suspend,
2350 .resume = ath9k_resume,
2351 .set_wakeup = ath9k_set_wakeup,
2352 #endif
2353
2354 #ifdef CONFIG_ATH9K_DEBUGFS
2355 .get_et_sset_count = ath9k_get_et_sset_count,
2356 .get_et_stats = ath9k_get_et_stats,
2357 .get_et_strings = ath9k_get_et_strings,
2358 #endif
2359
2360 #if defined(CONFIG_MAC80211_DEBUGFS) && defined(CONFIG_ATH9K_DEBUGFS)
2361 .sta_add_debugfs = ath9k_sta_add_debugfs,
2362 .sta_remove_debugfs = ath9k_sta_remove_debugfs,
2363 #endif
2364 .sw_scan_start = ath9k_sw_scan_start,
2365 .sw_scan_complete = ath9k_sw_scan_complete,
2366 };
Linux kernel - Deliverables
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