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sg_start_req(): use import_iovec()
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / main.c
1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/nl80211.h>
18 #include <linux/delay.h>
19 #include "ath9k.h"
20 #include "btcoex.h"
21
22 u8 ath9k_parse_mpdudensity(u8 mpdudensity)
23 {
24 /*
25 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
26 * 0 for no restriction
27 * 1 for 1/4 us
28 * 2 for 1/2 us
29 * 3 for 1 us
30 * 4 for 2 us
31 * 5 for 4 us
32 * 6 for 8 us
33 * 7 for 16 us
34 */
35 switch (mpdudensity) {
36 case 0:
37 return 0;
38 case 1:
39 case 2:
40 case 3:
41 /* Our lower layer calculations limit our precision to
42 1 microsecond */
43 return 1;
44 case 4:
45 return 2;
46 case 5:
47 return 4;
48 case 6:
49 return 8;
50 case 7:
51 return 16;
52 default:
53 return 0;
54 }
55 }
56
57 static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq,
58 bool sw_pending)
59 {
60 bool pending = false;
61
62 spin_lock_bh(&txq->axq_lock);
63
64 if (txq->axq_depth) {
65 pending = true;
66 goto out;
67 }
68
69 if (!sw_pending)
70 goto out;
71
72 if (txq->mac80211_qnum >= 0) {
73 struct list_head *list;
74
75 list = &sc->cur_chan->acq[txq->mac80211_qnum];
76 if (!list_empty(list))
77 pending = true;
78 }
79 out:
80 spin_unlock_bh(&txq->axq_lock);
81 return pending;
82 }
83
84 static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
85 {
86 unsigned long flags;
87 bool ret;
88
89 spin_lock_irqsave(&sc->sc_pm_lock, flags);
90 ret = ath9k_hw_setpower(sc->sc_ah, mode);
91 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
92
93 return ret;
94 }
95
96 void ath_ps_full_sleep(unsigned long data)
97 {
98 struct ath_softc *sc = (struct ath_softc *) data;
99 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
100 bool reset;
101
102 spin_lock(&common->cc_lock);
103 ath_hw_cycle_counters_update(common);
104 spin_unlock(&common->cc_lock);
105
106 ath9k_hw_setrxabort(sc->sc_ah, 1);
107 ath9k_hw_stopdmarecv(sc->sc_ah, &reset);
108
109 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
110 }
111
112 void ath9k_ps_wakeup(struct ath_softc *sc)
113 {
114 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
115 unsigned long flags;
116 enum ath9k_power_mode power_mode;
117
118 spin_lock_irqsave(&sc->sc_pm_lock, flags);
119 if (++sc->ps_usecount != 1)
120 goto unlock;
121
122 del_timer_sync(&sc->sleep_timer);
123 power_mode = sc->sc_ah->power_mode;
124 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
125
126 /*
127 * While the hardware is asleep, the cycle counters contain no
128 * useful data. Better clear them now so that they don't mess up
129 * survey data results.
130 */
131 if (power_mode != ATH9K_PM_AWAKE) {
132 spin_lock(&common->cc_lock);
133 ath_hw_cycle_counters_update(common);
134 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
135 memset(&common->cc_ani, 0, sizeof(common->cc_ani));
136 spin_unlock(&common->cc_lock);
137 }
138
139 unlock:
140 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
141 }
142
143 void ath9k_ps_restore(struct ath_softc *sc)
144 {
145 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
146 enum ath9k_power_mode mode;
147 unsigned long flags;
148
149 spin_lock_irqsave(&sc->sc_pm_lock, flags);
150 if (--sc->ps_usecount != 0)
151 goto unlock;
152
153 if (sc->ps_idle) {
154 mod_timer(&sc->sleep_timer, jiffies + HZ / 10);
155 goto unlock;
156 }
157
158 if (sc->ps_enabled &&
159 !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
160 PS_WAIT_FOR_CAB |
161 PS_WAIT_FOR_PSPOLL_DATA |
162 PS_WAIT_FOR_TX_ACK |
163 PS_WAIT_FOR_ANI))) {
164 mode = ATH9K_PM_NETWORK_SLEEP;
165 if (ath9k_hw_btcoex_is_enabled(sc->sc_ah))
166 ath9k_btcoex_stop_gen_timer(sc);
167 } else {
168 goto unlock;
169 }
170
171 spin_lock(&common->cc_lock);
172 ath_hw_cycle_counters_update(common);
173 spin_unlock(&common->cc_lock);
174
175 ath9k_hw_setpower(sc->sc_ah, mode);
176
177 unlock:
178 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
179 }
180
181 static void __ath_cancel_work(struct ath_softc *sc)
182 {
183 cancel_work_sync(&sc->paprd_work);
184 cancel_delayed_work_sync(&sc->tx_complete_work);
185 cancel_delayed_work_sync(&sc->hw_pll_work);
186
187 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
188 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
189 cancel_work_sync(&sc->mci_work);
190 #endif
191 }
192
193 void ath_cancel_work(struct ath_softc *sc)
194 {
195 __ath_cancel_work(sc);
196 cancel_work_sync(&sc->hw_reset_work);
197 }
198
199 void ath_restart_work(struct ath_softc *sc)
200 {
201 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
202
203 if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9330(sc->sc_ah))
204 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work,
205 msecs_to_jiffies(ATH_PLL_WORK_INTERVAL));
206
207 ath_start_ani(sc);
208 }
209
210 static bool ath_prepare_reset(struct ath_softc *sc)
211 {
212 struct ath_hw *ah = sc->sc_ah;
213 bool ret = true;
214
215 ieee80211_stop_queues(sc->hw);
216 ath_stop_ani(sc);
217 ath9k_hw_disable_interrupts(ah);
218
219 if (!ath_drain_all_txq(sc))
220 ret = false;
221
222 if (!ath_stoprecv(sc))
223 ret = false;
224
225 return ret;
226 }
227
228 static bool ath_complete_reset(struct ath_softc *sc, bool start)
229 {
230 struct ath_hw *ah = sc->sc_ah;
231 struct ath_common *common = ath9k_hw_common(ah);
232 unsigned long flags;
233
234 ath9k_calculate_summary_state(sc, sc->cur_chan);
235 ath_startrecv(sc);
236 ath9k_cmn_update_txpow(ah, sc->cur_chan->cur_txpower,
237 sc->cur_chan->txpower,
238 &sc->cur_chan->cur_txpower);
239 clear_bit(ATH_OP_HW_RESET, &common->op_flags);
240
241 if (!sc->cur_chan->offchannel && start) {
242 /* restore per chanctx TSF timer */
243 if (sc->cur_chan->tsf_val) {
244 u32 offset;
245
246 offset = ath9k_hw_get_tsf_offset(&sc->cur_chan->tsf_ts,
247 NULL);
248 ath9k_hw_settsf64(ah, sc->cur_chan->tsf_val + offset);
249 }
250
251
252 if (!test_bit(ATH_OP_BEACONS, &common->op_flags))
253 goto work;
254
255 if (ah->opmode == NL80211_IFTYPE_STATION &&
256 test_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags)) {
257 spin_lock_irqsave(&sc->sc_pm_lock, flags);
258 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
259 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
260 } else {
261 ath9k_set_beacon(sc);
262 }
263 work:
264 ath_restart_work(sc);
265 ath_txq_schedule_all(sc);
266 }
267
268 sc->gtt_cnt = 0;
269
270 ath9k_hw_set_interrupts(ah);
271 ath9k_hw_enable_interrupts(ah);
272 ieee80211_wake_queues(sc->hw);
273 ath9k_p2p_ps_timer(sc);
274
275 return true;
276 }
277
278 static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan)
279 {
280 struct ath_hw *ah = sc->sc_ah;
281 struct ath_common *common = ath9k_hw_common(ah);
282 struct ath9k_hw_cal_data *caldata = NULL;
283 bool fastcc = true;
284 int r;
285
286 __ath_cancel_work(sc);
287
288 disable_irq(sc->irq);
289 tasklet_disable(&sc->intr_tq);
290 tasklet_disable(&sc->bcon_tasklet);
291 spin_lock_bh(&sc->sc_pcu_lock);
292
293 if (!sc->cur_chan->offchannel) {
294 fastcc = false;
295 caldata = &sc->cur_chan->caldata;
296 }
297
298 if (!hchan) {
299 fastcc = false;
300 hchan = ah->curchan;
301 }
302
303 if (!ath_prepare_reset(sc))
304 fastcc = false;
305
306 if (ath9k_is_chanctx_enabled())
307 fastcc = false;
308
309 spin_lock_bh(&sc->chan_lock);
310 sc->cur_chandef = sc->cur_chan->chandef;
311 spin_unlock_bh(&sc->chan_lock);
312
313 ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n",
314 hchan->channel, IS_CHAN_HT40(hchan), fastcc);
315
316 r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
317 if (r) {
318 ath_err(common,
319 "Unable to reset channel, reset status %d\n", r);
320
321 ath9k_hw_enable_interrupts(ah);
322 ath9k_queue_reset(sc, RESET_TYPE_BB_HANG);
323
324 goto out;
325 }
326
327 if (ath9k_hw_mci_is_enabled(sc->sc_ah) &&
328 sc->cur_chan->offchannel)
329 ath9k_mci_set_txpower(sc, true, false);
330
331 if (!ath_complete_reset(sc, true))
332 r = -EIO;
333
334 out:
335 enable_irq(sc->irq);
336 spin_unlock_bh(&sc->sc_pcu_lock);
337 tasklet_enable(&sc->bcon_tasklet);
338 tasklet_enable(&sc->intr_tq);
339
340 return r;
341 }
342
343 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
344 struct ieee80211_vif *vif)
345 {
346 struct ath_node *an;
347 an = (struct ath_node *)sta->drv_priv;
348
349 an->sc = sc;
350 an->sta = sta;
351 an->vif = vif;
352 memset(&an->key_idx, 0, sizeof(an->key_idx));
353
354 ath_tx_node_init(sc, an);
355
356 ath_dynack_node_init(sc->sc_ah, an);
357 }
358
359 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
360 {
361 struct ath_node *an = (struct ath_node *)sta->drv_priv;
362 ath_tx_node_cleanup(sc, an);
363
364 ath_dynack_node_deinit(sc->sc_ah, an);
365 }
366
367 void ath9k_tasklet(unsigned long data)
368 {
369 struct ath_softc *sc = (struct ath_softc *)data;
370 struct ath_hw *ah = sc->sc_ah;
371 struct ath_common *common = ath9k_hw_common(ah);
372 enum ath_reset_type type;
373 unsigned long flags;
374 u32 status = sc->intrstatus;
375 u32 rxmask;
376
377 ath9k_ps_wakeup(sc);
378 spin_lock(&sc->sc_pcu_lock);
379
380 if (status & ATH9K_INT_FATAL) {
381 type = RESET_TYPE_FATAL_INT;
382 ath9k_queue_reset(sc, type);
383
384 /*
385 * Increment the ref. counter here so that
386 * interrupts are enabled in the reset routine.
387 */
388 atomic_inc(&ah->intr_ref_cnt);
389 ath_dbg(common, RESET, "FATAL: Skipping interrupts\n");
390 goto out;
391 }
392
393 if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) &&
394 (status & ATH9K_INT_BB_WATCHDOG)) {
395 spin_lock(&common->cc_lock);
396 ath_hw_cycle_counters_update(common);
397 ar9003_hw_bb_watchdog_dbg_info(ah);
398 spin_unlock(&common->cc_lock);
399
400 if (ar9003_hw_bb_watchdog_check(ah)) {
401 type = RESET_TYPE_BB_WATCHDOG;
402 ath9k_queue_reset(sc, type);
403
404 /*
405 * Increment the ref. counter here so that
406 * interrupts are enabled in the reset routine.
407 */
408 atomic_inc(&ah->intr_ref_cnt);
409 ath_dbg(common, RESET,
410 "BB_WATCHDOG: Skipping interrupts\n");
411 goto out;
412 }
413 }
414
415 if (status & ATH9K_INT_GTT) {
416 sc->gtt_cnt++;
417
418 if ((sc->gtt_cnt >= MAX_GTT_CNT) && !ath9k_hw_check_alive(ah)) {
419 type = RESET_TYPE_TX_GTT;
420 ath9k_queue_reset(sc, type);
421 atomic_inc(&ah->intr_ref_cnt);
422 ath_dbg(common, RESET,
423 "GTT: Skipping interrupts\n");
424 goto out;
425 }
426 }
427
428 spin_lock_irqsave(&sc->sc_pm_lock, flags);
429 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
430 /*
431 * TSF sync does not look correct; remain awake to sync with
432 * the next Beacon.
433 */
434 ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n");
435 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
436 }
437 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
438
439 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
440 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
441 ATH9K_INT_RXORN);
442 else
443 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
444
445 if (status & rxmask) {
446 /* Check for high priority Rx first */
447 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
448 (status & ATH9K_INT_RXHP))
449 ath_rx_tasklet(sc, 0, true);
450
451 ath_rx_tasklet(sc, 0, false);
452 }
453
454 if (status & ATH9K_INT_TX) {
455 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
456 /*
457 * For EDMA chips, TX completion is enabled for the
458 * beacon queue, so if a beacon has been transmitted
459 * successfully after a GTT interrupt, the GTT counter
460 * gets reset to zero here.
461 */
462 sc->gtt_cnt = 0;
463
464 ath_tx_edma_tasklet(sc);
465 } else {
466 ath_tx_tasklet(sc);
467 }
468
469 wake_up(&sc->tx_wait);
470 }
471
472 if (status & ATH9K_INT_GENTIMER)
473 ath_gen_timer_isr(sc->sc_ah);
474
475 ath9k_btcoex_handle_interrupt(sc, status);
476
477 /* re-enable hardware interrupt */
478 ath9k_hw_enable_interrupts(ah);
479 out:
480 spin_unlock(&sc->sc_pcu_lock);
481 ath9k_ps_restore(sc);
482 }
483
484 irqreturn_t ath_isr(int irq, void *dev)
485 {
486 #define SCHED_INTR ( \
487 ATH9K_INT_FATAL | \
488 ATH9K_INT_BB_WATCHDOG | \
489 ATH9K_INT_RXORN | \
490 ATH9K_INT_RXEOL | \
491 ATH9K_INT_RX | \
492 ATH9K_INT_RXLP | \
493 ATH9K_INT_RXHP | \
494 ATH9K_INT_TX | \
495 ATH9K_INT_BMISS | \
496 ATH9K_INT_CST | \
497 ATH9K_INT_GTT | \
498 ATH9K_INT_TSFOOR | \
499 ATH9K_INT_GENTIMER | \
500 ATH9K_INT_MCI)
501
502 struct ath_softc *sc = dev;
503 struct ath_hw *ah = sc->sc_ah;
504 struct ath_common *common = ath9k_hw_common(ah);
505 enum ath9k_int status;
506 u32 sync_cause = 0;
507 bool sched = false;
508
509 /*
510 * The hardware is not ready/present, don't
511 * touch anything. Note this can happen early
512 * on if the IRQ is shared.
513 */
514 if (!ah || test_bit(ATH_OP_INVALID, &common->op_flags))
515 return IRQ_NONE;
516
517 /* shared irq, not for us */
518 if (!ath9k_hw_intrpend(ah))
519 return IRQ_NONE;
520
521 /*
522 * Figure out the reason(s) for the interrupt. Note
523 * that the hal returns a pseudo-ISR that may include
524 * bits we haven't explicitly enabled so we mask the
525 * value to insure we only process bits we requested.
526 */
527 ath9k_hw_getisr(ah, &status, &sync_cause); /* NB: clears ISR too */
528 ath9k_debug_sync_cause(sc, sync_cause);
529 status &= ah->imask; /* discard unasked-for bits */
530
531 if (test_bit(ATH_OP_HW_RESET, &common->op_flags))
532 return IRQ_HANDLED;
533
534 /*
535 * If there are no status bits set, then this interrupt was not
536 * for me (should have been caught above).
537 */
538 if (!status)
539 return IRQ_NONE;
540
541 /* Cache the status */
542 sc->intrstatus = status;
543
544 if (status & SCHED_INTR)
545 sched = true;
546
547 /*
548 * If a FATAL interrupt is received, we have to reset the chip
549 * immediately.
550 */
551 if (status & ATH9K_INT_FATAL)
552 goto chip_reset;
553
554 if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) &&
555 (status & ATH9K_INT_BB_WATCHDOG))
556 goto chip_reset;
557
558 if (status & ATH9K_INT_SWBA)
559 tasklet_schedule(&sc->bcon_tasklet);
560
561 if (status & ATH9K_INT_TXURN)
562 ath9k_hw_updatetxtriglevel(ah, true);
563
564 if (status & ATH9K_INT_RXEOL) {
565 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
566 ath9k_hw_set_interrupts(ah);
567 }
568
569 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
570 if (status & ATH9K_INT_TIM_TIMER) {
571 if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
572 goto chip_reset;
573 /* Clear RxAbort bit so that we can
574 * receive frames */
575 ath9k_setpower(sc, ATH9K_PM_AWAKE);
576 spin_lock(&sc->sc_pm_lock);
577 ath9k_hw_setrxabort(sc->sc_ah, 0);
578 sc->ps_flags |= PS_WAIT_FOR_BEACON;
579 spin_unlock(&sc->sc_pm_lock);
580 }
581
582 chip_reset:
583
584 ath_debug_stat_interrupt(sc, status);
585
586 if (sched) {
587 /* turn off every interrupt */
588 ath9k_hw_disable_interrupts(ah);
589 tasklet_schedule(&sc->intr_tq);
590 }
591
592 return IRQ_HANDLED;
593
594 #undef SCHED_INTR
595 }
596
597 /*
598 * This function is called when a HW reset cannot be deferred
599 * and has to be immediate.
600 */
601 int ath_reset(struct ath_softc *sc, struct ath9k_channel *hchan)
602 {
603 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
604 int r;
605
606 ath9k_hw_kill_interrupts(sc->sc_ah);
607 set_bit(ATH_OP_HW_RESET, &common->op_flags);
608
609 ath9k_ps_wakeup(sc);
610 r = ath_reset_internal(sc, hchan);
611 ath9k_ps_restore(sc);
612
613 return r;
614 }
615
616 /*
617 * When a HW reset can be deferred, it is added to the
618 * hw_reset_work workqueue, but we set ATH_OP_HW_RESET before
619 * queueing.
620 */
621 void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type)
622 {
623 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
624 #ifdef CONFIG_ATH9K_DEBUGFS
625 RESET_STAT_INC(sc, type);
626 #endif
627 ath9k_hw_kill_interrupts(sc->sc_ah);
628 set_bit(ATH_OP_HW_RESET, &common->op_flags);
629 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
630 }
631
632 void ath_reset_work(struct work_struct *work)
633 {
634 struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work);
635
636 ath9k_ps_wakeup(sc);
637 ath_reset_internal(sc, NULL);
638 ath9k_ps_restore(sc);
639 }
640
641 /**********************/
642 /* mac80211 callbacks */
643 /**********************/
644
645 static int ath9k_start(struct ieee80211_hw *hw)
646 {
647 struct ath_softc *sc = hw->priv;
648 struct ath_hw *ah = sc->sc_ah;
649 struct ath_common *common = ath9k_hw_common(ah);
650 struct ieee80211_channel *curchan = sc->cur_chan->chandef.chan;
651 struct ath_chanctx *ctx = sc->cur_chan;
652 struct ath9k_channel *init_channel;
653 int r;
654
655 ath_dbg(common, CONFIG,
656 "Starting driver with initial channel: %d MHz\n",
657 curchan->center_freq);
658
659 ath9k_ps_wakeup(sc);
660 mutex_lock(&sc->mutex);
661
662 init_channel = ath9k_cmn_get_channel(hw, ah, &ctx->chandef);
663 sc->cur_chandef = hw->conf.chandef;
664
665 /* Reset SERDES registers */
666 ath9k_hw_configpcipowersave(ah, false);
667
668 /*
669 * The basic interface to setting the hardware in a good
670 * state is ``reset''. On return the hardware is known to
671 * be powered up and with interrupts disabled. This must
672 * be followed by initialization of the appropriate bits
673 * and then setup of the interrupt mask.
674 */
675 spin_lock_bh(&sc->sc_pcu_lock);
676
677 atomic_set(&ah->intr_ref_cnt, -1);
678
679 r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
680 if (r) {
681 ath_err(common,
682 "Unable to reset hardware; reset status %d (freq %u MHz)\n",
683 r, curchan->center_freq);
684 ah->reset_power_on = false;
685 }
686
687 /* Setup our intr mask. */
688 ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
689 ATH9K_INT_RXORN | ATH9K_INT_FATAL |
690 ATH9K_INT_GLOBAL;
691
692 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
693 ah->imask |= ATH9K_INT_RXHP |
694 ATH9K_INT_RXLP;
695 else
696 ah->imask |= ATH9K_INT_RX;
697
698 if (ah->config.hw_hang_checks & HW_BB_WATCHDOG)
699 ah->imask |= ATH9K_INT_BB_WATCHDOG;
700
701 /*
702 * Enable GTT interrupts only for AR9003/AR9004 chips
703 * for now.
704 */
705 if (AR_SREV_9300_20_OR_LATER(ah))
706 ah->imask |= ATH9K_INT_GTT;
707
708 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
709 ah->imask |= ATH9K_INT_CST;
710
711 ath_mci_enable(sc);
712
713 clear_bit(ATH_OP_INVALID, &common->op_flags);
714 sc->sc_ah->is_monitoring = false;
715
716 if (!ath_complete_reset(sc, false))
717 ah->reset_power_on = false;
718
719 if (ah->led_pin >= 0) {
720 ath9k_hw_cfg_output(ah, ah->led_pin,
721 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
722 ath9k_hw_set_gpio(ah, ah->led_pin,
723 (ah->config.led_active_high) ? 1 : 0);
724 }
725
726 /*
727 * Reset key cache to sane defaults (all entries cleared) instead of
728 * semi-random values after suspend/resume.
729 */
730 ath9k_cmn_init_crypto(sc->sc_ah);
731
732 ath9k_hw_reset_tsf(ah);
733
734 spin_unlock_bh(&sc->sc_pcu_lock);
735
736 mutex_unlock(&sc->mutex);
737
738 ath9k_ps_restore(sc);
739
740 return 0;
741 }
742
743 static void ath9k_tx(struct ieee80211_hw *hw,
744 struct ieee80211_tx_control *control,
745 struct sk_buff *skb)
746 {
747 struct ath_softc *sc = hw->priv;
748 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
749 struct ath_tx_control txctl;
750 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
751 unsigned long flags;
752
753 if (sc->ps_enabled) {
754 /*
755 * mac80211 does not set PM field for normal data frames, so we
756 * need to update that based on the current PS mode.
757 */
758 if (ieee80211_is_data(hdr->frame_control) &&
759 !ieee80211_is_nullfunc(hdr->frame_control) &&
760 !ieee80211_has_pm(hdr->frame_control)) {
761 ath_dbg(common, PS,
762 "Add PM=1 for a TX frame while in PS mode\n");
763 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
764 }
765 }
766
767 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) {
768 /*
769 * We are using PS-Poll and mac80211 can request TX while in
770 * power save mode. Need to wake up hardware for the TX to be
771 * completed and if needed, also for RX of buffered frames.
772 */
773 ath9k_ps_wakeup(sc);
774 spin_lock_irqsave(&sc->sc_pm_lock, flags);
775 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
776 ath9k_hw_setrxabort(sc->sc_ah, 0);
777 if (ieee80211_is_pspoll(hdr->frame_control)) {
778 ath_dbg(common, PS,
779 "Sending PS-Poll to pick a buffered frame\n");
780 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
781 } else {
782 ath_dbg(common, PS, "Wake up to complete TX\n");
783 sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
784 }
785 /*
786 * The actual restore operation will happen only after
787 * the ps_flags bit is cleared. We are just dropping
788 * the ps_usecount here.
789 */
790 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
791 ath9k_ps_restore(sc);
792 }
793
794 /*
795 * Cannot tx while the hardware is in full sleep, it first needs a full
796 * chip reset to recover from that
797 */
798 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) {
799 ath_err(common, "TX while HW is in FULL_SLEEP mode\n");
800 goto exit;
801 }
802
803 memset(&txctl, 0, sizeof(struct ath_tx_control));
804 txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
805 txctl.sta = control->sta;
806
807 ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb);
808
809 if (ath_tx_start(hw, skb, &txctl) != 0) {
810 ath_dbg(common, XMIT, "TX failed\n");
811 TX_STAT_INC(txctl.txq->axq_qnum, txfailed);
812 goto exit;
813 }
814
815 return;
816 exit:
817 ieee80211_free_txskb(hw, skb);
818 }
819
820 static void ath9k_stop(struct ieee80211_hw *hw)
821 {
822 struct ath_softc *sc = hw->priv;
823 struct ath_hw *ah = sc->sc_ah;
824 struct ath_common *common = ath9k_hw_common(ah);
825 bool prev_idle;
826
827 ath9k_deinit_channel_context(sc);
828
829 mutex_lock(&sc->mutex);
830
831 ath_cancel_work(sc);
832
833 if (test_bit(ATH_OP_INVALID, &common->op_flags)) {
834 ath_dbg(common, ANY, "Device not present\n");
835 mutex_unlock(&sc->mutex);
836 return;
837 }
838
839 /* Ensure HW is awake when we try to shut it down. */
840 ath9k_ps_wakeup(sc);
841
842 spin_lock_bh(&sc->sc_pcu_lock);
843
844 /* prevent tasklets to enable interrupts once we disable them */
845 ah->imask &= ~ATH9K_INT_GLOBAL;
846
847 /* make sure h/w will not generate any interrupt
848 * before setting the invalid flag. */
849 ath9k_hw_disable_interrupts(ah);
850
851 spin_unlock_bh(&sc->sc_pcu_lock);
852
853 /* we can now sync irq and kill any running tasklets, since we already
854 * disabled interrupts and not holding a spin lock */
855 synchronize_irq(sc->irq);
856 tasklet_kill(&sc->intr_tq);
857 tasklet_kill(&sc->bcon_tasklet);
858
859 prev_idle = sc->ps_idle;
860 sc->ps_idle = true;
861
862 spin_lock_bh(&sc->sc_pcu_lock);
863
864 if (ah->led_pin >= 0) {
865 ath9k_hw_set_gpio(ah, ah->led_pin,
866 (ah->config.led_active_high) ? 0 : 1);
867 ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
868 }
869
870 ath_prepare_reset(sc);
871
872 if (sc->rx.frag) {
873 dev_kfree_skb_any(sc->rx.frag);
874 sc->rx.frag = NULL;
875 }
876
877 if (!ah->curchan)
878 ah->curchan = ath9k_cmn_get_channel(hw, ah,
879 &sc->cur_chan->chandef);
880
881 ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
882
883 set_bit(ATH_OP_INVALID, &common->op_flags);
884
885 ath9k_hw_phy_disable(ah);
886
887 ath9k_hw_configpcipowersave(ah, true);
888
889 spin_unlock_bh(&sc->sc_pcu_lock);
890
891 ath9k_ps_restore(sc);
892
893 sc->ps_idle = prev_idle;
894
895 mutex_unlock(&sc->mutex);
896
897 ath_dbg(common, CONFIG, "Driver halt\n");
898 }
899
900 static bool ath9k_uses_beacons(int type)
901 {
902 switch (type) {
903 case NL80211_IFTYPE_AP:
904 case NL80211_IFTYPE_ADHOC:
905 case NL80211_IFTYPE_MESH_POINT:
906 return true;
907 default:
908 return false;
909 }
910 }
911
912 static void ath9k_vif_iter(struct ath9k_vif_iter_data *iter_data,
913 u8 *mac, struct ieee80211_vif *vif)
914 {
915 struct ath_vif *avp = (struct ath_vif *)vif->drv_priv;
916 int i;
917
918 if (iter_data->has_hw_macaddr) {
919 for (i = 0; i < ETH_ALEN; i++)
920 iter_data->mask[i] &=
921 ~(iter_data->hw_macaddr[i] ^ mac[i]);
922 } else {
923 memcpy(iter_data->hw_macaddr, mac, ETH_ALEN);
924 iter_data->has_hw_macaddr = true;
925 }
926
927 if (!vif->bss_conf.use_short_slot)
928 iter_data->slottime = ATH9K_SLOT_TIME_20;
929
930 switch (vif->type) {
931 case NL80211_IFTYPE_AP:
932 iter_data->naps++;
933 break;
934 case NL80211_IFTYPE_STATION:
935 iter_data->nstations++;
936 if (avp->assoc && !iter_data->primary_sta)
937 iter_data->primary_sta = vif;
938 break;
939 case NL80211_IFTYPE_ADHOC:
940 iter_data->nadhocs++;
941 if (vif->bss_conf.enable_beacon)
942 iter_data->beacons = true;
943 break;
944 case NL80211_IFTYPE_MESH_POINT:
945 iter_data->nmeshes++;
946 if (vif->bss_conf.enable_beacon)
947 iter_data->beacons = true;
948 break;
949 case NL80211_IFTYPE_WDS:
950 iter_data->nwds++;
951 break;
952 default:
953 break;
954 }
955 }
956
957 static void ath9k_update_bssid_mask(struct ath_softc *sc,
958 struct ath_chanctx *ctx,
959 struct ath9k_vif_iter_data *iter_data)
960 {
961 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
962 struct ath_vif *avp;
963 int i;
964
965 if (!ath9k_is_chanctx_enabled())
966 return;
967
968 list_for_each_entry(avp, &ctx->vifs, list) {
969 if (ctx->nvifs_assigned != 1)
970 continue;
971
972 if (!avp->vif->p2p || !iter_data->has_hw_macaddr)
973 continue;
974
975 ether_addr_copy(common->curbssid, avp->bssid);
976
977 /* perm_addr will be used as the p2p device address. */
978 for (i = 0; i < ETH_ALEN; i++)
979 iter_data->mask[i] &=
980 ~(iter_data->hw_macaddr[i] ^
981 sc->hw->wiphy->perm_addr[i]);
982 }
983 }
984
985 /* Called with sc->mutex held. */
986 void ath9k_calculate_iter_data(struct ath_softc *sc,
987 struct ath_chanctx *ctx,
988 struct ath9k_vif_iter_data *iter_data)
989 {
990 struct ath_vif *avp;
991
992 /*
993 * The hardware will use primary station addr together with the
994 * BSSID mask when matching addresses.
995 */
996 memset(iter_data, 0, sizeof(*iter_data));
997 memset(&iter_data->mask, 0xff, ETH_ALEN);
998 iter_data->slottime = ATH9K_SLOT_TIME_9;
999
1000 list_for_each_entry(avp, &ctx->vifs, list)
1001 ath9k_vif_iter(iter_data, avp->vif->addr, avp->vif);
1002
1003 ath9k_update_bssid_mask(sc, ctx, iter_data);
1004 }
1005
1006 static void ath9k_set_assoc_state(struct ath_softc *sc,
1007 struct ieee80211_vif *vif, bool changed)
1008 {
1009 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1010 struct ath_vif *avp = (struct ath_vif *)vif->drv_priv;
1011 unsigned long flags;
1012
1013 set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
1014
1015 ether_addr_copy(common->curbssid, avp->bssid);
1016 common->curaid = avp->aid;
1017 ath9k_hw_write_associd(sc->sc_ah);
1018
1019 if (changed) {
1020 common->last_rssi = ATH_RSSI_DUMMY_MARKER;
1021 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
1022
1023 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1024 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
1025 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1026 }
1027
1028 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
1029 ath9k_mci_update_wlan_channels(sc, false);
1030
1031 ath_dbg(common, CONFIG,
1032 "Primary Station interface: %pM, BSSID: %pM\n",
1033 vif->addr, common->curbssid);
1034 }
1035
1036 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
1037 static void ath9k_set_offchannel_state(struct ath_softc *sc)
1038 {
1039 struct ath_hw *ah = sc->sc_ah;
1040 struct ath_common *common = ath9k_hw_common(ah);
1041 struct ieee80211_vif *vif = NULL;
1042
1043 ath9k_ps_wakeup(sc);
1044
1045 if (sc->offchannel.state < ATH_OFFCHANNEL_ROC_START)
1046 vif = sc->offchannel.scan_vif;
1047 else
1048 vif = sc->offchannel.roc_vif;
1049
1050 if (WARN_ON(!vif))
1051 goto exit;
1052
1053 eth_zero_addr(common->curbssid);
1054 eth_broadcast_addr(common->bssidmask);
1055 memcpy(common->macaddr, vif->addr, ETH_ALEN);
1056 common->curaid = 0;
1057 ah->opmode = vif->type;
1058 ah->imask &= ~ATH9K_INT_SWBA;
1059 ah->imask &= ~ATH9K_INT_TSFOOR;
1060 ah->slottime = ATH9K_SLOT_TIME_9;
1061
1062 ath_hw_setbssidmask(common);
1063 ath9k_hw_setopmode(ah);
1064 ath9k_hw_write_associd(sc->sc_ah);
1065 ath9k_hw_set_interrupts(ah);
1066 ath9k_hw_init_global_settings(ah);
1067
1068 exit:
1069 ath9k_ps_restore(sc);
1070 }
1071 #endif
1072
1073 /* Called with sc->mutex held. */
1074 void ath9k_calculate_summary_state(struct ath_softc *sc,
1075 struct ath_chanctx *ctx)
1076 {
1077 struct ath_hw *ah = sc->sc_ah;
1078 struct ath_common *common = ath9k_hw_common(ah);
1079 struct ath9k_vif_iter_data iter_data;
1080 struct ath_beacon_config *cur_conf;
1081
1082 ath_chanctx_check_active(sc, ctx);
1083
1084 if (ctx != sc->cur_chan)
1085 return;
1086
1087 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
1088 if (ctx == &sc->offchannel.chan)
1089 return ath9k_set_offchannel_state(sc);
1090 #endif
1091
1092 ath9k_ps_wakeup(sc);
1093 ath9k_calculate_iter_data(sc, ctx, &iter_data);
1094
1095 if (iter_data.has_hw_macaddr)
1096 memcpy(common->macaddr, iter_data.hw_macaddr, ETH_ALEN);
1097
1098 memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
1099 ath_hw_setbssidmask(common);
1100
1101 if (iter_data.naps > 0) {
1102 cur_conf = &ctx->beacon;
1103 ath9k_hw_set_tsfadjust(ah, true);
1104 ah->opmode = NL80211_IFTYPE_AP;
1105 if (cur_conf->enable_beacon)
1106 iter_data.beacons = true;
1107 } else {
1108 ath9k_hw_set_tsfadjust(ah, false);
1109
1110 if (iter_data.nmeshes)
1111 ah->opmode = NL80211_IFTYPE_MESH_POINT;
1112 else if (iter_data.nwds)
1113 ah->opmode = NL80211_IFTYPE_AP;
1114 else if (iter_data.nadhocs)
1115 ah->opmode = NL80211_IFTYPE_ADHOC;
1116 else
1117 ah->opmode = NL80211_IFTYPE_STATION;
1118 }
1119
1120 ath9k_hw_setopmode(ah);
1121
1122 ctx->switch_after_beacon = false;
1123 if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0)
1124 ah->imask |= ATH9K_INT_TSFOOR;
1125 else {
1126 ah->imask &= ~ATH9K_INT_TSFOOR;
1127 if (iter_data.naps == 1 && iter_data.beacons)
1128 ctx->switch_after_beacon = true;
1129 }
1130
1131 ah->imask &= ~ATH9K_INT_SWBA;
1132 if (ah->opmode == NL80211_IFTYPE_STATION) {
1133 bool changed = (iter_data.primary_sta != ctx->primary_sta);
1134
1135 if (iter_data.primary_sta) {
1136 iter_data.beacons = true;
1137 ath9k_set_assoc_state(sc, iter_data.primary_sta,
1138 changed);
1139 ctx->primary_sta = iter_data.primary_sta;
1140 } else {
1141 ctx->primary_sta = NULL;
1142 memset(common->curbssid, 0, ETH_ALEN);
1143 common->curaid = 0;
1144 ath9k_hw_write_associd(sc->sc_ah);
1145 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
1146 ath9k_mci_update_wlan_channels(sc, true);
1147 }
1148 } else if (iter_data.beacons) {
1149 ah->imask |= ATH9K_INT_SWBA;
1150 }
1151 ath9k_hw_set_interrupts(ah);
1152
1153 if (iter_data.beacons)
1154 set_bit(ATH_OP_BEACONS, &common->op_flags);
1155 else
1156 clear_bit(ATH_OP_BEACONS, &common->op_flags);
1157
1158 if (ah->slottime != iter_data.slottime) {
1159 ah->slottime = iter_data.slottime;
1160 ath9k_hw_init_global_settings(ah);
1161 }
1162
1163 if (iter_data.primary_sta)
1164 set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
1165 else
1166 clear_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
1167
1168 ath_dbg(common, CONFIG,
1169 "macaddr: %pM, bssid: %pM, bssidmask: %pM\n",
1170 common->macaddr, common->curbssid, common->bssidmask);
1171
1172 ath9k_ps_restore(sc);
1173 }
1174
1175 static void ath9k_assign_hw_queues(struct ieee80211_hw *hw,
1176 struct ieee80211_vif *vif)
1177 {
1178 int i;
1179
1180 if (!ath9k_is_chanctx_enabled())
1181 return;
1182
1183 for (i = 0; i < IEEE80211_NUM_ACS; i++)
1184 vif->hw_queue[i] = i;
1185
1186 if (vif->type == NL80211_IFTYPE_AP ||
1187 vif->type == NL80211_IFTYPE_MESH_POINT)
1188 vif->cab_queue = hw->queues - 2;
1189 else
1190 vif->cab_queue = IEEE80211_INVAL_HW_QUEUE;
1191 }
1192
1193 static int ath9k_add_interface(struct ieee80211_hw *hw,
1194 struct ieee80211_vif *vif)
1195 {
1196 struct ath_softc *sc = hw->priv;
1197 struct ath_hw *ah = sc->sc_ah;
1198 struct ath_common *common = ath9k_hw_common(ah);
1199 struct ath_vif *avp = (void *)vif->drv_priv;
1200 struct ath_node *an = &avp->mcast_node;
1201
1202 mutex_lock(&sc->mutex);
1203
1204 if (config_enabled(CONFIG_ATH9K_TX99)) {
1205 if (sc->cur_chan->nvifs >= 1) {
1206 mutex_unlock(&sc->mutex);
1207 return -EOPNOTSUPP;
1208 }
1209 sc->tx99_vif = vif;
1210 }
1211
1212 ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type);
1213 sc->cur_chan->nvifs++;
1214
1215 if (ath9k_uses_beacons(vif->type))
1216 ath9k_beacon_assign_slot(sc, vif);
1217
1218 avp->vif = vif;
1219 if (!ath9k_is_chanctx_enabled()) {
1220 avp->chanctx = sc->cur_chan;
1221 list_add_tail(&avp->list, &avp->chanctx->vifs);
1222 }
1223
1224 ath9k_calculate_summary_state(sc, avp->chanctx);
1225
1226 ath9k_assign_hw_queues(hw, vif);
1227
1228 an->sc = sc;
1229 an->sta = NULL;
1230 an->vif = vif;
1231 an->no_ps_filter = true;
1232 ath_tx_node_init(sc, an);
1233
1234 mutex_unlock(&sc->mutex);
1235 return 0;
1236 }
1237
1238 static int ath9k_change_interface(struct ieee80211_hw *hw,
1239 struct ieee80211_vif *vif,
1240 enum nl80211_iftype new_type,
1241 bool p2p)
1242 {
1243 struct ath_softc *sc = hw->priv;
1244 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1245 struct ath_vif *avp = (void *)vif->drv_priv;
1246
1247 mutex_lock(&sc->mutex);
1248
1249 if (config_enabled(CONFIG_ATH9K_TX99)) {
1250 mutex_unlock(&sc->mutex);
1251 return -EOPNOTSUPP;
1252 }
1253
1254 ath_dbg(common, CONFIG, "Change Interface\n");
1255
1256 if (ath9k_uses_beacons(vif->type))
1257 ath9k_beacon_remove_slot(sc, vif);
1258
1259 vif->type = new_type;
1260 vif->p2p = p2p;
1261
1262 if (ath9k_uses_beacons(vif->type))
1263 ath9k_beacon_assign_slot(sc, vif);
1264
1265 ath9k_assign_hw_queues(hw, vif);
1266 ath9k_calculate_summary_state(sc, avp->chanctx);
1267
1268 mutex_unlock(&sc->mutex);
1269 return 0;
1270 }
1271
1272 static void ath9k_remove_interface(struct ieee80211_hw *hw,
1273 struct ieee80211_vif *vif)
1274 {
1275 struct ath_softc *sc = hw->priv;
1276 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1277 struct ath_vif *avp = (void *)vif->drv_priv;
1278
1279 ath_dbg(common, CONFIG, "Detach Interface\n");
1280
1281 mutex_lock(&sc->mutex);
1282
1283 ath9k_p2p_remove_vif(sc, vif);
1284
1285 sc->cur_chan->nvifs--;
1286 sc->tx99_vif = NULL;
1287 if (!ath9k_is_chanctx_enabled())
1288 list_del(&avp->list);
1289
1290 if (ath9k_uses_beacons(vif->type))
1291 ath9k_beacon_remove_slot(sc, vif);
1292
1293 ath_tx_node_cleanup(sc, &avp->mcast_node);
1294
1295 ath9k_calculate_summary_state(sc, avp->chanctx);
1296
1297 mutex_unlock(&sc->mutex);
1298 }
1299
1300 static void ath9k_enable_ps(struct ath_softc *sc)
1301 {
1302 struct ath_hw *ah = sc->sc_ah;
1303 struct ath_common *common = ath9k_hw_common(ah);
1304
1305 if (config_enabled(CONFIG_ATH9K_TX99))
1306 return;
1307
1308 sc->ps_enabled = true;
1309 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1310 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
1311 ah->imask |= ATH9K_INT_TIM_TIMER;
1312 ath9k_hw_set_interrupts(ah);
1313 }
1314 ath9k_hw_setrxabort(ah, 1);
1315 }
1316 ath_dbg(common, PS, "PowerSave enabled\n");
1317 }
1318
1319 static void ath9k_disable_ps(struct ath_softc *sc)
1320 {
1321 struct ath_hw *ah = sc->sc_ah;
1322 struct ath_common *common = ath9k_hw_common(ah);
1323
1324 if (config_enabled(CONFIG_ATH9K_TX99))
1325 return;
1326
1327 sc->ps_enabled = false;
1328 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
1329 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1330 ath9k_hw_setrxabort(ah, 0);
1331 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
1332 PS_WAIT_FOR_CAB |
1333 PS_WAIT_FOR_PSPOLL_DATA |
1334 PS_WAIT_FOR_TX_ACK);
1335 if (ah->imask & ATH9K_INT_TIM_TIMER) {
1336 ah->imask &= ~ATH9K_INT_TIM_TIMER;
1337 ath9k_hw_set_interrupts(ah);
1338 }
1339 }
1340 ath_dbg(common, PS, "PowerSave disabled\n");
1341 }
1342
1343 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
1344 {
1345 struct ath_softc *sc = hw->priv;
1346 struct ath_hw *ah = sc->sc_ah;
1347 struct ath_common *common = ath9k_hw_common(ah);
1348 struct ieee80211_conf *conf = &hw->conf;
1349 struct ath_chanctx *ctx = sc->cur_chan;
1350
1351 ath9k_ps_wakeup(sc);
1352 mutex_lock(&sc->mutex);
1353
1354 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
1355 sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
1356 if (sc->ps_idle) {
1357 ath_cancel_work(sc);
1358 ath9k_stop_btcoex(sc);
1359 } else {
1360 ath9k_start_btcoex(sc);
1361 /*
1362 * The chip needs a reset to properly wake up from
1363 * full sleep
1364 */
1365 ath_chanctx_set_channel(sc, ctx, &ctx->chandef);
1366 }
1367 }
1368
1369 /*
1370 * We just prepare to enable PS. We have to wait until our AP has
1371 * ACK'd our null data frame to disable RX otherwise we'll ignore
1372 * those ACKs and end up retransmitting the same null data frames.
1373 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
1374 */
1375 if (changed & IEEE80211_CONF_CHANGE_PS) {
1376 unsigned long flags;
1377 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1378 if (conf->flags & IEEE80211_CONF_PS)
1379 ath9k_enable_ps(sc);
1380 else
1381 ath9k_disable_ps(sc);
1382 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1383 }
1384
1385 if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
1386 if (conf->flags & IEEE80211_CONF_MONITOR) {
1387 ath_dbg(common, CONFIG, "Monitor mode is enabled\n");
1388 sc->sc_ah->is_monitoring = true;
1389 } else {
1390 ath_dbg(common, CONFIG, "Monitor mode is disabled\n");
1391 sc->sc_ah->is_monitoring = false;
1392 }
1393 }
1394
1395 if (!ath9k_is_chanctx_enabled() && (changed & IEEE80211_CONF_CHANGE_CHANNEL)) {
1396 ctx->offchannel = !!(conf->flags & IEEE80211_CONF_OFFCHANNEL);
1397 ath_chanctx_set_channel(sc, ctx, &hw->conf.chandef);
1398 }
1399
1400 if (changed & IEEE80211_CONF_CHANGE_POWER) {
1401 ath_dbg(common, CONFIG, "Set power: %d\n", conf->power_level);
1402 sc->cur_chan->txpower = 2 * conf->power_level;
1403 ath9k_cmn_update_txpow(ah, sc->cur_chan->cur_txpower,
1404 sc->cur_chan->txpower,
1405 &sc->cur_chan->cur_txpower);
1406 }
1407
1408 mutex_unlock(&sc->mutex);
1409 ath9k_ps_restore(sc);
1410
1411 return 0;
1412 }
1413
1414 #define SUPPORTED_FILTERS \
1415 (FIF_PROMISC_IN_BSS | \
1416 FIF_ALLMULTI | \
1417 FIF_CONTROL | \
1418 FIF_PSPOLL | \
1419 FIF_OTHER_BSS | \
1420 FIF_BCN_PRBRESP_PROMISC | \
1421 FIF_PROBE_REQ | \
1422 FIF_FCSFAIL)
1423
1424 /* FIXME: sc->sc_full_reset ? */
1425 static void ath9k_configure_filter(struct ieee80211_hw *hw,
1426 unsigned int changed_flags,
1427 unsigned int *total_flags,
1428 u64 multicast)
1429 {
1430 struct ath_softc *sc = hw->priv;
1431 u32 rfilt;
1432
1433 changed_flags &= SUPPORTED_FILTERS;
1434 *total_flags &= SUPPORTED_FILTERS;
1435
1436 spin_lock_bh(&sc->chan_lock);
1437 sc->cur_chan->rxfilter = *total_flags;
1438 spin_unlock_bh(&sc->chan_lock);
1439
1440 ath9k_ps_wakeup(sc);
1441 rfilt = ath_calcrxfilter(sc);
1442 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
1443 ath9k_ps_restore(sc);
1444
1445 ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n",
1446 rfilt);
1447 }
1448
1449 static int ath9k_sta_add(struct ieee80211_hw *hw,
1450 struct ieee80211_vif *vif,
1451 struct ieee80211_sta *sta)
1452 {
1453 struct ath_softc *sc = hw->priv;
1454 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1455 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1456 struct ieee80211_key_conf ps_key = { };
1457 int key;
1458
1459 ath_node_attach(sc, sta, vif);
1460
1461 if (vif->type != NL80211_IFTYPE_AP &&
1462 vif->type != NL80211_IFTYPE_AP_VLAN)
1463 return 0;
1464
1465 key = ath_key_config(common, vif, sta, &ps_key);
1466 if (key > 0) {
1467 an->ps_key = key;
1468 an->key_idx[0] = key;
1469 }
1470
1471 return 0;
1472 }
1473
1474 static void ath9k_del_ps_key(struct ath_softc *sc,
1475 struct ieee80211_vif *vif,
1476 struct ieee80211_sta *sta)
1477 {
1478 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1479 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1480 struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key };
1481
1482 if (!an->ps_key)
1483 return;
1484
1485 ath_key_delete(common, &ps_key);
1486 an->ps_key = 0;
1487 an->key_idx[0] = 0;
1488 }
1489
1490 static int ath9k_sta_remove(struct ieee80211_hw *hw,
1491 struct ieee80211_vif *vif,
1492 struct ieee80211_sta *sta)
1493 {
1494 struct ath_softc *sc = hw->priv;
1495
1496 ath9k_del_ps_key(sc, vif, sta);
1497 ath_node_detach(sc, sta);
1498
1499 return 0;
1500 }
1501
1502 static int ath9k_sta_state(struct ieee80211_hw *hw,
1503 struct ieee80211_vif *vif,
1504 struct ieee80211_sta *sta,
1505 enum ieee80211_sta_state old_state,
1506 enum ieee80211_sta_state new_state)
1507 {
1508 struct ath_softc *sc = hw->priv;
1509 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1510 int ret = 0;
1511
1512 if (old_state == IEEE80211_STA_AUTH &&
1513 new_state == IEEE80211_STA_ASSOC) {
1514 ret = ath9k_sta_add(hw, vif, sta);
1515 ath_dbg(common, CONFIG,
1516 "Add station: %pM\n", sta->addr);
1517 } else if (old_state == IEEE80211_STA_ASSOC &&
1518 new_state == IEEE80211_STA_AUTH) {
1519 ret = ath9k_sta_remove(hw, vif, sta);
1520 ath_dbg(common, CONFIG,
1521 "Remove station: %pM\n", sta->addr);
1522 }
1523
1524 if (ath9k_is_chanctx_enabled()) {
1525 if (vif->type == NL80211_IFTYPE_STATION) {
1526 if (old_state == IEEE80211_STA_ASSOC &&
1527 new_state == IEEE80211_STA_AUTHORIZED)
1528 ath_chanctx_event(sc, vif,
1529 ATH_CHANCTX_EVENT_AUTHORIZED);
1530 }
1531 }
1532
1533 return ret;
1534 }
1535
1536 static void ath9k_sta_set_tx_filter(struct ath_hw *ah,
1537 struct ath_node *an,
1538 bool set)
1539 {
1540 int i;
1541
1542 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
1543 if (!an->key_idx[i])
1544 continue;
1545 ath9k_hw_set_tx_filter(ah, an->key_idx[i], set);
1546 }
1547 }
1548
1549 static void ath9k_sta_notify(struct ieee80211_hw *hw,
1550 struct ieee80211_vif *vif,
1551 enum sta_notify_cmd cmd,
1552 struct ieee80211_sta *sta)
1553 {
1554 struct ath_softc *sc = hw->priv;
1555 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1556
1557 switch (cmd) {
1558 case STA_NOTIFY_SLEEP:
1559 an->sleeping = true;
1560 ath_tx_aggr_sleep(sta, sc, an);
1561 ath9k_sta_set_tx_filter(sc->sc_ah, an, true);
1562 break;
1563 case STA_NOTIFY_AWAKE:
1564 ath9k_sta_set_tx_filter(sc->sc_ah, an, false);
1565 an->sleeping = false;
1566 ath_tx_aggr_wakeup(sc, an);
1567 break;
1568 }
1569 }
1570
1571 static int ath9k_conf_tx(struct ieee80211_hw *hw,
1572 struct ieee80211_vif *vif, u16 queue,
1573 const struct ieee80211_tx_queue_params *params)
1574 {
1575 struct ath_softc *sc = hw->priv;
1576 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1577 struct ath_txq *txq;
1578 struct ath9k_tx_queue_info qi;
1579 int ret = 0;
1580
1581 if (queue >= IEEE80211_NUM_ACS)
1582 return 0;
1583
1584 txq = sc->tx.txq_map[queue];
1585
1586 ath9k_ps_wakeup(sc);
1587 mutex_lock(&sc->mutex);
1588
1589 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
1590
1591 qi.tqi_aifs = params->aifs;
1592 qi.tqi_cwmin = params->cw_min;
1593 qi.tqi_cwmax = params->cw_max;
1594 qi.tqi_burstTime = params->txop * 32;
1595
1596 ath_dbg(common, CONFIG,
1597 "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
1598 queue, txq->axq_qnum, params->aifs, params->cw_min,
1599 params->cw_max, params->txop);
1600
1601 ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime);
1602 ret = ath_txq_update(sc, txq->axq_qnum, &qi);
1603 if (ret)
1604 ath_err(common, "TXQ Update failed\n");
1605
1606 mutex_unlock(&sc->mutex);
1607 ath9k_ps_restore(sc);
1608
1609 return ret;
1610 }
1611
1612 static int ath9k_set_key(struct ieee80211_hw *hw,
1613 enum set_key_cmd cmd,
1614 struct ieee80211_vif *vif,
1615 struct ieee80211_sta *sta,
1616 struct ieee80211_key_conf *key)
1617 {
1618 struct ath_softc *sc = hw->priv;
1619 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1620 struct ath_node *an = NULL;
1621 int ret = 0, i;
1622
1623 if (ath9k_modparam_nohwcrypt)
1624 return -ENOSPC;
1625
1626 if ((vif->type == NL80211_IFTYPE_ADHOC ||
1627 vif->type == NL80211_IFTYPE_MESH_POINT) &&
1628 (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
1629 key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
1630 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
1631 /*
1632 * For now, disable hw crypto for the RSN IBSS group keys. This
1633 * could be optimized in the future to use a modified key cache
1634 * design to support per-STA RX GTK, but until that gets
1635 * implemented, use of software crypto for group addressed
1636 * frames is a acceptable to allow RSN IBSS to be used.
1637 */
1638 return -EOPNOTSUPP;
1639 }
1640
1641 mutex_lock(&sc->mutex);
1642 ath9k_ps_wakeup(sc);
1643 ath_dbg(common, CONFIG, "Set HW Key %d\n", cmd);
1644 if (sta)
1645 an = (struct ath_node *)sta->drv_priv;
1646
1647 switch (cmd) {
1648 case SET_KEY:
1649 if (sta)
1650 ath9k_del_ps_key(sc, vif, sta);
1651
1652 key->hw_key_idx = 0;
1653 ret = ath_key_config(common, vif, sta, key);
1654 if (ret >= 0) {
1655 key->hw_key_idx = ret;
1656 /* push IV and Michael MIC generation to stack */
1657 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
1658 if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
1659 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
1660 if (sc->sc_ah->sw_mgmt_crypto_tx &&
1661 key->cipher == WLAN_CIPHER_SUITE_CCMP)
1662 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
1663 ret = 0;
1664 }
1665 if (an && key->hw_key_idx) {
1666 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
1667 if (an->key_idx[i])
1668 continue;
1669 an->key_idx[i] = key->hw_key_idx;
1670 break;
1671 }
1672 WARN_ON(i == ARRAY_SIZE(an->key_idx));
1673 }
1674 break;
1675 case DISABLE_KEY:
1676 ath_key_delete(common, key);
1677 if (an) {
1678 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
1679 if (an->key_idx[i] != key->hw_key_idx)
1680 continue;
1681 an->key_idx[i] = 0;
1682 break;
1683 }
1684 }
1685 key->hw_key_idx = 0;
1686 break;
1687 default:
1688 ret = -EINVAL;
1689 }
1690
1691 ath9k_ps_restore(sc);
1692 mutex_unlock(&sc->mutex);
1693
1694 return ret;
1695 }
1696
1697 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
1698 struct ieee80211_vif *vif,
1699 struct ieee80211_bss_conf *bss_conf,
1700 u32 changed)
1701 {
1702 #define CHECK_ANI \
1703 (BSS_CHANGED_ASSOC | \
1704 BSS_CHANGED_IBSS | \
1705 BSS_CHANGED_BEACON_ENABLED)
1706
1707 struct ath_softc *sc = hw->priv;
1708 struct ath_hw *ah = sc->sc_ah;
1709 struct ath_common *common = ath9k_hw_common(ah);
1710 struct ath_vif *avp = (void *)vif->drv_priv;
1711 int slottime;
1712
1713 ath9k_ps_wakeup(sc);
1714 mutex_lock(&sc->mutex);
1715
1716 if (changed & BSS_CHANGED_ASSOC) {
1717 ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n",
1718 bss_conf->bssid, bss_conf->assoc);
1719
1720 memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
1721 avp->aid = bss_conf->aid;
1722 avp->assoc = bss_conf->assoc;
1723
1724 ath9k_calculate_summary_state(sc, avp->chanctx);
1725 }
1726
1727 if (changed & BSS_CHANGED_IBSS) {
1728 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1729 common->curaid = bss_conf->aid;
1730 ath9k_hw_write_associd(sc->sc_ah);
1731 }
1732
1733 if ((changed & BSS_CHANGED_BEACON_ENABLED) ||
1734 (changed & BSS_CHANGED_BEACON_INT) ||
1735 (changed & BSS_CHANGED_BEACON_INFO)) {
1736 ath9k_beacon_config(sc, vif, changed);
1737 if (changed & BSS_CHANGED_BEACON_ENABLED)
1738 ath9k_calculate_summary_state(sc, avp->chanctx);
1739 }
1740
1741 if ((avp->chanctx == sc->cur_chan) &&
1742 (changed & BSS_CHANGED_ERP_SLOT)) {
1743 if (bss_conf->use_short_slot)
1744 slottime = 9;
1745 else
1746 slottime = 20;
1747 if (vif->type == NL80211_IFTYPE_AP) {
1748 /*
1749 * Defer update, so that connected stations can adjust
1750 * their settings at the same time.
1751 * See beacon.c for more details
1752 */
1753 sc->beacon.slottime = slottime;
1754 sc->beacon.updateslot = UPDATE;
1755 } else {
1756 ah->slottime = slottime;
1757 ath9k_hw_init_global_settings(ah);
1758 }
1759 }
1760
1761 if (changed & BSS_CHANGED_P2P_PS)
1762 ath9k_p2p_bss_info_changed(sc, vif);
1763
1764 if (changed & CHECK_ANI)
1765 ath_check_ani(sc);
1766
1767 mutex_unlock(&sc->mutex);
1768 ath9k_ps_restore(sc);
1769
1770 #undef CHECK_ANI
1771 }
1772
1773 static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1774 {
1775 struct ath_softc *sc = hw->priv;
1776 u64 tsf;
1777
1778 mutex_lock(&sc->mutex);
1779 ath9k_ps_wakeup(sc);
1780 tsf = ath9k_hw_gettsf64(sc->sc_ah);
1781 ath9k_ps_restore(sc);
1782 mutex_unlock(&sc->mutex);
1783
1784 return tsf;
1785 }
1786
1787 static void ath9k_set_tsf(struct ieee80211_hw *hw,
1788 struct ieee80211_vif *vif,
1789 u64 tsf)
1790 {
1791 struct ath_softc *sc = hw->priv;
1792
1793 mutex_lock(&sc->mutex);
1794 ath9k_ps_wakeup(sc);
1795 ath9k_hw_settsf64(sc->sc_ah, tsf);
1796 ath9k_ps_restore(sc);
1797 mutex_unlock(&sc->mutex);
1798 }
1799
1800 static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1801 {
1802 struct ath_softc *sc = hw->priv;
1803
1804 mutex_lock(&sc->mutex);
1805
1806 ath9k_ps_wakeup(sc);
1807 ath9k_hw_reset_tsf(sc->sc_ah);
1808 ath9k_ps_restore(sc);
1809
1810 mutex_unlock(&sc->mutex);
1811 }
1812
1813 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
1814 struct ieee80211_vif *vif,
1815 enum ieee80211_ampdu_mlme_action action,
1816 struct ieee80211_sta *sta,
1817 u16 tid, u16 *ssn, u8 buf_size)
1818 {
1819 struct ath_softc *sc = hw->priv;
1820 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1821 bool flush = false;
1822 int ret = 0;
1823
1824 mutex_lock(&sc->mutex);
1825
1826 switch (action) {
1827 case IEEE80211_AMPDU_RX_START:
1828 break;
1829 case IEEE80211_AMPDU_RX_STOP:
1830 break;
1831 case IEEE80211_AMPDU_TX_START:
1832 if (ath9k_is_chanctx_enabled()) {
1833 if (test_bit(ATH_OP_SCANNING, &common->op_flags)) {
1834 ret = -EBUSY;
1835 break;
1836 }
1837 }
1838 ath9k_ps_wakeup(sc);
1839 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
1840 if (!ret)
1841 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
1842 ath9k_ps_restore(sc);
1843 break;
1844 case IEEE80211_AMPDU_TX_STOP_FLUSH:
1845 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
1846 flush = true;
1847 case IEEE80211_AMPDU_TX_STOP_CONT:
1848 ath9k_ps_wakeup(sc);
1849 ath_tx_aggr_stop(sc, sta, tid);
1850 if (!flush)
1851 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
1852 ath9k_ps_restore(sc);
1853 break;
1854 case IEEE80211_AMPDU_TX_OPERATIONAL:
1855 ath9k_ps_wakeup(sc);
1856 ath_tx_aggr_resume(sc, sta, tid);
1857 ath9k_ps_restore(sc);
1858 break;
1859 default:
1860 ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
1861 }
1862
1863 mutex_unlock(&sc->mutex);
1864
1865 return ret;
1866 }
1867
1868 static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
1869 struct survey_info *survey)
1870 {
1871 struct ath_softc *sc = hw->priv;
1872 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1873 struct ieee80211_supported_band *sband;
1874 struct ieee80211_channel *chan;
1875 int pos;
1876
1877 if (config_enabled(CONFIG_ATH9K_TX99))
1878 return -EOPNOTSUPP;
1879
1880 spin_lock_bh(&common->cc_lock);
1881 if (idx == 0)
1882 ath_update_survey_stats(sc);
1883
1884 sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
1885 if (sband && idx >= sband->n_channels) {
1886 idx -= sband->n_channels;
1887 sband = NULL;
1888 }
1889
1890 if (!sband)
1891 sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
1892
1893 if (!sband || idx >= sband->n_channels) {
1894 spin_unlock_bh(&common->cc_lock);
1895 return -ENOENT;
1896 }
1897
1898 chan = &sband->channels[idx];
1899 pos = chan->hw_value;
1900 memcpy(survey, &sc->survey[pos], sizeof(*survey));
1901 survey->channel = chan;
1902 spin_unlock_bh(&common->cc_lock);
1903
1904 return 0;
1905 }
1906
1907 static void ath9k_enable_dynack(struct ath_softc *sc)
1908 {
1909 #ifdef CONFIG_ATH9K_DYNACK
1910 u32 rfilt;
1911 struct ath_hw *ah = sc->sc_ah;
1912
1913 ath_dynack_reset(ah);
1914
1915 ah->dynack.enabled = true;
1916 rfilt = ath_calcrxfilter(sc);
1917 ath9k_hw_setrxfilter(ah, rfilt);
1918 #endif
1919 }
1920
1921 static void ath9k_set_coverage_class(struct ieee80211_hw *hw,
1922 s16 coverage_class)
1923 {
1924 struct ath_softc *sc = hw->priv;
1925 struct ath_hw *ah = sc->sc_ah;
1926
1927 if (config_enabled(CONFIG_ATH9K_TX99))
1928 return;
1929
1930 mutex_lock(&sc->mutex);
1931
1932 if (coverage_class >= 0) {
1933 ah->coverage_class = coverage_class;
1934 if (ah->dynack.enabled) {
1935 u32 rfilt;
1936
1937 ah->dynack.enabled = false;
1938 rfilt = ath_calcrxfilter(sc);
1939 ath9k_hw_setrxfilter(ah, rfilt);
1940 }
1941 ath9k_ps_wakeup(sc);
1942 ath9k_hw_init_global_settings(ah);
1943 ath9k_ps_restore(sc);
1944 } else if (!ah->dynack.enabled) {
1945 ath9k_enable_dynack(sc);
1946 }
1947
1948 mutex_unlock(&sc->mutex);
1949 }
1950
1951 static bool ath9k_has_tx_pending(struct ath_softc *sc,
1952 bool sw_pending)
1953 {
1954 int i, npend = 0;
1955
1956 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1957 if (!ATH_TXQ_SETUP(sc, i))
1958 continue;
1959
1960 npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i],
1961 sw_pending);
1962 if (npend)
1963 break;
1964 }
1965
1966 return !!npend;
1967 }
1968
1969 static void ath9k_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1970 u32 queues, bool drop)
1971 {
1972 struct ath_softc *sc = hw->priv;
1973 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1974
1975 if (ath9k_is_chanctx_enabled()) {
1976 if (!test_bit(ATH_OP_MULTI_CHANNEL, &common->op_flags))
1977 goto flush;
1978
1979 /*
1980 * If MCC is active, extend the flush timeout
1981 * and wait for the HW/SW queues to become
1982 * empty. This needs to be done outside the
1983 * sc->mutex lock to allow the channel scheduler
1984 * to switch channel contexts.
1985 *
1986 * The vif queues have been stopped in mac80211,
1987 * so there won't be any incoming frames.
1988 */
1989 __ath9k_flush(hw, queues, drop, true, true);
1990 return;
1991 }
1992 flush:
1993 mutex_lock(&sc->mutex);
1994 __ath9k_flush(hw, queues, drop, true, false);
1995 mutex_unlock(&sc->mutex);
1996 }
1997
1998 void __ath9k_flush(struct ieee80211_hw *hw, u32 queues, bool drop,
1999 bool sw_pending, bool timeout_override)
2000 {
2001 struct ath_softc *sc = hw->priv;
2002 struct ath_hw *ah = sc->sc_ah;
2003 struct ath_common *common = ath9k_hw_common(ah);
2004 int timeout;
2005 bool drain_txq;
2006
2007 cancel_delayed_work_sync(&sc->tx_complete_work);
2008
2009 if (ah->ah_flags & AH_UNPLUGGED) {
2010 ath_dbg(common, ANY, "Device has been unplugged!\n");
2011 return;
2012 }
2013
2014 if (test_bit(ATH_OP_INVALID, &common->op_flags)) {
2015 ath_dbg(common, ANY, "Device not present\n");
2016 return;
2017 }
2018
2019 spin_lock_bh(&sc->chan_lock);
2020 if (timeout_override)
2021 timeout = HZ / 5;
2022 else
2023 timeout = sc->cur_chan->flush_timeout;
2024 spin_unlock_bh(&sc->chan_lock);
2025
2026 ath_dbg(common, CHAN_CTX,
2027 "Flush timeout: %d\n", jiffies_to_msecs(timeout));
2028
2029 if (wait_event_timeout(sc->tx_wait, !ath9k_has_tx_pending(sc, sw_pending),
2030 timeout) > 0)
2031 drop = false;
2032
2033 if (drop) {
2034 ath9k_ps_wakeup(sc);
2035 spin_lock_bh(&sc->sc_pcu_lock);
2036 drain_txq = ath_drain_all_txq(sc);
2037 spin_unlock_bh(&sc->sc_pcu_lock);
2038
2039 if (!drain_txq)
2040 ath_reset(sc, NULL);
2041
2042 ath9k_ps_restore(sc);
2043 }
2044
2045 ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0);
2046 }
2047
2048 static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
2049 {
2050 struct ath_softc *sc = hw->priv;
2051
2052 return ath9k_has_tx_pending(sc, true);
2053 }
2054
2055 static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
2056 {
2057 struct ath_softc *sc = hw->priv;
2058 struct ath_hw *ah = sc->sc_ah;
2059 struct ieee80211_vif *vif;
2060 struct ath_vif *avp;
2061 struct ath_buf *bf;
2062 struct ath_tx_status ts;
2063 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
2064 int status;
2065
2066 vif = sc->beacon.bslot[0];
2067 if (!vif)
2068 return 0;
2069
2070 if (!vif->bss_conf.enable_beacon)
2071 return 0;
2072
2073 avp = (void *)vif->drv_priv;
2074
2075 if (!sc->beacon.tx_processed && !edma) {
2076 tasklet_disable(&sc->bcon_tasklet);
2077
2078 bf = avp->av_bcbuf;
2079 if (!bf || !bf->bf_mpdu)
2080 goto skip;
2081
2082 status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
2083 if (status == -EINPROGRESS)
2084 goto skip;
2085
2086 sc->beacon.tx_processed = true;
2087 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
2088
2089 skip:
2090 tasklet_enable(&sc->bcon_tasklet);
2091 }
2092
2093 return sc->beacon.tx_last;
2094 }
2095
2096 static int ath9k_get_stats(struct ieee80211_hw *hw,
2097 struct ieee80211_low_level_stats *stats)
2098 {
2099 struct ath_softc *sc = hw->priv;
2100 struct ath_hw *ah = sc->sc_ah;
2101 struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats;
2102
2103 stats->dot11ACKFailureCount = mib_stats->ackrcv_bad;
2104 stats->dot11RTSFailureCount = mib_stats->rts_bad;
2105 stats->dot11FCSErrorCount = mib_stats->fcs_bad;
2106 stats->dot11RTSSuccessCount = mib_stats->rts_good;
2107 return 0;
2108 }
2109
2110 static u32 fill_chainmask(u32 cap, u32 new)
2111 {
2112 u32 filled = 0;
2113 int i;
2114
2115 for (i = 0; cap && new; i++, cap >>= 1) {
2116 if (!(cap & BIT(0)))
2117 continue;
2118
2119 if (new & BIT(0))
2120 filled |= BIT(i);
2121
2122 new >>= 1;
2123 }
2124
2125 return filled;
2126 }
2127
2128 static bool validate_antenna_mask(struct ath_hw *ah, u32 val)
2129 {
2130 if (AR_SREV_9300_20_OR_LATER(ah))
2131 return true;
2132
2133 switch (val & 0x7) {
2134 case 0x1:
2135 case 0x3:
2136 case 0x7:
2137 return true;
2138 case 0x2:
2139 return (ah->caps.rx_chainmask == 1);
2140 default:
2141 return false;
2142 }
2143 }
2144
2145 static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
2146 {
2147 struct ath_softc *sc = hw->priv;
2148 struct ath_hw *ah = sc->sc_ah;
2149
2150 if (ah->caps.rx_chainmask != 1)
2151 rx_ant |= tx_ant;
2152
2153 if (!validate_antenna_mask(ah, rx_ant) || !tx_ant)
2154 return -EINVAL;
2155
2156 sc->ant_rx = rx_ant;
2157 sc->ant_tx = tx_ant;
2158
2159 if (ah->caps.rx_chainmask == 1)
2160 return 0;
2161
2162 /* AR9100 runs into calibration issues if not all rx chains are enabled */
2163 if (AR_SREV_9100(ah))
2164 ah->rxchainmask = 0x7;
2165 else
2166 ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant);
2167
2168 ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant);
2169 ath9k_cmn_reload_chainmask(ah);
2170
2171 return 0;
2172 }
2173
2174 static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
2175 {
2176 struct ath_softc *sc = hw->priv;
2177
2178 *tx_ant = sc->ant_tx;
2179 *rx_ant = sc->ant_rx;
2180 return 0;
2181 }
2182
2183 static void ath9k_sw_scan_start(struct ieee80211_hw *hw,
2184 struct ieee80211_vif *vif,
2185 const u8 *mac_addr)
2186 {
2187 struct ath_softc *sc = hw->priv;
2188 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2189 set_bit(ATH_OP_SCANNING, &common->op_flags);
2190 }
2191
2192 static void ath9k_sw_scan_complete(struct ieee80211_hw *hw,
2193 struct ieee80211_vif *vif)
2194 {
2195 struct ath_softc *sc = hw->priv;
2196 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2197 clear_bit(ATH_OP_SCANNING, &common->op_flags);
2198 }
2199
2200 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
2201
2202 static void ath9k_cancel_pending_offchannel(struct ath_softc *sc)
2203 {
2204 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2205
2206 if (sc->offchannel.roc_vif) {
2207 ath_dbg(common, CHAN_CTX,
2208 "%s: Aborting RoC\n", __func__);
2209
2210 del_timer_sync(&sc->offchannel.timer);
2211 if (sc->offchannel.state >= ATH_OFFCHANNEL_ROC_START)
2212 ath_roc_complete(sc, true);
2213 }
2214
2215 if (test_bit(ATH_OP_SCANNING, &common->op_flags)) {
2216 ath_dbg(common, CHAN_CTX,
2217 "%s: Aborting HW scan\n", __func__);
2218
2219 del_timer_sync(&sc->offchannel.timer);
2220 ath_scan_complete(sc, true);
2221 }
2222 }
2223
2224 static int ath9k_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2225 struct ieee80211_scan_request *hw_req)
2226 {
2227 struct cfg80211_scan_request *req = &hw_req->req;
2228 struct ath_softc *sc = hw->priv;
2229 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2230 int ret = 0;
2231
2232 mutex_lock(&sc->mutex);
2233
2234 if (WARN_ON(sc->offchannel.scan_req)) {
2235 ret = -EBUSY;
2236 goto out;
2237 }
2238
2239 ath9k_ps_wakeup(sc);
2240 set_bit(ATH_OP_SCANNING, &common->op_flags);
2241 sc->offchannel.scan_vif = vif;
2242 sc->offchannel.scan_req = req;
2243 sc->offchannel.scan_idx = 0;
2244
2245 ath_dbg(common, CHAN_CTX, "HW scan request received on vif: %pM\n",
2246 vif->addr);
2247
2248 if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) {
2249 ath_dbg(common, CHAN_CTX, "Starting HW scan\n");
2250 ath_offchannel_next(sc);
2251 }
2252
2253 out:
2254 mutex_unlock(&sc->mutex);
2255
2256 return ret;
2257 }
2258
2259 static void ath9k_cancel_hw_scan(struct ieee80211_hw *hw,
2260 struct ieee80211_vif *vif)
2261 {
2262 struct ath_softc *sc = hw->priv;
2263 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2264
2265 ath_dbg(common, CHAN_CTX, "Cancel HW scan on vif: %pM\n", vif->addr);
2266
2267 mutex_lock(&sc->mutex);
2268 del_timer_sync(&sc->offchannel.timer);
2269 ath_scan_complete(sc, true);
2270 mutex_unlock(&sc->mutex);
2271 }
2272
2273 static int ath9k_remain_on_channel(struct ieee80211_hw *hw,
2274 struct ieee80211_vif *vif,
2275 struct ieee80211_channel *chan, int duration,
2276 enum ieee80211_roc_type type)
2277 {
2278 struct ath_softc *sc = hw->priv;
2279 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2280 int ret = 0;
2281
2282 mutex_lock(&sc->mutex);
2283
2284 if (WARN_ON(sc->offchannel.roc_vif)) {
2285 ret = -EBUSY;
2286 goto out;
2287 }
2288
2289 ath9k_ps_wakeup(sc);
2290 sc->offchannel.roc_vif = vif;
2291 sc->offchannel.roc_chan = chan;
2292 sc->offchannel.roc_duration = duration;
2293
2294 ath_dbg(common, CHAN_CTX,
2295 "RoC request on vif: %pM, type: %d duration: %d\n",
2296 vif->addr, type, duration);
2297
2298 if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) {
2299 ath_dbg(common, CHAN_CTX, "Starting RoC period\n");
2300 ath_offchannel_next(sc);
2301 }
2302
2303 out:
2304 mutex_unlock(&sc->mutex);
2305
2306 return ret;
2307 }
2308
2309 static int ath9k_cancel_remain_on_channel(struct ieee80211_hw *hw)
2310 {
2311 struct ath_softc *sc = hw->priv;
2312 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2313
2314 mutex_lock(&sc->mutex);
2315
2316 ath_dbg(common, CHAN_CTX, "Cancel RoC\n");
2317 del_timer_sync(&sc->offchannel.timer);
2318
2319 if (sc->offchannel.roc_vif) {
2320 if (sc->offchannel.state >= ATH_OFFCHANNEL_ROC_START)
2321 ath_roc_complete(sc, true);
2322 }
2323
2324 mutex_unlock(&sc->mutex);
2325
2326 return 0;
2327 }
2328
2329 static int ath9k_add_chanctx(struct ieee80211_hw *hw,
2330 struct ieee80211_chanctx_conf *conf)
2331 {
2332 struct ath_softc *sc = hw->priv;
2333 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2334 struct ath_chanctx *ctx, **ptr;
2335 int pos;
2336
2337 mutex_lock(&sc->mutex);
2338
2339 ath_for_each_chanctx(sc, ctx) {
2340 if (ctx->assigned)
2341 continue;
2342
2343 ptr = (void *) conf->drv_priv;
2344 *ptr = ctx;
2345 ctx->assigned = true;
2346 pos = ctx - &sc->chanctx[0];
2347 ctx->hw_queue_base = pos * IEEE80211_NUM_ACS;
2348
2349 ath_dbg(common, CHAN_CTX,
2350 "Add channel context: %d MHz\n",
2351 conf->def.chan->center_freq);
2352
2353 ath_chanctx_set_channel(sc, ctx, &conf->def);
2354
2355 mutex_unlock(&sc->mutex);
2356 return 0;
2357 }
2358
2359 mutex_unlock(&sc->mutex);
2360 return -ENOSPC;
2361 }
2362
2363
2364 static void ath9k_remove_chanctx(struct ieee80211_hw *hw,
2365 struct ieee80211_chanctx_conf *conf)
2366 {
2367 struct ath_softc *sc = hw->priv;
2368 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2369 struct ath_chanctx *ctx = ath_chanctx_get(conf);
2370
2371 mutex_lock(&sc->mutex);
2372
2373 ath_dbg(common, CHAN_CTX,
2374 "Remove channel context: %d MHz\n",
2375 conf->def.chan->center_freq);
2376
2377 ctx->assigned = false;
2378 ctx->hw_queue_base = 0;
2379 ath_chanctx_event(sc, NULL, ATH_CHANCTX_EVENT_UNASSIGN);
2380
2381 mutex_unlock(&sc->mutex);
2382 }
2383
2384 static void ath9k_change_chanctx(struct ieee80211_hw *hw,
2385 struct ieee80211_chanctx_conf *conf,
2386 u32 changed)
2387 {
2388 struct ath_softc *sc = hw->priv;
2389 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2390 struct ath_chanctx *ctx = ath_chanctx_get(conf);
2391
2392 mutex_lock(&sc->mutex);
2393 ath_dbg(common, CHAN_CTX,
2394 "Change channel context: %d MHz\n",
2395 conf->def.chan->center_freq);
2396 ath_chanctx_set_channel(sc, ctx, &conf->def);
2397 mutex_unlock(&sc->mutex);
2398 }
2399
2400 static int ath9k_assign_vif_chanctx(struct ieee80211_hw *hw,
2401 struct ieee80211_vif *vif,
2402 struct ieee80211_chanctx_conf *conf)
2403 {
2404 struct ath_softc *sc = hw->priv;
2405 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2406 struct ath_vif *avp = (void *)vif->drv_priv;
2407 struct ath_chanctx *ctx = ath_chanctx_get(conf);
2408 int i;
2409
2410 ath9k_cancel_pending_offchannel(sc);
2411
2412 mutex_lock(&sc->mutex);
2413
2414 ath_dbg(common, CHAN_CTX,
2415 "Assign VIF (addr: %pM, type: %d, p2p: %d) to channel context: %d MHz\n",
2416 vif->addr, vif->type, vif->p2p,
2417 conf->def.chan->center_freq);
2418
2419 avp->chanctx = ctx;
2420 ctx->nvifs_assigned++;
2421 list_add_tail(&avp->list, &ctx->vifs);
2422 ath9k_calculate_summary_state(sc, ctx);
2423 for (i = 0; i < IEEE80211_NUM_ACS; i++)
2424 vif->hw_queue[i] = ctx->hw_queue_base + i;
2425
2426 mutex_unlock(&sc->mutex);
2427
2428 return 0;
2429 }
2430
2431 static void ath9k_unassign_vif_chanctx(struct ieee80211_hw *hw,
2432 struct ieee80211_vif *vif,
2433 struct ieee80211_chanctx_conf *conf)
2434 {
2435 struct ath_softc *sc = hw->priv;
2436 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2437 struct ath_vif *avp = (void *)vif->drv_priv;
2438 struct ath_chanctx *ctx = ath_chanctx_get(conf);
2439 int ac;
2440
2441 ath9k_cancel_pending_offchannel(sc);
2442
2443 mutex_lock(&sc->mutex);
2444
2445 ath_dbg(common, CHAN_CTX,
2446 "Remove VIF (addr: %pM, type: %d, p2p: %d) from channel context: %d MHz\n",
2447 vif->addr, vif->type, vif->p2p,
2448 conf->def.chan->center_freq);
2449
2450 avp->chanctx = NULL;
2451 ctx->nvifs_assigned--;
2452 list_del(&avp->list);
2453 ath9k_calculate_summary_state(sc, ctx);
2454 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++)
2455 vif->hw_queue[ac] = IEEE80211_INVAL_HW_QUEUE;
2456
2457 mutex_unlock(&sc->mutex);
2458 }
2459
2460 static void ath9k_mgd_prepare_tx(struct ieee80211_hw *hw,
2461 struct ieee80211_vif *vif)
2462 {
2463 struct ath_softc *sc = hw->priv;
2464 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2465 struct ath_vif *avp = (struct ath_vif *) vif->drv_priv;
2466 struct ath_beacon_config *cur_conf;
2467 struct ath_chanctx *go_ctx;
2468 unsigned long timeout;
2469 bool changed = false;
2470 u32 beacon_int;
2471
2472 if (!test_bit(ATH_OP_MULTI_CHANNEL, &common->op_flags))
2473 return;
2474
2475 if (!avp->chanctx)
2476 return;
2477
2478 mutex_lock(&sc->mutex);
2479
2480 spin_lock_bh(&sc->chan_lock);
2481 if (sc->next_chan || (sc->cur_chan != avp->chanctx))
2482 changed = true;
2483 spin_unlock_bh(&sc->chan_lock);
2484
2485 if (!changed)
2486 goto out;
2487
2488 ath9k_cancel_pending_offchannel(sc);
2489
2490 go_ctx = ath_is_go_chanctx_present(sc);
2491
2492 if (go_ctx) {
2493 /*
2494 * Wait till the GO interface gets a chance
2495 * to send out an NoA.
2496 */
2497 spin_lock_bh(&sc->chan_lock);
2498 sc->sched.mgd_prepare_tx = true;
2499 cur_conf = &go_ctx->beacon;
2500 beacon_int = TU_TO_USEC(cur_conf->beacon_interval);
2501 spin_unlock_bh(&sc->chan_lock);
2502
2503 timeout = usecs_to_jiffies(beacon_int * 2);
2504 init_completion(&sc->go_beacon);
2505
2506 mutex_unlock(&sc->mutex);
2507
2508 if (wait_for_completion_timeout(&sc->go_beacon,
2509 timeout) == 0) {
2510 ath_dbg(common, CHAN_CTX,
2511 "Failed to send new NoA\n");
2512
2513 spin_lock_bh(&sc->chan_lock);
2514 sc->sched.mgd_prepare_tx = false;
2515 spin_unlock_bh(&sc->chan_lock);
2516 }
2517
2518 mutex_lock(&sc->mutex);
2519 }
2520
2521 ath_dbg(common, CHAN_CTX,
2522 "%s: Set chanctx state to FORCE_ACTIVE for vif: %pM\n",
2523 __func__, vif->addr);
2524
2525 spin_lock_bh(&sc->chan_lock);
2526 sc->next_chan = avp->chanctx;
2527 sc->sched.state = ATH_CHANCTX_STATE_FORCE_ACTIVE;
2528 spin_unlock_bh(&sc->chan_lock);
2529
2530 ath_chanctx_set_next(sc, true);
2531 out:
2532 mutex_unlock(&sc->mutex);
2533 }
2534
2535 void ath9k_fill_chanctx_ops(void)
2536 {
2537 if (!ath9k_is_chanctx_enabled())
2538 return;
2539
2540 ath9k_ops.hw_scan = ath9k_hw_scan;
2541 ath9k_ops.cancel_hw_scan = ath9k_cancel_hw_scan;
2542 ath9k_ops.remain_on_channel = ath9k_remain_on_channel;
2543 ath9k_ops.cancel_remain_on_channel = ath9k_cancel_remain_on_channel;
2544 ath9k_ops.add_chanctx = ath9k_add_chanctx;
2545 ath9k_ops.remove_chanctx = ath9k_remove_chanctx;
2546 ath9k_ops.change_chanctx = ath9k_change_chanctx;
2547 ath9k_ops.assign_vif_chanctx = ath9k_assign_vif_chanctx;
2548 ath9k_ops.unassign_vif_chanctx = ath9k_unassign_vif_chanctx;
2549 ath9k_ops.mgd_prepare_tx = ath9k_mgd_prepare_tx;
2550 }
2551
2552 #endif
2553
2554 static int ath9k_get_txpower(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2555 int *dbm)
2556 {
2557 struct ath_softc *sc = hw->priv;
2558 struct ath_vif *avp = (void *)vif->drv_priv;
2559
2560 mutex_lock(&sc->mutex);
2561 if (avp->chanctx)
2562 *dbm = avp->chanctx->cur_txpower;
2563 else
2564 *dbm = sc->cur_chan->cur_txpower;
2565 mutex_unlock(&sc->mutex);
2566
2567 *dbm /= 2;
2568
2569 return 0;
2570 }
2571
2572 struct ieee80211_ops ath9k_ops = {
2573 .tx = ath9k_tx,
2574 .start = ath9k_start,
2575 .stop = ath9k_stop,
2576 .add_interface = ath9k_add_interface,
2577 .change_interface = ath9k_change_interface,
2578 .remove_interface = ath9k_remove_interface,
2579 .config = ath9k_config,
2580 .configure_filter = ath9k_configure_filter,
2581 .sta_state = ath9k_sta_state,
2582 .sta_notify = ath9k_sta_notify,
2583 .conf_tx = ath9k_conf_tx,
2584 .bss_info_changed = ath9k_bss_info_changed,
2585 .set_key = ath9k_set_key,
2586 .get_tsf = ath9k_get_tsf,
2587 .set_tsf = ath9k_set_tsf,
2588 .reset_tsf = ath9k_reset_tsf,
2589 .ampdu_action = ath9k_ampdu_action,
2590 .get_survey = ath9k_get_survey,
2591 .rfkill_poll = ath9k_rfkill_poll_state,
2592 .set_coverage_class = ath9k_set_coverage_class,
2593 .flush = ath9k_flush,
2594 .tx_frames_pending = ath9k_tx_frames_pending,
2595 .tx_last_beacon = ath9k_tx_last_beacon,
2596 .release_buffered_frames = ath9k_release_buffered_frames,
2597 .get_stats = ath9k_get_stats,
2598 .set_antenna = ath9k_set_antenna,
2599 .get_antenna = ath9k_get_antenna,
2600
2601 #ifdef CONFIG_ATH9K_WOW
2602 .suspend = ath9k_suspend,
2603 .resume = ath9k_resume,
2604 .set_wakeup = ath9k_set_wakeup,
2605 #endif
2606
2607 #ifdef CONFIG_ATH9K_DEBUGFS
2608 .get_et_sset_count = ath9k_get_et_sset_count,
2609 .get_et_stats = ath9k_get_et_stats,
2610 .get_et_strings = ath9k_get_et_strings,
2611 #endif
2612
2613 #if defined(CONFIG_MAC80211_DEBUGFS) && defined(CONFIG_ATH9K_STATION_STATISTICS)
2614 .sta_add_debugfs = ath9k_sta_add_debugfs,
2615 #endif
2616 .sw_scan_start = ath9k_sw_scan_start,
2617 .sw_scan_complete = ath9k_sw_scan_complete,
2618 .get_txpower = ath9k_get_txpower,
2619 };
Linux kernel - Deliverables
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