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Merge tag 'nfc-next-3.6-1' of git://git.kernel.org/pub/scm/linux/kernel/git/sameo...
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / main.c
1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/nl80211.h>
18 #include <linux/delay.h>
19 #include "ath9k.h"
20 #include "btcoex.h"
21
22 static u8 parse_mpdudensity(u8 mpdudensity)
23 {
24 /*
25 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
26 * 0 for no restriction
27 * 1 for 1/4 us
28 * 2 for 1/2 us
29 * 3 for 1 us
30 * 4 for 2 us
31 * 5 for 4 us
32 * 6 for 8 us
33 * 7 for 16 us
34 */
35 switch (mpdudensity) {
36 case 0:
37 return 0;
38 case 1:
39 case 2:
40 case 3:
41 /* Our lower layer calculations limit our precision to
42 1 microsecond */
43 return 1;
44 case 4:
45 return 2;
46 case 5:
47 return 4;
48 case 6:
49 return 8;
50 case 7:
51 return 16;
52 default:
53 return 0;
54 }
55 }
56
57 static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq)
58 {
59 bool pending = false;
60
61 spin_lock_bh(&txq->axq_lock);
62
63 if (txq->axq_depth || !list_empty(&txq->axq_acq))
64 pending = true;
65
66 spin_unlock_bh(&txq->axq_lock);
67 return pending;
68 }
69
70 static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
71 {
72 unsigned long flags;
73 bool ret;
74
75 spin_lock_irqsave(&sc->sc_pm_lock, flags);
76 ret = ath9k_hw_setpower(sc->sc_ah, mode);
77 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
78
79 return ret;
80 }
81
82 void ath9k_ps_wakeup(struct ath_softc *sc)
83 {
84 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
85 unsigned long flags;
86 enum ath9k_power_mode power_mode;
87
88 spin_lock_irqsave(&sc->sc_pm_lock, flags);
89 if (++sc->ps_usecount != 1)
90 goto unlock;
91
92 power_mode = sc->sc_ah->power_mode;
93 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
94
95 /*
96 * While the hardware is asleep, the cycle counters contain no
97 * useful data. Better clear them now so that they don't mess up
98 * survey data results.
99 */
100 if (power_mode != ATH9K_PM_AWAKE) {
101 spin_lock(&common->cc_lock);
102 ath_hw_cycle_counters_update(common);
103 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
104 memset(&common->cc_ani, 0, sizeof(common->cc_ani));
105 spin_unlock(&common->cc_lock);
106 }
107
108 unlock:
109 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
110 }
111
112 void ath9k_ps_restore(struct ath_softc *sc)
113 {
114 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
115 enum ath9k_power_mode mode;
116 unsigned long flags;
117 bool reset;
118
119 spin_lock_irqsave(&sc->sc_pm_lock, flags);
120 if (--sc->ps_usecount != 0)
121 goto unlock;
122
123 if (sc->ps_idle) {
124 ath9k_hw_setrxabort(sc->sc_ah, 1);
125 ath9k_hw_stopdmarecv(sc->sc_ah, &reset);
126 mode = ATH9K_PM_FULL_SLEEP;
127 } else if (sc->ps_enabled &&
128 !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
129 PS_WAIT_FOR_CAB |
130 PS_WAIT_FOR_PSPOLL_DATA |
131 PS_WAIT_FOR_TX_ACK))) {
132 mode = ATH9K_PM_NETWORK_SLEEP;
133 } else {
134 goto unlock;
135 }
136
137 spin_lock(&common->cc_lock);
138 ath_hw_cycle_counters_update(common);
139 spin_unlock(&common->cc_lock);
140
141 ath9k_hw_setpower(sc->sc_ah, mode);
142
143 unlock:
144 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
145 }
146
147 static void __ath_cancel_work(struct ath_softc *sc)
148 {
149 cancel_work_sync(&sc->paprd_work);
150 cancel_work_sync(&sc->hw_check_work);
151 cancel_delayed_work_sync(&sc->tx_complete_work);
152 cancel_delayed_work_sync(&sc->hw_pll_work);
153 }
154
155 static void ath_cancel_work(struct ath_softc *sc)
156 {
157 __ath_cancel_work(sc);
158 cancel_work_sync(&sc->hw_reset_work);
159 }
160
161 static void ath_restart_work(struct ath_softc *sc)
162 {
163 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
164
165 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
166
167 if (AR_SREV_9485(sc->sc_ah) || AR_SREV_9340(sc->sc_ah))
168 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work,
169 msecs_to_jiffies(ATH_PLL_WORK_INTERVAL));
170
171 ath_start_rx_poll(sc, 3);
172
173 if (!common->disable_ani)
174 ath_start_ani(common);
175 }
176
177 static bool ath_prepare_reset(struct ath_softc *sc, bool retry_tx, bool flush)
178 {
179 struct ath_hw *ah = sc->sc_ah;
180 struct ath_common *common = ath9k_hw_common(ah);
181 bool ret = true;
182
183 ieee80211_stop_queues(sc->hw);
184
185 sc->hw_busy_count = 0;
186 del_timer_sync(&common->ani.timer);
187 del_timer_sync(&sc->rx_poll_timer);
188
189 ath9k_debug_samp_bb_mac(sc);
190 ath9k_hw_disable_interrupts(ah);
191
192 if (!ath_stoprecv(sc))
193 ret = false;
194
195 if (!ath_drain_all_txq(sc, retry_tx))
196 ret = false;
197
198 if (!flush) {
199 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
200 ath_rx_tasklet(sc, 1, true);
201 ath_rx_tasklet(sc, 1, false);
202 } else {
203 ath_flushrecv(sc);
204 }
205
206 return ret;
207 }
208
209 static bool ath_complete_reset(struct ath_softc *sc, bool start)
210 {
211 struct ath_hw *ah = sc->sc_ah;
212 struct ath_common *common = ath9k_hw_common(ah);
213 unsigned long flags;
214
215 if (ath_startrecv(sc) != 0) {
216 ath_err(common, "Unable to restart recv logic\n");
217 return false;
218 }
219
220 ath9k_cmn_update_txpow(ah, sc->curtxpow,
221 sc->config.txpowlimit, &sc->curtxpow);
222
223 clear_bit(SC_OP_HW_RESET, &sc->sc_flags);
224 ath9k_hw_set_interrupts(ah);
225 ath9k_hw_enable_interrupts(ah);
226
227 if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) && start) {
228 if (!test_bit(SC_OP_BEACONS, &sc->sc_flags))
229 goto work;
230
231 ath_set_beacon(sc);
232
233 if (ah->opmode == NL80211_IFTYPE_STATION &&
234 test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
235 spin_lock_irqsave(&sc->sc_pm_lock, flags);
236 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
237 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
238 }
239 work:
240 ath_restart_work(sc);
241 }
242
243 if ((ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) && sc->ant_rx != 3)
244 ath_ant_comb_update(sc);
245
246 ieee80211_wake_queues(sc->hw);
247
248 return true;
249 }
250
251 static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan,
252 bool retry_tx)
253 {
254 struct ath_hw *ah = sc->sc_ah;
255 struct ath_common *common = ath9k_hw_common(ah);
256 struct ath9k_hw_cal_data *caldata = NULL;
257 bool fastcc = true;
258 bool flush = false;
259 int r;
260
261 __ath_cancel_work(sc);
262
263 spin_lock_bh(&sc->sc_pcu_lock);
264
265 if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) {
266 fastcc = false;
267 caldata = &sc->caldata;
268 }
269
270 if (!hchan) {
271 fastcc = false;
272 flush = true;
273 hchan = ah->curchan;
274 }
275
276 if (!ath_prepare_reset(sc, retry_tx, flush))
277 fastcc = false;
278
279 ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n",
280 hchan->channel, IS_CHAN_HT40(hchan), fastcc);
281
282 r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
283 if (r) {
284 ath_err(common,
285 "Unable to reset channel, reset status %d\n", r);
286 goto out;
287 }
288
289 if (!ath_complete_reset(sc, true))
290 r = -EIO;
291
292 out:
293 spin_unlock_bh(&sc->sc_pcu_lock);
294 return r;
295 }
296
297
298 /*
299 * Set/change channels. If the channel is really being changed, it's done
300 * by reseting the chip. To accomplish this we must first cleanup any pending
301 * DMA, then restart stuff.
302 */
303 static int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
304 struct ath9k_channel *hchan)
305 {
306 int r;
307
308 if (test_bit(SC_OP_INVALID, &sc->sc_flags))
309 return -EIO;
310
311 r = ath_reset_internal(sc, hchan, false);
312
313 return r;
314 }
315
316 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
317 struct ieee80211_vif *vif)
318 {
319 struct ath_node *an;
320 an = (struct ath_node *)sta->drv_priv;
321
322 #ifdef CONFIG_ATH9K_DEBUGFS
323 spin_lock(&sc->nodes_lock);
324 list_add(&an->list, &sc->nodes);
325 spin_unlock(&sc->nodes_lock);
326 #endif
327 an->sta = sta;
328 an->vif = vif;
329
330 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
331 ath_tx_node_init(sc, an);
332 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
333 sta->ht_cap.ampdu_factor);
334 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
335 }
336 }
337
338 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
339 {
340 struct ath_node *an = (struct ath_node *)sta->drv_priv;
341
342 #ifdef CONFIG_ATH9K_DEBUGFS
343 spin_lock(&sc->nodes_lock);
344 list_del(&an->list);
345 spin_unlock(&sc->nodes_lock);
346 an->sta = NULL;
347 #endif
348
349 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
350 ath_tx_node_cleanup(sc, an);
351 }
352
353 void ath9k_tasklet(unsigned long data)
354 {
355 struct ath_softc *sc = (struct ath_softc *)data;
356 struct ath_hw *ah = sc->sc_ah;
357 struct ath_common *common = ath9k_hw_common(ah);
358 unsigned long flags;
359 u32 status = sc->intrstatus;
360 u32 rxmask;
361
362 ath9k_ps_wakeup(sc);
363 spin_lock(&sc->sc_pcu_lock);
364
365 if ((status & ATH9K_INT_FATAL) ||
366 (status & ATH9K_INT_BB_WATCHDOG)) {
367 #ifdef CONFIG_ATH9K_DEBUGFS
368 enum ath_reset_type type;
369
370 if (status & ATH9K_INT_FATAL)
371 type = RESET_TYPE_FATAL_INT;
372 else
373 type = RESET_TYPE_BB_WATCHDOG;
374
375 RESET_STAT_INC(sc, type);
376 #endif
377 set_bit(SC_OP_HW_RESET, &sc->sc_flags);
378 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
379 goto out;
380 }
381
382 spin_lock_irqsave(&sc->sc_pm_lock, flags);
383 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
384 /*
385 * TSF sync does not look correct; remain awake to sync with
386 * the next Beacon.
387 */
388 ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n");
389 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
390 }
391 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
392
393 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
394 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
395 ATH9K_INT_RXORN);
396 else
397 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
398
399 if (status & rxmask) {
400 /* Check for high priority Rx first */
401 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
402 (status & ATH9K_INT_RXHP))
403 ath_rx_tasklet(sc, 0, true);
404
405 ath_rx_tasklet(sc, 0, false);
406 }
407
408 if (status & ATH9K_INT_TX) {
409 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
410 ath_tx_edma_tasklet(sc);
411 else
412 ath_tx_tasklet(sc);
413 }
414
415 ath9k_btcoex_handle_interrupt(sc, status);
416
417 out:
418 /* re-enable hardware interrupt */
419 ath9k_hw_enable_interrupts(ah);
420
421 spin_unlock(&sc->sc_pcu_lock);
422 ath9k_ps_restore(sc);
423 }
424
425 irqreturn_t ath_isr(int irq, void *dev)
426 {
427 #define SCHED_INTR ( \
428 ATH9K_INT_FATAL | \
429 ATH9K_INT_BB_WATCHDOG | \
430 ATH9K_INT_RXORN | \
431 ATH9K_INT_RXEOL | \
432 ATH9K_INT_RX | \
433 ATH9K_INT_RXLP | \
434 ATH9K_INT_RXHP | \
435 ATH9K_INT_TX | \
436 ATH9K_INT_BMISS | \
437 ATH9K_INT_CST | \
438 ATH9K_INT_TSFOOR | \
439 ATH9K_INT_GENTIMER | \
440 ATH9K_INT_MCI)
441
442 struct ath_softc *sc = dev;
443 struct ath_hw *ah = sc->sc_ah;
444 struct ath_common *common = ath9k_hw_common(ah);
445 enum ath9k_int status;
446 bool sched = false;
447
448 /*
449 * The hardware is not ready/present, don't
450 * touch anything. Note this can happen early
451 * on if the IRQ is shared.
452 */
453 if (test_bit(SC_OP_INVALID, &sc->sc_flags))
454 return IRQ_NONE;
455
456 /* shared irq, not for us */
457
458 if (!ath9k_hw_intrpend(ah))
459 return IRQ_NONE;
460
461 if(test_bit(SC_OP_HW_RESET, &sc->sc_flags))
462 return IRQ_HANDLED;
463
464 /*
465 * Figure out the reason(s) for the interrupt. Note
466 * that the hal returns a pseudo-ISR that may include
467 * bits we haven't explicitly enabled so we mask the
468 * value to insure we only process bits we requested.
469 */
470 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
471 status &= ah->imask; /* discard unasked-for bits */
472
473 /*
474 * If there are no status bits set, then this interrupt was not
475 * for me (should have been caught above).
476 */
477 if (!status)
478 return IRQ_NONE;
479
480 /* Cache the status */
481 sc->intrstatus = status;
482
483 if (status & SCHED_INTR)
484 sched = true;
485
486 /*
487 * If a FATAL or RXORN interrupt is received, we have to reset the
488 * chip immediately.
489 */
490 if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
491 !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
492 goto chip_reset;
493
494 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
495 (status & ATH9K_INT_BB_WATCHDOG)) {
496
497 spin_lock(&common->cc_lock);
498 ath_hw_cycle_counters_update(common);
499 ar9003_hw_bb_watchdog_dbg_info(ah);
500 spin_unlock(&common->cc_lock);
501
502 goto chip_reset;
503 }
504
505 if (status & ATH9K_INT_SWBA)
506 tasklet_schedule(&sc->bcon_tasklet);
507
508 if (status & ATH9K_INT_TXURN)
509 ath9k_hw_updatetxtriglevel(ah, true);
510
511 if (status & ATH9K_INT_RXEOL) {
512 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
513 ath9k_hw_set_interrupts(ah);
514 }
515
516 if (status & ATH9K_INT_MIB) {
517 /*
518 * Disable interrupts until we service the MIB
519 * interrupt; otherwise it will continue to
520 * fire.
521 */
522 ath9k_hw_disable_interrupts(ah);
523 /*
524 * Let the hal handle the event. We assume
525 * it will clear whatever condition caused
526 * the interrupt.
527 */
528 spin_lock(&common->cc_lock);
529 ath9k_hw_proc_mib_event(ah);
530 spin_unlock(&common->cc_lock);
531 ath9k_hw_enable_interrupts(ah);
532 }
533
534 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
535 if (status & ATH9K_INT_TIM_TIMER) {
536 if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
537 goto chip_reset;
538 /* Clear RxAbort bit so that we can
539 * receive frames */
540 ath9k_setpower(sc, ATH9K_PM_AWAKE);
541 spin_lock(&sc->sc_pm_lock);
542 ath9k_hw_setrxabort(sc->sc_ah, 0);
543 sc->ps_flags |= PS_WAIT_FOR_BEACON;
544 spin_unlock(&sc->sc_pm_lock);
545 }
546
547 chip_reset:
548
549 ath_debug_stat_interrupt(sc, status);
550
551 if (sched) {
552 /* turn off every interrupt */
553 ath9k_hw_disable_interrupts(ah);
554 tasklet_schedule(&sc->intr_tq);
555 }
556
557 return IRQ_HANDLED;
558
559 #undef SCHED_INTR
560 }
561
562 static int ath_reset(struct ath_softc *sc, bool retry_tx)
563 {
564 int r;
565
566 ath9k_ps_wakeup(sc);
567
568 r = ath_reset_internal(sc, NULL, retry_tx);
569
570 if (retry_tx) {
571 int i;
572 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
573 if (ATH_TXQ_SETUP(sc, i)) {
574 spin_lock_bh(&sc->tx.txq[i].axq_lock);
575 ath_txq_schedule(sc, &sc->tx.txq[i]);
576 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
577 }
578 }
579 }
580
581 ath9k_ps_restore(sc);
582
583 return r;
584 }
585
586 void ath_reset_work(struct work_struct *work)
587 {
588 struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work);
589
590 ath_reset(sc, true);
591 }
592
593 /**********************/
594 /* mac80211 callbacks */
595 /**********************/
596
597 static int ath9k_start(struct ieee80211_hw *hw)
598 {
599 struct ath_softc *sc = hw->priv;
600 struct ath_hw *ah = sc->sc_ah;
601 struct ath_common *common = ath9k_hw_common(ah);
602 struct ieee80211_channel *curchan = hw->conf.channel;
603 struct ath9k_channel *init_channel;
604 int r;
605
606 ath_dbg(common, CONFIG,
607 "Starting driver with initial channel: %d MHz\n",
608 curchan->center_freq);
609
610 ath9k_ps_wakeup(sc);
611 mutex_lock(&sc->mutex);
612
613 init_channel = ath9k_cmn_get_curchannel(hw, ah);
614
615 /* Reset SERDES registers */
616 ath9k_hw_configpcipowersave(ah, false);
617
618 /*
619 * The basic interface to setting the hardware in a good
620 * state is ``reset''. On return the hardware is known to
621 * be powered up and with interrupts disabled. This must
622 * be followed by initialization of the appropriate bits
623 * and then setup of the interrupt mask.
624 */
625 spin_lock_bh(&sc->sc_pcu_lock);
626
627 atomic_set(&ah->intr_ref_cnt, -1);
628
629 r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
630 if (r) {
631 ath_err(common,
632 "Unable to reset hardware; reset status %d (freq %u MHz)\n",
633 r, curchan->center_freq);
634 spin_unlock_bh(&sc->sc_pcu_lock);
635 goto mutex_unlock;
636 }
637
638 /* Setup our intr mask. */
639 ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
640 ATH9K_INT_RXORN | ATH9K_INT_FATAL |
641 ATH9K_INT_GLOBAL;
642
643 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
644 ah->imask |= ATH9K_INT_RXHP |
645 ATH9K_INT_RXLP |
646 ATH9K_INT_BB_WATCHDOG;
647 else
648 ah->imask |= ATH9K_INT_RX;
649
650 ah->imask |= ATH9K_INT_GTT;
651
652 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
653 ah->imask |= ATH9K_INT_CST;
654
655 ath_mci_enable(sc);
656
657 clear_bit(SC_OP_INVALID, &sc->sc_flags);
658 sc->sc_ah->is_monitoring = false;
659
660 if (!ath_complete_reset(sc, false)) {
661 r = -EIO;
662 spin_unlock_bh(&sc->sc_pcu_lock);
663 goto mutex_unlock;
664 }
665
666 if (ah->led_pin >= 0) {
667 ath9k_hw_cfg_output(ah, ah->led_pin,
668 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
669 ath9k_hw_set_gpio(ah, ah->led_pin, 0);
670 }
671
672 /*
673 * Reset key cache to sane defaults (all entries cleared) instead of
674 * semi-random values after suspend/resume.
675 */
676 ath9k_cmn_init_crypto(sc->sc_ah);
677
678 spin_unlock_bh(&sc->sc_pcu_lock);
679
680 ath9k_start_btcoex(sc);
681
682 if (ah->caps.pcie_lcr_extsync_en && common->bus_ops->extn_synch_en)
683 common->bus_ops->extn_synch_en(common);
684
685 mutex_unlock:
686 mutex_unlock(&sc->mutex);
687
688 ath9k_ps_restore(sc);
689
690 return r;
691 }
692
693 static void ath9k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
694 {
695 struct ath_softc *sc = hw->priv;
696 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
697 struct ath_tx_control txctl;
698 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
699 unsigned long flags;
700
701 if (sc->ps_enabled) {
702 /*
703 * mac80211 does not set PM field for normal data frames, so we
704 * need to update that based on the current PS mode.
705 */
706 if (ieee80211_is_data(hdr->frame_control) &&
707 !ieee80211_is_nullfunc(hdr->frame_control) &&
708 !ieee80211_has_pm(hdr->frame_control)) {
709 ath_dbg(common, PS,
710 "Add PM=1 for a TX frame while in PS mode\n");
711 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
712 }
713 }
714
715 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) {
716 /*
717 * We are using PS-Poll and mac80211 can request TX while in
718 * power save mode. Need to wake up hardware for the TX to be
719 * completed and if needed, also for RX of buffered frames.
720 */
721 ath9k_ps_wakeup(sc);
722 spin_lock_irqsave(&sc->sc_pm_lock, flags);
723 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
724 ath9k_hw_setrxabort(sc->sc_ah, 0);
725 if (ieee80211_is_pspoll(hdr->frame_control)) {
726 ath_dbg(common, PS,
727 "Sending PS-Poll to pick a buffered frame\n");
728 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
729 } else {
730 ath_dbg(common, PS, "Wake up to complete TX\n");
731 sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
732 }
733 /*
734 * The actual restore operation will happen only after
735 * the ps_flags bit is cleared. We are just dropping
736 * the ps_usecount here.
737 */
738 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
739 ath9k_ps_restore(sc);
740 }
741
742 /*
743 * Cannot tx while the hardware is in full sleep, it first needs a full
744 * chip reset to recover from that
745 */
746 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) {
747 ath_err(common, "TX while HW is in FULL_SLEEP mode\n");
748 goto exit;
749 }
750
751 memset(&txctl, 0, sizeof(struct ath_tx_control));
752 txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
753
754 ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb);
755
756 if (ath_tx_start(hw, skb, &txctl) != 0) {
757 ath_dbg(common, XMIT, "TX failed\n");
758 TX_STAT_INC(txctl.txq->axq_qnum, txfailed);
759 goto exit;
760 }
761
762 return;
763 exit:
764 dev_kfree_skb_any(skb);
765 }
766
767 static void ath9k_stop(struct ieee80211_hw *hw)
768 {
769 struct ath_softc *sc = hw->priv;
770 struct ath_hw *ah = sc->sc_ah;
771 struct ath_common *common = ath9k_hw_common(ah);
772 bool prev_idle;
773
774 mutex_lock(&sc->mutex);
775
776 ath_cancel_work(sc);
777 del_timer_sync(&sc->rx_poll_timer);
778
779 if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
780 ath_dbg(common, ANY, "Device not present\n");
781 mutex_unlock(&sc->mutex);
782 return;
783 }
784
785 /* Ensure HW is awake when we try to shut it down. */
786 ath9k_ps_wakeup(sc);
787
788 ath9k_stop_btcoex(sc);
789
790 spin_lock_bh(&sc->sc_pcu_lock);
791
792 /* prevent tasklets to enable interrupts once we disable them */
793 ah->imask &= ~ATH9K_INT_GLOBAL;
794
795 /* make sure h/w will not generate any interrupt
796 * before setting the invalid flag. */
797 ath9k_hw_disable_interrupts(ah);
798
799 spin_unlock_bh(&sc->sc_pcu_lock);
800
801 /* we can now sync irq and kill any running tasklets, since we already
802 * disabled interrupts and not holding a spin lock */
803 synchronize_irq(sc->irq);
804 tasklet_kill(&sc->intr_tq);
805 tasklet_kill(&sc->bcon_tasklet);
806
807 prev_idle = sc->ps_idle;
808 sc->ps_idle = true;
809
810 spin_lock_bh(&sc->sc_pcu_lock);
811
812 if (ah->led_pin >= 0) {
813 ath9k_hw_set_gpio(ah, ah->led_pin, 1);
814 ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
815 }
816
817 ath_prepare_reset(sc, false, true);
818
819 if (sc->rx.frag) {
820 dev_kfree_skb_any(sc->rx.frag);
821 sc->rx.frag = NULL;
822 }
823
824 if (!ah->curchan)
825 ah->curchan = ath9k_cmn_get_curchannel(hw, ah);
826
827 ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
828 ath9k_hw_phy_disable(ah);
829
830 ath9k_hw_configpcipowersave(ah, true);
831
832 spin_unlock_bh(&sc->sc_pcu_lock);
833
834 ath9k_ps_restore(sc);
835
836 set_bit(SC_OP_INVALID, &sc->sc_flags);
837 sc->ps_idle = prev_idle;
838
839 mutex_unlock(&sc->mutex);
840
841 ath_dbg(common, CONFIG, "Driver halt\n");
842 }
843
844 bool ath9k_uses_beacons(int type)
845 {
846 switch (type) {
847 case NL80211_IFTYPE_AP:
848 case NL80211_IFTYPE_ADHOC:
849 case NL80211_IFTYPE_MESH_POINT:
850 return true;
851 default:
852 return false;
853 }
854 }
855
856 static void ath9k_reclaim_beacon(struct ath_softc *sc,
857 struct ieee80211_vif *vif)
858 {
859 struct ath_vif *avp = (void *)vif->drv_priv;
860
861 ath9k_set_beaconing_status(sc, false);
862 ath_beacon_return(sc, avp);
863 ath9k_set_beaconing_status(sc, true);
864 }
865
866 static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
867 {
868 struct ath9k_vif_iter_data *iter_data = data;
869 int i;
870
871 if (iter_data->hw_macaddr)
872 for (i = 0; i < ETH_ALEN; i++)
873 iter_data->mask[i] &=
874 ~(iter_data->hw_macaddr[i] ^ mac[i]);
875
876 switch (vif->type) {
877 case NL80211_IFTYPE_AP:
878 iter_data->naps++;
879 break;
880 case NL80211_IFTYPE_STATION:
881 iter_data->nstations++;
882 break;
883 case NL80211_IFTYPE_ADHOC:
884 iter_data->nadhocs++;
885 break;
886 case NL80211_IFTYPE_MESH_POINT:
887 iter_data->nmeshes++;
888 break;
889 case NL80211_IFTYPE_WDS:
890 iter_data->nwds++;
891 break;
892 default:
893 break;
894 }
895 }
896
897 /* Called with sc->mutex held. */
898 void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
899 struct ieee80211_vif *vif,
900 struct ath9k_vif_iter_data *iter_data)
901 {
902 struct ath_softc *sc = hw->priv;
903 struct ath_hw *ah = sc->sc_ah;
904 struct ath_common *common = ath9k_hw_common(ah);
905
906 /*
907 * Use the hardware MAC address as reference, the hardware uses it
908 * together with the BSSID mask when matching addresses.
909 */
910 memset(iter_data, 0, sizeof(*iter_data));
911 iter_data->hw_macaddr = common->macaddr;
912 memset(&iter_data->mask, 0xff, ETH_ALEN);
913
914 if (vif)
915 ath9k_vif_iter(iter_data, vif->addr, vif);
916
917 /* Get list of all active MAC addresses */
918 ieee80211_iterate_active_interfaces_atomic(sc->hw, ath9k_vif_iter,
919 iter_data);
920 }
921
922 /* Called with sc->mutex held. */
923 static void ath9k_calculate_summary_state(struct ieee80211_hw *hw,
924 struct ieee80211_vif *vif)
925 {
926 struct ath_softc *sc = hw->priv;
927 struct ath_hw *ah = sc->sc_ah;
928 struct ath_common *common = ath9k_hw_common(ah);
929 struct ath9k_vif_iter_data iter_data;
930
931 ath9k_calculate_iter_data(hw, vif, &iter_data);
932
933 /* Set BSSID mask. */
934 memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
935 ath_hw_setbssidmask(common);
936
937 /* Set op-mode & TSF */
938 if (iter_data.naps > 0) {
939 ath9k_hw_set_tsfadjust(ah, 1);
940 set_bit(SC_OP_TSF_RESET, &sc->sc_flags);
941 ah->opmode = NL80211_IFTYPE_AP;
942 } else {
943 ath9k_hw_set_tsfadjust(ah, 0);
944 clear_bit(SC_OP_TSF_RESET, &sc->sc_flags);
945
946 if (iter_data.nmeshes)
947 ah->opmode = NL80211_IFTYPE_MESH_POINT;
948 else if (iter_data.nwds)
949 ah->opmode = NL80211_IFTYPE_AP;
950 else if (iter_data.nadhocs)
951 ah->opmode = NL80211_IFTYPE_ADHOC;
952 else
953 ah->opmode = NL80211_IFTYPE_STATION;
954 }
955
956 /*
957 * Enable MIB interrupts when there are hardware phy counters.
958 */
959 if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0) {
960 if (ah->config.enable_ani)
961 ah->imask |= ATH9K_INT_MIB;
962 ah->imask |= ATH9K_INT_TSFOOR;
963 } else {
964 ah->imask &= ~ATH9K_INT_MIB;
965 ah->imask &= ~ATH9K_INT_TSFOOR;
966 }
967
968 ath9k_hw_set_interrupts(ah);
969
970 /* Set up ANI */
971 if (iter_data.naps > 0) {
972 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
973
974 if (!common->disable_ani) {
975 set_bit(SC_OP_ANI_RUN, &sc->sc_flags);
976 ath_start_ani(common);
977 }
978
979 } else {
980 clear_bit(SC_OP_ANI_RUN, &sc->sc_flags);
981 del_timer_sync(&common->ani.timer);
982 }
983 }
984
985 /* Called with sc->mutex held, vif counts set up properly. */
986 static void ath9k_do_vif_add_setup(struct ieee80211_hw *hw,
987 struct ieee80211_vif *vif)
988 {
989 struct ath_softc *sc = hw->priv;
990
991 ath9k_calculate_summary_state(hw, vif);
992
993 if (ath9k_uses_beacons(vif->type)) {
994 /* Reserve a beacon slot for the vif */
995 ath9k_set_beaconing_status(sc, false);
996 ath_beacon_alloc(sc, vif);
997 ath9k_set_beaconing_status(sc, true);
998 }
999 }
1000
1001 static int ath9k_add_interface(struct ieee80211_hw *hw,
1002 struct ieee80211_vif *vif)
1003 {
1004 struct ath_softc *sc = hw->priv;
1005 struct ath_hw *ah = sc->sc_ah;
1006 struct ath_common *common = ath9k_hw_common(ah);
1007 int ret = 0;
1008
1009 ath9k_ps_wakeup(sc);
1010 mutex_lock(&sc->mutex);
1011
1012 switch (vif->type) {
1013 case NL80211_IFTYPE_STATION:
1014 case NL80211_IFTYPE_WDS:
1015 case NL80211_IFTYPE_ADHOC:
1016 case NL80211_IFTYPE_AP:
1017 case NL80211_IFTYPE_MESH_POINT:
1018 break;
1019 default:
1020 ath_err(common, "Interface type %d not yet supported\n",
1021 vif->type);
1022 ret = -EOPNOTSUPP;
1023 goto out;
1024 }
1025
1026 if (ath9k_uses_beacons(vif->type)) {
1027 if (sc->nbcnvifs >= ATH_BCBUF) {
1028 ath_err(common, "Not enough beacon buffers when adding"
1029 " new interface of type: %i\n",
1030 vif->type);
1031 ret = -ENOBUFS;
1032 goto out;
1033 }
1034 }
1035
1036 if ((ah->opmode == NL80211_IFTYPE_ADHOC) ||
1037 ((vif->type == NL80211_IFTYPE_ADHOC) &&
1038 sc->nvifs > 0)) {
1039 ath_err(common, "Cannot create ADHOC interface when other"
1040 " interfaces already exist.\n");
1041 ret = -EINVAL;
1042 goto out;
1043 }
1044
1045 ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type);
1046
1047 sc->nvifs++;
1048
1049 ath9k_do_vif_add_setup(hw, vif);
1050 out:
1051 mutex_unlock(&sc->mutex);
1052 ath9k_ps_restore(sc);
1053 return ret;
1054 }
1055
1056 static int ath9k_change_interface(struct ieee80211_hw *hw,
1057 struct ieee80211_vif *vif,
1058 enum nl80211_iftype new_type,
1059 bool p2p)
1060 {
1061 struct ath_softc *sc = hw->priv;
1062 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1063 int ret = 0;
1064
1065 ath_dbg(common, CONFIG, "Change Interface\n");
1066 mutex_lock(&sc->mutex);
1067 ath9k_ps_wakeup(sc);
1068
1069 /* See if new interface type is valid. */
1070 if ((new_type == NL80211_IFTYPE_ADHOC) &&
1071 (sc->nvifs > 1)) {
1072 ath_err(common, "When using ADHOC, it must be the only"
1073 " interface.\n");
1074 ret = -EINVAL;
1075 goto out;
1076 }
1077
1078 if (ath9k_uses_beacons(new_type) &&
1079 !ath9k_uses_beacons(vif->type)) {
1080 if (sc->nbcnvifs >= ATH_BCBUF) {
1081 ath_err(common, "No beacon slot available\n");
1082 ret = -ENOBUFS;
1083 goto out;
1084 }
1085 }
1086
1087 /* Clean up old vif stuff */
1088 if (ath9k_uses_beacons(vif->type))
1089 ath9k_reclaim_beacon(sc, vif);
1090
1091 /* Add new settings */
1092 vif->type = new_type;
1093 vif->p2p = p2p;
1094
1095 ath9k_do_vif_add_setup(hw, vif);
1096 out:
1097 ath9k_ps_restore(sc);
1098 mutex_unlock(&sc->mutex);
1099 return ret;
1100 }
1101
1102 static void ath9k_remove_interface(struct ieee80211_hw *hw,
1103 struct ieee80211_vif *vif)
1104 {
1105 struct ath_softc *sc = hw->priv;
1106 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1107
1108 ath_dbg(common, CONFIG, "Detach Interface\n");
1109
1110 ath9k_ps_wakeup(sc);
1111 mutex_lock(&sc->mutex);
1112
1113 sc->nvifs--;
1114
1115 /* Reclaim beacon resources */
1116 if (ath9k_uses_beacons(vif->type))
1117 ath9k_reclaim_beacon(sc, vif);
1118
1119 ath9k_calculate_summary_state(hw, NULL);
1120
1121 mutex_unlock(&sc->mutex);
1122 ath9k_ps_restore(sc);
1123 }
1124
1125 static void ath9k_enable_ps(struct ath_softc *sc)
1126 {
1127 struct ath_hw *ah = sc->sc_ah;
1128 struct ath_common *common = ath9k_hw_common(ah);
1129
1130 sc->ps_enabled = true;
1131 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1132 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
1133 ah->imask |= ATH9K_INT_TIM_TIMER;
1134 ath9k_hw_set_interrupts(ah);
1135 }
1136 ath9k_hw_setrxabort(ah, 1);
1137 }
1138 ath_dbg(common, PS, "PowerSave enabled\n");
1139 }
1140
1141 static void ath9k_disable_ps(struct ath_softc *sc)
1142 {
1143 struct ath_hw *ah = sc->sc_ah;
1144 struct ath_common *common = ath9k_hw_common(ah);
1145
1146 sc->ps_enabled = false;
1147 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
1148 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1149 ath9k_hw_setrxabort(ah, 0);
1150 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
1151 PS_WAIT_FOR_CAB |
1152 PS_WAIT_FOR_PSPOLL_DATA |
1153 PS_WAIT_FOR_TX_ACK);
1154 if (ah->imask & ATH9K_INT_TIM_TIMER) {
1155 ah->imask &= ~ATH9K_INT_TIM_TIMER;
1156 ath9k_hw_set_interrupts(ah);
1157 }
1158 }
1159 ath_dbg(common, PS, "PowerSave disabled\n");
1160 }
1161
1162 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
1163 {
1164 struct ath_softc *sc = hw->priv;
1165 struct ath_hw *ah = sc->sc_ah;
1166 struct ath_common *common = ath9k_hw_common(ah);
1167 struct ieee80211_conf *conf = &hw->conf;
1168 bool reset_channel = false;
1169
1170 ath9k_ps_wakeup(sc);
1171 mutex_lock(&sc->mutex);
1172
1173 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
1174 sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
1175 if (sc->ps_idle)
1176 ath_cancel_work(sc);
1177 else
1178 /*
1179 * The chip needs a reset to properly wake up from
1180 * full sleep
1181 */
1182 reset_channel = ah->chip_fullsleep;
1183 }
1184
1185 /*
1186 * We just prepare to enable PS. We have to wait until our AP has
1187 * ACK'd our null data frame to disable RX otherwise we'll ignore
1188 * those ACKs and end up retransmitting the same null data frames.
1189 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
1190 */
1191 if (changed & IEEE80211_CONF_CHANGE_PS) {
1192 unsigned long flags;
1193 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1194 if (conf->flags & IEEE80211_CONF_PS)
1195 ath9k_enable_ps(sc);
1196 else
1197 ath9k_disable_ps(sc);
1198 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1199 }
1200
1201 if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
1202 if (conf->flags & IEEE80211_CONF_MONITOR) {
1203 ath_dbg(common, CONFIG, "Monitor mode is enabled\n");
1204 sc->sc_ah->is_monitoring = true;
1205 } else {
1206 ath_dbg(common, CONFIG, "Monitor mode is disabled\n");
1207 sc->sc_ah->is_monitoring = false;
1208 }
1209 }
1210
1211 if ((changed & IEEE80211_CONF_CHANGE_CHANNEL) || reset_channel) {
1212 struct ieee80211_channel *curchan = hw->conf.channel;
1213 int pos = curchan->hw_value;
1214 int old_pos = -1;
1215 unsigned long flags;
1216
1217 if (ah->curchan)
1218 old_pos = ah->curchan - &ah->channels[0];
1219
1220 ath_dbg(common, CONFIG, "Set channel: %d MHz type: %d\n",
1221 curchan->center_freq, conf->channel_type);
1222
1223 /* update survey stats for the old channel before switching */
1224 spin_lock_irqsave(&common->cc_lock, flags);
1225 ath_update_survey_stats(sc);
1226 spin_unlock_irqrestore(&common->cc_lock, flags);
1227
1228 /*
1229 * Preserve the current channel values, before updating
1230 * the same channel
1231 */
1232 if (ah->curchan && (old_pos == pos))
1233 ath9k_hw_getnf(ah, ah->curchan);
1234
1235 ath9k_cmn_update_ichannel(&sc->sc_ah->channels[pos],
1236 curchan, conf->channel_type);
1237
1238 /*
1239 * If the operating channel changes, change the survey in-use flags
1240 * along with it.
1241 * Reset the survey data for the new channel, unless we're switching
1242 * back to the operating channel from an off-channel operation.
1243 */
1244 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) &&
1245 sc->cur_survey != &sc->survey[pos]) {
1246
1247 if (sc->cur_survey)
1248 sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE;
1249
1250 sc->cur_survey = &sc->survey[pos];
1251
1252 memset(sc->cur_survey, 0, sizeof(struct survey_info));
1253 sc->cur_survey->filled |= SURVEY_INFO_IN_USE;
1254 } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) {
1255 memset(&sc->survey[pos], 0, sizeof(struct survey_info));
1256 }
1257
1258 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
1259 ath_err(common, "Unable to set channel\n");
1260 mutex_unlock(&sc->mutex);
1261 return -EINVAL;
1262 }
1263
1264 /*
1265 * The most recent snapshot of channel->noisefloor for the old
1266 * channel is only available after the hardware reset. Copy it to
1267 * the survey stats now.
1268 */
1269 if (old_pos >= 0)
1270 ath_update_survey_nf(sc, old_pos);
1271 }
1272
1273 if (changed & IEEE80211_CONF_CHANGE_POWER) {
1274 ath_dbg(common, CONFIG, "Set power: %d\n", conf->power_level);
1275 sc->config.txpowlimit = 2 * conf->power_level;
1276 ath9k_cmn_update_txpow(ah, sc->curtxpow,
1277 sc->config.txpowlimit, &sc->curtxpow);
1278 }
1279
1280 mutex_unlock(&sc->mutex);
1281 ath9k_ps_restore(sc);
1282
1283 return 0;
1284 }
1285
1286 #define SUPPORTED_FILTERS \
1287 (FIF_PROMISC_IN_BSS | \
1288 FIF_ALLMULTI | \
1289 FIF_CONTROL | \
1290 FIF_PSPOLL | \
1291 FIF_OTHER_BSS | \
1292 FIF_BCN_PRBRESP_PROMISC | \
1293 FIF_PROBE_REQ | \
1294 FIF_FCSFAIL)
1295
1296 /* FIXME: sc->sc_full_reset ? */
1297 static void ath9k_configure_filter(struct ieee80211_hw *hw,
1298 unsigned int changed_flags,
1299 unsigned int *total_flags,
1300 u64 multicast)
1301 {
1302 struct ath_softc *sc = hw->priv;
1303 u32 rfilt;
1304
1305 changed_flags &= SUPPORTED_FILTERS;
1306 *total_flags &= SUPPORTED_FILTERS;
1307
1308 sc->rx.rxfilter = *total_flags;
1309 ath9k_ps_wakeup(sc);
1310 rfilt = ath_calcrxfilter(sc);
1311 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
1312 ath9k_ps_restore(sc);
1313
1314 ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n",
1315 rfilt);
1316 }
1317
1318 static int ath9k_sta_add(struct ieee80211_hw *hw,
1319 struct ieee80211_vif *vif,
1320 struct ieee80211_sta *sta)
1321 {
1322 struct ath_softc *sc = hw->priv;
1323 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1324 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1325 struct ieee80211_key_conf ps_key = { };
1326
1327 ath_node_attach(sc, sta, vif);
1328
1329 if (vif->type != NL80211_IFTYPE_AP &&
1330 vif->type != NL80211_IFTYPE_AP_VLAN)
1331 return 0;
1332
1333 an->ps_key = ath_key_config(common, vif, sta, &ps_key);
1334
1335 return 0;
1336 }
1337
1338 static void ath9k_del_ps_key(struct ath_softc *sc,
1339 struct ieee80211_vif *vif,
1340 struct ieee80211_sta *sta)
1341 {
1342 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1343 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1344 struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key };
1345
1346 if (!an->ps_key)
1347 return;
1348
1349 ath_key_delete(common, &ps_key);
1350 }
1351
1352 static int ath9k_sta_remove(struct ieee80211_hw *hw,
1353 struct ieee80211_vif *vif,
1354 struct ieee80211_sta *sta)
1355 {
1356 struct ath_softc *sc = hw->priv;
1357
1358 ath9k_del_ps_key(sc, vif, sta);
1359 ath_node_detach(sc, sta);
1360
1361 return 0;
1362 }
1363
1364 static void ath9k_sta_notify(struct ieee80211_hw *hw,
1365 struct ieee80211_vif *vif,
1366 enum sta_notify_cmd cmd,
1367 struct ieee80211_sta *sta)
1368 {
1369 struct ath_softc *sc = hw->priv;
1370 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1371
1372 if (!sta->ht_cap.ht_supported)
1373 return;
1374
1375 switch (cmd) {
1376 case STA_NOTIFY_SLEEP:
1377 an->sleeping = true;
1378 ath_tx_aggr_sleep(sta, sc, an);
1379 break;
1380 case STA_NOTIFY_AWAKE:
1381 an->sleeping = false;
1382 ath_tx_aggr_wakeup(sc, an);
1383 break;
1384 }
1385 }
1386
1387 static int ath9k_conf_tx(struct ieee80211_hw *hw,
1388 struct ieee80211_vif *vif, u16 queue,
1389 const struct ieee80211_tx_queue_params *params)
1390 {
1391 struct ath_softc *sc = hw->priv;
1392 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1393 struct ath_txq *txq;
1394 struct ath9k_tx_queue_info qi;
1395 int ret = 0;
1396
1397 if (queue >= WME_NUM_AC)
1398 return 0;
1399
1400 txq = sc->tx.txq_map[queue];
1401
1402 ath9k_ps_wakeup(sc);
1403 mutex_lock(&sc->mutex);
1404
1405 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
1406
1407 qi.tqi_aifs = params->aifs;
1408 qi.tqi_cwmin = params->cw_min;
1409 qi.tqi_cwmax = params->cw_max;
1410 qi.tqi_burstTime = params->txop;
1411
1412 ath_dbg(common, CONFIG,
1413 "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
1414 queue, txq->axq_qnum, params->aifs, params->cw_min,
1415 params->cw_max, params->txop);
1416
1417 ret = ath_txq_update(sc, txq->axq_qnum, &qi);
1418 if (ret)
1419 ath_err(common, "TXQ Update failed\n");
1420
1421 if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC)
1422 if (queue == WME_AC_BE && !ret)
1423 ath_beaconq_config(sc);
1424
1425 mutex_unlock(&sc->mutex);
1426 ath9k_ps_restore(sc);
1427
1428 return ret;
1429 }
1430
1431 static int ath9k_set_key(struct ieee80211_hw *hw,
1432 enum set_key_cmd cmd,
1433 struct ieee80211_vif *vif,
1434 struct ieee80211_sta *sta,
1435 struct ieee80211_key_conf *key)
1436 {
1437 struct ath_softc *sc = hw->priv;
1438 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1439 int ret = 0;
1440
1441 if (ath9k_modparam_nohwcrypt)
1442 return -ENOSPC;
1443
1444 if ((vif->type == NL80211_IFTYPE_ADHOC ||
1445 vif->type == NL80211_IFTYPE_MESH_POINT) &&
1446 (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
1447 key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
1448 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
1449 /*
1450 * For now, disable hw crypto for the RSN IBSS group keys. This
1451 * could be optimized in the future to use a modified key cache
1452 * design to support per-STA RX GTK, but until that gets
1453 * implemented, use of software crypto for group addressed
1454 * frames is a acceptable to allow RSN IBSS to be used.
1455 */
1456 return -EOPNOTSUPP;
1457 }
1458
1459 mutex_lock(&sc->mutex);
1460 ath9k_ps_wakeup(sc);
1461 ath_dbg(common, CONFIG, "Set HW Key\n");
1462
1463 switch (cmd) {
1464 case SET_KEY:
1465 if (sta)
1466 ath9k_del_ps_key(sc, vif, sta);
1467
1468 ret = ath_key_config(common, vif, sta, key);
1469 if (ret >= 0) {
1470 key->hw_key_idx = ret;
1471 /* push IV and Michael MIC generation to stack */
1472 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
1473 if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
1474 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
1475 if (sc->sc_ah->sw_mgmt_crypto &&
1476 key->cipher == WLAN_CIPHER_SUITE_CCMP)
1477 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
1478 ret = 0;
1479 }
1480 break;
1481 case DISABLE_KEY:
1482 ath_key_delete(common, key);
1483 break;
1484 default:
1485 ret = -EINVAL;
1486 }
1487
1488 ath9k_ps_restore(sc);
1489 mutex_unlock(&sc->mutex);
1490
1491 return ret;
1492 }
1493 static void ath9k_bss_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
1494 {
1495 struct ath_softc *sc = data;
1496 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1497 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
1498 struct ath_vif *avp = (void *)vif->drv_priv;
1499 unsigned long flags;
1500 /*
1501 * Skip iteration if primary station vif's bss info
1502 * was not changed
1503 */
1504 if (test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags))
1505 return;
1506
1507 if (bss_conf->assoc) {
1508 set_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags);
1509 avp->primary_sta_vif = true;
1510 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1511 common->curaid = bss_conf->aid;
1512 ath9k_hw_write_associd(sc->sc_ah);
1513 ath_dbg(common, CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
1514 bss_conf->aid, common->curbssid);
1515 ath_beacon_config(sc, vif);
1516 /*
1517 * Request a re-configuration of Beacon related timers
1518 * on the receipt of the first Beacon frame (i.e.,
1519 * after time sync with the AP).
1520 */
1521 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1522 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
1523 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1524
1525 /* Reset rssi stats */
1526 sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
1527 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
1528
1529 ath_start_rx_poll(sc, 3);
1530
1531 if (!common->disable_ani) {
1532 set_bit(SC_OP_ANI_RUN, &sc->sc_flags);
1533 ath_start_ani(common);
1534 }
1535
1536 }
1537 }
1538
1539 static void ath9k_config_bss(struct ath_softc *sc, struct ieee80211_vif *vif)
1540 {
1541 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1542 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
1543 struct ath_vif *avp = (void *)vif->drv_priv;
1544
1545 if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION)
1546 return;
1547
1548 /* Reconfigure bss info */
1549 if (avp->primary_sta_vif && !bss_conf->assoc) {
1550 ath_dbg(common, CONFIG, "Bss Info DISASSOC %d, bssid %pM\n",
1551 common->curaid, common->curbssid);
1552 clear_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags);
1553 clear_bit(SC_OP_BEACONS, &sc->sc_flags);
1554 avp->primary_sta_vif = false;
1555 memset(common->curbssid, 0, ETH_ALEN);
1556 common->curaid = 0;
1557 }
1558
1559 ieee80211_iterate_active_interfaces_atomic(
1560 sc->hw, ath9k_bss_iter, sc);
1561
1562 /*
1563 * None of station vifs are associated.
1564 * Clear bssid & aid
1565 */
1566 if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
1567 ath9k_hw_write_associd(sc->sc_ah);
1568 clear_bit(SC_OP_ANI_RUN, &sc->sc_flags);
1569 del_timer_sync(&common->ani.timer);
1570 del_timer_sync(&sc->rx_poll_timer);
1571 memset(&sc->caldata, 0, sizeof(sc->caldata));
1572 }
1573 }
1574
1575 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
1576 struct ieee80211_vif *vif,
1577 struct ieee80211_bss_conf *bss_conf,
1578 u32 changed)
1579 {
1580 struct ath_softc *sc = hw->priv;
1581 struct ath_hw *ah = sc->sc_ah;
1582 struct ath_common *common = ath9k_hw_common(ah);
1583 struct ath_vif *avp = (void *)vif->drv_priv;
1584 int slottime;
1585
1586 ath9k_ps_wakeup(sc);
1587 mutex_lock(&sc->mutex);
1588
1589 if (changed & BSS_CHANGED_ASSOC) {
1590 ath9k_config_bss(sc, vif);
1591
1592 ath_dbg(common, CONFIG, "BSSID: %pM aid: 0x%x\n",
1593 common->curbssid, common->curaid);
1594 }
1595
1596 if (changed & BSS_CHANGED_IBSS) {
1597 /* There can be only one vif available */
1598 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1599 common->curaid = bss_conf->aid;
1600 ath9k_hw_write_associd(sc->sc_ah);
1601
1602 if (bss_conf->ibss_joined) {
1603 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
1604
1605 if (!common->disable_ani) {
1606 set_bit(SC_OP_ANI_RUN, &sc->sc_flags);
1607 ath_start_ani(common);
1608 }
1609
1610 } else {
1611 clear_bit(SC_OP_ANI_RUN, &sc->sc_flags);
1612 del_timer_sync(&common->ani.timer);
1613 del_timer_sync(&sc->rx_poll_timer);
1614 }
1615 }
1616
1617 /*
1618 * In case of AP mode, the HW TSF has to be reset
1619 * when the beacon interval changes.
1620 */
1621 if ((changed & BSS_CHANGED_BEACON_INT) &&
1622 (vif->type == NL80211_IFTYPE_AP))
1623 set_bit(SC_OP_TSF_RESET, &sc->sc_flags);
1624
1625 /* Configure beaconing (AP, IBSS, MESH) */
1626 if (ath9k_uses_beacons(vif->type) &&
1627 ((changed & BSS_CHANGED_BEACON) ||
1628 (changed & BSS_CHANGED_BEACON_ENABLED) ||
1629 (changed & BSS_CHANGED_BEACON_INT))) {
1630 ath9k_set_beaconing_status(sc, false);
1631 if (bss_conf->enable_beacon)
1632 ath_beacon_alloc(sc, vif);
1633 else
1634 avp->is_bslot_active = false;
1635 ath_beacon_config(sc, vif);
1636 ath9k_set_beaconing_status(sc, true);
1637 }
1638
1639 if (changed & BSS_CHANGED_ERP_SLOT) {
1640 if (bss_conf->use_short_slot)
1641 slottime = 9;
1642 else
1643 slottime = 20;
1644 if (vif->type == NL80211_IFTYPE_AP) {
1645 /*
1646 * Defer update, so that connected stations can adjust
1647 * their settings at the same time.
1648 * See beacon.c for more details
1649 */
1650 sc->beacon.slottime = slottime;
1651 sc->beacon.updateslot = UPDATE;
1652 } else {
1653 ah->slottime = slottime;
1654 ath9k_hw_init_global_settings(ah);
1655 }
1656 }
1657
1658 mutex_unlock(&sc->mutex);
1659 ath9k_ps_restore(sc);
1660 }
1661
1662 static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1663 {
1664 struct ath_softc *sc = hw->priv;
1665 u64 tsf;
1666
1667 mutex_lock(&sc->mutex);
1668 ath9k_ps_wakeup(sc);
1669 tsf = ath9k_hw_gettsf64(sc->sc_ah);
1670 ath9k_ps_restore(sc);
1671 mutex_unlock(&sc->mutex);
1672
1673 return tsf;
1674 }
1675
1676 static void ath9k_set_tsf(struct ieee80211_hw *hw,
1677 struct ieee80211_vif *vif,
1678 u64 tsf)
1679 {
1680 struct ath_softc *sc = hw->priv;
1681
1682 mutex_lock(&sc->mutex);
1683 ath9k_ps_wakeup(sc);
1684 ath9k_hw_settsf64(sc->sc_ah, tsf);
1685 ath9k_ps_restore(sc);
1686 mutex_unlock(&sc->mutex);
1687 }
1688
1689 static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1690 {
1691 struct ath_softc *sc = hw->priv;
1692
1693 mutex_lock(&sc->mutex);
1694
1695 ath9k_ps_wakeup(sc);
1696 ath9k_hw_reset_tsf(sc->sc_ah);
1697 ath9k_ps_restore(sc);
1698
1699 mutex_unlock(&sc->mutex);
1700 }
1701
1702 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
1703 struct ieee80211_vif *vif,
1704 enum ieee80211_ampdu_mlme_action action,
1705 struct ieee80211_sta *sta,
1706 u16 tid, u16 *ssn, u8 buf_size)
1707 {
1708 struct ath_softc *sc = hw->priv;
1709 int ret = 0;
1710
1711 local_bh_disable();
1712
1713 switch (action) {
1714 case IEEE80211_AMPDU_RX_START:
1715 break;
1716 case IEEE80211_AMPDU_RX_STOP:
1717 break;
1718 case IEEE80211_AMPDU_TX_START:
1719 ath9k_ps_wakeup(sc);
1720 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
1721 if (!ret)
1722 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
1723 ath9k_ps_restore(sc);
1724 break;
1725 case IEEE80211_AMPDU_TX_STOP:
1726 ath9k_ps_wakeup(sc);
1727 ath_tx_aggr_stop(sc, sta, tid);
1728 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
1729 ath9k_ps_restore(sc);
1730 break;
1731 case IEEE80211_AMPDU_TX_OPERATIONAL:
1732 ath9k_ps_wakeup(sc);
1733 ath_tx_aggr_resume(sc, sta, tid);
1734 ath9k_ps_restore(sc);
1735 break;
1736 default:
1737 ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
1738 }
1739
1740 local_bh_enable();
1741
1742 return ret;
1743 }
1744
1745 static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
1746 struct survey_info *survey)
1747 {
1748 struct ath_softc *sc = hw->priv;
1749 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1750 struct ieee80211_supported_band *sband;
1751 struct ieee80211_channel *chan;
1752 unsigned long flags;
1753 int pos;
1754
1755 spin_lock_irqsave(&common->cc_lock, flags);
1756 if (idx == 0)
1757 ath_update_survey_stats(sc);
1758
1759 sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
1760 if (sband && idx >= sband->n_channels) {
1761 idx -= sband->n_channels;
1762 sband = NULL;
1763 }
1764
1765 if (!sband)
1766 sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
1767
1768 if (!sband || idx >= sband->n_channels) {
1769 spin_unlock_irqrestore(&common->cc_lock, flags);
1770 return -ENOENT;
1771 }
1772
1773 chan = &sband->channels[idx];
1774 pos = chan->hw_value;
1775 memcpy(survey, &sc->survey[pos], sizeof(*survey));
1776 survey->channel = chan;
1777 spin_unlock_irqrestore(&common->cc_lock, flags);
1778
1779 return 0;
1780 }
1781
1782 static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
1783 {
1784 struct ath_softc *sc = hw->priv;
1785 struct ath_hw *ah = sc->sc_ah;
1786
1787 mutex_lock(&sc->mutex);
1788 ah->coverage_class = coverage_class;
1789
1790 ath9k_ps_wakeup(sc);
1791 ath9k_hw_init_global_settings(ah);
1792 ath9k_ps_restore(sc);
1793
1794 mutex_unlock(&sc->mutex);
1795 }
1796
1797 static void ath9k_flush(struct ieee80211_hw *hw, bool drop)
1798 {
1799 struct ath_softc *sc = hw->priv;
1800 struct ath_hw *ah = sc->sc_ah;
1801 struct ath_common *common = ath9k_hw_common(ah);
1802 int timeout = 200; /* ms */
1803 int i, j;
1804 bool drain_txq;
1805
1806 mutex_lock(&sc->mutex);
1807 cancel_delayed_work_sync(&sc->tx_complete_work);
1808
1809 if (ah->ah_flags & AH_UNPLUGGED) {
1810 ath_dbg(common, ANY, "Device has been unplugged!\n");
1811 mutex_unlock(&sc->mutex);
1812 return;
1813 }
1814
1815 if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
1816 ath_dbg(common, ANY, "Device not present\n");
1817 mutex_unlock(&sc->mutex);
1818 return;
1819 }
1820
1821 for (j = 0; j < timeout; j++) {
1822 bool npend = false;
1823
1824 if (j)
1825 usleep_range(1000, 2000);
1826
1827 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1828 if (!ATH_TXQ_SETUP(sc, i))
1829 continue;
1830
1831 npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]);
1832
1833 if (npend)
1834 break;
1835 }
1836
1837 if (!npend)
1838 break;
1839 }
1840
1841 if (drop) {
1842 ath9k_ps_wakeup(sc);
1843 spin_lock_bh(&sc->sc_pcu_lock);
1844 drain_txq = ath_drain_all_txq(sc, false);
1845 spin_unlock_bh(&sc->sc_pcu_lock);
1846
1847 if (!drain_txq)
1848 ath_reset(sc, false);
1849
1850 ath9k_ps_restore(sc);
1851 ieee80211_wake_queues(hw);
1852 }
1853
1854 ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0);
1855 mutex_unlock(&sc->mutex);
1856 }
1857
1858 static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
1859 {
1860 struct ath_softc *sc = hw->priv;
1861 int i;
1862
1863 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1864 if (!ATH_TXQ_SETUP(sc, i))
1865 continue;
1866
1867 if (ath9k_has_pending_frames(sc, &sc->tx.txq[i]))
1868 return true;
1869 }
1870 return false;
1871 }
1872
1873 static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
1874 {
1875 struct ath_softc *sc = hw->priv;
1876 struct ath_hw *ah = sc->sc_ah;
1877 struct ieee80211_vif *vif;
1878 struct ath_vif *avp;
1879 struct ath_buf *bf;
1880 struct ath_tx_status ts;
1881 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1882 int status;
1883
1884 vif = sc->beacon.bslot[0];
1885 if (!vif)
1886 return 0;
1887
1888 avp = (void *)vif->drv_priv;
1889 if (!avp->is_bslot_active)
1890 return 0;
1891
1892 if (!sc->beacon.tx_processed && !edma) {
1893 tasklet_disable(&sc->bcon_tasklet);
1894
1895 bf = avp->av_bcbuf;
1896 if (!bf || !bf->bf_mpdu)
1897 goto skip;
1898
1899 status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
1900 if (status == -EINPROGRESS)
1901 goto skip;
1902
1903 sc->beacon.tx_processed = true;
1904 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
1905
1906 skip:
1907 tasklet_enable(&sc->bcon_tasklet);
1908 }
1909
1910 return sc->beacon.tx_last;
1911 }
1912
1913 static int ath9k_get_stats(struct ieee80211_hw *hw,
1914 struct ieee80211_low_level_stats *stats)
1915 {
1916 struct ath_softc *sc = hw->priv;
1917 struct ath_hw *ah = sc->sc_ah;
1918 struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats;
1919
1920 stats->dot11ACKFailureCount = mib_stats->ackrcv_bad;
1921 stats->dot11RTSFailureCount = mib_stats->rts_bad;
1922 stats->dot11FCSErrorCount = mib_stats->fcs_bad;
1923 stats->dot11RTSSuccessCount = mib_stats->rts_good;
1924 return 0;
1925 }
1926
1927 static u32 fill_chainmask(u32 cap, u32 new)
1928 {
1929 u32 filled = 0;
1930 int i;
1931
1932 for (i = 0; cap && new; i++, cap >>= 1) {
1933 if (!(cap & BIT(0)))
1934 continue;
1935
1936 if (new & BIT(0))
1937 filled |= BIT(i);
1938
1939 new >>= 1;
1940 }
1941
1942 return filled;
1943 }
1944
1945 static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
1946 {
1947 struct ath_softc *sc = hw->priv;
1948 struct ath_hw *ah = sc->sc_ah;
1949
1950 if (!rx_ant || !tx_ant)
1951 return -EINVAL;
1952
1953 sc->ant_rx = rx_ant;
1954 sc->ant_tx = tx_ant;
1955
1956 if (ah->caps.rx_chainmask == 1)
1957 return 0;
1958
1959 /* AR9100 runs into calibration issues if not all rx chains are enabled */
1960 if (AR_SREV_9100(ah))
1961 ah->rxchainmask = 0x7;
1962 else
1963 ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant);
1964
1965 ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant);
1966 ath9k_reload_chainmask_settings(sc);
1967
1968 return 0;
1969 }
1970
1971 static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
1972 {
1973 struct ath_softc *sc = hw->priv;
1974
1975 *tx_ant = sc->ant_tx;
1976 *rx_ant = sc->ant_rx;
1977 return 0;
1978 }
1979
1980 #ifdef CONFIG_ATH9K_DEBUGFS
1981
1982 /* Ethtool support for get-stats */
1983
1984 #define AMKSTR(nm) #nm "_BE", #nm "_BK", #nm "_VI", #nm "_VO"
1985 static const char ath9k_gstrings_stats[][ETH_GSTRING_LEN] = {
1986 "tx_pkts_nic",
1987 "tx_bytes_nic",
1988 "rx_pkts_nic",
1989 "rx_bytes_nic",
1990 AMKSTR(d_tx_pkts),
1991 AMKSTR(d_tx_bytes),
1992 AMKSTR(d_tx_mpdus_queued),
1993 AMKSTR(d_tx_mpdus_completed),
1994 AMKSTR(d_tx_mpdu_xretries),
1995 AMKSTR(d_tx_aggregates),
1996 AMKSTR(d_tx_ampdus_queued_hw),
1997 AMKSTR(d_tx_ampdus_queued_sw),
1998 AMKSTR(d_tx_ampdus_completed),
1999 AMKSTR(d_tx_ampdu_retries),
2000 AMKSTR(d_tx_ampdu_xretries),
2001 AMKSTR(d_tx_fifo_underrun),
2002 AMKSTR(d_tx_op_exceeded),
2003 AMKSTR(d_tx_timer_expiry),
2004 AMKSTR(d_tx_desc_cfg_err),
2005 AMKSTR(d_tx_data_underrun),
2006 AMKSTR(d_tx_delim_underrun),
2007
2008 "d_rx_decrypt_crc_err",
2009 "d_rx_phy_err",
2010 "d_rx_mic_err",
2011 "d_rx_pre_delim_crc_err",
2012 "d_rx_post_delim_crc_err",
2013 "d_rx_decrypt_busy_err",
2014
2015 "d_rx_phyerr_radar",
2016 "d_rx_phyerr_ofdm_timing",
2017 "d_rx_phyerr_cck_timing",
2018
2019 };
2020 #define ATH9K_SSTATS_LEN ARRAY_SIZE(ath9k_gstrings_stats)
2021
2022 static void ath9k_get_et_strings(struct ieee80211_hw *hw,
2023 struct ieee80211_vif *vif,
2024 u32 sset, u8 *data)
2025 {
2026 if (sset == ETH_SS_STATS)
2027 memcpy(data, *ath9k_gstrings_stats,
2028 sizeof(ath9k_gstrings_stats));
2029 }
2030
2031 static int ath9k_get_et_sset_count(struct ieee80211_hw *hw,
2032 struct ieee80211_vif *vif, int sset)
2033 {
2034 if (sset == ETH_SS_STATS)
2035 return ATH9K_SSTATS_LEN;
2036 return 0;
2037 }
2038
2039 #define PR_QNUM(_n) (sc->tx.txq_map[_n]->axq_qnum)
2040 #define AWDATA(elem) \
2041 do { \
2042 data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_BE)].elem; \
2043 data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_BK)].elem; \
2044 data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_VI)].elem; \
2045 data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_VO)].elem; \
2046 } while (0)
2047
2048 #define AWDATA_RX(elem) \
2049 do { \
2050 data[i++] = sc->debug.stats.rxstats.elem; \
2051 } while (0)
2052
2053 static void ath9k_get_et_stats(struct ieee80211_hw *hw,
2054 struct ieee80211_vif *vif,
2055 struct ethtool_stats *stats, u64 *data)
2056 {
2057 struct ath_softc *sc = hw->priv;
2058 int i = 0;
2059
2060 data[i++] = (sc->debug.stats.txstats[PR_QNUM(WME_AC_BE)].tx_pkts_all +
2061 sc->debug.stats.txstats[PR_QNUM(WME_AC_BK)].tx_pkts_all +
2062 sc->debug.stats.txstats[PR_QNUM(WME_AC_VI)].tx_pkts_all +
2063 sc->debug.stats.txstats[PR_QNUM(WME_AC_VO)].tx_pkts_all);
2064 data[i++] = (sc->debug.stats.txstats[PR_QNUM(WME_AC_BE)].tx_bytes_all +
2065 sc->debug.stats.txstats[PR_QNUM(WME_AC_BK)].tx_bytes_all +
2066 sc->debug.stats.txstats[PR_QNUM(WME_AC_VI)].tx_bytes_all +
2067 sc->debug.stats.txstats[PR_QNUM(WME_AC_VO)].tx_bytes_all);
2068 AWDATA_RX(rx_pkts_all);
2069 AWDATA_RX(rx_bytes_all);
2070
2071 AWDATA(tx_pkts_all);
2072 AWDATA(tx_bytes_all);
2073 AWDATA(queued);
2074 AWDATA(completed);
2075 AWDATA(xretries);
2076 AWDATA(a_aggr);
2077 AWDATA(a_queued_hw);
2078 AWDATA(a_queued_sw);
2079 AWDATA(a_completed);
2080 AWDATA(a_retries);
2081 AWDATA(a_xretries);
2082 AWDATA(fifo_underrun);
2083 AWDATA(xtxop);
2084 AWDATA(timer_exp);
2085 AWDATA(desc_cfg_err);
2086 AWDATA(data_underrun);
2087 AWDATA(delim_underrun);
2088
2089 AWDATA_RX(decrypt_crc_err);
2090 AWDATA_RX(phy_err);
2091 AWDATA_RX(mic_err);
2092 AWDATA_RX(pre_delim_crc_err);
2093 AWDATA_RX(post_delim_crc_err);
2094 AWDATA_RX(decrypt_busy_err);
2095
2096 AWDATA_RX(phy_err_stats[ATH9K_PHYERR_RADAR]);
2097 AWDATA_RX(phy_err_stats[ATH9K_PHYERR_OFDM_TIMING]);
2098 AWDATA_RX(phy_err_stats[ATH9K_PHYERR_CCK_TIMING]);
2099
2100 WARN_ON(i != ATH9K_SSTATS_LEN);
2101 }
2102
2103 /* End of ethtool get-stats functions */
2104
2105 #endif
2106
2107
2108 struct ieee80211_ops ath9k_ops = {
2109 .tx = ath9k_tx,
2110 .start = ath9k_start,
2111 .stop = ath9k_stop,
2112 .add_interface = ath9k_add_interface,
2113 .change_interface = ath9k_change_interface,
2114 .remove_interface = ath9k_remove_interface,
2115 .config = ath9k_config,
2116 .configure_filter = ath9k_configure_filter,
2117 .sta_add = ath9k_sta_add,
2118 .sta_remove = ath9k_sta_remove,
2119 .sta_notify = ath9k_sta_notify,
2120 .conf_tx = ath9k_conf_tx,
2121 .bss_info_changed = ath9k_bss_info_changed,
2122 .set_key = ath9k_set_key,
2123 .get_tsf = ath9k_get_tsf,
2124 .set_tsf = ath9k_set_tsf,
2125 .reset_tsf = ath9k_reset_tsf,
2126 .ampdu_action = ath9k_ampdu_action,
2127 .get_survey = ath9k_get_survey,
2128 .rfkill_poll = ath9k_rfkill_poll_state,
2129 .set_coverage_class = ath9k_set_coverage_class,
2130 .flush = ath9k_flush,
2131 .tx_frames_pending = ath9k_tx_frames_pending,
2132 .tx_last_beacon = ath9k_tx_last_beacon,
2133 .get_stats = ath9k_get_stats,
2134 .set_antenna = ath9k_set_antenna,
2135 .get_antenna = ath9k_get_antenna,
2136
2137 #ifdef CONFIG_ATH9K_DEBUGFS
2138 .get_et_sset_count = ath9k_get_et_sset_count,
2139 .get_et_stats = ath9k_get_et_stats,
2140 .get_et_strings = ath9k_get_et_strings,
2141 #endif
2142 };
Linux kernel - Deliverables
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