2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/nl80211.h>
20 #define ATH_PCI_VERSION "0.1"
22 static char *dev_info
= "ath9k";
24 MODULE_AUTHOR("Atheros Communications");
25 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
26 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
27 MODULE_LICENSE("Dual BSD/GPL");
29 static int modparam_nohwcrypt
;
30 module_param_named(nohwcrypt
, modparam_nohwcrypt
, int, 0444);
31 MODULE_PARM_DESC(nohwcrypt
, "Disable hardware encryption");
33 /* We use the hw_value as an index into our private channel structure */
35 #define CHAN2G(_freq, _idx) { \
36 .center_freq = (_freq), \
41 #define CHAN5G(_freq, _idx) { \
42 .band = IEEE80211_BAND_5GHZ, \
43 .center_freq = (_freq), \
48 /* Some 2 GHz radios are actually tunable on 2312-2732
49 * on 5 MHz steps, we support the channels which we know
50 * we have calibration data for all cards though to make
52 static struct ieee80211_channel ath9k_2ghz_chantable
[] = {
53 CHAN2G(2412, 0), /* Channel 1 */
54 CHAN2G(2417, 1), /* Channel 2 */
55 CHAN2G(2422, 2), /* Channel 3 */
56 CHAN2G(2427, 3), /* Channel 4 */
57 CHAN2G(2432, 4), /* Channel 5 */
58 CHAN2G(2437, 5), /* Channel 6 */
59 CHAN2G(2442, 6), /* Channel 7 */
60 CHAN2G(2447, 7), /* Channel 8 */
61 CHAN2G(2452, 8), /* Channel 9 */
62 CHAN2G(2457, 9), /* Channel 10 */
63 CHAN2G(2462, 10), /* Channel 11 */
64 CHAN2G(2467, 11), /* Channel 12 */
65 CHAN2G(2472, 12), /* Channel 13 */
66 CHAN2G(2484, 13), /* Channel 14 */
69 /* Some 5 GHz radios are actually tunable on XXXX-YYYY
70 * on 5 MHz steps, we support the channels which we know
71 * we have calibration data for all cards though to make
73 static struct ieee80211_channel ath9k_5ghz_chantable
[] = {
74 /* _We_ call this UNII 1 */
75 CHAN5G(5180, 14), /* Channel 36 */
76 CHAN5G(5200, 15), /* Channel 40 */
77 CHAN5G(5220, 16), /* Channel 44 */
78 CHAN5G(5240, 17), /* Channel 48 */
79 /* _We_ call this UNII 2 */
80 CHAN5G(5260, 18), /* Channel 52 */
81 CHAN5G(5280, 19), /* Channel 56 */
82 CHAN5G(5300, 20), /* Channel 60 */
83 CHAN5G(5320, 21), /* Channel 64 */
84 /* _We_ call this "Middle band" */
85 CHAN5G(5500, 22), /* Channel 100 */
86 CHAN5G(5520, 23), /* Channel 104 */
87 CHAN5G(5540, 24), /* Channel 108 */
88 CHAN5G(5560, 25), /* Channel 112 */
89 CHAN5G(5580, 26), /* Channel 116 */
90 CHAN5G(5600, 27), /* Channel 120 */
91 CHAN5G(5620, 28), /* Channel 124 */
92 CHAN5G(5640, 29), /* Channel 128 */
93 CHAN5G(5660, 30), /* Channel 132 */
94 CHAN5G(5680, 31), /* Channel 136 */
95 CHAN5G(5700, 32), /* Channel 140 */
96 /* _We_ call this UNII 3 */
97 CHAN5G(5745, 33), /* Channel 149 */
98 CHAN5G(5765, 34), /* Channel 153 */
99 CHAN5G(5785, 35), /* Channel 157 */
100 CHAN5G(5805, 36), /* Channel 161 */
101 CHAN5G(5825, 37), /* Channel 165 */
104 static void ath_cache_conf_rate(struct ath_softc
*sc
,
105 struct ieee80211_conf
*conf
)
107 switch (conf
->channel
->band
) {
108 case IEEE80211_BAND_2GHZ
:
109 if (conf_is_ht20(conf
))
111 sc
->hw_rate_table
[ATH9K_MODE_11NG_HT20
];
112 else if (conf_is_ht40_minus(conf
))
114 sc
->hw_rate_table
[ATH9K_MODE_11NG_HT40MINUS
];
115 else if (conf_is_ht40_plus(conf
))
117 sc
->hw_rate_table
[ATH9K_MODE_11NG_HT40PLUS
];
120 sc
->hw_rate_table
[ATH9K_MODE_11G
];
122 case IEEE80211_BAND_5GHZ
:
123 if (conf_is_ht20(conf
))
125 sc
->hw_rate_table
[ATH9K_MODE_11NA_HT20
];
126 else if (conf_is_ht40_minus(conf
))
128 sc
->hw_rate_table
[ATH9K_MODE_11NA_HT40MINUS
];
129 else if (conf_is_ht40_plus(conf
))
131 sc
->hw_rate_table
[ATH9K_MODE_11NA_HT40PLUS
];
134 sc
->hw_rate_table
[ATH9K_MODE_11A
];
142 static void ath_update_txpow(struct ath_softc
*sc
)
144 struct ath_hw
*ah
= sc
->sc_ah
;
147 if (sc
->curtxpow
!= sc
->config
.txpowlimit
) {
148 ath9k_hw_set_txpowerlimit(ah
, sc
->config
.txpowlimit
);
149 /* read back in case value is clamped */
150 ath9k_hw_getcapability(ah
, ATH9K_CAP_TXPOW
, 1, &txpow
);
151 sc
->curtxpow
= txpow
;
155 static u8
parse_mpdudensity(u8 mpdudensity
)
158 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
159 * 0 for no restriction
168 switch (mpdudensity
) {
174 /* Our lower layer calculations limit our precision to
190 static void ath_setup_rates(struct ath_softc
*sc
, enum ieee80211_band band
)
192 struct ath_rate_table
*rate_table
= NULL
;
193 struct ieee80211_supported_band
*sband
;
194 struct ieee80211_rate
*rate
;
198 case IEEE80211_BAND_2GHZ
:
199 rate_table
= sc
->hw_rate_table
[ATH9K_MODE_11G
];
201 case IEEE80211_BAND_5GHZ
:
202 rate_table
= sc
->hw_rate_table
[ATH9K_MODE_11A
];
208 if (rate_table
== NULL
)
211 sband
= &sc
->sbands
[band
];
212 rate
= sc
->rates
[band
];
214 if (rate_table
->rate_cnt
> ATH_RATE_MAX
)
215 maxrates
= ATH_RATE_MAX
;
217 maxrates
= rate_table
->rate_cnt
;
219 for (i
= 0; i
< maxrates
; i
++) {
220 rate
[i
].bitrate
= rate_table
->info
[i
].ratekbps
/ 100;
221 rate
[i
].hw_value
= rate_table
->info
[i
].ratecode
;
222 if (rate_table
->info
[i
].short_preamble
) {
223 rate
[i
].hw_value_short
= rate_table
->info
[i
].ratecode
|
224 rate_table
->info
[i
].short_preamble
;
225 rate
[i
].flags
= IEEE80211_RATE_SHORT_PREAMBLE
;
229 DPRINTF(sc
, ATH_DBG_CONFIG
, "Rate: %2dMbps, ratecode: %2d\n",
230 rate
[i
].bitrate
/ 10, rate
[i
].hw_value
);
235 * Set/change channels. If the channel is really being changed, it's done
236 * by reseting the chip. To accomplish this we must first cleanup any pending
237 * DMA, then restart stuff.
239 int ath_set_channel(struct ath_softc
*sc
, struct ieee80211_hw
*hw
,
240 struct ath9k_channel
*hchan
)
242 struct ath_hw
*ah
= sc
->sc_ah
;
243 bool fastcc
= true, stopped
;
244 struct ieee80211_channel
*channel
= hw
->conf
.channel
;
247 if (sc
->sc_flags
& SC_OP_INVALID
)
253 * This is only performed if the channel settings have
256 * To switch channels clear any pending DMA operations;
257 * wait long enough for the RX fifo to drain, reset the
258 * hardware at the new frequency, and then re-enable
259 * the relevant bits of the h/w.
261 ath9k_hw_set_interrupts(ah
, 0);
262 ath_drain_all_txq(sc
, false);
263 stopped
= ath_stoprecv(sc
);
265 /* XXX: do not flush receive queue here. We don't want
266 * to flush data frames already in queue because of
267 * changing channel. */
269 if (!stopped
|| (sc
->sc_flags
& SC_OP_FULL_RESET
))
272 DPRINTF(sc
, ATH_DBG_CONFIG
,
273 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
274 sc
->sc_ah
->curchan
->channel
,
275 channel
->center_freq
, sc
->tx_chan_width
);
277 spin_lock_bh(&sc
->sc_resetlock
);
279 r
= ath9k_hw_reset(ah
, hchan
, fastcc
);
281 DPRINTF(sc
, ATH_DBG_FATAL
,
282 "Unable to reset channel (%u Mhz) "
284 channel
->center_freq
, r
);
285 spin_unlock_bh(&sc
->sc_resetlock
);
288 spin_unlock_bh(&sc
->sc_resetlock
);
290 sc
->sc_flags
&= ~SC_OP_FULL_RESET
;
292 if (ath_startrecv(sc
) != 0) {
293 DPRINTF(sc
, ATH_DBG_FATAL
,
294 "Unable to restart recv logic\n");
298 ath_cache_conf_rate(sc
, &hw
->conf
);
299 ath_update_txpow(sc
);
300 ath9k_hw_set_interrupts(ah
, sc
->imask
);
301 ath9k_ps_restore(sc
);
306 * This routine performs the periodic noise floor calibration function
307 * that is used to adjust and optimize the chip performance. This
308 * takes environmental changes (location, temperature) into account.
309 * When the task is complete, it reschedules itself depending on the
310 * appropriate interval that was calculated.
312 static void ath_ani_calibrate(unsigned long data
)
314 struct ath_softc
*sc
= (struct ath_softc
*)data
;
315 struct ath_hw
*ah
= sc
->sc_ah
;
316 bool longcal
= false;
317 bool shortcal
= false;
318 bool aniflag
= false;
319 unsigned int timestamp
= jiffies_to_msecs(jiffies
);
320 u32 cal_interval
, short_cal_interval
;
322 short_cal_interval
= (ah
->opmode
== NL80211_IFTYPE_AP
) ?
323 ATH_AP_SHORT_CALINTERVAL
: ATH_STA_SHORT_CALINTERVAL
;
326 * don't calibrate when we're scanning.
327 * we are most likely not on our home channel.
329 if (sc
->sc_flags
& SC_OP_SCANNING
)
332 /* Long calibration runs independently of short calibration. */
333 if ((timestamp
- sc
->ani
.longcal_timer
) >= ATH_LONG_CALINTERVAL
) {
335 DPRINTF(sc
, ATH_DBG_ANI
, "longcal @%lu\n", jiffies
);
336 sc
->ani
.longcal_timer
= timestamp
;
339 /* Short calibration applies only while caldone is false */
340 if (!sc
->ani
.caldone
) {
341 if ((timestamp
- sc
->ani
.shortcal_timer
) >= short_cal_interval
) {
343 DPRINTF(sc
, ATH_DBG_ANI
, "shortcal @%lu\n", jiffies
);
344 sc
->ani
.shortcal_timer
= timestamp
;
345 sc
->ani
.resetcal_timer
= timestamp
;
348 if ((timestamp
- sc
->ani
.resetcal_timer
) >=
349 ATH_RESTART_CALINTERVAL
) {
350 sc
->ani
.caldone
= ath9k_hw_reset_calvalid(ah
);
352 sc
->ani
.resetcal_timer
= timestamp
;
356 /* Verify whether we must check ANI */
357 if ((timestamp
- sc
->ani
.checkani_timer
) >= ATH_ANI_POLLINTERVAL
) {
359 sc
->ani
.checkani_timer
= timestamp
;
362 /* Skip all processing if there's nothing to do. */
363 if (longcal
|| shortcal
|| aniflag
) {
364 /* Call ANI routine if necessary */
366 ath9k_hw_ani_monitor(ah
, &sc
->nodestats
, ah
->curchan
);
368 /* Perform calibration if necessary */
369 if (longcal
|| shortcal
) {
370 sc
->ani
.caldone
= ath9k_hw_calibrate(ah
, ah
->curchan
,
371 sc
->rx_chainmask
, longcal
);
374 sc
->ani
.noise_floor
= ath9k_hw_getchan_noise(ah
,
377 DPRINTF(sc
, ATH_DBG_ANI
," calibrate chan %u/%x nf: %d\n",
378 ah
->curchan
->channel
, ah
->curchan
->channelFlags
,
379 sc
->ani
.noise_floor
);
385 * Set timer interval based on previous results.
386 * The interval must be the shortest necessary to satisfy ANI,
387 * short calibration and long calibration.
389 cal_interval
= ATH_LONG_CALINTERVAL
;
390 if (sc
->sc_ah
->config
.enable_ani
)
391 cal_interval
= min(cal_interval
, (u32
)ATH_ANI_POLLINTERVAL
);
392 if (!sc
->ani
.caldone
)
393 cal_interval
= min(cal_interval
, (u32
)short_cal_interval
);
395 mod_timer(&sc
->ani
.timer
, jiffies
+ msecs_to_jiffies(cal_interval
));
398 static void ath_start_ani(struct ath_softc
*sc
)
400 unsigned long timestamp
= jiffies_to_msecs(jiffies
);
402 sc
->ani
.longcal_timer
= timestamp
;
403 sc
->ani
.shortcal_timer
= timestamp
;
404 sc
->ani
.checkani_timer
= timestamp
;
406 mod_timer(&sc
->ani
.timer
,
407 jiffies
+ msecs_to_jiffies(ATH_ANI_POLLINTERVAL
));
411 * Update tx/rx chainmask. For legacy association,
412 * hard code chainmask to 1x1, for 11n association, use
413 * the chainmask configuration, for bt coexistence, use
414 * the chainmask configuration even in legacy mode.
416 void ath_update_chainmask(struct ath_softc
*sc
, int is_ht
)
419 (sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_BT_COEX
)) {
420 sc
->tx_chainmask
= sc
->sc_ah
->caps
.tx_chainmask
;
421 sc
->rx_chainmask
= sc
->sc_ah
->caps
.rx_chainmask
;
423 sc
->tx_chainmask
= 1;
424 sc
->rx_chainmask
= 1;
427 DPRINTF(sc
, ATH_DBG_CONFIG
, "tx chmask: %d, rx chmask: %d\n",
428 sc
->tx_chainmask
, sc
->rx_chainmask
);
431 static void ath_node_attach(struct ath_softc
*sc
, struct ieee80211_sta
*sta
)
435 an
= (struct ath_node
*)sta
->drv_priv
;
437 if (sc
->sc_flags
& SC_OP_TXAGGR
) {
438 ath_tx_node_init(sc
, an
);
439 an
->maxampdu
= 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR
+
440 sta
->ht_cap
.ampdu_factor
);
441 an
->mpdudensity
= parse_mpdudensity(sta
->ht_cap
.ampdu_density
);
445 static void ath_node_detach(struct ath_softc
*sc
, struct ieee80211_sta
*sta
)
447 struct ath_node
*an
= (struct ath_node
*)sta
->drv_priv
;
449 if (sc
->sc_flags
& SC_OP_TXAGGR
)
450 ath_tx_node_cleanup(sc
, an
);
453 static void ath9k_tasklet(unsigned long data
)
455 struct ath_softc
*sc
= (struct ath_softc
*)data
;
456 u32 status
= sc
->intrstatus
;
458 if (status
& ATH9K_INT_FATAL
) {
459 ath_reset(sc
, false);
463 if (status
& (ATH9K_INT_RX
| ATH9K_INT_RXEOL
| ATH9K_INT_RXORN
)) {
464 spin_lock_bh(&sc
->rx
.rxflushlock
);
465 ath_rx_tasklet(sc
, 0);
466 spin_unlock_bh(&sc
->rx
.rxflushlock
);
469 if (status
& ATH9K_INT_TX
)
472 /* re-enable hardware interrupt */
473 ath9k_hw_set_interrupts(sc
->sc_ah
, sc
->imask
);
476 irqreturn_t
ath_isr(int irq
, void *dev
)
478 #define SCHED_INTR ( \
488 struct ath_softc
*sc
= dev
;
489 struct ath_hw
*ah
= sc
->sc_ah
;
490 enum ath9k_int status
;
494 * The hardware is not ready/present, don't
495 * touch anything. Note this can happen early
496 * on if the IRQ is shared.
498 if (sc
->sc_flags
& SC_OP_INVALID
)
503 /* shared irq, not for us */
505 if (!ath9k_hw_intrpend(ah
)) {
506 ath9k_ps_restore(sc
);
511 * Figure out the reason(s) for the interrupt. Note
512 * that the hal returns a pseudo-ISR that may include
513 * bits we haven't explicitly enabled so we mask the
514 * value to insure we only process bits we requested.
516 ath9k_hw_getisr(ah
, &status
); /* NB: clears ISR too */
517 status
&= sc
->imask
; /* discard unasked-for bits */
520 * If there are no status bits set, then this interrupt was not
521 * for me (should have been caught above).
524 ath9k_ps_restore(sc
);
528 /* Cache the status */
529 sc
->intrstatus
= status
;
531 if (status
& SCHED_INTR
)
535 * If a FATAL or RXORN interrupt is received, we have to reset the
538 if (status
& (ATH9K_INT_FATAL
| ATH9K_INT_RXORN
))
541 if (status
& ATH9K_INT_SWBA
)
542 tasklet_schedule(&sc
->bcon_tasklet
);
544 if (status
& ATH9K_INT_TXURN
)
545 ath9k_hw_updatetxtriglevel(ah
, true);
547 if (status
& ATH9K_INT_MIB
) {
549 * Disable interrupts until we service the MIB
550 * interrupt; otherwise it will continue to
553 ath9k_hw_set_interrupts(ah
, 0);
555 * Let the hal handle the event. We assume
556 * it will clear whatever condition caused
559 ath9k_hw_procmibevent(ah
, &sc
->nodestats
);
560 ath9k_hw_set_interrupts(ah
, sc
->imask
);
563 if (status
& ATH9K_INT_TIM_TIMER
) {
564 if (!(ah
->caps
.hw_caps
& ATH9K_HW_CAP_AUTOSLEEP
)) {
565 /* Clear RxAbort bit so that we can
567 ath9k_hw_setpower(ah
, ATH9K_PM_AWAKE
);
568 ath9k_hw_setrxabort(ah
, 0);
570 sc
->sc_flags
|= SC_OP_WAIT_FOR_BEACON
;
576 ath9k_ps_restore(sc
);
577 ath_debug_stat_interrupt(sc
, status
);
580 /* turn off every interrupt except SWBA */
581 ath9k_hw_set_interrupts(ah
, (sc
->imask
& ATH9K_INT_SWBA
));
582 tasklet_schedule(&sc
->intr_tq
);
590 static u32
ath_get_extchanmode(struct ath_softc
*sc
,
591 struct ieee80211_channel
*chan
,
592 enum nl80211_channel_type channel_type
)
596 switch (chan
->band
) {
597 case IEEE80211_BAND_2GHZ
:
598 switch(channel_type
) {
599 case NL80211_CHAN_NO_HT
:
600 case NL80211_CHAN_HT20
:
601 chanmode
= CHANNEL_G_HT20
;
603 case NL80211_CHAN_HT40PLUS
:
604 chanmode
= CHANNEL_G_HT40PLUS
;
606 case NL80211_CHAN_HT40MINUS
:
607 chanmode
= CHANNEL_G_HT40MINUS
;
611 case IEEE80211_BAND_5GHZ
:
612 switch(channel_type
) {
613 case NL80211_CHAN_NO_HT
:
614 case NL80211_CHAN_HT20
:
615 chanmode
= CHANNEL_A_HT20
;
617 case NL80211_CHAN_HT40PLUS
:
618 chanmode
= CHANNEL_A_HT40PLUS
;
620 case NL80211_CHAN_HT40MINUS
:
621 chanmode
= CHANNEL_A_HT40MINUS
;
632 static int ath_setkey_tkip(struct ath_softc
*sc
, u16 keyix
, const u8
*key
,
633 struct ath9k_keyval
*hk
, const u8
*addr
,
639 key_txmic
= key
+ NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY
;
640 key_rxmic
= key
+ NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY
;
644 * Group key installation - only two key cache entries are used
645 * regardless of splitmic capability since group key is only
646 * used either for TX or RX.
649 memcpy(hk
->kv_mic
, key_txmic
, sizeof(hk
->kv_mic
));
650 memcpy(hk
->kv_txmic
, key_txmic
, sizeof(hk
->kv_mic
));
652 memcpy(hk
->kv_mic
, key_rxmic
, sizeof(hk
->kv_mic
));
653 memcpy(hk
->kv_txmic
, key_rxmic
, sizeof(hk
->kv_mic
));
655 return ath9k_hw_set_keycache_entry(sc
->sc_ah
, keyix
, hk
, addr
);
658 /* TX and RX keys share the same key cache entry. */
659 memcpy(hk
->kv_mic
, key_rxmic
, sizeof(hk
->kv_mic
));
660 memcpy(hk
->kv_txmic
, key_txmic
, sizeof(hk
->kv_txmic
));
661 return ath9k_hw_set_keycache_entry(sc
->sc_ah
, keyix
, hk
, addr
);
664 /* Separate key cache entries for TX and RX */
666 /* TX key goes at first index, RX key at +32. */
667 memcpy(hk
->kv_mic
, key_txmic
, sizeof(hk
->kv_mic
));
668 if (!ath9k_hw_set_keycache_entry(sc
->sc_ah
, keyix
, hk
, NULL
)) {
669 /* TX MIC entry failed. No need to proceed further */
670 DPRINTF(sc
, ATH_DBG_FATAL
,
671 "Setting TX MIC Key Failed\n");
675 memcpy(hk
->kv_mic
, key_rxmic
, sizeof(hk
->kv_mic
));
676 /* XXX delete tx key on failure? */
677 return ath9k_hw_set_keycache_entry(sc
->sc_ah
, keyix
+ 32, hk
, addr
);
680 static int ath_reserve_key_cache_slot_tkip(struct ath_softc
*sc
)
684 for (i
= IEEE80211_WEP_NKID
; i
< sc
->keymax
/ 2; i
++) {
685 if (test_bit(i
, sc
->keymap
) ||
686 test_bit(i
+ 64, sc
->keymap
))
687 continue; /* At least one part of TKIP key allocated */
689 (test_bit(i
+ 32, sc
->keymap
) ||
690 test_bit(i
+ 64 + 32, sc
->keymap
)))
691 continue; /* At least one part of TKIP key allocated */
693 /* Found a free slot for a TKIP key */
699 static int ath_reserve_key_cache_slot(struct ath_softc
*sc
)
703 /* First, try to find slots that would not be available for TKIP. */
705 for (i
= IEEE80211_WEP_NKID
; i
< sc
->keymax
/ 4; i
++) {
706 if (!test_bit(i
, sc
->keymap
) &&
707 (test_bit(i
+ 32, sc
->keymap
) ||
708 test_bit(i
+ 64, sc
->keymap
) ||
709 test_bit(i
+ 64 + 32, sc
->keymap
)))
711 if (!test_bit(i
+ 32, sc
->keymap
) &&
712 (test_bit(i
, sc
->keymap
) ||
713 test_bit(i
+ 64, sc
->keymap
) ||
714 test_bit(i
+ 64 + 32, sc
->keymap
)))
716 if (!test_bit(i
+ 64, sc
->keymap
) &&
717 (test_bit(i
, sc
->keymap
) ||
718 test_bit(i
+ 32, sc
->keymap
) ||
719 test_bit(i
+ 64 + 32, sc
->keymap
)))
721 if (!test_bit(i
+ 64 + 32, sc
->keymap
) &&
722 (test_bit(i
, sc
->keymap
) ||
723 test_bit(i
+ 32, sc
->keymap
) ||
724 test_bit(i
+ 64, sc
->keymap
)))
728 for (i
= IEEE80211_WEP_NKID
; i
< sc
->keymax
/ 2; i
++) {
729 if (!test_bit(i
, sc
->keymap
) &&
730 test_bit(i
+ 64, sc
->keymap
))
732 if (test_bit(i
, sc
->keymap
) &&
733 !test_bit(i
+ 64, sc
->keymap
))
738 /* No partially used TKIP slots, pick any available slot */
739 for (i
= IEEE80211_WEP_NKID
; i
< sc
->keymax
; i
++) {
740 /* Do not allow slots that could be needed for TKIP group keys
741 * to be used. This limitation could be removed if we know that
742 * TKIP will not be used. */
743 if (i
>= 64 && i
< 64 + IEEE80211_WEP_NKID
)
746 if (i
>= 32 && i
< 32 + IEEE80211_WEP_NKID
)
748 if (i
>= 64 + 32 && i
< 64 + 32 + IEEE80211_WEP_NKID
)
752 if (!test_bit(i
, sc
->keymap
))
753 return i
; /* Found a free slot for a key */
756 /* No free slot found */
760 static int ath_key_config(struct ath_softc
*sc
,
761 struct ieee80211_vif
*vif
,
762 struct ieee80211_sta
*sta
,
763 struct ieee80211_key_conf
*key
)
765 struct ath9k_keyval hk
;
766 const u8
*mac
= NULL
;
770 memset(&hk
, 0, sizeof(hk
));
774 hk
.kv_type
= ATH9K_CIPHER_WEP
;
777 hk
.kv_type
= ATH9K_CIPHER_TKIP
;
780 hk
.kv_type
= ATH9K_CIPHER_AES_CCM
;
786 hk
.kv_len
= key
->keylen
;
787 memcpy(hk
.kv_val
, key
->key
, key
->keylen
);
789 if (!(key
->flags
& IEEE80211_KEY_FLAG_PAIRWISE
)) {
790 /* For now, use the default keys for broadcast keys. This may
791 * need to change with virtual interfaces. */
793 } else if (key
->keyidx
) {
798 if (vif
->type
!= NL80211_IFTYPE_AP
) {
799 /* Only keyidx 0 should be used with unicast key, but
800 * allow this for client mode for now. */
809 if (key
->alg
== ALG_TKIP
)
810 idx
= ath_reserve_key_cache_slot_tkip(sc
);
812 idx
= ath_reserve_key_cache_slot(sc
);
814 return -ENOSPC
; /* no free key cache entries */
817 if (key
->alg
== ALG_TKIP
)
818 ret
= ath_setkey_tkip(sc
, idx
, key
->key
, &hk
, mac
,
819 vif
->type
== NL80211_IFTYPE_AP
);
821 ret
= ath9k_hw_set_keycache_entry(sc
->sc_ah
, idx
, &hk
, mac
);
826 set_bit(idx
, sc
->keymap
);
827 if (key
->alg
== ALG_TKIP
) {
828 set_bit(idx
+ 64, sc
->keymap
);
830 set_bit(idx
+ 32, sc
->keymap
);
831 set_bit(idx
+ 64 + 32, sc
->keymap
);
838 static void ath_key_delete(struct ath_softc
*sc
, struct ieee80211_key_conf
*key
)
840 ath9k_hw_keyreset(sc
->sc_ah
, key
->hw_key_idx
);
841 if (key
->hw_key_idx
< IEEE80211_WEP_NKID
)
844 clear_bit(key
->hw_key_idx
, sc
->keymap
);
845 if (key
->alg
!= ALG_TKIP
)
848 clear_bit(key
->hw_key_idx
+ 64, sc
->keymap
);
850 clear_bit(key
->hw_key_idx
+ 32, sc
->keymap
);
851 clear_bit(key
->hw_key_idx
+ 64 + 32, sc
->keymap
);
855 static void setup_ht_cap(struct ath_softc
*sc
,
856 struct ieee80211_sta_ht_cap
*ht_info
)
858 #define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3 /* 2 ^ 16 */
859 #define ATH9K_HT_CAP_MPDUDENSITY_8 0x6 /* 8 usec */
861 ht_info
->ht_supported
= true;
862 ht_info
->cap
= IEEE80211_HT_CAP_SUP_WIDTH_20_40
|
863 IEEE80211_HT_CAP_SM_PS
|
864 IEEE80211_HT_CAP_SGI_40
|
865 IEEE80211_HT_CAP_DSSSCCK40
;
867 ht_info
->ampdu_factor
= ATH9K_HT_CAP_MAXRXAMPDU_65536
;
868 ht_info
->ampdu_density
= ATH9K_HT_CAP_MPDUDENSITY_8
;
870 /* set up supported mcs set */
871 memset(&ht_info
->mcs
, 0, sizeof(ht_info
->mcs
));
873 switch(sc
->rx_chainmask
) {
875 ht_info
->mcs
.rx_mask
[0] = 0xff;
881 ht_info
->mcs
.rx_mask
[0] = 0xff;
882 ht_info
->mcs
.rx_mask
[1] = 0xff;
886 ht_info
->mcs
.tx_params
= IEEE80211_HT_MCS_TX_DEFINED
;
889 static void ath9k_bss_assoc_info(struct ath_softc
*sc
,
890 struct ieee80211_vif
*vif
,
891 struct ieee80211_bss_conf
*bss_conf
)
893 struct ath_vif
*avp
= (void *)vif
->drv_priv
;
895 if (bss_conf
->assoc
) {
896 DPRINTF(sc
, ATH_DBG_CONFIG
, "Bss Info ASSOC %d, bssid: %pM\n",
897 bss_conf
->aid
, sc
->curbssid
);
899 /* New association, store aid */
900 if (avp
->av_opmode
== NL80211_IFTYPE_STATION
) {
901 sc
->curaid
= bss_conf
->aid
;
902 ath9k_hw_write_associd(sc
);
905 /* Configure the beacon */
906 ath_beacon_config(sc
, vif
);
908 /* Reset rssi stats */
909 sc
->nodestats
.ns_avgbrssi
= ATH_RSSI_DUMMY_MARKER
;
910 sc
->nodestats
.ns_avgrssi
= ATH_RSSI_DUMMY_MARKER
;
911 sc
->nodestats
.ns_avgtxrssi
= ATH_RSSI_DUMMY_MARKER
;
912 sc
->nodestats
.ns_avgtxrate
= ATH_RATE_DUMMY_MARKER
;
916 DPRINTF(sc
, ATH_DBG_CONFIG
, "Bss Info DISASSOC\n");
921 /********************************/
923 /********************************/
925 static void ath_led_blink_work(struct work_struct
*work
)
927 struct ath_softc
*sc
= container_of(work
, struct ath_softc
,
928 ath_led_blink_work
.work
);
930 if (!(sc
->sc_flags
& SC_OP_LED_ASSOCIATED
))
933 if ((sc
->led_on_duration
== ATH_LED_ON_DURATION_IDLE
) ||
934 (sc
->led_off_duration
== ATH_LED_OFF_DURATION_IDLE
))
935 ath9k_hw_set_gpio(sc
->sc_ah
, ATH_LED_PIN
, 0);
937 ath9k_hw_set_gpio(sc
->sc_ah
, ATH_LED_PIN
,
938 (sc
->sc_flags
& SC_OP_LED_ON
) ? 1 : 0);
940 queue_delayed_work(sc
->hw
->workqueue
, &sc
->ath_led_blink_work
,
941 (sc
->sc_flags
& SC_OP_LED_ON
) ?
942 msecs_to_jiffies(sc
->led_off_duration
) :
943 msecs_to_jiffies(sc
->led_on_duration
));
945 sc
->led_on_duration
= sc
->led_on_cnt
?
946 max((ATH_LED_ON_DURATION_IDLE
- sc
->led_on_cnt
), 25) :
947 ATH_LED_ON_DURATION_IDLE
;
948 sc
->led_off_duration
= sc
->led_off_cnt
?
949 max((ATH_LED_OFF_DURATION_IDLE
- sc
->led_off_cnt
), 10) :
950 ATH_LED_OFF_DURATION_IDLE
;
951 sc
->led_on_cnt
= sc
->led_off_cnt
= 0;
952 if (sc
->sc_flags
& SC_OP_LED_ON
)
953 sc
->sc_flags
&= ~SC_OP_LED_ON
;
955 sc
->sc_flags
|= SC_OP_LED_ON
;
958 static void ath_led_brightness(struct led_classdev
*led_cdev
,
959 enum led_brightness brightness
)
961 struct ath_led
*led
= container_of(led_cdev
, struct ath_led
, led_cdev
);
962 struct ath_softc
*sc
= led
->sc
;
964 switch (brightness
) {
966 if (led
->led_type
== ATH_LED_ASSOC
||
967 led
->led_type
== ATH_LED_RADIO
) {
968 ath9k_hw_set_gpio(sc
->sc_ah
, ATH_LED_PIN
,
969 (led
->led_type
== ATH_LED_RADIO
));
970 sc
->sc_flags
&= ~SC_OP_LED_ASSOCIATED
;
971 if (led
->led_type
== ATH_LED_RADIO
)
972 sc
->sc_flags
&= ~SC_OP_LED_ON
;
978 if (led
->led_type
== ATH_LED_ASSOC
) {
979 sc
->sc_flags
|= SC_OP_LED_ASSOCIATED
;
980 queue_delayed_work(sc
->hw
->workqueue
,
981 &sc
->ath_led_blink_work
, 0);
982 } else if (led
->led_type
== ATH_LED_RADIO
) {
983 ath9k_hw_set_gpio(sc
->sc_ah
, ATH_LED_PIN
, 0);
984 sc
->sc_flags
|= SC_OP_LED_ON
;
994 static int ath_register_led(struct ath_softc
*sc
, struct ath_led
*led
,
1000 led
->led_cdev
.name
= led
->name
;
1001 led
->led_cdev
.default_trigger
= trigger
;
1002 led
->led_cdev
.brightness_set
= ath_led_brightness
;
1004 ret
= led_classdev_register(wiphy_dev(sc
->hw
->wiphy
), &led
->led_cdev
);
1006 DPRINTF(sc
, ATH_DBG_FATAL
,
1007 "Failed to register led:%s", led
->name
);
1009 led
->registered
= 1;
1013 static void ath_unregister_led(struct ath_led
*led
)
1015 if (led
->registered
) {
1016 led_classdev_unregister(&led
->led_cdev
);
1017 led
->registered
= 0;
1021 static void ath_deinit_leds(struct ath_softc
*sc
)
1023 cancel_delayed_work_sync(&sc
->ath_led_blink_work
);
1024 ath_unregister_led(&sc
->assoc_led
);
1025 sc
->sc_flags
&= ~SC_OP_LED_ASSOCIATED
;
1026 ath_unregister_led(&sc
->tx_led
);
1027 ath_unregister_led(&sc
->rx_led
);
1028 ath_unregister_led(&sc
->radio_led
);
1029 ath9k_hw_set_gpio(sc
->sc_ah
, ATH_LED_PIN
, 1);
1032 static void ath_init_leds(struct ath_softc
*sc
)
1037 /* Configure gpio 1 for output */
1038 ath9k_hw_cfg_output(sc
->sc_ah
, ATH_LED_PIN
,
1039 AR_GPIO_OUTPUT_MUX_AS_OUTPUT
);
1040 /* LED off, active low */
1041 ath9k_hw_set_gpio(sc
->sc_ah
, ATH_LED_PIN
, 1);
1043 INIT_DELAYED_WORK(&sc
->ath_led_blink_work
, ath_led_blink_work
);
1045 trigger
= ieee80211_get_radio_led_name(sc
->hw
);
1046 snprintf(sc
->radio_led
.name
, sizeof(sc
->radio_led
.name
),
1047 "ath9k-%s::radio", wiphy_name(sc
->hw
->wiphy
));
1048 ret
= ath_register_led(sc
, &sc
->radio_led
, trigger
);
1049 sc
->radio_led
.led_type
= ATH_LED_RADIO
;
1053 trigger
= ieee80211_get_assoc_led_name(sc
->hw
);
1054 snprintf(sc
->assoc_led
.name
, sizeof(sc
->assoc_led
.name
),
1055 "ath9k-%s::assoc", wiphy_name(sc
->hw
->wiphy
));
1056 ret
= ath_register_led(sc
, &sc
->assoc_led
, trigger
);
1057 sc
->assoc_led
.led_type
= ATH_LED_ASSOC
;
1061 trigger
= ieee80211_get_tx_led_name(sc
->hw
);
1062 snprintf(sc
->tx_led
.name
, sizeof(sc
->tx_led
.name
),
1063 "ath9k-%s::tx", wiphy_name(sc
->hw
->wiphy
));
1064 ret
= ath_register_led(sc
, &sc
->tx_led
, trigger
);
1065 sc
->tx_led
.led_type
= ATH_LED_TX
;
1069 trigger
= ieee80211_get_rx_led_name(sc
->hw
);
1070 snprintf(sc
->rx_led
.name
, sizeof(sc
->rx_led
.name
),
1071 "ath9k-%s::rx", wiphy_name(sc
->hw
->wiphy
));
1072 ret
= ath_register_led(sc
, &sc
->rx_led
, trigger
);
1073 sc
->rx_led
.led_type
= ATH_LED_RX
;
1080 ath_deinit_leds(sc
);
1083 void ath_radio_enable(struct ath_softc
*sc
)
1085 struct ath_hw
*ah
= sc
->sc_ah
;
1086 struct ieee80211_channel
*channel
= sc
->hw
->conf
.channel
;
1089 ath9k_ps_wakeup(sc
);
1090 ath9k_hw_configpcipowersave(ah
, 0);
1092 spin_lock_bh(&sc
->sc_resetlock
);
1093 r
= ath9k_hw_reset(ah
, ah
->curchan
, false);
1095 DPRINTF(sc
, ATH_DBG_FATAL
,
1096 "Unable to reset channel %u (%uMhz) ",
1097 "reset status %u\n",
1098 channel
->center_freq
, r
);
1100 spin_unlock_bh(&sc
->sc_resetlock
);
1102 ath_update_txpow(sc
);
1103 if (ath_startrecv(sc
) != 0) {
1104 DPRINTF(sc
, ATH_DBG_FATAL
,
1105 "Unable to restart recv logic\n");
1109 if (sc
->sc_flags
& SC_OP_BEACONS
)
1110 ath_beacon_config(sc
, NULL
); /* restart beacons */
1112 /* Re-Enable interrupts */
1113 ath9k_hw_set_interrupts(ah
, sc
->imask
);
1116 ath9k_hw_cfg_output(ah
, ATH_LED_PIN
,
1117 AR_GPIO_OUTPUT_MUX_AS_OUTPUT
);
1118 ath9k_hw_set_gpio(ah
, ATH_LED_PIN
, 0);
1120 ieee80211_wake_queues(sc
->hw
);
1121 ath9k_ps_restore(sc
);
1124 void ath_radio_disable(struct ath_softc
*sc
)
1126 struct ath_hw
*ah
= sc
->sc_ah
;
1127 struct ieee80211_channel
*channel
= sc
->hw
->conf
.channel
;
1130 ath9k_ps_wakeup(sc
);
1131 ieee80211_stop_queues(sc
->hw
);
1134 ath9k_hw_set_gpio(ah
, ATH_LED_PIN
, 1);
1135 ath9k_hw_cfg_gpio_input(ah
, ATH_LED_PIN
);
1137 /* Disable interrupts */
1138 ath9k_hw_set_interrupts(ah
, 0);
1140 ath_drain_all_txq(sc
, false); /* clear pending tx frames */
1141 ath_stoprecv(sc
); /* turn off frame recv */
1142 ath_flushrecv(sc
); /* flush recv queue */
1144 spin_lock_bh(&sc
->sc_resetlock
);
1145 r
= ath9k_hw_reset(ah
, ah
->curchan
, false);
1147 DPRINTF(sc
, ATH_DBG_FATAL
,
1148 "Unable to reset channel %u (%uMhz) "
1149 "reset status %u\n",
1150 channel
->center_freq
, r
);
1152 spin_unlock_bh(&sc
->sc_resetlock
);
1154 ath9k_hw_phy_disable(ah
);
1155 ath9k_hw_configpcipowersave(ah
, 1);
1156 ath9k_hw_setpower(ah
, ATH9K_PM_FULL_SLEEP
);
1157 ath9k_ps_restore(sc
);
1160 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1162 /*******************/
1164 /*******************/
1166 static bool ath_is_rfkill_set(struct ath_softc
*sc
)
1168 struct ath_hw
*ah
= sc
->sc_ah
;
1170 return ath9k_hw_gpio_get(ah
, ah
->rfkill_gpio
) ==
1171 ah
->rfkill_polarity
;
1174 /* h/w rfkill poll function */
1175 static void ath_rfkill_poll(struct work_struct
*work
)
1177 struct ath_softc
*sc
= container_of(work
, struct ath_softc
,
1178 rf_kill
.rfkill_poll
.work
);
1181 if (sc
->sc_flags
& SC_OP_INVALID
)
1184 radio_on
= !ath_is_rfkill_set(sc
);
1187 * enable/disable radio only when there is a
1188 * state change in RF switch
1190 if (radio_on
== !!(sc
->sc_flags
& SC_OP_RFKILL_HW_BLOCKED
)) {
1191 enum rfkill_state state
;
1193 if (sc
->sc_flags
& SC_OP_RFKILL_SW_BLOCKED
) {
1194 state
= radio_on
? RFKILL_STATE_SOFT_BLOCKED
1195 : RFKILL_STATE_HARD_BLOCKED
;
1196 } else if (radio_on
) {
1197 ath_radio_enable(sc
);
1198 state
= RFKILL_STATE_UNBLOCKED
;
1200 ath_radio_disable(sc
);
1201 state
= RFKILL_STATE_HARD_BLOCKED
;
1204 if (state
== RFKILL_STATE_HARD_BLOCKED
)
1205 sc
->sc_flags
|= SC_OP_RFKILL_HW_BLOCKED
;
1207 sc
->sc_flags
&= ~SC_OP_RFKILL_HW_BLOCKED
;
1209 rfkill_force_state(sc
->rf_kill
.rfkill
, state
);
1212 queue_delayed_work(sc
->hw
->workqueue
, &sc
->rf_kill
.rfkill_poll
,
1213 msecs_to_jiffies(ATH_RFKILL_POLL_INTERVAL
));
1216 /* s/w rfkill handler */
1217 static int ath_sw_toggle_radio(void *data
, enum rfkill_state state
)
1219 struct ath_softc
*sc
= data
;
1222 case RFKILL_STATE_SOFT_BLOCKED
:
1223 if (!(sc
->sc_flags
& (SC_OP_RFKILL_HW_BLOCKED
|
1224 SC_OP_RFKILL_SW_BLOCKED
)))
1225 ath_radio_disable(sc
);
1226 sc
->sc_flags
|= SC_OP_RFKILL_SW_BLOCKED
;
1228 case RFKILL_STATE_UNBLOCKED
:
1229 if ((sc
->sc_flags
& SC_OP_RFKILL_SW_BLOCKED
)) {
1230 sc
->sc_flags
&= ~SC_OP_RFKILL_SW_BLOCKED
;
1231 if (sc
->sc_flags
& SC_OP_RFKILL_HW_BLOCKED
) {
1232 DPRINTF(sc
, ATH_DBG_FATAL
, "Can't turn on the"
1233 "radio as it is disabled by h/w\n");
1236 ath_radio_enable(sc
);
1244 /* Init s/w rfkill */
1245 static int ath_init_sw_rfkill(struct ath_softc
*sc
)
1247 sc
->rf_kill
.rfkill
= rfkill_allocate(wiphy_dev(sc
->hw
->wiphy
),
1249 if (!sc
->rf_kill
.rfkill
) {
1250 DPRINTF(sc
, ATH_DBG_FATAL
, "Failed to allocate rfkill\n");
1254 snprintf(sc
->rf_kill
.rfkill_name
, sizeof(sc
->rf_kill
.rfkill_name
),
1255 "ath9k-%s::rfkill", wiphy_name(sc
->hw
->wiphy
));
1256 sc
->rf_kill
.rfkill
->name
= sc
->rf_kill
.rfkill_name
;
1257 sc
->rf_kill
.rfkill
->data
= sc
;
1258 sc
->rf_kill
.rfkill
->toggle_radio
= ath_sw_toggle_radio
;
1259 sc
->rf_kill
.rfkill
->state
= RFKILL_STATE_UNBLOCKED
;
1264 /* Deinitialize rfkill */
1265 static void ath_deinit_rfkill(struct ath_softc
*sc
)
1267 if (sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_RFSILENT
)
1268 cancel_delayed_work_sync(&sc
->rf_kill
.rfkill_poll
);
1270 if (sc
->sc_flags
& SC_OP_RFKILL_REGISTERED
) {
1271 rfkill_unregister(sc
->rf_kill
.rfkill
);
1272 sc
->sc_flags
&= ~SC_OP_RFKILL_REGISTERED
;
1273 sc
->rf_kill
.rfkill
= NULL
;
1277 static int ath_start_rfkill_poll(struct ath_softc
*sc
)
1279 if (sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_RFSILENT
)
1280 queue_delayed_work(sc
->hw
->workqueue
,
1281 &sc
->rf_kill
.rfkill_poll
, 0);
1283 if (!(sc
->sc_flags
& SC_OP_RFKILL_REGISTERED
)) {
1284 if (rfkill_register(sc
->rf_kill
.rfkill
)) {
1285 DPRINTF(sc
, ATH_DBG_FATAL
,
1286 "Unable to register rfkill\n");
1287 rfkill_free(sc
->rf_kill
.rfkill
);
1289 /* Deinitialize the device */
1293 sc
->sc_flags
|= SC_OP_RFKILL_REGISTERED
;
1299 #endif /* CONFIG_RFKILL */
1301 void ath_cleanup(struct ath_softc
*sc
)
1304 free_irq(sc
->irq
, sc
);
1305 ath_bus_cleanup(sc
);
1306 kfree(sc
->sec_wiphy
);
1307 ieee80211_free_hw(sc
->hw
);
1310 void ath_detach(struct ath_softc
*sc
)
1312 struct ieee80211_hw
*hw
= sc
->hw
;
1315 ath9k_ps_wakeup(sc
);
1317 DPRINTF(sc
, ATH_DBG_CONFIG
, "Detach ATH hw\n");
1319 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1320 ath_deinit_rfkill(sc
);
1322 ath_deinit_leds(sc
);
1323 cancel_work_sync(&sc
->chan_work
);
1324 cancel_delayed_work_sync(&sc
->wiphy_work
);
1326 for (i
= 0; i
< sc
->num_sec_wiphy
; i
++) {
1327 struct ath_wiphy
*aphy
= sc
->sec_wiphy
[i
];
1330 sc
->sec_wiphy
[i
] = NULL
;
1331 ieee80211_unregister_hw(aphy
->hw
);
1332 ieee80211_free_hw(aphy
->hw
);
1334 ieee80211_unregister_hw(hw
);
1338 tasklet_kill(&sc
->intr_tq
);
1339 tasklet_kill(&sc
->bcon_tasklet
);
1341 if (!(sc
->sc_flags
& SC_OP_INVALID
))
1342 ath9k_hw_setpower(sc
->sc_ah
, ATH9K_PM_AWAKE
);
1344 /* cleanup tx queues */
1345 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++)
1346 if (ATH_TXQ_SETUP(sc
, i
))
1347 ath_tx_cleanupq(sc
, &sc
->tx
.txq
[i
]);
1349 ath9k_hw_detach(sc
->sc_ah
);
1350 ath9k_exit_debug(sc
);
1351 ath9k_ps_restore(sc
);
1354 static int ath9k_reg_notifier(struct wiphy
*wiphy
,
1355 struct regulatory_request
*request
)
1357 struct ieee80211_hw
*hw
= wiphy_to_ieee80211_hw(wiphy
);
1358 struct ath_wiphy
*aphy
= hw
->priv
;
1359 struct ath_softc
*sc
= aphy
->sc
;
1360 struct ath_regulatory
*reg
= &sc
->sc_ah
->regulatory
;
1362 return ath_reg_notifier_apply(wiphy
, request
, reg
);
1365 static int ath_init(u16 devid
, struct ath_softc
*sc
)
1367 struct ath_hw
*ah
= NULL
;
1372 /* XXX: hardware will not be ready until ath_open() being called */
1373 sc
->sc_flags
|= SC_OP_INVALID
;
1375 if (ath9k_init_debug(sc
) < 0)
1376 printk(KERN_ERR
"Unable to create debugfs files\n");
1378 spin_lock_init(&sc
->wiphy_lock
);
1379 spin_lock_init(&sc
->sc_resetlock
);
1380 spin_lock_init(&sc
->sc_serial_rw
);
1381 mutex_init(&sc
->mutex
);
1382 tasklet_init(&sc
->intr_tq
, ath9k_tasklet
, (unsigned long)sc
);
1383 tasklet_init(&sc
->bcon_tasklet
, ath_beacon_tasklet
,
1387 * Cache line size is used to size and align various
1388 * structures used to communicate with the hardware.
1390 ath_read_cachesize(sc
, &csz
);
1391 /* XXX assert csz is non-zero */
1392 sc
->cachelsz
= csz
<< 2; /* convert to bytes */
1394 ah
= ath9k_hw_attach(devid
, sc
, &status
);
1396 DPRINTF(sc
, ATH_DBG_FATAL
,
1397 "Unable to attach hardware; HAL status %d\n", status
);
1403 /* Get the hardware key cache size. */
1404 sc
->keymax
= ah
->caps
.keycache_size
;
1405 if (sc
->keymax
> ATH_KEYMAX
) {
1406 DPRINTF(sc
, ATH_DBG_ANY
,
1407 "Warning, using only %u entries in %u key cache\n",
1408 ATH_KEYMAX
, sc
->keymax
);
1409 sc
->keymax
= ATH_KEYMAX
;
1413 * Reset the key cache since some parts do not
1414 * reset the contents on initial power up.
1416 for (i
= 0; i
< sc
->keymax
; i
++)
1417 ath9k_hw_keyreset(ah
, (u16
) i
);
1419 error
= ath_regd_init(&sc
->sc_ah
->regulatory
, sc
->hw
->wiphy
,
1420 ath9k_reg_notifier
);
1424 /* default to MONITOR mode */
1425 sc
->sc_ah
->opmode
= NL80211_IFTYPE_MONITOR
;
1427 /* Setup rate tables */
1429 ath_rate_attach(sc
);
1430 ath_setup_rates(sc
, IEEE80211_BAND_2GHZ
);
1431 ath_setup_rates(sc
, IEEE80211_BAND_5GHZ
);
1434 * Allocate hardware transmit queues: one queue for
1435 * beacon frames and one data queue for each QoS
1436 * priority. Note that the hal handles reseting
1437 * these queues at the needed time.
1439 sc
->beacon
.beaconq
= ath_beaconq_setup(ah
);
1440 if (sc
->beacon
.beaconq
== -1) {
1441 DPRINTF(sc
, ATH_DBG_FATAL
,
1442 "Unable to setup a beacon xmit queue\n");
1446 sc
->beacon
.cabq
= ath_txq_setup(sc
, ATH9K_TX_QUEUE_CAB
, 0);
1447 if (sc
->beacon
.cabq
== NULL
) {
1448 DPRINTF(sc
, ATH_DBG_FATAL
,
1449 "Unable to setup CAB xmit queue\n");
1454 sc
->config
.cabqReadytime
= ATH_CABQ_READY_TIME
;
1455 ath_cabq_update(sc
);
1457 for (i
= 0; i
< ARRAY_SIZE(sc
->tx
.hwq_map
); i
++)
1458 sc
->tx
.hwq_map
[i
] = -1;
1460 /* Setup data queues */
1461 /* NB: ensure BK queue is the lowest priority h/w queue */
1462 if (!ath_tx_setup(sc
, ATH9K_WME_AC_BK
)) {
1463 DPRINTF(sc
, ATH_DBG_FATAL
,
1464 "Unable to setup xmit queue for BK traffic\n");
1469 if (!ath_tx_setup(sc
, ATH9K_WME_AC_BE
)) {
1470 DPRINTF(sc
, ATH_DBG_FATAL
,
1471 "Unable to setup xmit queue for BE traffic\n");
1475 if (!ath_tx_setup(sc
, ATH9K_WME_AC_VI
)) {
1476 DPRINTF(sc
, ATH_DBG_FATAL
,
1477 "Unable to setup xmit queue for VI traffic\n");
1481 if (!ath_tx_setup(sc
, ATH9K_WME_AC_VO
)) {
1482 DPRINTF(sc
, ATH_DBG_FATAL
,
1483 "Unable to setup xmit queue for VO traffic\n");
1488 /* Initializes the noise floor to a reasonable default value.
1489 * Later on this will be updated during ANI processing. */
1491 sc
->ani
.noise_floor
= ATH_DEFAULT_NOISE_FLOOR
;
1492 setup_timer(&sc
->ani
.timer
, ath_ani_calibrate
, (unsigned long)sc
);
1494 if (ath9k_hw_getcapability(ah
, ATH9K_CAP_CIPHER
,
1495 ATH9K_CIPHER_TKIP
, NULL
)) {
1497 * Whether we should enable h/w TKIP MIC.
1498 * XXX: if we don't support WME TKIP MIC, then we wouldn't
1499 * report WMM capable, so it's always safe to turn on
1500 * TKIP MIC in this case.
1502 ath9k_hw_setcapability(sc
->sc_ah
, ATH9K_CAP_TKIP_MIC
,
1507 * Check whether the separate key cache entries
1508 * are required to handle both tx+rx MIC keys.
1509 * With split mic keys the number of stations is limited
1510 * to 27 otherwise 59.
1512 if (ath9k_hw_getcapability(ah
, ATH9K_CAP_CIPHER
,
1513 ATH9K_CIPHER_TKIP
, NULL
)
1514 && ath9k_hw_getcapability(ah
, ATH9K_CAP_CIPHER
,
1515 ATH9K_CIPHER_MIC
, NULL
)
1516 && ath9k_hw_getcapability(ah
, ATH9K_CAP_TKIP_SPLIT
,
1520 /* turn on mcast key search if possible */
1521 if (!ath9k_hw_getcapability(ah
, ATH9K_CAP_MCAST_KEYSRCH
, 0, NULL
))
1522 (void)ath9k_hw_setcapability(ah
, ATH9K_CAP_MCAST_KEYSRCH
, 1,
1525 sc
->config
.txpowlimit
= ATH_TXPOWER_MAX
;
1527 /* 11n Capabilities */
1528 if (ah
->caps
.hw_caps
& ATH9K_HW_CAP_HT
) {
1529 sc
->sc_flags
|= SC_OP_TXAGGR
;
1530 sc
->sc_flags
|= SC_OP_RXAGGR
;
1533 sc
->tx_chainmask
= ah
->caps
.tx_chainmask
;
1534 sc
->rx_chainmask
= ah
->caps
.rx_chainmask
;
1536 ath9k_hw_setcapability(ah
, ATH9K_CAP_DIVERSITY
, 1, true, NULL
);
1537 sc
->rx
.defant
= ath9k_hw_getdefantenna(ah
);
1539 if (ah
->caps
.hw_caps
& ATH9K_HW_CAP_BSSIDMASK
)
1540 memcpy(sc
->bssidmask
, ath_bcast_mac
, ETH_ALEN
);
1542 sc
->beacon
.slottime
= ATH9K_SLOT_TIME_9
; /* default to short slot time */
1544 /* initialize beacon slots */
1545 for (i
= 0; i
< ARRAY_SIZE(sc
->beacon
.bslot
); i
++) {
1546 sc
->beacon
.bslot
[i
] = NULL
;
1547 sc
->beacon
.bslot_aphy
[i
] = NULL
;
1550 /* setup channels and rates */
1552 sc
->sbands
[IEEE80211_BAND_2GHZ
].channels
= ath9k_2ghz_chantable
;
1553 sc
->sbands
[IEEE80211_BAND_2GHZ
].bitrates
=
1554 sc
->rates
[IEEE80211_BAND_2GHZ
];
1555 sc
->sbands
[IEEE80211_BAND_2GHZ
].band
= IEEE80211_BAND_2GHZ
;
1556 sc
->sbands
[IEEE80211_BAND_2GHZ
].n_channels
=
1557 ARRAY_SIZE(ath9k_2ghz_chantable
);
1559 if (test_bit(ATH9K_MODE_11A
, sc
->sc_ah
->caps
.wireless_modes
)) {
1560 sc
->sbands
[IEEE80211_BAND_5GHZ
].channels
= ath9k_5ghz_chantable
;
1561 sc
->sbands
[IEEE80211_BAND_5GHZ
].bitrates
=
1562 sc
->rates
[IEEE80211_BAND_5GHZ
];
1563 sc
->sbands
[IEEE80211_BAND_5GHZ
].band
= IEEE80211_BAND_5GHZ
;
1564 sc
->sbands
[IEEE80211_BAND_5GHZ
].n_channels
=
1565 ARRAY_SIZE(ath9k_5ghz_chantable
);
1568 if (sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_BT_COEX
)
1569 ath9k_hw_btcoex_enable(sc
->sc_ah
);
1573 /* cleanup tx queues */
1574 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++)
1575 if (ATH_TXQ_SETUP(sc
, i
))
1576 ath_tx_cleanupq(sc
, &sc
->tx
.txq
[i
]);
1579 ath9k_hw_detach(ah
);
1580 ath9k_exit_debug(sc
);
1585 void ath_set_hw_capab(struct ath_softc
*sc
, struct ieee80211_hw
*hw
)
1587 hw
->flags
= IEEE80211_HW_RX_INCLUDES_FCS
|
1588 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING
|
1589 IEEE80211_HW_SIGNAL_DBM
|
1590 IEEE80211_HW_AMPDU_AGGREGATION
|
1591 IEEE80211_HW_SUPPORTS_PS
|
1592 IEEE80211_HW_PS_NULLFUNC_STACK
|
1593 IEEE80211_HW_SPECTRUM_MGMT
;
1595 if (AR_SREV_9160_10_OR_LATER(sc
->sc_ah
) || modparam_nohwcrypt
)
1596 hw
->flags
|= IEEE80211_HW_MFP_CAPABLE
;
1598 hw
->wiphy
->interface_modes
=
1599 BIT(NL80211_IFTYPE_AP
) |
1600 BIT(NL80211_IFTYPE_STATION
) |
1601 BIT(NL80211_IFTYPE_ADHOC
) |
1602 BIT(NL80211_IFTYPE_MESH_POINT
);
1606 hw
->channel_change_time
= 5000;
1607 hw
->max_listen_interval
= 10;
1608 hw
->max_rate_tries
= ATH_11N_TXMAXTRY
;
1609 hw
->sta_data_size
= sizeof(struct ath_node
);
1610 hw
->vif_data_size
= sizeof(struct ath_vif
);
1612 hw
->rate_control_algorithm
= "ath9k_rate_control";
1614 hw
->wiphy
->bands
[IEEE80211_BAND_2GHZ
] =
1615 &sc
->sbands
[IEEE80211_BAND_2GHZ
];
1616 if (test_bit(ATH9K_MODE_11A
, sc
->sc_ah
->caps
.wireless_modes
))
1617 hw
->wiphy
->bands
[IEEE80211_BAND_5GHZ
] =
1618 &sc
->sbands
[IEEE80211_BAND_5GHZ
];
1621 int ath_attach(u16 devid
, struct ath_softc
*sc
)
1623 struct ieee80211_hw
*hw
= sc
->hw
;
1625 struct ath_regulatory
*reg
;
1627 DPRINTF(sc
, ATH_DBG_CONFIG
, "Attach ATH hw\n");
1629 error
= ath_init(devid
, sc
);
1633 reg
= &sc
->sc_ah
->regulatory
;
1635 /* get mac address from hardware and set in mac80211 */
1637 SET_IEEE80211_PERM_ADDR(hw
, sc
->sc_ah
->macaddr
);
1639 ath_set_hw_capab(sc
, hw
);
1641 if (sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_HT
) {
1642 setup_ht_cap(sc
, &sc
->sbands
[IEEE80211_BAND_2GHZ
].ht_cap
);
1643 if (test_bit(ATH9K_MODE_11A
, sc
->sc_ah
->caps
.wireless_modes
))
1644 setup_ht_cap(sc
, &sc
->sbands
[IEEE80211_BAND_5GHZ
].ht_cap
);
1647 /* initialize tx/rx engine */
1648 error
= ath_tx_init(sc
, ATH_TXBUF
);
1652 error
= ath_rx_init(sc
, ATH_RXBUF
);
1656 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1657 /* Initialze h/w Rfkill */
1658 if (sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_RFSILENT
)
1659 INIT_DELAYED_WORK(&sc
->rf_kill
.rfkill_poll
, ath_rfkill_poll
);
1661 /* Initialize s/w rfkill */
1662 error
= ath_init_sw_rfkill(sc
);
1667 INIT_WORK(&sc
->chan_work
, ath9k_wiphy_chan_work
);
1668 INIT_DELAYED_WORK(&sc
->wiphy_work
, ath9k_wiphy_work
);
1669 sc
->wiphy_scheduler_int
= msecs_to_jiffies(500);
1671 error
= ieee80211_register_hw(hw
);
1673 if (!ath_is_world_regd(reg
)) {
1674 error
= regulatory_hint(hw
->wiphy
, reg
->alpha2
);
1679 /* Initialize LED control */
1686 /* cleanup tx queues */
1687 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++)
1688 if (ATH_TXQ_SETUP(sc
, i
))
1689 ath_tx_cleanupq(sc
, &sc
->tx
.txq
[i
]);
1691 ath9k_hw_detach(sc
->sc_ah
);
1692 ath9k_exit_debug(sc
);
1697 int ath_reset(struct ath_softc
*sc
, bool retry_tx
)
1699 struct ath_hw
*ah
= sc
->sc_ah
;
1700 struct ieee80211_hw
*hw
= sc
->hw
;
1703 ath9k_hw_set_interrupts(ah
, 0);
1704 ath_drain_all_txq(sc
, retry_tx
);
1708 spin_lock_bh(&sc
->sc_resetlock
);
1709 r
= ath9k_hw_reset(ah
, sc
->sc_ah
->curchan
, false);
1711 DPRINTF(sc
, ATH_DBG_FATAL
,
1712 "Unable to reset hardware; reset status %u\n", r
);
1713 spin_unlock_bh(&sc
->sc_resetlock
);
1715 if (ath_startrecv(sc
) != 0)
1716 DPRINTF(sc
, ATH_DBG_FATAL
, "Unable to start recv logic\n");
1719 * We may be doing a reset in response to a request
1720 * that changes the channel so update any state that
1721 * might change as a result.
1723 ath_cache_conf_rate(sc
, &hw
->conf
);
1725 ath_update_txpow(sc
);
1727 if (sc
->sc_flags
& SC_OP_BEACONS
)
1728 ath_beacon_config(sc
, NULL
); /* restart beacons */
1730 ath9k_hw_set_interrupts(ah
, sc
->imask
);
1734 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++) {
1735 if (ATH_TXQ_SETUP(sc
, i
)) {
1736 spin_lock_bh(&sc
->tx
.txq
[i
].axq_lock
);
1737 ath_txq_schedule(sc
, &sc
->tx
.txq
[i
]);
1738 spin_unlock_bh(&sc
->tx
.txq
[i
].axq_lock
);
1747 * This function will allocate both the DMA descriptor structure, and the
1748 * buffers it contains. These are used to contain the descriptors used
1751 int ath_descdma_setup(struct ath_softc
*sc
, struct ath_descdma
*dd
,
1752 struct list_head
*head
, const char *name
,
1753 int nbuf
, int ndesc
)
1755 #define DS2PHYS(_dd, _ds) \
1756 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1757 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1758 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1760 struct ath_desc
*ds
;
1762 int i
, bsize
, error
;
1764 DPRINTF(sc
, ATH_DBG_CONFIG
, "%s DMA: %u buffers %u desc/buf\n",
1767 INIT_LIST_HEAD(head
);
1768 /* ath_desc must be a multiple of DWORDs */
1769 if ((sizeof(struct ath_desc
) % 4) != 0) {
1770 DPRINTF(sc
, ATH_DBG_FATAL
, "ath_desc not DWORD aligned\n");
1771 ASSERT((sizeof(struct ath_desc
) % 4) == 0);
1776 dd
->dd_desc_len
= sizeof(struct ath_desc
) * nbuf
* ndesc
;
1779 * Need additional DMA memory because we can't use
1780 * descriptors that cross the 4K page boundary. Assume
1781 * one skipped descriptor per 4K page.
1783 if (!(sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_4KB_SPLITTRANS
)) {
1785 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd
->dd_desc_len
);
1788 while (ndesc_skipped
) {
1789 dma_len
= ndesc_skipped
* sizeof(struct ath_desc
);
1790 dd
->dd_desc_len
+= dma_len
;
1792 ndesc_skipped
= ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len
);
1796 /* allocate descriptors */
1797 dd
->dd_desc
= dma_alloc_coherent(sc
->dev
, dd
->dd_desc_len
,
1798 &dd
->dd_desc_paddr
, GFP_KERNEL
);
1799 if (dd
->dd_desc
== NULL
) {
1804 DPRINTF(sc
, ATH_DBG_CONFIG
, "%s DMA map: %p (%u) -> %llx (%u)\n",
1805 name
, ds
, (u32
) dd
->dd_desc_len
,
1806 ito64(dd
->dd_desc_paddr
), /*XXX*/(u32
) dd
->dd_desc_len
);
1808 /* allocate buffers */
1809 bsize
= sizeof(struct ath_buf
) * nbuf
;
1810 bf
= kzalloc(bsize
, GFP_KERNEL
);
1817 for (i
= 0; i
< nbuf
; i
++, bf
++, ds
+= ndesc
) {
1819 bf
->bf_daddr
= DS2PHYS(dd
, ds
);
1821 if (!(sc
->sc_ah
->caps
.hw_caps
&
1822 ATH9K_HW_CAP_4KB_SPLITTRANS
)) {
1824 * Skip descriptor addresses which can cause 4KB
1825 * boundary crossing (addr + length) with a 32 dword
1828 while (ATH_DESC_4KB_BOUND_CHECK(bf
->bf_daddr
)) {
1829 ASSERT((caddr_t
) bf
->bf_desc
<
1830 ((caddr_t
) dd
->dd_desc
+
1835 bf
->bf_daddr
= DS2PHYS(dd
, ds
);
1838 list_add_tail(&bf
->list
, head
);
1842 dma_free_coherent(sc
->dev
, dd
->dd_desc_len
, dd
->dd_desc
,
1845 memset(dd
, 0, sizeof(*dd
));
1847 #undef ATH_DESC_4KB_BOUND_CHECK
1848 #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1852 void ath_descdma_cleanup(struct ath_softc
*sc
,
1853 struct ath_descdma
*dd
,
1854 struct list_head
*head
)
1856 dma_free_coherent(sc
->dev
, dd
->dd_desc_len
, dd
->dd_desc
,
1859 INIT_LIST_HEAD(head
);
1860 kfree(dd
->dd_bufptr
);
1861 memset(dd
, 0, sizeof(*dd
));
1864 int ath_get_hal_qnum(u16 queue
, struct ath_softc
*sc
)
1870 qnum
= sc
->tx
.hwq_map
[ATH9K_WME_AC_VO
];
1873 qnum
= sc
->tx
.hwq_map
[ATH9K_WME_AC_VI
];
1876 qnum
= sc
->tx
.hwq_map
[ATH9K_WME_AC_BE
];
1879 qnum
= sc
->tx
.hwq_map
[ATH9K_WME_AC_BK
];
1882 qnum
= sc
->tx
.hwq_map
[ATH9K_WME_AC_BE
];
1889 int ath_get_mac80211_qnum(u32 queue
, struct ath_softc
*sc
)
1894 case ATH9K_WME_AC_VO
:
1897 case ATH9K_WME_AC_VI
:
1900 case ATH9K_WME_AC_BE
:
1903 case ATH9K_WME_AC_BK
:
1914 /* XXX: Remove me once we don't depend on ath9k_channel for all
1915 * this redundant data */
1916 void ath9k_update_ichannel(struct ath_softc
*sc
, struct ieee80211_hw
*hw
,
1917 struct ath9k_channel
*ichan
)
1919 struct ieee80211_channel
*chan
= hw
->conf
.channel
;
1920 struct ieee80211_conf
*conf
= &hw
->conf
;
1922 ichan
->channel
= chan
->center_freq
;
1925 if (chan
->band
== IEEE80211_BAND_2GHZ
) {
1926 ichan
->chanmode
= CHANNEL_G
;
1927 ichan
->channelFlags
= CHANNEL_2GHZ
| CHANNEL_OFDM
;
1929 ichan
->chanmode
= CHANNEL_A
;
1930 ichan
->channelFlags
= CHANNEL_5GHZ
| CHANNEL_OFDM
;
1933 sc
->tx_chan_width
= ATH9K_HT_MACMODE_20
;
1935 if (conf_is_ht(conf
)) {
1936 if (conf_is_ht40(conf
))
1937 sc
->tx_chan_width
= ATH9K_HT_MACMODE_2040
;
1939 ichan
->chanmode
= ath_get_extchanmode(sc
, chan
,
1940 conf
->channel_type
);
1944 /**********************/
1945 /* mac80211 callbacks */
1946 /**********************/
1948 static int ath9k_start(struct ieee80211_hw
*hw
)
1950 struct ath_wiphy
*aphy
= hw
->priv
;
1951 struct ath_softc
*sc
= aphy
->sc
;
1952 struct ieee80211_channel
*curchan
= hw
->conf
.channel
;
1953 struct ath9k_channel
*init_channel
;
1956 DPRINTF(sc
, ATH_DBG_CONFIG
, "Starting driver with "
1957 "initial channel: %d MHz\n", curchan
->center_freq
);
1959 mutex_lock(&sc
->mutex
);
1961 if (ath9k_wiphy_started(sc
)) {
1962 if (sc
->chan_idx
== curchan
->hw_value
) {
1964 * Already on the operational channel, the new wiphy
1965 * can be marked active.
1967 aphy
->state
= ATH_WIPHY_ACTIVE
;
1968 ieee80211_wake_queues(hw
);
1971 * Another wiphy is on another channel, start the new
1972 * wiphy in paused state.
1974 aphy
->state
= ATH_WIPHY_PAUSED
;
1975 ieee80211_stop_queues(hw
);
1977 mutex_unlock(&sc
->mutex
);
1980 aphy
->state
= ATH_WIPHY_ACTIVE
;
1982 /* setup initial channel */
1984 pos
= curchan
->hw_value
;
1987 init_channel
= &sc
->sc_ah
->channels
[pos
];
1988 ath9k_update_ichannel(sc
, hw
, init_channel
);
1990 /* Reset SERDES registers */
1991 ath9k_hw_configpcipowersave(sc
->sc_ah
, 0);
1994 * The basic interface to setting the hardware in a good
1995 * state is ``reset''. On return the hardware is known to
1996 * be powered up and with interrupts disabled. This must
1997 * be followed by initialization of the appropriate bits
1998 * and then setup of the interrupt mask.
2000 spin_lock_bh(&sc
->sc_resetlock
);
2001 r
= ath9k_hw_reset(sc
->sc_ah
, init_channel
, false);
2003 DPRINTF(sc
, ATH_DBG_FATAL
,
2004 "Unable to reset hardware; reset status %u "
2005 "(freq %u MHz)\n", r
,
2006 curchan
->center_freq
);
2007 spin_unlock_bh(&sc
->sc_resetlock
);
2010 spin_unlock_bh(&sc
->sc_resetlock
);
2013 * This is needed only to setup initial state
2014 * but it's best done after a reset.
2016 ath_update_txpow(sc
);
2019 * Setup the hardware after reset:
2020 * The receive engine is set going.
2021 * Frame transmit is handled entirely
2022 * in the frame output path; there's nothing to do
2023 * here except setup the interrupt mask.
2025 if (ath_startrecv(sc
) != 0) {
2026 DPRINTF(sc
, ATH_DBG_FATAL
, "Unable to start recv logic\n");
2031 /* Setup our intr mask. */
2032 sc
->imask
= ATH9K_INT_RX
| ATH9K_INT_TX
2033 | ATH9K_INT_RXEOL
| ATH9K_INT_RXORN
2034 | ATH9K_INT_FATAL
| ATH9K_INT_GLOBAL
;
2036 if (sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_GTT
)
2037 sc
->imask
|= ATH9K_INT_GTT
;
2039 if (sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_HT
)
2040 sc
->imask
|= ATH9K_INT_CST
;
2042 ath_cache_conf_rate(sc
, &hw
->conf
);
2044 sc
->sc_flags
&= ~SC_OP_INVALID
;
2046 /* Disable BMISS interrupt when we're not associated */
2047 sc
->imask
&= ~(ATH9K_INT_SWBA
| ATH9K_INT_BMISS
);
2048 ath9k_hw_set_interrupts(sc
->sc_ah
, sc
->imask
);
2050 ieee80211_wake_queues(hw
);
2052 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2053 r
= ath_start_rfkill_poll(sc
);
2057 mutex_unlock(&sc
->mutex
);
2062 static int ath9k_tx(struct ieee80211_hw
*hw
,
2063 struct sk_buff
*skb
)
2065 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
2066 struct ath_wiphy
*aphy
= hw
->priv
;
2067 struct ath_softc
*sc
= aphy
->sc
;
2068 struct ath_tx_control txctl
;
2069 int hdrlen
, padsize
;
2071 if (aphy
->state
!= ATH_WIPHY_ACTIVE
&& aphy
->state
!= ATH_WIPHY_SCAN
) {
2072 printk(KERN_DEBUG
"ath9k: %s: TX in unexpected wiphy state "
2073 "%d\n", wiphy_name(hw
->wiphy
), aphy
->state
);
2077 memset(&txctl
, 0, sizeof(struct ath_tx_control
));
2080 * As a temporary workaround, assign seq# here; this will likely need
2081 * to be cleaned up to work better with Beacon transmission and virtual
2084 if (info
->flags
& IEEE80211_TX_CTL_ASSIGN_SEQ
) {
2085 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*) skb
->data
;
2086 if (info
->flags
& IEEE80211_TX_CTL_FIRST_FRAGMENT
)
2087 sc
->tx
.seq_no
+= 0x10;
2088 hdr
->seq_ctrl
&= cpu_to_le16(IEEE80211_SCTL_FRAG
);
2089 hdr
->seq_ctrl
|= cpu_to_le16(sc
->tx
.seq_no
);
2092 /* Add the padding after the header if this is not already done */
2093 hdrlen
= ieee80211_get_hdrlen_from_skb(skb
);
2095 padsize
= hdrlen
% 4;
2096 if (skb_headroom(skb
) < padsize
)
2098 skb_push(skb
, padsize
);
2099 memmove(skb
->data
, skb
->data
+ padsize
, hdrlen
);
2102 /* Check if a tx queue is available */
2104 txctl
.txq
= ath_test_get_txq(sc
, skb
);
2108 DPRINTF(sc
, ATH_DBG_XMIT
, "transmitting packet, skb: %p\n", skb
);
2110 if (ath_tx_start(hw
, skb
, &txctl
) != 0) {
2111 DPRINTF(sc
, ATH_DBG_XMIT
, "TX failed\n");
2117 dev_kfree_skb_any(skb
);
2121 static void ath9k_stop(struct ieee80211_hw
*hw
)
2123 struct ath_wiphy
*aphy
= hw
->priv
;
2124 struct ath_softc
*sc
= aphy
->sc
;
2126 aphy
->state
= ATH_WIPHY_INACTIVE
;
2128 if (sc
->sc_flags
& SC_OP_INVALID
) {
2129 DPRINTF(sc
, ATH_DBG_ANY
, "Device not present\n");
2133 mutex_lock(&sc
->mutex
);
2135 ieee80211_stop_queues(hw
);
2137 if (ath9k_wiphy_started(sc
)) {
2138 mutex_unlock(&sc
->mutex
);
2139 return; /* another wiphy still in use */
2142 /* make sure h/w will not generate any interrupt
2143 * before setting the invalid flag. */
2144 ath9k_hw_set_interrupts(sc
->sc_ah
, 0);
2146 if (!(sc
->sc_flags
& SC_OP_INVALID
)) {
2147 ath_drain_all_txq(sc
, false);
2149 ath9k_hw_phy_disable(sc
->sc_ah
);
2151 sc
->rx
.rxlink
= NULL
;
2153 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2154 if (sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_RFSILENT
)
2155 cancel_delayed_work_sync(&sc
->rf_kill
.rfkill_poll
);
2157 /* disable HAL and put h/w to sleep */
2158 ath9k_hw_disable(sc
->sc_ah
);
2159 ath9k_hw_configpcipowersave(sc
->sc_ah
, 1);
2161 sc
->sc_flags
|= SC_OP_INVALID
;
2163 mutex_unlock(&sc
->mutex
);
2165 DPRINTF(sc
, ATH_DBG_CONFIG
, "Driver halt\n");
2168 static int ath9k_add_interface(struct ieee80211_hw
*hw
,
2169 struct ieee80211_if_init_conf
*conf
)
2171 struct ath_wiphy
*aphy
= hw
->priv
;
2172 struct ath_softc
*sc
= aphy
->sc
;
2173 struct ath_vif
*avp
= (void *)conf
->vif
->drv_priv
;
2174 enum nl80211_iftype ic_opmode
= NL80211_IFTYPE_UNSPECIFIED
;
2177 mutex_lock(&sc
->mutex
);
2179 if (!(sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_BSSIDMASK
) &&
2185 switch (conf
->type
) {
2186 case NL80211_IFTYPE_STATION
:
2187 ic_opmode
= NL80211_IFTYPE_STATION
;
2189 case NL80211_IFTYPE_ADHOC
:
2190 case NL80211_IFTYPE_AP
:
2191 case NL80211_IFTYPE_MESH_POINT
:
2192 if (sc
->nbcnvifs
>= ATH_BCBUF
) {
2196 ic_opmode
= conf
->type
;
2199 DPRINTF(sc
, ATH_DBG_FATAL
,
2200 "Interface type %d not yet supported\n", conf
->type
);
2205 DPRINTF(sc
, ATH_DBG_CONFIG
, "Attach a VIF of type: %d\n", ic_opmode
);
2207 /* Set the VIF opmode */
2208 avp
->av_opmode
= ic_opmode
;
2213 if (sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_BSSIDMASK
)
2214 ath9k_set_bssid_mask(hw
);
2217 goto out
; /* skip global settings for secondary vif */
2219 if (ic_opmode
== NL80211_IFTYPE_AP
) {
2220 ath9k_hw_set_tsfadjust(sc
->sc_ah
, 1);
2221 sc
->sc_flags
|= SC_OP_TSF_RESET
;
2224 /* Set the device opmode */
2225 sc
->sc_ah
->opmode
= ic_opmode
;
2228 * Enable MIB interrupts when there are hardware phy counters.
2229 * Note we only do this (at the moment) for station mode.
2231 if ((conf
->type
== NL80211_IFTYPE_STATION
) ||
2232 (conf
->type
== NL80211_IFTYPE_ADHOC
) ||
2233 (conf
->type
== NL80211_IFTYPE_MESH_POINT
)) {
2234 if (ath9k_hw_phycounters(sc
->sc_ah
))
2235 sc
->imask
|= ATH9K_INT_MIB
;
2236 sc
->imask
|= ATH9K_INT_TSFOOR
;
2239 ath9k_hw_set_interrupts(sc
->sc_ah
, sc
->imask
);
2241 if (conf
->type
== NL80211_IFTYPE_AP
)
2245 mutex_unlock(&sc
->mutex
);
2249 static void ath9k_remove_interface(struct ieee80211_hw
*hw
,
2250 struct ieee80211_if_init_conf
*conf
)
2252 struct ath_wiphy
*aphy
= hw
->priv
;
2253 struct ath_softc
*sc
= aphy
->sc
;
2254 struct ath_vif
*avp
= (void *)conf
->vif
->drv_priv
;
2257 DPRINTF(sc
, ATH_DBG_CONFIG
, "Detach Interface\n");
2259 mutex_lock(&sc
->mutex
);
2262 del_timer_sync(&sc
->ani
.timer
);
2264 /* Reclaim beacon resources */
2265 if ((sc
->sc_ah
->opmode
== NL80211_IFTYPE_AP
) ||
2266 (sc
->sc_ah
->opmode
== NL80211_IFTYPE_ADHOC
) ||
2267 (sc
->sc_ah
->opmode
== NL80211_IFTYPE_MESH_POINT
)) {
2268 ath9k_hw_stoptxdma(sc
->sc_ah
, sc
->beacon
.beaconq
);
2269 ath_beacon_return(sc
, avp
);
2272 sc
->sc_flags
&= ~SC_OP_BEACONS
;
2274 for (i
= 0; i
< ARRAY_SIZE(sc
->beacon
.bslot
); i
++) {
2275 if (sc
->beacon
.bslot
[i
] == conf
->vif
) {
2276 printk(KERN_DEBUG
"%s: vif had allocated beacon "
2277 "slot\n", __func__
);
2278 sc
->beacon
.bslot
[i
] = NULL
;
2279 sc
->beacon
.bslot_aphy
[i
] = NULL
;
2285 mutex_unlock(&sc
->mutex
);
2288 static int ath9k_config(struct ieee80211_hw
*hw
, u32 changed
)
2290 struct ath_wiphy
*aphy
= hw
->priv
;
2291 struct ath_softc
*sc
= aphy
->sc
;
2292 struct ieee80211_conf
*conf
= &hw
->conf
;
2293 struct ath_hw
*ah
= sc
->sc_ah
;
2295 mutex_lock(&sc
->mutex
);
2297 if (changed
& IEEE80211_CONF_CHANGE_PS
) {
2298 if (conf
->flags
& IEEE80211_CONF_PS
) {
2299 if (!(ah
->caps
.hw_caps
&
2300 ATH9K_HW_CAP_AUTOSLEEP
)) {
2301 if ((sc
->imask
& ATH9K_INT_TIM_TIMER
) == 0) {
2302 sc
->imask
|= ATH9K_INT_TIM_TIMER
;
2303 ath9k_hw_set_interrupts(sc
->sc_ah
,
2306 ath9k_hw_setrxabort(sc
->sc_ah
, 1);
2308 ath9k_hw_setpower(sc
->sc_ah
, ATH9K_PM_NETWORK_SLEEP
);
2310 ath9k_hw_setpower(sc
->sc_ah
, ATH9K_PM_AWAKE
);
2311 if (!(ah
->caps
.hw_caps
&
2312 ATH9K_HW_CAP_AUTOSLEEP
)) {
2313 ath9k_hw_setrxabort(sc
->sc_ah
, 0);
2314 sc
->sc_flags
&= ~SC_OP_WAIT_FOR_BEACON
;
2315 if (sc
->imask
& ATH9K_INT_TIM_TIMER
) {
2316 sc
->imask
&= ~ATH9K_INT_TIM_TIMER
;
2317 ath9k_hw_set_interrupts(sc
->sc_ah
,
2324 if (changed
& IEEE80211_CONF_CHANGE_CHANNEL
) {
2325 struct ieee80211_channel
*curchan
= hw
->conf
.channel
;
2326 int pos
= curchan
->hw_value
;
2328 aphy
->chan_idx
= pos
;
2329 aphy
->chan_is_ht
= conf_is_ht(conf
);
2331 if (aphy
->state
== ATH_WIPHY_SCAN
||
2332 aphy
->state
== ATH_WIPHY_ACTIVE
)
2333 ath9k_wiphy_pause_all_forced(sc
, aphy
);
2336 * Do not change operational channel based on a paused
2339 goto skip_chan_change
;
2342 DPRINTF(sc
, ATH_DBG_CONFIG
, "Set channel: %d MHz\n",
2343 curchan
->center_freq
);
2345 /* XXX: remove me eventualy */
2346 ath9k_update_ichannel(sc
, hw
, &sc
->sc_ah
->channels
[pos
]);
2348 ath_update_chainmask(sc
, conf_is_ht(conf
));
2350 if (ath_set_channel(sc
, hw
, &sc
->sc_ah
->channels
[pos
]) < 0) {
2351 DPRINTF(sc
, ATH_DBG_FATAL
, "Unable to set channel\n");
2352 mutex_unlock(&sc
->mutex
);
2358 if (changed
& IEEE80211_CONF_CHANGE_POWER
)
2359 sc
->config
.txpowlimit
= 2 * conf
->power_level
;
2362 * The HW TSF has to be reset when the beacon interval changes.
2363 * We set the flag here, and ath_beacon_config_ap() would take this
2364 * into account when it gets called through the subsequent
2365 * config_interface() call - with IFCC_BEACON in the changed field.
2368 if (changed
& IEEE80211_CONF_CHANGE_BEACON_INTERVAL
)
2369 sc
->sc_flags
|= SC_OP_TSF_RESET
;
2371 mutex_unlock(&sc
->mutex
);
2376 static int ath9k_config_interface(struct ieee80211_hw
*hw
,
2377 struct ieee80211_vif
*vif
,
2378 struct ieee80211_if_conf
*conf
)
2380 struct ath_wiphy
*aphy
= hw
->priv
;
2381 struct ath_softc
*sc
= aphy
->sc
;
2382 struct ath_hw
*ah
= sc
->sc_ah
;
2383 struct ath_vif
*avp
= (void *)vif
->drv_priv
;
2387 mutex_lock(&sc
->mutex
);
2389 /* TODO: Need to decide which hw opmode to use for multi-interface
2391 if (vif
->type
== NL80211_IFTYPE_AP
&&
2392 ah
->opmode
!= NL80211_IFTYPE_AP
) {
2393 ah
->opmode
= NL80211_IFTYPE_STATION
;
2394 ath9k_hw_setopmode(ah
);
2395 memcpy(sc
->curbssid
, sc
->sc_ah
->macaddr
, ETH_ALEN
);
2397 ath9k_hw_write_associd(sc
);
2398 /* Request full reset to get hw opmode changed properly */
2399 sc
->sc_flags
|= SC_OP_FULL_RESET
;
2402 if ((conf
->changed
& IEEE80211_IFCC_BSSID
) &&
2403 !is_zero_ether_addr(conf
->bssid
)) {
2404 switch (vif
->type
) {
2405 case NL80211_IFTYPE_STATION
:
2406 case NL80211_IFTYPE_ADHOC
:
2407 case NL80211_IFTYPE_MESH_POINT
:
2409 memcpy(sc
->curbssid
, conf
->bssid
, ETH_ALEN
);
2410 memcpy(avp
->bssid
, conf
->bssid
, ETH_ALEN
);
2412 ath9k_hw_write_associd(sc
);
2414 /* Set aggregation protection mode parameters */
2415 sc
->config
.ath_aggr_prot
= 0;
2417 DPRINTF(sc
, ATH_DBG_CONFIG
,
2418 "RX filter 0x%x bssid %pM aid 0x%x\n",
2419 rfilt
, sc
->curbssid
, sc
->curaid
);
2421 /* need to reconfigure the beacon */
2422 sc
->sc_flags
&= ~SC_OP_BEACONS
;
2430 if ((vif
->type
== NL80211_IFTYPE_ADHOC
) ||
2431 (vif
->type
== NL80211_IFTYPE_AP
) ||
2432 (vif
->type
== NL80211_IFTYPE_MESH_POINT
)) {
2433 if ((conf
->changed
& IEEE80211_IFCC_BEACON
) ||
2434 (conf
->changed
& IEEE80211_IFCC_BEACON_ENABLED
&&
2435 conf
->enable_beacon
)) {
2437 * Allocate and setup the beacon frame.
2439 * Stop any previous beacon DMA. This may be
2440 * necessary, for example, when an ibss merge
2441 * causes reconfiguration; we may be called
2442 * with beacon transmission active.
2444 ath9k_hw_stoptxdma(sc
->sc_ah
, sc
->beacon
.beaconq
);
2446 error
= ath_beacon_alloc(aphy
, vif
);
2448 mutex_unlock(&sc
->mutex
);
2452 ath_beacon_config(sc
, vif
);
2456 /* Check for WLAN_CAPABILITY_PRIVACY ? */
2457 if ((avp
->av_opmode
!= NL80211_IFTYPE_STATION
)) {
2458 for (i
= 0; i
< IEEE80211_WEP_NKID
; i
++)
2459 if (ath9k_hw_keyisvalid(sc
->sc_ah
, (u16
)i
))
2460 ath9k_hw_keysetmac(sc
->sc_ah
,
2465 /* Only legacy IBSS for now */
2466 if (vif
->type
== NL80211_IFTYPE_ADHOC
)
2467 ath_update_chainmask(sc
, 0);
2469 mutex_unlock(&sc
->mutex
);
2474 #define SUPPORTED_FILTERS \
2475 (FIF_PROMISC_IN_BSS | \
2479 FIF_BCN_PRBRESP_PROMISC | \
2482 /* FIXME: sc->sc_full_reset ? */
2483 static void ath9k_configure_filter(struct ieee80211_hw
*hw
,
2484 unsigned int changed_flags
,
2485 unsigned int *total_flags
,
2487 struct dev_mc_list
*mclist
)
2489 struct ath_wiphy
*aphy
= hw
->priv
;
2490 struct ath_softc
*sc
= aphy
->sc
;
2493 changed_flags
&= SUPPORTED_FILTERS
;
2494 *total_flags
&= SUPPORTED_FILTERS
;
2496 sc
->rx
.rxfilter
= *total_flags
;
2497 rfilt
= ath_calcrxfilter(sc
);
2498 ath9k_hw_setrxfilter(sc
->sc_ah
, rfilt
);
2500 DPRINTF(sc
, ATH_DBG_CONFIG
, "Set HW RX filter: 0x%x\n", sc
->rx
.rxfilter
);
2503 static void ath9k_sta_notify(struct ieee80211_hw
*hw
,
2504 struct ieee80211_vif
*vif
,
2505 enum sta_notify_cmd cmd
,
2506 struct ieee80211_sta
*sta
)
2508 struct ath_wiphy
*aphy
= hw
->priv
;
2509 struct ath_softc
*sc
= aphy
->sc
;
2512 case STA_NOTIFY_ADD
:
2513 ath_node_attach(sc
, sta
);
2515 case STA_NOTIFY_REMOVE
:
2516 ath_node_detach(sc
, sta
);
2523 static int ath9k_conf_tx(struct ieee80211_hw
*hw
, u16 queue
,
2524 const struct ieee80211_tx_queue_params
*params
)
2526 struct ath_wiphy
*aphy
= hw
->priv
;
2527 struct ath_softc
*sc
= aphy
->sc
;
2528 struct ath9k_tx_queue_info qi
;
2531 if (queue
>= WME_NUM_AC
)
2534 mutex_lock(&sc
->mutex
);
2536 memset(&qi
, 0, sizeof(struct ath9k_tx_queue_info
));
2538 qi
.tqi_aifs
= params
->aifs
;
2539 qi
.tqi_cwmin
= params
->cw_min
;
2540 qi
.tqi_cwmax
= params
->cw_max
;
2541 qi
.tqi_burstTime
= params
->txop
;
2542 qnum
= ath_get_hal_qnum(queue
, sc
);
2544 DPRINTF(sc
, ATH_DBG_CONFIG
,
2545 "Configure tx [queue/halq] [%d/%d], "
2546 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2547 queue
, qnum
, params
->aifs
, params
->cw_min
,
2548 params
->cw_max
, params
->txop
);
2550 ret
= ath_txq_update(sc
, qnum
, &qi
);
2552 DPRINTF(sc
, ATH_DBG_FATAL
, "TXQ Update failed\n");
2554 mutex_unlock(&sc
->mutex
);
2559 static int ath9k_set_key(struct ieee80211_hw
*hw
,
2560 enum set_key_cmd cmd
,
2561 struct ieee80211_vif
*vif
,
2562 struct ieee80211_sta
*sta
,
2563 struct ieee80211_key_conf
*key
)
2565 struct ath_wiphy
*aphy
= hw
->priv
;
2566 struct ath_softc
*sc
= aphy
->sc
;
2569 if (modparam_nohwcrypt
)
2572 mutex_lock(&sc
->mutex
);
2573 ath9k_ps_wakeup(sc
);
2574 DPRINTF(sc
, ATH_DBG_CONFIG
, "Set HW Key\n");
2578 ret
= ath_key_config(sc
, vif
, sta
, key
);
2580 key
->hw_key_idx
= ret
;
2581 /* push IV and Michael MIC generation to stack */
2582 key
->flags
|= IEEE80211_KEY_FLAG_GENERATE_IV
;
2583 if (key
->alg
== ALG_TKIP
)
2584 key
->flags
|= IEEE80211_KEY_FLAG_GENERATE_MMIC
;
2585 if (sc
->sc_ah
->sw_mgmt_crypto
&& key
->alg
== ALG_CCMP
)
2586 key
->flags
|= IEEE80211_KEY_FLAG_SW_MGMT
;
2591 ath_key_delete(sc
, key
);
2597 ath9k_ps_restore(sc
);
2598 mutex_unlock(&sc
->mutex
);
2603 static void ath9k_bss_info_changed(struct ieee80211_hw
*hw
,
2604 struct ieee80211_vif
*vif
,
2605 struct ieee80211_bss_conf
*bss_conf
,
2608 struct ath_wiphy
*aphy
= hw
->priv
;
2609 struct ath_softc
*sc
= aphy
->sc
;
2611 mutex_lock(&sc
->mutex
);
2613 if (changed
& BSS_CHANGED_ERP_PREAMBLE
) {
2614 DPRINTF(sc
, ATH_DBG_CONFIG
, "BSS Changed PREAMBLE %d\n",
2615 bss_conf
->use_short_preamble
);
2616 if (bss_conf
->use_short_preamble
)
2617 sc
->sc_flags
|= SC_OP_PREAMBLE_SHORT
;
2619 sc
->sc_flags
&= ~SC_OP_PREAMBLE_SHORT
;
2622 if (changed
& BSS_CHANGED_ERP_CTS_PROT
) {
2623 DPRINTF(sc
, ATH_DBG_CONFIG
, "BSS Changed CTS PROT %d\n",
2624 bss_conf
->use_cts_prot
);
2625 if (bss_conf
->use_cts_prot
&&
2626 hw
->conf
.channel
->band
!= IEEE80211_BAND_5GHZ
)
2627 sc
->sc_flags
|= SC_OP_PROTECT_ENABLE
;
2629 sc
->sc_flags
&= ~SC_OP_PROTECT_ENABLE
;
2632 if (changed
& BSS_CHANGED_ASSOC
) {
2633 DPRINTF(sc
, ATH_DBG_CONFIG
, "BSS Changed ASSOC %d\n",
2635 ath9k_bss_assoc_info(sc
, vif
, bss_conf
);
2638 mutex_unlock(&sc
->mutex
);
2641 static u64
ath9k_get_tsf(struct ieee80211_hw
*hw
)
2644 struct ath_wiphy
*aphy
= hw
->priv
;
2645 struct ath_softc
*sc
= aphy
->sc
;
2647 mutex_lock(&sc
->mutex
);
2648 tsf
= ath9k_hw_gettsf64(sc
->sc_ah
);
2649 mutex_unlock(&sc
->mutex
);
2654 static void ath9k_set_tsf(struct ieee80211_hw
*hw
, u64 tsf
)
2656 struct ath_wiphy
*aphy
= hw
->priv
;
2657 struct ath_softc
*sc
= aphy
->sc
;
2659 mutex_lock(&sc
->mutex
);
2660 ath9k_hw_settsf64(sc
->sc_ah
, tsf
);
2661 mutex_unlock(&sc
->mutex
);
2664 static void ath9k_reset_tsf(struct ieee80211_hw
*hw
)
2666 struct ath_wiphy
*aphy
= hw
->priv
;
2667 struct ath_softc
*sc
= aphy
->sc
;
2669 mutex_lock(&sc
->mutex
);
2670 ath9k_hw_reset_tsf(sc
->sc_ah
);
2671 mutex_unlock(&sc
->mutex
);
2674 static int ath9k_ampdu_action(struct ieee80211_hw
*hw
,
2675 enum ieee80211_ampdu_mlme_action action
,
2676 struct ieee80211_sta
*sta
,
2679 struct ath_wiphy
*aphy
= hw
->priv
;
2680 struct ath_softc
*sc
= aphy
->sc
;
2684 case IEEE80211_AMPDU_RX_START
:
2685 if (!(sc
->sc_flags
& SC_OP_RXAGGR
))
2688 case IEEE80211_AMPDU_RX_STOP
:
2690 case IEEE80211_AMPDU_TX_START
:
2691 ret
= ath_tx_aggr_start(sc
, sta
, tid
, ssn
);
2693 DPRINTF(sc
, ATH_DBG_FATAL
,
2694 "Unable to start TX aggregation\n");
2696 ieee80211_start_tx_ba_cb_irqsafe(hw
, sta
->addr
, tid
);
2698 case IEEE80211_AMPDU_TX_STOP
:
2699 ret
= ath_tx_aggr_stop(sc
, sta
, tid
);
2701 DPRINTF(sc
, ATH_DBG_FATAL
,
2702 "Unable to stop TX aggregation\n");
2704 ieee80211_stop_tx_ba_cb_irqsafe(hw
, sta
->addr
, tid
);
2706 case IEEE80211_AMPDU_TX_OPERATIONAL
:
2707 ath_tx_aggr_resume(sc
, sta
, tid
);
2710 DPRINTF(sc
, ATH_DBG_FATAL
, "Unknown AMPDU action\n");
2716 static void ath9k_sw_scan_start(struct ieee80211_hw
*hw
)
2718 struct ath_wiphy
*aphy
= hw
->priv
;
2719 struct ath_softc
*sc
= aphy
->sc
;
2721 if (ath9k_wiphy_scanning(sc
)) {
2722 printk(KERN_DEBUG
"ath9k: Two wiphys trying to scan at the "
2725 * Do not allow the concurrent scanning state for now. This
2726 * could be improved with scanning control moved into ath9k.
2731 aphy
->state
= ATH_WIPHY_SCAN
;
2732 ath9k_wiphy_pause_all_forced(sc
, aphy
);
2734 mutex_lock(&sc
->mutex
);
2735 sc
->sc_flags
|= SC_OP_SCANNING
;
2736 mutex_unlock(&sc
->mutex
);
2739 static void ath9k_sw_scan_complete(struct ieee80211_hw
*hw
)
2741 struct ath_wiphy
*aphy
= hw
->priv
;
2742 struct ath_softc
*sc
= aphy
->sc
;
2744 mutex_lock(&sc
->mutex
);
2745 aphy
->state
= ATH_WIPHY_ACTIVE
;
2746 sc
->sc_flags
&= ~SC_OP_SCANNING
;
2747 sc
->sc_flags
|= SC_OP_FULL_RESET
;
2748 mutex_unlock(&sc
->mutex
);
2751 struct ieee80211_ops ath9k_ops
= {
2753 .start
= ath9k_start
,
2755 .add_interface
= ath9k_add_interface
,
2756 .remove_interface
= ath9k_remove_interface
,
2757 .config
= ath9k_config
,
2758 .config_interface
= ath9k_config_interface
,
2759 .configure_filter
= ath9k_configure_filter
,
2760 .sta_notify
= ath9k_sta_notify
,
2761 .conf_tx
= ath9k_conf_tx
,
2762 .bss_info_changed
= ath9k_bss_info_changed
,
2763 .set_key
= ath9k_set_key
,
2764 .get_tsf
= ath9k_get_tsf
,
2765 .set_tsf
= ath9k_set_tsf
,
2766 .reset_tsf
= ath9k_reset_tsf
,
2767 .ampdu_action
= ath9k_ampdu_action
,
2768 .sw_scan_start
= ath9k_sw_scan_start
,
2769 .sw_scan_complete
= ath9k_sw_scan_complete
,
2775 } ath_mac_bb_names
[] = {
2776 { AR_SREV_VERSION_5416_PCI
, "5416" },
2777 { AR_SREV_VERSION_5416_PCIE
, "5418" },
2778 { AR_SREV_VERSION_9100
, "9100" },
2779 { AR_SREV_VERSION_9160
, "9160" },
2780 { AR_SREV_VERSION_9280
, "9280" },
2781 { AR_SREV_VERSION_9285
, "9285" }
2787 } ath_rf_names
[] = {
2789 { AR_RAD5133_SREV_MAJOR
, "5133" },
2790 { AR_RAD5122_SREV_MAJOR
, "5122" },
2791 { AR_RAD2133_SREV_MAJOR
, "2133" },
2792 { AR_RAD2122_SREV_MAJOR
, "2122" }
2796 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2799 ath_mac_bb_name(u32 mac_bb_version
)
2803 for (i
=0; i
<ARRAY_SIZE(ath_mac_bb_names
); i
++) {
2804 if (ath_mac_bb_names
[i
].version
== mac_bb_version
) {
2805 return ath_mac_bb_names
[i
].name
;
2813 * Return the RF name. "????" is returned if the RF is unknown.
2816 ath_rf_name(u16 rf_version
)
2820 for (i
=0; i
<ARRAY_SIZE(ath_rf_names
); i
++) {
2821 if (ath_rf_names
[i
].version
== rf_version
) {
2822 return ath_rf_names
[i
].name
;
2829 static int __init
ath9k_init(void)
2833 /* Register rate control algorithm */
2834 error
= ath_rate_control_register();
2837 "ath9k: Unable to register rate control "
2843 error
= ath9k_debug_create_root();
2846 "ath9k: Unable to create debugfs root: %d\n",
2848 goto err_rate_unregister
;
2851 error
= ath_pci_init();
2854 "ath9k: No PCI devices found, driver not installed.\n");
2856 goto err_remove_root
;
2859 error
= ath_ahb_init();
2871 ath9k_debug_remove_root();
2872 err_rate_unregister
:
2873 ath_rate_control_unregister();
2877 module_init(ath9k_init
);
2879 static void __exit
ath9k_exit(void)
2883 ath9k_debug_remove_root();
2884 ath_rate_control_unregister();
2885 printk(KERN_INFO
"%s: Driver unloaded\n", dev_info
);
2887 module_exit(ath9k_exit
);