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ath9k: Manipulate and report the correct RSSI
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / main.c
1 /*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/nl80211.h>
18 #include "ath9k.h"
19
20 #define ATH_PCI_VERSION "0.1"
21
22 static char *dev_info = "ath9k";
23
24 MODULE_AUTHOR("Atheros Communications");
25 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
26 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
27 MODULE_LICENSE("Dual BSD/GPL");
28
29 static int modparam_nohwcrypt;
30 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
31 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
32
33 /* We use the hw_value as an index into our private channel structure */
34
35 #define CHAN2G(_freq, _idx) { \
36 .center_freq = (_freq), \
37 .hw_value = (_idx), \
38 .max_power = 20, \
39 }
40
41 #define CHAN5G(_freq, _idx) { \
42 .band = IEEE80211_BAND_5GHZ, \
43 .center_freq = (_freq), \
44 .hw_value = (_idx), \
45 .max_power = 20, \
46 }
47
48 /* Some 2 GHz radios are actually tunable on 2312-2732
49 * on 5 MHz steps, we support the channels which we know
50 * we have calibration data for all cards though to make
51 * this static */
52 static struct ieee80211_channel ath9k_2ghz_chantable[] = {
53 CHAN2G(2412, 0), /* Channel 1 */
54 CHAN2G(2417, 1), /* Channel 2 */
55 CHAN2G(2422, 2), /* Channel 3 */
56 CHAN2G(2427, 3), /* Channel 4 */
57 CHAN2G(2432, 4), /* Channel 5 */
58 CHAN2G(2437, 5), /* Channel 6 */
59 CHAN2G(2442, 6), /* Channel 7 */
60 CHAN2G(2447, 7), /* Channel 8 */
61 CHAN2G(2452, 8), /* Channel 9 */
62 CHAN2G(2457, 9), /* Channel 10 */
63 CHAN2G(2462, 10), /* Channel 11 */
64 CHAN2G(2467, 11), /* Channel 12 */
65 CHAN2G(2472, 12), /* Channel 13 */
66 CHAN2G(2484, 13), /* Channel 14 */
67 };
68
69 /* Some 5 GHz radios are actually tunable on XXXX-YYYY
70 * on 5 MHz steps, we support the channels which we know
71 * we have calibration data for all cards though to make
72 * this static */
73 static struct ieee80211_channel ath9k_5ghz_chantable[] = {
74 /* _We_ call this UNII 1 */
75 CHAN5G(5180, 14), /* Channel 36 */
76 CHAN5G(5200, 15), /* Channel 40 */
77 CHAN5G(5220, 16), /* Channel 44 */
78 CHAN5G(5240, 17), /* Channel 48 */
79 /* _We_ call this UNII 2 */
80 CHAN5G(5260, 18), /* Channel 52 */
81 CHAN5G(5280, 19), /* Channel 56 */
82 CHAN5G(5300, 20), /* Channel 60 */
83 CHAN5G(5320, 21), /* Channel 64 */
84 /* _We_ call this "Middle band" */
85 CHAN5G(5500, 22), /* Channel 100 */
86 CHAN5G(5520, 23), /* Channel 104 */
87 CHAN5G(5540, 24), /* Channel 108 */
88 CHAN5G(5560, 25), /* Channel 112 */
89 CHAN5G(5580, 26), /* Channel 116 */
90 CHAN5G(5600, 27), /* Channel 120 */
91 CHAN5G(5620, 28), /* Channel 124 */
92 CHAN5G(5640, 29), /* Channel 128 */
93 CHAN5G(5660, 30), /* Channel 132 */
94 CHAN5G(5680, 31), /* Channel 136 */
95 CHAN5G(5700, 32), /* Channel 140 */
96 /* _We_ call this UNII 3 */
97 CHAN5G(5745, 33), /* Channel 149 */
98 CHAN5G(5765, 34), /* Channel 153 */
99 CHAN5G(5785, 35), /* Channel 157 */
100 CHAN5G(5805, 36), /* Channel 161 */
101 CHAN5G(5825, 37), /* Channel 165 */
102 };
103
104 static void ath_cache_conf_rate(struct ath_softc *sc,
105 struct ieee80211_conf *conf)
106 {
107 switch (conf->channel->band) {
108 case IEEE80211_BAND_2GHZ:
109 if (conf_is_ht20(conf))
110 sc->cur_rate_table =
111 sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
112 else if (conf_is_ht40_minus(conf))
113 sc->cur_rate_table =
114 sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
115 else if (conf_is_ht40_plus(conf))
116 sc->cur_rate_table =
117 sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
118 else
119 sc->cur_rate_table =
120 sc->hw_rate_table[ATH9K_MODE_11G];
121 break;
122 case IEEE80211_BAND_5GHZ:
123 if (conf_is_ht20(conf))
124 sc->cur_rate_table =
125 sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
126 else if (conf_is_ht40_minus(conf))
127 sc->cur_rate_table =
128 sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
129 else if (conf_is_ht40_plus(conf))
130 sc->cur_rate_table =
131 sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
132 else
133 sc->cur_rate_table =
134 sc->hw_rate_table[ATH9K_MODE_11A];
135 break;
136 default:
137 BUG_ON(1);
138 break;
139 }
140 }
141
142 static void ath_update_txpow(struct ath_softc *sc)
143 {
144 struct ath_hw *ah = sc->sc_ah;
145 u32 txpow;
146
147 if (sc->curtxpow != sc->config.txpowlimit) {
148 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
149 /* read back in case value is clamped */
150 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
151 sc->curtxpow = txpow;
152 }
153 }
154
155 static u8 parse_mpdudensity(u8 mpdudensity)
156 {
157 /*
158 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
159 * 0 for no restriction
160 * 1 for 1/4 us
161 * 2 for 1/2 us
162 * 3 for 1 us
163 * 4 for 2 us
164 * 5 for 4 us
165 * 6 for 8 us
166 * 7 for 16 us
167 */
168 switch (mpdudensity) {
169 case 0:
170 return 0;
171 case 1:
172 case 2:
173 case 3:
174 /* Our lower layer calculations limit our precision to
175 1 microsecond */
176 return 1;
177 case 4:
178 return 2;
179 case 5:
180 return 4;
181 case 6:
182 return 8;
183 case 7:
184 return 16;
185 default:
186 return 0;
187 }
188 }
189
190 static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
191 {
192 const struct ath_rate_table *rate_table = NULL;
193 struct ieee80211_supported_band *sband;
194 struct ieee80211_rate *rate;
195 int i, maxrates;
196
197 switch (band) {
198 case IEEE80211_BAND_2GHZ:
199 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
200 break;
201 case IEEE80211_BAND_5GHZ:
202 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
203 break;
204 default:
205 break;
206 }
207
208 if (rate_table == NULL)
209 return;
210
211 sband = &sc->sbands[band];
212 rate = sc->rates[band];
213
214 if (rate_table->rate_cnt > ATH_RATE_MAX)
215 maxrates = ATH_RATE_MAX;
216 else
217 maxrates = rate_table->rate_cnt;
218
219 for (i = 0; i < maxrates; i++) {
220 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
221 rate[i].hw_value = rate_table->info[i].ratecode;
222 if (rate_table->info[i].short_preamble) {
223 rate[i].hw_value_short = rate_table->info[i].ratecode |
224 rate_table->info[i].short_preamble;
225 rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE;
226 }
227 sband->n_bitrates++;
228
229 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
230 rate[i].bitrate / 10, rate[i].hw_value);
231 }
232 }
233
234 static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc,
235 struct ieee80211_hw *hw)
236 {
237 struct ieee80211_channel *curchan = hw->conf.channel;
238 struct ath9k_channel *channel;
239 u8 chan_idx;
240
241 chan_idx = curchan->hw_value;
242 channel = &sc->sc_ah->channels[chan_idx];
243 ath9k_update_ichannel(sc, hw, channel);
244 return channel;
245 }
246
247 /*
248 * Set/change channels. If the channel is really being changed, it's done
249 * by reseting the chip. To accomplish this we must first cleanup any pending
250 * DMA, then restart stuff.
251 */
252 int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
253 struct ath9k_channel *hchan)
254 {
255 struct ath_hw *ah = sc->sc_ah;
256 bool fastcc = true, stopped;
257 struct ieee80211_channel *channel = hw->conf.channel;
258 int r;
259
260 if (sc->sc_flags & SC_OP_INVALID)
261 return -EIO;
262
263 ath9k_ps_wakeup(sc);
264
265 /*
266 * This is only performed if the channel settings have
267 * actually changed.
268 *
269 * To switch channels clear any pending DMA operations;
270 * wait long enough for the RX fifo to drain, reset the
271 * hardware at the new frequency, and then re-enable
272 * the relevant bits of the h/w.
273 */
274 ath9k_hw_set_interrupts(ah, 0);
275 ath_drain_all_txq(sc, false);
276 stopped = ath_stoprecv(sc);
277
278 /* XXX: do not flush receive queue here. We don't want
279 * to flush data frames already in queue because of
280 * changing channel. */
281
282 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
283 fastcc = false;
284
285 DPRINTF(sc, ATH_DBG_CONFIG,
286 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
287 sc->sc_ah->curchan->channel,
288 channel->center_freq, sc->tx_chan_width);
289
290 spin_lock_bh(&sc->sc_resetlock);
291
292 r = ath9k_hw_reset(ah, hchan, fastcc);
293 if (r) {
294 DPRINTF(sc, ATH_DBG_FATAL,
295 "Unable to reset channel (%u Mhz) "
296 "reset status %d\n",
297 channel->center_freq, r);
298 spin_unlock_bh(&sc->sc_resetlock);
299 goto ps_restore;
300 }
301 spin_unlock_bh(&sc->sc_resetlock);
302
303 sc->sc_flags &= ~SC_OP_FULL_RESET;
304
305 if (ath_startrecv(sc) != 0) {
306 DPRINTF(sc, ATH_DBG_FATAL,
307 "Unable to restart recv logic\n");
308 r = -EIO;
309 goto ps_restore;
310 }
311
312 ath_cache_conf_rate(sc, &hw->conf);
313 ath_update_txpow(sc);
314 ath9k_hw_set_interrupts(ah, sc->imask);
315
316 ps_restore:
317 ath9k_ps_restore(sc);
318 return r;
319 }
320
321 /*
322 * This routine performs the periodic noise floor calibration function
323 * that is used to adjust and optimize the chip performance. This
324 * takes environmental changes (location, temperature) into account.
325 * When the task is complete, it reschedules itself depending on the
326 * appropriate interval that was calculated.
327 */
328 static void ath_ani_calibrate(unsigned long data)
329 {
330 struct ath_softc *sc = (struct ath_softc *)data;
331 struct ath_hw *ah = sc->sc_ah;
332 bool longcal = false;
333 bool shortcal = false;
334 bool aniflag = false;
335 unsigned int timestamp = jiffies_to_msecs(jiffies);
336 u32 cal_interval, short_cal_interval;
337
338 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
339 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
340
341 /*
342 * don't calibrate when we're scanning.
343 * we are most likely not on our home channel.
344 */
345 spin_lock(&sc->ani_lock);
346 if (sc->sc_flags & SC_OP_SCANNING)
347 goto set_timer;
348
349 /* Only calibrate if awake */
350 if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
351 goto set_timer;
352
353 ath9k_ps_wakeup(sc);
354
355 /* Long calibration runs independently of short calibration. */
356 if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
357 longcal = true;
358 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
359 sc->ani.longcal_timer = timestamp;
360 }
361
362 /* Short calibration applies only while caldone is false */
363 if (!sc->ani.caldone) {
364 if ((timestamp - sc->ani.shortcal_timer) >= short_cal_interval) {
365 shortcal = true;
366 DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
367 sc->ani.shortcal_timer = timestamp;
368 sc->ani.resetcal_timer = timestamp;
369 }
370 } else {
371 if ((timestamp - sc->ani.resetcal_timer) >=
372 ATH_RESTART_CALINTERVAL) {
373 sc->ani.caldone = ath9k_hw_reset_calvalid(ah);
374 if (sc->ani.caldone)
375 sc->ani.resetcal_timer = timestamp;
376 }
377 }
378
379 /* Verify whether we must check ANI */
380 if ((timestamp - sc->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
381 aniflag = true;
382 sc->ani.checkani_timer = timestamp;
383 }
384
385 /* Skip all processing if there's nothing to do. */
386 if (longcal || shortcal || aniflag) {
387 /* Call ANI routine if necessary */
388 if (aniflag)
389 ath9k_hw_ani_monitor(ah, &sc->nodestats, ah->curchan);
390
391 /* Perform calibration if necessary */
392 if (longcal || shortcal) {
393 sc->ani.caldone = ath9k_hw_calibrate(ah, ah->curchan,
394 sc->rx_chainmask, longcal);
395
396 if (longcal)
397 sc->ani.noise_floor = ath9k_hw_getchan_noise(ah,
398 ah->curchan);
399
400 DPRINTF(sc, ATH_DBG_ANI," calibrate chan %u/%x nf: %d\n",
401 ah->curchan->channel, ah->curchan->channelFlags,
402 sc->ani.noise_floor);
403 }
404 }
405
406 ath9k_ps_restore(sc);
407
408 set_timer:
409 spin_unlock(&sc->ani_lock);
410 /*
411 * Set timer interval based on previous results.
412 * The interval must be the shortest necessary to satisfy ANI,
413 * short calibration and long calibration.
414 */
415 cal_interval = ATH_LONG_CALINTERVAL;
416 if (sc->sc_ah->config.enable_ani)
417 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
418 if (!sc->ani.caldone)
419 cal_interval = min(cal_interval, (u32)short_cal_interval);
420
421 mod_timer(&sc->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
422 }
423
424 static void ath_start_ani(struct ath_softc *sc)
425 {
426 unsigned long timestamp = jiffies_to_msecs(jiffies);
427
428 sc->ani.longcal_timer = timestamp;
429 sc->ani.shortcal_timer = timestamp;
430 sc->ani.checkani_timer = timestamp;
431
432 mod_timer(&sc->ani.timer,
433 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
434 }
435
436 /*
437 * Update tx/rx chainmask. For legacy association,
438 * hard code chainmask to 1x1, for 11n association, use
439 * the chainmask configuration, for bt coexistence, use
440 * the chainmask configuration even in legacy mode.
441 */
442 void ath_update_chainmask(struct ath_softc *sc, int is_ht)
443 {
444 if (is_ht ||
445 (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)) {
446 sc->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
447 sc->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
448 } else {
449 sc->tx_chainmask = 1;
450 sc->rx_chainmask = 1;
451 }
452
453 DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
454 sc->tx_chainmask, sc->rx_chainmask);
455 }
456
457 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
458 {
459 struct ath_node *an;
460
461 an = (struct ath_node *)sta->drv_priv;
462
463 if (sc->sc_flags & SC_OP_TXAGGR) {
464 ath_tx_node_init(sc, an);
465 an->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
466 sta->ht_cap.ampdu_factor);
467 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
468 an->last_rssi = ATH_RSSI_DUMMY_MARKER;
469 }
470 }
471
472 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
473 {
474 struct ath_node *an = (struct ath_node *)sta->drv_priv;
475
476 if (sc->sc_flags & SC_OP_TXAGGR)
477 ath_tx_node_cleanup(sc, an);
478 }
479
480 static void ath9k_tasklet(unsigned long data)
481 {
482 struct ath_softc *sc = (struct ath_softc *)data;
483 u32 status = sc->intrstatus;
484
485 ath9k_ps_wakeup(sc);
486
487 if (status & ATH9K_INT_FATAL) {
488 ath_reset(sc, false);
489 ath9k_ps_restore(sc);
490 return;
491 }
492
493 if (status & (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
494 spin_lock_bh(&sc->rx.rxflushlock);
495 ath_rx_tasklet(sc, 0);
496 spin_unlock_bh(&sc->rx.rxflushlock);
497 }
498
499 if (status & ATH9K_INT_TX)
500 ath_tx_tasklet(sc);
501
502 if ((status & ATH9K_INT_TSFOOR) &&
503 (sc->hw->conf.flags & IEEE80211_CONF_PS)) {
504 /*
505 * TSF sync does not look correct; remain awake to sync with
506 * the next Beacon.
507 */
508 DPRINTF(sc, ATH_DBG_PS, "TSFOOR - Sync with next Beacon\n");
509 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON | SC_OP_BEACON_SYNC;
510 }
511
512 /* re-enable hardware interrupt */
513 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
514 ath9k_ps_restore(sc);
515 }
516
517 irqreturn_t ath_isr(int irq, void *dev)
518 {
519 #define SCHED_INTR ( \
520 ATH9K_INT_FATAL | \
521 ATH9K_INT_RXORN | \
522 ATH9K_INT_RXEOL | \
523 ATH9K_INT_RX | \
524 ATH9K_INT_TX | \
525 ATH9K_INT_BMISS | \
526 ATH9K_INT_CST | \
527 ATH9K_INT_TSFOOR)
528
529 struct ath_softc *sc = dev;
530 struct ath_hw *ah = sc->sc_ah;
531 enum ath9k_int status;
532 bool sched = false;
533
534 /*
535 * The hardware is not ready/present, don't
536 * touch anything. Note this can happen early
537 * on if the IRQ is shared.
538 */
539 if (sc->sc_flags & SC_OP_INVALID)
540 return IRQ_NONE;
541
542
543 /* shared irq, not for us */
544
545 if (!ath9k_hw_intrpend(ah))
546 return IRQ_NONE;
547
548 /*
549 * Figure out the reason(s) for the interrupt. Note
550 * that the hal returns a pseudo-ISR that may include
551 * bits we haven't explicitly enabled so we mask the
552 * value to insure we only process bits we requested.
553 */
554 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
555 status &= sc->imask; /* discard unasked-for bits */
556
557 /*
558 * If there are no status bits set, then this interrupt was not
559 * for me (should have been caught above).
560 */
561 if (!status)
562 return IRQ_NONE;
563
564 /* Cache the status */
565 sc->intrstatus = status;
566
567 if (status & SCHED_INTR)
568 sched = true;
569
570 /*
571 * If a FATAL or RXORN interrupt is received, we have to reset the
572 * chip immediately.
573 */
574 if (status & (ATH9K_INT_FATAL | ATH9K_INT_RXORN))
575 goto chip_reset;
576
577 if (status & ATH9K_INT_SWBA)
578 tasklet_schedule(&sc->bcon_tasklet);
579
580 if (status & ATH9K_INT_TXURN)
581 ath9k_hw_updatetxtriglevel(ah, true);
582
583 if (status & ATH9K_INT_MIB) {
584 /*
585 * Disable interrupts until we service the MIB
586 * interrupt; otherwise it will continue to
587 * fire.
588 */
589 ath9k_hw_set_interrupts(ah, 0);
590 /*
591 * Let the hal handle the event. We assume
592 * it will clear whatever condition caused
593 * the interrupt.
594 */
595 ath9k_hw_procmibevent(ah, &sc->nodestats);
596 ath9k_hw_set_interrupts(ah, sc->imask);
597 }
598
599 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
600 if (status & ATH9K_INT_TIM_TIMER) {
601 /* Clear RxAbort bit so that we can
602 * receive frames */
603 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
604 ath9k_hw_setrxabort(sc->sc_ah, 0);
605 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
606 }
607
608 chip_reset:
609
610 ath_debug_stat_interrupt(sc, status);
611
612 if (sched) {
613 /* turn off every interrupt except SWBA */
614 ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA));
615 tasklet_schedule(&sc->intr_tq);
616 }
617
618 return IRQ_HANDLED;
619
620 #undef SCHED_INTR
621 }
622
623 static u32 ath_get_extchanmode(struct ath_softc *sc,
624 struct ieee80211_channel *chan,
625 enum nl80211_channel_type channel_type)
626 {
627 u32 chanmode = 0;
628
629 switch (chan->band) {
630 case IEEE80211_BAND_2GHZ:
631 switch(channel_type) {
632 case NL80211_CHAN_NO_HT:
633 case NL80211_CHAN_HT20:
634 chanmode = CHANNEL_G_HT20;
635 break;
636 case NL80211_CHAN_HT40PLUS:
637 chanmode = CHANNEL_G_HT40PLUS;
638 break;
639 case NL80211_CHAN_HT40MINUS:
640 chanmode = CHANNEL_G_HT40MINUS;
641 break;
642 }
643 break;
644 case IEEE80211_BAND_5GHZ:
645 switch(channel_type) {
646 case NL80211_CHAN_NO_HT:
647 case NL80211_CHAN_HT20:
648 chanmode = CHANNEL_A_HT20;
649 break;
650 case NL80211_CHAN_HT40PLUS:
651 chanmode = CHANNEL_A_HT40PLUS;
652 break;
653 case NL80211_CHAN_HT40MINUS:
654 chanmode = CHANNEL_A_HT40MINUS;
655 break;
656 }
657 break;
658 default:
659 break;
660 }
661
662 return chanmode;
663 }
664
665 static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
666 struct ath9k_keyval *hk, const u8 *addr,
667 bool authenticator)
668 {
669 const u8 *key_rxmic;
670 const u8 *key_txmic;
671
672 key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
673 key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
674
675 if (addr == NULL) {
676 /*
677 * Group key installation - only two key cache entries are used
678 * regardless of splitmic capability since group key is only
679 * used either for TX or RX.
680 */
681 if (authenticator) {
682 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
683 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
684 } else {
685 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
686 memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
687 }
688 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
689 }
690 if (!sc->splitmic) {
691 /* TX and RX keys share the same key cache entry. */
692 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
693 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
694 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
695 }
696
697 /* Separate key cache entries for TX and RX */
698
699 /* TX key goes at first index, RX key at +32. */
700 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
701 if (!ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, NULL)) {
702 /* TX MIC entry failed. No need to proceed further */
703 DPRINTF(sc, ATH_DBG_FATAL,
704 "Setting TX MIC Key Failed\n");
705 return 0;
706 }
707
708 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
709 /* XXX delete tx key on failure? */
710 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix + 32, hk, addr);
711 }
712
713 static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
714 {
715 int i;
716
717 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
718 if (test_bit(i, sc->keymap) ||
719 test_bit(i + 64, sc->keymap))
720 continue; /* At least one part of TKIP key allocated */
721 if (sc->splitmic &&
722 (test_bit(i + 32, sc->keymap) ||
723 test_bit(i + 64 + 32, sc->keymap)))
724 continue; /* At least one part of TKIP key allocated */
725
726 /* Found a free slot for a TKIP key */
727 return i;
728 }
729 return -1;
730 }
731
732 static int ath_reserve_key_cache_slot(struct ath_softc *sc)
733 {
734 int i;
735
736 /* First, try to find slots that would not be available for TKIP. */
737 if (sc->splitmic) {
738 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 4; i++) {
739 if (!test_bit(i, sc->keymap) &&
740 (test_bit(i + 32, sc->keymap) ||
741 test_bit(i + 64, sc->keymap) ||
742 test_bit(i + 64 + 32, sc->keymap)))
743 return i;
744 if (!test_bit(i + 32, sc->keymap) &&
745 (test_bit(i, sc->keymap) ||
746 test_bit(i + 64, sc->keymap) ||
747 test_bit(i + 64 + 32, sc->keymap)))
748 return i + 32;
749 if (!test_bit(i + 64, sc->keymap) &&
750 (test_bit(i , sc->keymap) ||
751 test_bit(i + 32, sc->keymap) ||
752 test_bit(i + 64 + 32, sc->keymap)))
753 return i + 64;
754 if (!test_bit(i + 64 + 32, sc->keymap) &&
755 (test_bit(i, sc->keymap) ||
756 test_bit(i + 32, sc->keymap) ||
757 test_bit(i + 64, sc->keymap)))
758 return i + 64 + 32;
759 }
760 } else {
761 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
762 if (!test_bit(i, sc->keymap) &&
763 test_bit(i + 64, sc->keymap))
764 return i;
765 if (test_bit(i, sc->keymap) &&
766 !test_bit(i + 64, sc->keymap))
767 return i + 64;
768 }
769 }
770
771 /* No partially used TKIP slots, pick any available slot */
772 for (i = IEEE80211_WEP_NKID; i < sc->keymax; i++) {
773 /* Do not allow slots that could be needed for TKIP group keys
774 * to be used. This limitation could be removed if we know that
775 * TKIP will not be used. */
776 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
777 continue;
778 if (sc->splitmic) {
779 if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
780 continue;
781 if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
782 continue;
783 }
784
785 if (!test_bit(i, sc->keymap))
786 return i; /* Found a free slot for a key */
787 }
788
789 /* No free slot found */
790 return -1;
791 }
792
793 static int ath_key_config(struct ath_softc *sc,
794 struct ieee80211_vif *vif,
795 struct ieee80211_sta *sta,
796 struct ieee80211_key_conf *key)
797 {
798 struct ath9k_keyval hk;
799 const u8 *mac = NULL;
800 int ret = 0;
801 int idx;
802
803 memset(&hk, 0, sizeof(hk));
804
805 switch (key->alg) {
806 case ALG_WEP:
807 hk.kv_type = ATH9K_CIPHER_WEP;
808 break;
809 case ALG_TKIP:
810 hk.kv_type = ATH9K_CIPHER_TKIP;
811 break;
812 case ALG_CCMP:
813 hk.kv_type = ATH9K_CIPHER_AES_CCM;
814 break;
815 default:
816 return -EOPNOTSUPP;
817 }
818
819 hk.kv_len = key->keylen;
820 memcpy(hk.kv_val, key->key, key->keylen);
821
822 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
823 /* For now, use the default keys for broadcast keys. This may
824 * need to change with virtual interfaces. */
825 idx = key->keyidx;
826 } else if (key->keyidx) {
827 if (WARN_ON(!sta))
828 return -EOPNOTSUPP;
829 mac = sta->addr;
830
831 if (vif->type != NL80211_IFTYPE_AP) {
832 /* Only keyidx 0 should be used with unicast key, but
833 * allow this for client mode for now. */
834 idx = key->keyidx;
835 } else
836 return -EIO;
837 } else {
838 if (WARN_ON(!sta))
839 return -EOPNOTSUPP;
840 mac = sta->addr;
841
842 if (key->alg == ALG_TKIP)
843 idx = ath_reserve_key_cache_slot_tkip(sc);
844 else
845 idx = ath_reserve_key_cache_slot(sc);
846 if (idx < 0)
847 return -ENOSPC; /* no free key cache entries */
848 }
849
850 if (key->alg == ALG_TKIP)
851 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac,
852 vif->type == NL80211_IFTYPE_AP);
853 else
854 ret = ath9k_hw_set_keycache_entry(sc->sc_ah, idx, &hk, mac);
855
856 if (!ret)
857 return -EIO;
858
859 set_bit(idx, sc->keymap);
860 if (key->alg == ALG_TKIP) {
861 set_bit(idx + 64, sc->keymap);
862 if (sc->splitmic) {
863 set_bit(idx + 32, sc->keymap);
864 set_bit(idx + 64 + 32, sc->keymap);
865 }
866 }
867
868 return idx;
869 }
870
871 static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
872 {
873 ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
874 if (key->hw_key_idx < IEEE80211_WEP_NKID)
875 return;
876
877 clear_bit(key->hw_key_idx, sc->keymap);
878 if (key->alg != ALG_TKIP)
879 return;
880
881 clear_bit(key->hw_key_idx + 64, sc->keymap);
882 if (sc->splitmic) {
883 clear_bit(key->hw_key_idx + 32, sc->keymap);
884 clear_bit(key->hw_key_idx + 64 + 32, sc->keymap);
885 }
886 }
887
888 static void setup_ht_cap(struct ath_softc *sc,
889 struct ieee80211_sta_ht_cap *ht_info)
890 {
891 #define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3 /* 2 ^ 16 */
892 #define ATH9K_HT_CAP_MPDUDENSITY_8 0x6 /* 8 usec */
893 u8 tx_streams, rx_streams;
894
895 ht_info->ht_supported = true;
896 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
897 IEEE80211_HT_CAP_SM_PS |
898 IEEE80211_HT_CAP_SGI_40 |
899 IEEE80211_HT_CAP_DSSSCCK40;
900
901 ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
902 ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
903
904 /* set up supported mcs set */
905 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
906 tx_streams = !(sc->tx_chainmask & (sc->tx_chainmask - 1)) ? 1 : 2;
907 rx_streams = !(sc->rx_chainmask & (sc->rx_chainmask - 1)) ? 1 : 2;
908
909 if (tx_streams != rx_streams) {
910 DPRINTF(sc, ATH_DBG_CONFIG, "TX streams %d, RX streams: %d\n",
911 tx_streams, rx_streams);
912 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
913 ht_info->mcs.tx_params |= ((tx_streams - 1) <<
914 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
915 }
916
917 ht_info->mcs.rx_mask[0] = 0xff;
918 if (rx_streams >= 2)
919 ht_info->mcs.rx_mask[1] = 0xff;
920
921 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
922 }
923
924 static void ath9k_bss_assoc_info(struct ath_softc *sc,
925 struct ieee80211_vif *vif,
926 struct ieee80211_bss_conf *bss_conf)
927 {
928
929 if (bss_conf->assoc) {
930 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
931 bss_conf->aid, sc->curbssid);
932
933 /* New association, store aid */
934 sc->curaid = bss_conf->aid;
935 ath9k_hw_write_associd(sc);
936
937 /*
938 * Request a re-configuration of Beacon related timers
939 * on the receipt of the first Beacon frame (i.e.,
940 * after time sync with the AP).
941 */
942 sc->sc_flags |= SC_OP_BEACON_SYNC;
943
944 /* Configure the beacon */
945 ath_beacon_config(sc, vif);
946
947 /* Reset rssi stats */
948 sc->nodestats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
949 sc->nodestats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
950 sc->nodestats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
951 sc->nodestats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
952
953 ath_start_ani(sc);
954 } else {
955 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
956 sc->curaid = 0;
957 /* Stop ANI */
958 del_timer_sync(&sc->ani.timer);
959 }
960 }
961
962 /********************************/
963 /* LED functions */
964 /********************************/
965
966 static void ath_led_blink_work(struct work_struct *work)
967 {
968 struct ath_softc *sc = container_of(work, struct ath_softc,
969 ath_led_blink_work.work);
970
971 if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
972 return;
973
974 if ((sc->led_on_duration == ATH_LED_ON_DURATION_IDLE) ||
975 (sc->led_off_duration == ATH_LED_OFF_DURATION_IDLE))
976 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
977 else
978 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
979 (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
980
981 queue_delayed_work(sc->hw->workqueue, &sc->ath_led_blink_work,
982 (sc->sc_flags & SC_OP_LED_ON) ?
983 msecs_to_jiffies(sc->led_off_duration) :
984 msecs_to_jiffies(sc->led_on_duration));
985
986 sc->led_on_duration = sc->led_on_cnt ?
987 max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25) :
988 ATH_LED_ON_DURATION_IDLE;
989 sc->led_off_duration = sc->led_off_cnt ?
990 max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10) :
991 ATH_LED_OFF_DURATION_IDLE;
992 sc->led_on_cnt = sc->led_off_cnt = 0;
993 if (sc->sc_flags & SC_OP_LED_ON)
994 sc->sc_flags &= ~SC_OP_LED_ON;
995 else
996 sc->sc_flags |= SC_OP_LED_ON;
997 }
998
999 static void ath_led_brightness(struct led_classdev *led_cdev,
1000 enum led_brightness brightness)
1001 {
1002 struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
1003 struct ath_softc *sc = led->sc;
1004
1005 switch (brightness) {
1006 case LED_OFF:
1007 if (led->led_type == ATH_LED_ASSOC ||
1008 led->led_type == ATH_LED_RADIO) {
1009 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
1010 (led->led_type == ATH_LED_RADIO));
1011 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1012 if (led->led_type == ATH_LED_RADIO)
1013 sc->sc_flags &= ~SC_OP_LED_ON;
1014 } else {
1015 sc->led_off_cnt++;
1016 }
1017 break;
1018 case LED_FULL:
1019 if (led->led_type == ATH_LED_ASSOC) {
1020 sc->sc_flags |= SC_OP_LED_ASSOCIATED;
1021 queue_delayed_work(sc->hw->workqueue,
1022 &sc->ath_led_blink_work, 0);
1023 } else if (led->led_type == ATH_LED_RADIO) {
1024 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
1025 sc->sc_flags |= SC_OP_LED_ON;
1026 } else {
1027 sc->led_on_cnt++;
1028 }
1029 break;
1030 default:
1031 break;
1032 }
1033 }
1034
1035 static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
1036 char *trigger)
1037 {
1038 int ret;
1039
1040 led->sc = sc;
1041 led->led_cdev.name = led->name;
1042 led->led_cdev.default_trigger = trigger;
1043 led->led_cdev.brightness_set = ath_led_brightness;
1044
1045 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1046 if (ret)
1047 DPRINTF(sc, ATH_DBG_FATAL,
1048 "Failed to register led:%s", led->name);
1049 else
1050 led->registered = 1;
1051 return ret;
1052 }
1053
1054 static void ath_unregister_led(struct ath_led *led)
1055 {
1056 if (led->registered) {
1057 led_classdev_unregister(&led->led_cdev);
1058 led->registered = 0;
1059 }
1060 }
1061
1062 static void ath_deinit_leds(struct ath_softc *sc)
1063 {
1064 cancel_delayed_work_sync(&sc->ath_led_blink_work);
1065 ath_unregister_led(&sc->assoc_led);
1066 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1067 ath_unregister_led(&sc->tx_led);
1068 ath_unregister_led(&sc->rx_led);
1069 ath_unregister_led(&sc->radio_led);
1070 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1071 }
1072
1073 static void ath_init_leds(struct ath_softc *sc)
1074 {
1075 char *trigger;
1076 int ret;
1077
1078 /* Configure gpio 1 for output */
1079 ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
1080 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1081 /* LED off, active low */
1082 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1083
1084 INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
1085
1086 trigger = ieee80211_get_radio_led_name(sc->hw);
1087 snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
1088 "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
1089 ret = ath_register_led(sc, &sc->radio_led, trigger);
1090 sc->radio_led.led_type = ATH_LED_RADIO;
1091 if (ret)
1092 goto fail;
1093
1094 trigger = ieee80211_get_assoc_led_name(sc->hw);
1095 snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
1096 "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
1097 ret = ath_register_led(sc, &sc->assoc_led, trigger);
1098 sc->assoc_led.led_type = ATH_LED_ASSOC;
1099 if (ret)
1100 goto fail;
1101
1102 trigger = ieee80211_get_tx_led_name(sc->hw);
1103 snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
1104 "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
1105 ret = ath_register_led(sc, &sc->tx_led, trigger);
1106 sc->tx_led.led_type = ATH_LED_TX;
1107 if (ret)
1108 goto fail;
1109
1110 trigger = ieee80211_get_rx_led_name(sc->hw);
1111 snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
1112 "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
1113 ret = ath_register_led(sc, &sc->rx_led, trigger);
1114 sc->rx_led.led_type = ATH_LED_RX;
1115 if (ret)
1116 goto fail;
1117
1118 return;
1119
1120 fail:
1121 ath_deinit_leds(sc);
1122 }
1123
1124 void ath_radio_enable(struct ath_softc *sc)
1125 {
1126 struct ath_hw *ah = sc->sc_ah;
1127 struct ieee80211_channel *channel = sc->hw->conf.channel;
1128 int r;
1129
1130 ath9k_ps_wakeup(sc);
1131 ath9k_hw_configpcipowersave(ah, 0);
1132
1133 if (!ah->curchan)
1134 ah->curchan = ath_get_curchannel(sc, sc->hw);
1135
1136 spin_lock_bh(&sc->sc_resetlock);
1137 r = ath9k_hw_reset(ah, ah->curchan, false);
1138 if (r) {
1139 DPRINTF(sc, ATH_DBG_FATAL,
1140 "Unable to reset channel %u (%uMhz) ",
1141 "reset status %d\n",
1142 channel->center_freq, r);
1143 }
1144 spin_unlock_bh(&sc->sc_resetlock);
1145
1146 ath_update_txpow(sc);
1147 if (ath_startrecv(sc) != 0) {
1148 DPRINTF(sc, ATH_DBG_FATAL,
1149 "Unable to restart recv logic\n");
1150 return;
1151 }
1152
1153 if (sc->sc_flags & SC_OP_BEACONS)
1154 ath_beacon_config(sc, NULL); /* restart beacons */
1155
1156 /* Re-Enable interrupts */
1157 ath9k_hw_set_interrupts(ah, sc->imask);
1158
1159 /* Enable LED */
1160 ath9k_hw_cfg_output(ah, ATH_LED_PIN,
1161 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1162 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
1163
1164 ieee80211_wake_queues(sc->hw);
1165 ath9k_ps_restore(sc);
1166 }
1167
1168 void ath_radio_disable(struct ath_softc *sc)
1169 {
1170 struct ath_hw *ah = sc->sc_ah;
1171 struct ieee80211_channel *channel = sc->hw->conf.channel;
1172 int r;
1173
1174 ath9k_ps_wakeup(sc);
1175 ieee80211_stop_queues(sc->hw);
1176
1177 /* Disable LED */
1178 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
1179 ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
1180
1181 /* Disable interrupts */
1182 ath9k_hw_set_interrupts(ah, 0);
1183
1184 ath_drain_all_txq(sc, false); /* clear pending tx frames */
1185 ath_stoprecv(sc); /* turn off frame recv */
1186 ath_flushrecv(sc); /* flush recv queue */
1187
1188 if (!ah->curchan)
1189 ah->curchan = ath_get_curchannel(sc, sc->hw);
1190
1191 spin_lock_bh(&sc->sc_resetlock);
1192 r = ath9k_hw_reset(ah, ah->curchan, false);
1193 if (r) {
1194 DPRINTF(sc, ATH_DBG_FATAL,
1195 "Unable to reset channel %u (%uMhz) "
1196 "reset status %d\n",
1197 channel->center_freq, r);
1198 }
1199 spin_unlock_bh(&sc->sc_resetlock);
1200
1201 ath9k_hw_phy_disable(ah);
1202 ath9k_hw_configpcipowersave(ah, 1);
1203 ath9k_ps_restore(sc);
1204 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1205 }
1206
1207 /*******************/
1208 /* Rfkill */
1209 /*******************/
1210
1211 static bool ath_is_rfkill_set(struct ath_softc *sc)
1212 {
1213 struct ath_hw *ah = sc->sc_ah;
1214
1215 return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
1216 ah->rfkill_polarity;
1217 }
1218
1219 static void ath9k_rfkill_poll_state(struct ieee80211_hw *hw)
1220 {
1221 struct ath_wiphy *aphy = hw->priv;
1222 struct ath_softc *sc = aphy->sc;
1223 bool blocked = !!ath_is_rfkill_set(sc);
1224
1225 wiphy_rfkill_set_hw_state(hw->wiphy, blocked);
1226
1227 if (blocked)
1228 ath_radio_disable(sc);
1229 else
1230 ath_radio_enable(sc);
1231 }
1232
1233 static void ath_start_rfkill_poll(struct ath_softc *sc)
1234 {
1235 struct ath_hw *ah = sc->sc_ah;
1236
1237 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1238 wiphy_rfkill_start_polling(sc->hw->wiphy);
1239 }
1240
1241 void ath_cleanup(struct ath_softc *sc)
1242 {
1243 ath_detach(sc);
1244 free_irq(sc->irq, sc);
1245 ath_bus_cleanup(sc);
1246 kfree(sc->sec_wiphy);
1247 ieee80211_free_hw(sc->hw);
1248 }
1249
1250 void ath_detach(struct ath_softc *sc)
1251 {
1252 struct ieee80211_hw *hw = sc->hw;
1253 int i = 0;
1254
1255 ath9k_ps_wakeup(sc);
1256
1257 DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
1258
1259 ath_deinit_leds(sc);
1260 cancel_work_sync(&sc->chan_work);
1261 cancel_delayed_work_sync(&sc->wiphy_work);
1262
1263 for (i = 0; i < sc->num_sec_wiphy; i++) {
1264 struct ath_wiphy *aphy = sc->sec_wiphy[i];
1265 if (aphy == NULL)
1266 continue;
1267 sc->sec_wiphy[i] = NULL;
1268 ieee80211_unregister_hw(aphy->hw);
1269 ieee80211_free_hw(aphy->hw);
1270 }
1271 ieee80211_unregister_hw(hw);
1272 ath_rx_cleanup(sc);
1273 ath_tx_cleanup(sc);
1274
1275 tasklet_kill(&sc->intr_tq);
1276 tasklet_kill(&sc->bcon_tasklet);
1277
1278 if (!(sc->sc_flags & SC_OP_INVALID))
1279 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
1280
1281 /* cleanup tx queues */
1282 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1283 if (ATH_TXQ_SETUP(sc, i))
1284 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1285
1286 ath9k_hw_detach(sc->sc_ah);
1287 ath9k_exit_debug(sc);
1288 ath9k_ps_restore(sc);
1289 }
1290
1291 static int ath9k_reg_notifier(struct wiphy *wiphy,
1292 struct regulatory_request *request)
1293 {
1294 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
1295 struct ath_wiphy *aphy = hw->priv;
1296 struct ath_softc *sc = aphy->sc;
1297 struct ath_regulatory *reg = &sc->sc_ah->regulatory;
1298
1299 return ath_reg_notifier_apply(wiphy, request, reg);
1300 }
1301
1302 static int ath_init(u16 devid, struct ath_softc *sc)
1303 {
1304 struct ath_hw *ah = NULL;
1305 int status;
1306 int error = 0, i;
1307 int csz = 0;
1308
1309 /* XXX: hardware will not be ready until ath_open() being called */
1310 sc->sc_flags |= SC_OP_INVALID;
1311
1312 if (ath9k_init_debug(sc) < 0)
1313 printk(KERN_ERR "Unable to create debugfs files\n");
1314
1315 spin_lock_init(&sc->wiphy_lock);
1316 spin_lock_init(&sc->sc_resetlock);
1317 spin_lock_init(&sc->sc_serial_rw);
1318 spin_lock_init(&sc->ani_lock);
1319 mutex_init(&sc->mutex);
1320 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1321 tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
1322 (unsigned long)sc);
1323
1324 /*
1325 * Cache line size is used to size and align various
1326 * structures used to communicate with the hardware.
1327 */
1328 ath_read_cachesize(sc, &csz);
1329 /* XXX assert csz is non-zero */
1330 sc->cachelsz = csz << 2; /* convert to bytes */
1331
1332 ah = ath9k_hw_attach(devid, sc, &status);
1333 if (ah == NULL) {
1334 DPRINTF(sc, ATH_DBG_FATAL,
1335 "Unable to attach hardware; HAL status %d\n", status);
1336 error = -ENXIO;
1337 goto bad;
1338 }
1339 sc->sc_ah = ah;
1340
1341 /* Get the hardware key cache size. */
1342 sc->keymax = ah->caps.keycache_size;
1343 if (sc->keymax > ATH_KEYMAX) {
1344 DPRINTF(sc, ATH_DBG_ANY,
1345 "Warning, using only %u entries in %u key cache\n",
1346 ATH_KEYMAX, sc->keymax);
1347 sc->keymax = ATH_KEYMAX;
1348 }
1349
1350 /*
1351 * Reset the key cache since some parts do not
1352 * reset the contents on initial power up.
1353 */
1354 for (i = 0; i < sc->keymax; i++)
1355 ath9k_hw_keyreset(ah, (u16) i);
1356
1357 if (error)
1358 goto bad;
1359
1360 /* default to MONITOR mode */
1361 sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
1362
1363 /* Setup rate tables */
1364
1365 ath_rate_attach(sc);
1366 ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1367 ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1368
1369 /*
1370 * Allocate hardware transmit queues: one queue for
1371 * beacon frames and one data queue for each QoS
1372 * priority. Note that the hal handles reseting
1373 * these queues at the needed time.
1374 */
1375 sc->beacon.beaconq = ath_beaconq_setup(ah);
1376 if (sc->beacon.beaconq == -1) {
1377 DPRINTF(sc, ATH_DBG_FATAL,
1378 "Unable to setup a beacon xmit queue\n");
1379 error = -EIO;
1380 goto bad2;
1381 }
1382 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1383 if (sc->beacon.cabq == NULL) {
1384 DPRINTF(sc, ATH_DBG_FATAL,
1385 "Unable to setup CAB xmit queue\n");
1386 error = -EIO;
1387 goto bad2;
1388 }
1389
1390 sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
1391 ath_cabq_update(sc);
1392
1393 for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1394 sc->tx.hwq_map[i] = -1;
1395
1396 /* Setup data queues */
1397 /* NB: ensure BK queue is the lowest priority h/w queue */
1398 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1399 DPRINTF(sc, ATH_DBG_FATAL,
1400 "Unable to setup xmit queue for BK traffic\n");
1401 error = -EIO;
1402 goto bad2;
1403 }
1404
1405 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1406 DPRINTF(sc, ATH_DBG_FATAL,
1407 "Unable to setup xmit queue for BE traffic\n");
1408 error = -EIO;
1409 goto bad2;
1410 }
1411 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1412 DPRINTF(sc, ATH_DBG_FATAL,
1413 "Unable to setup xmit queue for VI traffic\n");
1414 error = -EIO;
1415 goto bad2;
1416 }
1417 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1418 DPRINTF(sc, ATH_DBG_FATAL,
1419 "Unable to setup xmit queue for VO traffic\n");
1420 error = -EIO;
1421 goto bad2;
1422 }
1423
1424 /* Initializes the noise floor to a reasonable default value.
1425 * Later on this will be updated during ANI processing. */
1426
1427 sc->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1428 setup_timer(&sc->ani.timer, ath_ani_calibrate, (unsigned long)sc);
1429
1430 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1431 ATH9K_CIPHER_TKIP, NULL)) {
1432 /*
1433 * Whether we should enable h/w TKIP MIC.
1434 * XXX: if we don't support WME TKIP MIC, then we wouldn't
1435 * report WMM capable, so it's always safe to turn on
1436 * TKIP MIC in this case.
1437 */
1438 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1439 0, 1, NULL);
1440 }
1441
1442 /*
1443 * Check whether the separate key cache entries
1444 * are required to handle both tx+rx MIC keys.
1445 * With split mic keys the number of stations is limited
1446 * to 27 otherwise 59.
1447 */
1448 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1449 ATH9K_CIPHER_TKIP, NULL)
1450 && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1451 ATH9K_CIPHER_MIC, NULL)
1452 && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1453 0, NULL))
1454 sc->splitmic = 1;
1455
1456 /* turn on mcast key search if possible */
1457 if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1458 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1459 1, NULL);
1460
1461 sc->config.txpowlimit = ATH_TXPOWER_MAX;
1462
1463 /* 11n Capabilities */
1464 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1465 sc->sc_flags |= SC_OP_TXAGGR;
1466 sc->sc_flags |= SC_OP_RXAGGR;
1467 }
1468
1469 sc->tx_chainmask = ah->caps.tx_chainmask;
1470 sc->rx_chainmask = ah->caps.rx_chainmask;
1471
1472 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
1473 sc->rx.defant = ath9k_hw_getdefantenna(ah);
1474
1475 if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
1476 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
1477
1478 sc->beacon.slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
1479
1480 /* initialize beacon slots */
1481 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
1482 sc->beacon.bslot[i] = NULL;
1483 sc->beacon.bslot_aphy[i] = NULL;
1484 }
1485
1486 /* setup channels and rates */
1487
1488 sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
1489 sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1490 sc->rates[IEEE80211_BAND_2GHZ];
1491 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
1492 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1493 ARRAY_SIZE(ath9k_2ghz_chantable);
1494
1495 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
1496 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
1497 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1498 sc->rates[IEEE80211_BAND_5GHZ];
1499 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
1500 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1501 ARRAY_SIZE(ath9k_5ghz_chantable);
1502 }
1503
1504 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)
1505 ath9k_hw_btcoex_enable(sc->sc_ah);
1506
1507 return 0;
1508 bad2:
1509 /* cleanup tx queues */
1510 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1511 if (ATH_TXQ_SETUP(sc, i))
1512 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1513 bad:
1514 if (ah)
1515 ath9k_hw_detach(ah);
1516 ath9k_exit_debug(sc);
1517
1518 return error;
1519 }
1520
1521 void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
1522 {
1523 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1524 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1525 IEEE80211_HW_SIGNAL_DBM |
1526 IEEE80211_HW_AMPDU_AGGREGATION |
1527 IEEE80211_HW_SUPPORTS_PS |
1528 IEEE80211_HW_PS_NULLFUNC_STACK |
1529 IEEE80211_HW_SPECTRUM_MGMT;
1530
1531 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
1532 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1533
1534 hw->wiphy->interface_modes =
1535 BIT(NL80211_IFTYPE_AP) |
1536 BIT(NL80211_IFTYPE_STATION) |
1537 BIT(NL80211_IFTYPE_ADHOC) |
1538 BIT(NL80211_IFTYPE_MESH_POINT);
1539
1540 hw->queues = 4;
1541 hw->max_rates = 4;
1542 hw->channel_change_time = 5000;
1543 hw->max_listen_interval = 10;
1544 /* Hardware supports 10 but we use 4 */
1545 hw->max_rate_tries = 4;
1546 hw->sta_data_size = sizeof(struct ath_node);
1547 hw->vif_data_size = sizeof(struct ath_vif);
1548
1549 hw->rate_control_algorithm = "ath9k_rate_control";
1550
1551 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
1552 &sc->sbands[IEEE80211_BAND_2GHZ];
1553 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1554 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1555 &sc->sbands[IEEE80211_BAND_5GHZ];
1556 }
1557
1558 int ath_attach(u16 devid, struct ath_softc *sc)
1559 {
1560 struct ieee80211_hw *hw = sc->hw;
1561 int error = 0, i;
1562 struct ath_regulatory *reg;
1563
1564 DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
1565
1566 error = ath_init(devid, sc);
1567 if (error != 0)
1568 return error;
1569
1570 /* get mac address from hardware and set in mac80211 */
1571
1572 SET_IEEE80211_PERM_ADDR(hw, sc->sc_ah->macaddr);
1573
1574 ath_set_hw_capab(sc, hw);
1575
1576 error = ath_regd_init(&sc->sc_ah->regulatory, sc->hw->wiphy,
1577 ath9k_reg_notifier);
1578 if (error)
1579 return error;
1580
1581 reg = &sc->sc_ah->regulatory;
1582
1583 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1584 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
1585 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1586 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
1587 }
1588
1589 /* initialize tx/rx engine */
1590 error = ath_tx_init(sc, ATH_TXBUF);
1591 if (error != 0)
1592 goto error_attach;
1593
1594 error = ath_rx_init(sc, ATH_RXBUF);
1595 if (error != 0)
1596 goto error_attach;
1597
1598 INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
1599 INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work);
1600 sc->wiphy_scheduler_int = msecs_to_jiffies(500);
1601
1602 error = ieee80211_register_hw(hw);
1603
1604 if (!ath_is_world_regd(reg)) {
1605 error = regulatory_hint(hw->wiphy, reg->alpha2);
1606 if (error)
1607 goto error_attach;
1608 }
1609
1610 /* Initialize LED control */
1611 ath_init_leds(sc);
1612
1613 ath_start_rfkill_poll(sc);
1614
1615 return 0;
1616
1617 error_attach:
1618 /* cleanup tx queues */
1619 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1620 if (ATH_TXQ_SETUP(sc, i))
1621 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1622
1623 ath9k_hw_detach(sc->sc_ah);
1624 ath9k_exit_debug(sc);
1625
1626 return error;
1627 }
1628
1629 int ath_reset(struct ath_softc *sc, bool retry_tx)
1630 {
1631 struct ath_hw *ah = sc->sc_ah;
1632 struct ieee80211_hw *hw = sc->hw;
1633 int r;
1634
1635 ath9k_hw_set_interrupts(ah, 0);
1636 ath_drain_all_txq(sc, retry_tx);
1637 ath_stoprecv(sc);
1638 ath_flushrecv(sc);
1639
1640 spin_lock_bh(&sc->sc_resetlock);
1641 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
1642 if (r)
1643 DPRINTF(sc, ATH_DBG_FATAL,
1644 "Unable to reset hardware; reset status %d\n", r);
1645 spin_unlock_bh(&sc->sc_resetlock);
1646
1647 if (ath_startrecv(sc) != 0)
1648 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
1649
1650 /*
1651 * We may be doing a reset in response to a request
1652 * that changes the channel so update any state that
1653 * might change as a result.
1654 */
1655 ath_cache_conf_rate(sc, &hw->conf);
1656
1657 ath_update_txpow(sc);
1658
1659 if (sc->sc_flags & SC_OP_BEACONS)
1660 ath_beacon_config(sc, NULL); /* restart beacons */
1661
1662 ath9k_hw_set_interrupts(ah, sc->imask);
1663
1664 if (retry_tx) {
1665 int i;
1666 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1667 if (ATH_TXQ_SETUP(sc, i)) {
1668 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1669 ath_txq_schedule(sc, &sc->tx.txq[i]);
1670 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
1671 }
1672 }
1673 }
1674
1675 return r;
1676 }
1677
1678 /*
1679 * This function will allocate both the DMA descriptor structure, and the
1680 * buffers it contains. These are used to contain the descriptors used
1681 * by the system.
1682 */
1683 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1684 struct list_head *head, const char *name,
1685 int nbuf, int ndesc)
1686 {
1687 #define DS2PHYS(_dd, _ds) \
1688 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1689 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1690 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1691
1692 struct ath_desc *ds;
1693 struct ath_buf *bf;
1694 int i, bsize, error;
1695
1696 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1697 name, nbuf, ndesc);
1698
1699 INIT_LIST_HEAD(head);
1700 /* ath_desc must be a multiple of DWORDs */
1701 if ((sizeof(struct ath_desc) % 4) != 0) {
1702 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
1703 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1704 error = -ENOMEM;
1705 goto fail;
1706 }
1707
1708 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1709
1710 /*
1711 * Need additional DMA memory because we can't use
1712 * descriptors that cross the 4K page boundary. Assume
1713 * one skipped descriptor per 4K page.
1714 */
1715 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1716 u32 ndesc_skipped =
1717 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1718 u32 dma_len;
1719
1720 while (ndesc_skipped) {
1721 dma_len = ndesc_skipped * sizeof(struct ath_desc);
1722 dd->dd_desc_len += dma_len;
1723
1724 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1725 };
1726 }
1727
1728 /* allocate descriptors */
1729 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
1730 &dd->dd_desc_paddr, GFP_KERNEL);
1731 if (dd->dd_desc == NULL) {
1732 error = -ENOMEM;
1733 goto fail;
1734 }
1735 ds = dd->dd_desc;
1736 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
1737 name, ds, (u32) dd->dd_desc_len,
1738 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1739
1740 /* allocate buffers */
1741 bsize = sizeof(struct ath_buf) * nbuf;
1742 bf = kzalloc(bsize, GFP_KERNEL);
1743 if (bf == NULL) {
1744 error = -ENOMEM;
1745 goto fail2;
1746 }
1747 dd->dd_bufptr = bf;
1748
1749 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1750 bf->bf_desc = ds;
1751 bf->bf_daddr = DS2PHYS(dd, ds);
1752
1753 if (!(sc->sc_ah->caps.hw_caps &
1754 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1755 /*
1756 * Skip descriptor addresses which can cause 4KB
1757 * boundary crossing (addr + length) with a 32 dword
1758 * descriptor fetch.
1759 */
1760 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1761 ASSERT((caddr_t) bf->bf_desc <
1762 ((caddr_t) dd->dd_desc +
1763 dd->dd_desc_len));
1764
1765 ds += ndesc;
1766 bf->bf_desc = ds;
1767 bf->bf_daddr = DS2PHYS(dd, ds);
1768 }
1769 }
1770 list_add_tail(&bf->list, head);
1771 }
1772 return 0;
1773 fail2:
1774 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1775 dd->dd_desc_paddr);
1776 fail:
1777 memset(dd, 0, sizeof(*dd));
1778 return error;
1779 #undef ATH_DESC_4KB_BOUND_CHECK
1780 #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1781 #undef DS2PHYS
1782 }
1783
1784 void ath_descdma_cleanup(struct ath_softc *sc,
1785 struct ath_descdma *dd,
1786 struct list_head *head)
1787 {
1788 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1789 dd->dd_desc_paddr);
1790
1791 INIT_LIST_HEAD(head);
1792 kfree(dd->dd_bufptr);
1793 memset(dd, 0, sizeof(*dd));
1794 }
1795
1796 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1797 {
1798 int qnum;
1799
1800 switch (queue) {
1801 case 0:
1802 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
1803 break;
1804 case 1:
1805 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
1806 break;
1807 case 2:
1808 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1809 break;
1810 case 3:
1811 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
1812 break;
1813 default:
1814 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1815 break;
1816 }
1817
1818 return qnum;
1819 }
1820
1821 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1822 {
1823 int qnum;
1824
1825 switch (queue) {
1826 case ATH9K_WME_AC_VO:
1827 qnum = 0;
1828 break;
1829 case ATH9K_WME_AC_VI:
1830 qnum = 1;
1831 break;
1832 case ATH9K_WME_AC_BE:
1833 qnum = 2;
1834 break;
1835 case ATH9K_WME_AC_BK:
1836 qnum = 3;
1837 break;
1838 default:
1839 qnum = -1;
1840 break;
1841 }
1842
1843 return qnum;
1844 }
1845
1846 /* XXX: Remove me once we don't depend on ath9k_channel for all
1847 * this redundant data */
1848 void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
1849 struct ath9k_channel *ichan)
1850 {
1851 struct ieee80211_channel *chan = hw->conf.channel;
1852 struct ieee80211_conf *conf = &hw->conf;
1853
1854 ichan->channel = chan->center_freq;
1855 ichan->chan = chan;
1856
1857 if (chan->band == IEEE80211_BAND_2GHZ) {
1858 ichan->chanmode = CHANNEL_G;
1859 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM;
1860 } else {
1861 ichan->chanmode = CHANNEL_A;
1862 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
1863 }
1864
1865 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
1866
1867 if (conf_is_ht(conf)) {
1868 if (conf_is_ht40(conf))
1869 sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
1870
1871 ichan->chanmode = ath_get_extchanmode(sc, chan,
1872 conf->channel_type);
1873 }
1874 }
1875
1876 /**********************/
1877 /* mac80211 callbacks */
1878 /**********************/
1879
1880 static int ath9k_start(struct ieee80211_hw *hw)
1881 {
1882 struct ath_wiphy *aphy = hw->priv;
1883 struct ath_softc *sc = aphy->sc;
1884 struct ieee80211_channel *curchan = hw->conf.channel;
1885 struct ath9k_channel *init_channel;
1886 int r;
1887
1888 DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1889 "initial channel: %d MHz\n", curchan->center_freq);
1890
1891 mutex_lock(&sc->mutex);
1892
1893 if (ath9k_wiphy_started(sc)) {
1894 if (sc->chan_idx == curchan->hw_value) {
1895 /*
1896 * Already on the operational channel, the new wiphy
1897 * can be marked active.
1898 */
1899 aphy->state = ATH_WIPHY_ACTIVE;
1900 ieee80211_wake_queues(hw);
1901 } else {
1902 /*
1903 * Another wiphy is on another channel, start the new
1904 * wiphy in paused state.
1905 */
1906 aphy->state = ATH_WIPHY_PAUSED;
1907 ieee80211_stop_queues(hw);
1908 }
1909 mutex_unlock(&sc->mutex);
1910 return 0;
1911 }
1912 aphy->state = ATH_WIPHY_ACTIVE;
1913
1914 /* setup initial channel */
1915
1916 sc->chan_idx = curchan->hw_value;
1917
1918 init_channel = ath_get_curchannel(sc, hw);
1919
1920 /* Reset SERDES registers */
1921 ath9k_hw_configpcipowersave(sc->sc_ah, 0);
1922
1923 /*
1924 * The basic interface to setting the hardware in a good
1925 * state is ``reset''. On return the hardware is known to
1926 * be powered up and with interrupts disabled. This must
1927 * be followed by initialization of the appropriate bits
1928 * and then setup of the interrupt mask.
1929 */
1930 spin_lock_bh(&sc->sc_resetlock);
1931 r = ath9k_hw_reset(sc->sc_ah, init_channel, false);
1932 if (r) {
1933 DPRINTF(sc, ATH_DBG_FATAL,
1934 "Unable to reset hardware; reset status %d "
1935 "(freq %u MHz)\n", r,
1936 curchan->center_freq);
1937 spin_unlock_bh(&sc->sc_resetlock);
1938 goto mutex_unlock;
1939 }
1940 spin_unlock_bh(&sc->sc_resetlock);
1941
1942 /*
1943 * This is needed only to setup initial state
1944 * but it's best done after a reset.
1945 */
1946 ath_update_txpow(sc);
1947
1948 /*
1949 * Setup the hardware after reset:
1950 * The receive engine is set going.
1951 * Frame transmit is handled entirely
1952 * in the frame output path; there's nothing to do
1953 * here except setup the interrupt mask.
1954 */
1955 if (ath_startrecv(sc) != 0) {
1956 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
1957 r = -EIO;
1958 goto mutex_unlock;
1959 }
1960
1961 /* Setup our intr mask. */
1962 sc->imask = ATH9K_INT_RX | ATH9K_INT_TX
1963 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
1964 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
1965
1966 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
1967 sc->imask |= ATH9K_INT_GTT;
1968
1969 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
1970 sc->imask |= ATH9K_INT_CST;
1971
1972 ath_cache_conf_rate(sc, &hw->conf);
1973
1974 sc->sc_flags &= ~SC_OP_INVALID;
1975
1976 /* Disable BMISS interrupt when we're not associated */
1977 sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
1978 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
1979
1980 ieee80211_wake_queues(hw);
1981
1982 mutex_unlock:
1983 mutex_unlock(&sc->mutex);
1984
1985 return r;
1986 }
1987
1988 static int ath9k_tx(struct ieee80211_hw *hw,
1989 struct sk_buff *skb)
1990 {
1991 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1992 struct ath_wiphy *aphy = hw->priv;
1993 struct ath_softc *sc = aphy->sc;
1994 struct ath_tx_control txctl;
1995 int hdrlen, padsize;
1996
1997 if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
1998 printk(KERN_DEBUG "ath9k: %s: TX in unexpected wiphy state "
1999 "%d\n", wiphy_name(hw->wiphy), aphy->state);
2000 goto exit;
2001 }
2002
2003 if (sc->hw->conf.flags & IEEE80211_CONF_PS) {
2004 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2005 /*
2006 * mac80211 does not set PM field for normal data frames, so we
2007 * need to update that based on the current PS mode.
2008 */
2009 if (ieee80211_is_data(hdr->frame_control) &&
2010 !ieee80211_is_nullfunc(hdr->frame_control) &&
2011 !ieee80211_has_pm(hdr->frame_control)) {
2012 DPRINTF(sc, ATH_DBG_PS, "Add PM=1 for a TX frame "
2013 "while in PS mode\n");
2014 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
2015 }
2016 }
2017
2018 if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
2019 /*
2020 * We are using PS-Poll and mac80211 can request TX while in
2021 * power save mode. Need to wake up hardware for the TX to be
2022 * completed and if needed, also for RX of buffered frames.
2023 */
2024 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2025 ath9k_ps_wakeup(sc);
2026 ath9k_hw_setrxabort(sc->sc_ah, 0);
2027 if (ieee80211_is_pspoll(hdr->frame_control)) {
2028 DPRINTF(sc, ATH_DBG_PS, "Sending PS-Poll to pick a "
2029 "buffered frame\n");
2030 sc->sc_flags |= SC_OP_WAIT_FOR_PSPOLL_DATA;
2031 } else {
2032 DPRINTF(sc, ATH_DBG_PS, "Wake up to complete TX\n");
2033 sc->sc_flags |= SC_OP_WAIT_FOR_TX_ACK;
2034 }
2035 /*
2036 * The actual restore operation will happen only after
2037 * the sc_flags bit is cleared. We are just dropping
2038 * the ps_usecount here.
2039 */
2040 ath9k_ps_restore(sc);
2041 }
2042
2043 memset(&txctl, 0, sizeof(struct ath_tx_control));
2044
2045 /*
2046 * As a temporary workaround, assign seq# here; this will likely need
2047 * to be cleaned up to work better with Beacon transmission and virtual
2048 * BSSes.
2049 */
2050 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2051 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2052 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2053 sc->tx.seq_no += 0x10;
2054 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2055 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
2056 }
2057
2058 /* Add the padding after the header if this is not already done */
2059 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2060 if (hdrlen & 3) {
2061 padsize = hdrlen % 4;
2062 if (skb_headroom(skb) < padsize)
2063 return -1;
2064 skb_push(skb, padsize);
2065 memmove(skb->data, skb->data + padsize, hdrlen);
2066 }
2067
2068 /* Check if a tx queue is available */
2069
2070 txctl.txq = ath_test_get_txq(sc, skb);
2071 if (!txctl.txq)
2072 goto exit;
2073
2074 DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
2075
2076 if (ath_tx_start(hw, skb, &txctl) != 0) {
2077 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
2078 goto exit;
2079 }
2080
2081 return 0;
2082 exit:
2083 dev_kfree_skb_any(skb);
2084 return 0;
2085 }
2086
2087 static void ath9k_stop(struct ieee80211_hw *hw)
2088 {
2089 struct ath_wiphy *aphy = hw->priv;
2090 struct ath_softc *sc = aphy->sc;
2091
2092 aphy->state = ATH_WIPHY_INACTIVE;
2093
2094 if (sc->sc_flags & SC_OP_INVALID) {
2095 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
2096 return;
2097 }
2098
2099 mutex_lock(&sc->mutex);
2100
2101 ieee80211_stop_queues(hw);
2102
2103 if (ath9k_wiphy_started(sc)) {
2104 mutex_unlock(&sc->mutex);
2105 return; /* another wiphy still in use */
2106 }
2107
2108 /* make sure h/w will not generate any interrupt
2109 * before setting the invalid flag. */
2110 ath9k_hw_set_interrupts(sc->sc_ah, 0);
2111
2112 if (!(sc->sc_flags & SC_OP_INVALID)) {
2113 ath_drain_all_txq(sc, false);
2114 ath_stoprecv(sc);
2115 ath9k_hw_phy_disable(sc->sc_ah);
2116 } else
2117 sc->rx.rxlink = NULL;
2118
2119 wiphy_rfkill_stop_polling(sc->hw->wiphy);
2120
2121 /* disable HAL and put h/w to sleep */
2122 ath9k_hw_disable(sc->sc_ah);
2123 ath9k_hw_configpcipowersave(sc->sc_ah, 1);
2124
2125 sc->sc_flags |= SC_OP_INVALID;
2126
2127 mutex_unlock(&sc->mutex);
2128
2129 DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
2130 }
2131
2132 static int ath9k_add_interface(struct ieee80211_hw *hw,
2133 struct ieee80211_if_init_conf *conf)
2134 {
2135 struct ath_wiphy *aphy = hw->priv;
2136 struct ath_softc *sc = aphy->sc;
2137 struct ath_vif *avp = (void *)conf->vif->drv_priv;
2138 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2139 int ret = 0;
2140
2141 mutex_lock(&sc->mutex);
2142
2143 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
2144 sc->nvifs > 0) {
2145 ret = -ENOBUFS;
2146 goto out;
2147 }
2148
2149 switch (conf->type) {
2150 case NL80211_IFTYPE_STATION:
2151 ic_opmode = NL80211_IFTYPE_STATION;
2152 break;
2153 case NL80211_IFTYPE_ADHOC:
2154 case NL80211_IFTYPE_AP:
2155 case NL80211_IFTYPE_MESH_POINT:
2156 if (sc->nbcnvifs >= ATH_BCBUF) {
2157 ret = -ENOBUFS;
2158 goto out;
2159 }
2160 ic_opmode = conf->type;
2161 break;
2162 default:
2163 DPRINTF(sc, ATH_DBG_FATAL,
2164 "Interface type %d not yet supported\n", conf->type);
2165 ret = -EOPNOTSUPP;
2166 goto out;
2167 }
2168
2169 DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VIF of type: %d\n", ic_opmode);
2170
2171 /* Set the VIF opmode */
2172 avp->av_opmode = ic_opmode;
2173 avp->av_bslot = -1;
2174
2175 sc->nvifs++;
2176
2177 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
2178 ath9k_set_bssid_mask(hw);
2179
2180 if (sc->nvifs > 1)
2181 goto out; /* skip global settings for secondary vif */
2182
2183 if (ic_opmode == NL80211_IFTYPE_AP) {
2184 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2185 sc->sc_flags |= SC_OP_TSF_RESET;
2186 }
2187
2188 /* Set the device opmode */
2189 sc->sc_ah->opmode = ic_opmode;
2190
2191 /*
2192 * Enable MIB interrupts when there are hardware phy counters.
2193 * Note we only do this (at the moment) for station mode.
2194 */
2195 if ((conf->type == NL80211_IFTYPE_STATION) ||
2196 (conf->type == NL80211_IFTYPE_ADHOC) ||
2197 (conf->type == NL80211_IFTYPE_MESH_POINT)) {
2198 if (ath9k_hw_phycounters(sc->sc_ah))
2199 sc->imask |= ATH9K_INT_MIB;
2200 sc->imask |= ATH9K_INT_TSFOOR;
2201 }
2202
2203 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
2204
2205 if (conf->type == NL80211_IFTYPE_AP ||
2206 conf->type == NL80211_IFTYPE_ADHOC ||
2207 conf->type == NL80211_IFTYPE_MONITOR)
2208 ath_start_ani(sc);
2209
2210 out:
2211 mutex_unlock(&sc->mutex);
2212 return ret;
2213 }
2214
2215 static void ath9k_remove_interface(struct ieee80211_hw *hw,
2216 struct ieee80211_if_init_conf *conf)
2217 {
2218 struct ath_wiphy *aphy = hw->priv;
2219 struct ath_softc *sc = aphy->sc;
2220 struct ath_vif *avp = (void *)conf->vif->drv_priv;
2221 int i;
2222
2223 DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
2224
2225 mutex_lock(&sc->mutex);
2226
2227 /* Stop ANI */
2228 del_timer_sync(&sc->ani.timer);
2229
2230 /* Reclaim beacon resources */
2231 if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
2232 (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
2233 (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
2234 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2235 ath_beacon_return(sc, avp);
2236 }
2237
2238 sc->sc_flags &= ~SC_OP_BEACONS;
2239
2240 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2241 if (sc->beacon.bslot[i] == conf->vif) {
2242 printk(KERN_DEBUG "%s: vif had allocated beacon "
2243 "slot\n", __func__);
2244 sc->beacon.bslot[i] = NULL;
2245 sc->beacon.bslot_aphy[i] = NULL;
2246 }
2247 }
2248
2249 sc->nvifs--;
2250
2251 mutex_unlock(&sc->mutex);
2252 }
2253
2254 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2255 {
2256 struct ath_wiphy *aphy = hw->priv;
2257 struct ath_softc *sc = aphy->sc;
2258 struct ieee80211_conf *conf = &hw->conf;
2259 struct ath_hw *ah = sc->sc_ah;
2260
2261 mutex_lock(&sc->mutex);
2262
2263 if (changed & IEEE80211_CONF_CHANGE_PS) {
2264 if (conf->flags & IEEE80211_CONF_PS) {
2265 if (!(ah->caps.hw_caps &
2266 ATH9K_HW_CAP_AUTOSLEEP)) {
2267 if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
2268 sc->imask |= ATH9K_INT_TIM_TIMER;
2269 ath9k_hw_set_interrupts(sc->sc_ah,
2270 sc->imask);
2271 }
2272 ath9k_hw_setrxabort(sc->sc_ah, 1);
2273 }
2274 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
2275 } else {
2276 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
2277 if (!(ah->caps.hw_caps &
2278 ATH9K_HW_CAP_AUTOSLEEP)) {
2279 ath9k_hw_setrxabort(sc->sc_ah, 0);
2280 sc->sc_flags &= ~(SC_OP_WAIT_FOR_BEACON |
2281 SC_OP_WAIT_FOR_CAB |
2282 SC_OP_WAIT_FOR_PSPOLL_DATA |
2283 SC_OP_WAIT_FOR_TX_ACK);
2284 if (sc->imask & ATH9K_INT_TIM_TIMER) {
2285 sc->imask &= ~ATH9K_INT_TIM_TIMER;
2286 ath9k_hw_set_interrupts(sc->sc_ah,
2287 sc->imask);
2288 }
2289 }
2290 }
2291 }
2292
2293 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2294 struct ieee80211_channel *curchan = hw->conf.channel;
2295 int pos = curchan->hw_value;
2296
2297 aphy->chan_idx = pos;
2298 aphy->chan_is_ht = conf_is_ht(conf);
2299
2300 if (aphy->state == ATH_WIPHY_SCAN ||
2301 aphy->state == ATH_WIPHY_ACTIVE)
2302 ath9k_wiphy_pause_all_forced(sc, aphy);
2303 else {
2304 /*
2305 * Do not change operational channel based on a paused
2306 * wiphy changes.
2307 */
2308 goto skip_chan_change;
2309 }
2310
2311 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2312 curchan->center_freq);
2313
2314 /* XXX: remove me eventualy */
2315 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
2316
2317 ath_update_chainmask(sc, conf_is_ht(conf));
2318
2319 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
2320 DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
2321 mutex_unlock(&sc->mutex);
2322 return -EINVAL;
2323 }
2324 }
2325
2326 skip_chan_change:
2327 if (changed & IEEE80211_CONF_CHANGE_POWER)
2328 sc->config.txpowlimit = 2 * conf->power_level;
2329
2330 mutex_unlock(&sc->mutex);
2331
2332 return 0;
2333 }
2334
2335 #define SUPPORTED_FILTERS \
2336 (FIF_PROMISC_IN_BSS | \
2337 FIF_ALLMULTI | \
2338 FIF_CONTROL | \
2339 FIF_OTHER_BSS | \
2340 FIF_BCN_PRBRESP_PROMISC | \
2341 FIF_FCSFAIL)
2342
2343 /* FIXME: sc->sc_full_reset ? */
2344 static void ath9k_configure_filter(struct ieee80211_hw *hw,
2345 unsigned int changed_flags,
2346 unsigned int *total_flags,
2347 int mc_count,
2348 struct dev_mc_list *mclist)
2349 {
2350 struct ath_wiphy *aphy = hw->priv;
2351 struct ath_softc *sc = aphy->sc;
2352 u32 rfilt;
2353
2354 changed_flags &= SUPPORTED_FILTERS;
2355 *total_flags &= SUPPORTED_FILTERS;
2356
2357 sc->rx.rxfilter = *total_flags;
2358 ath9k_ps_wakeup(sc);
2359 rfilt = ath_calcrxfilter(sc);
2360 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
2361 ath9k_ps_restore(sc);
2362
2363 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
2364 }
2365
2366 static void ath9k_sta_notify(struct ieee80211_hw *hw,
2367 struct ieee80211_vif *vif,
2368 enum sta_notify_cmd cmd,
2369 struct ieee80211_sta *sta)
2370 {
2371 struct ath_wiphy *aphy = hw->priv;
2372 struct ath_softc *sc = aphy->sc;
2373
2374 switch (cmd) {
2375 case STA_NOTIFY_ADD:
2376 ath_node_attach(sc, sta);
2377 break;
2378 case STA_NOTIFY_REMOVE:
2379 ath_node_detach(sc, sta);
2380 break;
2381 default:
2382 break;
2383 }
2384 }
2385
2386 static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
2387 const struct ieee80211_tx_queue_params *params)
2388 {
2389 struct ath_wiphy *aphy = hw->priv;
2390 struct ath_softc *sc = aphy->sc;
2391 struct ath9k_tx_queue_info qi;
2392 int ret = 0, qnum;
2393
2394 if (queue >= WME_NUM_AC)
2395 return 0;
2396
2397 mutex_lock(&sc->mutex);
2398
2399 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
2400
2401 qi.tqi_aifs = params->aifs;
2402 qi.tqi_cwmin = params->cw_min;
2403 qi.tqi_cwmax = params->cw_max;
2404 qi.tqi_burstTime = params->txop;
2405 qnum = ath_get_hal_qnum(queue, sc);
2406
2407 DPRINTF(sc, ATH_DBG_CONFIG,
2408 "Configure tx [queue/halq] [%d/%d], "
2409 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2410 queue, qnum, params->aifs, params->cw_min,
2411 params->cw_max, params->txop);
2412
2413 ret = ath_txq_update(sc, qnum, &qi);
2414 if (ret)
2415 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
2416
2417 mutex_unlock(&sc->mutex);
2418
2419 return ret;
2420 }
2421
2422 static int ath9k_set_key(struct ieee80211_hw *hw,
2423 enum set_key_cmd cmd,
2424 struct ieee80211_vif *vif,
2425 struct ieee80211_sta *sta,
2426 struct ieee80211_key_conf *key)
2427 {
2428 struct ath_wiphy *aphy = hw->priv;
2429 struct ath_softc *sc = aphy->sc;
2430 int ret = 0;
2431
2432 if (modparam_nohwcrypt)
2433 return -ENOSPC;
2434
2435 mutex_lock(&sc->mutex);
2436 ath9k_ps_wakeup(sc);
2437 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW Key\n");
2438
2439 switch (cmd) {
2440 case SET_KEY:
2441 ret = ath_key_config(sc, vif, sta, key);
2442 if (ret >= 0) {
2443 key->hw_key_idx = ret;
2444 /* push IV and Michael MIC generation to stack */
2445 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2446 if (key->alg == ALG_TKIP)
2447 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
2448 if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2449 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
2450 ret = 0;
2451 }
2452 break;
2453 case DISABLE_KEY:
2454 ath_key_delete(sc, key);
2455 break;
2456 default:
2457 ret = -EINVAL;
2458 }
2459
2460 ath9k_ps_restore(sc);
2461 mutex_unlock(&sc->mutex);
2462
2463 return ret;
2464 }
2465
2466 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2467 struct ieee80211_vif *vif,
2468 struct ieee80211_bss_conf *bss_conf,
2469 u32 changed)
2470 {
2471 struct ath_wiphy *aphy = hw->priv;
2472 struct ath_softc *sc = aphy->sc;
2473 struct ath_hw *ah = sc->sc_ah;
2474 struct ath_vif *avp = (void *)vif->drv_priv;
2475 u32 rfilt = 0;
2476 int error, i;
2477
2478 mutex_lock(&sc->mutex);
2479
2480 /*
2481 * TODO: Need to decide which hw opmode to use for
2482 * multi-interface cases
2483 * XXX: This belongs into add_interface!
2484 */
2485 if (vif->type == NL80211_IFTYPE_AP &&
2486 ah->opmode != NL80211_IFTYPE_AP) {
2487 ah->opmode = NL80211_IFTYPE_STATION;
2488 ath9k_hw_setopmode(ah);
2489 memcpy(sc->curbssid, sc->sc_ah->macaddr, ETH_ALEN);
2490 sc->curaid = 0;
2491 ath9k_hw_write_associd(sc);
2492 /* Request full reset to get hw opmode changed properly */
2493 sc->sc_flags |= SC_OP_FULL_RESET;
2494 }
2495
2496 if ((changed & BSS_CHANGED_BSSID) &&
2497 !is_zero_ether_addr(bss_conf->bssid)) {
2498 switch (vif->type) {
2499 case NL80211_IFTYPE_STATION:
2500 case NL80211_IFTYPE_ADHOC:
2501 case NL80211_IFTYPE_MESH_POINT:
2502 /* Set BSSID */
2503 memcpy(sc->curbssid, bss_conf->bssid, ETH_ALEN);
2504 memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
2505 sc->curaid = 0;
2506 ath9k_hw_write_associd(sc);
2507
2508 /* Set aggregation protection mode parameters */
2509 sc->config.ath_aggr_prot = 0;
2510
2511 DPRINTF(sc, ATH_DBG_CONFIG,
2512 "RX filter 0x%x bssid %pM aid 0x%x\n",
2513 rfilt, sc->curbssid, sc->curaid);
2514
2515 /* need to reconfigure the beacon */
2516 sc->sc_flags &= ~SC_OP_BEACONS ;
2517
2518 break;
2519 default:
2520 break;
2521 }
2522 }
2523
2524 if ((vif->type == NL80211_IFTYPE_ADHOC) ||
2525 (vif->type == NL80211_IFTYPE_AP) ||
2526 (vif->type == NL80211_IFTYPE_MESH_POINT)) {
2527 if ((changed & BSS_CHANGED_BEACON) ||
2528 (changed & BSS_CHANGED_BEACON_ENABLED &&
2529 bss_conf->enable_beacon)) {
2530 /*
2531 * Allocate and setup the beacon frame.
2532 *
2533 * Stop any previous beacon DMA. This may be
2534 * necessary, for example, when an ibss merge
2535 * causes reconfiguration; we may be called
2536 * with beacon transmission active.
2537 */
2538 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2539
2540 error = ath_beacon_alloc(aphy, vif);
2541 if (!error)
2542 ath_beacon_config(sc, vif);
2543 }
2544 }
2545
2546 /* Check for WLAN_CAPABILITY_PRIVACY ? */
2547 if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
2548 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2549 if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2550 ath9k_hw_keysetmac(sc->sc_ah,
2551 (u16)i,
2552 sc->curbssid);
2553 }
2554
2555 /* Only legacy IBSS for now */
2556 if (vif->type == NL80211_IFTYPE_ADHOC)
2557 ath_update_chainmask(sc, 0);
2558
2559 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
2560 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
2561 bss_conf->use_short_preamble);
2562 if (bss_conf->use_short_preamble)
2563 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2564 else
2565 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2566 }
2567
2568 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
2569 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
2570 bss_conf->use_cts_prot);
2571 if (bss_conf->use_cts_prot &&
2572 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2573 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2574 else
2575 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2576 }
2577
2578 if (changed & BSS_CHANGED_ASSOC) {
2579 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
2580 bss_conf->assoc);
2581 ath9k_bss_assoc_info(sc, vif, bss_conf);
2582 }
2583
2584 /*
2585 * The HW TSF has to be reset when the beacon interval changes.
2586 * We set the flag here, and ath_beacon_config_ap() would take this
2587 * into account when it gets called through the subsequent
2588 * config_interface() call - with IFCC_BEACON in the changed field.
2589 */
2590
2591 if (changed & BSS_CHANGED_BEACON_INT) {
2592 sc->sc_flags |= SC_OP_TSF_RESET;
2593 sc->beacon_interval = bss_conf->beacon_int;
2594 }
2595
2596 mutex_unlock(&sc->mutex);
2597 }
2598
2599 static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2600 {
2601 u64 tsf;
2602 struct ath_wiphy *aphy = hw->priv;
2603 struct ath_softc *sc = aphy->sc;
2604
2605 mutex_lock(&sc->mutex);
2606 tsf = ath9k_hw_gettsf64(sc->sc_ah);
2607 mutex_unlock(&sc->mutex);
2608
2609 return tsf;
2610 }
2611
2612 static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2613 {
2614 struct ath_wiphy *aphy = hw->priv;
2615 struct ath_softc *sc = aphy->sc;
2616
2617 mutex_lock(&sc->mutex);
2618 ath9k_hw_settsf64(sc->sc_ah, tsf);
2619 mutex_unlock(&sc->mutex);
2620 }
2621
2622 static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2623 {
2624 struct ath_wiphy *aphy = hw->priv;
2625 struct ath_softc *sc = aphy->sc;
2626
2627 mutex_lock(&sc->mutex);
2628 ath9k_hw_reset_tsf(sc->sc_ah);
2629 mutex_unlock(&sc->mutex);
2630 }
2631
2632 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2633 enum ieee80211_ampdu_mlme_action action,
2634 struct ieee80211_sta *sta,
2635 u16 tid, u16 *ssn)
2636 {
2637 struct ath_wiphy *aphy = hw->priv;
2638 struct ath_softc *sc = aphy->sc;
2639 int ret = 0;
2640
2641 switch (action) {
2642 case IEEE80211_AMPDU_RX_START:
2643 if (!(sc->sc_flags & SC_OP_RXAGGR))
2644 ret = -ENOTSUPP;
2645 break;
2646 case IEEE80211_AMPDU_RX_STOP:
2647 break;
2648 case IEEE80211_AMPDU_TX_START:
2649 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
2650 if (ret < 0)
2651 DPRINTF(sc, ATH_DBG_FATAL,
2652 "Unable to start TX aggregation\n");
2653 else
2654 ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2655 break;
2656 case IEEE80211_AMPDU_TX_STOP:
2657 ret = ath_tx_aggr_stop(sc, sta, tid);
2658 if (ret < 0)
2659 DPRINTF(sc, ATH_DBG_FATAL,
2660 "Unable to stop TX aggregation\n");
2661
2662 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2663 break;
2664 case IEEE80211_AMPDU_TX_OPERATIONAL:
2665 ath_tx_aggr_resume(sc, sta, tid);
2666 break;
2667 default:
2668 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
2669 }
2670
2671 return ret;
2672 }
2673
2674 static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
2675 {
2676 struct ath_wiphy *aphy = hw->priv;
2677 struct ath_softc *sc = aphy->sc;
2678
2679 if (ath9k_wiphy_scanning(sc)) {
2680 printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the "
2681 "same time\n");
2682 /*
2683 * Do not allow the concurrent scanning state for now. This
2684 * could be improved with scanning control moved into ath9k.
2685 */
2686 return;
2687 }
2688
2689 aphy->state = ATH_WIPHY_SCAN;
2690 ath9k_wiphy_pause_all_forced(sc, aphy);
2691
2692 spin_lock_bh(&sc->ani_lock);
2693 sc->sc_flags |= SC_OP_SCANNING;
2694 spin_unlock_bh(&sc->ani_lock);
2695 }
2696
2697 static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
2698 {
2699 struct ath_wiphy *aphy = hw->priv;
2700 struct ath_softc *sc = aphy->sc;
2701
2702 spin_lock_bh(&sc->ani_lock);
2703 aphy->state = ATH_WIPHY_ACTIVE;
2704 sc->sc_flags &= ~SC_OP_SCANNING;
2705 sc->sc_flags |= SC_OP_FULL_RESET;
2706 spin_unlock_bh(&sc->ani_lock);
2707 }
2708
2709 struct ieee80211_ops ath9k_ops = {
2710 .tx = ath9k_tx,
2711 .start = ath9k_start,
2712 .stop = ath9k_stop,
2713 .add_interface = ath9k_add_interface,
2714 .remove_interface = ath9k_remove_interface,
2715 .config = ath9k_config,
2716 .configure_filter = ath9k_configure_filter,
2717 .sta_notify = ath9k_sta_notify,
2718 .conf_tx = ath9k_conf_tx,
2719 .bss_info_changed = ath9k_bss_info_changed,
2720 .set_key = ath9k_set_key,
2721 .get_tsf = ath9k_get_tsf,
2722 .set_tsf = ath9k_set_tsf,
2723 .reset_tsf = ath9k_reset_tsf,
2724 .ampdu_action = ath9k_ampdu_action,
2725 .sw_scan_start = ath9k_sw_scan_start,
2726 .sw_scan_complete = ath9k_sw_scan_complete,
2727 .rfkill_poll = ath9k_rfkill_poll_state,
2728 };
2729
2730 static struct {
2731 u32 version;
2732 const char * name;
2733 } ath_mac_bb_names[] = {
2734 { AR_SREV_VERSION_5416_PCI, "5416" },
2735 { AR_SREV_VERSION_5416_PCIE, "5418" },
2736 { AR_SREV_VERSION_9100, "9100" },
2737 { AR_SREV_VERSION_9160, "9160" },
2738 { AR_SREV_VERSION_9280, "9280" },
2739 { AR_SREV_VERSION_9285, "9285" }
2740 };
2741
2742 static struct {
2743 u16 version;
2744 const char * name;
2745 } ath_rf_names[] = {
2746 { 0, "5133" },
2747 { AR_RAD5133_SREV_MAJOR, "5133" },
2748 { AR_RAD5122_SREV_MAJOR, "5122" },
2749 { AR_RAD2133_SREV_MAJOR, "2133" },
2750 { AR_RAD2122_SREV_MAJOR, "2122" }
2751 };
2752
2753 /*
2754 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2755 */
2756 const char *
2757 ath_mac_bb_name(u32 mac_bb_version)
2758 {
2759 int i;
2760
2761 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2762 if (ath_mac_bb_names[i].version == mac_bb_version) {
2763 return ath_mac_bb_names[i].name;
2764 }
2765 }
2766
2767 return "????";
2768 }
2769
2770 /*
2771 * Return the RF name. "????" is returned if the RF is unknown.
2772 */
2773 const char *
2774 ath_rf_name(u16 rf_version)
2775 {
2776 int i;
2777
2778 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2779 if (ath_rf_names[i].version == rf_version) {
2780 return ath_rf_names[i].name;
2781 }
2782 }
2783
2784 return "????";
2785 }
2786
2787 static int __init ath9k_init(void)
2788 {
2789 int error;
2790
2791 /* Register rate control algorithm */
2792 error = ath_rate_control_register();
2793 if (error != 0) {
2794 printk(KERN_ERR
2795 "ath9k: Unable to register rate control "
2796 "algorithm: %d\n",
2797 error);
2798 goto err_out;
2799 }
2800
2801 error = ath9k_debug_create_root();
2802 if (error) {
2803 printk(KERN_ERR
2804 "ath9k: Unable to create debugfs root: %d\n",
2805 error);
2806 goto err_rate_unregister;
2807 }
2808
2809 error = ath_pci_init();
2810 if (error < 0) {
2811 printk(KERN_ERR
2812 "ath9k: No PCI devices found, driver not installed.\n");
2813 error = -ENODEV;
2814 goto err_remove_root;
2815 }
2816
2817 error = ath_ahb_init();
2818 if (error < 0) {
2819 error = -ENODEV;
2820 goto err_pci_exit;
2821 }
2822
2823 return 0;
2824
2825 err_pci_exit:
2826 ath_pci_exit();
2827
2828 err_remove_root:
2829 ath9k_debug_remove_root();
2830 err_rate_unregister:
2831 ath_rate_control_unregister();
2832 err_out:
2833 return error;
2834 }
2835 module_init(ath9k_init);
2836
2837 static void __exit ath9k_exit(void)
2838 {
2839 ath_ahb_exit();
2840 ath_pci_exit();
2841 ath9k_debug_remove_root();
2842 ath_rate_control_unregister();
2843 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
2844 }
2845 module_exit(ath9k_exit);
Linux kernel - Deliverables
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