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Merge tag 'parisc-misc' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/parisc-2.6
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / main.c
1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/nl80211.h>
18 #include <linux/delay.h>
19 #include "ath9k.h"
20 #include "btcoex.h"
21
22 static u8 parse_mpdudensity(u8 mpdudensity)
23 {
24 /*
25 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
26 * 0 for no restriction
27 * 1 for 1/4 us
28 * 2 for 1/2 us
29 * 3 for 1 us
30 * 4 for 2 us
31 * 5 for 4 us
32 * 6 for 8 us
33 * 7 for 16 us
34 */
35 switch (mpdudensity) {
36 case 0:
37 return 0;
38 case 1:
39 case 2:
40 case 3:
41 /* Our lower layer calculations limit our precision to
42 1 microsecond */
43 return 1;
44 case 4:
45 return 2;
46 case 5:
47 return 4;
48 case 6:
49 return 8;
50 case 7:
51 return 16;
52 default:
53 return 0;
54 }
55 }
56
57 static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq)
58 {
59 bool pending = false;
60
61 spin_lock_bh(&txq->axq_lock);
62
63 if (txq->axq_depth || !list_empty(&txq->axq_acq))
64 pending = true;
65
66 spin_unlock_bh(&txq->axq_lock);
67 return pending;
68 }
69
70 static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
71 {
72 unsigned long flags;
73 bool ret;
74
75 spin_lock_irqsave(&sc->sc_pm_lock, flags);
76 ret = ath9k_hw_setpower(sc->sc_ah, mode);
77 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
78
79 return ret;
80 }
81
82 void ath9k_ps_wakeup(struct ath_softc *sc)
83 {
84 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
85 unsigned long flags;
86 enum ath9k_power_mode power_mode;
87
88 spin_lock_irqsave(&sc->sc_pm_lock, flags);
89 if (++sc->ps_usecount != 1)
90 goto unlock;
91
92 power_mode = sc->sc_ah->power_mode;
93 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
94
95 /*
96 * While the hardware is asleep, the cycle counters contain no
97 * useful data. Better clear them now so that they don't mess up
98 * survey data results.
99 */
100 if (power_mode != ATH9K_PM_AWAKE) {
101 spin_lock(&common->cc_lock);
102 ath_hw_cycle_counters_update(common);
103 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
104 spin_unlock(&common->cc_lock);
105 }
106
107 unlock:
108 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
109 }
110
111 void ath9k_ps_restore(struct ath_softc *sc)
112 {
113 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
114 enum ath9k_power_mode mode;
115 unsigned long flags;
116 bool reset;
117
118 spin_lock_irqsave(&sc->sc_pm_lock, flags);
119 if (--sc->ps_usecount != 0)
120 goto unlock;
121
122 if (sc->ps_idle) {
123 ath9k_hw_setrxabort(sc->sc_ah, 1);
124 ath9k_hw_stopdmarecv(sc->sc_ah, &reset);
125 mode = ATH9K_PM_FULL_SLEEP;
126 } else if (sc->ps_enabled &&
127 !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
128 PS_WAIT_FOR_CAB |
129 PS_WAIT_FOR_PSPOLL_DATA |
130 PS_WAIT_FOR_TX_ACK))) {
131 mode = ATH9K_PM_NETWORK_SLEEP;
132 } else {
133 goto unlock;
134 }
135
136 spin_lock(&common->cc_lock);
137 ath_hw_cycle_counters_update(common);
138 spin_unlock(&common->cc_lock);
139
140 ath9k_hw_setpower(sc->sc_ah, mode);
141
142 unlock:
143 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
144 }
145
146 void ath_start_ani(struct ath_common *common)
147 {
148 struct ath_hw *ah = common->ah;
149 unsigned long timestamp = jiffies_to_msecs(jiffies);
150 struct ath_softc *sc = (struct ath_softc *) common->priv;
151
152 if (!(sc->sc_flags & SC_OP_ANI_RUN))
153 return;
154
155 if (sc->sc_flags & SC_OP_OFFCHANNEL)
156 return;
157
158 common->ani.longcal_timer = timestamp;
159 common->ani.shortcal_timer = timestamp;
160 common->ani.checkani_timer = timestamp;
161
162 mod_timer(&common->ani.timer,
163 jiffies +
164 msecs_to_jiffies((u32)ah->config.ani_poll_interval));
165 }
166
167 static void ath_update_survey_nf(struct ath_softc *sc, int channel)
168 {
169 struct ath_hw *ah = sc->sc_ah;
170 struct ath9k_channel *chan = &ah->channels[channel];
171 struct survey_info *survey = &sc->survey[channel];
172
173 if (chan->noisefloor) {
174 survey->filled |= SURVEY_INFO_NOISE_DBM;
175 survey->noise = ath9k_hw_getchan_noise(ah, chan);
176 }
177 }
178
179 /*
180 * Updates the survey statistics and returns the busy time since last
181 * update in %, if the measurement duration was long enough for the
182 * result to be useful, -1 otherwise.
183 */
184 static int ath_update_survey_stats(struct ath_softc *sc)
185 {
186 struct ath_hw *ah = sc->sc_ah;
187 struct ath_common *common = ath9k_hw_common(ah);
188 int pos = ah->curchan - &ah->channels[0];
189 struct survey_info *survey = &sc->survey[pos];
190 struct ath_cycle_counters *cc = &common->cc_survey;
191 unsigned int div = common->clockrate * 1000;
192 int ret = 0;
193
194 if (!ah->curchan)
195 return -1;
196
197 if (ah->power_mode == ATH9K_PM_AWAKE)
198 ath_hw_cycle_counters_update(common);
199
200 if (cc->cycles > 0) {
201 survey->filled |= SURVEY_INFO_CHANNEL_TIME |
202 SURVEY_INFO_CHANNEL_TIME_BUSY |
203 SURVEY_INFO_CHANNEL_TIME_RX |
204 SURVEY_INFO_CHANNEL_TIME_TX;
205 survey->channel_time += cc->cycles / div;
206 survey->channel_time_busy += cc->rx_busy / div;
207 survey->channel_time_rx += cc->rx_frame / div;
208 survey->channel_time_tx += cc->tx_frame / div;
209 }
210
211 if (cc->cycles < div)
212 return -1;
213
214 if (cc->cycles > 0)
215 ret = cc->rx_busy * 100 / cc->cycles;
216
217 memset(cc, 0, sizeof(*cc));
218
219 ath_update_survey_nf(sc, pos);
220
221 return ret;
222 }
223
224 static void __ath_cancel_work(struct ath_softc *sc)
225 {
226 cancel_work_sync(&sc->paprd_work);
227 cancel_work_sync(&sc->hw_check_work);
228 cancel_delayed_work_sync(&sc->tx_complete_work);
229 cancel_delayed_work_sync(&sc->hw_pll_work);
230 }
231
232 static void ath_cancel_work(struct ath_softc *sc)
233 {
234 __ath_cancel_work(sc);
235 cancel_work_sync(&sc->hw_reset_work);
236 }
237
238 static bool ath_prepare_reset(struct ath_softc *sc, bool retry_tx, bool flush)
239 {
240 struct ath_hw *ah = sc->sc_ah;
241 struct ath_common *common = ath9k_hw_common(ah);
242 bool ret = true;
243
244 ieee80211_stop_queues(sc->hw);
245
246 sc->hw_busy_count = 0;
247 del_timer_sync(&common->ani.timer);
248 del_timer_sync(&sc->rx_poll_timer);
249
250 ath9k_debug_samp_bb_mac(sc);
251 ath9k_hw_disable_interrupts(ah);
252
253 if (!ath_stoprecv(sc))
254 ret = false;
255
256 if (!ath_drain_all_txq(sc, retry_tx))
257 ret = false;
258
259 if (!flush) {
260 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
261 ath_rx_tasklet(sc, 1, true);
262 ath_rx_tasklet(sc, 1, false);
263 } else {
264 ath_flushrecv(sc);
265 }
266
267 return ret;
268 }
269
270 static bool ath_complete_reset(struct ath_softc *sc, bool start)
271 {
272 struct ath_hw *ah = sc->sc_ah;
273 struct ath_common *common = ath9k_hw_common(ah);
274
275 if (ath_startrecv(sc) != 0) {
276 ath_err(common, "Unable to restart recv logic\n");
277 return false;
278 }
279
280 ath9k_cmn_update_txpow(ah, sc->curtxpow,
281 sc->config.txpowlimit, &sc->curtxpow);
282 ath9k_hw_set_interrupts(ah);
283 ath9k_hw_enable_interrupts(ah);
284
285 if (!(sc->sc_flags & (SC_OP_OFFCHANNEL)) && start) {
286 if (sc->sc_flags & SC_OP_BEACONS)
287 ath_set_beacon(sc);
288
289 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
290 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/2);
291 ath_start_rx_poll(sc, 3);
292 if (!common->disable_ani)
293 ath_start_ani(common);
294 }
295
296 if ((ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) && sc->ant_rx != 3) {
297 struct ath_hw_antcomb_conf div_ant_conf;
298 u8 lna_conf;
299
300 ath9k_hw_antdiv_comb_conf_get(ah, &div_ant_conf);
301
302 if (sc->ant_rx == 1)
303 lna_conf = ATH_ANT_DIV_COMB_LNA1;
304 else
305 lna_conf = ATH_ANT_DIV_COMB_LNA2;
306 div_ant_conf.main_lna_conf = lna_conf;
307 div_ant_conf.alt_lna_conf = lna_conf;
308
309 ath9k_hw_antdiv_comb_conf_set(ah, &div_ant_conf);
310 }
311
312 ieee80211_wake_queues(sc->hw);
313
314 return true;
315 }
316
317 static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan,
318 bool retry_tx)
319 {
320 struct ath_hw *ah = sc->sc_ah;
321 struct ath_common *common = ath9k_hw_common(ah);
322 struct ath9k_hw_cal_data *caldata = NULL;
323 bool fastcc = true;
324 bool flush = false;
325 int r;
326
327 __ath_cancel_work(sc);
328
329 spin_lock_bh(&sc->sc_pcu_lock);
330
331 if (!(sc->sc_flags & SC_OP_OFFCHANNEL)) {
332 fastcc = false;
333 caldata = &sc->caldata;
334 }
335
336 if (!hchan) {
337 fastcc = false;
338 flush = true;
339 hchan = ah->curchan;
340 }
341
342 if (!ath_prepare_reset(sc, retry_tx, flush))
343 fastcc = false;
344
345 ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n",
346 hchan->channel, IS_CHAN_HT40(hchan), fastcc);
347
348 r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
349 if (r) {
350 ath_err(common,
351 "Unable to reset channel, reset status %d\n", r);
352 goto out;
353 }
354
355 if (!ath_complete_reset(sc, true))
356 r = -EIO;
357
358 out:
359 spin_unlock_bh(&sc->sc_pcu_lock);
360 return r;
361 }
362
363
364 /*
365 * Set/change channels. If the channel is really being changed, it's done
366 * by reseting the chip. To accomplish this we must first cleanup any pending
367 * DMA, then restart stuff.
368 */
369 static int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
370 struct ath9k_channel *hchan)
371 {
372 int r;
373
374 if (sc->sc_flags & SC_OP_INVALID)
375 return -EIO;
376
377 r = ath_reset_internal(sc, hchan, false);
378
379 return r;
380 }
381
382 static void ath_paprd_activate(struct ath_softc *sc)
383 {
384 struct ath_hw *ah = sc->sc_ah;
385 struct ath9k_hw_cal_data *caldata = ah->caldata;
386 int chain;
387
388 if (!caldata || !caldata->paprd_done)
389 return;
390
391 ath9k_ps_wakeup(sc);
392 ar9003_paprd_enable(ah, false);
393 for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
394 if (!(ah->txchainmask & BIT(chain)))
395 continue;
396
397 ar9003_paprd_populate_single_table(ah, caldata, chain);
398 }
399
400 ar9003_paprd_enable(ah, true);
401 ath9k_ps_restore(sc);
402 }
403
404 static bool ath_paprd_send_frame(struct ath_softc *sc, struct sk_buff *skb, int chain)
405 {
406 struct ieee80211_hw *hw = sc->hw;
407 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
408 struct ath_hw *ah = sc->sc_ah;
409 struct ath_common *common = ath9k_hw_common(ah);
410 struct ath_tx_control txctl;
411 int time_left;
412
413 memset(&txctl, 0, sizeof(txctl));
414 txctl.txq = sc->tx.txq_map[WME_AC_BE];
415
416 memset(tx_info, 0, sizeof(*tx_info));
417 tx_info->band = hw->conf.channel->band;
418 tx_info->flags |= IEEE80211_TX_CTL_NO_ACK;
419 tx_info->control.rates[0].idx = 0;
420 tx_info->control.rates[0].count = 1;
421 tx_info->control.rates[0].flags = IEEE80211_TX_RC_MCS;
422 tx_info->control.rates[1].idx = -1;
423
424 init_completion(&sc->paprd_complete);
425 txctl.paprd = BIT(chain);
426
427 if (ath_tx_start(hw, skb, &txctl) != 0) {
428 ath_dbg(common, CALIBRATE, "PAPRD TX failed\n");
429 dev_kfree_skb_any(skb);
430 return false;
431 }
432
433 time_left = wait_for_completion_timeout(&sc->paprd_complete,
434 msecs_to_jiffies(ATH_PAPRD_TIMEOUT));
435
436 if (!time_left)
437 ath_dbg(common, CALIBRATE,
438 "Timeout waiting for paprd training on TX chain %d\n",
439 chain);
440
441 return !!time_left;
442 }
443
444 void ath_paprd_calibrate(struct work_struct *work)
445 {
446 struct ath_softc *sc = container_of(work, struct ath_softc, paprd_work);
447 struct ieee80211_hw *hw = sc->hw;
448 struct ath_hw *ah = sc->sc_ah;
449 struct ieee80211_hdr *hdr;
450 struct sk_buff *skb = NULL;
451 struct ath9k_hw_cal_data *caldata = ah->caldata;
452 struct ath_common *common = ath9k_hw_common(ah);
453 int ftype;
454 int chain_ok = 0;
455 int chain;
456 int len = 1800;
457
458 if (!caldata)
459 return;
460
461 ath9k_ps_wakeup(sc);
462
463 if (ar9003_paprd_init_table(ah) < 0)
464 goto fail_paprd;
465
466 skb = alloc_skb(len, GFP_KERNEL);
467 if (!skb)
468 goto fail_paprd;
469
470 skb_put(skb, len);
471 memset(skb->data, 0, len);
472 hdr = (struct ieee80211_hdr *)skb->data;
473 ftype = IEEE80211_FTYPE_DATA | IEEE80211_STYPE_NULLFUNC;
474 hdr->frame_control = cpu_to_le16(ftype);
475 hdr->duration_id = cpu_to_le16(10);
476 memcpy(hdr->addr1, hw->wiphy->perm_addr, ETH_ALEN);
477 memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN);
478 memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN);
479
480 for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
481 if (!(ah->txchainmask & BIT(chain)))
482 continue;
483
484 chain_ok = 0;
485
486 ath_dbg(common, CALIBRATE,
487 "Sending PAPRD frame for thermal measurement on chain %d\n",
488 chain);
489 if (!ath_paprd_send_frame(sc, skb, chain))
490 goto fail_paprd;
491
492 ar9003_paprd_setup_gain_table(ah, chain);
493
494 ath_dbg(common, CALIBRATE,
495 "Sending PAPRD training frame on chain %d\n", chain);
496 if (!ath_paprd_send_frame(sc, skb, chain))
497 goto fail_paprd;
498
499 if (!ar9003_paprd_is_done(ah)) {
500 ath_dbg(common, CALIBRATE,
501 "PAPRD not yet done on chain %d\n", chain);
502 break;
503 }
504
505 if (ar9003_paprd_create_curve(ah, caldata, chain)) {
506 ath_dbg(common, CALIBRATE,
507 "PAPRD create curve failed on chain %d\n",
508 chain);
509 break;
510 }
511
512 chain_ok = 1;
513 }
514 kfree_skb(skb);
515
516 if (chain_ok) {
517 caldata->paprd_done = true;
518 ath_paprd_activate(sc);
519 }
520
521 fail_paprd:
522 ath9k_ps_restore(sc);
523 }
524
525 /*
526 * This routine performs the periodic noise floor calibration function
527 * that is used to adjust and optimize the chip performance. This
528 * takes environmental changes (location, temperature) into account.
529 * When the task is complete, it reschedules itself depending on the
530 * appropriate interval that was calculated.
531 */
532 void ath_ani_calibrate(unsigned long data)
533 {
534 struct ath_softc *sc = (struct ath_softc *)data;
535 struct ath_hw *ah = sc->sc_ah;
536 struct ath_common *common = ath9k_hw_common(ah);
537 bool longcal = false;
538 bool shortcal = false;
539 bool aniflag = false;
540 unsigned int timestamp = jiffies_to_msecs(jiffies);
541 u32 cal_interval, short_cal_interval, long_cal_interval;
542 unsigned long flags;
543
544 if (ah->caldata && ah->caldata->nfcal_interference)
545 long_cal_interval = ATH_LONG_CALINTERVAL_INT;
546 else
547 long_cal_interval = ATH_LONG_CALINTERVAL;
548
549 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
550 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
551
552 /* Only calibrate if awake */
553 if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
554 goto set_timer;
555
556 ath9k_ps_wakeup(sc);
557
558 /* Long calibration runs independently of short calibration. */
559 if ((timestamp - common->ani.longcal_timer) >= long_cal_interval) {
560 longcal = true;
561 common->ani.longcal_timer = timestamp;
562 }
563
564 /* Short calibration applies only while caldone is false */
565 if (!common->ani.caldone) {
566 if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) {
567 shortcal = true;
568 common->ani.shortcal_timer = timestamp;
569 common->ani.resetcal_timer = timestamp;
570 }
571 } else {
572 if ((timestamp - common->ani.resetcal_timer) >=
573 ATH_RESTART_CALINTERVAL) {
574 common->ani.caldone = ath9k_hw_reset_calvalid(ah);
575 if (common->ani.caldone)
576 common->ani.resetcal_timer = timestamp;
577 }
578 }
579
580 /* Verify whether we must check ANI */
581 if (sc->sc_ah->config.enable_ani
582 && (timestamp - common->ani.checkani_timer) >=
583 ah->config.ani_poll_interval) {
584 aniflag = true;
585 common->ani.checkani_timer = timestamp;
586 }
587
588 /* Call ANI routine if necessary */
589 if (aniflag) {
590 spin_lock_irqsave(&common->cc_lock, flags);
591 ath9k_hw_ani_monitor(ah, ah->curchan);
592 ath_update_survey_stats(sc);
593 spin_unlock_irqrestore(&common->cc_lock, flags);
594 }
595
596 /* Perform calibration if necessary */
597 if (longcal || shortcal) {
598 common->ani.caldone =
599 ath9k_hw_calibrate(ah, ah->curchan,
600 ah->rxchainmask, longcal);
601 }
602
603 ath_dbg(common, ANI,
604 "Calibration @%lu finished: %s %s %s, caldone: %s\n",
605 jiffies,
606 longcal ? "long" : "", shortcal ? "short" : "",
607 aniflag ? "ani" : "", common->ani.caldone ? "true" : "false");
608
609 ath9k_ps_restore(sc);
610
611 set_timer:
612 /*
613 * Set timer interval based on previous results.
614 * The interval must be the shortest necessary to satisfy ANI,
615 * short calibration and long calibration.
616 */
617 ath9k_debug_samp_bb_mac(sc);
618 cal_interval = ATH_LONG_CALINTERVAL;
619 if (sc->sc_ah->config.enable_ani)
620 cal_interval = min(cal_interval,
621 (u32)ah->config.ani_poll_interval);
622 if (!common->ani.caldone)
623 cal_interval = min(cal_interval, (u32)short_cal_interval);
624
625 mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
626 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_PAPRD) && ah->caldata) {
627 if (!ah->caldata->paprd_done)
628 ieee80211_queue_work(sc->hw, &sc->paprd_work);
629 else if (!ah->paprd_table_write_done)
630 ath_paprd_activate(sc);
631 }
632 }
633
634 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
635 struct ieee80211_vif *vif)
636 {
637 struct ath_node *an;
638 an = (struct ath_node *)sta->drv_priv;
639
640 #ifdef CONFIG_ATH9K_DEBUGFS
641 spin_lock(&sc->nodes_lock);
642 list_add(&an->list, &sc->nodes);
643 spin_unlock(&sc->nodes_lock);
644 #endif
645 an->sta = sta;
646 an->vif = vif;
647
648 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
649 ath_tx_node_init(sc, an);
650 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
651 sta->ht_cap.ampdu_factor);
652 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
653 }
654 }
655
656 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
657 {
658 struct ath_node *an = (struct ath_node *)sta->drv_priv;
659
660 #ifdef CONFIG_ATH9K_DEBUGFS
661 spin_lock(&sc->nodes_lock);
662 list_del(&an->list);
663 spin_unlock(&sc->nodes_lock);
664 an->sta = NULL;
665 #endif
666
667 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
668 ath_tx_node_cleanup(sc, an);
669 }
670
671
672 void ath9k_tasklet(unsigned long data)
673 {
674 struct ath_softc *sc = (struct ath_softc *)data;
675 struct ath_hw *ah = sc->sc_ah;
676 struct ath_common *common = ath9k_hw_common(ah);
677
678 u32 status = sc->intrstatus;
679 u32 rxmask;
680
681 ath9k_ps_wakeup(sc);
682 spin_lock(&sc->sc_pcu_lock);
683
684 if ((status & ATH9K_INT_FATAL) ||
685 (status & ATH9K_INT_BB_WATCHDOG)) {
686 #ifdef CONFIG_ATH9K_DEBUGFS
687 enum ath_reset_type type;
688
689 if (status & ATH9K_INT_FATAL)
690 type = RESET_TYPE_FATAL_INT;
691 else
692 type = RESET_TYPE_BB_WATCHDOG;
693
694 RESET_STAT_INC(sc, type);
695 #endif
696 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
697 goto out;
698 }
699
700 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
701 /*
702 * TSF sync does not look correct; remain awake to sync with
703 * the next Beacon.
704 */
705 ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n");
706 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
707 }
708
709 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
710 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
711 ATH9K_INT_RXORN);
712 else
713 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
714
715 if (status & rxmask) {
716 /* Check for high priority Rx first */
717 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
718 (status & ATH9K_INT_RXHP))
719 ath_rx_tasklet(sc, 0, true);
720
721 ath_rx_tasklet(sc, 0, false);
722 }
723
724 if (status & ATH9K_INT_TX) {
725 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
726 ath_tx_edma_tasklet(sc);
727 else
728 ath_tx_tasklet(sc);
729 }
730
731 ath9k_btcoex_handle_interrupt(sc, status);
732
733 out:
734 /* re-enable hardware interrupt */
735 ath9k_hw_enable_interrupts(ah);
736
737 spin_unlock(&sc->sc_pcu_lock);
738 ath9k_ps_restore(sc);
739 }
740
741 irqreturn_t ath_isr(int irq, void *dev)
742 {
743 #define SCHED_INTR ( \
744 ATH9K_INT_FATAL | \
745 ATH9K_INT_BB_WATCHDOG | \
746 ATH9K_INT_RXORN | \
747 ATH9K_INT_RXEOL | \
748 ATH9K_INT_RX | \
749 ATH9K_INT_RXLP | \
750 ATH9K_INT_RXHP | \
751 ATH9K_INT_TX | \
752 ATH9K_INT_BMISS | \
753 ATH9K_INT_CST | \
754 ATH9K_INT_TSFOOR | \
755 ATH9K_INT_GENTIMER | \
756 ATH9K_INT_MCI)
757
758 struct ath_softc *sc = dev;
759 struct ath_hw *ah = sc->sc_ah;
760 struct ath_common *common = ath9k_hw_common(ah);
761 enum ath9k_int status;
762 bool sched = false;
763
764 /*
765 * The hardware is not ready/present, don't
766 * touch anything. Note this can happen early
767 * on if the IRQ is shared.
768 */
769 if (sc->sc_flags & SC_OP_INVALID)
770 return IRQ_NONE;
771
772
773 /* shared irq, not for us */
774
775 if (!ath9k_hw_intrpend(ah))
776 return IRQ_NONE;
777
778 /*
779 * Figure out the reason(s) for the interrupt. Note
780 * that the hal returns a pseudo-ISR that may include
781 * bits we haven't explicitly enabled so we mask the
782 * value to insure we only process bits we requested.
783 */
784 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
785 status &= ah->imask; /* discard unasked-for bits */
786
787 /*
788 * If there are no status bits set, then this interrupt was not
789 * for me (should have been caught above).
790 */
791 if (!status)
792 return IRQ_NONE;
793
794 /* Cache the status */
795 sc->intrstatus = status;
796
797 if (status & SCHED_INTR)
798 sched = true;
799
800 /*
801 * If a FATAL or RXORN interrupt is received, we have to reset the
802 * chip immediately.
803 */
804 if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
805 !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
806 goto chip_reset;
807
808 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
809 (status & ATH9K_INT_BB_WATCHDOG)) {
810
811 spin_lock(&common->cc_lock);
812 ath_hw_cycle_counters_update(common);
813 ar9003_hw_bb_watchdog_dbg_info(ah);
814 spin_unlock(&common->cc_lock);
815
816 goto chip_reset;
817 }
818
819 if (status & ATH9K_INT_SWBA)
820 tasklet_schedule(&sc->bcon_tasklet);
821
822 if (status & ATH9K_INT_TXURN)
823 ath9k_hw_updatetxtriglevel(ah, true);
824
825 if (status & ATH9K_INT_RXEOL) {
826 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
827 ath9k_hw_set_interrupts(ah);
828 }
829
830 if (status & ATH9K_INT_MIB) {
831 /*
832 * Disable interrupts until we service the MIB
833 * interrupt; otherwise it will continue to
834 * fire.
835 */
836 ath9k_hw_disable_interrupts(ah);
837 /*
838 * Let the hal handle the event. We assume
839 * it will clear whatever condition caused
840 * the interrupt.
841 */
842 spin_lock(&common->cc_lock);
843 ath9k_hw_proc_mib_event(ah);
844 spin_unlock(&common->cc_lock);
845 ath9k_hw_enable_interrupts(ah);
846 }
847
848 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
849 if (status & ATH9K_INT_TIM_TIMER) {
850 if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
851 goto chip_reset;
852 /* Clear RxAbort bit so that we can
853 * receive frames */
854 ath9k_setpower(sc, ATH9K_PM_AWAKE);
855 ath9k_hw_setrxabort(sc->sc_ah, 0);
856 sc->ps_flags |= PS_WAIT_FOR_BEACON;
857 }
858
859 chip_reset:
860
861 ath_debug_stat_interrupt(sc, status);
862
863 if (sched) {
864 /* turn off every interrupt */
865 ath9k_hw_disable_interrupts(ah);
866 tasklet_schedule(&sc->intr_tq);
867 }
868
869 return IRQ_HANDLED;
870
871 #undef SCHED_INTR
872 }
873
874 static int ath_reset(struct ath_softc *sc, bool retry_tx)
875 {
876 int r;
877
878 ath9k_ps_wakeup(sc);
879
880 r = ath_reset_internal(sc, NULL, retry_tx);
881
882 if (retry_tx) {
883 int i;
884 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
885 if (ATH_TXQ_SETUP(sc, i)) {
886 spin_lock_bh(&sc->tx.txq[i].axq_lock);
887 ath_txq_schedule(sc, &sc->tx.txq[i]);
888 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
889 }
890 }
891 }
892
893 ath9k_ps_restore(sc);
894
895 return r;
896 }
897
898 void ath_reset_work(struct work_struct *work)
899 {
900 struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work);
901
902 ath_reset(sc, true);
903 }
904
905 void ath_hw_check(struct work_struct *work)
906 {
907 struct ath_softc *sc = container_of(work, struct ath_softc, hw_check_work);
908 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
909 unsigned long flags;
910 int busy;
911 u8 is_alive, nbeacon = 1;
912
913 ath9k_ps_wakeup(sc);
914 is_alive = ath9k_hw_check_alive(sc->sc_ah);
915
916 if (is_alive && !AR_SREV_9300(sc->sc_ah))
917 goto out;
918 else if (!is_alive && AR_SREV_9300(sc->sc_ah)) {
919 ath_dbg(common, RESET,
920 "DCU stuck is detected. Schedule chip reset\n");
921 RESET_STAT_INC(sc, RESET_TYPE_MAC_HANG);
922 goto sched_reset;
923 }
924
925 spin_lock_irqsave(&common->cc_lock, flags);
926 busy = ath_update_survey_stats(sc);
927 spin_unlock_irqrestore(&common->cc_lock, flags);
928
929 ath_dbg(common, RESET, "Possible baseband hang, busy=%d (try %d)\n",
930 busy, sc->hw_busy_count + 1);
931 if (busy >= 99) {
932 if (++sc->hw_busy_count >= 3) {
933 RESET_STAT_INC(sc, RESET_TYPE_BB_HANG);
934 goto sched_reset;
935 }
936 } else if (busy >= 0) {
937 sc->hw_busy_count = 0;
938 nbeacon = 3;
939 }
940
941 ath_start_rx_poll(sc, nbeacon);
942 goto out;
943
944 sched_reset:
945 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
946 out:
947 ath9k_ps_restore(sc);
948 }
949
950 static void ath_hw_pll_rx_hang_check(struct ath_softc *sc, u32 pll_sqsum)
951 {
952 static int count;
953 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
954
955 if (pll_sqsum >= 0x40000) {
956 count++;
957 if (count == 3) {
958 /* Rx is hung for more than 500ms. Reset it */
959 ath_dbg(common, RESET, "Possible RX hang, resetting\n");
960 RESET_STAT_INC(sc, RESET_TYPE_PLL_HANG);
961 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
962 count = 0;
963 }
964 } else
965 count = 0;
966 }
967
968 void ath_hw_pll_work(struct work_struct *work)
969 {
970 struct ath_softc *sc = container_of(work, struct ath_softc,
971 hw_pll_work.work);
972 u32 pll_sqsum;
973
974 if (AR_SREV_9485(sc->sc_ah)) {
975
976 ath9k_ps_wakeup(sc);
977 pll_sqsum = ar9003_get_pll_sqsum_dvc(sc->sc_ah);
978 ath9k_ps_restore(sc);
979
980 ath_hw_pll_rx_hang_check(sc, pll_sqsum);
981
982 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/5);
983 }
984 }
985
986 /**********************/
987 /* mac80211 callbacks */
988 /**********************/
989
990 static int ath9k_start(struct ieee80211_hw *hw)
991 {
992 struct ath_softc *sc = hw->priv;
993 struct ath_hw *ah = sc->sc_ah;
994 struct ath_common *common = ath9k_hw_common(ah);
995 struct ieee80211_channel *curchan = hw->conf.channel;
996 struct ath9k_channel *init_channel;
997 int r;
998
999 ath_dbg(common, CONFIG,
1000 "Starting driver with initial channel: %d MHz\n",
1001 curchan->center_freq);
1002
1003 ath9k_ps_wakeup(sc);
1004 mutex_lock(&sc->mutex);
1005
1006 init_channel = ath9k_cmn_get_curchannel(hw, ah);
1007
1008 /* Reset SERDES registers */
1009 ath9k_hw_configpcipowersave(ah, false);
1010
1011 /*
1012 * The basic interface to setting the hardware in a good
1013 * state is ``reset''. On return the hardware is known to
1014 * be powered up and with interrupts disabled. This must
1015 * be followed by initialization of the appropriate bits
1016 * and then setup of the interrupt mask.
1017 */
1018 spin_lock_bh(&sc->sc_pcu_lock);
1019
1020 atomic_set(&ah->intr_ref_cnt, -1);
1021
1022 r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
1023 if (r) {
1024 ath_err(common,
1025 "Unable to reset hardware; reset status %d (freq %u MHz)\n",
1026 r, curchan->center_freq);
1027 spin_unlock_bh(&sc->sc_pcu_lock);
1028 goto mutex_unlock;
1029 }
1030
1031 /* Setup our intr mask. */
1032 ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
1033 ATH9K_INT_RXORN | ATH9K_INT_FATAL |
1034 ATH9K_INT_GLOBAL;
1035
1036 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
1037 ah->imask |= ATH9K_INT_RXHP |
1038 ATH9K_INT_RXLP |
1039 ATH9K_INT_BB_WATCHDOG;
1040 else
1041 ah->imask |= ATH9K_INT_RX;
1042
1043 ah->imask |= ATH9K_INT_GTT;
1044
1045 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
1046 ah->imask |= ATH9K_INT_CST;
1047
1048 if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI)
1049 ah->imask |= ATH9K_INT_MCI;
1050
1051 sc->sc_flags &= ~SC_OP_INVALID;
1052 sc->sc_ah->is_monitoring = false;
1053
1054 if (!ath_complete_reset(sc, false)) {
1055 r = -EIO;
1056 spin_unlock_bh(&sc->sc_pcu_lock);
1057 goto mutex_unlock;
1058 }
1059
1060 if (ah->led_pin >= 0) {
1061 ath9k_hw_cfg_output(ah, ah->led_pin,
1062 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1063 ath9k_hw_set_gpio(ah, ah->led_pin, 0);
1064 }
1065
1066 /*
1067 * Reset key cache to sane defaults (all entries cleared) instead of
1068 * semi-random values after suspend/resume.
1069 */
1070 ath9k_cmn_init_crypto(sc->sc_ah);
1071
1072 spin_unlock_bh(&sc->sc_pcu_lock);
1073
1074 ath9k_start_btcoex(sc);
1075
1076 if (ah->caps.pcie_lcr_extsync_en && common->bus_ops->extn_synch_en)
1077 common->bus_ops->extn_synch_en(common);
1078
1079 mutex_unlock:
1080 mutex_unlock(&sc->mutex);
1081
1082 ath9k_ps_restore(sc);
1083
1084 return r;
1085 }
1086
1087 static void ath9k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
1088 {
1089 struct ath_softc *sc = hw->priv;
1090 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1091 struct ath_tx_control txctl;
1092 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1093
1094 if (sc->ps_enabled) {
1095 /*
1096 * mac80211 does not set PM field for normal data frames, so we
1097 * need to update that based on the current PS mode.
1098 */
1099 if (ieee80211_is_data(hdr->frame_control) &&
1100 !ieee80211_is_nullfunc(hdr->frame_control) &&
1101 !ieee80211_has_pm(hdr->frame_control)) {
1102 ath_dbg(common, PS,
1103 "Add PM=1 for a TX frame while in PS mode\n");
1104 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
1105 }
1106 }
1107
1108 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) {
1109 /*
1110 * We are using PS-Poll and mac80211 can request TX while in
1111 * power save mode. Need to wake up hardware for the TX to be
1112 * completed and if needed, also for RX of buffered frames.
1113 */
1114 ath9k_ps_wakeup(sc);
1115 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
1116 ath9k_hw_setrxabort(sc->sc_ah, 0);
1117 if (ieee80211_is_pspoll(hdr->frame_control)) {
1118 ath_dbg(common, PS,
1119 "Sending PS-Poll to pick a buffered frame\n");
1120 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
1121 } else {
1122 ath_dbg(common, PS, "Wake up to complete TX\n");
1123 sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
1124 }
1125 /*
1126 * The actual restore operation will happen only after
1127 * the ps_flags bit is cleared. We are just dropping
1128 * the ps_usecount here.
1129 */
1130 ath9k_ps_restore(sc);
1131 }
1132
1133 /*
1134 * Cannot tx while the hardware is in full sleep, it first needs a full
1135 * chip reset to recover from that
1136 */
1137 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) {
1138 ath_err(common, "TX while HW is in FULL_SLEEP mode\n");
1139 goto exit;
1140 }
1141
1142 memset(&txctl, 0, sizeof(struct ath_tx_control));
1143 txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
1144
1145 ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb);
1146
1147 if (ath_tx_start(hw, skb, &txctl) != 0) {
1148 ath_dbg(common, XMIT, "TX failed\n");
1149 TX_STAT_INC(txctl.txq->axq_qnum, txfailed);
1150 goto exit;
1151 }
1152
1153 return;
1154 exit:
1155 dev_kfree_skb_any(skb);
1156 }
1157
1158 static void ath9k_stop(struct ieee80211_hw *hw)
1159 {
1160 struct ath_softc *sc = hw->priv;
1161 struct ath_hw *ah = sc->sc_ah;
1162 struct ath_common *common = ath9k_hw_common(ah);
1163 bool prev_idle;
1164
1165 mutex_lock(&sc->mutex);
1166
1167 ath_cancel_work(sc);
1168 del_timer_sync(&sc->rx_poll_timer);
1169
1170 if (sc->sc_flags & SC_OP_INVALID) {
1171 ath_dbg(common, ANY, "Device not present\n");
1172 mutex_unlock(&sc->mutex);
1173 return;
1174 }
1175
1176 /* Ensure HW is awake when we try to shut it down. */
1177 ath9k_ps_wakeup(sc);
1178
1179 ath9k_stop_btcoex(sc);
1180
1181 spin_lock_bh(&sc->sc_pcu_lock);
1182
1183 /* prevent tasklets to enable interrupts once we disable them */
1184 ah->imask &= ~ATH9K_INT_GLOBAL;
1185
1186 /* make sure h/w will not generate any interrupt
1187 * before setting the invalid flag. */
1188 ath9k_hw_disable_interrupts(ah);
1189
1190 spin_unlock_bh(&sc->sc_pcu_lock);
1191
1192 /* we can now sync irq and kill any running tasklets, since we already
1193 * disabled interrupts and not holding a spin lock */
1194 synchronize_irq(sc->irq);
1195 tasklet_kill(&sc->intr_tq);
1196 tasklet_kill(&sc->bcon_tasklet);
1197
1198 prev_idle = sc->ps_idle;
1199 sc->ps_idle = true;
1200
1201 spin_lock_bh(&sc->sc_pcu_lock);
1202
1203 if (ah->led_pin >= 0) {
1204 ath9k_hw_set_gpio(ah, ah->led_pin, 1);
1205 ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
1206 }
1207
1208 ath_prepare_reset(sc, false, true);
1209
1210 if (sc->rx.frag) {
1211 dev_kfree_skb_any(sc->rx.frag);
1212 sc->rx.frag = NULL;
1213 }
1214
1215 if (!ah->curchan)
1216 ah->curchan = ath9k_cmn_get_curchannel(hw, ah);
1217
1218 ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
1219 ath9k_hw_phy_disable(ah);
1220
1221 ath9k_hw_configpcipowersave(ah, true);
1222
1223 spin_unlock_bh(&sc->sc_pcu_lock);
1224
1225 ath9k_ps_restore(sc);
1226
1227 sc->sc_flags |= SC_OP_INVALID;
1228 sc->ps_idle = prev_idle;
1229
1230 mutex_unlock(&sc->mutex);
1231
1232 ath_dbg(common, CONFIG, "Driver halt\n");
1233 }
1234
1235 bool ath9k_uses_beacons(int type)
1236 {
1237 switch (type) {
1238 case NL80211_IFTYPE_AP:
1239 case NL80211_IFTYPE_ADHOC:
1240 case NL80211_IFTYPE_MESH_POINT:
1241 return true;
1242 default:
1243 return false;
1244 }
1245 }
1246
1247 static void ath9k_reclaim_beacon(struct ath_softc *sc,
1248 struct ieee80211_vif *vif)
1249 {
1250 struct ath_vif *avp = (void *)vif->drv_priv;
1251
1252 ath9k_set_beaconing_status(sc, false);
1253 ath_beacon_return(sc, avp);
1254 ath9k_set_beaconing_status(sc, true);
1255 }
1256
1257 static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
1258 {
1259 struct ath9k_vif_iter_data *iter_data = data;
1260 int i;
1261
1262 if (iter_data->hw_macaddr)
1263 for (i = 0; i < ETH_ALEN; i++)
1264 iter_data->mask[i] &=
1265 ~(iter_data->hw_macaddr[i] ^ mac[i]);
1266
1267 switch (vif->type) {
1268 case NL80211_IFTYPE_AP:
1269 iter_data->naps++;
1270 break;
1271 case NL80211_IFTYPE_STATION:
1272 iter_data->nstations++;
1273 break;
1274 case NL80211_IFTYPE_ADHOC:
1275 iter_data->nadhocs++;
1276 break;
1277 case NL80211_IFTYPE_MESH_POINT:
1278 iter_data->nmeshes++;
1279 break;
1280 case NL80211_IFTYPE_WDS:
1281 iter_data->nwds++;
1282 break;
1283 default:
1284 break;
1285 }
1286 }
1287
1288 /* Called with sc->mutex held. */
1289 void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
1290 struct ieee80211_vif *vif,
1291 struct ath9k_vif_iter_data *iter_data)
1292 {
1293 struct ath_softc *sc = hw->priv;
1294 struct ath_hw *ah = sc->sc_ah;
1295 struct ath_common *common = ath9k_hw_common(ah);
1296
1297 /*
1298 * Use the hardware MAC address as reference, the hardware uses it
1299 * together with the BSSID mask when matching addresses.
1300 */
1301 memset(iter_data, 0, sizeof(*iter_data));
1302 iter_data->hw_macaddr = common->macaddr;
1303 memset(&iter_data->mask, 0xff, ETH_ALEN);
1304
1305 if (vif)
1306 ath9k_vif_iter(iter_data, vif->addr, vif);
1307
1308 /* Get list of all active MAC addresses */
1309 ieee80211_iterate_active_interfaces_atomic(sc->hw, ath9k_vif_iter,
1310 iter_data);
1311 }
1312
1313 /* Called with sc->mutex held. */
1314 static void ath9k_calculate_summary_state(struct ieee80211_hw *hw,
1315 struct ieee80211_vif *vif)
1316 {
1317 struct ath_softc *sc = hw->priv;
1318 struct ath_hw *ah = sc->sc_ah;
1319 struct ath_common *common = ath9k_hw_common(ah);
1320 struct ath9k_vif_iter_data iter_data;
1321
1322 ath9k_calculate_iter_data(hw, vif, &iter_data);
1323
1324 /* Set BSSID mask. */
1325 memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
1326 ath_hw_setbssidmask(common);
1327
1328 /* Set op-mode & TSF */
1329 if (iter_data.naps > 0) {
1330 ath9k_hw_set_tsfadjust(ah, 1);
1331 sc->sc_flags |= SC_OP_TSF_RESET;
1332 ah->opmode = NL80211_IFTYPE_AP;
1333 } else {
1334 ath9k_hw_set_tsfadjust(ah, 0);
1335 sc->sc_flags &= ~SC_OP_TSF_RESET;
1336
1337 if (iter_data.nmeshes)
1338 ah->opmode = NL80211_IFTYPE_MESH_POINT;
1339 else if (iter_data.nwds)
1340 ah->opmode = NL80211_IFTYPE_AP;
1341 else if (iter_data.nadhocs)
1342 ah->opmode = NL80211_IFTYPE_ADHOC;
1343 else
1344 ah->opmode = NL80211_IFTYPE_STATION;
1345 }
1346
1347 /*
1348 * Enable MIB interrupts when there are hardware phy counters.
1349 */
1350 if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0) {
1351 if (ah->config.enable_ani)
1352 ah->imask |= ATH9K_INT_MIB;
1353 ah->imask |= ATH9K_INT_TSFOOR;
1354 } else {
1355 ah->imask &= ~ATH9K_INT_MIB;
1356 ah->imask &= ~ATH9K_INT_TSFOOR;
1357 }
1358
1359 ath9k_hw_set_interrupts(ah);
1360
1361 /* Set up ANI */
1362 if (iter_data.naps > 0) {
1363 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
1364
1365 if (!common->disable_ani) {
1366 sc->sc_flags |= SC_OP_ANI_RUN;
1367 ath_start_ani(common);
1368 }
1369
1370 } else {
1371 sc->sc_flags &= ~SC_OP_ANI_RUN;
1372 del_timer_sync(&common->ani.timer);
1373 }
1374 }
1375
1376 /* Called with sc->mutex held, vif counts set up properly. */
1377 static void ath9k_do_vif_add_setup(struct ieee80211_hw *hw,
1378 struct ieee80211_vif *vif)
1379 {
1380 struct ath_softc *sc = hw->priv;
1381
1382 ath9k_calculate_summary_state(hw, vif);
1383
1384 if (ath9k_uses_beacons(vif->type)) {
1385 /* Reserve a beacon slot for the vif */
1386 ath9k_set_beaconing_status(sc, false);
1387 ath_beacon_alloc(sc, vif);
1388 ath9k_set_beaconing_status(sc, true);
1389 }
1390 }
1391
1392 void ath_start_rx_poll(struct ath_softc *sc, u8 nbeacon)
1393 {
1394 if (!AR_SREV_9300(sc->sc_ah))
1395 return;
1396
1397 if (!(sc->sc_flags & SC_OP_PRIM_STA_VIF))
1398 return;
1399
1400 mod_timer(&sc->rx_poll_timer, jiffies + msecs_to_jiffies
1401 (nbeacon * sc->cur_beacon_conf.beacon_interval));
1402 }
1403
1404 void ath_rx_poll(unsigned long data)
1405 {
1406 struct ath_softc *sc = (struct ath_softc *)data;
1407
1408 ieee80211_queue_work(sc->hw, &sc->hw_check_work);
1409 }
1410
1411 static int ath9k_add_interface(struct ieee80211_hw *hw,
1412 struct ieee80211_vif *vif)
1413 {
1414 struct ath_softc *sc = hw->priv;
1415 struct ath_hw *ah = sc->sc_ah;
1416 struct ath_common *common = ath9k_hw_common(ah);
1417 int ret = 0;
1418
1419 ath9k_ps_wakeup(sc);
1420 mutex_lock(&sc->mutex);
1421
1422 switch (vif->type) {
1423 case NL80211_IFTYPE_STATION:
1424 case NL80211_IFTYPE_WDS:
1425 case NL80211_IFTYPE_ADHOC:
1426 case NL80211_IFTYPE_AP:
1427 case NL80211_IFTYPE_MESH_POINT:
1428 break;
1429 default:
1430 ath_err(common, "Interface type %d not yet supported\n",
1431 vif->type);
1432 ret = -EOPNOTSUPP;
1433 goto out;
1434 }
1435
1436 if (ath9k_uses_beacons(vif->type)) {
1437 if (sc->nbcnvifs >= ATH_BCBUF) {
1438 ath_err(common, "Not enough beacon buffers when adding"
1439 " new interface of type: %i\n",
1440 vif->type);
1441 ret = -ENOBUFS;
1442 goto out;
1443 }
1444 }
1445
1446 if ((ah->opmode == NL80211_IFTYPE_ADHOC) ||
1447 ((vif->type == NL80211_IFTYPE_ADHOC) &&
1448 sc->nvifs > 0)) {
1449 ath_err(common, "Cannot create ADHOC interface when other"
1450 " interfaces already exist.\n");
1451 ret = -EINVAL;
1452 goto out;
1453 }
1454
1455 ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type);
1456
1457 sc->nvifs++;
1458
1459 ath9k_do_vif_add_setup(hw, vif);
1460 out:
1461 mutex_unlock(&sc->mutex);
1462 ath9k_ps_restore(sc);
1463 return ret;
1464 }
1465
1466 static int ath9k_change_interface(struct ieee80211_hw *hw,
1467 struct ieee80211_vif *vif,
1468 enum nl80211_iftype new_type,
1469 bool p2p)
1470 {
1471 struct ath_softc *sc = hw->priv;
1472 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1473 int ret = 0;
1474
1475 ath_dbg(common, CONFIG, "Change Interface\n");
1476 mutex_lock(&sc->mutex);
1477 ath9k_ps_wakeup(sc);
1478
1479 /* See if new interface type is valid. */
1480 if ((new_type == NL80211_IFTYPE_ADHOC) &&
1481 (sc->nvifs > 1)) {
1482 ath_err(common, "When using ADHOC, it must be the only"
1483 " interface.\n");
1484 ret = -EINVAL;
1485 goto out;
1486 }
1487
1488 if (ath9k_uses_beacons(new_type) &&
1489 !ath9k_uses_beacons(vif->type)) {
1490 if (sc->nbcnvifs >= ATH_BCBUF) {
1491 ath_err(common, "No beacon slot available\n");
1492 ret = -ENOBUFS;
1493 goto out;
1494 }
1495 }
1496
1497 /* Clean up old vif stuff */
1498 if (ath9k_uses_beacons(vif->type))
1499 ath9k_reclaim_beacon(sc, vif);
1500
1501 /* Add new settings */
1502 vif->type = new_type;
1503 vif->p2p = p2p;
1504
1505 ath9k_do_vif_add_setup(hw, vif);
1506 out:
1507 ath9k_ps_restore(sc);
1508 mutex_unlock(&sc->mutex);
1509 return ret;
1510 }
1511
1512 static void ath9k_remove_interface(struct ieee80211_hw *hw,
1513 struct ieee80211_vif *vif)
1514 {
1515 struct ath_softc *sc = hw->priv;
1516 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1517
1518 ath_dbg(common, CONFIG, "Detach Interface\n");
1519
1520 ath9k_ps_wakeup(sc);
1521 mutex_lock(&sc->mutex);
1522
1523 sc->nvifs--;
1524
1525 /* Reclaim beacon resources */
1526 if (ath9k_uses_beacons(vif->type))
1527 ath9k_reclaim_beacon(sc, vif);
1528
1529 ath9k_calculate_summary_state(hw, NULL);
1530
1531 mutex_unlock(&sc->mutex);
1532 ath9k_ps_restore(sc);
1533 }
1534
1535 static void ath9k_enable_ps(struct ath_softc *sc)
1536 {
1537 struct ath_hw *ah = sc->sc_ah;
1538 struct ath_common *common = ath9k_hw_common(ah);
1539
1540 sc->ps_enabled = true;
1541 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1542 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
1543 ah->imask |= ATH9K_INT_TIM_TIMER;
1544 ath9k_hw_set_interrupts(ah);
1545 }
1546 ath9k_hw_setrxabort(ah, 1);
1547 }
1548 ath_dbg(common, PS, "PowerSave enabled\n");
1549 }
1550
1551 static void ath9k_disable_ps(struct ath_softc *sc)
1552 {
1553 struct ath_hw *ah = sc->sc_ah;
1554 struct ath_common *common = ath9k_hw_common(ah);
1555
1556 sc->ps_enabled = false;
1557 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
1558 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1559 ath9k_hw_setrxabort(ah, 0);
1560 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
1561 PS_WAIT_FOR_CAB |
1562 PS_WAIT_FOR_PSPOLL_DATA |
1563 PS_WAIT_FOR_TX_ACK);
1564 if (ah->imask & ATH9K_INT_TIM_TIMER) {
1565 ah->imask &= ~ATH9K_INT_TIM_TIMER;
1566 ath9k_hw_set_interrupts(ah);
1567 }
1568 }
1569 ath_dbg(common, PS, "PowerSave disabled\n");
1570 }
1571
1572 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
1573 {
1574 struct ath_softc *sc = hw->priv;
1575 struct ath_hw *ah = sc->sc_ah;
1576 struct ath_common *common = ath9k_hw_common(ah);
1577 struct ieee80211_conf *conf = &hw->conf;
1578 bool reset_channel = false;
1579
1580 ath9k_ps_wakeup(sc);
1581 mutex_lock(&sc->mutex);
1582
1583 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
1584 sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
1585 if (sc->ps_idle)
1586 ath_cancel_work(sc);
1587 else
1588 /*
1589 * The chip needs a reset to properly wake up from
1590 * full sleep
1591 */
1592 reset_channel = ah->chip_fullsleep;
1593 }
1594
1595 /*
1596 * We just prepare to enable PS. We have to wait until our AP has
1597 * ACK'd our null data frame to disable RX otherwise we'll ignore
1598 * those ACKs and end up retransmitting the same null data frames.
1599 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
1600 */
1601 if (changed & IEEE80211_CONF_CHANGE_PS) {
1602 unsigned long flags;
1603 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1604 if (conf->flags & IEEE80211_CONF_PS)
1605 ath9k_enable_ps(sc);
1606 else
1607 ath9k_disable_ps(sc);
1608 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1609 }
1610
1611 if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
1612 if (conf->flags & IEEE80211_CONF_MONITOR) {
1613 ath_dbg(common, CONFIG, "Monitor mode is enabled\n");
1614 sc->sc_ah->is_monitoring = true;
1615 } else {
1616 ath_dbg(common, CONFIG, "Monitor mode is disabled\n");
1617 sc->sc_ah->is_monitoring = false;
1618 }
1619 }
1620
1621 if ((changed & IEEE80211_CONF_CHANGE_CHANNEL) || reset_channel) {
1622 struct ieee80211_channel *curchan = hw->conf.channel;
1623 int pos = curchan->hw_value;
1624 int old_pos = -1;
1625 unsigned long flags;
1626
1627 if (ah->curchan)
1628 old_pos = ah->curchan - &ah->channels[0];
1629
1630 if (hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)
1631 sc->sc_flags |= SC_OP_OFFCHANNEL;
1632 else
1633 sc->sc_flags &= ~SC_OP_OFFCHANNEL;
1634
1635 ath_dbg(common, CONFIG, "Set channel: %d MHz type: %d\n",
1636 curchan->center_freq, conf->channel_type);
1637
1638 /* update survey stats for the old channel before switching */
1639 spin_lock_irqsave(&common->cc_lock, flags);
1640 ath_update_survey_stats(sc);
1641 spin_unlock_irqrestore(&common->cc_lock, flags);
1642
1643 /*
1644 * Preserve the current channel values, before updating
1645 * the same channel
1646 */
1647 if (ah->curchan && (old_pos == pos))
1648 ath9k_hw_getnf(ah, ah->curchan);
1649
1650 ath9k_cmn_update_ichannel(&sc->sc_ah->channels[pos],
1651 curchan, conf->channel_type);
1652
1653 /*
1654 * If the operating channel changes, change the survey in-use flags
1655 * along with it.
1656 * Reset the survey data for the new channel, unless we're switching
1657 * back to the operating channel from an off-channel operation.
1658 */
1659 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) &&
1660 sc->cur_survey != &sc->survey[pos]) {
1661
1662 if (sc->cur_survey)
1663 sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE;
1664
1665 sc->cur_survey = &sc->survey[pos];
1666
1667 memset(sc->cur_survey, 0, sizeof(struct survey_info));
1668 sc->cur_survey->filled |= SURVEY_INFO_IN_USE;
1669 } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) {
1670 memset(&sc->survey[pos], 0, sizeof(struct survey_info));
1671 }
1672
1673 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
1674 ath_err(common, "Unable to set channel\n");
1675 mutex_unlock(&sc->mutex);
1676 return -EINVAL;
1677 }
1678
1679 /*
1680 * The most recent snapshot of channel->noisefloor for the old
1681 * channel is only available after the hardware reset. Copy it to
1682 * the survey stats now.
1683 */
1684 if (old_pos >= 0)
1685 ath_update_survey_nf(sc, old_pos);
1686 }
1687
1688 if (changed & IEEE80211_CONF_CHANGE_POWER) {
1689 ath_dbg(common, CONFIG, "Set power: %d\n", conf->power_level);
1690 sc->config.txpowlimit = 2 * conf->power_level;
1691 ath9k_cmn_update_txpow(ah, sc->curtxpow,
1692 sc->config.txpowlimit, &sc->curtxpow);
1693 }
1694
1695 mutex_unlock(&sc->mutex);
1696 ath9k_ps_restore(sc);
1697
1698 return 0;
1699 }
1700
1701 #define SUPPORTED_FILTERS \
1702 (FIF_PROMISC_IN_BSS | \
1703 FIF_ALLMULTI | \
1704 FIF_CONTROL | \
1705 FIF_PSPOLL | \
1706 FIF_OTHER_BSS | \
1707 FIF_BCN_PRBRESP_PROMISC | \
1708 FIF_PROBE_REQ | \
1709 FIF_FCSFAIL)
1710
1711 /* FIXME: sc->sc_full_reset ? */
1712 static void ath9k_configure_filter(struct ieee80211_hw *hw,
1713 unsigned int changed_flags,
1714 unsigned int *total_flags,
1715 u64 multicast)
1716 {
1717 struct ath_softc *sc = hw->priv;
1718 u32 rfilt;
1719
1720 changed_flags &= SUPPORTED_FILTERS;
1721 *total_flags &= SUPPORTED_FILTERS;
1722
1723 sc->rx.rxfilter = *total_flags;
1724 ath9k_ps_wakeup(sc);
1725 rfilt = ath_calcrxfilter(sc);
1726 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
1727 ath9k_ps_restore(sc);
1728
1729 ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n",
1730 rfilt);
1731 }
1732
1733 static int ath9k_sta_add(struct ieee80211_hw *hw,
1734 struct ieee80211_vif *vif,
1735 struct ieee80211_sta *sta)
1736 {
1737 struct ath_softc *sc = hw->priv;
1738 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1739 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1740 struct ieee80211_key_conf ps_key = { };
1741
1742 ath_node_attach(sc, sta, vif);
1743
1744 if (vif->type != NL80211_IFTYPE_AP &&
1745 vif->type != NL80211_IFTYPE_AP_VLAN)
1746 return 0;
1747
1748 an->ps_key = ath_key_config(common, vif, sta, &ps_key);
1749
1750 return 0;
1751 }
1752
1753 static void ath9k_del_ps_key(struct ath_softc *sc,
1754 struct ieee80211_vif *vif,
1755 struct ieee80211_sta *sta)
1756 {
1757 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1758 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1759 struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key };
1760
1761 if (!an->ps_key)
1762 return;
1763
1764 ath_key_delete(common, &ps_key);
1765 }
1766
1767 static int ath9k_sta_remove(struct ieee80211_hw *hw,
1768 struct ieee80211_vif *vif,
1769 struct ieee80211_sta *sta)
1770 {
1771 struct ath_softc *sc = hw->priv;
1772
1773 ath9k_del_ps_key(sc, vif, sta);
1774 ath_node_detach(sc, sta);
1775
1776 return 0;
1777 }
1778
1779 static void ath9k_sta_notify(struct ieee80211_hw *hw,
1780 struct ieee80211_vif *vif,
1781 enum sta_notify_cmd cmd,
1782 struct ieee80211_sta *sta)
1783 {
1784 struct ath_softc *sc = hw->priv;
1785 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1786
1787 if (!sta->ht_cap.ht_supported)
1788 return;
1789
1790 switch (cmd) {
1791 case STA_NOTIFY_SLEEP:
1792 an->sleeping = true;
1793 ath_tx_aggr_sleep(sta, sc, an);
1794 break;
1795 case STA_NOTIFY_AWAKE:
1796 an->sleeping = false;
1797 ath_tx_aggr_wakeup(sc, an);
1798 break;
1799 }
1800 }
1801
1802 static int ath9k_conf_tx(struct ieee80211_hw *hw,
1803 struct ieee80211_vif *vif, u16 queue,
1804 const struct ieee80211_tx_queue_params *params)
1805 {
1806 struct ath_softc *sc = hw->priv;
1807 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1808 struct ath_txq *txq;
1809 struct ath9k_tx_queue_info qi;
1810 int ret = 0;
1811
1812 if (queue >= WME_NUM_AC)
1813 return 0;
1814
1815 txq = sc->tx.txq_map[queue];
1816
1817 ath9k_ps_wakeup(sc);
1818 mutex_lock(&sc->mutex);
1819
1820 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
1821
1822 qi.tqi_aifs = params->aifs;
1823 qi.tqi_cwmin = params->cw_min;
1824 qi.tqi_cwmax = params->cw_max;
1825 qi.tqi_burstTime = params->txop;
1826
1827 ath_dbg(common, CONFIG,
1828 "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
1829 queue, txq->axq_qnum, params->aifs, params->cw_min,
1830 params->cw_max, params->txop);
1831
1832 ret = ath_txq_update(sc, txq->axq_qnum, &qi);
1833 if (ret)
1834 ath_err(common, "TXQ Update failed\n");
1835
1836 if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC)
1837 if (queue == WME_AC_BE && !ret)
1838 ath_beaconq_config(sc);
1839
1840 mutex_unlock(&sc->mutex);
1841 ath9k_ps_restore(sc);
1842
1843 return ret;
1844 }
1845
1846 static int ath9k_set_key(struct ieee80211_hw *hw,
1847 enum set_key_cmd cmd,
1848 struct ieee80211_vif *vif,
1849 struct ieee80211_sta *sta,
1850 struct ieee80211_key_conf *key)
1851 {
1852 struct ath_softc *sc = hw->priv;
1853 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1854 int ret = 0;
1855
1856 if (ath9k_modparam_nohwcrypt)
1857 return -ENOSPC;
1858
1859 if ((vif->type == NL80211_IFTYPE_ADHOC ||
1860 vif->type == NL80211_IFTYPE_MESH_POINT) &&
1861 (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
1862 key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
1863 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
1864 /*
1865 * For now, disable hw crypto for the RSN IBSS group keys. This
1866 * could be optimized in the future to use a modified key cache
1867 * design to support per-STA RX GTK, but until that gets
1868 * implemented, use of software crypto for group addressed
1869 * frames is a acceptable to allow RSN IBSS to be used.
1870 */
1871 return -EOPNOTSUPP;
1872 }
1873
1874 mutex_lock(&sc->mutex);
1875 ath9k_ps_wakeup(sc);
1876 ath_dbg(common, CONFIG, "Set HW Key\n");
1877
1878 switch (cmd) {
1879 case SET_KEY:
1880 if (sta)
1881 ath9k_del_ps_key(sc, vif, sta);
1882
1883 ret = ath_key_config(common, vif, sta, key);
1884 if (ret >= 0) {
1885 key->hw_key_idx = ret;
1886 /* push IV and Michael MIC generation to stack */
1887 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
1888 if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
1889 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
1890 if (sc->sc_ah->sw_mgmt_crypto &&
1891 key->cipher == WLAN_CIPHER_SUITE_CCMP)
1892 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
1893 ret = 0;
1894 }
1895 break;
1896 case DISABLE_KEY:
1897 ath_key_delete(common, key);
1898 break;
1899 default:
1900 ret = -EINVAL;
1901 }
1902
1903 ath9k_ps_restore(sc);
1904 mutex_unlock(&sc->mutex);
1905
1906 return ret;
1907 }
1908 static void ath9k_bss_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
1909 {
1910 struct ath_softc *sc = data;
1911 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1912 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
1913 struct ath_vif *avp = (void *)vif->drv_priv;
1914
1915 /*
1916 * Skip iteration if primary station vif's bss info
1917 * was not changed
1918 */
1919 if (sc->sc_flags & SC_OP_PRIM_STA_VIF)
1920 return;
1921
1922 if (bss_conf->assoc) {
1923 sc->sc_flags |= SC_OP_PRIM_STA_VIF;
1924 avp->primary_sta_vif = true;
1925 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1926 common->curaid = bss_conf->aid;
1927 ath9k_hw_write_associd(sc->sc_ah);
1928 ath_dbg(common, CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
1929 bss_conf->aid, common->curbssid);
1930 ath_beacon_config(sc, vif);
1931 /*
1932 * Request a re-configuration of Beacon related timers
1933 * on the receipt of the first Beacon frame (i.e.,
1934 * after time sync with the AP).
1935 */
1936 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
1937 /* Reset rssi stats */
1938 sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
1939 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
1940
1941 ath_start_rx_poll(sc, 3);
1942
1943 if (!common->disable_ani) {
1944 sc->sc_flags |= SC_OP_ANI_RUN;
1945 ath_start_ani(common);
1946 }
1947
1948 }
1949 }
1950
1951 static void ath9k_config_bss(struct ath_softc *sc, struct ieee80211_vif *vif)
1952 {
1953 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1954 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
1955 struct ath_vif *avp = (void *)vif->drv_priv;
1956
1957 if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION)
1958 return;
1959
1960 /* Reconfigure bss info */
1961 if (avp->primary_sta_vif && !bss_conf->assoc) {
1962 ath_dbg(common, CONFIG, "Bss Info DISASSOC %d, bssid %pM\n",
1963 common->curaid, common->curbssid);
1964 sc->sc_flags &= ~(SC_OP_PRIM_STA_VIF | SC_OP_BEACONS);
1965 avp->primary_sta_vif = false;
1966 memset(common->curbssid, 0, ETH_ALEN);
1967 common->curaid = 0;
1968 }
1969
1970 ieee80211_iterate_active_interfaces_atomic(
1971 sc->hw, ath9k_bss_iter, sc);
1972
1973 /*
1974 * None of station vifs are associated.
1975 * Clear bssid & aid
1976 */
1977 if (!(sc->sc_flags & SC_OP_PRIM_STA_VIF)) {
1978 ath9k_hw_write_associd(sc->sc_ah);
1979 /* Stop ANI */
1980 sc->sc_flags &= ~SC_OP_ANI_RUN;
1981 del_timer_sync(&common->ani.timer);
1982 del_timer_sync(&sc->rx_poll_timer);
1983 memset(&sc->caldata, 0, sizeof(sc->caldata));
1984 }
1985 }
1986
1987 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
1988 struct ieee80211_vif *vif,
1989 struct ieee80211_bss_conf *bss_conf,
1990 u32 changed)
1991 {
1992 struct ath_softc *sc = hw->priv;
1993 struct ath_hw *ah = sc->sc_ah;
1994 struct ath_common *common = ath9k_hw_common(ah);
1995 struct ath_vif *avp = (void *)vif->drv_priv;
1996 int slottime;
1997
1998 ath9k_ps_wakeup(sc);
1999 mutex_lock(&sc->mutex);
2000
2001 if (changed & BSS_CHANGED_ASSOC) {
2002 ath9k_config_bss(sc, vif);
2003
2004 ath_dbg(common, CONFIG, "BSSID: %pM aid: 0x%x\n",
2005 common->curbssid, common->curaid);
2006 }
2007
2008 if (changed & BSS_CHANGED_IBSS) {
2009 /* There can be only one vif available */
2010 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
2011 common->curaid = bss_conf->aid;
2012 ath9k_hw_write_associd(sc->sc_ah);
2013
2014 if (bss_conf->ibss_joined) {
2015 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
2016
2017 if (!common->disable_ani) {
2018 sc->sc_flags |= SC_OP_ANI_RUN;
2019 ath_start_ani(common);
2020 }
2021
2022 } else {
2023 sc->sc_flags &= ~SC_OP_ANI_RUN;
2024 del_timer_sync(&common->ani.timer);
2025 del_timer_sync(&sc->rx_poll_timer);
2026 }
2027 }
2028
2029 /*
2030 * In case of AP mode, the HW TSF has to be reset
2031 * when the beacon interval changes.
2032 */
2033 if ((changed & BSS_CHANGED_BEACON_INT) &&
2034 (vif->type == NL80211_IFTYPE_AP))
2035 sc->sc_flags |= SC_OP_TSF_RESET;
2036
2037 /* Configure beaconing (AP, IBSS, MESH) */
2038 if (ath9k_uses_beacons(vif->type) &&
2039 ((changed & BSS_CHANGED_BEACON) ||
2040 (changed & BSS_CHANGED_BEACON_ENABLED) ||
2041 (changed & BSS_CHANGED_BEACON_INT))) {
2042 ath9k_set_beaconing_status(sc, false);
2043 if (bss_conf->enable_beacon)
2044 ath_beacon_alloc(sc, vif);
2045 else
2046 avp->is_bslot_active = false;
2047 ath_beacon_config(sc, vif);
2048 ath9k_set_beaconing_status(sc, true);
2049 }
2050
2051 if (changed & BSS_CHANGED_ERP_SLOT) {
2052 if (bss_conf->use_short_slot)
2053 slottime = 9;
2054 else
2055 slottime = 20;
2056 if (vif->type == NL80211_IFTYPE_AP) {
2057 /*
2058 * Defer update, so that connected stations can adjust
2059 * their settings at the same time.
2060 * See beacon.c for more details
2061 */
2062 sc->beacon.slottime = slottime;
2063 sc->beacon.updateslot = UPDATE;
2064 } else {
2065 ah->slottime = slottime;
2066 ath9k_hw_init_global_settings(ah);
2067 }
2068 }
2069
2070 mutex_unlock(&sc->mutex);
2071 ath9k_ps_restore(sc);
2072 }
2073
2074 static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
2075 {
2076 struct ath_softc *sc = hw->priv;
2077 u64 tsf;
2078
2079 mutex_lock(&sc->mutex);
2080 ath9k_ps_wakeup(sc);
2081 tsf = ath9k_hw_gettsf64(sc->sc_ah);
2082 ath9k_ps_restore(sc);
2083 mutex_unlock(&sc->mutex);
2084
2085 return tsf;
2086 }
2087
2088 static void ath9k_set_tsf(struct ieee80211_hw *hw,
2089 struct ieee80211_vif *vif,
2090 u64 tsf)
2091 {
2092 struct ath_softc *sc = hw->priv;
2093
2094 mutex_lock(&sc->mutex);
2095 ath9k_ps_wakeup(sc);
2096 ath9k_hw_settsf64(sc->sc_ah, tsf);
2097 ath9k_ps_restore(sc);
2098 mutex_unlock(&sc->mutex);
2099 }
2100
2101 static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
2102 {
2103 struct ath_softc *sc = hw->priv;
2104
2105 mutex_lock(&sc->mutex);
2106
2107 ath9k_ps_wakeup(sc);
2108 ath9k_hw_reset_tsf(sc->sc_ah);
2109 ath9k_ps_restore(sc);
2110
2111 mutex_unlock(&sc->mutex);
2112 }
2113
2114 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2115 struct ieee80211_vif *vif,
2116 enum ieee80211_ampdu_mlme_action action,
2117 struct ieee80211_sta *sta,
2118 u16 tid, u16 *ssn, u8 buf_size)
2119 {
2120 struct ath_softc *sc = hw->priv;
2121 int ret = 0;
2122
2123 local_bh_disable();
2124
2125 switch (action) {
2126 case IEEE80211_AMPDU_RX_START:
2127 break;
2128 case IEEE80211_AMPDU_RX_STOP:
2129 break;
2130 case IEEE80211_AMPDU_TX_START:
2131 ath9k_ps_wakeup(sc);
2132 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
2133 if (!ret)
2134 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
2135 ath9k_ps_restore(sc);
2136 break;
2137 case IEEE80211_AMPDU_TX_STOP:
2138 ath9k_ps_wakeup(sc);
2139 ath_tx_aggr_stop(sc, sta, tid);
2140 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
2141 ath9k_ps_restore(sc);
2142 break;
2143 case IEEE80211_AMPDU_TX_OPERATIONAL:
2144 ath9k_ps_wakeup(sc);
2145 ath_tx_aggr_resume(sc, sta, tid);
2146 ath9k_ps_restore(sc);
2147 break;
2148 default:
2149 ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
2150 }
2151
2152 local_bh_enable();
2153
2154 return ret;
2155 }
2156
2157 static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
2158 struct survey_info *survey)
2159 {
2160 struct ath_softc *sc = hw->priv;
2161 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2162 struct ieee80211_supported_band *sband;
2163 struct ieee80211_channel *chan;
2164 unsigned long flags;
2165 int pos;
2166
2167 spin_lock_irqsave(&common->cc_lock, flags);
2168 if (idx == 0)
2169 ath_update_survey_stats(sc);
2170
2171 sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
2172 if (sband && idx >= sband->n_channels) {
2173 idx -= sband->n_channels;
2174 sband = NULL;
2175 }
2176
2177 if (!sband)
2178 sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
2179
2180 if (!sband || idx >= sband->n_channels) {
2181 spin_unlock_irqrestore(&common->cc_lock, flags);
2182 return -ENOENT;
2183 }
2184
2185 chan = &sband->channels[idx];
2186 pos = chan->hw_value;
2187 memcpy(survey, &sc->survey[pos], sizeof(*survey));
2188 survey->channel = chan;
2189 spin_unlock_irqrestore(&common->cc_lock, flags);
2190
2191 return 0;
2192 }
2193
2194 static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
2195 {
2196 struct ath_softc *sc = hw->priv;
2197 struct ath_hw *ah = sc->sc_ah;
2198
2199 mutex_lock(&sc->mutex);
2200 ah->coverage_class = coverage_class;
2201
2202 ath9k_ps_wakeup(sc);
2203 ath9k_hw_init_global_settings(ah);
2204 ath9k_ps_restore(sc);
2205
2206 mutex_unlock(&sc->mutex);
2207 }
2208
2209 static void ath9k_flush(struct ieee80211_hw *hw, bool drop)
2210 {
2211 struct ath_softc *sc = hw->priv;
2212 struct ath_hw *ah = sc->sc_ah;
2213 struct ath_common *common = ath9k_hw_common(ah);
2214 int timeout = 200; /* ms */
2215 int i, j;
2216 bool drain_txq;
2217
2218 mutex_lock(&sc->mutex);
2219 cancel_delayed_work_sync(&sc->tx_complete_work);
2220
2221 if (ah->ah_flags & AH_UNPLUGGED) {
2222 ath_dbg(common, ANY, "Device has been unplugged!\n");
2223 mutex_unlock(&sc->mutex);
2224 return;
2225 }
2226
2227 if (sc->sc_flags & SC_OP_INVALID) {
2228 ath_dbg(common, ANY, "Device not present\n");
2229 mutex_unlock(&sc->mutex);
2230 return;
2231 }
2232
2233 for (j = 0; j < timeout; j++) {
2234 bool npend = false;
2235
2236 if (j)
2237 usleep_range(1000, 2000);
2238
2239 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2240 if (!ATH_TXQ_SETUP(sc, i))
2241 continue;
2242
2243 npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]);
2244
2245 if (npend)
2246 break;
2247 }
2248
2249 if (!npend)
2250 break;
2251 }
2252
2253 if (drop) {
2254 ath9k_ps_wakeup(sc);
2255 spin_lock_bh(&sc->sc_pcu_lock);
2256 drain_txq = ath_drain_all_txq(sc, false);
2257 spin_unlock_bh(&sc->sc_pcu_lock);
2258
2259 if (!drain_txq)
2260 ath_reset(sc, false);
2261
2262 ath9k_ps_restore(sc);
2263 ieee80211_wake_queues(hw);
2264 }
2265
2266 ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0);
2267 mutex_unlock(&sc->mutex);
2268 }
2269
2270 static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
2271 {
2272 struct ath_softc *sc = hw->priv;
2273 int i;
2274
2275 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2276 if (!ATH_TXQ_SETUP(sc, i))
2277 continue;
2278
2279 if (ath9k_has_pending_frames(sc, &sc->tx.txq[i]))
2280 return true;
2281 }
2282 return false;
2283 }
2284
2285 static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
2286 {
2287 struct ath_softc *sc = hw->priv;
2288 struct ath_hw *ah = sc->sc_ah;
2289 struct ieee80211_vif *vif;
2290 struct ath_vif *avp;
2291 struct ath_buf *bf;
2292 struct ath_tx_status ts;
2293 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
2294 int status;
2295
2296 vif = sc->beacon.bslot[0];
2297 if (!vif)
2298 return 0;
2299
2300 avp = (void *)vif->drv_priv;
2301 if (!avp->is_bslot_active)
2302 return 0;
2303
2304 if (!sc->beacon.tx_processed && !edma) {
2305 tasklet_disable(&sc->bcon_tasklet);
2306
2307 bf = avp->av_bcbuf;
2308 if (!bf || !bf->bf_mpdu)
2309 goto skip;
2310
2311 status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
2312 if (status == -EINPROGRESS)
2313 goto skip;
2314
2315 sc->beacon.tx_processed = true;
2316 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
2317
2318 skip:
2319 tasklet_enable(&sc->bcon_tasklet);
2320 }
2321
2322 return sc->beacon.tx_last;
2323 }
2324
2325 static int ath9k_get_stats(struct ieee80211_hw *hw,
2326 struct ieee80211_low_level_stats *stats)
2327 {
2328 struct ath_softc *sc = hw->priv;
2329 struct ath_hw *ah = sc->sc_ah;
2330 struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats;
2331
2332 stats->dot11ACKFailureCount = mib_stats->ackrcv_bad;
2333 stats->dot11RTSFailureCount = mib_stats->rts_bad;
2334 stats->dot11FCSErrorCount = mib_stats->fcs_bad;
2335 stats->dot11RTSSuccessCount = mib_stats->rts_good;
2336 return 0;
2337 }
2338
2339 static u32 fill_chainmask(u32 cap, u32 new)
2340 {
2341 u32 filled = 0;
2342 int i;
2343
2344 for (i = 0; cap && new; i++, cap >>= 1) {
2345 if (!(cap & BIT(0)))
2346 continue;
2347
2348 if (new & BIT(0))
2349 filled |= BIT(i);
2350
2351 new >>= 1;
2352 }
2353
2354 return filled;
2355 }
2356
2357 static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
2358 {
2359 struct ath_softc *sc = hw->priv;
2360 struct ath_hw *ah = sc->sc_ah;
2361
2362 if (!rx_ant || !tx_ant)
2363 return -EINVAL;
2364
2365 sc->ant_rx = rx_ant;
2366 sc->ant_tx = tx_ant;
2367
2368 if (ah->caps.rx_chainmask == 1)
2369 return 0;
2370
2371 /* AR9100 runs into calibration issues if not all rx chains are enabled */
2372 if (AR_SREV_9100(ah))
2373 ah->rxchainmask = 0x7;
2374 else
2375 ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant);
2376
2377 ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant);
2378 ath9k_reload_chainmask_settings(sc);
2379
2380 return 0;
2381 }
2382
2383 static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
2384 {
2385 struct ath_softc *sc = hw->priv;
2386
2387 *tx_ant = sc->ant_tx;
2388 *rx_ant = sc->ant_rx;
2389 return 0;
2390 }
2391
2392 struct ieee80211_ops ath9k_ops = {
2393 .tx = ath9k_tx,
2394 .start = ath9k_start,
2395 .stop = ath9k_stop,
2396 .add_interface = ath9k_add_interface,
2397 .change_interface = ath9k_change_interface,
2398 .remove_interface = ath9k_remove_interface,
2399 .config = ath9k_config,
2400 .configure_filter = ath9k_configure_filter,
2401 .sta_add = ath9k_sta_add,
2402 .sta_remove = ath9k_sta_remove,
2403 .sta_notify = ath9k_sta_notify,
2404 .conf_tx = ath9k_conf_tx,
2405 .bss_info_changed = ath9k_bss_info_changed,
2406 .set_key = ath9k_set_key,
2407 .get_tsf = ath9k_get_tsf,
2408 .set_tsf = ath9k_set_tsf,
2409 .reset_tsf = ath9k_reset_tsf,
2410 .ampdu_action = ath9k_ampdu_action,
2411 .get_survey = ath9k_get_survey,
2412 .rfkill_poll = ath9k_rfkill_poll_state,
2413 .set_coverage_class = ath9k_set_coverage_class,
2414 .flush = ath9k_flush,
2415 .tx_frames_pending = ath9k_tx_frames_pending,
2416 .tx_last_beacon = ath9k_tx_last_beacon,
2417 .get_stats = ath9k_get_stats,
2418 .set_antenna = ath9k_set_antenna,
2419 .get_antenna = ath9k_get_antenna,
2420 };
Linux kernel - Deliverables
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