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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wirel...
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / main.c
1 /*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/nl80211.h>
18 #include "ath9k.h"
19
20 #define ATH_PCI_VERSION "0.1"
21
22 static char *dev_info = "ath9k";
23
24 MODULE_AUTHOR("Atheros Communications");
25 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
26 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
27 MODULE_LICENSE("Dual BSD/GPL");
28
29 static int modparam_nohwcrypt;
30 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
31 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
32
33 /* We use the hw_value as an index into our private channel structure */
34
35 #define CHAN2G(_freq, _idx) { \
36 .center_freq = (_freq), \
37 .hw_value = (_idx), \
38 .max_power = 20, \
39 }
40
41 #define CHAN5G(_freq, _idx) { \
42 .band = IEEE80211_BAND_5GHZ, \
43 .center_freq = (_freq), \
44 .hw_value = (_idx), \
45 .max_power = 20, \
46 }
47
48 /* Some 2 GHz radios are actually tunable on 2312-2732
49 * on 5 MHz steps, we support the channels which we know
50 * we have calibration data for all cards though to make
51 * this static */
52 static struct ieee80211_channel ath9k_2ghz_chantable[] = {
53 CHAN2G(2412, 0), /* Channel 1 */
54 CHAN2G(2417, 1), /* Channel 2 */
55 CHAN2G(2422, 2), /* Channel 3 */
56 CHAN2G(2427, 3), /* Channel 4 */
57 CHAN2G(2432, 4), /* Channel 5 */
58 CHAN2G(2437, 5), /* Channel 6 */
59 CHAN2G(2442, 6), /* Channel 7 */
60 CHAN2G(2447, 7), /* Channel 8 */
61 CHAN2G(2452, 8), /* Channel 9 */
62 CHAN2G(2457, 9), /* Channel 10 */
63 CHAN2G(2462, 10), /* Channel 11 */
64 CHAN2G(2467, 11), /* Channel 12 */
65 CHAN2G(2472, 12), /* Channel 13 */
66 CHAN2G(2484, 13), /* Channel 14 */
67 };
68
69 /* Some 5 GHz radios are actually tunable on XXXX-YYYY
70 * on 5 MHz steps, we support the channels which we know
71 * we have calibration data for all cards though to make
72 * this static */
73 static struct ieee80211_channel ath9k_5ghz_chantable[] = {
74 /* _We_ call this UNII 1 */
75 CHAN5G(5180, 14), /* Channel 36 */
76 CHAN5G(5200, 15), /* Channel 40 */
77 CHAN5G(5220, 16), /* Channel 44 */
78 CHAN5G(5240, 17), /* Channel 48 */
79 /* _We_ call this UNII 2 */
80 CHAN5G(5260, 18), /* Channel 52 */
81 CHAN5G(5280, 19), /* Channel 56 */
82 CHAN5G(5300, 20), /* Channel 60 */
83 CHAN5G(5320, 21), /* Channel 64 */
84 /* _We_ call this "Middle band" */
85 CHAN5G(5500, 22), /* Channel 100 */
86 CHAN5G(5520, 23), /* Channel 104 */
87 CHAN5G(5540, 24), /* Channel 108 */
88 CHAN5G(5560, 25), /* Channel 112 */
89 CHAN5G(5580, 26), /* Channel 116 */
90 CHAN5G(5600, 27), /* Channel 120 */
91 CHAN5G(5620, 28), /* Channel 124 */
92 CHAN5G(5640, 29), /* Channel 128 */
93 CHAN5G(5660, 30), /* Channel 132 */
94 CHAN5G(5680, 31), /* Channel 136 */
95 CHAN5G(5700, 32), /* Channel 140 */
96 /* _We_ call this UNII 3 */
97 CHAN5G(5745, 33), /* Channel 149 */
98 CHAN5G(5765, 34), /* Channel 153 */
99 CHAN5G(5785, 35), /* Channel 157 */
100 CHAN5G(5805, 36), /* Channel 161 */
101 CHAN5G(5825, 37), /* Channel 165 */
102 };
103
104 static void ath_cache_conf_rate(struct ath_softc *sc,
105 struct ieee80211_conf *conf)
106 {
107 switch (conf->channel->band) {
108 case IEEE80211_BAND_2GHZ:
109 if (conf_is_ht20(conf))
110 sc->cur_rate_table =
111 sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
112 else if (conf_is_ht40_minus(conf))
113 sc->cur_rate_table =
114 sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
115 else if (conf_is_ht40_plus(conf))
116 sc->cur_rate_table =
117 sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
118 else
119 sc->cur_rate_table =
120 sc->hw_rate_table[ATH9K_MODE_11G];
121 break;
122 case IEEE80211_BAND_5GHZ:
123 if (conf_is_ht20(conf))
124 sc->cur_rate_table =
125 sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
126 else if (conf_is_ht40_minus(conf))
127 sc->cur_rate_table =
128 sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
129 else if (conf_is_ht40_plus(conf))
130 sc->cur_rate_table =
131 sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
132 else
133 sc->cur_rate_table =
134 sc->hw_rate_table[ATH9K_MODE_11A];
135 break;
136 default:
137 BUG_ON(1);
138 break;
139 }
140 }
141
142 static void ath_update_txpow(struct ath_softc *sc)
143 {
144 struct ath_hw *ah = sc->sc_ah;
145 u32 txpow;
146
147 if (sc->curtxpow != sc->config.txpowlimit) {
148 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
149 /* read back in case value is clamped */
150 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
151 sc->curtxpow = txpow;
152 }
153 }
154
155 static u8 parse_mpdudensity(u8 mpdudensity)
156 {
157 /*
158 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
159 * 0 for no restriction
160 * 1 for 1/4 us
161 * 2 for 1/2 us
162 * 3 for 1 us
163 * 4 for 2 us
164 * 5 for 4 us
165 * 6 for 8 us
166 * 7 for 16 us
167 */
168 switch (mpdudensity) {
169 case 0:
170 return 0;
171 case 1:
172 case 2:
173 case 3:
174 /* Our lower layer calculations limit our precision to
175 1 microsecond */
176 return 1;
177 case 4:
178 return 2;
179 case 5:
180 return 4;
181 case 6:
182 return 8;
183 case 7:
184 return 16;
185 default:
186 return 0;
187 }
188 }
189
190 static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
191 {
192 const struct ath_rate_table *rate_table = NULL;
193 struct ieee80211_supported_band *sband;
194 struct ieee80211_rate *rate;
195 int i, maxrates;
196
197 switch (band) {
198 case IEEE80211_BAND_2GHZ:
199 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
200 break;
201 case IEEE80211_BAND_5GHZ:
202 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
203 break;
204 default:
205 break;
206 }
207
208 if (rate_table == NULL)
209 return;
210
211 sband = &sc->sbands[band];
212 rate = sc->rates[band];
213
214 if (rate_table->rate_cnt > ATH_RATE_MAX)
215 maxrates = ATH_RATE_MAX;
216 else
217 maxrates = rate_table->rate_cnt;
218
219 for (i = 0; i < maxrates; i++) {
220 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
221 rate[i].hw_value = rate_table->info[i].ratecode;
222 if (rate_table->info[i].short_preamble) {
223 rate[i].hw_value_short = rate_table->info[i].ratecode |
224 rate_table->info[i].short_preamble;
225 rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE;
226 }
227 sband->n_bitrates++;
228
229 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
230 rate[i].bitrate / 10, rate[i].hw_value);
231 }
232 }
233
234 static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc,
235 struct ieee80211_hw *hw)
236 {
237 struct ieee80211_channel *curchan = hw->conf.channel;
238 struct ath9k_channel *channel;
239 u8 chan_idx;
240
241 chan_idx = curchan->hw_value;
242 channel = &sc->sc_ah->channels[chan_idx];
243 ath9k_update_ichannel(sc, hw, channel);
244 return channel;
245 }
246
247 /*
248 * Set/change channels. If the channel is really being changed, it's done
249 * by reseting the chip. To accomplish this we must first cleanup any pending
250 * DMA, then restart stuff.
251 */
252 int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
253 struct ath9k_channel *hchan)
254 {
255 struct ath_hw *ah = sc->sc_ah;
256 bool fastcc = true, stopped;
257 struct ieee80211_channel *channel = hw->conf.channel;
258 int r;
259
260 if (sc->sc_flags & SC_OP_INVALID)
261 return -EIO;
262
263 ath9k_ps_wakeup(sc);
264
265 /*
266 * This is only performed if the channel settings have
267 * actually changed.
268 *
269 * To switch channels clear any pending DMA operations;
270 * wait long enough for the RX fifo to drain, reset the
271 * hardware at the new frequency, and then re-enable
272 * the relevant bits of the h/w.
273 */
274 ath9k_hw_set_interrupts(ah, 0);
275 ath_drain_all_txq(sc, false);
276 stopped = ath_stoprecv(sc);
277
278 /* XXX: do not flush receive queue here. We don't want
279 * to flush data frames already in queue because of
280 * changing channel. */
281
282 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
283 fastcc = false;
284
285 DPRINTF(sc, ATH_DBG_CONFIG,
286 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
287 sc->sc_ah->curchan->channel,
288 channel->center_freq, sc->tx_chan_width);
289
290 spin_lock_bh(&sc->sc_resetlock);
291
292 r = ath9k_hw_reset(ah, hchan, fastcc);
293 if (r) {
294 DPRINTF(sc, ATH_DBG_FATAL,
295 "Unable to reset channel (%u Mhz) "
296 "reset status %d\n",
297 channel->center_freq, r);
298 spin_unlock_bh(&sc->sc_resetlock);
299 goto ps_restore;
300 }
301 spin_unlock_bh(&sc->sc_resetlock);
302
303 sc->sc_flags &= ~SC_OP_FULL_RESET;
304
305 if (ath_startrecv(sc) != 0) {
306 DPRINTF(sc, ATH_DBG_FATAL,
307 "Unable to restart recv logic\n");
308 r = -EIO;
309 goto ps_restore;
310 }
311
312 ath_cache_conf_rate(sc, &hw->conf);
313 ath_update_txpow(sc);
314 ath9k_hw_set_interrupts(ah, sc->imask);
315
316 ps_restore:
317 ath9k_ps_restore(sc);
318 return r;
319 }
320
321 /*
322 * This routine performs the periodic noise floor calibration function
323 * that is used to adjust and optimize the chip performance. This
324 * takes environmental changes (location, temperature) into account.
325 * When the task is complete, it reschedules itself depending on the
326 * appropriate interval that was calculated.
327 */
328 static void ath_ani_calibrate(unsigned long data)
329 {
330 struct ath_softc *sc = (struct ath_softc *)data;
331 struct ath_hw *ah = sc->sc_ah;
332 bool longcal = false;
333 bool shortcal = false;
334 bool aniflag = false;
335 unsigned int timestamp = jiffies_to_msecs(jiffies);
336 u32 cal_interval, short_cal_interval;
337
338 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
339 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
340
341 /*
342 * don't calibrate when we're scanning.
343 * we are most likely not on our home channel.
344 */
345 spin_lock(&sc->ani_lock);
346 if (sc->sc_flags & SC_OP_SCANNING)
347 goto set_timer;
348
349 /* Only calibrate if awake */
350 if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
351 goto set_timer;
352
353 ath9k_ps_wakeup(sc);
354
355 /* Long calibration runs independently of short calibration. */
356 if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
357 longcal = true;
358 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
359 sc->ani.longcal_timer = timestamp;
360 }
361
362 /* Short calibration applies only while caldone is false */
363 if (!sc->ani.caldone) {
364 if ((timestamp - sc->ani.shortcal_timer) >= short_cal_interval) {
365 shortcal = true;
366 DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
367 sc->ani.shortcal_timer = timestamp;
368 sc->ani.resetcal_timer = timestamp;
369 }
370 } else {
371 if ((timestamp - sc->ani.resetcal_timer) >=
372 ATH_RESTART_CALINTERVAL) {
373 sc->ani.caldone = ath9k_hw_reset_calvalid(ah);
374 if (sc->ani.caldone)
375 sc->ani.resetcal_timer = timestamp;
376 }
377 }
378
379 /* Verify whether we must check ANI */
380 if ((timestamp - sc->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
381 aniflag = true;
382 sc->ani.checkani_timer = timestamp;
383 }
384
385 /* Skip all processing if there's nothing to do. */
386 if (longcal || shortcal || aniflag) {
387 /* Call ANI routine if necessary */
388 if (aniflag)
389 ath9k_hw_ani_monitor(ah, &sc->nodestats, ah->curchan);
390
391 /* Perform calibration if necessary */
392 if (longcal || shortcal) {
393 sc->ani.caldone = ath9k_hw_calibrate(ah, ah->curchan,
394 sc->rx_chainmask, longcal);
395
396 if (longcal)
397 sc->ani.noise_floor = ath9k_hw_getchan_noise(ah,
398 ah->curchan);
399
400 DPRINTF(sc, ATH_DBG_ANI," calibrate chan %u/%x nf: %d\n",
401 ah->curchan->channel, ah->curchan->channelFlags,
402 sc->ani.noise_floor);
403 }
404 }
405
406 ath9k_ps_restore(sc);
407
408 set_timer:
409 spin_unlock(&sc->ani_lock);
410 /*
411 * Set timer interval based on previous results.
412 * The interval must be the shortest necessary to satisfy ANI,
413 * short calibration and long calibration.
414 */
415 cal_interval = ATH_LONG_CALINTERVAL;
416 if (sc->sc_ah->config.enable_ani)
417 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
418 if (!sc->ani.caldone)
419 cal_interval = min(cal_interval, (u32)short_cal_interval);
420
421 mod_timer(&sc->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
422 }
423
424 static void ath_start_ani(struct ath_softc *sc)
425 {
426 unsigned long timestamp = jiffies_to_msecs(jiffies);
427
428 sc->ani.longcal_timer = timestamp;
429 sc->ani.shortcal_timer = timestamp;
430 sc->ani.checkani_timer = timestamp;
431
432 mod_timer(&sc->ani.timer,
433 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
434 }
435
436 /*
437 * Update tx/rx chainmask. For legacy association,
438 * hard code chainmask to 1x1, for 11n association, use
439 * the chainmask configuration, for bt coexistence, use
440 * the chainmask configuration even in legacy mode.
441 */
442 void ath_update_chainmask(struct ath_softc *sc, int is_ht)
443 {
444 if (is_ht ||
445 (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)) {
446 sc->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
447 sc->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
448 } else {
449 sc->tx_chainmask = 1;
450 sc->rx_chainmask = 1;
451 }
452
453 DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
454 sc->tx_chainmask, sc->rx_chainmask);
455 }
456
457 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
458 {
459 struct ath_node *an;
460
461 an = (struct ath_node *)sta->drv_priv;
462
463 if (sc->sc_flags & SC_OP_TXAGGR) {
464 ath_tx_node_init(sc, an);
465 an->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
466 sta->ht_cap.ampdu_factor);
467 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
468 an->last_rssi = ATH_RSSI_DUMMY_MARKER;
469 }
470 }
471
472 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
473 {
474 struct ath_node *an = (struct ath_node *)sta->drv_priv;
475
476 if (sc->sc_flags & SC_OP_TXAGGR)
477 ath_tx_node_cleanup(sc, an);
478 }
479
480 static void ath9k_tasklet(unsigned long data)
481 {
482 struct ath_softc *sc = (struct ath_softc *)data;
483 u32 status = sc->intrstatus;
484
485 ath9k_ps_wakeup(sc);
486
487 if (status & ATH9K_INT_FATAL) {
488 ath_reset(sc, false);
489 ath9k_ps_restore(sc);
490 return;
491 }
492
493 if (status & (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
494 spin_lock_bh(&sc->rx.rxflushlock);
495 ath_rx_tasklet(sc, 0);
496 spin_unlock_bh(&sc->rx.rxflushlock);
497 }
498
499 if (status & ATH9K_INT_TX)
500 ath_tx_tasklet(sc);
501
502 if ((status & ATH9K_INT_TSFOOR) &&
503 (sc->hw->conf.flags & IEEE80211_CONF_PS)) {
504 /*
505 * TSF sync does not look correct; remain awake to sync with
506 * the next Beacon.
507 */
508 DPRINTF(sc, ATH_DBG_PS, "TSFOOR - Sync with next Beacon\n");
509 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON | SC_OP_BEACON_SYNC;
510 }
511
512 /* re-enable hardware interrupt */
513 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
514 ath9k_ps_restore(sc);
515 }
516
517 irqreturn_t ath_isr(int irq, void *dev)
518 {
519 #define SCHED_INTR ( \
520 ATH9K_INT_FATAL | \
521 ATH9K_INT_RXORN | \
522 ATH9K_INT_RXEOL | \
523 ATH9K_INT_RX | \
524 ATH9K_INT_TX | \
525 ATH9K_INT_BMISS | \
526 ATH9K_INT_CST | \
527 ATH9K_INT_TSFOOR)
528
529 struct ath_softc *sc = dev;
530 struct ath_hw *ah = sc->sc_ah;
531 enum ath9k_int status;
532 bool sched = false;
533
534 /*
535 * The hardware is not ready/present, don't
536 * touch anything. Note this can happen early
537 * on if the IRQ is shared.
538 */
539 if (sc->sc_flags & SC_OP_INVALID)
540 return IRQ_NONE;
541
542
543 /* shared irq, not for us */
544
545 if (!ath9k_hw_intrpend(ah))
546 return IRQ_NONE;
547
548 /*
549 * Figure out the reason(s) for the interrupt. Note
550 * that the hal returns a pseudo-ISR that may include
551 * bits we haven't explicitly enabled so we mask the
552 * value to insure we only process bits we requested.
553 */
554 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
555 status &= sc->imask; /* discard unasked-for bits */
556
557 /*
558 * If there are no status bits set, then this interrupt was not
559 * for me (should have been caught above).
560 */
561 if (!status)
562 return IRQ_NONE;
563
564 /* Cache the status */
565 sc->intrstatus = status;
566
567 if (status & SCHED_INTR)
568 sched = true;
569
570 /*
571 * If a FATAL or RXORN interrupt is received, we have to reset the
572 * chip immediately.
573 */
574 if (status & (ATH9K_INT_FATAL | ATH9K_INT_RXORN))
575 goto chip_reset;
576
577 if (status & ATH9K_INT_SWBA)
578 tasklet_schedule(&sc->bcon_tasklet);
579
580 if (status & ATH9K_INT_TXURN)
581 ath9k_hw_updatetxtriglevel(ah, true);
582
583 if (status & ATH9K_INT_MIB) {
584 /*
585 * Disable interrupts until we service the MIB
586 * interrupt; otherwise it will continue to
587 * fire.
588 */
589 ath9k_hw_set_interrupts(ah, 0);
590 /*
591 * Let the hal handle the event. We assume
592 * it will clear whatever condition caused
593 * the interrupt.
594 */
595 ath9k_hw_procmibevent(ah, &sc->nodestats);
596 ath9k_hw_set_interrupts(ah, sc->imask);
597 }
598
599 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
600 if (status & ATH9K_INT_TIM_TIMER) {
601 /* Clear RxAbort bit so that we can
602 * receive frames */
603 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
604 ath9k_hw_setrxabort(sc->sc_ah, 0);
605 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
606 }
607
608 chip_reset:
609
610 ath_debug_stat_interrupt(sc, status);
611
612 if (sched) {
613 /* turn off every interrupt except SWBA */
614 ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA));
615 tasklet_schedule(&sc->intr_tq);
616 }
617
618 return IRQ_HANDLED;
619
620 #undef SCHED_INTR
621 }
622
623 static u32 ath_get_extchanmode(struct ath_softc *sc,
624 struct ieee80211_channel *chan,
625 enum nl80211_channel_type channel_type)
626 {
627 u32 chanmode = 0;
628
629 switch (chan->band) {
630 case IEEE80211_BAND_2GHZ:
631 switch(channel_type) {
632 case NL80211_CHAN_NO_HT:
633 case NL80211_CHAN_HT20:
634 chanmode = CHANNEL_G_HT20;
635 break;
636 case NL80211_CHAN_HT40PLUS:
637 chanmode = CHANNEL_G_HT40PLUS;
638 break;
639 case NL80211_CHAN_HT40MINUS:
640 chanmode = CHANNEL_G_HT40MINUS;
641 break;
642 }
643 break;
644 case IEEE80211_BAND_5GHZ:
645 switch(channel_type) {
646 case NL80211_CHAN_NO_HT:
647 case NL80211_CHAN_HT20:
648 chanmode = CHANNEL_A_HT20;
649 break;
650 case NL80211_CHAN_HT40PLUS:
651 chanmode = CHANNEL_A_HT40PLUS;
652 break;
653 case NL80211_CHAN_HT40MINUS:
654 chanmode = CHANNEL_A_HT40MINUS;
655 break;
656 }
657 break;
658 default:
659 break;
660 }
661
662 return chanmode;
663 }
664
665 static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
666 struct ath9k_keyval *hk, const u8 *addr,
667 bool authenticator)
668 {
669 const u8 *key_rxmic;
670 const u8 *key_txmic;
671
672 key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
673 key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
674
675 if (addr == NULL) {
676 /*
677 * Group key installation - only two key cache entries are used
678 * regardless of splitmic capability since group key is only
679 * used either for TX or RX.
680 */
681 if (authenticator) {
682 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
683 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
684 } else {
685 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
686 memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
687 }
688 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
689 }
690 if (!sc->splitmic) {
691 /* TX and RX keys share the same key cache entry. */
692 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
693 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
694 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
695 }
696
697 /* Separate key cache entries for TX and RX */
698
699 /* TX key goes at first index, RX key at +32. */
700 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
701 if (!ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, NULL)) {
702 /* TX MIC entry failed. No need to proceed further */
703 DPRINTF(sc, ATH_DBG_FATAL,
704 "Setting TX MIC Key Failed\n");
705 return 0;
706 }
707
708 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
709 /* XXX delete tx key on failure? */
710 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix + 32, hk, addr);
711 }
712
713 static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
714 {
715 int i;
716
717 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
718 if (test_bit(i, sc->keymap) ||
719 test_bit(i + 64, sc->keymap))
720 continue; /* At least one part of TKIP key allocated */
721 if (sc->splitmic &&
722 (test_bit(i + 32, sc->keymap) ||
723 test_bit(i + 64 + 32, sc->keymap)))
724 continue; /* At least one part of TKIP key allocated */
725
726 /* Found a free slot for a TKIP key */
727 return i;
728 }
729 return -1;
730 }
731
732 static int ath_reserve_key_cache_slot(struct ath_softc *sc)
733 {
734 int i;
735
736 /* First, try to find slots that would not be available for TKIP. */
737 if (sc->splitmic) {
738 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 4; i++) {
739 if (!test_bit(i, sc->keymap) &&
740 (test_bit(i + 32, sc->keymap) ||
741 test_bit(i + 64, sc->keymap) ||
742 test_bit(i + 64 + 32, sc->keymap)))
743 return i;
744 if (!test_bit(i + 32, sc->keymap) &&
745 (test_bit(i, sc->keymap) ||
746 test_bit(i + 64, sc->keymap) ||
747 test_bit(i + 64 + 32, sc->keymap)))
748 return i + 32;
749 if (!test_bit(i + 64, sc->keymap) &&
750 (test_bit(i , sc->keymap) ||
751 test_bit(i + 32, sc->keymap) ||
752 test_bit(i + 64 + 32, sc->keymap)))
753 return i + 64;
754 if (!test_bit(i + 64 + 32, sc->keymap) &&
755 (test_bit(i, sc->keymap) ||
756 test_bit(i + 32, sc->keymap) ||
757 test_bit(i + 64, sc->keymap)))
758 return i + 64 + 32;
759 }
760 } else {
761 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
762 if (!test_bit(i, sc->keymap) &&
763 test_bit(i + 64, sc->keymap))
764 return i;
765 if (test_bit(i, sc->keymap) &&
766 !test_bit(i + 64, sc->keymap))
767 return i + 64;
768 }
769 }
770
771 /* No partially used TKIP slots, pick any available slot */
772 for (i = IEEE80211_WEP_NKID; i < sc->keymax; i++) {
773 /* Do not allow slots that could be needed for TKIP group keys
774 * to be used. This limitation could be removed if we know that
775 * TKIP will not be used. */
776 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
777 continue;
778 if (sc->splitmic) {
779 if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
780 continue;
781 if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
782 continue;
783 }
784
785 if (!test_bit(i, sc->keymap))
786 return i; /* Found a free slot for a key */
787 }
788
789 /* No free slot found */
790 return -1;
791 }
792
793 static int ath_key_config(struct ath_softc *sc,
794 struct ieee80211_vif *vif,
795 struct ieee80211_sta *sta,
796 struct ieee80211_key_conf *key)
797 {
798 struct ath9k_keyval hk;
799 const u8 *mac = NULL;
800 int ret = 0;
801 int idx;
802
803 memset(&hk, 0, sizeof(hk));
804
805 switch (key->alg) {
806 case ALG_WEP:
807 hk.kv_type = ATH9K_CIPHER_WEP;
808 break;
809 case ALG_TKIP:
810 hk.kv_type = ATH9K_CIPHER_TKIP;
811 break;
812 case ALG_CCMP:
813 hk.kv_type = ATH9K_CIPHER_AES_CCM;
814 break;
815 default:
816 return -EOPNOTSUPP;
817 }
818
819 hk.kv_len = key->keylen;
820 memcpy(hk.kv_val, key->key, key->keylen);
821
822 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
823 /* For now, use the default keys for broadcast keys. This may
824 * need to change with virtual interfaces. */
825 idx = key->keyidx;
826 } else if (key->keyidx) {
827 if (WARN_ON(!sta))
828 return -EOPNOTSUPP;
829 mac = sta->addr;
830
831 if (vif->type != NL80211_IFTYPE_AP) {
832 /* Only keyidx 0 should be used with unicast key, but
833 * allow this for client mode for now. */
834 idx = key->keyidx;
835 } else
836 return -EIO;
837 } else {
838 if (WARN_ON(!sta))
839 return -EOPNOTSUPP;
840 mac = sta->addr;
841
842 if (key->alg == ALG_TKIP)
843 idx = ath_reserve_key_cache_slot_tkip(sc);
844 else
845 idx = ath_reserve_key_cache_slot(sc);
846 if (idx < 0)
847 return -ENOSPC; /* no free key cache entries */
848 }
849
850 if (key->alg == ALG_TKIP)
851 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac,
852 vif->type == NL80211_IFTYPE_AP);
853 else
854 ret = ath9k_hw_set_keycache_entry(sc->sc_ah, idx, &hk, mac);
855
856 if (!ret)
857 return -EIO;
858
859 set_bit(idx, sc->keymap);
860 if (key->alg == ALG_TKIP) {
861 set_bit(idx + 64, sc->keymap);
862 if (sc->splitmic) {
863 set_bit(idx + 32, sc->keymap);
864 set_bit(idx + 64 + 32, sc->keymap);
865 }
866 }
867
868 return idx;
869 }
870
871 static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
872 {
873 ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
874 if (key->hw_key_idx < IEEE80211_WEP_NKID)
875 return;
876
877 clear_bit(key->hw_key_idx, sc->keymap);
878 if (key->alg != ALG_TKIP)
879 return;
880
881 clear_bit(key->hw_key_idx + 64, sc->keymap);
882 if (sc->splitmic) {
883 clear_bit(key->hw_key_idx + 32, sc->keymap);
884 clear_bit(key->hw_key_idx + 64 + 32, sc->keymap);
885 }
886 }
887
888 static void setup_ht_cap(struct ath_softc *sc,
889 struct ieee80211_sta_ht_cap *ht_info)
890 {
891 #define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3 /* 2 ^ 16 */
892 #define ATH9K_HT_CAP_MPDUDENSITY_8 0x6 /* 8 usec */
893 u8 tx_streams, rx_streams;
894
895 ht_info->ht_supported = true;
896 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
897 IEEE80211_HT_CAP_SM_PS |
898 IEEE80211_HT_CAP_SGI_40 |
899 IEEE80211_HT_CAP_DSSSCCK40;
900
901 ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
902 ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
903
904 /* set up supported mcs set */
905 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
906 tx_streams = !(sc->tx_chainmask & (sc->tx_chainmask - 1)) ? 1 : 2;
907 rx_streams = !(sc->rx_chainmask & (sc->rx_chainmask - 1)) ? 1 : 2;
908
909 if (tx_streams != rx_streams) {
910 DPRINTF(sc, ATH_DBG_CONFIG, "TX streams %d, RX streams: %d\n",
911 tx_streams, rx_streams);
912 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
913 ht_info->mcs.tx_params |= ((tx_streams - 1) <<
914 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
915 }
916
917 ht_info->mcs.rx_mask[0] = 0xff;
918 if (rx_streams >= 2)
919 ht_info->mcs.rx_mask[1] = 0xff;
920
921 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
922 }
923
924 static void ath9k_bss_assoc_info(struct ath_softc *sc,
925 struct ieee80211_vif *vif,
926 struct ieee80211_bss_conf *bss_conf)
927 {
928
929 if (bss_conf->assoc) {
930 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
931 bss_conf->aid, sc->curbssid);
932
933 /* New association, store aid */
934 sc->curaid = bss_conf->aid;
935 ath9k_hw_write_associd(sc);
936
937 /*
938 * Request a re-configuration of Beacon related timers
939 * on the receipt of the first Beacon frame (i.e.,
940 * after time sync with the AP).
941 */
942 sc->sc_flags |= SC_OP_BEACON_SYNC;
943
944 /* Configure the beacon */
945 ath_beacon_config(sc, vif);
946
947 /* Reset rssi stats */
948 sc->nodestats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
949 sc->nodestats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
950 sc->nodestats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
951 sc->nodestats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
952
953 ath_start_ani(sc);
954 } else {
955 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
956 sc->curaid = 0;
957 /* Stop ANI */
958 del_timer_sync(&sc->ani.timer);
959 }
960 }
961
962 /********************************/
963 /* LED functions */
964 /********************************/
965
966 static void ath_led_blink_work(struct work_struct *work)
967 {
968 struct ath_softc *sc = container_of(work, struct ath_softc,
969 ath_led_blink_work.work);
970
971 if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
972 return;
973
974 if ((sc->led_on_duration == ATH_LED_ON_DURATION_IDLE) ||
975 (sc->led_off_duration == ATH_LED_OFF_DURATION_IDLE))
976 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
977 else
978 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
979 (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
980
981 queue_delayed_work(sc->hw->workqueue, &sc->ath_led_blink_work,
982 (sc->sc_flags & SC_OP_LED_ON) ?
983 msecs_to_jiffies(sc->led_off_duration) :
984 msecs_to_jiffies(sc->led_on_duration));
985
986 sc->led_on_duration = sc->led_on_cnt ?
987 max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25) :
988 ATH_LED_ON_DURATION_IDLE;
989 sc->led_off_duration = sc->led_off_cnt ?
990 max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10) :
991 ATH_LED_OFF_DURATION_IDLE;
992 sc->led_on_cnt = sc->led_off_cnt = 0;
993 if (sc->sc_flags & SC_OP_LED_ON)
994 sc->sc_flags &= ~SC_OP_LED_ON;
995 else
996 sc->sc_flags |= SC_OP_LED_ON;
997 }
998
999 static void ath_led_brightness(struct led_classdev *led_cdev,
1000 enum led_brightness brightness)
1001 {
1002 struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
1003 struct ath_softc *sc = led->sc;
1004
1005 switch (brightness) {
1006 case LED_OFF:
1007 if (led->led_type == ATH_LED_ASSOC ||
1008 led->led_type == ATH_LED_RADIO) {
1009 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
1010 (led->led_type == ATH_LED_RADIO));
1011 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1012 if (led->led_type == ATH_LED_RADIO)
1013 sc->sc_flags &= ~SC_OP_LED_ON;
1014 } else {
1015 sc->led_off_cnt++;
1016 }
1017 break;
1018 case LED_FULL:
1019 if (led->led_type == ATH_LED_ASSOC) {
1020 sc->sc_flags |= SC_OP_LED_ASSOCIATED;
1021 queue_delayed_work(sc->hw->workqueue,
1022 &sc->ath_led_blink_work, 0);
1023 } else if (led->led_type == ATH_LED_RADIO) {
1024 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
1025 sc->sc_flags |= SC_OP_LED_ON;
1026 } else {
1027 sc->led_on_cnt++;
1028 }
1029 break;
1030 default:
1031 break;
1032 }
1033 }
1034
1035 static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
1036 char *trigger)
1037 {
1038 int ret;
1039
1040 led->sc = sc;
1041 led->led_cdev.name = led->name;
1042 led->led_cdev.default_trigger = trigger;
1043 led->led_cdev.brightness_set = ath_led_brightness;
1044
1045 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1046 if (ret)
1047 DPRINTF(sc, ATH_DBG_FATAL,
1048 "Failed to register led:%s", led->name);
1049 else
1050 led->registered = 1;
1051 return ret;
1052 }
1053
1054 static void ath_unregister_led(struct ath_led *led)
1055 {
1056 if (led->registered) {
1057 led_classdev_unregister(&led->led_cdev);
1058 led->registered = 0;
1059 }
1060 }
1061
1062 static void ath_deinit_leds(struct ath_softc *sc)
1063 {
1064 cancel_delayed_work_sync(&sc->ath_led_blink_work);
1065 ath_unregister_led(&sc->assoc_led);
1066 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1067 ath_unregister_led(&sc->tx_led);
1068 ath_unregister_led(&sc->rx_led);
1069 ath_unregister_led(&sc->radio_led);
1070 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1071 }
1072
1073 static void ath_init_leds(struct ath_softc *sc)
1074 {
1075 char *trigger;
1076 int ret;
1077
1078 /* Configure gpio 1 for output */
1079 ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
1080 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1081 /* LED off, active low */
1082 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1083
1084 INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
1085
1086 trigger = ieee80211_get_radio_led_name(sc->hw);
1087 snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
1088 "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
1089 ret = ath_register_led(sc, &sc->radio_led, trigger);
1090 sc->radio_led.led_type = ATH_LED_RADIO;
1091 if (ret)
1092 goto fail;
1093
1094 trigger = ieee80211_get_assoc_led_name(sc->hw);
1095 snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
1096 "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
1097 ret = ath_register_led(sc, &sc->assoc_led, trigger);
1098 sc->assoc_led.led_type = ATH_LED_ASSOC;
1099 if (ret)
1100 goto fail;
1101
1102 trigger = ieee80211_get_tx_led_name(sc->hw);
1103 snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
1104 "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
1105 ret = ath_register_led(sc, &sc->tx_led, trigger);
1106 sc->tx_led.led_type = ATH_LED_TX;
1107 if (ret)
1108 goto fail;
1109
1110 trigger = ieee80211_get_rx_led_name(sc->hw);
1111 snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
1112 "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
1113 ret = ath_register_led(sc, &sc->rx_led, trigger);
1114 sc->rx_led.led_type = ATH_LED_RX;
1115 if (ret)
1116 goto fail;
1117
1118 return;
1119
1120 fail:
1121 ath_deinit_leds(sc);
1122 }
1123
1124 void ath_radio_enable(struct ath_softc *sc)
1125 {
1126 struct ath_hw *ah = sc->sc_ah;
1127 struct ieee80211_channel *channel = sc->hw->conf.channel;
1128 int r;
1129
1130 ath9k_ps_wakeup(sc);
1131 ath9k_hw_configpcipowersave(ah, 0);
1132
1133 if (!ah->curchan)
1134 ah->curchan = ath_get_curchannel(sc, sc->hw);
1135
1136 spin_lock_bh(&sc->sc_resetlock);
1137 r = ath9k_hw_reset(ah, ah->curchan, false);
1138 if (r) {
1139 DPRINTF(sc, ATH_DBG_FATAL,
1140 "Unable to reset channel %u (%uMhz) ",
1141 "reset status %d\n",
1142 channel->center_freq, r);
1143 }
1144 spin_unlock_bh(&sc->sc_resetlock);
1145
1146 ath_update_txpow(sc);
1147 if (ath_startrecv(sc) != 0) {
1148 DPRINTF(sc, ATH_DBG_FATAL,
1149 "Unable to restart recv logic\n");
1150 return;
1151 }
1152
1153 if (sc->sc_flags & SC_OP_BEACONS)
1154 ath_beacon_config(sc, NULL); /* restart beacons */
1155
1156 /* Re-Enable interrupts */
1157 ath9k_hw_set_interrupts(ah, sc->imask);
1158
1159 /* Enable LED */
1160 ath9k_hw_cfg_output(ah, ATH_LED_PIN,
1161 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1162 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
1163
1164 ieee80211_wake_queues(sc->hw);
1165 ath9k_ps_restore(sc);
1166 }
1167
1168 void ath_radio_disable(struct ath_softc *sc)
1169 {
1170 struct ath_hw *ah = sc->sc_ah;
1171 struct ieee80211_channel *channel = sc->hw->conf.channel;
1172 int r;
1173
1174 ath9k_ps_wakeup(sc);
1175 ieee80211_stop_queues(sc->hw);
1176
1177 /* Disable LED */
1178 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
1179 ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
1180
1181 /* Disable interrupts */
1182 ath9k_hw_set_interrupts(ah, 0);
1183
1184 ath_drain_all_txq(sc, false); /* clear pending tx frames */
1185 ath_stoprecv(sc); /* turn off frame recv */
1186 ath_flushrecv(sc); /* flush recv queue */
1187
1188 if (!ah->curchan)
1189 ah->curchan = ath_get_curchannel(sc, sc->hw);
1190
1191 spin_lock_bh(&sc->sc_resetlock);
1192 r = ath9k_hw_reset(ah, ah->curchan, false);
1193 if (r) {
1194 DPRINTF(sc, ATH_DBG_FATAL,
1195 "Unable to reset channel %u (%uMhz) "
1196 "reset status %d\n",
1197 channel->center_freq, r);
1198 }
1199 spin_unlock_bh(&sc->sc_resetlock);
1200
1201 ath9k_hw_phy_disable(ah);
1202 ath9k_hw_configpcipowersave(ah, 1);
1203 ath9k_ps_restore(sc);
1204 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1205 }
1206
1207 /*******************/
1208 /* Rfkill */
1209 /*******************/
1210
1211 static bool ath_is_rfkill_set(struct ath_softc *sc)
1212 {
1213 struct ath_hw *ah = sc->sc_ah;
1214
1215 return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
1216 ah->rfkill_polarity;
1217 }
1218
1219 static void ath9k_rfkill_poll_state(struct ieee80211_hw *hw)
1220 {
1221 struct ath_wiphy *aphy = hw->priv;
1222 struct ath_softc *sc = aphy->sc;
1223 bool blocked = !!ath_is_rfkill_set(sc);
1224
1225 wiphy_rfkill_set_hw_state(hw->wiphy, blocked);
1226
1227 if (blocked)
1228 ath_radio_disable(sc);
1229 else
1230 ath_radio_enable(sc);
1231 }
1232
1233 static void ath_start_rfkill_poll(struct ath_softc *sc)
1234 {
1235 struct ath_hw *ah = sc->sc_ah;
1236
1237 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1238 wiphy_rfkill_start_polling(sc->hw->wiphy);
1239 }
1240
1241 void ath_cleanup(struct ath_softc *sc)
1242 {
1243 ath_detach(sc);
1244 free_irq(sc->irq, sc);
1245 ath_bus_cleanup(sc);
1246 kfree(sc->sec_wiphy);
1247 ieee80211_free_hw(sc->hw);
1248 }
1249
1250 void ath_detach(struct ath_softc *sc)
1251 {
1252 struct ieee80211_hw *hw = sc->hw;
1253 int i = 0;
1254
1255 ath9k_ps_wakeup(sc);
1256
1257 DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
1258
1259 ath_deinit_leds(sc);
1260 cancel_work_sync(&sc->chan_work);
1261 cancel_delayed_work_sync(&sc->wiphy_work);
1262 cancel_delayed_work_sync(&sc->tx_complete_work);
1263
1264 for (i = 0; i < sc->num_sec_wiphy; i++) {
1265 struct ath_wiphy *aphy = sc->sec_wiphy[i];
1266 if (aphy == NULL)
1267 continue;
1268 sc->sec_wiphy[i] = NULL;
1269 ieee80211_unregister_hw(aphy->hw);
1270 ieee80211_free_hw(aphy->hw);
1271 }
1272 ieee80211_unregister_hw(hw);
1273 ath_rx_cleanup(sc);
1274 ath_tx_cleanup(sc);
1275
1276 tasklet_kill(&sc->intr_tq);
1277 tasklet_kill(&sc->bcon_tasklet);
1278
1279 if (!(sc->sc_flags & SC_OP_INVALID))
1280 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
1281
1282 /* cleanup tx queues */
1283 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1284 if (ATH_TXQ_SETUP(sc, i))
1285 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1286
1287 ath9k_hw_detach(sc->sc_ah);
1288 ath9k_exit_debug(sc);
1289 }
1290
1291 static int ath9k_reg_notifier(struct wiphy *wiphy,
1292 struct regulatory_request *request)
1293 {
1294 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
1295 struct ath_wiphy *aphy = hw->priv;
1296 struct ath_softc *sc = aphy->sc;
1297 struct ath_regulatory *reg = &sc->sc_ah->regulatory;
1298
1299 return ath_reg_notifier_apply(wiphy, request, reg);
1300 }
1301
1302 static int ath_init(u16 devid, struct ath_softc *sc)
1303 {
1304 struct ath_hw *ah = NULL;
1305 int status;
1306 int error = 0, i;
1307 int csz = 0;
1308
1309 /* XXX: hardware will not be ready until ath_open() being called */
1310 sc->sc_flags |= SC_OP_INVALID;
1311
1312 if (ath9k_init_debug(sc) < 0)
1313 printk(KERN_ERR "Unable to create debugfs files\n");
1314
1315 spin_lock_init(&sc->wiphy_lock);
1316 spin_lock_init(&sc->sc_resetlock);
1317 spin_lock_init(&sc->sc_serial_rw);
1318 spin_lock_init(&sc->ani_lock);
1319 spin_lock_init(&sc->sc_pm_lock);
1320 mutex_init(&sc->mutex);
1321 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1322 tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
1323 (unsigned long)sc);
1324
1325 /*
1326 * Cache line size is used to size and align various
1327 * structures used to communicate with the hardware.
1328 */
1329 ath_read_cachesize(sc, &csz);
1330 /* XXX assert csz is non-zero */
1331 sc->cachelsz = csz << 2; /* convert to bytes */
1332
1333 ah = ath9k_hw_attach(devid, sc, &status);
1334 if (ah == NULL) {
1335 DPRINTF(sc, ATH_DBG_FATAL,
1336 "Unable to attach hardware; HAL status %d\n", status);
1337 error = -ENXIO;
1338 goto bad;
1339 }
1340 sc->sc_ah = ah;
1341
1342 /* Get the hardware key cache size. */
1343 sc->keymax = ah->caps.keycache_size;
1344 if (sc->keymax > ATH_KEYMAX) {
1345 DPRINTF(sc, ATH_DBG_ANY,
1346 "Warning, using only %u entries in %u key cache\n",
1347 ATH_KEYMAX, sc->keymax);
1348 sc->keymax = ATH_KEYMAX;
1349 }
1350
1351 /*
1352 * Reset the key cache since some parts do not
1353 * reset the contents on initial power up.
1354 */
1355 for (i = 0; i < sc->keymax; i++)
1356 ath9k_hw_keyreset(ah, (u16) i);
1357
1358 if (error)
1359 goto bad;
1360
1361 /* default to MONITOR mode */
1362 sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
1363
1364 /* Setup rate tables */
1365
1366 ath_rate_attach(sc);
1367 ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1368 ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1369
1370 /*
1371 * Allocate hardware transmit queues: one queue for
1372 * beacon frames and one data queue for each QoS
1373 * priority. Note that the hal handles reseting
1374 * these queues at the needed time.
1375 */
1376 sc->beacon.beaconq = ath_beaconq_setup(ah);
1377 if (sc->beacon.beaconq == -1) {
1378 DPRINTF(sc, ATH_DBG_FATAL,
1379 "Unable to setup a beacon xmit queue\n");
1380 error = -EIO;
1381 goto bad2;
1382 }
1383 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1384 if (sc->beacon.cabq == NULL) {
1385 DPRINTF(sc, ATH_DBG_FATAL,
1386 "Unable to setup CAB xmit queue\n");
1387 error = -EIO;
1388 goto bad2;
1389 }
1390
1391 sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
1392 ath_cabq_update(sc);
1393
1394 for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1395 sc->tx.hwq_map[i] = -1;
1396
1397 /* Setup data queues */
1398 /* NB: ensure BK queue is the lowest priority h/w queue */
1399 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1400 DPRINTF(sc, ATH_DBG_FATAL,
1401 "Unable to setup xmit queue for BK traffic\n");
1402 error = -EIO;
1403 goto bad2;
1404 }
1405
1406 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1407 DPRINTF(sc, ATH_DBG_FATAL,
1408 "Unable to setup xmit queue for BE traffic\n");
1409 error = -EIO;
1410 goto bad2;
1411 }
1412 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1413 DPRINTF(sc, ATH_DBG_FATAL,
1414 "Unable to setup xmit queue for VI traffic\n");
1415 error = -EIO;
1416 goto bad2;
1417 }
1418 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1419 DPRINTF(sc, ATH_DBG_FATAL,
1420 "Unable to setup xmit queue for VO traffic\n");
1421 error = -EIO;
1422 goto bad2;
1423 }
1424
1425 /* Initializes the noise floor to a reasonable default value.
1426 * Later on this will be updated during ANI processing. */
1427
1428 sc->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1429 setup_timer(&sc->ani.timer, ath_ani_calibrate, (unsigned long)sc);
1430
1431 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1432 ATH9K_CIPHER_TKIP, NULL)) {
1433 /*
1434 * Whether we should enable h/w TKIP MIC.
1435 * XXX: if we don't support WME TKIP MIC, then we wouldn't
1436 * report WMM capable, so it's always safe to turn on
1437 * TKIP MIC in this case.
1438 */
1439 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1440 0, 1, NULL);
1441 }
1442
1443 /*
1444 * Check whether the separate key cache entries
1445 * are required to handle both tx+rx MIC keys.
1446 * With split mic keys the number of stations is limited
1447 * to 27 otherwise 59.
1448 */
1449 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1450 ATH9K_CIPHER_TKIP, NULL)
1451 && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1452 ATH9K_CIPHER_MIC, NULL)
1453 && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1454 0, NULL))
1455 sc->splitmic = 1;
1456
1457 /* turn on mcast key search if possible */
1458 if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1459 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1460 1, NULL);
1461
1462 sc->config.txpowlimit = ATH_TXPOWER_MAX;
1463
1464 /* 11n Capabilities */
1465 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1466 sc->sc_flags |= SC_OP_TXAGGR;
1467 sc->sc_flags |= SC_OP_RXAGGR;
1468 }
1469
1470 sc->tx_chainmask = ah->caps.tx_chainmask;
1471 sc->rx_chainmask = ah->caps.rx_chainmask;
1472
1473 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
1474 sc->rx.defant = ath9k_hw_getdefantenna(ah);
1475
1476 if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
1477 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
1478
1479 sc->beacon.slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
1480
1481 /* initialize beacon slots */
1482 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
1483 sc->beacon.bslot[i] = NULL;
1484 sc->beacon.bslot_aphy[i] = NULL;
1485 }
1486
1487 /* setup channels and rates */
1488
1489 sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
1490 sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1491 sc->rates[IEEE80211_BAND_2GHZ];
1492 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
1493 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1494 ARRAY_SIZE(ath9k_2ghz_chantable);
1495
1496 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
1497 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
1498 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1499 sc->rates[IEEE80211_BAND_5GHZ];
1500 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
1501 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1502 ARRAY_SIZE(ath9k_5ghz_chantable);
1503 }
1504
1505 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)
1506 ath9k_hw_btcoex_enable(sc->sc_ah);
1507
1508 return 0;
1509 bad2:
1510 /* cleanup tx queues */
1511 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1512 if (ATH_TXQ_SETUP(sc, i))
1513 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1514 bad:
1515 if (ah)
1516 ath9k_hw_detach(ah);
1517 ath9k_exit_debug(sc);
1518
1519 return error;
1520 }
1521
1522 void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
1523 {
1524 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1525 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1526 IEEE80211_HW_SIGNAL_DBM |
1527 IEEE80211_HW_AMPDU_AGGREGATION |
1528 IEEE80211_HW_SUPPORTS_PS |
1529 IEEE80211_HW_PS_NULLFUNC_STACK |
1530 IEEE80211_HW_SPECTRUM_MGMT;
1531
1532 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
1533 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1534
1535 hw->wiphy->interface_modes =
1536 BIT(NL80211_IFTYPE_AP) |
1537 BIT(NL80211_IFTYPE_STATION) |
1538 BIT(NL80211_IFTYPE_ADHOC) |
1539 BIT(NL80211_IFTYPE_MESH_POINT);
1540
1541 hw->queues = 4;
1542 hw->max_rates = 4;
1543 hw->channel_change_time = 5000;
1544 hw->max_listen_interval = 10;
1545 /* Hardware supports 10 but we use 4 */
1546 hw->max_rate_tries = 4;
1547 hw->sta_data_size = sizeof(struct ath_node);
1548 hw->vif_data_size = sizeof(struct ath_vif);
1549
1550 hw->rate_control_algorithm = "ath9k_rate_control";
1551
1552 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
1553 &sc->sbands[IEEE80211_BAND_2GHZ];
1554 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1555 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1556 &sc->sbands[IEEE80211_BAND_5GHZ];
1557 }
1558
1559 int ath_attach(u16 devid, struct ath_softc *sc)
1560 {
1561 struct ieee80211_hw *hw = sc->hw;
1562 int error = 0, i;
1563 struct ath_regulatory *reg;
1564
1565 DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
1566
1567 error = ath_init(devid, sc);
1568 if (error != 0)
1569 return error;
1570
1571 /* get mac address from hardware and set in mac80211 */
1572
1573 SET_IEEE80211_PERM_ADDR(hw, sc->sc_ah->macaddr);
1574
1575 ath_set_hw_capab(sc, hw);
1576
1577 error = ath_regd_init(&sc->sc_ah->regulatory, sc->hw->wiphy,
1578 ath9k_reg_notifier);
1579 if (error)
1580 return error;
1581
1582 reg = &sc->sc_ah->regulatory;
1583
1584 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1585 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
1586 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1587 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
1588 }
1589
1590 /* initialize tx/rx engine */
1591 error = ath_tx_init(sc, ATH_TXBUF);
1592 if (error != 0)
1593 goto error_attach;
1594
1595 error = ath_rx_init(sc, ATH_RXBUF);
1596 if (error != 0)
1597 goto error_attach;
1598
1599 INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
1600 INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work);
1601 sc->wiphy_scheduler_int = msecs_to_jiffies(500);
1602
1603 error = ieee80211_register_hw(hw);
1604
1605 if (!ath_is_world_regd(reg)) {
1606 error = regulatory_hint(hw->wiphy, reg->alpha2);
1607 if (error)
1608 goto error_attach;
1609 }
1610
1611 /* Initialize LED control */
1612 ath_init_leds(sc);
1613
1614 ath_start_rfkill_poll(sc);
1615
1616 return 0;
1617
1618 error_attach:
1619 /* cleanup tx queues */
1620 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1621 if (ATH_TXQ_SETUP(sc, i))
1622 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1623
1624 ath9k_hw_detach(sc->sc_ah);
1625 ath9k_exit_debug(sc);
1626
1627 return error;
1628 }
1629
1630 int ath_reset(struct ath_softc *sc, bool retry_tx)
1631 {
1632 struct ath_hw *ah = sc->sc_ah;
1633 struct ieee80211_hw *hw = sc->hw;
1634 int r;
1635
1636 ath9k_hw_set_interrupts(ah, 0);
1637 ath_drain_all_txq(sc, retry_tx);
1638 ath_stoprecv(sc);
1639 ath_flushrecv(sc);
1640
1641 spin_lock_bh(&sc->sc_resetlock);
1642 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
1643 if (r)
1644 DPRINTF(sc, ATH_DBG_FATAL,
1645 "Unable to reset hardware; reset status %d\n", r);
1646 spin_unlock_bh(&sc->sc_resetlock);
1647
1648 if (ath_startrecv(sc) != 0)
1649 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
1650
1651 /*
1652 * We may be doing a reset in response to a request
1653 * that changes the channel so update any state that
1654 * might change as a result.
1655 */
1656 ath_cache_conf_rate(sc, &hw->conf);
1657
1658 ath_update_txpow(sc);
1659
1660 if (sc->sc_flags & SC_OP_BEACONS)
1661 ath_beacon_config(sc, NULL); /* restart beacons */
1662
1663 ath9k_hw_set_interrupts(ah, sc->imask);
1664
1665 if (retry_tx) {
1666 int i;
1667 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1668 if (ATH_TXQ_SETUP(sc, i)) {
1669 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1670 ath_txq_schedule(sc, &sc->tx.txq[i]);
1671 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
1672 }
1673 }
1674 }
1675
1676 return r;
1677 }
1678
1679 /*
1680 * This function will allocate both the DMA descriptor structure, and the
1681 * buffers it contains. These are used to contain the descriptors used
1682 * by the system.
1683 */
1684 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1685 struct list_head *head, const char *name,
1686 int nbuf, int ndesc)
1687 {
1688 #define DS2PHYS(_dd, _ds) \
1689 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1690 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1691 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1692
1693 struct ath_desc *ds;
1694 struct ath_buf *bf;
1695 int i, bsize, error;
1696
1697 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1698 name, nbuf, ndesc);
1699
1700 INIT_LIST_HEAD(head);
1701 /* ath_desc must be a multiple of DWORDs */
1702 if ((sizeof(struct ath_desc) % 4) != 0) {
1703 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
1704 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1705 error = -ENOMEM;
1706 goto fail;
1707 }
1708
1709 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1710
1711 /*
1712 * Need additional DMA memory because we can't use
1713 * descriptors that cross the 4K page boundary. Assume
1714 * one skipped descriptor per 4K page.
1715 */
1716 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1717 u32 ndesc_skipped =
1718 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1719 u32 dma_len;
1720
1721 while (ndesc_skipped) {
1722 dma_len = ndesc_skipped * sizeof(struct ath_desc);
1723 dd->dd_desc_len += dma_len;
1724
1725 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1726 };
1727 }
1728
1729 /* allocate descriptors */
1730 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
1731 &dd->dd_desc_paddr, GFP_KERNEL);
1732 if (dd->dd_desc == NULL) {
1733 error = -ENOMEM;
1734 goto fail;
1735 }
1736 ds = dd->dd_desc;
1737 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
1738 name, ds, (u32) dd->dd_desc_len,
1739 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1740
1741 /* allocate buffers */
1742 bsize = sizeof(struct ath_buf) * nbuf;
1743 bf = kzalloc(bsize, GFP_KERNEL);
1744 if (bf == NULL) {
1745 error = -ENOMEM;
1746 goto fail2;
1747 }
1748 dd->dd_bufptr = bf;
1749
1750 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1751 bf->bf_desc = ds;
1752 bf->bf_daddr = DS2PHYS(dd, ds);
1753
1754 if (!(sc->sc_ah->caps.hw_caps &
1755 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1756 /*
1757 * Skip descriptor addresses which can cause 4KB
1758 * boundary crossing (addr + length) with a 32 dword
1759 * descriptor fetch.
1760 */
1761 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1762 ASSERT((caddr_t) bf->bf_desc <
1763 ((caddr_t) dd->dd_desc +
1764 dd->dd_desc_len));
1765
1766 ds += ndesc;
1767 bf->bf_desc = ds;
1768 bf->bf_daddr = DS2PHYS(dd, ds);
1769 }
1770 }
1771 list_add_tail(&bf->list, head);
1772 }
1773 return 0;
1774 fail2:
1775 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1776 dd->dd_desc_paddr);
1777 fail:
1778 memset(dd, 0, sizeof(*dd));
1779 return error;
1780 #undef ATH_DESC_4KB_BOUND_CHECK
1781 #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1782 #undef DS2PHYS
1783 }
1784
1785 void ath_descdma_cleanup(struct ath_softc *sc,
1786 struct ath_descdma *dd,
1787 struct list_head *head)
1788 {
1789 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1790 dd->dd_desc_paddr);
1791
1792 INIT_LIST_HEAD(head);
1793 kfree(dd->dd_bufptr);
1794 memset(dd, 0, sizeof(*dd));
1795 }
1796
1797 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1798 {
1799 int qnum;
1800
1801 switch (queue) {
1802 case 0:
1803 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
1804 break;
1805 case 1:
1806 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
1807 break;
1808 case 2:
1809 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1810 break;
1811 case 3:
1812 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
1813 break;
1814 default:
1815 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1816 break;
1817 }
1818
1819 return qnum;
1820 }
1821
1822 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1823 {
1824 int qnum;
1825
1826 switch (queue) {
1827 case ATH9K_WME_AC_VO:
1828 qnum = 0;
1829 break;
1830 case ATH9K_WME_AC_VI:
1831 qnum = 1;
1832 break;
1833 case ATH9K_WME_AC_BE:
1834 qnum = 2;
1835 break;
1836 case ATH9K_WME_AC_BK:
1837 qnum = 3;
1838 break;
1839 default:
1840 qnum = -1;
1841 break;
1842 }
1843
1844 return qnum;
1845 }
1846
1847 /* XXX: Remove me once we don't depend on ath9k_channel for all
1848 * this redundant data */
1849 void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
1850 struct ath9k_channel *ichan)
1851 {
1852 struct ieee80211_channel *chan = hw->conf.channel;
1853 struct ieee80211_conf *conf = &hw->conf;
1854
1855 ichan->channel = chan->center_freq;
1856 ichan->chan = chan;
1857
1858 if (chan->band == IEEE80211_BAND_2GHZ) {
1859 ichan->chanmode = CHANNEL_G;
1860 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM;
1861 } else {
1862 ichan->chanmode = CHANNEL_A;
1863 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
1864 }
1865
1866 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
1867
1868 if (conf_is_ht(conf)) {
1869 if (conf_is_ht40(conf))
1870 sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
1871
1872 ichan->chanmode = ath_get_extchanmode(sc, chan,
1873 conf->channel_type);
1874 }
1875 }
1876
1877 /**********************/
1878 /* mac80211 callbacks */
1879 /**********************/
1880
1881 static int ath9k_start(struct ieee80211_hw *hw)
1882 {
1883 struct ath_wiphy *aphy = hw->priv;
1884 struct ath_softc *sc = aphy->sc;
1885 struct ieee80211_channel *curchan = hw->conf.channel;
1886 struct ath9k_channel *init_channel;
1887 int r;
1888
1889 DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1890 "initial channel: %d MHz\n", curchan->center_freq);
1891
1892 mutex_lock(&sc->mutex);
1893
1894 if (ath9k_wiphy_started(sc)) {
1895 if (sc->chan_idx == curchan->hw_value) {
1896 /*
1897 * Already on the operational channel, the new wiphy
1898 * can be marked active.
1899 */
1900 aphy->state = ATH_WIPHY_ACTIVE;
1901 ieee80211_wake_queues(hw);
1902 } else {
1903 /*
1904 * Another wiphy is on another channel, start the new
1905 * wiphy in paused state.
1906 */
1907 aphy->state = ATH_WIPHY_PAUSED;
1908 ieee80211_stop_queues(hw);
1909 }
1910 mutex_unlock(&sc->mutex);
1911 return 0;
1912 }
1913 aphy->state = ATH_WIPHY_ACTIVE;
1914
1915 /* setup initial channel */
1916
1917 sc->chan_idx = curchan->hw_value;
1918
1919 init_channel = ath_get_curchannel(sc, hw);
1920
1921 /* Reset SERDES registers */
1922 ath9k_hw_configpcipowersave(sc->sc_ah, 0);
1923
1924 /*
1925 * The basic interface to setting the hardware in a good
1926 * state is ``reset''. On return the hardware is known to
1927 * be powered up and with interrupts disabled. This must
1928 * be followed by initialization of the appropriate bits
1929 * and then setup of the interrupt mask.
1930 */
1931 spin_lock_bh(&sc->sc_resetlock);
1932 r = ath9k_hw_reset(sc->sc_ah, init_channel, false);
1933 if (r) {
1934 DPRINTF(sc, ATH_DBG_FATAL,
1935 "Unable to reset hardware; reset status %d "
1936 "(freq %u MHz)\n", r,
1937 curchan->center_freq);
1938 spin_unlock_bh(&sc->sc_resetlock);
1939 goto mutex_unlock;
1940 }
1941 spin_unlock_bh(&sc->sc_resetlock);
1942
1943 /*
1944 * This is needed only to setup initial state
1945 * but it's best done after a reset.
1946 */
1947 ath_update_txpow(sc);
1948
1949 /*
1950 * Setup the hardware after reset:
1951 * The receive engine is set going.
1952 * Frame transmit is handled entirely
1953 * in the frame output path; there's nothing to do
1954 * here except setup the interrupt mask.
1955 */
1956 if (ath_startrecv(sc) != 0) {
1957 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
1958 r = -EIO;
1959 goto mutex_unlock;
1960 }
1961
1962 /* Setup our intr mask. */
1963 sc->imask = ATH9K_INT_RX | ATH9K_INT_TX
1964 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
1965 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
1966
1967 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
1968 sc->imask |= ATH9K_INT_GTT;
1969
1970 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
1971 sc->imask |= ATH9K_INT_CST;
1972
1973 ath_cache_conf_rate(sc, &hw->conf);
1974
1975 sc->sc_flags &= ~SC_OP_INVALID;
1976
1977 /* Disable BMISS interrupt when we're not associated */
1978 sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
1979 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
1980
1981 ieee80211_wake_queues(hw);
1982
1983 queue_delayed_work(sc->hw->workqueue, &sc->tx_complete_work, 0);
1984
1985 mutex_unlock:
1986 mutex_unlock(&sc->mutex);
1987
1988 return r;
1989 }
1990
1991 static int ath9k_tx(struct ieee80211_hw *hw,
1992 struct sk_buff *skb)
1993 {
1994 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1995 struct ath_wiphy *aphy = hw->priv;
1996 struct ath_softc *sc = aphy->sc;
1997 struct ath_tx_control txctl;
1998 int hdrlen, padsize;
1999
2000 if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
2001 printk(KERN_DEBUG "ath9k: %s: TX in unexpected wiphy state "
2002 "%d\n", wiphy_name(hw->wiphy), aphy->state);
2003 goto exit;
2004 }
2005
2006 if (sc->hw->conf.flags & IEEE80211_CONF_PS) {
2007 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2008 /*
2009 * mac80211 does not set PM field for normal data frames, so we
2010 * need to update that based on the current PS mode.
2011 */
2012 if (ieee80211_is_data(hdr->frame_control) &&
2013 !ieee80211_is_nullfunc(hdr->frame_control) &&
2014 !ieee80211_has_pm(hdr->frame_control)) {
2015 DPRINTF(sc, ATH_DBG_PS, "Add PM=1 for a TX frame "
2016 "while in PS mode\n");
2017 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
2018 }
2019 }
2020
2021 if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
2022 /*
2023 * We are using PS-Poll and mac80211 can request TX while in
2024 * power save mode. Need to wake up hardware for the TX to be
2025 * completed and if needed, also for RX of buffered frames.
2026 */
2027 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2028 ath9k_ps_wakeup(sc);
2029 ath9k_hw_setrxabort(sc->sc_ah, 0);
2030 if (ieee80211_is_pspoll(hdr->frame_control)) {
2031 DPRINTF(sc, ATH_DBG_PS, "Sending PS-Poll to pick a "
2032 "buffered frame\n");
2033 sc->sc_flags |= SC_OP_WAIT_FOR_PSPOLL_DATA;
2034 } else {
2035 DPRINTF(sc, ATH_DBG_PS, "Wake up to complete TX\n");
2036 sc->sc_flags |= SC_OP_WAIT_FOR_TX_ACK;
2037 }
2038 /*
2039 * The actual restore operation will happen only after
2040 * the sc_flags bit is cleared. We are just dropping
2041 * the ps_usecount here.
2042 */
2043 ath9k_ps_restore(sc);
2044 }
2045
2046 memset(&txctl, 0, sizeof(struct ath_tx_control));
2047
2048 /*
2049 * As a temporary workaround, assign seq# here; this will likely need
2050 * to be cleaned up to work better with Beacon transmission and virtual
2051 * BSSes.
2052 */
2053 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2054 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2055 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2056 sc->tx.seq_no += 0x10;
2057 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2058 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
2059 }
2060
2061 /* Add the padding after the header if this is not already done */
2062 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2063 if (hdrlen & 3) {
2064 padsize = hdrlen % 4;
2065 if (skb_headroom(skb) < padsize)
2066 return -1;
2067 skb_push(skb, padsize);
2068 memmove(skb->data, skb->data + padsize, hdrlen);
2069 }
2070
2071 /* Check if a tx queue is available */
2072
2073 txctl.txq = ath_test_get_txq(sc, skb);
2074 if (!txctl.txq)
2075 goto exit;
2076
2077 DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
2078
2079 if (ath_tx_start(hw, skb, &txctl) != 0) {
2080 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
2081 goto exit;
2082 }
2083
2084 return 0;
2085 exit:
2086 dev_kfree_skb_any(skb);
2087 return 0;
2088 }
2089
2090 static void ath9k_stop(struct ieee80211_hw *hw)
2091 {
2092 struct ath_wiphy *aphy = hw->priv;
2093 struct ath_softc *sc = aphy->sc;
2094
2095 aphy->state = ATH_WIPHY_INACTIVE;
2096
2097 if (sc->sc_flags & SC_OP_INVALID) {
2098 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
2099 return;
2100 }
2101
2102 mutex_lock(&sc->mutex);
2103
2104 if (ath9k_wiphy_started(sc)) {
2105 mutex_unlock(&sc->mutex);
2106 return; /* another wiphy still in use */
2107 }
2108
2109 /* make sure h/w will not generate any interrupt
2110 * before setting the invalid flag. */
2111 ath9k_hw_set_interrupts(sc->sc_ah, 0);
2112
2113 if (!(sc->sc_flags & SC_OP_INVALID)) {
2114 ath_drain_all_txq(sc, false);
2115 ath_stoprecv(sc);
2116 ath9k_hw_phy_disable(sc->sc_ah);
2117 } else
2118 sc->rx.rxlink = NULL;
2119
2120 wiphy_rfkill_stop_polling(sc->hw->wiphy);
2121
2122 /* disable HAL and put h/w to sleep */
2123 ath9k_hw_disable(sc->sc_ah);
2124 ath9k_hw_configpcipowersave(sc->sc_ah, 1);
2125
2126 sc->sc_flags |= SC_OP_INVALID;
2127
2128 mutex_unlock(&sc->mutex);
2129
2130 DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
2131 }
2132
2133 static int ath9k_add_interface(struct ieee80211_hw *hw,
2134 struct ieee80211_if_init_conf *conf)
2135 {
2136 struct ath_wiphy *aphy = hw->priv;
2137 struct ath_softc *sc = aphy->sc;
2138 struct ath_vif *avp = (void *)conf->vif->drv_priv;
2139 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2140 int ret = 0;
2141
2142 mutex_lock(&sc->mutex);
2143
2144 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
2145 sc->nvifs > 0) {
2146 ret = -ENOBUFS;
2147 goto out;
2148 }
2149
2150 switch (conf->type) {
2151 case NL80211_IFTYPE_STATION:
2152 ic_opmode = NL80211_IFTYPE_STATION;
2153 break;
2154 case NL80211_IFTYPE_ADHOC:
2155 case NL80211_IFTYPE_AP:
2156 case NL80211_IFTYPE_MESH_POINT:
2157 if (sc->nbcnvifs >= ATH_BCBUF) {
2158 ret = -ENOBUFS;
2159 goto out;
2160 }
2161 ic_opmode = conf->type;
2162 break;
2163 default:
2164 DPRINTF(sc, ATH_DBG_FATAL,
2165 "Interface type %d not yet supported\n", conf->type);
2166 ret = -EOPNOTSUPP;
2167 goto out;
2168 }
2169
2170 DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VIF of type: %d\n", ic_opmode);
2171
2172 /* Set the VIF opmode */
2173 avp->av_opmode = ic_opmode;
2174 avp->av_bslot = -1;
2175
2176 sc->nvifs++;
2177
2178 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
2179 ath9k_set_bssid_mask(hw);
2180
2181 if (sc->nvifs > 1)
2182 goto out; /* skip global settings for secondary vif */
2183
2184 if (ic_opmode == NL80211_IFTYPE_AP) {
2185 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2186 sc->sc_flags |= SC_OP_TSF_RESET;
2187 }
2188
2189 /* Set the device opmode */
2190 sc->sc_ah->opmode = ic_opmode;
2191
2192 /*
2193 * Enable MIB interrupts when there are hardware phy counters.
2194 * Note we only do this (at the moment) for station mode.
2195 */
2196 if ((conf->type == NL80211_IFTYPE_STATION) ||
2197 (conf->type == NL80211_IFTYPE_ADHOC) ||
2198 (conf->type == NL80211_IFTYPE_MESH_POINT)) {
2199 if (ath9k_hw_phycounters(sc->sc_ah))
2200 sc->imask |= ATH9K_INT_MIB;
2201 sc->imask |= ATH9K_INT_TSFOOR;
2202 }
2203
2204 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
2205
2206 if (conf->type == NL80211_IFTYPE_AP ||
2207 conf->type == NL80211_IFTYPE_ADHOC ||
2208 conf->type == NL80211_IFTYPE_MONITOR)
2209 ath_start_ani(sc);
2210
2211 out:
2212 mutex_unlock(&sc->mutex);
2213 return ret;
2214 }
2215
2216 static void ath9k_remove_interface(struct ieee80211_hw *hw,
2217 struct ieee80211_if_init_conf *conf)
2218 {
2219 struct ath_wiphy *aphy = hw->priv;
2220 struct ath_softc *sc = aphy->sc;
2221 struct ath_vif *avp = (void *)conf->vif->drv_priv;
2222 int i;
2223
2224 DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
2225
2226 mutex_lock(&sc->mutex);
2227
2228 /* Stop ANI */
2229 del_timer_sync(&sc->ani.timer);
2230
2231 /* Reclaim beacon resources */
2232 if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
2233 (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
2234 (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
2235 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2236 ath_beacon_return(sc, avp);
2237 }
2238
2239 sc->sc_flags &= ~SC_OP_BEACONS;
2240
2241 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2242 if (sc->beacon.bslot[i] == conf->vif) {
2243 printk(KERN_DEBUG "%s: vif had allocated beacon "
2244 "slot\n", __func__);
2245 sc->beacon.bslot[i] = NULL;
2246 sc->beacon.bslot_aphy[i] = NULL;
2247 }
2248 }
2249
2250 sc->nvifs--;
2251
2252 mutex_unlock(&sc->mutex);
2253 }
2254
2255 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2256 {
2257 struct ath_wiphy *aphy = hw->priv;
2258 struct ath_softc *sc = aphy->sc;
2259 struct ieee80211_conf *conf = &hw->conf;
2260 struct ath_hw *ah = sc->sc_ah;
2261 bool all_wiphys_idle = false, disable_radio = false;
2262
2263 mutex_lock(&sc->mutex);
2264
2265 /* Leave this as the first check */
2266 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
2267
2268 spin_lock_bh(&sc->wiphy_lock);
2269 all_wiphys_idle = ath9k_all_wiphys_idle(sc);
2270 spin_unlock_bh(&sc->wiphy_lock);
2271
2272 if (conf->flags & IEEE80211_CONF_IDLE){
2273 if (all_wiphys_idle)
2274 disable_radio = true;
2275 }
2276 else if (all_wiphys_idle) {
2277 ath_radio_enable(sc);
2278 DPRINTF(sc, ATH_DBG_CONFIG,
2279 "not-idle: enabling radio\n");
2280 }
2281 }
2282
2283 if (changed & IEEE80211_CONF_CHANGE_PS) {
2284 if (conf->flags & IEEE80211_CONF_PS) {
2285 if (!(ah->caps.hw_caps &
2286 ATH9K_HW_CAP_AUTOSLEEP)) {
2287 if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
2288 sc->imask |= ATH9K_INT_TIM_TIMER;
2289 ath9k_hw_set_interrupts(sc->sc_ah,
2290 sc->imask);
2291 }
2292 ath9k_hw_setrxabort(sc->sc_ah, 1);
2293 }
2294 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
2295 } else {
2296 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
2297 if (!(ah->caps.hw_caps &
2298 ATH9K_HW_CAP_AUTOSLEEP)) {
2299 ath9k_hw_setrxabort(sc->sc_ah, 0);
2300 sc->sc_flags &= ~(SC_OP_WAIT_FOR_BEACON |
2301 SC_OP_WAIT_FOR_CAB |
2302 SC_OP_WAIT_FOR_PSPOLL_DATA |
2303 SC_OP_WAIT_FOR_TX_ACK);
2304 if (sc->imask & ATH9K_INT_TIM_TIMER) {
2305 sc->imask &= ~ATH9K_INT_TIM_TIMER;
2306 ath9k_hw_set_interrupts(sc->sc_ah,
2307 sc->imask);
2308 }
2309 }
2310 }
2311 }
2312
2313 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2314 struct ieee80211_channel *curchan = hw->conf.channel;
2315 int pos = curchan->hw_value;
2316
2317 aphy->chan_idx = pos;
2318 aphy->chan_is_ht = conf_is_ht(conf);
2319
2320 if (aphy->state == ATH_WIPHY_SCAN ||
2321 aphy->state == ATH_WIPHY_ACTIVE)
2322 ath9k_wiphy_pause_all_forced(sc, aphy);
2323 else {
2324 /*
2325 * Do not change operational channel based on a paused
2326 * wiphy changes.
2327 */
2328 goto skip_chan_change;
2329 }
2330
2331 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2332 curchan->center_freq);
2333
2334 /* XXX: remove me eventualy */
2335 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
2336
2337 ath_update_chainmask(sc, conf_is_ht(conf));
2338
2339 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
2340 DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
2341 mutex_unlock(&sc->mutex);
2342 return -EINVAL;
2343 }
2344 }
2345
2346 skip_chan_change:
2347 if (changed & IEEE80211_CONF_CHANGE_POWER)
2348 sc->config.txpowlimit = 2 * conf->power_level;
2349
2350 if (disable_radio) {
2351 DPRINTF(sc, ATH_DBG_CONFIG, "idle: disabling radio\n");
2352 ath_radio_disable(sc);
2353 }
2354
2355 mutex_unlock(&sc->mutex);
2356
2357 return 0;
2358 }
2359
2360 #define SUPPORTED_FILTERS \
2361 (FIF_PROMISC_IN_BSS | \
2362 FIF_ALLMULTI | \
2363 FIF_CONTROL | \
2364 FIF_OTHER_BSS | \
2365 FIF_BCN_PRBRESP_PROMISC | \
2366 FIF_FCSFAIL)
2367
2368 /* FIXME: sc->sc_full_reset ? */
2369 static void ath9k_configure_filter(struct ieee80211_hw *hw,
2370 unsigned int changed_flags,
2371 unsigned int *total_flags,
2372 int mc_count,
2373 struct dev_mc_list *mclist)
2374 {
2375 struct ath_wiphy *aphy = hw->priv;
2376 struct ath_softc *sc = aphy->sc;
2377 u32 rfilt;
2378
2379 changed_flags &= SUPPORTED_FILTERS;
2380 *total_flags &= SUPPORTED_FILTERS;
2381
2382 sc->rx.rxfilter = *total_flags;
2383 ath9k_ps_wakeup(sc);
2384 rfilt = ath_calcrxfilter(sc);
2385 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
2386 ath9k_ps_restore(sc);
2387
2388 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
2389 }
2390
2391 static void ath9k_sta_notify(struct ieee80211_hw *hw,
2392 struct ieee80211_vif *vif,
2393 enum sta_notify_cmd cmd,
2394 struct ieee80211_sta *sta)
2395 {
2396 struct ath_wiphy *aphy = hw->priv;
2397 struct ath_softc *sc = aphy->sc;
2398
2399 switch (cmd) {
2400 case STA_NOTIFY_ADD:
2401 ath_node_attach(sc, sta);
2402 break;
2403 case STA_NOTIFY_REMOVE:
2404 ath_node_detach(sc, sta);
2405 break;
2406 default:
2407 break;
2408 }
2409 }
2410
2411 static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
2412 const struct ieee80211_tx_queue_params *params)
2413 {
2414 struct ath_wiphy *aphy = hw->priv;
2415 struct ath_softc *sc = aphy->sc;
2416 struct ath9k_tx_queue_info qi;
2417 int ret = 0, qnum;
2418
2419 if (queue >= WME_NUM_AC)
2420 return 0;
2421
2422 mutex_lock(&sc->mutex);
2423
2424 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
2425
2426 qi.tqi_aifs = params->aifs;
2427 qi.tqi_cwmin = params->cw_min;
2428 qi.tqi_cwmax = params->cw_max;
2429 qi.tqi_burstTime = params->txop;
2430 qnum = ath_get_hal_qnum(queue, sc);
2431
2432 DPRINTF(sc, ATH_DBG_CONFIG,
2433 "Configure tx [queue/halq] [%d/%d], "
2434 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2435 queue, qnum, params->aifs, params->cw_min,
2436 params->cw_max, params->txop);
2437
2438 ret = ath_txq_update(sc, qnum, &qi);
2439 if (ret)
2440 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
2441
2442 mutex_unlock(&sc->mutex);
2443
2444 return ret;
2445 }
2446
2447 static int ath9k_set_key(struct ieee80211_hw *hw,
2448 enum set_key_cmd cmd,
2449 struct ieee80211_vif *vif,
2450 struct ieee80211_sta *sta,
2451 struct ieee80211_key_conf *key)
2452 {
2453 struct ath_wiphy *aphy = hw->priv;
2454 struct ath_softc *sc = aphy->sc;
2455 int ret = 0;
2456
2457 if (modparam_nohwcrypt)
2458 return -ENOSPC;
2459
2460 mutex_lock(&sc->mutex);
2461 ath9k_ps_wakeup(sc);
2462 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW Key\n");
2463
2464 switch (cmd) {
2465 case SET_KEY:
2466 ret = ath_key_config(sc, vif, sta, key);
2467 if (ret >= 0) {
2468 key->hw_key_idx = ret;
2469 /* push IV and Michael MIC generation to stack */
2470 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2471 if (key->alg == ALG_TKIP)
2472 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
2473 if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2474 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
2475 ret = 0;
2476 }
2477 break;
2478 case DISABLE_KEY:
2479 ath_key_delete(sc, key);
2480 break;
2481 default:
2482 ret = -EINVAL;
2483 }
2484
2485 ath9k_ps_restore(sc);
2486 mutex_unlock(&sc->mutex);
2487
2488 return ret;
2489 }
2490
2491 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2492 struct ieee80211_vif *vif,
2493 struct ieee80211_bss_conf *bss_conf,
2494 u32 changed)
2495 {
2496 struct ath_wiphy *aphy = hw->priv;
2497 struct ath_softc *sc = aphy->sc;
2498 struct ath_hw *ah = sc->sc_ah;
2499 struct ath_vif *avp = (void *)vif->drv_priv;
2500 u32 rfilt = 0;
2501 int error, i;
2502
2503 mutex_lock(&sc->mutex);
2504
2505 /*
2506 * TODO: Need to decide which hw opmode to use for
2507 * multi-interface cases
2508 * XXX: This belongs into add_interface!
2509 */
2510 if (vif->type == NL80211_IFTYPE_AP &&
2511 ah->opmode != NL80211_IFTYPE_AP) {
2512 ah->opmode = NL80211_IFTYPE_STATION;
2513 ath9k_hw_setopmode(ah);
2514 memcpy(sc->curbssid, sc->sc_ah->macaddr, ETH_ALEN);
2515 sc->curaid = 0;
2516 ath9k_hw_write_associd(sc);
2517 /* Request full reset to get hw opmode changed properly */
2518 sc->sc_flags |= SC_OP_FULL_RESET;
2519 }
2520
2521 if ((changed & BSS_CHANGED_BSSID) &&
2522 !is_zero_ether_addr(bss_conf->bssid)) {
2523 switch (vif->type) {
2524 case NL80211_IFTYPE_STATION:
2525 case NL80211_IFTYPE_ADHOC:
2526 case NL80211_IFTYPE_MESH_POINT:
2527 /* Set BSSID */
2528 memcpy(sc->curbssid, bss_conf->bssid, ETH_ALEN);
2529 memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
2530 sc->curaid = 0;
2531 ath9k_hw_write_associd(sc);
2532
2533 /* Set aggregation protection mode parameters */
2534 sc->config.ath_aggr_prot = 0;
2535
2536 DPRINTF(sc, ATH_DBG_CONFIG,
2537 "RX filter 0x%x bssid %pM aid 0x%x\n",
2538 rfilt, sc->curbssid, sc->curaid);
2539
2540 /* need to reconfigure the beacon */
2541 sc->sc_flags &= ~SC_OP_BEACONS ;
2542
2543 break;
2544 default:
2545 break;
2546 }
2547 }
2548
2549 if ((vif->type == NL80211_IFTYPE_ADHOC) ||
2550 (vif->type == NL80211_IFTYPE_AP) ||
2551 (vif->type == NL80211_IFTYPE_MESH_POINT)) {
2552 if ((changed & BSS_CHANGED_BEACON) ||
2553 (changed & BSS_CHANGED_BEACON_ENABLED &&
2554 bss_conf->enable_beacon)) {
2555 /*
2556 * Allocate and setup the beacon frame.
2557 *
2558 * Stop any previous beacon DMA. This may be
2559 * necessary, for example, when an ibss merge
2560 * causes reconfiguration; we may be called
2561 * with beacon transmission active.
2562 */
2563 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2564
2565 error = ath_beacon_alloc(aphy, vif);
2566 if (!error)
2567 ath_beacon_config(sc, vif);
2568 }
2569 }
2570
2571 /* Check for WLAN_CAPABILITY_PRIVACY ? */
2572 if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
2573 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2574 if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2575 ath9k_hw_keysetmac(sc->sc_ah,
2576 (u16)i,
2577 sc->curbssid);
2578 }
2579
2580 /* Only legacy IBSS for now */
2581 if (vif->type == NL80211_IFTYPE_ADHOC)
2582 ath_update_chainmask(sc, 0);
2583
2584 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
2585 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
2586 bss_conf->use_short_preamble);
2587 if (bss_conf->use_short_preamble)
2588 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2589 else
2590 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2591 }
2592
2593 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
2594 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
2595 bss_conf->use_cts_prot);
2596 if (bss_conf->use_cts_prot &&
2597 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2598 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2599 else
2600 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2601 }
2602
2603 if (changed & BSS_CHANGED_ASSOC) {
2604 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
2605 bss_conf->assoc);
2606 ath9k_bss_assoc_info(sc, vif, bss_conf);
2607 }
2608
2609 /*
2610 * The HW TSF has to be reset when the beacon interval changes.
2611 * We set the flag here, and ath_beacon_config_ap() would take this
2612 * into account when it gets called through the subsequent
2613 * config_interface() call - with IFCC_BEACON in the changed field.
2614 */
2615
2616 if (changed & BSS_CHANGED_BEACON_INT) {
2617 sc->sc_flags |= SC_OP_TSF_RESET;
2618 sc->beacon_interval = bss_conf->beacon_int;
2619 }
2620
2621 mutex_unlock(&sc->mutex);
2622 }
2623
2624 static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2625 {
2626 u64 tsf;
2627 struct ath_wiphy *aphy = hw->priv;
2628 struct ath_softc *sc = aphy->sc;
2629
2630 mutex_lock(&sc->mutex);
2631 tsf = ath9k_hw_gettsf64(sc->sc_ah);
2632 mutex_unlock(&sc->mutex);
2633
2634 return tsf;
2635 }
2636
2637 static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2638 {
2639 struct ath_wiphy *aphy = hw->priv;
2640 struct ath_softc *sc = aphy->sc;
2641
2642 mutex_lock(&sc->mutex);
2643 ath9k_hw_settsf64(sc->sc_ah, tsf);
2644 mutex_unlock(&sc->mutex);
2645 }
2646
2647 static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2648 {
2649 struct ath_wiphy *aphy = hw->priv;
2650 struct ath_softc *sc = aphy->sc;
2651
2652 mutex_lock(&sc->mutex);
2653 ath9k_hw_reset_tsf(sc->sc_ah);
2654 mutex_unlock(&sc->mutex);
2655 }
2656
2657 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2658 enum ieee80211_ampdu_mlme_action action,
2659 struct ieee80211_sta *sta,
2660 u16 tid, u16 *ssn)
2661 {
2662 struct ath_wiphy *aphy = hw->priv;
2663 struct ath_softc *sc = aphy->sc;
2664 int ret = 0;
2665
2666 switch (action) {
2667 case IEEE80211_AMPDU_RX_START:
2668 if (!(sc->sc_flags & SC_OP_RXAGGR))
2669 ret = -ENOTSUPP;
2670 break;
2671 case IEEE80211_AMPDU_RX_STOP:
2672 break;
2673 case IEEE80211_AMPDU_TX_START:
2674 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
2675 if (ret < 0)
2676 DPRINTF(sc, ATH_DBG_FATAL,
2677 "Unable to start TX aggregation\n");
2678 else
2679 ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2680 break;
2681 case IEEE80211_AMPDU_TX_STOP:
2682 ret = ath_tx_aggr_stop(sc, sta, tid);
2683 if (ret < 0)
2684 DPRINTF(sc, ATH_DBG_FATAL,
2685 "Unable to stop TX aggregation\n");
2686
2687 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2688 break;
2689 case IEEE80211_AMPDU_TX_OPERATIONAL:
2690 ath_tx_aggr_resume(sc, sta, tid);
2691 break;
2692 default:
2693 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
2694 }
2695
2696 return ret;
2697 }
2698
2699 static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
2700 {
2701 struct ath_wiphy *aphy = hw->priv;
2702 struct ath_softc *sc = aphy->sc;
2703
2704 if (ath9k_wiphy_scanning(sc)) {
2705 printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the "
2706 "same time\n");
2707 /*
2708 * Do not allow the concurrent scanning state for now. This
2709 * could be improved with scanning control moved into ath9k.
2710 */
2711 return;
2712 }
2713
2714 aphy->state = ATH_WIPHY_SCAN;
2715 ath9k_wiphy_pause_all_forced(sc, aphy);
2716
2717 spin_lock_bh(&sc->ani_lock);
2718 sc->sc_flags |= SC_OP_SCANNING;
2719 spin_unlock_bh(&sc->ani_lock);
2720 }
2721
2722 static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
2723 {
2724 struct ath_wiphy *aphy = hw->priv;
2725 struct ath_softc *sc = aphy->sc;
2726
2727 spin_lock_bh(&sc->ani_lock);
2728 aphy->state = ATH_WIPHY_ACTIVE;
2729 sc->sc_flags &= ~SC_OP_SCANNING;
2730 sc->sc_flags |= SC_OP_FULL_RESET;
2731 spin_unlock_bh(&sc->ani_lock);
2732 }
2733
2734 struct ieee80211_ops ath9k_ops = {
2735 .tx = ath9k_tx,
2736 .start = ath9k_start,
2737 .stop = ath9k_stop,
2738 .add_interface = ath9k_add_interface,
2739 .remove_interface = ath9k_remove_interface,
2740 .config = ath9k_config,
2741 .configure_filter = ath9k_configure_filter,
2742 .sta_notify = ath9k_sta_notify,
2743 .conf_tx = ath9k_conf_tx,
2744 .bss_info_changed = ath9k_bss_info_changed,
2745 .set_key = ath9k_set_key,
2746 .get_tsf = ath9k_get_tsf,
2747 .set_tsf = ath9k_set_tsf,
2748 .reset_tsf = ath9k_reset_tsf,
2749 .ampdu_action = ath9k_ampdu_action,
2750 .sw_scan_start = ath9k_sw_scan_start,
2751 .sw_scan_complete = ath9k_sw_scan_complete,
2752 .rfkill_poll = ath9k_rfkill_poll_state,
2753 };
2754
2755 static struct {
2756 u32 version;
2757 const char * name;
2758 } ath_mac_bb_names[] = {
2759 { AR_SREV_VERSION_5416_PCI, "5416" },
2760 { AR_SREV_VERSION_5416_PCIE, "5418" },
2761 { AR_SREV_VERSION_9100, "9100" },
2762 { AR_SREV_VERSION_9160, "9160" },
2763 { AR_SREV_VERSION_9280, "9280" },
2764 { AR_SREV_VERSION_9285, "9285" }
2765 };
2766
2767 static struct {
2768 u16 version;
2769 const char * name;
2770 } ath_rf_names[] = {
2771 { 0, "5133" },
2772 { AR_RAD5133_SREV_MAJOR, "5133" },
2773 { AR_RAD5122_SREV_MAJOR, "5122" },
2774 { AR_RAD2133_SREV_MAJOR, "2133" },
2775 { AR_RAD2122_SREV_MAJOR, "2122" }
2776 };
2777
2778 /*
2779 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2780 */
2781 const char *
2782 ath_mac_bb_name(u32 mac_bb_version)
2783 {
2784 int i;
2785
2786 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2787 if (ath_mac_bb_names[i].version == mac_bb_version) {
2788 return ath_mac_bb_names[i].name;
2789 }
2790 }
2791
2792 return "????";
2793 }
2794
2795 /*
2796 * Return the RF name. "????" is returned if the RF is unknown.
2797 */
2798 const char *
2799 ath_rf_name(u16 rf_version)
2800 {
2801 int i;
2802
2803 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2804 if (ath_rf_names[i].version == rf_version) {
2805 return ath_rf_names[i].name;
2806 }
2807 }
2808
2809 return "????";
2810 }
2811
2812 static int __init ath9k_init(void)
2813 {
2814 int error;
2815
2816 /* Register rate control algorithm */
2817 error = ath_rate_control_register();
2818 if (error != 0) {
2819 printk(KERN_ERR
2820 "ath9k: Unable to register rate control "
2821 "algorithm: %d\n",
2822 error);
2823 goto err_out;
2824 }
2825
2826 error = ath9k_debug_create_root();
2827 if (error) {
2828 printk(KERN_ERR
2829 "ath9k: Unable to create debugfs root: %d\n",
2830 error);
2831 goto err_rate_unregister;
2832 }
2833
2834 error = ath_pci_init();
2835 if (error < 0) {
2836 printk(KERN_ERR
2837 "ath9k: No PCI devices found, driver not installed.\n");
2838 error = -ENODEV;
2839 goto err_remove_root;
2840 }
2841
2842 error = ath_ahb_init();
2843 if (error < 0) {
2844 error = -ENODEV;
2845 goto err_pci_exit;
2846 }
2847
2848 return 0;
2849
2850 err_pci_exit:
2851 ath_pci_exit();
2852
2853 err_remove_root:
2854 ath9k_debug_remove_root();
2855 err_rate_unregister:
2856 ath_rate_control_unregister();
2857 err_out:
2858 return error;
2859 }
2860 module_init(ath9k_init);
2861
2862 static void __exit ath9k_exit(void)
2863 {
2864 ath_ahb_exit();
2865 ath_pci_exit();
2866 ath9k_debug_remove_root();
2867 ath_rate_control_unregister();
2868 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
2869 }
2870 module_exit(ath9k_exit);
Linux kernel - Deliverables
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