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ath9k: cleanup try count for MRR in rate control
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / main.c
1 /*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/nl80211.h>
18 #include "ath9k.h"
19
20 #define ATH_PCI_VERSION "0.1"
21
22 static char *dev_info = "ath9k";
23
24 MODULE_AUTHOR("Atheros Communications");
25 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
26 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
27 MODULE_LICENSE("Dual BSD/GPL");
28
29 static int modparam_nohwcrypt;
30 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
31 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
32
33 /* We use the hw_value as an index into our private channel structure */
34
35 #define CHAN2G(_freq, _idx) { \
36 .center_freq = (_freq), \
37 .hw_value = (_idx), \
38 .max_power = 20, \
39 }
40
41 #define CHAN5G(_freq, _idx) { \
42 .band = IEEE80211_BAND_5GHZ, \
43 .center_freq = (_freq), \
44 .hw_value = (_idx), \
45 .max_power = 20, \
46 }
47
48 /* Some 2 GHz radios are actually tunable on 2312-2732
49 * on 5 MHz steps, we support the channels which we know
50 * we have calibration data for all cards though to make
51 * this static */
52 static struct ieee80211_channel ath9k_2ghz_chantable[] = {
53 CHAN2G(2412, 0), /* Channel 1 */
54 CHAN2G(2417, 1), /* Channel 2 */
55 CHAN2G(2422, 2), /* Channel 3 */
56 CHAN2G(2427, 3), /* Channel 4 */
57 CHAN2G(2432, 4), /* Channel 5 */
58 CHAN2G(2437, 5), /* Channel 6 */
59 CHAN2G(2442, 6), /* Channel 7 */
60 CHAN2G(2447, 7), /* Channel 8 */
61 CHAN2G(2452, 8), /* Channel 9 */
62 CHAN2G(2457, 9), /* Channel 10 */
63 CHAN2G(2462, 10), /* Channel 11 */
64 CHAN2G(2467, 11), /* Channel 12 */
65 CHAN2G(2472, 12), /* Channel 13 */
66 CHAN2G(2484, 13), /* Channel 14 */
67 };
68
69 /* Some 5 GHz radios are actually tunable on XXXX-YYYY
70 * on 5 MHz steps, we support the channels which we know
71 * we have calibration data for all cards though to make
72 * this static */
73 static struct ieee80211_channel ath9k_5ghz_chantable[] = {
74 /* _We_ call this UNII 1 */
75 CHAN5G(5180, 14), /* Channel 36 */
76 CHAN5G(5200, 15), /* Channel 40 */
77 CHAN5G(5220, 16), /* Channel 44 */
78 CHAN5G(5240, 17), /* Channel 48 */
79 /* _We_ call this UNII 2 */
80 CHAN5G(5260, 18), /* Channel 52 */
81 CHAN5G(5280, 19), /* Channel 56 */
82 CHAN5G(5300, 20), /* Channel 60 */
83 CHAN5G(5320, 21), /* Channel 64 */
84 /* _We_ call this "Middle band" */
85 CHAN5G(5500, 22), /* Channel 100 */
86 CHAN5G(5520, 23), /* Channel 104 */
87 CHAN5G(5540, 24), /* Channel 108 */
88 CHAN5G(5560, 25), /* Channel 112 */
89 CHAN5G(5580, 26), /* Channel 116 */
90 CHAN5G(5600, 27), /* Channel 120 */
91 CHAN5G(5620, 28), /* Channel 124 */
92 CHAN5G(5640, 29), /* Channel 128 */
93 CHAN5G(5660, 30), /* Channel 132 */
94 CHAN5G(5680, 31), /* Channel 136 */
95 CHAN5G(5700, 32), /* Channel 140 */
96 /* _We_ call this UNII 3 */
97 CHAN5G(5745, 33), /* Channel 149 */
98 CHAN5G(5765, 34), /* Channel 153 */
99 CHAN5G(5785, 35), /* Channel 157 */
100 CHAN5G(5805, 36), /* Channel 161 */
101 CHAN5G(5825, 37), /* Channel 165 */
102 };
103
104 static void ath_cache_conf_rate(struct ath_softc *sc,
105 struct ieee80211_conf *conf)
106 {
107 switch (conf->channel->band) {
108 case IEEE80211_BAND_2GHZ:
109 if (conf_is_ht20(conf))
110 sc->cur_rate_table =
111 sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
112 else if (conf_is_ht40_minus(conf))
113 sc->cur_rate_table =
114 sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
115 else if (conf_is_ht40_plus(conf))
116 sc->cur_rate_table =
117 sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
118 else
119 sc->cur_rate_table =
120 sc->hw_rate_table[ATH9K_MODE_11G];
121 break;
122 case IEEE80211_BAND_5GHZ:
123 if (conf_is_ht20(conf))
124 sc->cur_rate_table =
125 sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
126 else if (conf_is_ht40_minus(conf))
127 sc->cur_rate_table =
128 sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
129 else if (conf_is_ht40_plus(conf))
130 sc->cur_rate_table =
131 sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
132 else
133 sc->cur_rate_table =
134 sc->hw_rate_table[ATH9K_MODE_11A];
135 break;
136 default:
137 BUG_ON(1);
138 break;
139 }
140 }
141
142 static void ath_update_txpow(struct ath_softc *sc)
143 {
144 struct ath_hw *ah = sc->sc_ah;
145 u32 txpow;
146
147 if (sc->curtxpow != sc->config.txpowlimit) {
148 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
149 /* read back in case value is clamped */
150 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
151 sc->curtxpow = txpow;
152 }
153 }
154
155 static u8 parse_mpdudensity(u8 mpdudensity)
156 {
157 /*
158 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
159 * 0 for no restriction
160 * 1 for 1/4 us
161 * 2 for 1/2 us
162 * 3 for 1 us
163 * 4 for 2 us
164 * 5 for 4 us
165 * 6 for 8 us
166 * 7 for 16 us
167 */
168 switch (mpdudensity) {
169 case 0:
170 return 0;
171 case 1:
172 case 2:
173 case 3:
174 /* Our lower layer calculations limit our precision to
175 1 microsecond */
176 return 1;
177 case 4:
178 return 2;
179 case 5:
180 return 4;
181 case 6:
182 return 8;
183 case 7:
184 return 16;
185 default:
186 return 0;
187 }
188 }
189
190 static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
191 {
192 const struct ath_rate_table *rate_table = NULL;
193 struct ieee80211_supported_band *sband;
194 struct ieee80211_rate *rate;
195 int i, maxrates;
196
197 switch (band) {
198 case IEEE80211_BAND_2GHZ:
199 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
200 break;
201 case IEEE80211_BAND_5GHZ:
202 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
203 break;
204 default:
205 break;
206 }
207
208 if (rate_table == NULL)
209 return;
210
211 sband = &sc->sbands[band];
212 rate = sc->rates[band];
213
214 if (rate_table->rate_cnt > ATH_RATE_MAX)
215 maxrates = ATH_RATE_MAX;
216 else
217 maxrates = rate_table->rate_cnt;
218
219 for (i = 0; i < maxrates; i++) {
220 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
221 rate[i].hw_value = rate_table->info[i].ratecode;
222 if (rate_table->info[i].short_preamble) {
223 rate[i].hw_value_short = rate_table->info[i].ratecode |
224 rate_table->info[i].short_preamble;
225 rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE;
226 }
227 sband->n_bitrates++;
228
229 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
230 rate[i].bitrate / 10, rate[i].hw_value);
231 }
232 }
233
234 static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc,
235 struct ieee80211_hw *hw)
236 {
237 struct ieee80211_channel *curchan = hw->conf.channel;
238 struct ath9k_channel *channel;
239 u8 chan_idx;
240
241 chan_idx = curchan->hw_value;
242 channel = &sc->sc_ah->channels[chan_idx];
243 ath9k_update_ichannel(sc, hw, channel);
244 return channel;
245 }
246
247 /*
248 * Set/change channels. If the channel is really being changed, it's done
249 * by reseting the chip. To accomplish this we must first cleanup any pending
250 * DMA, then restart stuff.
251 */
252 int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
253 struct ath9k_channel *hchan)
254 {
255 struct ath_hw *ah = sc->sc_ah;
256 bool fastcc = true, stopped;
257 struct ieee80211_channel *channel = hw->conf.channel;
258 int r;
259
260 if (sc->sc_flags & SC_OP_INVALID)
261 return -EIO;
262
263 ath9k_ps_wakeup(sc);
264
265 /*
266 * This is only performed if the channel settings have
267 * actually changed.
268 *
269 * To switch channels clear any pending DMA operations;
270 * wait long enough for the RX fifo to drain, reset the
271 * hardware at the new frequency, and then re-enable
272 * the relevant bits of the h/w.
273 */
274 ath9k_hw_set_interrupts(ah, 0);
275 ath_drain_all_txq(sc, false);
276 stopped = ath_stoprecv(sc);
277
278 /* XXX: do not flush receive queue here. We don't want
279 * to flush data frames already in queue because of
280 * changing channel. */
281
282 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
283 fastcc = false;
284
285 DPRINTF(sc, ATH_DBG_CONFIG,
286 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
287 sc->sc_ah->curchan->channel,
288 channel->center_freq, sc->tx_chan_width);
289
290 spin_lock_bh(&sc->sc_resetlock);
291
292 r = ath9k_hw_reset(ah, hchan, fastcc);
293 if (r) {
294 DPRINTF(sc, ATH_DBG_FATAL,
295 "Unable to reset channel (%u Mhz) "
296 "reset status %d\n",
297 channel->center_freq, r);
298 spin_unlock_bh(&sc->sc_resetlock);
299 goto ps_restore;
300 }
301 spin_unlock_bh(&sc->sc_resetlock);
302
303 sc->sc_flags &= ~SC_OP_FULL_RESET;
304
305 if (ath_startrecv(sc) != 0) {
306 DPRINTF(sc, ATH_DBG_FATAL,
307 "Unable to restart recv logic\n");
308 r = -EIO;
309 goto ps_restore;
310 }
311
312 ath_cache_conf_rate(sc, &hw->conf);
313 ath_update_txpow(sc);
314 ath9k_hw_set_interrupts(ah, sc->imask);
315
316 ps_restore:
317 ath9k_ps_restore(sc);
318 return r;
319 }
320
321 /*
322 * This routine performs the periodic noise floor calibration function
323 * that is used to adjust and optimize the chip performance. This
324 * takes environmental changes (location, temperature) into account.
325 * When the task is complete, it reschedules itself depending on the
326 * appropriate interval that was calculated.
327 */
328 static void ath_ani_calibrate(unsigned long data)
329 {
330 struct ath_softc *sc = (struct ath_softc *)data;
331 struct ath_hw *ah = sc->sc_ah;
332 bool longcal = false;
333 bool shortcal = false;
334 bool aniflag = false;
335 unsigned int timestamp = jiffies_to_msecs(jiffies);
336 u32 cal_interval, short_cal_interval;
337
338 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
339 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
340
341 /*
342 * don't calibrate when we're scanning.
343 * we are most likely not on our home channel.
344 */
345 spin_lock(&sc->ani_lock);
346 if (sc->sc_flags & SC_OP_SCANNING)
347 goto set_timer;
348
349 /* Only calibrate if awake */
350 if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
351 goto set_timer;
352
353 ath9k_ps_wakeup(sc);
354
355 /* Long calibration runs independently of short calibration. */
356 if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
357 longcal = true;
358 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
359 sc->ani.longcal_timer = timestamp;
360 }
361
362 /* Short calibration applies only while caldone is false */
363 if (!sc->ani.caldone) {
364 if ((timestamp - sc->ani.shortcal_timer) >= short_cal_interval) {
365 shortcal = true;
366 DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
367 sc->ani.shortcal_timer = timestamp;
368 sc->ani.resetcal_timer = timestamp;
369 }
370 } else {
371 if ((timestamp - sc->ani.resetcal_timer) >=
372 ATH_RESTART_CALINTERVAL) {
373 sc->ani.caldone = ath9k_hw_reset_calvalid(ah);
374 if (sc->ani.caldone)
375 sc->ani.resetcal_timer = timestamp;
376 }
377 }
378
379 /* Verify whether we must check ANI */
380 if ((timestamp - sc->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
381 aniflag = true;
382 sc->ani.checkani_timer = timestamp;
383 }
384
385 /* Skip all processing if there's nothing to do. */
386 if (longcal || shortcal || aniflag) {
387 /* Call ANI routine if necessary */
388 if (aniflag)
389 ath9k_hw_ani_monitor(ah, &sc->nodestats, ah->curchan);
390
391 /* Perform calibration if necessary */
392 if (longcal || shortcal) {
393 sc->ani.caldone = ath9k_hw_calibrate(ah, ah->curchan,
394 sc->rx_chainmask, longcal);
395
396 if (longcal)
397 sc->ani.noise_floor = ath9k_hw_getchan_noise(ah,
398 ah->curchan);
399
400 DPRINTF(sc, ATH_DBG_ANI," calibrate chan %u/%x nf: %d\n",
401 ah->curchan->channel, ah->curchan->channelFlags,
402 sc->ani.noise_floor);
403 }
404 }
405
406 ath9k_ps_restore(sc);
407
408 set_timer:
409 spin_unlock(&sc->ani_lock);
410 /*
411 * Set timer interval based on previous results.
412 * The interval must be the shortest necessary to satisfy ANI,
413 * short calibration and long calibration.
414 */
415 cal_interval = ATH_LONG_CALINTERVAL;
416 if (sc->sc_ah->config.enable_ani)
417 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
418 if (!sc->ani.caldone)
419 cal_interval = min(cal_interval, (u32)short_cal_interval);
420
421 mod_timer(&sc->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
422 }
423
424 static void ath_start_ani(struct ath_softc *sc)
425 {
426 unsigned long timestamp = jiffies_to_msecs(jiffies);
427
428 sc->ani.longcal_timer = timestamp;
429 sc->ani.shortcal_timer = timestamp;
430 sc->ani.checkani_timer = timestamp;
431
432 mod_timer(&sc->ani.timer,
433 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
434 }
435
436 /*
437 * Update tx/rx chainmask. For legacy association,
438 * hard code chainmask to 1x1, for 11n association, use
439 * the chainmask configuration, for bt coexistence, use
440 * the chainmask configuration even in legacy mode.
441 */
442 void ath_update_chainmask(struct ath_softc *sc, int is_ht)
443 {
444 if (is_ht ||
445 (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)) {
446 sc->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
447 sc->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
448 } else {
449 sc->tx_chainmask = 1;
450 sc->rx_chainmask = 1;
451 }
452
453 DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
454 sc->tx_chainmask, sc->rx_chainmask);
455 }
456
457 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
458 {
459 struct ath_node *an;
460
461 an = (struct ath_node *)sta->drv_priv;
462
463 if (sc->sc_flags & SC_OP_TXAGGR) {
464 ath_tx_node_init(sc, an);
465 an->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
466 sta->ht_cap.ampdu_factor);
467 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
468 }
469 }
470
471 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
472 {
473 struct ath_node *an = (struct ath_node *)sta->drv_priv;
474
475 if (sc->sc_flags & SC_OP_TXAGGR)
476 ath_tx_node_cleanup(sc, an);
477 }
478
479 static void ath9k_tasklet(unsigned long data)
480 {
481 struct ath_softc *sc = (struct ath_softc *)data;
482 u32 status = sc->intrstatus;
483
484 ath9k_ps_wakeup(sc);
485
486 if (status & ATH9K_INT_FATAL) {
487 ath_reset(sc, false);
488 ath9k_ps_restore(sc);
489 return;
490 }
491
492 if (status & (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
493 spin_lock_bh(&sc->rx.rxflushlock);
494 ath_rx_tasklet(sc, 0);
495 spin_unlock_bh(&sc->rx.rxflushlock);
496 }
497
498 if (status & ATH9K_INT_TX)
499 ath_tx_tasklet(sc);
500
501 if ((status & ATH9K_INT_TSFOOR) &&
502 (sc->hw->conf.flags & IEEE80211_CONF_PS)) {
503 /*
504 * TSF sync does not look correct; remain awake to sync with
505 * the next Beacon.
506 */
507 DPRINTF(sc, ATH_DBG_PS, "TSFOOR - Sync with next Beacon\n");
508 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON | SC_OP_BEACON_SYNC;
509 }
510
511 /* re-enable hardware interrupt */
512 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
513 ath9k_ps_restore(sc);
514 }
515
516 irqreturn_t ath_isr(int irq, void *dev)
517 {
518 #define SCHED_INTR ( \
519 ATH9K_INT_FATAL | \
520 ATH9K_INT_RXORN | \
521 ATH9K_INT_RXEOL | \
522 ATH9K_INT_RX | \
523 ATH9K_INT_TX | \
524 ATH9K_INT_BMISS | \
525 ATH9K_INT_CST | \
526 ATH9K_INT_TSFOOR)
527
528 struct ath_softc *sc = dev;
529 struct ath_hw *ah = sc->sc_ah;
530 enum ath9k_int status;
531 bool sched = false;
532
533 /*
534 * The hardware is not ready/present, don't
535 * touch anything. Note this can happen early
536 * on if the IRQ is shared.
537 */
538 if (sc->sc_flags & SC_OP_INVALID)
539 return IRQ_NONE;
540
541
542 /* shared irq, not for us */
543
544 if (!ath9k_hw_intrpend(ah))
545 return IRQ_NONE;
546
547 /*
548 * Figure out the reason(s) for the interrupt. Note
549 * that the hal returns a pseudo-ISR that may include
550 * bits we haven't explicitly enabled so we mask the
551 * value to insure we only process bits we requested.
552 */
553 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
554 status &= sc->imask; /* discard unasked-for bits */
555
556 /*
557 * If there are no status bits set, then this interrupt was not
558 * for me (should have been caught above).
559 */
560 if (!status)
561 return IRQ_NONE;
562
563 /* Cache the status */
564 sc->intrstatus = status;
565
566 if (status & SCHED_INTR)
567 sched = true;
568
569 /*
570 * If a FATAL or RXORN interrupt is received, we have to reset the
571 * chip immediately.
572 */
573 if (status & (ATH9K_INT_FATAL | ATH9K_INT_RXORN))
574 goto chip_reset;
575
576 if (status & ATH9K_INT_SWBA)
577 tasklet_schedule(&sc->bcon_tasklet);
578
579 if (status & ATH9K_INT_TXURN)
580 ath9k_hw_updatetxtriglevel(ah, true);
581
582 if (status & ATH9K_INT_MIB) {
583 /*
584 * Disable interrupts until we service the MIB
585 * interrupt; otherwise it will continue to
586 * fire.
587 */
588 ath9k_hw_set_interrupts(ah, 0);
589 /*
590 * Let the hal handle the event. We assume
591 * it will clear whatever condition caused
592 * the interrupt.
593 */
594 ath9k_hw_procmibevent(ah, &sc->nodestats);
595 ath9k_hw_set_interrupts(ah, sc->imask);
596 }
597
598 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
599 if (status & ATH9K_INT_TIM_TIMER) {
600 /* Clear RxAbort bit so that we can
601 * receive frames */
602 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
603 ath9k_hw_setrxabort(sc->sc_ah, 0);
604 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
605 }
606
607 chip_reset:
608
609 ath_debug_stat_interrupt(sc, status);
610
611 if (sched) {
612 /* turn off every interrupt except SWBA */
613 ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA));
614 tasklet_schedule(&sc->intr_tq);
615 }
616
617 return IRQ_HANDLED;
618
619 #undef SCHED_INTR
620 }
621
622 static u32 ath_get_extchanmode(struct ath_softc *sc,
623 struct ieee80211_channel *chan,
624 enum nl80211_channel_type channel_type)
625 {
626 u32 chanmode = 0;
627
628 switch (chan->band) {
629 case IEEE80211_BAND_2GHZ:
630 switch(channel_type) {
631 case NL80211_CHAN_NO_HT:
632 case NL80211_CHAN_HT20:
633 chanmode = CHANNEL_G_HT20;
634 break;
635 case NL80211_CHAN_HT40PLUS:
636 chanmode = CHANNEL_G_HT40PLUS;
637 break;
638 case NL80211_CHAN_HT40MINUS:
639 chanmode = CHANNEL_G_HT40MINUS;
640 break;
641 }
642 break;
643 case IEEE80211_BAND_5GHZ:
644 switch(channel_type) {
645 case NL80211_CHAN_NO_HT:
646 case NL80211_CHAN_HT20:
647 chanmode = CHANNEL_A_HT20;
648 break;
649 case NL80211_CHAN_HT40PLUS:
650 chanmode = CHANNEL_A_HT40PLUS;
651 break;
652 case NL80211_CHAN_HT40MINUS:
653 chanmode = CHANNEL_A_HT40MINUS;
654 break;
655 }
656 break;
657 default:
658 break;
659 }
660
661 return chanmode;
662 }
663
664 static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
665 struct ath9k_keyval *hk, const u8 *addr,
666 bool authenticator)
667 {
668 const u8 *key_rxmic;
669 const u8 *key_txmic;
670
671 key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
672 key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
673
674 if (addr == NULL) {
675 /*
676 * Group key installation - only two key cache entries are used
677 * regardless of splitmic capability since group key is only
678 * used either for TX or RX.
679 */
680 if (authenticator) {
681 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
682 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
683 } else {
684 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
685 memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
686 }
687 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
688 }
689 if (!sc->splitmic) {
690 /* TX and RX keys share the same key cache entry. */
691 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
692 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
693 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
694 }
695
696 /* Separate key cache entries for TX and RX */
697
698 /* TX key goes at first index, RX key at +32. */
699 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
700 if (!ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, NULL)) {
701 /* TX MIC entry failed. No need to proceed further */
702 DPRINTF(sc, ATH_DBG_FATAL,
703 "Setting TX MIC Key Failed\n");
704 return 0;
705 }
706
707 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
708 /* XXX delete tx key on failure? */
709 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix + 32, hk, addr);
710 }
711
712 static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
713 {
714 int i;
715
716 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
717 if (test_bit(i, sc->keymap) ||
718 test_bit(i + 64, sc->keymap))
719 continue; /* At least one part of TKIP key allocated */
720 if (sc->splitmic &&
721 (test_bit(i + 32, sc->keymap) ||
722 test_bit(i + 64 + 32, sc->keymap)))
723 continue; /* At least one part of TKIP key allocated */
724
725 /* Found a free slot for a TKIP key */
726 return i;
727 }
728 return -1;
729 }
730
731 static int ath_reserve_key_cache_slot(struct ath_softc *sc)
732 {
733 int i;
734
735 /* First, try to find slots that would not be available for TKIP. */
736 if (sc->splitmic) {
737 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 4; i++) {
738 if (!test_bit(i, sc->keymap) &&
739 (test_bit(i + 32, sc->keymap) ||
740 test_bit(i + 64, sc->keymap) ||
741 test_bit(i + 64 + 32, sc->keymap)))
742 return i;
743 if (!test_bit(i + 32, sc->keymap) &&
744 (test_bit(i, sc->keymap) ||
745 test_bit(i + 64, sc->keymap) ||
746 test_bit(i + 64 + 32, sc->keymap)))
747 return i + 32;
748 if (!test_bit(i + 64, sc->keymap) &&
749 (test_bit(i , sc->keymap) ||
750 test_bit(i + 32, sc->keymap) ||
751 test_bit(i + 64 + 32, sc->keymap)))
752 return i + 64;
753 if (!test_bit(i + 64 + 32, sc->keymap) &&
754 (test_bit(i, sc->keymap) ||
755 test_bit(i + 32, sc->keymap) ||
756 test_bit(i + 64, sc->keymap)))
757 return i + 64 + 32;
758 }
759 } else {
760 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
761 if (!test_bit(i, sc->keymap) &&
762 test_bit(i + 64, sc->keymap))
763 return i;
764 if (test_bit(i, sc->keymap) &&
765 !test_bit(i + 64, sc->keymap))
766 return i + 64;
767 }
768 }
769
770 /* No partially used TKIP slots, pick any available slot */
771 for (i = IEEE80211_WEP_NKID; i < sc->keymax; i++) {
772 /* Do not allow slots that could be needed for TKIP group keys
773 * to be used. This limitation could be removed if we know that
774 * TKIP will not be used. */
775 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
776 continue;
777 if (sc->splitmic) {
778 if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
779 continue;
780 if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
781 continue;
782 }
783
784 if (!test_bit(i, sc->keymap))
785 return i; /* Found a free slot for a key */
786 }
787
788 /* No free slot found */
789 return -1;
790 }
791
792 static int ath_key_config(struct ath_softc *sc,
793 struct ieee80211_vif *vif,
794 struct ieee80211_sta *sta,
795 struct ieee80211_key_conf *key)
796 {
797 struct ath9k_keyval hk;
798 const u8 *mac = NULL;
799 int ret = 0;
800 int idx;
801
802 memset(&hk, 0, sizeof(hk));
803
804 switch (key->alg) {
805 case ALG_WEP:
806 hk.kv_type = ATH9K_CIPHER_WEP;
807 break;
808 case ALG_TKIP:
809 hk.kv_type = ATH9K_CIPHER_TKIP;
810 break;
811 case ALG_CCMP:
812 hk.kv_type = ATH9K_CIPHER_AES_CCM;
813 break;
814 default:
815 return -EOPNOTSUPP;
816 }
817
818 hk.kv_len = key->keylen;
819 memcpy(hk.kv_val, key->key, key->keylen);
820
821 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
822 /* For now, use the default keys for broadcast keys. This may
823 * need to change with virtual interfaces. */
824 idx = key->keyidx;
825 } else if (key->keyidx) {
826 if (WARN_ON(!sta))
827 return -EOPNOTSUPP;
828 mac = sta->addr;
829
830 if (vif->type != NL80211_IFTYPE_AP) {
831 /* Only keyidx 0 should be used with unicast key, but
832 * allow this for client mode for now. */
833 idx = key->keyidx;
834 } else
835 return -EIO;
836 } else {
837 if (WARN_ON(!sta))
838 return -EOPNOTSUPP;
839 mac = sta->addr;
840
841 if (key->alg == ALG_TKIP)
842 idx = ath_reserve_key_cache_slot_tkip(sc);
843 else
844 idx = ath_reserve_key_cache_slot(sc);
845 if (idx < 0)
846 return -ENOSPC; /* no free key cache entries */
847 }
848
849 if (key->alg == ALG_TKIP)
850 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac,
851 vif->type == NL80211_IFTYPE_AP);
852 else
853 ret = ath9k_hw_set_keycache_entry(sc->sc_ah, idx, &hk, mac);
854
855 if (!ret)
856 return -EIO;
857
858 set_bit(idx, sc->keymap);
859 if (key->alg == ALG_TKIP) {
860 set_bit(idx + 64, sc->keymap);
861 if (sc->splitmic) {
862 set_bit(idx + 32, sc->keymap);
863 set_bit(idx + 64 + 32, sc->keymap);
864 }
865 }
866
867 return idx;
868 }
869
870 static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
871 {
872 ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
873 if (key->hw_key_idx < IEEE80211_WEP_NKID)
874 return;
875
876 clear_bit(key->hw_key_idx, sc->keymap);
877 if (key->alg != ALG_TKIP)
878 return;
879
880 clear_bit(key->hw_key_idx + 64, sc->keymap);
881 if (sc->splitmic) {
882 clear_bit(key->hw_key_idx + 32, sc->keymap);
883 clear_bit(key->hw_key_idx + 64 + 32, sc->keymap);
884 }
885 }
886
887 static void setup_ht_cap(struct ath_softc *sc,
888 struct ieee80211_sta_ht_cap *ht_info)
889 {
890 #define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3 /* 2 ^ 16 */
891 #define ATH9K_HT_CAP_MPDUDENSITY_8 0x6 /* 8 usec */
892 u8 tx_streams, rx_streams;
893
894 ht_info->ht_supported = true;
895 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
896 IEEE80211_HT_CAP_SM_PS |
897 IEEE80211_HT_CAP_SGI_40 |
898 IEEE80211_HT_CAP_DSSSCCK40;
899
900 ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
901 ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
902
903 /* set up supported mcs set */
904 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
905 tx_streams = !(sc->tx_chainmask & (sc->tx_chainmask - 1)) ? 1 : 2;
906 rx_streams = !(sc->rx_chainmask & (sc->rx_chainmask - 1)) ? 1 : 2;
907
908 if (tx_streams != rx_streams) {
909 DPRINTF(sc, ATH_DBG_CONFIG, "TX streams %d, RX streams: %d\n",
910 tx_streams, rx_streams);
911 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
912 ht_info->mcs.tx_params |= ((tx_streams - 1) <<
913 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
914 }
915
916 ht_info->mcs.rx_mask[0] = 0xff;
917 if (rx_streams >= 2)
918 ht_info->mcs.rx_mask[1] = 0xff;
919
920 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
921 }
922
923 static void ath9k_bss_assoc_info(struct ath_softc *sc,
924 struct ieee80211_vif *vif,
925 struct ieee80211_bss_conf *bss_conf)
926 {
927
928 if (bss_conf->assoc) {
929 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
930 bss_conf->aid, sc->curbssid);
931
932 /* New association, store aid */
933 sc->curaid = bss_conf->aid;
934 ath9k_hw_write_associd(sc);
935
936 /*
937 * Request a re-configuration of Beacon related timers
938 * on the receipt of the first Beacon frame (i.e.,
939 * after time sync with the AP).
940 */
941 sc->sc_flags |= SC_OP_BEACON_SYNC;
942
943 /* Configure the beacon */
944 ath_beacon_config(sc, vif);
945
946 /* Reset rssi stats */
947 sc->nodestats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
948 sc->nodestats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
949 sc->nodestats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
950 sc->nodestats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
951
952 ath_start_ani(sc);
953 } else {
954 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
955 sc->curaid = 0;
956 /* Stop ANI */
957 del_timer_sync(&sc->ani.timer);
958 }
959 }
960
961 /********************************/
962 /* LED functions */
963 /********************************/
964
965 static void ath_led_blink_work(struct work_struct *work)
966 {
967 struct ath_softc *sc = container_of(work, struct ath_softc,
968 ath_led_blink_work.work);
969
970 if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
971 return;
972
973 if ((sc->led_on_duration == ATH_LED_ON_DURATION_IDLE) ||
974 (sc->led_off_duration == ATH_LED_OFF_DURATION_IDLE))
975 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
976 else
977 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
978 (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
979
980 queue_delayed_work(sc->hw->workqueue, &sc->ath_led_blink_work,
981 (sc->sc_flags & SC_OP_LED_ON) ?
982 msecs_to_jiffies(sc->led_off_duration) :
983 msecs_to_jiffies(sc->led_on_duration));
984
985 sc->led_on_duration = sc->led_on_cnt ?
986 max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25) :
987 ATH_LED_ON_DURATION_IDLE;
988 sc->led_off_duration = sc->led_off_cnt ?
989 max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10) :
990 ATH_LED_OFF_DURATION_IDLE;
991 sc->led_on_cnt = sc->led_off_cnt = 0;
992 if (sc->sc_flags & SC_OP_LED_ON)
993 sc->sc_flags &= ~SC_OP_LED_ON;
994 else
995 sc->sc_flags |= SC_OP_LED_ON;
996 }
997
998 static void ath_led_brightness(struct led_classdev *led_cdev,
999 enum led_brightness brightness)
1000 {
1001 struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
1002 struct ath_softc *sc = led->sc;
1003
1004 switch (brightness) {
1005 case LED_OFF:
1006 if (led->led_type == ATH_LED_ASSOC ||
1007 led->led_type == ATH_LED_RADIO) {
1008 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
1009 (led->led_type == ATH_LED_RADIO));
1010 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1011 if (led->led_type == ATH_LED_RADIO)
1012 sc->sc_flags &= ~SC_OP_LED_ON;
1013 } else {
1014 sc->led_off_cnt++;
1015 }
1016 break;
1017 case LED_FULL:
1018 if (led->led_type == ATH_LED_ASSOC) {
1019 sc->sc_flags |= SC_OP_LED_ASSOCIATED;
1020 queue_delayed_work(sc->hw->workqueue,
1021 &sc->ath_led_blink_work, 0);
1022 } else if (led->led_type == ATH_LED_RADIO) {
1023 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
1024 sc->sc_flags |= SC_OP_LED_ON;
1025 } else {
1026 sc->led_on_cnt++;
1027 }
1028 break;
1029 default:
1030 break;
1031 }
1032 }
1033
1034 static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
1035 char *trigger)
1036 {
1037 int ret;
1038
1039 led->sc = sc;
1040 led->led_cdev.name = led->name;
1041 led->led_cdev.default_trigger = trigger;
1042 led->led_cdev.brightness_set = ath_led_brightness;
1043
1044 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1045 if (ret)
1046 DPRINTF(sc, ATH_DBG_FATAL,
1047 "Failed to register led:%s", led->name);
1048 else
1049 led->registered = 1;
1050 return ret;
1051 }
1052
1053 static void ath_unregister_led(struct ath_led *led)
1054 {
1055 if (led->registered) {
1056 led_classdev_unregister(&led->led_cdev);
1057 led->registered = 0;
1058 }
1059 }
1060
1061 static void ath_deinit_leds(struct ath_softc *sc)
1062 {
1063 cancel_delayed_work_sync(&sc->ath_led_blink_work);
1064 ath_unregister_led(&sc->assoc_led);
1065 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1066 ath_unregister_led(&sc->tx_led);
1067 ath_unregister_led(&sc->rx_led);
1068 ath_unregister_led(&sc->radio_led);
1069 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1070 }
1071
1072 static void ath_init_leds(struct ath_softc *sc)
1073 {
1074 char *trigger;
1075 int ret;
1076
1077 /* Configure gpio 1 for output */
1078 ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
1079 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1080 /* LED off, active low */
1081 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1082
1083 INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
1084
1085 trigger = ieee80211_get_radio_led_name(sc->hw);
1086 snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
1087 "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
1088 ret = ath_register_led(sc, &sc->radio_led, trigger);
1089 sc->radio_led.led_type = ATH_LED_RADIO;
1090 if (ret)
1091 goto fail;
1092
1093 trigger = ieee80211_get_assoc_led_name(sc->hw);
1094 snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
1095 "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
1096 ret = ath_register_led(sc, &sc->assoc_led, trigger);
1097 sc->assoc_led.led_type = ATH_LED_ASSOC;
1098 if (ret)
1099 goto fail;
1100
1101 trigger = ieee80211_get_tx_led_name(sc->hw);
1102 snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
1103 "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
1104 ret = ath_register_led(sc, &sc->tx_led, trigger);
1105 sc->tx_led.led_type = ATH_LED_TX;
1106 if (ret)
1107 goto fail;
1108
1109 trigger = ieee80211_get_rx_led_name(sc->hw);
1110 snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
1111 "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
1112 ret = ath_register_led(sc, &sc->rx_led, trigger);
1113 sc->rx_led.led_type = ATH_LED_RX;
1114 if (ret)
1115 goto fail;
1116
1117 return;
1118
1119 fail:
1120 ath_deinit_leds(sc);
1121 }
1122
1123 void ath_radio_enable(struct ath_softc *sc)
1124 {
1125 struct ath_hw *ah = sc->sc_ah;
1126 struct ieee80211_channel *channel = sc->hw->conf.channel;
1127 int r;
1128
1129 ath9k_ps_wakeup(sc);
1130 ath9k_hw_configpcipowersave(ah, 0);
1131
1132 if (!ah->curchan)
1133 ah->curchan = ath_get_curchannel(sc, sc->hw);
1134
1135 spin_lock_bh(&sc->sc_resetlock);
1136 r = ath9k_hw_reset(ah, ah->curchan, false);
1137 if (r) {
1138 DPRINTF(sc, ATH_DBG_FATAL,
1139 "Unable to reset channel %u (%uMhz) ",
1140 "reset status %d\n",
1141 channel->center_freq, r);
1142 }
1143 spin_unlock_bh(&sc->sc_resetlock);
1144
1145 ath_update_txpow(sc);
1146 if (ath_startrecv(sc) != 0) {
1147 DPRINTF(sc, ATH_DBG_FATAL,
1148 "Unable to restart recv logic\n");
1149 return;
1150 }
1151
1152 if (sc->sc_flags & SC_OP_BEACONS)
1153 ath_beacon_config(sc, NULL); /* restart beacons */
1154
1155 /* Re-Enable interrupts */
1156 ath9k_hw_set_interrupts(ah, sc->imask);
1157
1158 /* Enable LED */
1159 ath9k_hw_cfg_output(ah, ATH_LED_PIN,
1160 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1161 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
1162
1163 ieee80211_wake_queues(sc->hw);
1164 ath9k_ps_restore(sc);
1165 }
1166
1167 void ath_radio_disable(struct ath_softc *sc)
1168 {
1169 struct ath_hw *ah = sc->sc_ah;
1170 struct ieee80211_channel *channel = sc->hw->conf.channel;
1171 int r;
1172
1173 ath9k_ps_wakeup(sc);
1174 ieee80211_stop_queues(sc->hw);
1175
1176 /* Disable LED */
1177 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
1178 ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
1179
1180 /* Disable interrupts */
1181 ath9k_hw_set_interrupts(ah, 0);
1182
1183 ath_drain_all_txq(sc, false); /* clear pending tx frames */
1184 ath_stoprecv(sc); /* turn off frame recv */
1185 ath_flushrecv(sc); /* flush recv queue */
1186
1187 if (!ah->curchan)
1188 ah->curchan = ath_get_curchannel(sc, sc->hw);
1189
1190 spin_lock_bh(&sc->sc_resetlock);
1191 r = ath9k_hw_reset(ah, ah->curchan, false);
1192 if (r) {
1193 DPRINTF(sc, ATH_DBG_FATAL,
1194 "Unable to reset channel %u (%uMhz) "
1195 "reset status %d\n",
1196 channel->center_freq, r);
1197 }
1198 spin_unlock_bh(&sc->sc_resetlock);
1199
1200 ath9k_hw_phy_disable(ah);
1201 ath9k_hw_configpcipowersave(ah, 1);
1202 ath9k_ps_restore(sc);
1203 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1204 }
1205
1206 /*******************/
1207 /* Rfkill */
1208 /*******************/
1209
1210 static bool ath_is_rfkill_set(struct ath_softc *sc)
1211 {
1212 struct ath_hw *ah = sc->sc_ah;
1213
1214 return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
1215 ah->rfkill_polarity;
1216 }
1217
1218 static void ath9k_rfkill_poll_state(struct ieee80211_hw *hw)
1219 {
1220 struct ath_wiphy *aphy = hw->priv;
1221 struct ath_softc *sc = aphy->sc;
1222 bool blocked = !!ath_is_rfkill_set(sc);
1223
1224 wiphy_rfkill_set_hw_state(hw->wiphy, blocked);
1225
1226 if (blocked)
1227 ath_radio_disable(sc);
1228 else
1229 ath_radio_enable(sc);
1230 }
1231
1232 static void ath_start_rfkill_poll(struct ath_softc *sc)
1233 {
1234 struct ath_hw *ah = sc->sc_ah;
1235
1236 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1237 wiphy_rfkill_start_polling(sc->hw->wiphy);
1238 }
1239
1240 void ath_cleanup(struct ath_softc *sc)
1241 {
1242 ath_detach(sc);
1243 free_irq(sc->irq, sc);
1244 ath_bus_cleanup(sc);
1245 kfree(sc->sec_wiphy);
1246 ieee80211_free_hw(sc->hw);
1247 }
1248
1249 void ath_detach(struct ath_softc *sc)
1250 {
1251 struct ieee80211_hw *hw = sc->hw;
1252 int i = 0;
1253
1254 ath9k_ps_wakeup(sc);
1255
1256 DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
1257
1258 ath_deinit_leds(sc);
1259 cancel_work_sync(&sc->chan_work);
1260 cancel_delayed_work_sync(&sc->wiphy_work);
1261
1262 for (i = 0; i < sc->num_sec_wiphy; i++) {
1263 struct ath_wiphy *aphy = sc->sec_wiphy[i];
1264 if (aphy == NULL)
1265 continue;
1266 sc->sec_wiphy[i] = NULL;
1267 ieee80211_unregister_hw(aphy->hw);
1268 ieee80211_free_hw(aphy->hw);
1269 }
1270 ieee80211_unregister_hw(hw);
1271 ath_rx_cleanup(sc);
1272 ath_tx_cleanup(sc);
1273
1274 tasklet_kill(&sc->intr_tq);
1275 tasklet_kill(&sc->bcon_tasklet);
1276
1277 if (!(sc->sc_flags & SC_OP_INVALID))
1278 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
1279
1280 /* cleanup tx queues */
1281 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1282 if (ATH_TXQ_SETUP(sc, i))
1283 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1284
1285 ath9k_hw_detach(sc->sc_ah);
1286 ath9k_exit_debug(sc);
1287 ath9k_ps_restore(sc);
1288 }
1289
1290 static int ath9k_reg_notifier(struct wiphy *wiphy,
1291 struct regulatory_request *request)
1292 {
1293 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
1294 struct ath_wiphy *aphy = hw->priv;
1295 struct ath_softc *sc = aphy->sc;
1296 struct ath_regulatory *reg = &sc->sc_ah->regulatory;
1297
1298 return ath_reg_notifier_apply(wiphy, request, reg);
1299 }
1300
1301 static int ath_init(u16 devid, struct ath_softc *sc)
1302 {
1303 struct ath_hw *ah = NULL;
1304 int status;
1305 int error = 0, i;
1306 int csz = 0;
1307
1308 /* XXX: hardware will not be ready until ath_open() being called */
1309 sc->sc_flags |= SC_OP_INVALID;
1310
1311 if (ath9k_init_debug(sc) < 0)
1312 printk(KERN_ERR "Unable to create debugfs files\n");
1313
1314 spin_lock_init(&sc->wiphy_lock);
1315 spin_lock_init(&sc->sc_resetlock);
1316 spin_lock_init(&sc->sc_serial_rw);
1317 spin_lock_init(&sc->ani_lock);
1318 mutex_init(&sc->mutex);
1319 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1320 tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
1321 (unsigned long)sc);
1322
1323 /*
1324 * Cache line size is used to size and align various
1325 * structures used to communicate with the hardware.
1326 */
1327 ath_read_cachesize(sc, &csz);
1328 /* XXX assert csz is non-zero */
1329 sc->cachelsz = csz << 2; /* convert to bytes */
1330
1331 ah = ath9k_hw_attach(devid, sc, &status);
1332 if (ah == NULL) {
1333 DPRINTF(sc, ATH_DBG_FATAL,
1334 "Unable to attach hardware; HAL status %d\n", status);
1335 error = -ENXIO;
1336 goto bad;
1337 }
1338 sc->sc_ah = ah;
1339
1340 /* Get the hardware key cache size. */
1341 sc->keymax = ah->caps.keycache_size;
1342 if (sc->keymax > ATH_KEYMAX) {
1343 DPRINTF(sc, ATH_DBG_ANY,
1344 "Warning, using only %u entries in %u key cache\n",
1345 ATH_KEYMAX, sc->keymax);
1346 sc->keymax = ATH_KEYMAX;
1347 }
1348
1349 /*
1350 * Reset the key cache since some parts do not
1351 * reset the contents on initial power up.
1352 */
1353 for (i = 0; i < sc->keymax; i++)
1354 ath9k_hw_keyreset(ah, (u16) i);
1355
1356 if (error)
1357 goto bad;
1358
1359 /* default to MONITOR mode */
1360 sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
1361
1362 /* Setup rate tables */
1363
1364 ath_rate_attach(sc);
1365 ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1366 ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1367
1368 /*
1369 * Allocate hardware transmit queues: one queue for
1370 * beacon frames and one data queue for each QoS
1371 * priority. Note that the hal handles reseting
1372 * these queues at the needed time.
1373 */
1374 sc->beacon.beaconq = ath_beaconq_setup(ah);
1375 if (sc->beacon.beaconq == -1) {
1376 DPRINTF(sc, ATH_DBG_FATAL,
1377 "Unable to setup a beacon xmit queue\n");
1378 error = -EIO;
1379 goto bad2;
1380 }
1381 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1382 if (sc->beacon.cabq == NULL) {
1383 DPRINTF(sc, ATH_DBG_FATAL,
1384 "Unable to setup CAB xmit queue\n");
1385 error = -EIO;
1386 goto bad2;
1387 }
1388
1389 sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
1390 ath_cabq_update(sc);
1391
1392 for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1393 sc->tx.hwq_map[i] = -1;
1394
1395 /* Setup data queues */
1396 /* NB: ensure BK queue is the lowest priority h/w queue */
1397 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1398 DPRINTF(sc, ATH_DBG_FATAL,
1399 "Unable to setup xmit queue for BK traffic\n");
1400 error = -EIO;
1401 goto bad2;
1402 }
1403
1404 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1405 DPRINTF(sc, ATH_DBG_FATAL,
1406 "Unable to setup xmit queue for BE traffic\n");
1407 error = -EIO;
1408 goto bad2;
1409 }
1410 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1411 DPRINTF(sc, ATH_DBG_FATAL,
1412 "Unable to setup xmit queue for VI traffic\n");
1413 error = -EIO;
1414 goto bad2;
1415 }
1416 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1417 DPRINTF(sc, ATH_DBG_FATAL,
1418 "Unable to setup xmit queue for VO traffic\n");
1419 error = -EIO;
1420 goto bad2;
1421 }
1422
1423 /* Initializes the noise floor to a reasonable default value.
1424 * Later on this will be updated during ANI processing. */
1425
1426 sc->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1427 setup_timer(&sc->ani.timer, ath_ani_calibrate, (unsigned long)sc);
1428
1429 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1430 ATH9K_CIPHER_TKIP, NULL)) {
1431 /*
1432 * Whether we should enable h/w TKIP MIC.
1433 * XXX: if we don't support WME TKIP MIC, then we wouldn't
1434 * report WMM capable, so it's always safe to turn on
1435 * TKIP MIC in this case.
1436 */
1437 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1438 0, 1, NULL);
1439 }
1440
1441 /*
1442 * Check whether the separate key cache entries
1443 * are required to handle both tx+rx MIC keys.
1444 * With split mic keys the number of stations is limited
1445 * to 27 otherwise 59.
1446 */
1447 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1448 ATH9K_CIPHER_TKIP, NULL)
1449 && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1450 ATH9K_CIPHER_MIC, NULL)
1451 && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1452 0, NULL))
1453 sc->splitmic = 1;
1454
1455 /* turn on mcast key search if possible */
1456 if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1457 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1458 1, NULL);
1459
1460 sc->config.txpowlimit = ATH_TXPOWER_MAX;
1461
1462 /* 11n Capabilities */
1463 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1464 sc->sc_flags |= SC_OP_TXAGGR;
1465 sc->sc_flags |= SC_OP_RXAGGR;
1466 }
1467
1468 sc->tx_chainmask = ah->caps.tx_chainmask;
1469 sc->rx_chainmask = ah->caps.rx_chainmask;
1470
1471 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
1472 sc->rx.defant = ath9k_hw_getdefantenna(ah);
1473
1474 if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
1475 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
1476
1477 sc->beacon.slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
1478
1479 /* initialize beacon slots */
1480 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
1481 sc->beacon.bslot[i] = NULL;
1482 sc->beacon.bslot_aphy[i] = NULL;
1483 }
1484
1485 /* setup channels and rates */
1486
1487 sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
1488 sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1489 sc->rates[IEEE80211_BAND_2GHZ];
1490 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
1491 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1492 ARRAY_SIZE(ath9k_2ghz_chantable);
1493
1494 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
1495 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
1496 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1497 sc->rates[IEEE80211_BAND_5GHZ];
1498 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
1499 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1500 ARRAY_SIZE(ath9k_5ghz_chantable);
1501 }
1502
1503 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)
1504 ath9k_hw_btcoex_enable(sc->sc_ah);
1505
1506 return 0;
1507 bad2:
1508 /* cleanup tx queues */
1509 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1510 if (ATH_TXQ_SETUP(sc, i))
1511 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1512 bad:
1513 if (ah)
1514 ath9k_hw_detach(ah);
1515 ath9k_exit_debug(sc);
1516
1517 return error;
1518 }
1519
1520 void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
1521 {
1522 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1523 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1524 IEEE80211_HW_SIGNAL_DBM |
1525 IEEE80211_HW_AMPDU_AGGREGATION |
1526 IEEE80211_HW_SUPPORTS_PS |
1527 IEEE80211_HW_PS_NULLFUNC_STACK |
1528 IEEE80211_HW_SPECTRUM_MGMT;
1529
1530 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
1531 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1532
1533 hw->wiphy->interface_modes =
1534 BIT(NL80211_IFTYPE_AP) |
1535 BIT(NL80211_IFTYPE_STATION) |
1536 BIT(NL80211_IFTYPE_ADHOC) |
1537 BIT(NL80211_IFTYPE_MESH_POINT);
1538
1539 hw->queues = 4;
1540 hw->max_rates = 4;
1541 hw->channel_change_time = 5000;
1542 hw->max_listen_interval = 10;
1543 /* Hardware supports 10 but we use 4 */
1544 hw->max_rate_tries = 4;
1545 hw->sta_data_size = sizeof(struct ath_node);
1546 hw->vif_data_size = sizeof(struct ath_vif);
1547
1548 hw->rate_control_algorithm = "ath9k_rate_control";
1549
1550 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
1551 &sc->sbands[IEEE80211_BAND_2GHZ];
1552 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1553 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1554 &sc->sbands[IEEE80211_BAND_5GHZ];
1555 }
1556
1557 int ath_attach(u16 devid, struct ath_softc *sc)
1558 {
1559 struct ieee80211_hw *hw = sc->hw;
1560 int error = 0, i;
1561 struct ath_regulatory *reg;
1562
1563 DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
1564
1565 error = ath_init(devid, sc);
1566 if (error != 0)
1567 return error;
1568
1569 /* get mac address from hardware and set in mac80211 */
1570
1571 SET_IEEE80211_PERM_ADDR(hw, sc->sc_ah->macaddr);
1572
1573 ath_set_hw_capab(sc, hw);
1574
1575 error = ath_regd_init(&sc->sc_ah->regulatory, sc->hw->wiphy,
1576 ath9k_reg_notifier);
1577 if (error)
1578 return error;
1579
1580 reg = &sc->sc_ah->regulatory;
1581
1582 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1583 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
1584 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1585 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
1586 }
1587
1588 /* initialize tx/rx engine */
1589 error = ath_tx_init(sc, ATH_TXBUF);
1590 if (error != 0)
1591 goto error_attach;
1592
1593 error = ath_rx_init(sc, ATH_RXBUF);
1594 if (error != 0)
1595 goto error_attach;
1596
1597 INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
1598 INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work);
1599 sc->wiphy_scheduler_int = msecs_to_jiffies(500);
1600
1601 error = ieee80211_register_hw(hw);
1602
1603 if (!ath_is_world_regd(reg)) {
1604 error = regulatory_hint(hw->wiphy, reg->alpha2);
1605 if (error)
1606 goto error_attach;
1607 }
1608
1609 /* Initialize LED control */
1610 ath_init_leds(sc);
1611
1612 ath_start_rfkill_poll(sc);
1613
1614 return 0;
1615
1616 error_attach:
1617 /* cleanup tx queues */
1618 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1619 if (ATH_TXQ_SETUP(sc, i))
1620 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1621
1622 ath9k_hw_detach(sc->sc_ah);
1623 ath9k_exit_debug(sc);
1624
1625 return error;
1626 }
1627
1628 int ath_reset(struct ath_softc *sc, bool retry_tx)
1629 {
1630 struct ath_hw *ah = sc->sc_ah;
1631 struct ieee80211_hw *hw = sc->hw;
1632 int r;
1633
1634 ath9k_hw_set_interrupts(ah, 0);
1635 ath_drain_all_txq(sc, retry_tx);
1636 ath_stoprecv(sc);
1637 ath_flushrecv(sc);
1638
1639 spin_lock_bh(&sc->sc_resetlock);
1640 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
1641 if (r)
1642 DPRINTF(sc, ATH_DBG_FATAL,
1643 "Unable to reset hardware; reset status %d\n", r);
1644 spin_unlock_bh(&sc->sc_resetlock);
1645
1646 if (ath_startrecv(sc) != 0)
1647 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
1648
1649 /*
1650 * We may be doing a reset in response to a request
1651 * that changes the channel so update any state that
1652 * might change as a result.
1653 */
1654 ath_cache_conf_rate(sc, &hw->conf);
1655
1656 ath_update_txpow(sc);
1657
1658 if (sc->sc_flags & SC_OP_BEACONS)
1659 ath_beacon_config(sc, NULL); /* restart beacons */
1660
1661 ath9k_hw_set_interrupts(ah, sc->imask);
1662
1663 if (retry_tx) {
1664 int i;
1665 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1666 if (ATH_TXQ_SETUP(sc, i)) {
1667 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1668 ath_txq_schedule(sc, &sc->tx.txq[i]);
1669 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
1670 }
1671 }
1672 }
1673
1674 return r;
1675 }
1676
1677 /*
1678 * This function will allocate both the DMA descriptor structure, and the
1679 * buffers it contains. These are used to contain the descriptors used
1680 * by the system.
1681 */
1682 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1683 struct list_head *head, const char *name,
1684 int nbuf, int ndesc)
1685 {
1686 #define DS2PHYS(_dd, _ds) \
1687 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1688 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1689 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1690
1691 struct ath_desc *ds;
1692 struct ath_buf *bf;
1693 int i, bsize, error;
1694
1695 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1696 name, nbuf, ndesc);
1697
1698 INIT_LIST_HEAD(head);
1699 /* ath_desc must be a multiple of DWORDs */
1700 if ((sizeof(struct ath_desc) % 4) != 0) {
1701 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
1702 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1703 error = -ENOMEM;
1704 goto fail;
1705 }
1706
1707 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1708
1709 /*
1710 * Need additional DMA memory because we can't use
1711 * descriptors that cross the 4K page boundary. Assume
1712 * one skipped descriptor per 4K page.
1713 */
1714 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1715 u32 ndesc_skipped =
1716 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1717 u32 dma_len;
1718
1719 while (ndesc_skipped) {
1720 dma_len = ndesc_skipped * sizeof(struct ath_desc);
1721 dd->dd_desc_len += dma_len;
1722
1723 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1724 };
1725 }
1726
1727 /* allocate descriptors */
1728 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
1729 &dd->dd_desc_paddr, GFP_KERNEL);
1730 if (dd->dd_desc == NULL) {
1731 error = -ENOMEM;
1732 goto fail;
1733 }
1734 ds = dd->dd_desc;
1735 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
1736 name, ds, (u32) dd->dd_desc_len,
1737 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1738
1739 /* allocate buffers */
1740 bsize = sizeof(struct ath_buf) * nbuf;
1741 bf = kzalloc(bsize, GFP_KERNEL);
1742 if (bf == NULL) {
1743 error = -ENOMEM;
1744 goto fail2;
1745 }
1746 dd->dd_bufptr = bf;
1747
1748 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1749 bf->bf_desc = ds;
1750 bf->bf_daddr = DS2PHYS(dd, ds);
1751
1752 if (!(sc->sc_ah->caps.hw_caps &
1753 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1754 /*
1755 * Skip descriptor addresses which can cause 4KB
1756 * boundary crossing (addr + length) with a 32 dword
1757 * descriptor fetch.
1758 */
1759 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1760 ASSERT((caddr_t) bf->bf_desc <
1761 ((caddr_t) dd->dd_desc +
1762 dd->dd_desc_len));
1763
1764 ds += ndesc;
1765 bf->bf_desc = ds;
1766 bf->bf_daddr = DS2PHYS(dd, ds);
1767 }
1768 }
1769 list_add_tail(&bf->list, head);
1770 }
1771 return 0;
1772 fail2:
1773 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1774 dd->dd_desc_paddr);
1775 fail:
1776 memset(dd, 0, sizeof(*dd));
1777 return error;
1778 #undef ATH_DESC_4KB_BOUND_CHECK
1779 #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1780 #undef DS2PHYS
1781 }
1782
1783 void ath_descdma_cleanup(struct ath_softc *sc,
1784 struct ath_descdma *dd,
1785 struct list_head *head)
1786 {
1787 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1788 dd->dd_desc_paddr);
1789
1790 INIT_LIST_HEAD(head);
1791 kfree(dd->dd_bufptr);
1792 memset(dd, 0, sizeof(*dd));
1793 }
1794
1795 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1796 {
1797 int qnum;
1798
1799 switch (queue) {
1800 case 0:
1801 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
1802 break;
1803 case 1:
1804 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
1805 break;
1806 case 2:
1807 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1808 break;
1809 case 3:
1810 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
1811 break;
1812 default:
1813 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1814 break;
1815 }
1816
1817 return qnum;
1818 }
1819
1820 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1821 {
1822 int qnum;
1823
1824 switch (queue) {
1825 case ATH9K_WME_AC_VO:
1826 qnum = 0;
1827 break;
1828 case ATH9K_WME_AC_VI:
1829 qnum = 1;
1830 break;
1831 case ATH9K_WME_AC_BE:
1832 qnum = 2;
1833 break;
1834 case ATH9K_WME_AC_BK:
1835 qnum = 3;
1836 break;
1837 default:
1838 qnum = -1;
1839 break;
1840 }
1841
1842 return qnum;
1843 }
1844
1845 /* XXX: Remove me once we don't depend on ath9k_channel for all
1846 * this redundant data */
1847 void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
1848 struct ath9k_channel *ichan)
1849 {
1850 struct ieee80211_channel *chan = hw->conf.channel;
1851 struct ieee80211_conf *conf = &hw->conf;
1852
1853 ichan->channel = chan->center_freq;
1854 ichan->chan = chan;
1855
1856 if (chan->band == IEEE80211_BAND_2GHZ) {
1857 ichan->chanmode = CHANNEL_G;
1858 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM;
1859 } else {
1860 ichan->chanmode = CHANNEL_A;
1861 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
1862 }
1863
1864 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
1865
1866 if (conf_is_ht(conf)) {
1867 if (conf_is_ht40(conf))
1868 sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
1869
1870 ichan->chanmode = ath_get_extchanmode(sc, chan,
1871 conf->channel_type);
1872 }
1873 }
1874
1875 /**********************/
1876 /* mac80211 callbacks */
1877 /**********************/
1878
1879 static int ath9k_start(struct ieee80211_hw *hw)
1880 {
1881 struct ath_wiphy *aphy = hw->priv;
1882 struct ath_softc *sc = aphy->sc;
1883 struct ieee80211_channel *curchan = hw->conf.channel;
1884 struct ath9k_channel *init_channel;
1885 int r;
1886
1887 DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1888 "initial channel: %d MHz\n", curchan->center_freq);
1889
1890 mutex_lock(&sc->mutex);
1891
1892 if (ath9k_wiphy_started(sc)) {
1893 if (sc->chan_idx == curchan->hw_value) {
1894 /*
1895 * Already on the operational channel, the new wiphy
1896 * can be marked active.
1897 */
1898 aphy->state = ATH_WIPHY_ACTIVE;
1899 ieee80211_wake_queues(hw);
1900 } else {
1901 /*
1902 * Another wiphy is on another channel, start the new
1903 * wiphy in paused state.
1904 */
1905 aphy->state = ATH_WIPHY_PAUSED;
1906 ieee80211_stop_queues(hw);
1907 }
1908 mutex_unlock(&sc->mutex);
1909 return 0;
1910 }
1911 aphy->state = ATH_WIPHY_ACTIVE;
1912
1913 /* setup initial channel */
1914
1915 sc->chan_idx = curchan->hw_value;
1916
1917 init_channel = ath_get_curchannel(sc, hw);
1918
1919 /* Reset SERDES registers */
1920 ath9k_hw_configpcipowersave(sc->sc_ah, 0);
1921
1922 /*
1923 * The basic interface to setting the hardware in a good
1924 * state is ``reset''. On return the hardware is known to
1925 * be powered up and with interrupts disabled. This must
1926 * be followed by initialization of the appropriate bits
1927 * and then setup of the interrupt mask.
1928 */
1929 spin_lock_bh(&sc->sc_resetlock);
1930 r = ath9k_hw_reset(sc->sc_ah, init_channel, false);
1931 if (r) {
1932 DPRINTF(sc, ATH_DBG_FATAL,
1933 "Unable to reset hardware; reset status %d "
1934 "(freq %u MHz)\n", r,
1935 curchan->center_freq);
1936 spin_unlock_bh(&sc->sc_resetlock);
1937 goto mutex_unlock;
1938 }
1939 spin_unlock_bh(&sc->sc_resetlock);
1940
1941 /*
1942 * This is needed only to setup initial state
1943 * but it's best done after a reset.
1944 */
1945 ath_update_txpow(sc);
1946
1947 /*
1948 * Setup the hardware after reset:
1949 * The receive engine is set going.
1950 * Frame transmit is handled entirely
1951 * in the frame output path; there's nothing to do
1952 * here except setup the interrupt mask.
1953 */
1954 if (ath_startrecv(sc) != 0) {
1955 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
1956 r = -EIO;
1957 goto mutex_unlock;
1958 }
1959
1960 /* Setup our intr mask. */
1961 sc->imask = ATH9K_INT_RX | ATH9K_INT_TX
1962 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
1963 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
1964
1965 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
1966 sc->imask |= ATH9K_INT_GTT;
1967
1968 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
1969 sc->imask |= ATH9K_INT_CST;
1970
1971 ath_cache_conf_rate(sc, &hw->conf);
1972
1973 sc->sc_flags &= ~SC_OP_INVALID;
1974
1975 /* Disable BMISS interrupt when we're not associated */
1976 sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
1977 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
1978
1979 ieee80211_wake_queues(hw);
1980
1981 mutex_unlock:
1982 mutex_unlock(&sc->mutex);
1983
1984 return r;
1985 }
1986
1987 static int ath9k_tx(struct ieee80211_hw *hw,
1988 struct sk_buff *skb)
1989 {
1990 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1991 struct ath_wiphy *aphy = hw->priv;
1992 struct ath_softc *sc = aphy->sc;
1993 struct ath_tx_control txctl;
1994 int hdrlen, padsize;
1995
1996 if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
1997 printk(KERN_DEBUG "ath9k: %s: TX in unexpected wiphy state "
1998 "%d\n", wiphy_name(hw->wiphy), aphy->state);
1999 goto exit;
2000 }
2001
2002 if (sc->hw->conf.flags & IEEE80211_CONF_PS) {
2003 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2004 /*
2005 * mac80211 does not set PM field for normal data frames, so we
2006 * need to update that based on the current PS mode.
2007 */
2008 if (ieee80211_is_data(hdr->frame_control) &&
2009 !ieee80211_is_nullfunc(hdr->frame_control) &&
2010 !ieee80211_has_pm(hdr->frame_control)) {
2011 DPRINTF(sc, ATH_DBG_PS, "Add PM=1 for a TX frame "
2012 "while in PS mode\n");
2013 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
2014 }
2015 }
2016
2017 if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
2018 /*
2019 * We are using PS-Poll and mac80211 can request TX while in
2020 * power save mode. Need to wake up hardware for the TX to be
2021 * completed and if needed, also for RX of buffered frames.
2022 */
2023 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2024 ath9k_ps_wakeup(sc);
2025 ath9k_hw_setrxabort(sc->sc_ah, 0);
2026 if (ieee80211_is_pspoll(hdr->frame_control)) {
2027 DPRINTF(sc, ATH_DBG_PS, "Sending PS-Poll to pick a "
2028 "buffered frame\n");
2029 sc->sc_flags |= SC_OP_WAIT_FOR_PSPOLL_DATA;
2030 } else {
2031 DPRINTF(sc, ATH_DBG_PS, "Wake up to complete TX\n");
2032 sc->sc_flags |= SC_OP_WAIT_FOR_TX_ACK;
2033 }
2034 /*
2035 * The actual restore operation will happen only after
2036 * the sc_flags bit is cleared. We are just dropping
2037 * the ps_usecount here.
2038 */
2039 ath9k_ps_restore(sc);
2040 }
2041
2042 memset(&txctl, 0, sizeof(struct ath_tx_control));
2043
2044 /*
2045 * As a temporary workaround, assign seq# here; this will likely need
2046 * to be cleaned up to work better with Beacon transmission and virtual
2047 * BSSes.
2048 */
2049 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2050 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2051 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2052 sc->tx.seq_no += 0x10;
2053 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2054 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
2055 }
2056
2057 /* Add the padding after the header if this is not already done */
2058 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2059 if (hdrlen & 3) {
2060 padsize = hdrlen % 4;
2061 if (skb_headroom(skb) < padsize)
2062 return -1;
2063 skb_push(skb, padsize);
2064 memmove(skb->data, skb->data + padsize, hdrlen);
2065 }
2066
2067 /* Check if a tx queue is available */
2068
2069 txctl.txq = ath_test_get_txq(sc, skb);
2070 if (!txctl.txq)
2071 goto exit;
2072
2073 DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
2074
2075 if (ath_tx_start(hw, skb, &txctl) != 0) {
2076 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
2077 goto exit;
2078 }
2079
2080 return 0;
2081 exit:
2082 dev_kfree_skb_any(skb);
2083 return 0;
2084 }
2085
2086 static void ath9k_stop(struct ieee80211_hw *hw)
2087 {
2088 struct ath_wiphy *aphy = hw->priv;
2089 struct ath_softc *sc = aphy->sc;
2090
2091 aphy->state = ATH_WIPHY_INACTIVE;
2092
2093 if (sc->sc_flags & SC_OP_INVALID) {
2094 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
2095 return;
2096 }
2097
2098 mutex_lock(&sc->mutex);
2099
2100 ieee80211_stop_queues(hw);
2101
2102 if (ath9k_wiphy_started(sc)) {
2103 mutex_unlock(&sc->mutex);
2104 return; /* another wiphy still in use */
2105 }
2106
2107 /* make sure h/w will not generate any interrupt
2108 * before setting the invalid flag. */
2109 ath9k_hw_set_interrupts(sc->sc_ah, 0);
2110
2111 if (!(sc->sc_flags & SC_OP_INVALID)) {
2112 ath_drain_all_txq(sc, false);
2113 ath_stoprecv(sc);
2114 ath9k_hw_phy_disable(sc->sc_ah);
2115 } else
2116 sc->rx.rxlink = NULL;
2117
2118 wiphy_rfkill_stop_polling(sc->hw->wiphy);
2119
2120 /* disable HAL and put h/w to sleep */
2121 ath9k_hw_disable(sc->sc_ah);
2122 ath9k_hw_configpcipowersave(sc->sc_ah, 1);
2123
2124 sc->sc_flags |= SC_OP_INVALID;
2125
2126 mutex_unlock(&sc->mutex);
2127
2128 DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
2129 }
2130
2131 static int ath9k_add_interface(struct ieee80211_hw *hw,
2132 struct ieee80211_if_init_conf *conf)
2133 {
2134 struct ath_wiphy *aphy = hw->priv;
2135 struct ath_softc *sc = aphy->sc;
2136 struct ath_vif *avp = (void *)conf->vif->drv_priv;
2137 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2138 int ret = 0;
2139
2140 mutex_lock(&sc->mutex);
2141
2142 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
2143 sc->nvifs > 0) {
2144 ret = -ENOBUFS;
2145 goto out;
2146 }
2147
2148 switch (conf->type) {
2149 case NL80211_IFTYPE_STATION:
2150 ic_opmode = NL80211_IFTYPE_STATION;
2151 break;
2152 case NL80211_IFTYPE_ADHOC:
2153 case NL80211_IFTYPE_AP:
2154 case NL80211_IFTYPE_MESH_POINT:
2155 if (sc->nbcnvifs >= ATH_BCBUF) {
2156 ret = -ENOBUFS;
2157 goto out;
2158 }
2159 ic_opmode = conf->type;
2160 break;
2161 default:
2162 DPRINTF(sc, ATH_DBG_FATAL,
2163 "Interface type %d not yet supported\n", conf->type);
2164 ret = -EOPNOTSUPP;
2165 goto out;
2166 }
2167
2168 DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VIF of type: %d\n", ic_opmode);
2169
2170 /* Set the VIF opmode */
2171 avp->av_opmode = ic_opmode;
2172 avp->av_bslot = -1;
2173
2174 sc->nvifs++;
2175
2176 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
2177 ath9k_set_bssid_mask(hw);
2178
2179 if (sc->nvifs > 1)
2180 goto out; /* skip global settings for secondary vif */
2181
2182 if (ic_opmode == NL80211_IFTYPE_AP) {
2183 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2184 sc->sc_flags |= SC_OP_TSF_RESET;
2185 }
2186
2187 /* Set the device opmode */
2188 sc->sc_ah->opmode = ic_opmode;
2189
2190 /*
2191 * Enable MIB interrupts when there are hardware phy counters.
2192 * Note we only do this (at the moment) for station mode.
2193 */
2194 if ((conf->type == NL80211_IFTYPE_STATION) ||
2195 (conf->type == NL80211_IFTYPE_ADHOC) ||
2196 (conf->type == NL80211_IFTYPE_MESH_POINT)) {
2197 if (ath9k_hw_phycounters(sc->sc_ah))
2198 sc->imask |= ATH9K_INT_MIB;
2199 sc->imask |= ATH9K_INT_TSFOOR;
2200 }
2201
2202 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
2203
2204 if (conf->type == NL80211_IFTYPE_AP ||
2205 conf->type == NL80211_IFTYPE_ADHOC ||
2206 conf->type == NL80211_IFTYPE_MONITOR)
2207 ath_start_ani(sc);
2208
2209 out:
2210 mutex_unlock(&sc->mutex);
2211 return ret;
2212 }
2213
2214 static void ath9k_remove_interface(struct ieee80211_hw *hw,
2215 struct ieee80211_if_init_conf *conf)
2216 {
2217 struct ath_wiphy *aphy = hw->priv;
2218 struct ath_softc *sc = aphy->sc;
2219 struct ath_vif *avp = (void *)conf->vif->drv_priv;
2220 int i;
2221
2222 DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
2223
2224 mutex_lock(&sc->mutex);
2225
2226 /* Stop ANI */
2227 del_timer_sync(&sc->ani.timer);
2228
2229 /* Reclaim beacon resources */
2230 if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
2231 (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
2232 (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
2233 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2234 ath_beacon_return(sc, avp);
2235 }
2236
2237 sc->sc_flags &= ~SC_OP_BEACONS;
2238
2239 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2240 if (sc->beacon.bslot[i] == conf->vif) {
2241 printk(KERN_DEBUG "%s: vif had allocated beacon "
2242 "slot\n", __func__);
2243 sc->beacon.bslot[i] = NULL;
2244 sc->beacon.bslot_aphy[i] = NULL;
2245 }
2246 }
2247
2248 sc->nvifs--;
2249
2250 mutex_unlock(&sc->mutex);
2251 }
2252
2253 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2254 {
2255 struct ath_wiphy *aphy = hw->priv;
2256 struct ath_softc *sc = aphy->sc;
2257 struct ieee80211_conf *conf = &hw->conf;
2258 struct ath_hw *ah = sc->sc_ah;
2259
2260 mutex_lock(&sc->mutex);
2261
2262 if (changed & IEEE80211_CONF_CHANGE_PS) {
2263 if (conf->flags & IEEE80211_CONF_PS) {
2264 if (!(ah->caps.hw_caps &
2265 ATH9K_HW_CAP_AUTOSLEEP)) {
2266 if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
2267 sc->imask |= ATH9K_INT_TIM_TIMER;
2268 ath9k_hw_set_interrupts(sc->sc_ah,
2269 sc->imask);
2270 }
2271 ath9k_hw_setrxabort(sc->sc_ah, 1);
2272 }
2273 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
2274 } else {
2275 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
2276 if (!(ah->caps.hw_caps &
2277 ATH9K_HW_CAP_AUTOSLEEP)) {
2278 ath9k_hw_setrxabort(sc->sc_ah, 0);
2279 sc->sc_flags &= ~(SC_OP_WAIT_FOR_BEACON |
2280 SC_OP_WAIT_FOR_CAB |
2281 SC_OP_WAIT_FOR_PSPOLL_DATA |
2282 SC_OP_WAIT_FOR_TX_ACK);
2283 if (sc->imask & ATH9K_INT_TIM_TIMER) {
2284 sc->imask &= ~ATH9K_INT_TIM_TIMER;
2285 ath9k_hw_set_interrupts(sc->sc_ah,
2286 sc->imask);
2287 }
2288 }
2289 }
2290 }
2291
2292 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2293 struct ieee80211_channel *curchan = hw->conf.channel;
2294 int pos = curchan->hw_value;
2295
2296 aphy->chan_idx = pos;
2297 aphy->chan_is_ht = conf_is_ht(conf);
2298
2299 if (aphy->state == ATH_WIPHY_SCAN ||
2300 aphy->state == ATH_WIPHY_ACTIVE)
2301 ath9k_wiphy_pause_all_forced(sc, aphy);
2302 else {
2303 /*
2304 * Do not change operational channel based on a paused
2305 * wiphy changes.
2306 */
2307 goto skip_chan_change;
2308 }
2309
2310 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2311 curchan->center_freq);
2312
2313 /* XXX: remove me eventualy */
2314 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
2315
2316 ath_update_chainmask(sc, conf_is_ht(conf));
2317
2318 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
2319 DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
2320 mutex_unlock(&sc->mutex);
2321 return -EINVAL;
2322 }
2323 }
2324
2325 skip_chan_change:
2326 if (changed & IEEE80211_CONF_CHANGE_POWER)
2327 sc->config.txpowlimit = 2 * conf->power_level;
2328
2329 mutex_unlock(&sc->mutex);
2330
2331 return 0;
2332 }
2333
2334 #define SUPPORTED_FILTERS \
2335 (FIF_PROMISC_IN_BSS | \
2336 FIF_ALLMULTI | \
2337 FIF_CONTROL | \
2338 FIF_OTHER_BSS | \
2339 FIF_BCN_PRBRESP_PROMISC | \
2340 FIF_FCSFAIL)
2341
2342 /* FIXME: sc->sc_full_reset ? */
2343 static void ath9k_configure_filter(struct ieee80211_hw *hw,
2344 unsigned int changed_flags,
2345 unsigned int *total_flags,
2346 int mc_count,
2347 struct dev_mc_list *mclist)
2348 {
2349 struct ath_wiphy *aphy = hw->priv;
2350 struct ath_softc *sc = aphy->sc;
2351 u32 rfilt;
2352
2353 changed_flags &= SUPPORTED_FILTERS;
2354 *total_flags &= SUPPORTED_FILTERS;
2355
2356 sc->rx.rxfilter = *total_flags;
2357 ath9k_ps_wakeup(sc);
2358 rfilt = ath_calcrxfilter(sc);
2359 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
2360 ath9k_ps_restore(sc);
2361
2362 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
2363 }
2364
2365 static void ath9k_sta_notify(struct ieee80211_hw *hw,
2366 struct ieee80211_vif *vif,
2367 enum sta_notify_cmd cmd,
2368 struct ieee80211_sta *sta)
2369 {
2370 struct ath_wiphy *aphy = hw->priv;
2371 struct ath_softc *sc = aphy->sc;
2372
2373 switch (cmd) {
2374 case STA_NOTIFY_ADD:
2375 ath_node_attach(sc, sta);
2376 break;
2377 case STA_NOTIFY_REMOVE:
2378 ath_node_detach(sc, sta);
2379 break;
2380 default:
2381 break;
2382 }
2383 }
2384
2385 static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
2386 const struct ieee80211_tx_queue_params *params)
2387 {
2388 struct ath_wiphy *aphy = hw->priv;
2389 struct ath_softc *sc = aphy->sc;
2390 struct ath9k_tx_queue_info qi;
2391 int ret = 0, qnum;
2392
2393 if (queue >= WME_NUM_AC)
2394 return 0;
2395
2396 mutex_lock(&sc->mutex);
2397
2398 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
2399
2400 qi.tqi_aifs = params->aifs;
2401 qi.tqi_cwmin = params->cw_min;
2402 qi.tqi_cwmax = params->cw_max;
2403 qi.tqi_burstTime = params->txop;
2404 qnum = ath_get_hal_qnum(queue, sc);
2405
2406 DPRINTF(sc, ATH_DBG_CONFIG,
2407 "Configure tx [queue/halq] [%d/%d], "
2408 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2409 queue, qnum, params->aifs, params->cw_min,
2410 params->cw_max, params->txop);
2411
2412 ret = ath_txq_update(sc, qnum, &qi);
2413 if (ret)
2414 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
2415
2416 mutex_unlock(&sc->mutex);
2417
2418 return ret;
2419 }
2420
2421 static int ath9k_set_key(struct ieee80211_hw *hw,
2422 enum set_key_cmd cmd,
2423 struct ieee80211_vif *vif,
2424 struct ieee80211_sta *sta,
2425 struct ieee80211_key_conf *key)
2426 {
2427 struct ath_wiphy *aphy = hw->priv;
2428 struct ath_softc *sc = aphy->sc;
2429 int ret = 0;
2430
2431 if (modparam_nohwcrypt)
2432 return -ENOSPC;
2433
2434 mutex_lock(&sc->mutex);
2435 ath9k_ps_wakeup(sc);
2436 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW Key\n");
2437
2438 switch (cmd) {
2439 case SET_KEY:
2440 ret = ath_key_config(sc, vif, sta, key);
2441 if (ret >= 0) {
2442 key->hw_key_idx = ret;
2443 /* push IV and Michael MIC generation to stack */
2444 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2445 if (key->alg == ALG_TKIP)
2446 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
2447 if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2448 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
2449 ret = 0;
2450 }
2451 break;
2452 case DISABLE_KEY:
2453 ath_key_delete(sc, key);
2454 break;
2455 default:
2456 ret = -EINVAL;
2457 }
2458
2459 ath9k_ps_restore(sc);
2460 mutex_unlock(&sc->mutex);
2461
2462 return ret;
2463 }
2464
2465 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2466 struct ieee80211_vif *vif,
2467 struct ieee80211_bss_conf *bss_conf,
2468 u32 changed)
2469 {
2470 struct ath_wiphy *aphy = hw->priv;
2471 struct ath_softc *sc = aphy->sc;
2472 struct ath_hw *ah = sc->sc_ah;
2473 struct ath_vif *avp = (void *)vif->drv_priv;
2474 u32 rfilt = 0;
2475 int error, i;
2476
2477 mutex_lock(&sc->mutex);
2478
2479 /*
2480 * TODO: Need to decide which hw opmode to use for
2481 * multi-interface cases
2482 * XXX: This belongs into add_interface!
2483 */
2484 if (vif->type == NL80211_IFTYPE_AP &&
2485 ah->opmode != NL80211_IFTYPE_AP) {
2486 ah->opmode = NL80211_IFTYPE_STATION;
2487 ath9k_hw_setopmode(ah);
2488 memcpy(sc->curbssid, sc->sc_ah->macaddr, ETH_ALEN);
2489 sc->curaid = 0;
2490 ath9k_hw_write_associd(sc);
2491 /* Request full reset to get hw opmode changed properly */
2492 sc->sc_flags |= SC_OP_FULL_RESET;
2493 }
2494
2495 if ((changed & BSS_CHANGED_BSSID) &&
2496 !is_zero_ether_addr(bss_conf->bssid)) {
2497 switch (vif->type) {
2498 case NL80211_IFTYPE_STATION:
2499 case NL80211_IFTYPE_ADHOC:
2500 case NL80211_IFTYPE_MESH_POINT:
2501 /* Set BSSID */
2502 memcpy(sc->curbssid, bss_conf->bssid, ETH_ALEN);
2503 memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
2504 sc->curaid = 0;
2505 ath9k_hw_write_associd(sc);
2506
2507 /* Set aggregation protection mode parameters */
2508 sc->config.ath_aggr_prot = 0;
2509
2510 DPRINTF(sc, ATH_DBG_CONFIG,
2511 "RX filter 0x%x bssid %pM aid 0x%x\n",
2512 rfilt, sc->curbssid, sc->curaid);
2513
2514 /* need to reconfigure the beacon */
2515 sc->sc_flags &= ~SC_OP_BEACONS ;
2516
2517 break;
2518 default:
2519 break;
2520 }
2521 }
2522
2523 if ((vif->type == NL80211_IFTYPE_ADHOC) ||
2524 (vif->type == NL80211_IFTYPE_AP) ||
2525 (vif->type == NL80211_IFTYPE_MESH_POINT)) {
2526 if ((changed & BSS_CHANGED_BEACON) ||
2527 (changed & BSS_CHANGED_BEACON_ENABLED &&
2528 bss_conf->enable_beacon)) {
2529 /*
2530 * Allocate and setup the beacon frame.
2531 *
2532 * Stop any previous beacon DMA. This may be
2533 * necessary, for example, when an ibss merge
2534 * causes reconfiguration; we may be called
2535 * with beacon transmission active.
2536 */
2537 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2538
2539 error = ath_beacon_alloc(aphy, vif);
2540 if (!error)
2541 ath_beacon_config(sc, vif);
2542 }
2543 }
2544
2545 /* Check for WLAN_CAPABILITY_PRIVACY ? */
2546 if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
2547 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2548 if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2549 ath9k_hw_keysetmac(sc->sc_ah,
2550 (u16)i,
2551 sc->curbssid);
2552 }
2553
2554 /* Only legacy IBSS for now */
2555 if (vif->type == NL80211_IFTYPE_ADHOC)
2556 ath_update_chainmask(sc, 0);
2557
2558 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
2559 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
2560 bss_conf->use_short_preamble);
2561 if (bss_conf->use_short_preamble)
2562 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2563 else
2564 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2565 }
2566
2567 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
2568 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
2569 bss_conf->use_cts_prot);
2570 if (bss_conf->use_cts_prot &&
2571 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2572 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2573 else
2574 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2575 }
2576
2577 if (changed & BSS_CHANGED_ASSOC) {
2578 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
2579 bss_conf->assoc);
2580 ath9k_bss_assoc_info(sc, vif, bss_conf);
2581 }
2582
2583 /*
2584 * The HW TSF has to be reset when the beacon interval changes.
2585 * We set the flag here, and ath_beacon_config_ap() would take this
2586 * into account when it gets called through the subsequent
2587 * config_interface() call - with IFCC_BEACON in the changed field.
2588 */
2589
2590 if (changed & BSS_CHANGED_BEACON_INT) {
2591 sc->sc_flags |= SC_OP_TSF_RESET;
2592 sc->beacon_interval = bss_conf->beacon_int;
2593 }
2594
2595 mutex_unlock(&sc->mutex);
2596 }
2597
2598 static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2599 {
2600 u64 tsf;
2601 struct ath_wiphy *aphy = hw->priv;
2602 struct ath_softc *sc = aphy->sc;
2603
2604 mutex_lock(&sc->mutex);
2605 tsf = ath9k_hw_gettsf64(sc->sc_ah);
2606 mutex_unlock(&sc->mutex);
2607
2608 return tsf;
2609 }
2610
2611 static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2612 {
2613 struct ath_wiphy *aphy = hw->priv;
2614 struct ath_softc *sc = aphy->sc;
2615
2616 mutex_lock(&sc->mutex);
2617 ath9k_hw_settsf64(sc->sc_ah, tsf);
2618 mutex_unlock(&sc->mutex);
2619 }
2620
2621 static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2622 {
2623 struct ath_wiphy *aphy = hw->priv;
2624 struct ath_softc *sc = aphy->sc;
2625
2626 mutex_lock(&sc->mutex);
2627 ath9k_hw_reset_tsf(sc->sc_ah);
2628 mutex_unlock(&sc->mutex);
2629 }
2630
2631 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2632 enum ieee80211_ampdu_mlme_action action,
2633 struct ieee80211_sta *sta,
2634 u16 tid, u16 *ssn)
2635 {
2636 struct ath_wiphy *aphy = hw->priv;
2637 struct ath_softc *sc = aphy->sc;
2638 int ret = 0;
2639
2640 switch (action) {
2641 case IEEE80211_AMPDU_RX_START:
2642 if (!(sc->sc_flags & SC_OP_RXAGGR))
2643 ret = -ENOTSUPP;
2644 break;
2645 case IEEE80211_AMPDU_RX_STOP:
2646 break;
2647 case IEEE80211_AMPDU_TX_START:
2648 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
2649 if (ret < 0)
2650 DPRINTF(sc, ATH_DBG_FATAL,
2651 "Unable to start TX aggregation\n");
2652 else
2653 ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2654 break;
2655 case IEEE80211_AMPDU_TX_STOP:
2656 ret = ath_tx_aggr_stop(sc, sta, tid);
2657 if (ret < 0)
2658 DPRINTF(sc, ATH_DBG_FATAL,
2659 "Unable to stop TX aggregation\n");
2660
2661 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2662 break;
2663 case IEEE80211_AMPDU_TX_OPERATIONAL:
2664 ath_tx_aggr_resume(sc, sta, tid);
2665 break;
2666 default:
2667 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
2668 }
2669
2670 return ret;
2671 }
2672
2673 static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
2674 {
2675 struct ath_wiphy *aphy = hw->priv;
2676 struct ath_softc *sc = aphy->sc;
2677
2678 if (ath9k_wiphy_scanning(sc)) {
2679 printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the "
2680 "same time\n");
2681 /*
2682 * Do not allow the concurrent scanning state for now. This
2683 * could be improved with scanning control moved into ath9k.
2684 */
2685 return;
2686 }
2687
2688 aphy->state = ATH_WIPHY_SCAN;
2689 ath9k_wiphy_pause_all_forced(sc, aphy);
2690
2691 spin_lock_bh(&sc->ani_lock);
2692 sc->sc_flags |= SC_OP_SCANNING;
2693 spin_unlock_bh(&sc->ani_lock);
2694 }
2695
2696 static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
2697 {
2698 struct ath_wiphy *aphy = hw->priv;
2699 struct ath_softc *sc = aphy->sc;
2700
2701 spin_lock_bh(&sc->ani_lock);
2702 aphy->state = ATH_WIPHY_ACTIVE;
2703 sc->sc_flags &= ~SC_OP_SCANNING;
2704 sc->sc_flags |= SC_OP_FULL_RESET;
2705 spin_unlock_bh(&sc->ani_lock);
2706 }
2707
2708 struct ieee80211_ops ath9k_ops = {
2709 .tx = ath9k_tx,
2710 .start = ath9k_start,
2711 .stop = ath9k_stop,
2712 .add_interface = ath9k_add_interface,
2713 .remove_interface = ath9k_remove_interface,
2714 .config = ath9k_config,
2715 .configure_filter = ath9k_configure_filter,
2716 .sta_notify = ath9k_sta_notify,
2717 .conf_tx = ath9k_conf_tx,
2718 .bss_info_changed = ath9k_bss_info_changed,
2719 .set_key = ath9k_set_key,
2720 .get_tsf = ath9k_get_tsf,
2721 .set_tsf = ath9k_set_tsf,
2722 .reset_tsf = ath9k_reset_tsf,
2723 .ampdu_action = ath9k_ampdu_action,
2724 .sw_scan_start = ath9k_sw_scan_start,
2725 .sw_scan_complete = ath9k_sw_scan_complete,
2726 .rfkill_poll = ath9k_rfkill_poll_state,
2727 };
2728
2729 static struct {
2730 u32 version;
2731 const char * name;
2732 } ath_mac_bb_names[] = {
2733 { AR_SREV_VERSION_5416_PCI, "5416" },
2734 { AR_SREV_VERSION_5416_PCIE, "5418" },
2735 { AR_SREV_VERSION_9100, "9100" },
2736 { AR_SREV_VERSION_9160, "9160" },
2737 { AR_SREV_VERSION_9280, "9280" },
2738 { AR_SREV_VERSION_9285, "9285" }
2739 };
2740
2741 static struct {
2742 u16 version;
2743 const char * name;
2744 } ath_rf_names[] = {
2745 { 0, "5133" },
2746 { AR_RAD5133_SREV_MAJOR, "5133" },
2747 { AR_RAD5122_SREV_MAJOR, "5122" },
2748 { AR_RAD2133_SREV_MAJOR, "2133" },
2749 { AR_RAD2122_SREV_MAJOR, "2122" }
2750 };
2751
2752 /*
2753 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2754 */
2755 const char *
2756 ath_mac_bb_name(u32 mac_bb_version)
2757 {
2758 int i;
2759
2760 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2761 if (ath_mac_bb_names[i].version == mac_bb_version) {
2762 return ath_mac_bb_names[i].name;
2763 }
2764 }
2765
2766 return "????";
2767 }
2768
2769 /*
2770 * Return the RF name. "????" is returned if the RF is unknown.
2771 */
2772 const char *
2773 ath_rf_name(u16 rf_version)
2774 {
2775 int i;
2776
2777 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2778 if (ath_rf_names[i].version == rf_version) {
2779 return ath_rf_names[i].name;
2780 }
2781 }
2782
2783 return "????";
2784 }
2785
2786 static int __init ath9k_init(void)
2787 {
2788 int error;
2789
2790 /* Register rate control algorithm */
2791 error = ath_rate_control_register();
2792 if (error != 0) {
2793 printk(KERN_ERR
2794 "ath9k: Unable to register rate control "
2795 "algorithm: %d\n",
2796 error);
2797 goto err_out;
2798 }
2799
2800 error = ath9k_debug_create_root();
2801 if (error) {
2802 printk(KERN_ERR
2803 "ath9k: Unable to create debugfs root: %d\n",
2804 error);
2805 goto err_rate_unregister;
2806 }
2807
2808 error = ath_pci_init();
2809 if (error < 0) {
2810 printk(KERN_ERR
2811 "ath9k: No PCI devices found, driver not installed.\n");
2812 error = -ENODEV;
2813 goto err_remove_root;
2814 }
2815
2816 error = ath_ahb_init();
2817 if (error < 0) {
2818 error = -ENODEV;
2819 goto err_pci_exit;
2820 }
2821
2822 return 0;
2823
2824 err_pci_exit:
2825 ath_pci_exit();
2826
2827 err_remove_root:
2828 ath9k_debug_remove_root();
2829 err_rate_unregister:
2830 ath_rate_control_unregister();
2831 err_out:
2832 return error;
2833 }
2834 module_init(ath9k_init);
2835
2836 static void __exit ath9k_exit(void)
2837 {
2838 ath_ahb_exit();
2839 ath_pci_exit();
2840 ath9k_debug_remove_root();
2841 ath_rate_control_unregister();
2842 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
2843 }
2844 module_exit(ath9k_exit);
Linux kernel - Deliverables
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