drivers/net/wireless/ath/ath9k/phy.c

   1 /*
   2  * Copyright (c) 2008-2009 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include "ath9k.h"
  18
  19 void
  20 ath9k_hw_write_regs(struct ath_hw *ah, u32 modesIndex, u32 freqIndex,
  21                     int regWrites)
  22 {
  23         REG_WRITE_ARRAY(&ah->iniBB_RfGain, freqIndex, regWrites);
  24 }
  25
  26 bool
  27 ath9k_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
  28 {
  29         u32 channelSel = 0;
  30         u32 bModeSynth = 0;
  31         u32 aModeRefSel = 0;
  32         u32 reg32 = 0;
  33         u16 freq;
  34         struct chan_centers centers;
  35
  36         ath9k_hw_get_channel_centers(ah, chan, &centers);
  37         freq = centers.synth_center;
  38
  39         if (freq < 4800) {
  40                 u32 txctl;
  41
  42                 if (((freq - 2192) % 5) == 0) {
  43                         channelSel = ((freq - 672) * 2 - 3040) / 10;
  44                         bModeSynth = 0;
  45                 } else if (((freq - 2224) % 5) == 0) {
  46                         channelSel = ((freq - 704) * 2 - 3040) / 10;
  47                         bModeSynth = 1;
  48                 } else {
  49                         DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
  50                                 "Invalid channel %u MHz\n", freq);
  51                         return false;
  52                 }
  53
  54                 channelSel = (channelSel << 2) & 0xff;
  55                 channelSel = ath9k_hw_reverse_bits(channelSel, 8);
  56
  57                 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
  58                 if (freq == 2484) {
  59
  60                         REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
  61                                   txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
  62                 } else {
  63                         REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
  64                                   txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN);
  65                 }
  66
  67         } else if ((freq % 20) == 0 && freq >= 5120) {
  68                 channelSel =
  69                     ath9k_hw_reverse_bits(((freq - 4800) / 20 << 2), 8);
  70                 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
  71         } else if ((freq % 10) == 0) {
  72                 channelSel =
  73                     ath9k_hw_reverse_bits(((freq - 4800) / 10 << 1), 8);
  74                 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah))
  75                         aModeRefSel = ath9k_hw_reverse_bits(2, 2);
  76                 else
  77                         aModeRefSel = ath9k_hw_reverse_bits(1, 2);
  78         } else if ((freq % 5) == 0) {
  79                 channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8);
  80                 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
  81         } else {
  82                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
  83                         "Invalid channel %u MHz\n", freq);
  84                 return false;
  85         }
  86
  87         reg32 =
  88             (channelSel << 8) | (aModeRefSel << 2) | (bModeSynth << 1) |
  89             (1 << 5) | 0x1;
  90
  91         REG_WRITE(ah, AR_PHY(0x37), reg32);
  92
  93         ah->curchan = chan;
  94         ah->curchan_rad_index = -1;
  95
  96         return true;
  97 }
  98
  99 void ath9k_hw_ar9280_set_channel(struct ath_hw *ah,
 100                                  struct ath9k_channel *chan)
 101 {
 102         u16 bMode, fracMode, aModeRefSel = 0;
 103         u32 freq, ndiv, channelSel = 0, channelFrac = 0, reg32 = 0;
 104         struct chan_centers centers;
 105         u32 refDivA = 24;
 106
 107         ath9k_hw_get_channel_centers(ah, chan, &centers);
 108         freq = centers.synth_center;
 109
 110         reg32 = REG_READ(ah, AR_PHY_SYNTH_CONTROL);
 111         reg32 &= 0xc0000000;
 112
 113         if (freq < 4800) {
 114                 u32 txctl;
 115
 116                 bMode = 1;
 117                 fracMode = 1;
 118                 aModeRefSel = 0;
 119                 channelSel = (freq * 0x10000) / 15;
 120
 121                 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
 122                 if (freq == 2484) {
 123
 124                         REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
 125                                   txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
 126                 } else {
 127                         REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
 128                                   txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN);
 129                 }
 130         } else {
 131                 bMode = 0;
 132                 fracMode = 0;
 133
 134                 switch(ah->eep_ops->get_eeprom(ah, EEP_FRAC_N_5G)) {
 135                 case 0:
 136                         if ((freq % 20) == 0) {
 137                                 aModeRefSel = 3;
 138                         } else if ((freq % 10) == 0) {
 139                                 aModeRefSel = 2;
 140                         }
 141                         if (aModeRefSel)
 142                                 break;
 143                 case 1:
 144                 default:
 145                         aModeRefSel = 0;
 146                         fracMode = 1;
 147                         refDivA = 1;
 148                         channelSel = (freq * 0x8000) / 15;
 149
 150                         REG_RMW_FIELD(ah, AR_AN_SYNTH9,
 151                                       AR_AN_SYNTH9_REFDIVA, refDivA);
 152
 153                 }
 154
 155                 if (!fracMode) {
 156                         ndiv = (freq * (refDivA >> aModeRefSel)) / 60;
 157                         channelSel = ndiv & 0x1ff;
 158                         channelFrac = (ndiv & 0xfffffe00) * 2;
 159                         channelSel = (channelSel << 17) | channelFrac;
 160                 }
 161         }
 162
 163         reg32 = reg32 |
 164             (bMode << 29) |
 165             (fracMode << 28) | (aModeRefSel << 26) | (channelSel);
 166
 167         REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
 168
 169         ah->curchan = chan;
 170         ah->curchan_rad_index = -1;
 171 }
 172
 173 static void
 174 ath9k_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32,
 175                            u32 numBits, u32 firstBit,
 176                            u32 column)
 177 {
 178         u32 tmp32, mask, arrayEntry, lastBit;
 179         int32_t bitPosition, bitsLeft;
 180
 181         tmp32 = ath9k_hw_reverse_bits(reg32, numBits);
 182         arrayEntry = (firstBit - 1) / 8;
 183         bitPosition = (firstBit - 1) % 8;
 184         bitsLeft = numBits;
 185         while (bitsLeft > 0) {
 186                 lastBit = (bitPosition + bitsLeft > 8) ?
 187                     8 : bitPosition + bitsLeft;
 188                 mask = (((1 << lastBit) - 1) ^ ((1 << bitPosition) - 1)) <<
 189                     (column * 8);
 190                 rfBuf[arrayEntry] &= ~mask;
 191                 rfBuf[arrayEntry] |= ((tmp32 << bitPosition) <<
 192                                       (column * 8)) & mask;
 193                 bitsLeft -= 8 - bitPosition;
 194                 tmp32 = tmp32 >> (8 - bitPosition);
 195                 bitPosition = 0;
 196                 arrayEntry++;
 197         }
 198 }
 199
 200 bool
 201 ath9k_hw_set_rf_regs(struct ath_hw *ah, struct ath9k_channel *chan,
 202                      u16 modesIndex)
 203 {
 204         u32 eepMinorRev;
 205         u32 ob5GHz = 0, db5GHz = 0;
 206         u32 ob2GHz = 0, db2GHz = 0;
 207         int regWrites = 0;
 208
 209         if (AR_SREV_9280_10_OR_LATER(ah))
 210                 return true;
 211
 212         eepMinorRev = ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV);
 213
 214         RF_BANK_SETUP(ah->analogBank0Data, &ah->iniBank0, 1);
 215
 216         RF_BANK_SETUP(ah->analogBank1Data, &ah->iniBank1, 1);
 217
 218         RF_BANK_SETUP(ah->analogBank2Data, &ah->iniBank2, 1);
 219
 220         RF_BANK_SETUP(ah->analogBank3Data, &ah->iniBank3,
 221                       modesIndex);
 222         {
 223                 int i;
 224                 for (i = 0; i < ah->iniBank6TPC.ia_rows; i++) {
 225                         ah->analogBank6Data[i] =
 226                             INI_RA(&ah->iniBank6TPC, i, modesIndex);
 227                 }
 228         }
 229
 230         if (eepMinorRev >= 2) {
 231                 if (IS_CHAN_2GHZ(chan)) {
 232                         ob2GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_2);
 233                         db2GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_2);
 234                         ath9k_phy_modify_rx_buffer(ah->analogBank6Data,
 235                                                    ob2GHz, 3, 197, 0);
 236                         ath9k_phy_modify_rx_buffer(ah->analogBank6Data,
 237                                                    db2GHz, 3, 194, 0);
 238                 } else {
 239                         ob5GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_5);
 240                         db5GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_5);
 241                         ath9k_phy_modify_rx_buffer(ah->analogBank6Data,
 242                                                    ob5GHz, 3, 203, 0);
 243                         ath9k_phy_modify_rx_buffer(ah->analogBank6Data,
 244                                                    db5GHz, 3, 200, 0);
 245                 }
 246         }
 247
 248         RF_BANK_SETUP(ah->analogBank7Data, &ah->iniBank7, 1);
 249
 250         REG_WRITE_RF_ARRAY(&ah->iniBank0, ah->analogBank0Data,
 251                            regWrites);
 252         REG_WRITE_RF_ARRAY(&ah->iniBank1, ah->analogBank1Data,
 253                            regWrites);
 254         REG_WRITE_RF_ARRAY(&ah->iniBank2, ah->analogBank2Data,
 255                            regWrites);
 256         REG_WRITE_RF_ARRAY(&ah->iniBank3, ah->analogBank3Data,
 257                            regWrites);
 258         REG_WRITE_RF_ARRAY(&ah->iniBank6TPC, ah->analogBank6Data,
 259                            regWrites);
 260         REG_WRITE_RF_ARRAY(&ah->iniBank7, ah->analogBank7Data,
 261                            regWrites);
 262
 263         return true;
 264 }
 265
 266 void
 267 ath9k_hw_rf_free(struct ath_hw *ah)
 268 {
 269 #define ATH_FREE_BANK(bank) do { \
 270                 kfree(bank); \
 271                 bank = NULL; \
 272         } while (0);
 273
 274         ATH_FREE_BANK(ah->analogBank0Data);
 275         ATH_FREE_BANK(ah->analogBank1Data);
 276         ATH_FREE_BANK(ah->analogBank2Data);
 277         ATH_FREE_BANK(ah->analogBank3Data);
 278         ATH_FREE_BANK(ah->analogBank6Data);
 279         ATH_FREE_BANK(ah->analogBank6TPCData);
 280         ATH_FREE_BANK(ah->analogBank7Data);
 281         ATH_FREE_BANK(ah->addac5416_21);
 282         ATH_FREE_BANK(ah->bank6Temp);
 283 #undef ATH_FREE_BANK
 284 }
 285
 286 bool ath9k_hw_init_rf(struct ath_hw *ah, int *status)
 287 {
 288         if (!AR_SREV_9280_10_OR_LATER(ah)) {
 289                 ah->analogBank0Data =
 290                     kzalloc((sizeof(u32) *
 291                              ah->iniBank0.ia_rows), GFP_KERNEL);
 292                 ah->analogBank1Data =
 293                     kzalloc((sizeof(u32) *
 294                              ah->iniBank1.ia_rows), GFP_KERNEL);
 295                 ah->analogBank2Data =
 296                     kzalloc((sizeof(u32) *
 297                              ah->iniBank2.ia_rows), GFP_KERNEL);
 298                 ah->analogBank3Data =
 299                     kzalloc((sizeof(u32) *
 300                              ah->iniBank3.ia_rows), GFP_KERNEL);
 301                 ah->analogBank6Data =
 302                     kzalloc((sizeof(u32) *
 303                              ah->iniBank6.ia_rows), GFP_KERNEL);
 304                 ah->analogBank6TPCData =
 305                     kzalloc((sizeof(u32) *
 306                              ah->iniBank6TPC.ia_rows), GFP_KERNEL);
 307                 ah->analogBank7Data =
 308                     kzalloc((sizeof(u32) *
 309                              ah->iniBank7.ia_rows), GFP_KERNEL);
 310
 311                 if (ah->analogBank0Data == NULL
 312                     || ah->analogBank1Data == NULL
 313                     || ah->analogBank2Data == NULL
 314                     || ah->analogBank3Data == NULL
 315                     || ah->analogBank6Data == NULL
 316                     || ah->analogBank6TPCData == NULL
 317                     || ah->analogBank7Data == NULL) {
 318                         DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
 319                                 "Cannot allocate RF banks\n");
 320                         *status = -ENOMEM;
 321                         return false;
 322                 }
 323
 324                 ah->addac5416_21 =
 325                     kzalloc((sizeof(u32) *
 326                              ah->iniAddac.ia_rows *
 327                              ah->iniAddac.ia_columns), GFP_KERNEL);
 328                 if (ah->addac5416_21 == NULL) {
 329                         DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
 330                                 "Cannot allocate addac5416_21\n");
 331                         *status = -ENOMEM;
 332                         return false;
 333                 }
 334
 335                 ah->bank6Temp =
 336                     kzalloc((sizeof(u32) *
 337                              ah->iniBank6.ia_rows), GFP_KERNEL);
 338                 if (ah->bank6Temp == NULL) {
 339                         DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
 340                                 "Cannot allocate bank6Temp\n");
 341                         *status = -ENOMEM;
 342                         return false;
 343                 }
 344         }
 345
 346         return true;
 347 }
 348
 349 void
 350 ath9k_hw_decrease_chain_power(struct ath_hw *ah, struct ath9k_channel *chan)
 351 {
 352         int i, regWrites = 0;
 353         u32 bank6SelMask;
 354         u32 *bank6Temp = ah->bank6Temp;
 355
 356         switch (ah->diversity_control) {
 357         case ATH9K_ANT_FIXED_A:
 358                 bank6SelMask =
 359                     (ah->
 360                      antenna_switch_swap & ANTSWAP_AB) ? REDUCE_CHAIN_0 :
 361                     REDUCE_CHAIN_1;
 362                 break;
 363         case ATH9K_ANT_FIXED_B:
 364                 bank6SelMask =
 365                     (ah->
 366                      antenna_switch_swap & ANTSWAP_AB) ? REDUCE_CHAIN_1 :
 367                     REDUCE_CHAIN_0;
 368                 break;
 369         case ATH9K_ANT_VARIABLE:
 370                 return;
 371                 break;
 372         default:
 373                 return;
 374                 break;
 375         }
 376
 377         for (i = 0; i < ah->iniBank6.ia_rows; i++)
 378                 bank6Temp[i] = ah->analogBank6Data[i];
 379
 380         REG_WRITE(ah, AR_PHY_BASE + 0xD8, bank6SelMask);
 381
 382         ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 189, 0);
 383         ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 190, 0);
 384         ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 191, 0);
 385         ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 192, 0);
 386         ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 193, 0);
 387         ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 222, 0);
 388         ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 245, 0);
 389         ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 246, 0);
 390         ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 247, 0);
 391
 392         REG_WRITE_RF_ARRAY(&ah->iniBank6, bank6Temp, regWrites);
 393
 394         REG_WRITE(ah, AR_PHY_BASE + 0xD8, 0x00000053);
 395 #ifdef ALTER_SWITCH
 396         REG_WRITE(ah, PHY_SWITCH_CHAIN_0,
 397                   (REG_READ(ah, PHY_SWITCH_CHAIN_0) & ~0x38)
 398                   | ((REG_READ(ah, PHY_SWITCH_CHAIN_0) >> 3) & 0x38));
 399 #endif
 400 }