2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/dma-mapping.h>
19 #include "ar9003_mac.h"
21 #define SKB_CB_ATHBUF(__skb) (*((struct ath_buf **)__skb->cb))
23 static inline bool ath9k_check_auto_sleep(struct ath_softc
*sc
)
25 return sc
->ps_enabled
&&
26 (sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_AUTOSLEEP
);
30 * Setup and link descriptors.
32 * 11N: we can no longer afford to self link the last descriptor.
33 * MAC acknowledges BA status as long as it copies frames to host
34 * buffer (or rx fifo). This can incorrectly acknowledge packets
35 * to a sender if last desc is self-linked.
37 static void ath_rx_buf_link(struct ath_softc
*sc
, struct ath_buf
*bf
)
39 struct ath_hw
*ah
= sc
->sc_ah
;
40 struct ath_common
*common
= ath9k_hw_common(ah
);
47 ds
->ds_link
= 0; /* link to null */
48 ds
->ds_data
= bf
->bf_buf_addr
;
50 /* virtual addr of the beginning of the buffer. */
53 ds
->ds_vdata
= skb
->data
;
56 * setup rx descriptors. The rx_bufsize here tells the hardware
57 * how much data it can DMA to us and that we are prepared
60 ath9k_hw_setuprxdesc(ah
, ds
,
64 if (sc
->rx
.rxlink
== NULL
)
65 ath9k_hw_putrxbuf(ah
, bf
->bf_daddr
);
67 *sc
->rx
.rxlink
= bf
->bf_daddr
;
69 sc
->rx
.rxlink
= &ds
->ds_link
;
72 static void ath_setdefantenna(struct ath_softc
*sc
, u32 antenna
)
74 /* XXX block beacon interrupts */
75 ath9k_hw_setantenna(sc
->sc_ah
, antenna
);
76 sc
->rx
.defant
= antenna
;
77 sc
->rx
.rxotherant
= 0;
80 static void ath_opmode_init(struct ath_softc
*sc
)
82 struct ath_hw
*ah
= sc
->sc_ah
;
83 struct ath_common
*common
= ath9k_hw_common(ah
);
87 /* configure rx filter */
88 rfilt
= ath_calcrxfilter(sc
);
89 ath9k_hw_setrxfilter(ah
, rfilt
);
91 /* configure bssid mask */
92 ath_hw_setbssidmask(common
);
94 /* configure operational mode */
95 ath9k_hw_setopmode(ah
);
97 /* calculate and install multicast filter */
98 mfilt
[0] = mfilt
[1] = ~0;
99 ath9k_hw_setmcastfilter(ah
, mfilt
[0], mfilt
[1]);
102 static bool ath_rx_edma_buf_link(struct ath_softc
*sc
,
103 enum ath9k_rx_qtype qtype
)
105 struct ath_hw
*ah
= sc
->sc_ah
;
106 struct ath_rx_edma
*rx_edma
;
110 rx_edma
= &sc
->rx
.rx_edma
[qtype
];
111 if (skb_queue_len(&rx_edma
->rx_fifo
) >= rx_edma
->rx_fifo_hwsize
)
114 bf
= list_first_entry(&sc
->rx
.rxbuf
, struct ath_buf
, list
);
115 list_del_init(&bf
->list
);
120 memset(skb
->data
, 0, ah
->caps
.rx_status_len
);
121 dma_sync_single_for_device(sc
->dev
, bf
->bf_buf_addr
,
122 ah
->caps
.rx_status_len
, DMA_TO_DEVICE
);
124 SKB_CB_ATHBUF(skb
) = bf
;
125 ath9k_hw_addrxbuf_edma(ah
, bf
->bf_buf_addr
, qtype
);
126 skb_queue_tail(&rx_edma
->rx_fifo
, skb
);
131 static void ath_rx_addbuffer_edma(struct ath_softc
*sc
,
132 enum ath9k_rx_qtype qtype
, int size
)
134 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
135 struct ath_buf
*bf
, *tbf
;
137 if (list_empty(&sc
->rx
.rxbuf
)) {
138 ath_dbg(common
, QUEUE
, "No free rx buf available\n");
142 list_for_each_entry_safe(bf
, tbf
, &sc
->rx
.rxbuf
, list
)
143 if (!ath_rx_edma_buf_link(sc
, qtype
))
148 static void ath_rx_remove_buffer(struct ath_softc
*sc
,
149 enum ath9k_rx_qtype qtype
)
152 struct ath_rx_edma
*rx_edma
;
155 rx_edma
= &sc
->rx
.rx_edma
[qtype
];
157 while ((skb
= skb_dequeue(&rx_edma
->rx_fifo
)) != NULL
) {
158 bf
= SKB_CB_ATHBUF(skb
);
160 list_add_tail(&bf
->list
, &sc
->rx
.rxbuf
);
164 static void ath_rx_edma_cleanup(struct ath_softc
*sc
)
166 struct ath_hw
*ah
= sc
->sc_ah
;
167 struct ath_common
*common
= ath9k_hw_common(ah
);
170 ath_rx_remove_buffer(sc
, ATH9K_RX_QUEUE_LP
);
171 ath_rx_remove_buffer(sc
, ATH9K_RX_QUEUE_HP
);
173 list_for_each_entry(bf
, &sc
->rx
.rxbuf
, list
) {
175 dma_unmap_single(sc
->dev
, bf
->bf_buf_addr
,
178 dev_kfree_skb_any(bf
->bf_mpdu
);
184 INIT_LIST_HEAD(&sc
->rx
.rxbuf
);
186 kfree(sc
->rx
.rx_bufptr
);
187 sc
->rx
.rx_bufptr
= NULL
;
190 static void ath_rx_edma_init_queue(struct ath_rx_edma
*rx_edma
, int size
)
192 skb_queue_head_init(&rx_edma
->rx_fifo
);
193 rx_edma
->rx_fifo_hwsize
= size
;
196 static int ath_rx_edma_init(struct ath_softc
*sc
, int nbufs
)
198 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
199 struct ath_hw
*ah
= sc
->sc_ah
;
205 ath9k_hw_set_rx_bufsize(ah
, common
->rx_bufsize
-
206 ah
->caps
.rx_status_len
);
208 ath_rx_edma_init_queue(&sc
->rx
.rx_edma
[ATH9K_RX_QUEUE_LP
],
209 ah
->caps
.rx_lp_qdepth
);
210 ath_rx_edma_init_queue(&sc
->rx
.rx_edma
[ATH9K_RX_QUEUE_HP
],
211 ah
->caps
.rx_hp_qdepth
);
213 size
= sizeof(struct ath_buf
) * nbufs
;
214 bf
= kzalloc(size
, GFP_KERNEL
);
218 INIT_LIST_HEAD(&sc
->rx
.rxbuf
);
219 sc
->rx
.rx_bufptr
= bf
;
221 for (i
= 0; i
< nbufs
; i
++, bf
++) {
222 skb
= ath_rxbuf_alloc(common
, common
->rx_bufsize
, GFP_KERNEL
);
228 memset(skb
->data
, 0, common
->rx_bufsize
);
231 bf
->bf_buf_addr
= dma_map_single(sc
->dev
, skb
->data
,
234 if (unlikely(dma_mapping_error(sc
->dev
,
236 dev_kfree_skb_any(skb
);
240 "dma_mapping_error() on RX init\n");
245 list_add_tail(&bf
->list
, &sc
->rx
.rxbuf
);
251 ath_rx_edma_cleanup(sc
);
255 static void ath_edma_start_recv(struct ath_softc
*sc
)
257 spin_lock_bh(&sc
->rx
.rxbuflock
);
259 ath9k_hw_rxena(sc
->sc_ah
);
261 ath_rx_addbuffer_edma(sc
, ATH9K_RX_QUEUE_HP
,
262 sc
->rx
.rx_edma
[ATH9K_RX_QUEUE_HP
].rx_fifo_hwsize
);
264 ath_rx_addbuffer_edma(sc
, ATH9K_RX_QUEUE_LP
,
265 sc
->rx
.rx_edma
[ATH9K_RX_QUEUE_LP
].rx_fifo_hwsize
);
269 ath9k_hw_startpcureceive(sc
->sc_ah
, !!(sc
->hw
->conf
.flags
& IEEE80211_CONF_OFFCHANNEL
));
271 spin_unlock_bh(&sc
->rx
.rxbuflock
);
274 static void ath_edma_stop_recv(struct ath_softc
*sc
)
276 ath_rx_remove_buffer(sc
, ATH9K_RX_QUEUE_HP
);
277 ath_rx_remove_buffer(sc
, ATH9K_RX_QUEUE_LP
);
280 int ath_rx_init(struct ath_softc
*sc
, int nbufs
)
282 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
287 spin_lock_init(&sc
->sc_pcu_lock
);
288 spin_lock_init(&sc
->rx
.rxbuflock
);
289 clear_bit(SC_OP_RXFLUSH
, &sc
->sc_flags
);
291 common
->rx_bufsize
= IEEE80211_MAX_MPDU_LEN
/ 2 +
292 sc
->sc_ah
->caps
.rx_status_len
;
294 if (sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_EDMA
) {
295 return ath_rx_edma_init(sc
, nbufs
);
297 ath_dbg(common
, CONFIG
, "cachelsz %u rxbufsize %u\n",
298 common
->cachelsz
, common
->rx_bufsize
);
300 /* Initialize rx descriptors */
302 error
= ath_descdma_setup(sc
, &sc
->rx
.rxdma
, &sc
->rx
.rxbuf
,
306 "failed to allocate rx descriptors: %d\n",
311 list_for_each_entry(bf
, &sc
->rx
.rxbuf
, list
) {
312 skb
= ath_rxbuf_alloc(common
, common
->rx_bufsize
,
320 bf
->bf_buf_addr
= dma_map_single(sc
->dev
, skb
->data
,
323 if (unlikely(dma_mapping_error(sc
->dev
,
325 dev_kfree_skb_any(skb
);
329 "dma_mapping_error() on RX init\n");
334 sc
->rx
.rxlink
= NULL
;
344 void ath_rx_cleanup(struct ath_softc
*sc
)
346 struct ath_hw
*ah
= sc
->sc_ah
;
347 struct ath_common
*common
= ath9k_hw_common(ah
);
351 if (sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_EDMA
) {
352 ath_rx_edma_cleanup(sc
);
355 list_for_each_entry(bf
, &sc
->rx
.rxbuf
, list
) {
358 dma_unmap_single(sc
->dev
, bf
->bf_buf_addr
,
367 if (sc
->rx
.rxdma
.dd_desc_len
!= 0)
368 ath_descdma_cleanup(sc
, &sc
->rx
.rxdma
, &sc
->rx
.rxbuf
);
373 * Calculate the receive filter according to the
374 * operating mode and state:
376 * o always accept unicast, broadcast, and multicast traffic
377 * o maintain current state of phy error reception (the hal
378 * may enable phy error frames for noise immunity work)
379 * o probe request frames are accepted only when operating in
380 * hostap, adhoc, or monitor modes
381 * o enable promiscuous mode according to the interface state
383 * - when operating in adhoc mode so the 802.11 layer creates
384 * node table entries for peers,
385 * - when operating in station mode for collecting rssi data when
386 * the station is otherwise quiet, or
387 * - when operating as a repeater so we see repeater-sta beacons
391 u32
ath_calcrxfilter(struct ath_softc
*sc
)
395 rfilt
= ATH9K_RX_FILTER_UCAST
| ATH9K_RX_FILTER_BCAST
396 | ATH9K_RX_FILTER_MCAST
;
398 if (sc
->rx
.rxfilter
& FIF_PROBE_REQ
)
399 rfilt
|= ATH9K_RX_FILTER_PROBEREQ
;
402 * Set promiscuous mode when FIF_PROMISC_IN_BSS is enabled for station
403 * mode interface or when in monitor mode. AP mode does not need this
404 * since it receives all in-BSS frames anyway.
406 if (sc
->sc_ah
->is_monitoring
)
407 rfilt
|= ATH9K_RX_FILTER_PROM
;
409 if (sc
->rx
.rxfilter
& FIF_CONTROL
)
410 rfilt
|= ATH9K_RX_FILTER_CONTROL
;
412 if ((sc
->sc_ah
->opmode
== NL80211_IFTYPE_STATION
) &&
414 !(sc
->rx
.rxfilter
& FIF_BCN_PRBRESP_PROMISC
))
415 rfilt
|= ATH9K_RX_FILTER_MYBEACON
;
417 rfilt
|= ATH9K_RX_FILTER_BEACON
;
419 if ((sc
->sc_ah
->opmode
== NL80211_IFTYPE_AP
) ||
420 (sc
->rx
.rxfilter
& FIF_PSPOLL
))
421 rfilt
|= ATH9K_RX_FILTER_PSPOLL
;
423 if (conf_is_ht(&sc
->hw
->conf
))
424 rfilt
|= ATH9K_RX_FILTER_COMP_BAR
;
426 if (sc
->nvifs
> 1 || (sc
->rx
.rxfilter
& FIF_OTHER_BSS
)) {
427 /* This is needed for older chips */
428 if (sc
->sc_ah
->hw_version
.macVersion
<= AR_SREV_VERSION_9160
)
429 rfilt
|= ATH9K_RX_FILTER_PROM
;
430 rfilt
|= ATH9K_RX_FILTER_MCAST_BCAST_ALL
;
433 if (AR_SREV_9550(sc
->sc_ah
))
434 rfilt
|= ATH9K_RX_FILTER_4ADDRESS
;
440 int ath_startrecv(struct ath_softc
*sc
)
442 struct ath_hw
*ah
= sc
->sc_ah
;
443 struct ath_buf
*bf
, *tbf
;
445 if (ah
->caps
.hw_caps
& ATH9K_HW_CAP_EDMA
) {
446 ath_edma_start_recv(sc
);
450 spin_lock_bh(&sc
->rx
.rxbuflock
);
451 if (list_empty(&sc
->rx
.rxbuf
))
454 sc
->rx
.rxlink
= NULL
;
455 list_for_each_entry_safe(bf
, tbf
, &sc
->rx
.rxbuf
, list
) {
456 ath_rx_buf_link(sc
, bf
);
459 /* We could have deleted elements so the list may be empty now */
460 if (list_empty(&sc
->rx
.rxbuf
))
463 bf
= list_first_entry(&sc
->rx
.rxbuf
, struct ath_buf
, list
);
464 ath9k_hw_putrxbuf(ah
, bf
->bf_daddr
);
469 ath9k_hw_startpcureceive(ah
, !!(sc
->hw
->conf
.flags
& IEEE80211_CONF_OFFCHANNEL
));
471 spin_unlock_bh(&sc
->rx
.rxbuflock
);
476 bool ath_stoprecv(struct ath_softc
*sc
)
478 struct ath_hw
*ah
= sc
->sc_ah
;
479 bool stopped
, reset
= false;
481 spin_lock_bh(&sc
->rx
.rxbuflock
);
482 ath9k_hw_abortpcurecv(ah
);
483 ath9k_hw_setrxfilter(ah
, 0);
484 stopped
= ath9k_hw_stopdmarecv(ah
, &reset
);
486 if (sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_EDMA
)
487 ath_edma_stop_recv(sc
);
489 sc
->rx
.rxlink
= NULL
;
490 spin_unlock_bh(&sc
->rx
.rxbuflock
);
492 if (!(ah
->ah_flags
& AH_UNPLUGGED
) &&
493 unlikely(!stopped
)) {
494 ath_err(ath9k_hw_common(sc
->sc_ah
),
495 "Could not stop RX, we could be "
496 "confusing the DMA engine when we start RX up\n");
497 ATH_DBG_WARN_ON_ONCE(!stopped
);
499 return stopped
&& !reset
;
502 void ath_flushrecv(struct ath_softc
*sc
)
504 set_bit(SC_OP_RXFLUSH
, &sc
->sc_flags
);
505 if (sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_EDMA
)
506 ath_rx_tasklet(sc
, 1, true);
507 ath_rx_tasklet(sc
, 1, false);
508 clear_bit(SC_OP_RXFLUSH
, &sc
->sc_flags
);
511 static bool ath_beacon_dtim_pending_cab(struct sk_buff
*skb
)
513 /* Check whether the Beacon frame has DTIM indicating buffered bc/mc */
514 struct ieee80211_mgmt
*mgmt
;
515 u8
*pos
, *end
, id
, elen
;
516 struct ieee80211_tim_ie
*tim
;
518 mgmt
= (struct ieee80211_mgmt
*)skb
->data
;
519 pos
= mgmt
->u
.beacon
.variable
;
520 end
= skb
->data
+ skb
->len
;
522 while (pos
+ 2 < end
) {
525 if (pos
+ elen
> end
)
528 if (id
== WLAN_EID_TIM
) {
529 if (elen
< sizeof(*tim
))
531 tim
= (struct ieee80211_tim_ie
*) pos
;
532 if (tim
->dtim_count
!= 0)
534 return tim
->bitmap_ctrl
& 0x01;
543 static void ath_rx_ps_beacon(struct ath_softc
*sc
, struct sk_buff
*skb
)
545 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
547 if (skb
->len
< 24 + 8 + 2 + 2)
550 sc
->ps_flags
&= ~PS_WAIT_FOR_BEACON
;
552 if (sc
->ps_flags
& PS_BEACON_SYNC
) {
553 sc
->ps_flags
&= ~PS_BEACON_SYNC
;
555 "Reconfigure Beacon timers based on timestamp from the AP\n");
556 ath9k_set_beacon(sc
);
559 if (ath_beacon_dtim_pending_cab(skb
)) {
561 * Remain awake waiting for buffered broadcast/multicast
562 * frames. If the last broadcast/multicast frame is not
563 * received properly, the next beacon frame will work as
564 * a backup trigger for returning into NETWORK SLEEP state,
565 * so we are waiting for it as well.
568 "Received DTIM beacon indicating buffered broadcast/multicast frame(s)\n");
569 sc
->ps_flags
|= PS_WAIT_FOR_CAB
| PS_WAIT_FOR_BEACON
;
573 if (sc
->ps_flags
& PS_WAIT_FOR_CAB
) {
575 * This can happen if a broadcast frame is dropped or the AP
576 * fails to send a frame indicating that all CAB frames have
579 sc
->ps_flags
&= ~PS_WAIT_FOR_CAB
;
580 ath_dbg(common
, PS
, "PS wait for CAB frames timed out\n");
584 static void ath_rx_ps(struct ath_softc
*sc
, struct sk_buff
*skb
, bool mybeacon
)
586 struct ieee80211_hdr
*hdr
;
587 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
589 hdr
= (struct ieee80211_hdr
*)skb
->data
;
591 /* Process Beacon and CAB receive in PS state */
592 if (((sc
->ps_flags
& PS_WAIT_FOR_BEACON
) || ath9k_check_auto_sleep(sc
))
594 ath_rx_ps_beacon(sc
, skb
);
595 } else if ((sc
->ps_flags
& PS_WAIT_FOR_CAB
) &&
596 (ieee80211_is_data(hdr
->frame_control
) ||
597 ieee80211_is_action(hdr
->frame_control
)) &&
598 is_multicast_ether_addr(hdr
->addr1
) &&
599 !ieee80211_has_moredata(hdr
->frame_control
)) {
601 * No more broadcast/multicast frames to be received at this
604 sc
->ps_flags
&= ~(PS_WAIT_FOR_CAB
| PS_WAIT_FOR_BEACON
);
606 "All PS CAB frames received, back to sleep\n");
607 } else if ((sc
->ps_flags
& PS_WAIT_FOR_PSPOLL_DATA
) &&
608 !is_multicast_ether_addr(hdr
->addr1
) &&
609 !ieee80211_has_morefrags(hdr
->frame_control
)) {
610 sc
->ps_flags
&= ~PS_WAIT_FOR_PSPOLL_DATA
;
612 "Going back to sleep after having received PS-Poll data (0x%lx)\n",
613 sc
->ps_flags
& (PS_WAIT_FOR_BEACON
|
615 PS_WAIT_FOR_PSPOLL_DATA
|
616 PS_WAIT_FOR_TX_ACK
));
620 static bool ath_edma_get_buffers(struct ath_softc
*sc
,
621 enum ath9k_rx_qtype qtype
,
622 struct ath_rx_status
*rs
,
623 struct ath_buf
**dest
)
625 struct ath_rx_edma
*rx_edma
= &sc
->rx
.rx_edma
[qtype
];
626 struct ath_hw
*ah
= sc
->sc_ah
;
627 struct ath_common
*common
= ath9k_hw_common(ah
);
632 skb
= skb_peek(&rx_edma
->rx_fifo
);
636 bf
= SKB_CB_ATHBUF(skb
);
639 dma_sync_single_for_cpu(sc
->dev
, bf
->bf_buf_addr
,
640 common
->rx_bufsize
, DMA_FROM_DEVICE
);
642 ret
= ath9k_hw_process_rxdesc_edma(ah
, rs
, skb
->data
);
643 if (ret
== -EINPROGRESS
) {
644 /*let device gain the buffer again*/
645 dma_sync_single_for_device(sc
->dev
, bf
->bf_buf_addr
,
646 common
->rx_bufsize
, DMA_FROM_DEVICE
);
650 __skb_unlink(skb
, &rx_edma
->rx_fifo
);
651 if (ret
== -EINVAL
) {
652 /* corrupt descriptor, skip this one and the following one */
653 list_add_tail(&bf
->list
, &sc
->rx
.rxbuf
);
654 ath_rx_edma_buf_link(sc
, qtype
);
656 skb
= skb_peek(&rx_edma
->rx_fifo
);
658 bf
= SKB_CB_ATHBUF(skb
);
661 __skb_unlink(skb
, &rx_edma
->rx_fifo
);
662 list_add_tail(&bf
->list
, &sc
->rx
.rxbuf
);
663 ath_rx_edma_buf_link(sc
, qtype
);
673 static struct ath_buf
*ath_edma_get_next_rx_buf(struct ath_softc
*sc
,
674 struct ath_rx_status
*rs
,
675 enum ath9k_rx_qtype qtype
)
677 struct ath_buf
*bf
= NULL
;
679 while (ath_edma_get_buffers(sc
, qtype
, rs
, &bf
)) {
688 static struct ath_buf
*ath_get_next_rx_buf(struct ath_softc
*sc
,
689 struct ath_rx_status
*rs
)
691 struct ath_hw
*ah
= sc
->sc_ah
;
692 struct ath_common
*common
= ath9k_hw_common(ah
);
697 if (list_empty(&sc
->rx
.rxbuf
)) {
698 sc
->rx
.rxlink
= NULL
;
702 bf
= list_first_entry(&sc
->rx
.rxbuf
, struct ath_buf
, list
);
706 * Must provide the virtual address of the current
707 * descriptor, the physical address, and the virtual
708 * address of the next descriptor in the h/w chain.
709 * This allows the HAL to look ahead to see if the
710 * hardware is done with a descriptor by checking the
711 * done bit in the following descriptor and the address
712 * of the current descriptor the DMA engine is working
713 * on. All this is necessary because of our use of
714 * a self-linked list to avoid rx overruns.
716 ret
= ath9k_hw_rxprocdesc(ah
, ds
, rs
);
717 if (ret
== -EINPROGRESS
) {
718 struct ath_rx_status trs
;
720 struct ath_desc
*tds
;
722 memset(&trs
, 0, sizeof(trs
));
723 if (list_is_last(&bf
->list
, &sc
->rx
.rxbuf
)) {
724 sc
->rx
.rxlink
= NULL
;
728 tbf
= list_entry(bf
->list
.next
, struct ath_buf
, list
);
731 * On some hardware the descriptor status words could
732 * get corrupted, including the done bit. Because of
733 * this, check if the next descriptor's done bit is
736 * If the next descriptor's done bit is set, the current
737 * descriptor has been corrupted. Force s/w to discard
738 * this descriptor and continue...
742 ret
= ath9k_hw_rxprocdesc(ah
, tds
, &trs
);
743 if (ret
== -EINPROGRESS
)
751 * Synchronize the DMA transfer with CPU before
752 * 1. accessing the frame
753 * 2. requeueing the same buffer to h/w
755 dma_sync_single_for_cpu(sc
->dev
, bf
->bf_buf_addr
,
762 /* Assumes you've already done the endian to CPU conversion */
763 static bool ath9k_rx_accept(struct ath_common
*common
,
764 struct ieee80211_hdr
*hdr
,
765 struct ieee80211_rx_status
*rxs
,
766 struct ath_rx_status
*rx_stats
,
769 struct ath_softc
*sc
= (struct ath_softc
*) common
->priv
;
770 bool is_mc
, is_valid_tkip
, strip_mic
, mic_error
;
771 struct ath_hw
*ah
= common
->ah
;
773 u8 rx_status_len
= ah
->caps
.rx_status_len
;
775 fc
= hdr
->frame_control
;
777 is_mc
= !!is_multicast_ether_addr(hdr
->addr1
);
778 is_valid_tkip
= rx_stats
->rs_keyix
!= ATH9K_RXKEYIX_INVALID
&&
779 test_bit(rx_stats
->rs_keyix
, common
->tkip_keymap
);
780 strip_mic
= is_valid_tkip
&& ieee80211_is_data(fc
) &&
781 ieee80211_has_protected(fc
) &&
782 !(rx_stats
->rs_status
&
783 (ATH9K_RXERR_DECRYPT
| ATH9K_RXERR_CRC
| ATH9K_RXERR_MIC
|
784 ATH9K_RXERR_KEYMISS
));
787 * Key miss events are only relevant for pairwise keys where the
788 * descriptor does contain a valid key index. This has been observed
789 * mostly with CCMP encryption.
791 if (rx_stats
->rs_keyix
== ATH9K_RXKEYIX_INVALID
||
792 !test_bit(rx_stats
->rs_keyix
, common
->ccmp_keymap
))
793 rx_stats
->rs_status
&= ~ATH9K_RXERR_KEYMISS
;
795 if (!rx_stats
->rs_datalen
) {
796 RX_STAT_INC(rx_len_err
);
801 * rs_status follows rs_datalen so if rs_datalen is too large
802 * we can take a hint that hardware corrupted it, so ignore
805 if (rx_stats
->rs_datalen
> (common
->rx_bufsize
- rx_status_len
)) {
806 RX_STAT_INC(rx_len_err
);
810 /* Only use error bits from the last fragment */
811 if (rx_stats
->rs_more
)
814 mic_error
= is_valid_tkip
&& !ieee80211_is_ctl(fc
) &&
815 !ieee80211_has_morefrags(fc
) &&
816 !(le16_to_cpu(hdr
->seq_ctrl
) & IEEE80211_SCTL_FRAG
) &&
817 (rx_stats
->rs_status
& ATH9K_RXERR_MIC
);
820 * The rx_stats->rs_status will not be set until the end of the
821 * chained descriptors so it can be ignored if rs_more is set. The
822 * rs_more will be false at the last element of the chained
825 if (rx_stats
->rs_status
!= 0) {
828 if (rx_stats
->rs_status
& ATH9K_RXERR_CRC
) {
829 rxs
->flag
|= RX_FLAG_FAILED_FCS_CRC
;
832 if (rx_stats
->rs_status
& ATH9K_RXERR_PHY
)
835 if ((rx_stats
->rs_status
& ATH9K_RXERR_DECRYPT
) ||
836 (!is_mc
&& (rx_stats
->rs_status
& ATH9K_RXERR_KEYMISS
))) {
837 *decrypt_error
= true;
842 * Reject error frames with the exception of
843 * decryption and MIC failures. For monitor mode,
844 * we also ignore the CRC error.
846 status_mask
= ATH9K_RXERR_DECRYPT
| ATH9K_RXERR_MIC
|
849 if (ah
->is_monitoring
&& (sc
->rx
.rxfilter
& FIF_FCSFAIL
))
850 status_mask
|= ATH9K_RXERR_CRC
;
852 if (rx_stats
->rs_status
& ~status_mask
)
857 * For unicast frames the MIC error bit can have false positives,
858 * so all MIC error reports need to be validated in software.
859 * False negatives are not common, so skip software verification
860 * if the hardware considers the MIC valid.
863 rxs
->flag
|= RX_FLAG_MMIC_STRIPPED
;
864 else if (is_mc
&& mic_error
)
865 rxs
->flag
|= RX_FLAG_MMIC_ERROR
;
870 static int ath9k_process_rate(struct ath_common
*common
,
871 struct ieee80211_hw
*hw
,
872 struct ath_rx_status
*rx_stats
,
873 struct ieee80211_rx_status
*rxs
)
875 struct ieee80211_supported_band
*sband
;
876 enum ieee80211_band band
;
878 struct ath_softc __maybe_unused
*sc
= common
->priv
;
880 band
= hw
->conf
.channel
->band
;
881 sband
= hw
->wiphy
->bands
[band
];
883 if (rx_stats
->rs_rate
& 0x80) {
885 rxs
->flag
|= RX_FLAG_HT
;
886 if (rx_stats
->rs_flags
& ATH9K_RX_2040
)
887 rxs
->flag
|= RX_FLAG_40MHZ
;
888 if (rx_stats
->rs_flags
& ATH9K_RX_GI
)
889 rxs
->flag
|= RX_FLAG_SHORT_GI
;
890 rxs
->rate_idx
= rx_stats
->rs_rate
& 0x7f;
894 for (i
= 0; i
< sband
->n_bitrates
; i
++) {
895 if (sband
->bitrates
[i
].hw_value
== rx_stats
->rs_rate
) {
899 if (sband
->bitrates
[i
].hw_value_short
== rx_stats
->rs_rate
) {
900 rxs
->flag
|= RX_FLAG_SHORTPRE
;
907 * No valid hardware bitrate found -- we should not get here
908 * because hardware has already validated this frame as OK.
911 "unsupported hw bitrate detected 0x%02x using 1 Mbit\n",
913 RX_STAT_INC(rx_rate_err
);
917 static void ath9k_process_rssi(struct ath_common
*common
,
918 struct ieee80211_hw
*hw
,
919 struct ieee80211_hdr
*hdr
,
920 struct ath_rx_status
*rx_stats
)
922 struct ath_softc
*sc
= hw
->priv
;
923 struct ath_hw
*ah
= common
->ah
;
925 int rssi
= rx_stats
->rs_rssi
;
927 if (!rx_stats
->is_mybeacon
||
928 ((ah
->opmode
!= NL80211_IFTYPE_STATION
) &&
929 (ah
->opmode
!= NL80211_IFTYPE_ADHOC
)))
932 if (rx_stats
->rs_rssi
!= ATH9K_RSSI_BAD
&& !rx_stats
->rs_moreaggr
)
933 ATH_RSSI_LPF(sc
->last_rssi
, rx_stats
->rs_rssi
);
935 last_rssi
= sc
->last_rssi
;
936 if (likely(last_rssi
!= ATH_RSSI_DUMMY_MARKER
))
937 rssi
= ATH_EP_RND(last_rssi
, ATH_RSSI_EP_MULTIPLIER
);
941 /* Update Beacon RSSI, this is used by ANI. */
942 ah
->stats
.avgbrssi
= rssi
;
946 * For Decrypt or Demic errors, we only mark packet status here and always push
947 * up the frame up to let mac80211 handle the actual error case, be it no
948 * decryption key or real decryption error. This let us keep statistics there.
950 static int ath9k_rx_skb_preprocess(struct ath_common
*common
,
951 struct ieee80211_hw
*hw
,
952 struct ieee80211_hdr
*hdr
,
953 struct ath_rx_status
*rx_stats
,
954 struct ieee80211_rx_status
*rx_status
,
957 struct ath_hw
*ah
= common
->ah
;
960 * everything but the rate is checked here, the rate check is done
961 * separately to avoid doing two lookups for a rate for each frame.
963 if (!ath9k_rx_accept(common
, hdr
, rx_status
, rx_stats
, decrypt_error
))
966 /* Only use status info from the last fragment */
967 if (rx_stats
->rs_more
)
970 ath9k_process_rssi(common
, hw
, hdr
, rx_stats
);
972 if (ath9k_process_rate(common
, hw
, rx_stats
, rx_status
))
975 rx_status
->band
= hw
->conf
.channel
->band
;
976 rx_status
->freq
= hw
->conf
.channel
->center_freq
;
977 rx_status
->signal
= ah
->noise
+ rx_stats
->rs_rssi
;
978 rx_status
->antenna
= rx_stats
->rs_antenna
;
979 rx_status
->flag
|= RX_FLAG_MACTIME_END
;
980 if (rx_stats
->rs_moreaggr
)
981 rx_status
->flag
|= RX_FLAG_NO_SIGNAL_VAL
;
986 static void ath9k_rx_skb_postprocess(struct ath_common
*common
,
988 struct ath_rx_status
*rx_stats
,
989 struct ieee80211_rx_status
*rxs
,
992 struct ath_hw
*ah
= common
->ah
;
993 struct ieee80211_hdr
*hdr
;
994 int hdrlen
, padpos
, padsize
;
998 /* see if any padding is done by the hw and remove it */
999 hdr
= (struct ieee80211_hdr
*) skb
->data
;
1000 hdrlen
= ieee80211_get_hdrlen_from_skb(skb
);
1001 fc
= hdr
->frame_control
;
1002 padpos
= ath9k_cmn_padpos(hdr
->frame_control
);
1004 /* The MAC header is padded to have 32-bit boundary if the
1005 * packet payload is non-zero. The general calculation for
1006 * padsize would take into account odd header lengths:
1007 * padsize = (4 - padpos % 4) % 4; However, since only
1008 * even-length headers are used, padding can only be 0 or 2
1009 * bytes and we can optimize this a bit. In addition, we must
1010 * not try to remove padding from short control frames that do
1011 * not have payload. */
1012 padsize
= padpos
& 3;
1013 if (padsize
&& skb
->len
>=padpos
+padsize
+FCS_LEN
) {
1014 memmove(skb
->data
+ padsize
, skb
->data
, padpos
);
1015 skb_pull(skb
, padsize
);
1018 keyix
= rx_stats
->rs_keyix
;
1020 if (!(keyix
== ATH9K_RXKEYIX_INVALID
) && !decrypt_error
&&
1021 ieee80211_has_protected(fc
)) {
1022 rxs
->flag
|= RX_FLAG_DECRYPTED
;
1023 } else if (ieee80211_has_protected(fc
)
1024 && !decrypt_error
&& skb
->len
>= hdrlen
+ 4) {
1025 keyix
= skb
->data
[hdrlen
+ 3] >> 6;
1027 if (test_bit(keyix
, common
->keymap
))
1028 rxs
->flag
|= RX_FLAG_DECRYPTED
;
1030 if (ah
->sw_mgmt_crypto
&&
1031 (rxs
->flag
& RX_FLAG_DECRYPTED
) &&
1032 ieee80211_is_mgmt(fc
))
1033 /* Use software decrypt for management frames. */
1034 rxs
->flag
&= ~RX_FLAG_DECRYPTED
;
1037 int ath_rx_tasklet(struct ath_softc
*sc
, int flush
, bool hp
)
1040 struct sk_buff
*skb
= NULL
, *requeue_skb
, *hdr_skb
;
1041 struct ieee80211_rx_status
*rxs
;
1042 struct ath_hw
*ah
= sc
->sc_ah
;
1043 struct ath_common
*common
= ath9k_hw_common(ah
);
1044 struct ieee80211_hw
*hw
= sc
->hw
;
1045 struct ieee80211_hdr
*hdr
;
1047 struct ath_rx_status rs
;
1048 enum ath9k_rx_qtype qtype
;
1049 bool edma
= !!(ah
->caps
.hw_caps
& ATH9K_HW_CAP_EDMA
);
1051 u8 rx_status_len
= ah
->caps
.rx_status_len
;
1054 unsigned long flags
;
1057 dma_type
= DMA_BIDIRECTIONAL
;
1059 dma_type
= DMA_FROM_DEVICE
;
1061 qtype
= hp
? ATH9K_RX_QUEUE_HP
: ATH9K_RX_QUEUE_LP
;
1062 spin_lock_bh(&sc
->rx
.rxbuflock
);
1064 tsf
= ath9k_hw_gettsf64(ah
);
1065 tsf_lower
= tsf
& 0xffffffff;
1068 bool decrypt_error
= false;
1069 /* If handling rx interrupt and flush is in progress => exit */
1070 if (test_bit(SC_OP_RXFLUSH
, &sc
->sc_flags
) && (flush
== 0))
1073 memset(&rs
, 0, sizeof(rs
));
1075 bf
= ath_edma_get_next_rx_buf(sc
, &rs
, qtype
);
1077 bf
= ath_get_next_rx_buf(sc
, &rs
);
1087 * Take frame header from the first fragment and RX status from
1091 hdr_skb
= sc
->rx
.frag
;
1095 hdr
= (struct ieee80211_hdr
*) (hdr_skb
->data
+ rx_status_len
);
1096 rxs
= IEEE80211_SKB_RXCB(hdr_skb
);
1097 if (ieee80211_is_beacon(hdr
->frame_control
)) {
1098 RX_STAT_INC(rx_beacons
);
1099 if (!is_zero_ether_addr(common
->curbssid
) &&
1100 ether_addr_equal(hdr
->addr3
, common
->curbssid
))
1101 rs
.is_mybeacon
= true;
1103 rs
.is_mybeacon
= false;
1106 rs
.is_mybeacon
= false;
1108 if (ieee80211_is_data_present(hdr
->frame_control
) &&
1109 !ieee80211_is_qos_nullfunc(hdr
->frame_control
))
1112 ath_debug_stat_rx(sc
, &rs
);
1115 * If we're asked to flush receive queue, directly
1116 * chain it back at the queue without processing it.
1118 if (test_bit(SC_OP_RXFLUSH
, &sc
->sc_flags
)) {
1119 RX_STAT_INC(rx_drop_rxflush
);
1120 goto requeue_drop_frag
;
1123 memset(rxs
, 0, sizeof(struct ieee80211_rx_status
));
1125 rxs
->mactime
= (tsf
& ~0xffffffffULL
) | rs
.rs_tstamp
;
1126 if (rs
.rs_tstamp
> tsf_lower
&&
1127 unlikely(rs
.rs_tstamp
- tsf_lower
> 0x10000000))
1128 rxs
->mactime
-= 0x100000000ULL
;
1130 if (rs
.rs_tstamp
< tsf_lower
&&
1131 unlikely(tsf_lower
- rs
.rs_tstamp
> 0x10000000))
1132 rxs
->mactime
+= 0x100000000ULL
;
1134 retval
= ath9k_rx_skb_preprocess(common
, hw
, hdr
, &rs
,
1135 rxs
, &decrypt_error
);
1137 goto requeue_drop_frag
;
1139 if (rs
.is_mybeacon
) {
1140 sc
->hw_busy_count
= 0;
1141 ath_start_rx_poll(sc
, 3);
1143 /* Ensure we always have an skb to requeue once we are done
1144 * processing the current buffer's skb */
1145 requeue_skb
= ath_rxbuf_alloc(common
, common
->rx_bufsize
, GFP_ATOMIC
);
1147 /* If there is no memory we ignore the current RX'd frame,
1148 * tell hardware it can give us a new frame using the old
1149 * skb and put it at the tail of the sc->rx.rxbuf list for
1152 RX_STAT_INC(rx_oom_err
);
1153 goto requeue_drop_frag
;
1156 /* Unmap the frame */
1157 dma_unmap_single(sc
->dev
, bf
->bf_buf_addr
,
1161 skb_put(skb
, rs
.rs_datalen
+ ah
->caps
.rx_status_len
);
1162 if (ah
->caps
.rx_status_len
)
1163 skb_pull(skb
, ah
->caps
.rx_status_len
);
1166 ath9k_rx_skb_postprocess(common
, hdr_skb
, &rs
,
1167 rxs
, decrypt_error
);
1169 /* We will now give hardware our shiny new allocated skb */
1170 bf
->bf_mpdu
= requeue_skb
;
1171 bf
->bf_buf_addr
= dma_map_single(sc
->dev
, requeue_skb
->data
,
1174 if (unlikely(dma_mapping_error(sc
->dev
,
1175 bf
->bf_buf_addr
))) {
1176 dev_kfree_skb_any(requeue_skb
);
1178 bf
->bf_buf_addr
= 0;
1179 ath_err(common
, "dma_mapping_error() on RX\n");
1180 ieee80211_rx(hw
, skb
);
1185 RX_STAT_INC(rx_frags
);
1187 * rs_more indicates chained descriptors which can be
1188 * used to link buffers together for a sort of
1189 * scatter-gather operation.
1192 /* too many fragments - cannot handle frame */
1193 dev_kfree_skb_any(sc
->rx
.frag
);
1194 dev_kfree_skb_any(skb
);
1195 RX_STAT_INC(rx_too_many_frags_err
);
1203 int space
= skb
->len
- skb_tailroom(hdr_skb
);
1205 if (pskb_expand_head(hdr_skb
, 0, space
, GFP_ATOMIC
) < 0) {
1207 RX_STAT_INC(rx_oom_err
);
1208 goto requeue_drop_frag
;
1213 skb_copy_from_linear_data(skb
, skb_put(hdr_skb
, skb
->len
),
1215 dev_kfree_skb_any(skb
);
1220 if (ah
->caps
.hw_caps
& ATH9K_HW_CAP_ANT_DIV_COMB
) {
1223 * change the default rx antenna if rx diversity
1224 * chooses the other antenna 3 times in a row.
1226 if (sc
->rx
.defant
!= rs
.rs_antenna
) {
1227 if (++sc
->rx
.rxotherant
>= 3)
1228 ath_setdefantenna(sc
, rs
.rs_antenna
);
1230 sc
->rx
.rxotherant
= 0;
1235 if (rxs
->flag
& RX_FLAG_MMIC_STRIPPED
)
1236 skb_trim(skb
, skb
->len
- 8);
1238 spin_lock_irqsave(&sc
->sc_pm_lock
, flags
);
1239 if ((sc
->ps_flags
& (PS_WAIT_FOR_BEACON
|
1241 PS_WAIT_FOR_PSPOLL_DATA
)) ||
1242 ath9k_check_auto_sleep(sc
))
1243 ath_rx_ps(sc
, skb
, rs
.is_mybeacon
);
1244 spin_unlock_irqrestore(&sc
->sc_pm_lock
, flags
);
1246 if ((ah
->caps
.hw_caps
& ATH9K_HW_CAP_ANT_DIV_COMB
) && sc
->ant_rx
== 3)
1247 ath_ant_comb_scan(sc
, &rs
);
1249 ieee80211_rx(hw
, skb
);
1253 dev_kfree_skb_any(sc
->rx
.frag
);
1258 list_add_tail(&bf
->list
, &sc
->rx
.rxbuf
);
1259 ath_rx_edma_buf_link(sc
, qtype
);
1261 list_move_tail(&bf
->list
, &sc
->rx
.rxbuf
);
1262 ath_rx_buf_link(sc
, bf
);
1268 spin_unlock_bh(&sc
->rx
.rxbuflock
);
1270 if (!(ah
->imask
& ATH9K_INT_RXEOL
)) {
1271 ah
->imask
|= (ATH9K_INT_RXEOL
| ATH9K_INT_RXORN
);
1272 ath9k_hw_set_interrupts(ah
);