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ath9k: Fix compile warnings when DEBUGFS is disabled.
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / recv.c
1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/dma-mapping.h>
18 #include "ath9k.h"
19 #include "ar9003_mac.h"
20
21 #define SKB_CB_ATHBUF(__skb) (*((struct ath_buf **)__skb->cb))
22
23 static inline bool ath_is_alt_ant_ratio_better(int alt_ratio, int maxdelta,
24 int mindelta, int main_rssi_avg,
25 int alt_rssi_avg, int pkt_count)
26 {
27 return (((alt_ratio >= ATH_ANT_DIV_COMB_ALT_ANT_RATIO2) &&
28 (alt_rssi_avg > main_rssi_avg + maxdelta)) ||
29 (alt_rssi_avg > main_rssi_avg + mindelta)) && (pkt_count > 50);
30 }
31
32 static inline bool ath_ant_div_comb_alt_check(u8 div_group, int alt_ratio,
33 int curr_main_set, int curr_alt_set,
34 int alt_rssi_avg, int main_rssi_avg)
35 {
36 bool result = false;
37 switch (div_group) {
38 case 0:
39 if (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO)
40 result = true;
41 break;
42 case 1:
43 case 2:
44 if ((((curr_main_set == ATH_ANT_DIV_COMB_LNA2) &&
45 (curr_alt_set == ATH_ANT_DIV_COMB_LNA1) &&
46 (alt_rssi_avg >= (main_rssi_avg - 5))) ||
47 ((curr_main_set == ATH_ANT_DIV_COMB_LNA1) &&
48 (curr_alt_set == ATH_ANT_DIV_COMB_LNA2) &&
49 (alt_rssi_avg >= (main_rssi_avg - 2)))) &&
50 (alt_rssi_avg >= 4))
51 result = true;
52 else
53 result = false;
54 break;
55 }
56
57 return result;
58 }
59
60 static inline bool ath9k_check_auto_sleep(struct ath_softc *sc)
61 {
62 return sc->ps_enabled &&
63 (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP);
64 }
65
66 /*
67 * Setup and link descriptors.
68 *
69 * 11N: we can no longer afford to self link the last descriptor.
70 * MAC acknowledges BA status as long as it copies frames to host
71 * buffer (or rx fifo). This can incorrectly acknowledge packets
72 * to a sender if last desc is self-linked.
73 */
74 static void ath_rx_buf_link(struct ath_softc *sc, struct ath_buf *bf)
75 {
76 struct ath_hw *ah = sc->sc_ah;
77 struct ath_common *common = ath9k_hw_common(ah);
78 struct ath_desc *ds;
79 struct sk_buff *skb;
80
81 ATH_RXBUF_RESET(bf);
82
83 ds = bf->bf_desc;
84 ds->ds_link = 0; /* link to null */
85 ds->ds_data = bf->bf_buf_addr;
86
87 /* virtual addr of the beginning of the buffer. */
88 skb = bf->bf_mpdu;
89 BUG_ON(skb == NULL);
90 ds->ds_vdata = skb->data;
91
92 /*
93 * setup rx descriptors. The rx_bufsize here tells the hardware
94 * how much data it can DMA to us and that we are prepared
95 * to process
96 */
97 ath9k_hw_setuprxdesc(ah, ds,
98 common->rx_bufsize,
99 0);
100
101 if (sc->rx.rxlink == NULL)
102 ath9k_hw_putrxbuf(ah, bf->bf_daddr);
103 else
104 *sc->rx.rxlink = bf->bf_daddr;
105
106 sc->rx.rxlink = &ds->ds_link;
107 }
108
109 static void ath_setdefantenna(struct ath_softc *sc, u32 antenna)
110 {
111 /* XXX block beacon interrupts */
112 ath9k_hw_setantenna(sc->sc_ah, antenna);
113 sc->rx.defant = antenna;
114 sc->rx.rxotherant = 0;
115 }
116
117 static void ath_opmode_init(struct ath_softc *sc)
118 {
119 struct ath_hw *ah = sc->sc_ah;
120 struct ath_common *common = ath9k_hw_common(ah);
121
122 u32 rfilt, mfilt[2];
123
124 /* configure rx filter */
125 rfilt = ath_calcrxfilter(sc);
126 ath9k_hw_setrxfilter(ah, rfilt);
127
128 /* configure bssid mask */
129 ath_hw_setbssidmask(common);
130
131 /* configure operational mode */
132 ath9k_hw_setopmode(ah);
133
134 /* calculate and install multicast filter */
135 mfilt[0] = mfilt[1] = ~0;
136 ath9k_hw_setmcastfilter(ah, mfilt[0], mfilt[1]);
137 }
138
139 static bool ath_rx_edma_buf_link(struct ath_softc *sc,
140 enum ath9k_rx_qtype qtype)
141 {
142 struct ath_hw *ah = sc->sc_ah;
143 struct ath_rx_edma *rx_edma;
144 struct sk_buff *skb;
145 struct ath_buf *bf;
146
147 rx_edma = &sc->rx.rx_edma[qtype];
148 if (skb_queue_len(&rx_edma->rx_fifo) >= rx_edma->rx_fifo_hwsize)
149 return false;
150
151 bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
152 list_del_init(&bf->list);
153
154 skb = bf->bf_mpdu;
155
156 ATH_RXBUF_RESET(bf);
157 memset(skb->data, 0, ah->caps.rx_status_len);
158 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
159 ah->caps.rx_status_len, DMA_TO_DEVICE);
160
161 SKB_CB_ATHBUF(skb) = bf;
162 ath9k_hw_addrxbuf_edma(ah, bf->bf_buf_addr, qtype);
163 skb_queue_tail(&rx_edma->rx_fifo, skb);
164
165 return true;
166 }
167
168 static void ath_rx_addbuffer_edma(struct ath_softc *sc,
169 enum ath9k_rx_qtype qtype, int size)
170 {
171 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
172 struct ath_buf *bf, *tbf;
173
174 if (list_empty(&sc->rx.rxbuf)) {
175 ath_dbg(common, QUEUE, "No free rx buf available\n");
176 return;
177 }
178
179 list_for_each_entry_safe(bf, tbf, &sc->rx.rxbuf, list)
180 if (!ath_rx_edma_buf_link(sc, qtype))
181 break;
182
183 }
184
185 static void ath_rx_remove_buffer(struct ath_softc *sc,
186 enum ath9k_rx_qtype qtype)
187 {
188 struct ath_buf *bf;
189 struct ath_rx_edma *rx_edma;
190 struct sk_buff *skb;
191
192 rx_edma = &sc->rx.rx_edma[qtype];
193
194 while ((skb = skb_dequeue(&rx_edma->rx_fifo)) != NULL) {
195 bf = SKB_CB_ATHBUF(skb);
196 BUG_ON(!bf);
197 list_add_tail(&bf->list, &sc->rx.rxbuf);
198 }
199 }
200
201 static void ath_rx_edma_cleanup(struct ath_softc *sc)
202 {
203 struct ath_hw *ah = sc->sc_ah;
204 struct ath_common *common = ath9k_hw_common(ah);
205 struct ath_buf *bf;
206
207 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP);
208 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP);
209
210 list_for_each_entry(bf, &sc->rx.rxbuf, list) {
211 if (bf->bf_mpdu) {
212 dma_unmap_single(sc->dev, bf->bf_buf_addr,
213 common->rx_bufsize,
214 DMA_BIDIRECTIONAL);
215 dev_kfree_skb_any(bf->bf_mpdu);
216 bf->bf_buf_addr = 0;
217 bf->bf_mpdu = NULL;
218 }
219 }
220
221 INIT_LIST_HEAD(&sc->rx.rxbuf);
222
223 kfree(sc->rx.rx_bufptr);
224 sc->rx.rx_bufptr = NULL;
225 }
226
227 static void ath_rx_edma_init_queue(struct ath_rx_edma *rx_edma, int size)
228 {
229 skb_queue_head_init(&rx_edma->rx_fifo);
230 rx_edma->rx_fifo_hwsize = size;
231 }
232
233 static int ath_rx_edma_init(struct ath_softc *sc, int nbufs)
234 {
235 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
236 struct ath_hw *ah = sc->sc_ah;
237 struct sk_buff *skb;
238 struct ath_buf *bf;
239 int error = 0, i;
240 u32 size;
241
242 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
243 ah->caps.rx_status_len);
244
245 ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_LP],
246 ah->caps.rx_lp_qdepth);
247 ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_HP],
248 ah->caps.rx_hp_qdepth);
249
250 size = sizeof(struct ath_buf) * nbufs;
251 bf = kzalloc(size, GFP_KERNEL);
252 if (!bf)
253 return -ENOMEM;
254
255 INIT_LIST_HEAD(&sc->rx.rxbuf);
256 sc->rx.rx_bufptr = bf;
257
258 for (i = 0; i < nbufs; i++, bf++) {
259 skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_KERNEL);
260 if (!skb) {
261 error = -ENOMEM;
262 goto rx_init_fail;
263 }
264
265 memset(skb->data, 0, common->rx_bufsize);
266 bf->bf_mpdu = skb;
267
268 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
269 common->rx_bufsize,
270 DMA_BIDIRECTIONAL);
271 if (unlikely(dma_mapping_error(sc->dev,
272 bf->bf_buf_addr))) {
273 dev_kfree_skb_any(skb);
274 bf->bf_mpdu = NULL;
275 bf->bf_buf_addr = 0;
276 ath_err(common,
277 "dma_mapping_error() on RX init\n");
278 error = -ENOMEM;
279 goto rx_init_fail;
280 }
281
282 list_add_tail(&bf->list, &sc->rx.rxbuf);
283 }
284
285 return 0;
286
287 rx_init_fail:
288 ath_rx_edma_cleanup(sc);
289 return error;
290 }
291
292 static void ath_edma_start_recv(struct ath_softc *sc)
293 {
294 spin_lock_bh(&sc->rx.rxbuflock);
295
296 ath9k_hw_rxena(sc->sc_ah);
297
298 ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_HP,
299 sc->rx.rx_edma[ATH9K_RX_QUEUE_HP].rx_fifo_hwsize);
300
301 ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_LP,
302 sc->rx.rx_edma[ATH9K_RX_QUEUE_LP].rx_fifo_hwsize);
303
304 ath_opmode_init(sc);
305
306 ath9k_hw_startpcureceive(sc->sc_ah, (sc->sc_flags & SC_OP_OFFCHANNEL));
307
308 spin_unlock_bh(&sc->rx.rxbuflock);
309 }
310
311 static void ath_edma_stop_recv(struct ath_softc *sc)
312 {
313 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP);
314 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP);
315 }
316
317 int ath_rx_init(struct ath_softc *sc, int nbufs)
318 {
319 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
320 struct sk_buff *skb;
321 struct ath_buf *bf;
322 int error = 0;
323
324 spin_lock_init(&sc->sc_pcu_lock);
325 sc->sc_flags &= ~SC_OP_RXFLUSH;
326 spin_lock_init(&sc->rx.rxbuflock);
327
328 common->rx_bufsize = IEEE80211_MAX_MPDU_LEN / 2 +
329 sc->sc_ah->caps.rx_status_len;
330
331 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
332 return ath_rx_edma_init(sc, nbufs);
333 } else {
334 ath_dbg(common, CONFIG, "cachelsz %u rxbufsize %u\n",
335 common->cachelsz, common->rx_bufsize);
336
337 /* Initialize rx descriptors */
338
339 error = ath_descdma_setup(sc, &sc->rx.rxdma, &sc->rx.rxbuf,
340 "rx", nbufs, 1, 0);
341 if (error != 0) {
342 ath_err(common,
343 "failed to allocate rx descriptors: %d\n",
344 error);
345 goto err;
346 }
347
348 list_for_each_entry(bf, &sc->rx.rxbuf, list) {
349 skb = ath_rxbuf_alloc(common, common->rx_bufsize,
350 GFP_KERNEL);
351 if (skb == NULL) {
352 error = -ENOMEM;
353 goto err;
354 }
355
356 bf->bf_mpdu = skb;
357 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
358 common->rx_bufsize,
359 DMA_FROM_DEVICE);
360 if (unlikely(dma_mapping_error(sc->dev,
361 bf->bf_buf_addr))) {
362 dev_kfree_skb_any(skb);
363 bf->bf_mpdu = NULL;
364 bf->bf_buf_addr = 0;
365 ath_err(common,
366 "dma_mapping_error() on RX init\n");
367 error = -ENOMEM;
368 goto err;
369 }
370 }
371 sc->rx.rxlink = NULL;
372 }
373
374 err:
375 if (error)
376 ath_rx_cleanup(sc);
377
378 return error;
379 }
380
381 void ath_rx_cleanup(struct ath_softc *sc)
382 {
383 struct ath_hw *ah = sc->sc_ah;
384 struct ath_common *common = ath9k_hw_common(ah);
385 struct sk_buff *skb;
386 struct ath_buf *bf;
387
388 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
389 ath_rx_edma_cleanup(sc);
390 return;
391 } else {
392 list_for_each_entry(bf, &sc->rx.rxbuf, list) {
393 skb = bf->bf_mpdu;
394 if (skb) {
395 dma_unmap_single(sc->dev, bf->bf_buf_addr,
396 common->rx_bufsize,
397 DMA_FROM_DEVICE);
398 dev_kfree_skb(skb);
399 bf->bf_buf_addr = 0;
400 bf->bf_mpdu = NULL;
401 }
402 }
403
404 if (sc->rx.rxdma.dd_desc_len != 0)
405 ath_descdma_cleanup(sc, &sc->rx.rxdma, &sc->rx.rxbuf);
406 }
407 }
408
409 /*
410 * Calculate the receive filter according to the
411 * operating mode and state:
412 *
413 * o always accept unicast, broadcast, and multicast traffic
414 * o maintain current state of phy error reception (the hal
415 * may enable phy error frames for noise immunity work)
416 * o probe request frames are accepted only when operating in
417 * hostap, adhoc, or monitor modes
418 * o enable promiscuous mode according to the interface state
419 * o accept beacons:
420 * - when operating in adhoc mode so the 802.11 layer creates
421 * node table entries for peers,
422 * - when operating in station mode for collecting rssi data when
423 * the station is otherwise quiet, or
424 * - when operating as a repeater so we see repeater-sta beacons
425 * - when scanning
426 */
427
428 u32 ath_calcrxfilter(struct ath_softc *sc)
429 {
430 u32 rfilt;
431
432 rfilt = ATH9K_RX_FILTER_UCAST | ATH9K_RX_FILTER_BCAST
433 | ATH9K_RX_FILTER_MCAST;
434
435 if (sc->rx.rxfilter & FIF_PROBE_REQ)
436 rfilt |= ATH9K_RX_FILTER_PROBEREQ;
437
438 /*
439 * Set promiscuous mode when FIF_PROMISC_IN_BSS is enabled for station
440 * mode interface or when in monitor mode. AP mode does not need this
441 * since it receives all in-BSS frames anyway.
442 */
443 if (sc->sc_ah->is_monitoring)
444 rfilt |= ATH9K_RX_FILTER_PROM;
445
446 if (sc->rx.rxfilter & FIF_CONTROL)
447 rfilt |= ATH9K_RX_FILTER_CONTROL;
448
449 if ((sc->sc_ah->opmode == NL80211_IFTYPE_STATION) &&
450 (sc->nvifs <= 1) &&
451 !(sc->rx.rxfilter & FIF_BCN_PRBRESP_PROMISC))
452 rfilt |= ATH9K_RX_FILTER_MYBEACON;
453 else
454 rfilt |= ATH9K_RX_FILTER_BEACON;
455
456 if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
457 (sc->rx.rxfilter & FIF_PSPOLL))
458 rfilt |= ATH9K_RX_FILTER_PSPOLL;
459
460 if (conf_is_ht(&sc->hw->conf))
461 rfilt |= ATH9K_RX_FILTER_COMP_BAR;
462
463 if (sc->nvifs > 1 || (sc->rx.rxfilter & FIF_OTHER_BSS)) {
464 /* The following may also be needed for other older chips */
465 if (sc->sc_ah->hw_version.macVersion == AR_SREV_VERSION_9160)
466 rfilt |= ATH9K_RX_FILTER_PROM;
467 rfilt |= ATH9K_RX_FILTER_MCAST_BCAST_ALL;
468 }
469
470 return rfilt;
471
472 }
473
474 int ath_startrecv(struct ath_softc *sc)
475 {
476 struct ath_hw *ah = sc->sc_ah;
477 struct ath_buf *bf, *tbf;
478
479 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
480 ath_edma_start_recv(sc);
481 return 0;
482 }
483
484 spin_lock_bh(&sc->rx.rxbuflock);
485 if (list_empty(&sc->rx.rxbuf))
486 goto start_recv;
487
488 sc->rx.rxlink = NULL;
489 list_for_each_entry_safe(bf, tbf, &sc->rx.rxbuf, list) {
490 ath_rx_buf_link(sc, bf);
491 }
492
493 /* We could have deleted elements so the list may be empty now */
494 if (list_empty(&sc->rx.rxbuf))
495 goto start_recv;
496
497 bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
498 ath9k_hw_putrxbuf(ah, bf->bf_daddr);
499 ath9k_hw_rxena(ah);
500
501 start_recv:
502 ath_opmode_init(sc);
503 ath9k_hw_startpcureceive(ah, (sc->sc_flags & SC_OP_OFFCHANNEL));
504
505 spin_unlock_bh(&sc->rx.rxbuflock);
506
507 return 0;
508 }
509
510 bool ath_stoprecv(struct ath_softc *sc)
511 {
512 struct ath_hw *ah = sc->sc_ah;
513 bool stopped, reset = false;
514
515 spin_lock_bh(&sc->rx.rxbuflock);
516 ath9k_hw_abortpcurecv(ah);
517 ath9k_hw_setrxfilter(ah, 0);
518 stopped = ath9k_hw_stopdmarecv(ah, &reset);
519
520 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
521 ath_edma_stop_recv(sc);
522 else
523 sc->rx.rxlink = NULL;
524 spin_unlock_bh(&sc->rx.rxbuflock);
525
526 if (!(ah->ah_flags & AH_UNPLUGGED) &&
527 unlikely(!stopped)) {
528 ath_err(ath9k_hw_common(sc->sc_ah),
529 "Could not stop RX, we could be "
530 "confusing the DMA engine when we start RX up\n");
531 ATH_DBG_WARN_ON_ONCE(!stopped);
532 }
533 return stopped && !reset;
534 }
535
536 void ath_flushrecv(struct ath_softc *sc)
537 {
538 sc->sc_flags |= SC_OP_RXFLUSH;
539 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
540 ath_rx_tasklet(sc, 1, true);
541 ath_rx_tasklet(sc, 1, false);
542 sc->sc_flags &= ~SC_OP_RXFLUSH;
543 }
544
545 static bool ath_beacon_dtim_pending_cab(struct sk_buff *skb)
546 {
547 /* Check whether the Beacon frame has DTIM indicating buffered bc/mc */
548 struct ieee80211_mgmt *mgmt;
549 u8 *pos, *end, id, elen;
550 struct ieee80211_tim_ie *tim;
551
552 mgmt = (struct ieee80211_mgmt *)skb->data;
553 pos = mgmt->u.beacon.variable;
554 end = skb->data + skb->len;
555
556 while (pos + 2 < end) {
557 id = *pos++;
558 elen = *pos++;
559 if (pos + elen > end)
560 break;
561
562 if (id == WLAN_EID_TIM) {
563 if (elen < sizeof(*tim))
564 break;
565 tim = (struct ieee80211_tim_ie *) pos;
566 if (tim->dtim_count != 0)
567 break;
568 return tim->bitmap_ctrl & 0x01;
569 }
570
571 pos += elen;
572 }
573
574 return false;
575 }
576
577 static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb)
578 {
579 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
580
581 if (skb->len < 24 + 8 + 2 + 2)
582 return;
583
584 sc->ps_flags &= ~PS_WAIT_FOR_BEACON;
585
586 if (sc->ps_flags & PS_BEACON_SYNC) {
587 sc->ps_flags &= ~PS_BEACON_SYNC;
588 ath_dbg(common, PS,
589 "Reconfigure Beacon timers based on timestamp from the AP\n");
590 ath_set_beacon(sc);
591 }
592
593 if (ath_beacon_dtim_pending_cab(skb)) {
594 /*
595 * Remain awake waiting for buffered broadcast/multicast
596 * frames. If the last broadcast/multicast frame is not
597 * received properly, the next beacon frame will work as
598 * a backup trigger for returning into NETWORK SLEEP state,
599 * so we are waiting for it as well.
600 */
601 ath_dbg(common, PS,
602 "Received DTIM beacon indicating buffered broadcast/multicast frame(s)\n");
603 sc->ps_flags |= PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON;
604 return;
605 }
606
607 if (sc->ps_flags & PS_WAIT_FOR_CAB) {
608 /*
609 * This can happen if a broadcast frame is dropped or the AP
610 * fails to send a frame indicating that all CAB frames have
611 * been delivered.
612 */
613 sc->ps_flags &= ~PS_WAIT_FOR_CAB;
614 ath_dbg(common, PS, "PS wait for CAB frames timed out\n");
615 }
616 }
617
618 static void ath_rx_ps(struct ath_softc *sc, struct sk_buff *skb, bool mybeacon)
619 {
620 struct ieee80211_hdr *hdr;
621 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
622
623 hdr = (struct ieee80211_hdr *)skb->data;
624
625 /* Process Beacon and CAB receive in PS state */
626 if (((sc->ps_flags & PS_WAIT_FOR_BEACON) || ath9k_check_auto_sleep(sc))
627 && mybeacon)
628 ath_rx_ps_beacon(sc, skb);
629 else if ((sc->ps_flags & PS_WAIT_FOR_CAB) &&
630 (ieee80211_is_data(hdr->frame_control) ||
631 ieee80211_is_action(hdr->frame_control)) &&
632 is_multicast_ether_addr(hdr->addr1) &&
633 !ieee80211_has_moredata(hdr->frame_control)) {
634 /*
635 * No more broadcast/multicast frames to be received at this
636 * point.
637 */
638 sc->ps_flags &= ~(PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON);
639 ath_dbg(common, PS,
640 "All PS CAB frames received, back to sleep\n");
641 } else if ((sc->ps_flags & PS_WAIT_FOR_PSPOLL_DATA) &&
642 !is_multicast_ether_addr(hdr->addr1) &&
643 !ieee80211_has_morefrags(hdr->frame_control)) {
644 sc->ps_flags &= ~PS_WAIT_FOR_PSPOLL_DATA;
645 ath_dbg(common, PS,
646 "Going back to sleep after having received PS-Poll data (0x%lx)\n",
647 sc->ps_flags & (PS_WAIT_FOR_BEACON |
648 PS_WAIT_FOR_CAB |
649 PS_WAIT_FOR_PSPOLL_DATA |
650 PS_WAIT_FOR_TX_ACK));
651 }
652 }
653
654 static bool ath_edma_get_buffers(struct ath_softc *sc,
655 enum ath9k_rx_qtype qtype,
656 struct ath_rx_status *rs,
657 struct ath_buf **dest)
658 {
659 struct ath_rx_edma *rx_edma = &sc->rx.rx_edma[qtype];
660 struct ath_hw *ah = sc->sc_ah;
661 struct ath_common *common = ath9k_hw_common(ah);
662 struct sk_buff *skb;
663 struct ath_buf *bf;
664 int ret;
665
666 skb = skb_peek(&rx_edma->rx_fifo);
667 if (!skb)
668 return false;
669
670 bf = SKB_CB_ATHBUF(skb);
671 BUG_ON(!bf);
672
673 dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr,
674 common->rx_bufsize, DMA_FROM_DEVICE);
675
676 ret = ath9k_hw_process_rxdesc_edma(ah, rs, skb->data);
677 if (ret == -EINPROGRESS) {
678 /*let device gain the buffer again*/
679 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
680 common->rx_bufsize, DMA_FROM_DEVICE);
681 return false;
682 }
683
684 __skb_unlink(skb, &rx_edma->rx_fifo);
685 if (ret == -EINVAL) {
686 /* corrupt descriptor, skip this one and the following one */
687 list_add_tail(&bf->list, &sc->rx.rxbuf);
688 ath_rx_edma_buf_link(sc, qtype);
689
690 skb = skb_peek(&rx_edma->rx_fifo);
691 if (skb) {
692 bf = SKB_CB_ATHBUF(skb);
693 BUG_ON(!bf);
694
695 __skb_unlink(skb, &rx_edma->rx_fifo);
696 list_add_tail(&bf->list, &sc->rx.rxbuf);
697 ath_rx_edma_buf_link(sc, qtype);
698 } else {
699 bf = NULL;
700 }
701 }
702
703 *dest = bf;
704 return true;
705 }
706
707 static struct ath_buf *ath_edma_get_next_rx_buf(struct ath_softc *sc,
708 struct ath_rx_status *rs,
709 enum ath9k_rx_qtype qtype)
710 {
711 struct ath_buf *bf = NULL;
712
713 while (ath_edma_get_buffers(sc, qtype, rs, &bf)) {
714 if (!bf)
715 continue;
716
717 return bf;
718 }
719 return NULL;
720 }
721
722 static struct ath_buf *ath_get_next_rx_buf(struct ath_softc *sc,
723 struct ath_rx_status *rs)
724 {
725 struct ath_hw *ah = sc->sc_ah;
726 struct ath_common *common = ath9k_hw_common(ah);
727 struct ath_desc *ds;
728 struct ath_buf *bf;
729 int ret;
730
731 if (list_empty(&sc->rx.rxbuf)) {
732 sc->rx.rxlink = NULL;
733 return NULL;
734 }
735
736 bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
737 ds = bf->bf_desc;
738
739 /*
740 * Must provide the virtual address of the current
741 * descriptor, the physical address, and the virtual
742 * address of the next descriptor in the h/w chain.
743 * This allows the HAL to look ahead to see if the
744 * hardware is done with a descriptor by checking the
745 * done bit in the following descriptor and the address
746 * of the current descriptor the DMA engine is working
747 * on. All this is necessary because of our use of
748 * a self-linked list to avoid rx overruns.
749 */
750 ret = ath9k_hw_rxprocdesc(ah, ds, rs);
751 if (ret == -EINPROGRESS) {
752 struct ath_rx_status trs;
753 struct ath_buf *tbf;
754 struct ath_desc *tds;
755
756 memset(&trs, 0, sizeof(trs));
757 if (list_is_last(&bf->list, &sc->rx.rxbuf)) {
758 sc->rx.rxlink = NULL;
759 return NULL;
760 }
761
762 tbf = list_entry(bf->list.next, struct ath_buf, list);
763
764 /*
765 * On some hardware the descriptor status words could
766 * get corrupted, including the done bit. Because of
767 * this, check if the next descriptor's done bit is
768 * set or not.
769 *
770 * If the next descriptor's done bit is set, the current
771 * descriptor has been corrupted. Force s/w to discard
772 * this descriptor and continue...
773 */
774
775 tds = tbf->bf_desc;
776 ret = ath9k_hw_rxprocdesc(ah, tds, &trs);
777 if (ret == -EINPROGRESS)
778 return NULL;
779 }
780
781 if (!bf->bf_mpdu)
782 return bf;
783
784 /*
785 * Synchronize the DMA transfer with CPU before
786 * 1. accessing the frame
787 * 2. requeueing the same buffer to h/w
788 */
789 dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr,
790 common->rx_bufsize,
791 DMA_FROM_DEVICE);
792
793 return bf;
794 }
795
796 /* Assumes you've already done the endian to CPU conversion */
797 static bool ath9k_rx_accept(struct ath_common *common,
798 struct ieee80211_hdr *hdr,
799 struct ieee80211_rx_status *rxs,
800 struct ath_rx_status *rx_stats,
801 bool *decrypt_error)
802 {
803 struct ath_softc *sc = (struct ath_softc *) common->priv;
804 bool is_mc, is_valid_tkip, strip_mic, mic_error;
805 struct ath_hw *ah = common->ah;
806 __le16 fc;
807 u8 rx_status_len = ah->caps.rx_status_len;
808
809 fc = hdr->frame_control;
810
811 is_mc = !!is_multicast_ether_addr(hdr->addr1);
812 is_valid_tkip = rx_stats->rs_keyix != ATH9K_RXKEYIX_INVALID &&
813 test_bit(rx_stats->rs_keyix, common->tkip_keymap);
814 strip_mic = is_valid_tkip && ieee80211_is_data(fc) &&
815 !(rx_stats->rs_status &
816 (ATH9K_RXERR_DECRYPT | ATH9K_RXERR_CRC | ATH9K_RXERR_MIC |
817 ATH9K_RXERR_KEYMISS));
818
819 /*
820 * Key miss events are only relevant for pairwise keys where the
821 * descriptor does contain a valid key index. This has been observed
822 * mostly with CCMP encryption.
823 */
824 if (rx_stats->rs_keyix == ATH9K_RXKEYIX_INVALID)
825 rx_stats->rs_status &= ~ATH9K_RXERR_KEYMISS;
826
827 if (!rx_stats->rs_datalen) {
828 RX_STAT_INC(rx_len_err);
829 return false;
830 }
831
832 /*
833 * rs_status follows rs_datalen so if rs_datalen is too large
834 * we can take a hint that hardware corrupted it, so ignore
835 * those frames.
836 */
837 if (rx_stats->rs_datalen > (common->rx_bufsize - rx_status_len)) {
838 RX_STAT_INC(rx_len_err);
839 return false;
840 }
841
842 /* Only use error bits from the last fragment */
843 if (rx_stats->rs_more)
844 return true;
845
846 mic_error = is_valid_tkip && !ieee80211_is_ctl(fc) &&
847 !ieee80211_has_morefrags(fc) &&
848 !(le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG) &&
849 (rx_stats->rs_status & ATH9K_RXERR_MIC);
850
851 /*
852 * The rx_stats->rs_status will not be set until the end of the
853 * chained descriptors so it can be ignored if rs_more is set. The
854 * rs_more will be false at the last element of the chained
855 * descriptors.
856 */
857 if (rx_stats->rs_status != 0) {
858 u8 status_mask;
859
860 if (rx_stats->rs_status & ATH9K_RXERR_CRC) {
861 rxs->flag |= RX_FLAG_FAILED_FCS_CRC;
862 mic_error = false;
863 }
864 if (rx_stats->rs_status & ATH9K_RXERR_PHY)
865 return false;
866
867 if ((rx_stats->rs_status & ATH9K_RXERR_DECRYPT) ||
868 (!is_mc && (rx_stats->rs_status & ATH9K_RXERR_KEYMISS))) {
869 *decrypt_error = true;
870 mic_error = false;
871 }
872
873 /*
874 * Reject error frames with the exception of
875 * decryption and MIC failures. For monitor mode,
876 * we also ignore the CRC error.
877 */
878 status_mask = ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC |
879 ATH9K_RXERR_KEYMISS;
880
881 if (ah->is_monitoring && (sc->rx.rxfilter & FIF_FCSFAIL))
882 status_mask |= ATH9K_RXERR_CRC;
883
884 if (rx_stats->rs_status & ~status_mask)
885 return false;
886 }
887
888 /*
889 * For unicast frames the MIC error bit can have false positives,
890 * so all MIC error reports need to be validated in software.
891 * False negatives are not common, so skip software verification
892 * if the hardware considers the MIC valid.
893 */
894 if (strip_mic)
895 rxs->flag |= RX_FLAG_MMIC_STRIPPED;
896 else if (is_mc && mic_error)
897 rxs->flag |= RX_FLAG_MMIC_ERROR;
898
899 return true;
900 }
901
902 static int ath9k_process_rate(struct ath_common *common,
903 struct ieee80211_hw *hw,
904 struct ath_rx_status *rx_stats,
905 struct ieee80211_rx_status *rxs)
906 {
907 struct ieee80211_supported_band *sband;
908 enum ieee80211_band band;
909 unsigned int i = 0;
910 struct ath_softc __maybe_unused *sc = common->priv;
911
912 band = hw->conf.channel->band;
913 sband = hw->wiphy->bands[band];
914
915 if (rx_stats->rs_rate & 0x80) {
916 /* HT rate */
917 rxs->flag |= RX_FLAG_HT;
918 if (rx_stats->rs_flags & ATH9K_RX_2040)
919 rxs->flag |= RX_FLAG_40MHZ;
920 if (rx_stats->rs_flags & ATH9K_RX_GI)
921 rxs->flag |= RX_FLAG_SHORT_GI;
922 rxs->rate_idx = rx_stats->rs_rate & 0x7f;
923 return 0;
924 }
925
926 for (i = 0; i < sband->n_bitrates; i++) {
927 if (sband->bitrates[i].hw_value == rx_stats->rs_rate) {
928 rxs->rate_idx = i;
929 return 0;
930 }
931 if (sband->bitrates[i].hw_value_short == rx_stats->rs_rate) {
932 rxs->flag |= RX_FLAG_SHORTPRE;
933 rxs->rate_idx = i;
934 return 0;
935 }
936 }
937
938 /*
939 * No valid hardware bitrate found -- we should not get here
940 * because hardware has already validated this frame as OK.
941 */
942 ath_dbg(common, ANY,
943 "unsupported hw bitrate detected 0x%02x using 1 Mbit\n",
944 rx_stats->rs_rate);
945 RX_STAT_INC(rx_rate_err);
946 return -EINVAL;
947 }
948
949 static void ath9k_process_rssi(struct ath_common *common,
950 struct ieee80211_hw *hw,
951 struct ieee80211_hdr *hdr,
952 struct ath_rx_status *rx_stats)
953 {
954 struct ath_softc *sc = hw->priv;
955 struct ath_hw *ah = common->ah;
956 int last_rssi;
957 int rssi = rx_stats->rs_rssi;
958
959 if (!rx_stats->is_mybeacon ||
960 ((ah->opmode != NL80211_IFTYPE_STATION) &&
961 (ah->opmode != NL80211_IFTYPE_ADHOC)))
962 return;
963
964 if (rx_stats->rs_rssi != ATH9K_RSSI_BAD && !rx_stats->rs_moreaggr)
965 ATH_RSSI_LPF(sc->last_rssi, rx_stats->rs_rssi);
966
967 last_rssi = sc->last_rssi;
968 if (likely(last_rssi != ATH_RSSI_DUMMY_MARKER))
969 rssi = ATH_EP_RND(last_rssi, ATH_RSSI_EP_MULTIPLIER);
970 if (rssi < 0)
971 rssi = 0;
972
973 /* Update Beacon RSSI, this is used by ANI. */
974 ah->stats.avgbrssi = rssi;
975 }
976
977 /*
978 * For Decrypt or Demic errors, we only mark packet status here and always push
979 * up the frame up to let mac80211 handle the actual error case, be it no
980 * decryption key or real decryption error. This let us keep statistics there.
981 */
982 static int ath9k_rx_skb_preprocess(struct ath_common *common,
983 struct ieee80211_hw *hw,
984 struct ieee80211_hdr *hdr,
985 struct ath_rx_status *rx_stats,
986 struct ieee80211_rx_status *rx_status,
987 bool *decrypt_error)
988 {
989 struct ath_hw *ah = common->ah;
990
991 /*
992 * everything but the rate is checked here, the rate check is done
993 * separately to avoid doing two lookups for a rate for each frame.
994 */
995 if (!ath9k_rx_accept(common, hdr, rx_status, rx_stats, decrypt_error))
996 return -EINVAL;
997
998 /* Only use status info from the last fragment */
999 if (rx_stats->rs_more)
1000 return 0;
1001
1002 ath9k_process_rssi(common, hw, hdr, rx_stats);
1003
1004 if (ath9k_process_rate(common, hw, rx_stats, rx_status))
1005 return -EINVAL;
1006
1007 rx_status->band = hw->conf.channel->band;
1008 rx_status->freq = hw->conf.channel->center_freq;
1009 rx_status->signal = ah->noise + rx_stats->rs_rssi;
1010 rx_status->antenna = rx_stats->rs_antenna;
1011 rx_status->flag |= RX_FLAG_MACTIME_MPDU;
1012 if (rx_stats->rs_moreaggr)
1013 rx_status->flag |= RX_FLAG_NO_SIGNAL_VAL;
1014
1015 return 0;
1016 }
1017
1018 static void ath9k_rx_skb_postprocess(struct ath_common *common,
1019 struct sk_buff *skb,
1020 struct ath_rx_status *rx_stats,
1021 struct ieee80211_rx_status *rxs,
1022 bool decrypt_error)
1023 {
1024 struct ath_hw *ah = common->ah;
1025 struct ieee80211_hdr *hdr;
1026 int hdrlen, padpos, padsize;
1027 u8 keyix;
1028 __le16 fc;
1029
1030 /* see if any padding is done by the hw and remove it */
1031 hdr = (struct ieee80211_hdr *) skb->data;
1032 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1033 fc = hdr->frame_control;
1034 padpos = ath9k_cmn_padpos(hdr->frame_control);
1035
1036 /* The MAC header is padded to have 32-bit boundary if the
1037 * packet payload is non-zero. The general calculation for
1038 * padsize would take into account odd header lengths:
1039 * padsize = (4 - padpos % 4) % 4; However, since only
1040 * even-length headers are used, padding can only be 0 or 2
1041 * bytes and we can optimize this a bit. In addition, we must
1042 * not try to remove padding from short control frames that do
1043 * not have payload. */
1044 padsize = padpos & 3;
1045 if (padsize && skb->len>=padpos+padsize+FCS_LEN) {
1046 memmove(skb->data + padsize, skb->data, padpos);
1047 skb_pull(skb, padsize);
1048 }
1049
1050 keyix = rx_stats->rs_keyix;
1051
1052 if (!(keyix == ATH9K_RXKEYIX_INVALID) && !decrypt_error &&
1053 ieee80211_has_protected(fc)) {
1054 rxs->flag |= RX_FLAG_DECRYPTED;
1055 } else if (ieee80211_has_protected(fc)
1056 && !decrypt_error && skb->len >= hdrlen + 4) {
1057 keyix = skb->data[hdrlen + 3] >> 6;
1058
1059 if (test_bit(keyix, common->keymap))
1060 rxs->flag |= RX_FLAG_DECRYPTED;
1061 }
1062 if (ah->sw_mgmt_crypto &&
1063 (rxs->flag & RX_FLAG_DECRYPTED) &&
1064 ieee80211_is_mgmt(fc))
1065 /* Use software decrypt for management frames. */
1066 rxs->flag &= ~RX_FLAG_DECRYPTED;
1067 }
1068
1069 static void ath_lnaconf_alt_good_scan(struct ath_ant_comb *antcomb,
1070 struct ath_hw_antcomb_conf ant_conf,
1071 int main_rssi_avg)
1072 {
1073 antcomb->quick_scan_cnt = 0;
1074
1075 if (ant_conf.main_lna_conf == ATH_ANT_DIV_COMB_LNA2)
1076 antcomb->rssi_lna2 = main_rssi_avg;
1077 else if (ant_conf.main_lna_conf == ATH_ANT_DIV_COMB_LNA1)
1078 antcomb->rssi_lna1 = main_rssi_avg;
1079
1080 switch ((ant_conf.main_lna_conf << 4) | ant_conf.alt_lna_conf) {
1081 case 0x10: /* LNA2 A-B */
1082 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1083 antcomb->first_quick_scan_conf =
1084 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1085 antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA1;
1086 break;
1087 case 0x20: /* LNA1 A-B */
1088 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1089 antcomb->first_quick_scan_conf =
1090 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1091 antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA2;
1092 break;
1093 case 0x21: /* LNA1 LNA2 */
1094 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA2;
1095 antcomb->first_quick_scan_conf =
1096 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1097 antcomb->second_quick_scan_conf =
1098 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1099 break;
1100 case 0x12: /* LNA2 LNA1 */
1101 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1;
1102 antcomb->first_quick_scan_conf =
1103 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1104 antcomb->second_quick_scan_conf =
1105 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1106 break;
1107 case 0x13: /* LNA2 A+B */
1108 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1109 antcomb->first_quick_scan_conf =
1110 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1111 antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA1;
1112 break;
1113 case 0x23: /* LNA1 A+B */
1114 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1115 antcomb->first_quick_scan_conf =
1116 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1117 antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA2;
1118 break;
1119 default:
1120 break;
1121 }
1122 }
1123
1124 static void ath_select_ant_div_from_quick_scan(struct ath_ant_comb *antcomb,
1125 struct ath_hw_antcomb_conf *div_ant_conf,
1126 int main_rssi_avg, int alt_rssi_avg,
1127 int alt_ratio)
1128 {
1129 /* alt_good */
1130 switch (antcomb->quick_scan_cnt) {
1131 case 0:
1132 /* set alt to main, and alt to first conf */
1133 div_ant_conf->main_lna_conf = antcomb->main_conf;
1134 div_ant_conf->alt_lna_conf = antcomb->first_quick_scan_conf;
1135 break;
1136 case 1:
1137 /* set alt to main, and alt to first conf */
1138 div_ant_conf->main_lna_conf = antcomb->main_conf;
1139 div_ant_conf->alt_lna_conf = antcomb->second_quick_scan_conf;
1140 antcomb->rssi_first = main_rssi_avg;
1141 antcomb->rssi_second = alt_rssi_avg;
1142
1143 if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1) {
1144 /* main is LNA1 */
1145 if (ath_is_alt_ant_ratio_better(alt_ratio,
1146 ATH_ANT_DIV_COMB_LNA1_DELTA_HI,
1147 ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
1148 main_rssi_avg, alt_rssi_avg,
1149 antcomb->total_pkt_count))
1150 antcomb->first_ratio = true;
1151 else
1152 antcomb->first_ratio = false;
1153 } else if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2) {
1154 if (ath_is_alt_ant_ratio_better(alt_ratio,
1155 ATH_ANT_DIV_COMB_LNA1_DELTA_MID,
1156 ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
1157 main_rssi_avg, alt_rssi_avg,
1158 antcomb->total_pkt_count))
1159 antcomb->first_ratio = true;
1160 else
1161 antcomb->first_ratio = false;
1162 } else {
1163 if ((((alt_ratio >= ATH_ANT_DIV_COMB_ALT_ANT_RATIO2) &&
1164 (alt_rssi_avg > main_rssi_avg +
1165 ATH_ANT_DIV_COMB_LNA1_DELTA_HI)) ||
1166 (alt_rssi_avg > main_rssi_avg)) &&
1167 (antcomb->total_pkt_count > 50))
1168 antcomb->first_ratio = true;
1169 else
1170 antcomb->first_ratio = false;
1171 }
1172 break;
1173 case 2:
1174 antcomb->alt_good = false;
1175 antcomb->scan_not_start = false;
1176 antcomb->scan = false;
1177 antcomb->rssi_first = main_rssi_avg;
1178 antcomb->rssi_third = alt_rssi_avg;
1179
1180 if (antcomb->second_quick_scan_conf == ATH_ANT_DIV_COMB_LNA1)
1181 antcomb->rssi_lna1 = alt_rssi_avg;
1182 else if (antcomb->second_quick_scan_conf ==
1183 ATH_ANT_DIV_COMB_LNA2)
1184 antcomb->rssi_lna2 = alt_rssi_avg;
1185 else if (antcomb->second_quick_scan_conf ==
1186 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2) {
1187 if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2)
1188 antcomb->rssi_lna2 = main_rssi_avg;
1189 else if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1)
1190 antcomb->rssi_lna1 = main_rssi_avg;
1191 }
1192
1193 if (antcomb->rssi_lna2 > antcomb->rssi_lna1 +
1194 ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA)
1195 div_ant_conf->main_lna_conf = ATH_ANT_DIV_COMB_LNA2;
1196 else
1197 div_ant_conf->main_lna_conf = ATH_ANT_DIV_COMB_LNA1;
1198
1199 if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1) {
1200 if (ath_is_alt_ant_ratio_better(alt_ratio,
1201 ATH_ANT_DIV_COMB_LNA1_DELTA_HI,
1202 ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
1203 main_rssi_avg, alt_rssi_avg,
1204 antcomb->total_pkt_count))
1205 antcomb->second_ratio = true;
1206 else
1207 antcomb->second_ratio = false;
1208 } else if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2) {
1209 if (ath_is_alt_ant_ratio_better(alt_ratio,
1210 ATH_ANT_DIV_COMB_LNA1_DELTA_MID,
1211 ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
1212 main_rssi_avg, alt_rssi_avg,
1213 antcomb->total_pkt_count))
1214 antcomb->second_ratio = true;
1215 else
1216 antcomb->second_ratio = false;
1217 } else {
1218 if ((((alt_ratio >= ATH_ANT_DIV_COMB_ALT_ANT_RATIO2) &&
1219 (alt_rssi_avg > main_rssi_avg +
1220 ATH_ANT_DIV_COMB_LNA1_DELTA_HI)) ||
1221 (alt_rssi_avg > main_rssi_avg)) &&
1222 (antcomb->total_pkt_count > 50))
1223 antcomb->second_ratio = true;
1224 else
1225 antcomb->second_ratio = false;
1226 }
1227
1228 /* set alt to the conf with maximun ratio */
1229 if (antcomb->first_ratio && antcomb->second_ratio) {
1230 if (antcomb->rssi_second > antcomb->rssi_third) {
1231 /* first alt*/
1232 if ((antcomb->first_quick_scan_conf ==
1233 ATH_ANT_DIV_COMB_LNA1) ||
1234 (antcomb->first_quick_scan_conf ==
1235 ATH_ANT_DIV_COMB_LNA2))
1236 /* Set alt LNA1 or LNA2*/
1237 if (div_ant_conf->main_lna_conf ==
1238 ATH_ANT_DIV_COMB_LNA2)
1239 div_ant_conf->alt_lna_conf =
1240 ATH_ANT_DIV_COMB_LNA1;
1241 else
1242 div_ant_conf->alt_lna_conf =
1243 ATH_ANT_DIV_COMB_LNA2;
1244 else
1245 /* Set alt to A+B or A-B */
1246 div_ant_conf->alt_lna_conf =
1247 antcomb->first_quick_scan_conf;
1248 } else if ((antcomb->second_quick_scan_conf ==
1249 ATH_ANT_DIV_COMB_LNA1) ||
1250 (antcomb->second_quick_scan_conf ==
1251 ATH_ANT_DIV_COMB_LNA2)) {
1252 /* Set alt LNA1 or LNA2 */
1253 if (div_ant_conf->main_lna_conf ==
1254 ATH_ANT_DIV_COMB_LNA2)
1255 div_ant_conf->alt_lna_conf =
1256 ATH_ANT_DIV_COMB_LNA1;
1257 else
1258 div_ant_conf->alt_lna_conf =
1259 ATH_ANT_DIV_COMB_LNA2;
1260 } else {
1261 /* Set alt to A+B or A-B */
1262 div_ant_conf->alt_lna_conf =
1263 antcomb->second_quick_scan_conf;
1264 }
1265 } else if (antcomb->first_ratio) {
1266 /* first alt */
1267 if ((antcomb->first_quick_scan_conf ==
1268 ATH_ANT_DIV_COMB_LNA1) ||
1269 (antcomb->first_quick_scan_conf ==
1270 ATH_ANT_DIV_COMB_LNA2))
1271 /* Set alt LNA1 or LNA2 */
1272 if (div_ant_conf->main_lna_conf ==
1273 ATH_ANT_DIV_COMB_LNA2)
1274 div_ant_conf->alt_lna_conf =
1275 ATH_ANT_DIV_COMB_LNA1;
1276 else
1277 div_ant_conf->alt_lna_conf =
1278 ATH_ANT_DIV_COMB_LNA2;
1279 else
1280 /* Set alt to A+B or A-B */
1281 div_ant_conf->alt_lna_conf =
1282 antcomb->first_quick_scan_conf;
1283 } else if (antcomb->second_ratio) {
1284 /* second alt */
1285 if ((antcomb->second_quick_scan_conf ==
1286 ATH_ANT_DIV_COMB_LNA1) ||
1287 (antcomb->second_quick_scan_conf ==
1288 ATH_ANT_DIV_COMB_LNA2))
1289 /* Set alt LNA1 or LNA2 */
1290 if (div_ant_conf->main_lna_conf ==
1291 ATH_ANT_DIV_COMB_LNA2)
1292 div_ant_conf->alt_lna_conf =
1293 ATH_ANT_DIV_COMB_LNA1;
1294 else
1295 div_ant_conf->alt_lna_conf =
1296 ATH_ANT_DIV_COMB_LNA2;
1297 else
1298 /* Set alt to A+B or A-B */
1299 div_ant_conf->alt_lna_conf =
1300 antcomb->second_quick_scan_conf;
1301 } else {
1302 /* main is largest */
1303 if ((antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1) ||
1304 (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2))
1305 /* Set alt LNA1 or LNA2 */
1306 if (div_ant_conf->main_lna_conf ==
1307 ATH_ANT_DIV_COMB_LNA2)
1308 div_ant_conf->alt_lna_conf =
1309 ATH_ANT_DIV_COMB_LNA1;
1310 else
1311 div_ant_conf->alt_lna_conf =
1312 ATH_ANT_DIV_COMB_LNA2;
1313 else
1314 /* Set alt to A+B or A-B */
1315 div_ant_conf->alt_lna_conf = antcomb->main_conf;
1316 }
1317 break;
1318 default:
1319 break;
1320 }
1321 }
1322
1323 static void ath_ant_div_conf_fast_divbias(struct ath_hw_antcomb_conf *ant_conf,
1324 struct ath_ant_comb *antcomb, int alt_ratio)
1325 {
1326 if (ant_conf->div_group == 0) {
1327 /* Adjust the fast_div_bias based on main and alt lna conf */
1328 switch ((ant_conf->main_lna_conf << 4) |
1329 ant_conf->alt_lna_conf) {
1330 case 0x01: /* A-B LNA2 */
1331 ant_conf->fast_div_bias = 0x3b;
1332 break;
1333 case 0x02: /* A-B LNA1 */
1334 ant_conf->fast_div_bias = 0x3d;
1335 break;
1336 case 0x03: /* A-B A+B */
1337 ant_conf->fast_div_bias = 0x1;
1338 break;
1339 case 0x10: /* LNA2 A-B */
1340 ant_conf->fast_div_bias = 0x7;
1341 break;
1342 case 0x12: /* LNA2 LNA1 */
1343 ant_conf->fast_div_bias = 0x2;
1344 break;
1345 case 0x13: /* LNA2 A+B */
1346 ant_conf->fast_div_bias = 0x7;
1347 break;
1348 case 0x20: /* LNA1 A-B */
1349 ant_conf->fast_div_bias = 0x6;
1350 break;
1351 case 0x21: /* LNA1 LNA2 */
1352 ant_conf->fast_div_bias = 0x0;
1353 break;
1354 case 0x23: /* LNA1 A+B */
1355 ant_conf->fast_div_bias = 0x6;
1356 break;
1357 case 0x30: /* A+B A-B */
1358 ant_conf->fast_div_bias = 0x1;
1359 break;
1360 case 0x31: /* A+B LNA2 */
1361 ant_conf->fast_div_bias = 0x3b;
1362 break;
1363 case 0x32: /* A+B LNA1 */
1364 ant_conf->fast_div_bias = 0x3d;
1365 break;
1366 default:
1367 break;
1368 }
1369 } else if (ant_conf->div_group == 1) {
1370 /* Adjust the fast_div_bias based on main and alt_lna_conf */
1371 switch ((ant_conf->main_lna_conf << 4) |
1372 ant_conf->alt_lna_conf) {
1373 case 0x01: /* A-B LNA2 */
1374 ant_conf->fast_div_bias = 0x1;
1375 ant_conf->main_gaintb = 0;
1376 ant_conf->alt_gaintb = 0;
1377 break;
1378 case 0x02: /* A-B LNA1 */
1379 ant_conf->fast_div_bias = 0x1;
1380 ant_conf->main_gaintb = 0;
1381 ant_conf->alt_gaintb = 0;
1382 break;
1383 case 0x03: /* A-B A+B */
1384 ant_conf->fast_div_bias = 0x1;
1385 ant_conf->main_gaintb = 0;
1386 ant_conf->alt_gaintb = 0;
1387 break;
1388 case 0x10: /* LNA2 A-B */
1389 if (!(antcomb->scan) &&
1390 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
1391 ant_conf->fast_div_bias = 0x3f;
1392 else
1393 ant_conf->fast_div_bias = 0x1;
1394 ant_conf->main_gaintb = 0;
1395 ant_conf->alt_gaintb = 0;
1396 break;
1397 case 0x12: /* LNA2 LNA1 */
1398 ant_conf->fast_div_bias = 0x1;
1399 ant_conf->main_gaintb = 0;
1400 ant_conf->alt_gaintb = 0;
1401 break;
1402 case 0x13: /* LNA2 A+B */
1403 if (!(antcomb->scan) &&
1404 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
1405 ant_conf->fast_div_bias = 0x3f;
1406 else
1407 ant_conf->fast_div_bias = 0x1;
1408 ant_conf->main_gaintb = 0;
1409 ant_conf->alt_gaintb = 0;
1410 break;
1411 case 0x20: /* LNA1 A-B */
1412 if (!(antcomb->scan) &&
1413 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
1414 ant_conf->fast_div_bias = 0x3f;
1415 else
1416 ant_conf->fast_div_bias = 0x1;
1417 ant_conf->main_gaintb = 0;
1418 ant_conf->alt_gaintb = 0;
1419 break;
1420 case 0x21: /* LNA1 LNA2 */
1421 ant_conf->fast_div_bias = 0x1;
1422 ant_conf->main_gaintb = 0;
1423 ant_conf->alt_gaintb = 0;
1424 break;
1425 case 0x23: /* LNA1 A+B */
1426 if (!(antcomb->scan) &&
1427 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
1428 ant_conf->fast_div_bias = 0x3f;
1429 else
1430 ant_conf->fast_div_bias = 0x1;
1431 ant_conf->main_gaintb = 0;
1432 ant_conf->alt_gaintb = 0;
1433 break;
1434 case 0x30: /* A+B A-B */
1435 ant_conf->fast_div_bias = 0x1;
1436 ant_conf->main_gaintb = 0;
1437 ant_conf->alt_gaintb = 0;
1438 break;
1439 case 0x31: /* A+B LNA2 */
1440 ant_conf->fast_div_bias = 0x1;
1441 ant_conf->main_gaintb = 0;
1442 ant_conf->alt_gaintb = 0;
1443 break;
1444 case 0x32: /* A+B LNA1 */
1445 ant_conf->fast_div_bias = 0x1;
1446 ant_conf->main_gaintb = 0;
1447 ant_conf->alt_gaintb = 0;
1448 break;
1449 default:
1450 break;
1451 }
1452 } else if (ant_conf->div_group == 2) {
1453 /* Adjust the fast_div_bias based on main and alt_lna_conf */
1454 switch ((ant_conf->main_lna_conf << 4) |
1455 ant_conf->alt_lna_conf) {
1456 case 0x01: /* A-B LNA2 */
1457 ant_conf->fast_div_bias = 0x1;
1458 ant_conf->main_gaintb = 0;
1459 ant_conf->alt_gaintb = 0;
1460 break;
1461 case 0x02: /* A-B LNA1 */
1462 ant_conf->fast_div_bias = 0x1;
1463 ant_conf->main_gaintb = 0;
1464 ant_conf->alt_gaintb = 0;
1465 break;
1466 case 0x03: /* A-B A+B */
1467 ant_conf->fast_div_bias = 0x1;
1468 ant_conf->main_gaintb = 0;
1469 ant_conf->alt_gaintb = 0;
1470 break;
1471 case 0x10: /* LNA2 A-B */
1472 if (!(antcomb->scan) &&
1473 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
1474 ant_conf->fast_div_bias = 0x1;
1475 else
1476 ant_conf->fast_div_bias = 0x2;
1477 ant_conf->main_gaintb = 0;
1478 ant_conf->alt_gaintb = 0;
1479 break;
1480 case 0x12: /* LNA2 LNA1 */
1481 ant_conf->fast_div_bias = 0x1;
1482 ant_conf->main_gaintb = 0;
1483 ant_conf->alt_gaintb = 0;
1484 break;
1485 case 0x13: /* LNA2 A+B */
1486 if (!(antcomb->scan) &&
1487 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
1488 ant_conf->fast_div_bias = 0x1;
1489 else
1490 ant_conf->fast_div_bias = 0x2;
1491 ant_conf->main_gaintb = 0;
1492 ant_conf->alt_gaintb = 0;
1493 break;
1494 case 0x20: /* LNA1 A-B */
1495 if (!(antcomb->scan) &&
1496 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
1497 ant_conf->fast_div_bias = 0x1;
1498 else
1499 ant_conf->fast_div_bias = 0x2;
1500 ant_conf->main_gaintb = 0;
1501 ant_conf->alt_gaintb = 0;
1502 break;
1503 case 0x21: /* LNA1 LNA2 */
1504 ant_conf->fast_div_bias = 0x1;
1505 ant_conf->main_gaintb = 0;
1506 ant_conf->alt_gaintb = 0;
1507 break;
1508 case 0x23: /* LNA1 A+B */
1509 if (!(antcomb->scan) &&
1510 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
1511 ant_conf->fast_div_bias = 0x1;
1512 else
1513 ant_conf->fast_div_bias = 0x2;
1514 ant_conf->main_gaintb = 0;
1515 ant_conf->alt_gaintb = 0;
1516 break;
1517 case 0x30: /* A+B A-B */
1518 ant_conf->fast_div_bias = 0x1;
1519 ant_conf->main_gaintb = 0;
1520 ant_conf->alt_gaintb = 0;
1521 break;
1522 case 0x31: /* A+B LNA2 */
1523 ant_conf->fast_div_bias = 0x1;
1524 ant_conf->main_gaintb = 0;
1525 ant_conf->alt_gaintb = 0;
1526 break;
1527 case 0x32: /* A+B LNA1 */
1528 ant_conf->fast_div_bias = 0x1;
1529 ant_conf->main_gaintb = 0;
1530 ant_conf->alt_gaintb = 0;
1531 break;
1532 default:
1533 break;
1534 }
1535 }
1536 }
1537
1538 /* Antenna diversity and combining */
1539 static void ath_ant_comb_scan(struct ath_softc *sc, struct ath_rx_status *rs)
1540 {
1541 struct ath_hw_antcomb_conf div_ant_conf;
1542 struct ath_ant_comb *antcomb = &sc->ant_comb;
1543 int alt_ratio = 0, alt_rssi_avg = 0, main_rssi_avg = 0, curr_alt_set;
1544 int curr_main_set;
1545 int main_rssi = rs->rs_rssi_ctl0;
1546 int alt_rssi = rs->rs_rssi_ctl1;
1547 int rx_ant_conf, main_ant_conf;
1548 bool short_scan = false;
1549
1550 rx_ant_conf = (rs->rs_rssi_ctl2 >> ATH_ANT_RX_CURRENT_SHIFT) &
1551 ATH_ANT_RX_MASK;
1552 main_ant_conf = (rs->rs_rssi_ctl2 >> ATH_ANT_RX_MAIN_SHIFT) &
1553 ATH_ANT_RX_MASK;
1554
1555 /* Record packet only when both main_rssi and alt_rssi is positive */
1556 if (main_rssi > 0 && alt_rssi > 0) {
1557 antcomb->total_pkt_count++;
1558 antcomb->main_total_rssi += main_rssi;
1559 antcomb->alt_total_rssi += alt_rssi;
1560 if (main_ant_conf == rx_ant_conf)
1561 antcomb->main_recv_cnt++;
1562 else
1563 antcomb->alt_recv_cnt++;
1564 }
1565
1566 /* Short scan check */
1567 if (antcomb->scan && antcomb->alt_good) {
1568 if (time_after(jiffies, antcomb->scan_start_time +
1569 msecs_to_jiffies(ATH_ANT_DIV_COMB_SHORT_SCAN_INTR)))
1570 short_scan = true;
1571 else
1572 if (antcomb->total_pkt_count ==
1573 ATH_ANT_DIV_COMB_SHORT_SCAN_PKTCOUNT) {
1574 alt_ratio = ((antcomb->alt_recv_cnt * 100) /
1575 antcomb->total_pkt_count);
1576 if (alt_ratio < ATH_ANT_DIV_COMB_ALT_ANT_RATIO)
1577 short_scan = true;
1578 }
1579 }
1580
1581 if (((antcomb->total_pkt_count < ATH_ANT_DIV_COMB_MAX_PKTCOUNT) ||
1582 rs->rs_moreaggr) && !short_scan)
1583 return;
1584
1585 if (antcomb->total_pkt_count) {
1586 alt_ratio = ((antcomb->alt_recv_cnt * 100) /
1587 antcomb->total_pkt_count);
1588 main_rssi_avg = (antcomb->main_total_rssi /
1589 antcomb->total_pkt_count);
1590 alt_rssi_avg = (antcomb->alt_total_rssi /
1591 antcomb->total_pkt_count);
1592 }
1593
1594
1595 ath9k_hw_antdiv_comb_conf_get(sc->sc_ah, &div_ant_conf);
1596 curr_alt_set = div_ant_conf.alt_lna_conf;
1597 curr_main_set = div_ant_conf.main_lna_conf;
1598
1599 antcomb->count++;
1600
1601 if (antcomb->count == ATH_ANT_DIV_COMB_MAX_COUNT) {
1602 if (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO) {
1603 ath_lnaconf_alt_good_scan(antcomb, div_ant_conf,
1604 main_rssi_avg);
1605 antcomb->alt_good = true;
1606 } else {
1607 antcomb->alt_good = false;
1608 }
1609
1610 antcomb->count = 0;
1611 antcomb->scan = true;
1612 antcomb->scan_not_start = true;
1613 }
1614
1615 if (!antcomb->scan) {
1616 if (ath_ant_div_comb_alt_check(div_ant_conf.div_group,
1617 alt_ratio, curr_main_set, curr_alt_set,
1618 alt_rssi_avg, main_rssi_avg)) {
1619 if (curr_alt_set == ATH_ANT_DIV_COMB_LNA2) {
1620 /* Switch main and alt LNA */
1621 div_ant_conf.main_lna_conf =
1622 ATH_ANT_DIV_COMB_LNA2;
1623 div_ant_conf.alt_lna_conf =
1624 ATH_ANT_DIV_COMB_LNA1;
1625 } else if (curr_alt_set == ATH_ANT_DIV_COMB_LNA1) {
1626 div_ant_conf.main_lna_conf =
1627 ATH_ANT_DIV_COMB_LNA1;
1628 div_ant_conf.alt_lna_conf =
1629 ATH_ANT_DIV_COMB_LNA2;
1630 }
1631
1632 goto div_comb_done;
1633 } else if ((curr_alt_set != ATH_ANT_DIV_COMB_LNA1) &&
1634 (curr_alt_set != ATH_ANT_DIV_COMB_LNA2)) {
1635 /* Set alt to another LNA */
1636 if (curr_main_set == ATH_ANT_DIV_COMB_LNA2)
1637 div_ant_conf.alt_lna_conf =
1638 ATH_ANT_DIV_COMB_LNA1;
1639 else if (curr_main_set == ATH_ANT_DIV_COMB_LNA1)
1640 div_ant_conf.alt_lna_conf =
1641 ATH_ANT_DIV_COMB_LNA2;
1642
1643 goto div_comb_done;
1644 }
1645
1646 if ((alt_rssi_avg < (main_rssi_avg +
1647 div_ant_conf.lna1_lna2_delta)))
1648 goto div_comb_done;
1649 }
1650
1651 if (!antcomb->scan_not_start) {
1652 switch (curr_alt_set) {
1653 case ATH_ANT_DIV_COMB_LNA2:
1654 antcomb->rssi_lna2 = alt_rssi_avg;
1655 antcomb->rssi_lna1 = main_rssi_avg;
1656 antcomb->scan = true;
1657 /* set to A+B */
1658 div_ant_conf.main_lna_conf =
1659 ATH_ANT_DIV_COMB_LNA1;
1660 div_ant_conf.alt_lna_conf =
1661 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1662 break;
1663 case ATH_ANT_DIV_COMB_LNA1:
1664 antcomb->rssi_lna1 = alt_rssi_avg;
1665 antcomb->rssi_lna2 = main_rssi_avg;
1666 antcomb->scan = true;
1667 /* set to A+B */
1668 div_ant_conf.main_lna_conf = ATH_ANT_DIV_COMB_LNA2;
1669 div_ant_conf.alt_lna_conf =
1670 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1671 break;
1672 case ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2:
1673 antcomb->rssi_add = alt_rssi_avg;
1674 antcomb->scan = true;
1675 /* set to A-B */
1676 div_ant_conf.alt_lna_conf =
1677 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1678 break;
1679 case ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2:
1680 antcomb->rssi_sub = alt_rssi_avg;
1681 antcomb->scan = false;
1682 if (antcomb->rssi_lna2 >
1683 (antcomb->rssi_lna1 +
1684 ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA)) {
1685 /* use LNA2 as main LNA */
1686 if ((antcomb->rssi_add > antcomb->rssi_lna1) &&
1687 (antcomb->rssi_add > antcomb->rssi_sub)) {
1688 /* set to A+B */
1689 div_ant_conf.main_lna_conf =
1690 ATH_ANT_DIV_COMB_LNA2;
1691 div_ant_conf.alt_lna_conf =
1692 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1693 } else if (antcomb->rssi_sub >
1694 antcomb->rssi_lna1) {
1695 /* set to A-B */
1696 div_ant_conf.main_lna_conf =
1697 ATH_ANT_DIV_COMB_LNA2;
1698 div_ant_conf.alt_lna_conf =
1699 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1700 } else {
1701 /* set to LNA1 */
1702 div_ant_conf.main_lna_conf =
1703 ATH_ANT_DIV_COMB_LNA2;
1704 div_ant_conf.alt_lna_conf =
1705 ATH_ANT_DIV_COMB_LNA1;
1706 }
1707 } else {
1708 /* use LNA1 as main LNA */
1709 if ((antcomb->rssi_add > antcomb->rssi_lna2) &&
1710 (antcomb->rssi_add > antcomb->rssi_sub)) {
1711 /* set to A+B */
1712 div_ant_conf.main_lna_conf =
1713 ATH_ANT_DIV_COMB_LNA1;
1714 div_ant_conf.alt_lna_conf =
1715 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1716 } else if (antcomb->rssi_sub >
1717 antcomb->rssi_lna1) {
1718 /* set to A-B */
1719 div_ant_conf.main_lna_conf =
1720 ATH_ANT_DIV_COMB_LNA1;
1721 div_ant_conf.alt_lna_conf =
1722 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1723 } else {
1724 /* set to LNA2 */
1725 div_ant_conf.main_lna_conf =
1726 ATH_ANT_DIV_COMB_LNA1;
1727 div_ant_conf.alt_lna_conf =
1728 ATH_ANT_DIV_COMB_LNA2;
1729 }
1730 }
1731 break;
1732 default:
1733 break;
1734 }
1735 } else {
1736 if (!antcomb->alt_good) {
1737 antcomb->scan_not_start = false;
1738 /* Set alt to another LNA */
1739 if (curr_main_set == ATH_ANT_DIV_COMB_LNA2) {
1740 div_ant_conf.main_lna_conf =
1741 ATH_ANT_DIV_COMB_LNA2;
1742 div_ant_conf.alt_lna_conf =
1743 ATH_ANT_DIV_COMB_LNA1;
1744 } else if (curr_main_set == ATH_ANT_DIV_COMB_LNA1) {
1745 div_ant_conf.main_lna_conf =
1746 ATH_ANT_DIV_COMB_LNA1;
1747 div_ant_conf.alt_lna_conf =
1748 ATH_ANT_DIV_COMB_LNA2;
1749 }
1750 goto div_comb_done;
1751 }
1752 }
1753
1754 ath_select_ant_div_from_quick_scan(antcomb, &div_ant_conf,
1755 main_rssi_avg, alt_rssi_avg,
1756 alt_ratio);
1757
1758 antcomb->quick_scan_cnt++;
1759
1760 div_comb_done:
1761 ath_ant_div_conf_fast_divbias(&div_ant_conf, antcomb, alt_ratio);
1762 ath9k_hw_antdiv_comb_conf_set(sc->sc_ah, &div_ant_conf);
1763
1764 antcomb->scan_start_time = jiffies;
1765 antcomb->total_pkt_count = 0;
1766 antcomb->main_total_rssi = 0;
1767 antcomb->alt_total_rssi = 0;
1768 antcomb->main_recv_cnt = 0;
1769 antcomb->alt_recv_cnt = 0;
1770 }
1771
1772 int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp)
1773 {
1774 struct ath_buf *bf;
1775 struct sk_buff *skb = NULL, *requeue_skb, *hdr_skb;
1776 struct ieee80211_rx_status *rxs;
1777 struct ath_hw *ah = sc->sc_ah;
1778 struct ath_common *common = ath9k_hw_common(ah);
1779 struct ieee80211_hw *hw = sc->hw;
1780 struct ieee80211_hdr *hdr;
1781 int retval;
1782 bool decrypt_error = false;
1783 struct ath_rx_status rs;
1784 enum ath9k_rx_qtype qtype;
1785 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1786 int dma_type;
1787 u8 rx_status_len = ah->caps.rx_status_len;
1788 u64 tsf = 0;
1789 u32 tsf_lower = 0;
1790 unsigned long flags;
1791
1792 if (edma)
1793 dma_type = DMA_BIDIRECTIONAL;
1794 else
1795 dma_type = DMA_FROM_DEVICE;
1796
1797 qtype = hp ? ATH9K_RX_QUEUE_HP : ATH9K_RX_QUEUE_LP;
1798 spin_lock_bh(&sc->rx.rxbuflock);
1799
1800 tsf = ath9k_hw_gettsf64(ah);
1801 tsf_lower = tsf & 0xffffffff;
1802
1803 do {
1804 /* If handling rx interrupt and flush is in progress => exit */
1805 if ((sc->sc_flags & SC_OP_RXFLUSH) && (flush == 0))
1806 break;
1807
1808 memset(&rs, 0, sizeof(rs));
1809 if (edma)
1810 bf = ath_edma_get_next_rx_buf(sc, &rs, qtype);
1811 else
1812 bf = ath_get_next_rx_buf(sc, &rs);
1813
1814 if (!bf)
1815 break;
1816
1817 skb = bf->bf_mpdu;
1818 if (!skb)
1819 continue;
1820
1821 /*
1822 * Take frame header from the first fragment and RX status from
1823 * the last one.
1824 */
1825 if (sc->rx.frag)
1826 hdr_skb = sc->rx.frag;
1827 else
1828 hdr_skb = skb;
1829
1830 hdr = (struct ieee80211_hdr *) (hdr_skb->data + rx_status_len);
1831 rxs = IEEE80211_SKB_RXCB(hdr_skb);
1832 if (ieee80211_is_beacon(hdr->frame_control)) {
1833 RX_STAT_INC(rx_beacons);
1834 if (!is_zero_ether_addr(common->curbssid) &&
1835 !compare_ether_addr(hdr->addr3, common->curbssid))
1836 rs.is_mybeacon = true;
1837 else
1838 rs.is_mybeacon = false;
1839 }
1840 else
1841 rs.is_mybeacon = false;
1842
1843 ath_debug_stat_rx(sc, &rs);
1844
1845 /*
1846 * If we're asked to flush receive queue, directly
1847 * chain it back at the queue without processing it.
1848 */
1849 if (sc->sc_flags & SC_OP_RXFLUSH) {
1850 RX_STAT_INC(rx_drop_rxflush);
1851 goto requeue_drop_frag;
1852 }
1853
1854 memset(rxs, 0, sizeof(struct ieee80211_rx_status));
1855
1856 rxs->mactime = (tsf & ~0xffffffffULL) | rs.rs_tstamp;
1857 if (rs.rs_tstamp > tsf_lower &&
1858 unlikely(rs.rs_tstamp - tsf_lower > 0x10000000))
1859 rxs->mactime -= 0x100000000ULL;
1860
1861 if (rs.rs_tstamp < tsf_lower &&
1862 unlikely(tsf_lower - rs.rs_tstamp > 0x10000000))
1863 rxs->mactime += 0x100000000ULL;
1864
1865 retval = ath9k_rx_skb_preprocess(common, hw, hdr, &rs,
1866 rxs, &decrypt_error);
1867 if (retval)
1868 goto requeue_drop_frag;
1869
1870 if (rs.is_mybeacon) {
1871 sc->hw_busy_count = 0;
1872 ath_start_rx_poll(sc, 3);
1873 }
1874 /* Ensure we always have an skb to requeue once we are done
1875 * processing the current buffer's skb */
1876 requeue_skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_ATOMIC);
1877
1878 /* If there is no memory we ignore the current RX'd frame,
1879 * tell hardware it can give us a new frame using the old
1880 * skb and put it at the tail of the sc->rx.rxbuf list for
1881 * processing. */
1882 if (!requeue_skb) {
1883 RX_STAT_INC(rx_oom_err);
1884 goto requeue_drop_frag;
1885 }
1886
1887 /* Unmap the frame */
1888 dma_unmap_single(sc->dev, bf->bf_buf_addr,
1889 common->rx_bufsize,
1890 dma_type);
1891
1892 skb_put(skb, rs.rs_datalen + ah->caps.rx_status_len);
1893 if (ah->caps.rx_status_len)
1894 skb_pull(skb, ah->caps.rx_status_len);
1895
1896 if (!rs.rs_more)
1897 ath9k_rx_skb_postprocess(common, hdr_skb, &rs,
1898 rxs, decrypt_error);
1899
1900 /* We will now give hardware our shiny new allocated skb */
1901 bf->bf_mpdu = requeue_skb;
1902 bf->bf_buf_addr = dma_map_single(sc->dev, requeue_skb->data,
1903 common->rx_bufsize,
1904 dma_type);
1905 if (unlikely(dma_mapping_error(sc->dev,
1906 bf->bf_buf_addr))) {
1907 dev_kfree_skb_any(requeue_skb);
1908 bf->bf_mpdu = NULL;
1909 bf->bf_buf_addr = 0;
1910 ath_err(common, "dma_mapping_error() on RX\n");
1911 ieee80211_rx(hw, skb);
1912 break;
1913 }
1914
1915 if (rs.rs_more) {
1916 RX_STAT_INC(rx_frags);
1917 /*
1918 * rs_more indicates chained descriptors which can be
1919 * used to link buffers together for a sort of
1920 * scatter-gather operation.
1921 */
1922 if (sc->rx.frag) {
1923 /* too many fragments - cannot handle frame */
1924 dev_kfree_skb_any(sc->rx.frag);
1925 dev_kfree_skb_any(skb);
1926 RX_STAT_INC(rx_too_many_frags_err);
1927 skb = NULL;
1928 }
1929 sc->rx.frag = skb;
1930 goto requeue;
1931 }
1932
1933 if (sc->rx.frag) {
1934 int space = skb->len - skb_tailroom(hdr_skb);
1935
1936 if (pskb_expand_head(hdr_skb, 0, space, GFP_ATOMIC) < 0) {
1937 dev_kfree_skb(skb);
1938 RX_STAT_INC(rx_oom_err);
1939 goto requeue_drop_frag;
1940 }
1941
1942 sc->rx.frag = NULL;
1943
1944 skb_copy_from_linear_data(skb, skb_put(hdr_skb, skb->len),
1945 skb->len);
1946 dev_kfree_skb_any(skb);
1947 skb = hdr_skb;
1948 }
1949
1950
1951 if (ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) {
1952
1953 /*
1954 * change the default rx antenna if rx diversity
1955 * chooses the other antenna 3 times in a row.
1956 */
1957 if (sc->rx.defant != rs.rs_antenna) {
1958 if (++sc->rx.rxotherant >= 3)
1959 ath_setdefantenna(sc, rs.rs_antenna);
1960 } else {
1961 sc->rx.rxotherant = 0;
1962 }
1963
1964 }
1965
1966 if (rxs->flag & RX_FLAG_MMIC_STRIPPED)
1967 skb_trim(skb, skb->len - 8);
1968
1969 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1970
1971 if ((sc->ps_flags & (PS_WAIT_FOR_BEACON |
1972 PS_WAIT_FOR_CAB |
1973 PS_WAIT_FOR_PSPOLL_DATA)) ||
1974 ath9k_check_auto_sleep(sc))
1975 ath_rx_ps(sc, skb, rs.is_mybeacon);
1976 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1977
1978 if ((ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) && sc->ant_rx == 3)
1979 ath_ant_comb_scan(sc, &rs);
1980
1981 ieee80211_rx(hw, skb);
1982
1983 requeue_drop_frag:
1984 if (sc->rx.frag) {
1985 dev_kfree_skb_any(sc->rx.frag);
1986 sc->rx.frag = NULL;
1987 }
1988 requeue:
1989 if (edma) {
1990 list_add_tail(&bf->list, &sc->rx.rxbuf);
1991 ath_rx_edma_buf_link(sc, qtype);
1992 } else {
1993 list_move_tail(&bf->list, &sc->rx.rxbuf);
1994 ath_rx_buf_link(sc, bf);
1995 if (!flush)
1996 ath9k_hw_rxena(ah);
1997 }
1998 } while (1);
1999
2000 spin_unlock_bh(&sc->rx.rxbuflock);
2001
2002 if (!(ah->imask & ATH9K_INT_RXEOL)) {
2003 ah->imask |= (ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
2004 ath9k_hw_set_interrupts(ah);
2005 }
2006
2007 return 0;
2008 }
Linux kernel - Deliverables
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