2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/dma-mapping.h>
19 #include "ar9003_mac.h"
21 #define SKB_CB_ATHBUF(__skb) (*((struct ath_rxbuf **)__skb->cb))
23 static inline bool ath9k_check_auto_sleep(struct ath_softc
*sc
)
25 return sc
->ps_enabled
&&
26 (sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_AUTOSLEEP
);
30 * Setup and link descriptors.
32 * 11N: we can no longer afford to self link the last descriptor.
33 * MAC acknowledges BA status as long as it copies frames to host
34 * buffer (or rx fifo). This can incorrectly acknowledge packets
35 * to a sender if last desc is self-linked.
37 static void ath_rx_buf_link(struct ath_softc
*sc
, struct ath_rxbuf
*bf
,
40 struct ath_hw
*ah
= sc
->sc_ah
;
41 struct ath_common
*common
= ath9k_hw_common(ah
);
46 ds
->ds_link
= 0; /* link to null */
47 ds
->ds_data
= bf
->bf_buf_addr
;
49 /* virtual addr of the beginning of the buffer. */
52 ds
->ds_vdata
= skb
->data
;
55 * setup rx descriptors. The rx_bufsize here tells the hardware
56 * how much data it can DMA to us and that we are prepared
59 ath9k_hw_setuprxdesc(ah
, ds
,
64 *sc
->rx
.rxlink
= bf
->bf_daddr
;
66 ath9k_hw_putrxbuf(ah
, bf
->bf_daddr
);
68 sc
->rx
.rxlink
= &ds
->ds_link
;
71 static void ath_rx_buf_relink(struct ath_softc
*sc
, struct ath_rxbuf
*bf
,
75 ath_rx_buf_link(sc
, sc
->rx
.buf_hold
, flush
);
80 static void ath_setdefantenna(struct ath_softc
*sc
, u32 antenna
)
82 /* XXX block beacon interrupts */
83 ath9k_hw_setantenna(sc
->sc_ah
, antenna
);
84 sc
->rx
.defant
= antenna
;
85 sc
->rx
.rxotherant
= 0;
88 static void ath_opmode_init(struct ath_softc
*sc
)
90 struct ath_hw
*ah
= sc
->sc_ah
;
91 struct ath_common
*common
= ath9k_hw_common(ah
);
95 /* configure rx filter */
96 rfilt
= ath_calcrxfilter(sc
);
97 ath9k_hw_setrxfilter(ah
, rfilt
);
99 /* configure bssid mask */
100 ath_hw_setbssidmask(common
);
102 /* configure operational mode */
103 ath9k_hw_setopmode(ah
);
105 /* calculate and install multicast filter */
106 mfilt
[0] = mfilt
[1] = ~0;
107 ath9k_hw_setmcastfilter(ah
, mfilt
[0], mfilt
[1]);
110 static bool ath_rx_edma_buf_link(struct ath_softc
*sc
,
111 enum ath9k_rx_qtype qtype
)
113 struct ath_hw
*ah
= sc
->sc_ah
;
114 struct ath_rx_edma
*rx_edma
;
116 struct ath_rxbuf
*bf
;
118 rx_edma
= &sc
->rx
.rx_edma
[qtype
];
119 if (skb_queue_len(&rx_edma
->rx_fifo
) >= rx_edma
->rx_fifo_hwsize
)
122 bf
= list_first_entry(&sc
->rx
.rxbuf
, struct ath_rxbuf
, list
);
123 list_del_init(&bf
->list
);
127 memset(skb
->data
, 0, ah
->caps
.rx_status_len
);
128 dma_sync_single_for_device(sc
->dev
, bf
->bf_buf_addr
,
129 ah
->caps
.rx_status_len
, DMA_TO_DEVICE
);
131 SKB_CB_ATHBUF(skb
) = bf
;
132 ath9k_hw_addrxbuf_edma(ah
, bf
->bf_buf_addr
, qtype
);
133 __skb_queue_tail(&rx_edma
->rx_fifo
, skb
);
138 static void ath_rx_addbuffer_edma(struct ath_softc
*sc
,
139 enum ath9k_rx_qtype qtype
)
141 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
142 struct ath_rxbuf
*bf
, *tbf
;
144 if (list_empty(&sc
->rx
.rxbuf
)) {
145 ath_dbg(common
, QUEUE
, "No free rx buf available\n");
149 list_for_each_entry_safe(bf
, tbf
, &sc
->rx
.rxbuf
, list
)
150 if (!ath_rx_edma_buf_link(sc
, qtype
))
155 static void ath_rx_remove_buffer(struct ath_softc
*sc
,
156 enum ath9k_rx_qtype qtype
)
158 struct ath_rxbuf
*bf
;
159 struct ath_rx_edma
*rx_edma
;
162 rx_edma
= &sc
->rx
.rx_edma
[qtype
];
164 while ((skb
= __skb_dequeue(&rx_edma
->rx_fifo
)) != NULL
) {
165 bf
= SKB_CB_ATHBUF(skb
);
167 list_add_tail(&bf
->list
, &sc
->rx
.rxbuf
);
171 static void ath_rx_edma_cleanup(struct ath_softc
*sc
)
173 struct ath_hw
*ah
= sc
->sc_ah
;
174 struct ath_common
*common
= ath9k_hw_common(ah
);
175 struct ath_rxbuf
*bf
;
177 ath_rx_remove_buffer(sc
, ATH9K_RX_QUEUE_LP
);
178 ath_rx_remove_buffer(sc
, ATH9K_RX_QUEUE_HP
);
180 list_for_each_entry(bf
, &sc
->rx
.rxbuf
, list
) {
182 dma_unmap_single(sc
->dev
, bf
->bf_buf_addr
,
185 dev_kfree_skb_any(bf
->bf_mpdu
);
192 static void ath_rx_edma_init_queue(struct ath_rx_edma
*rx_edma
, int size
)
194 __skb_queue_head_init(&rx_edma
->rx_fifo
);
195 rx_edma
->rx_fifo_hwsize
= size
;
198 static int ath_rx_edma_init(struct ath_softc
*sc
, int nbufs
)
200 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
201 struct ath_hw
*ah
= sc
->sc_ah
;
203 struct ath_rxbuf
*bf
;
207 ath9k_hw_set_rx_bufsize(ah
, common
->rx_bufsize
-
208 ah
->caps
.rx_status_len
);
210 ath_rx_edma_init_queue(&sc
->rx
.rx_edma
[ATH9K_RX_QUEUE_LP
],
211 ah
->caps
.rx_lp_qdepth
);
212 ath_rx_edma_init_queue(&sc
->rx
.rx_edma
[ATH9K_RX_QUEUE_HP
],
213 ah
->caps
.rx_hp_qdepth
);
215 size
= sizeof(struct ath_rxbuf
) * nbufs
;
216 bf
= devm_kzalloc(sc
->dev
, size
, GFP_KERNEL
);
220 INIT_LIST_HEAD(&sc
->rx
.rxbuf
);
222 for (i
= 0; i
< nbufs
; i
++, bf
++) {
223 skb
= ath_rxbuf_alloc(common
, common
->rx_bufsize
, GFP_KERNEL
);
229 memset(skb
->data
, 0, common
->rx_bufsize
);
232 bf
->bf_buf_addr
= dma_map_single(sc
->dev
, skb
->data
,
235 if (unlikely(dma_mapping_error(sc
->dev
,
237 dev_kfree_skb_any(skb
);
241 "dma_mapping_error() on RX init\n");
246 list_add_tail(&bf
->list
, &sc
->rx
.rxbuf
);
252 ath_rx_edma_cleanup(sc
);
256 static void ath_edma_start_recv(struct ath_softc
*sc
)
258 ath9k_hw_rxena(sc
->sc_ah
);
259 ath_rx_addbuffer_edma(sc
, ATH9K_RX_QUEUE_HP
);
260 ath_rx_addbuffer_edma(sc
, ATH9K_RX_QUEUE_LP
);
262 ath9k_hw_startpcureceive(sc
->sc_ah
, sc
->cur_chan
->offchannel
);
265 static void ath_edma_stop_recv(struct ath_softc
*sc
)
267 ath_rx_remove_buffer(sc
, ATH9K_RX_QUEUE_HP
);
268 ath_rx_remove_buffer(sc
, ATH9K_RX_QUEUE_LP
);
271 int ath_rx_init(struct ath_softc
*sc
, int nbufs
)
273 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
275 struct ath_rxbuf
*bf
;
278 spin_lock_init(&sc
->sc_pcu_lock
);
280 common
->rx_bufsize
= IEEE80211_MAX_MPDU_LEN
/ 2 +
281 sc
->sc_ah
->caps
.rx_status_len
;
283 if (sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_EDMA
)
284 return ath_rx_edma_init(sc
, nbufs
);
286 ath_dbg(common
, CONFIG
, "cachelsz %u rxbufsize %u\n",
287 common
->cachelsz
, common
->rx_bufsize
);
289 /* Initialize rx descriptors */
291 error
= ath_descdma_setup(sc
, &sc
->rx
.rxdma
, &sc
->rx
.rxbuf
,
295 "failed to allocate rx descriptors: %d\n",
300 list_for_each_entry(bf
, &sc
->rx
.rxbuf
, list
) {
301 skb
= ath_rxbuf_alloc(common
, common
->rx_bufsize
,
309 bf
->bf_buf_addr
= dma_map_single(sc
->dev
, skb
->data
,
312 if (unlikely(dma_mapping_error(sc
->dev
,
314 dev_kfree_skb_any(skb
);
318 "dma_mapping_error() on RX init\n");
323 sc
->rx
.rxlink
= NULL
;
331 void ath_rx_cleanup(struct ath_softc
*sc
)
333 struct ath_hw
*ah
= sc
->sc_ah
;
334 struct ath_common
*common
= ath9k_hw_common(ah
);
336 struct ath_rxbuf
*bf
;
338 if (sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_EDMA
) {
339 ath_rx_edma_cleanup(sc
);
343 list_for_each_entry(bf
, &sc
->rx
.rxbuf
, list
) {
346 dma_unmap_single(sc
->dev
, bf
->bf_buf_addr
,
357 * Calculate the receive filter according to the
358 * operating mode and state:
360 * o always accept unicast, broadcast, and multicast traffic
361 * o maintain current state of phy error reception (the hal
362 * may enable phy error frames for noise immunity work)
363 * o probe request frames are accepted only when operating in
364 * hostap, adhoc, or monitor modes
365 * o enable promiscuous mode according to the interface state
367 * - when operating in adhoc mode so the 802.11 layer creates
368 * node table entries for peers,
369 * - when operating in station mode for collecting rssi data when
370 * the station is otherwise quiet, or
371 * - when operating as a repeater so we see repeater-sta beacons
375 u32
ath_calcrxfilter(struct ath_softc
*sc
)
377 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
380 if (config_enabled(CONFIG_ATH9K_TX99
))
383 rfilt
= ATH9K_RX_FILTER_UCAST
| ATH9K_RX_FILTER_BCAST
384 | ATH9K_RX_FILTER_MCAST
;
386 /* if operating on a DFS channel, enable radar pulse detection */
387 if (sc
->hw
->conf
.radar_enabled
)
388 rfilt
|= ATH9K_RX_FILTER_PHYRADAR
| ATH9K_RX_FILTER_PHYERR
;
390 spin_lock_bh(&sc
->chan_lock
);
392 if (sc
->cur_chan
->rxfilter
& FIF_PROBE_REQ
)
393 rfilt
|= ATH9K_RX_FILTER_PROBEREQ
;
396 * Set promiscuous mode when FIF_PROMISC_IN_BSS is enabled for station
397 * mode interface or when in monitor mode. AP mode does not need this
398 * since it receives all in-BSS frames anyway.
400 if (sc
->sc_ah
->is_monitoring
)
401 rfilt
|= ATH9K_RX_FILTER_PROM
;
403 if ((sc
->cur_chan
->rxfilter
& FIF_CONTROL
) ||
404 sc
->sc_ah
->dynack
.enabled
)
405 rfilt
|= ATH9K_RX_FILTER_CONTROL
;
407 if ((sc
->sc_ah
->opmode
== NL80211_IFTYPE_STATION
) &&
408 (sc
->cur_chan
->nvifs
<= 1) &&
409 !(sc
->cur_chan
->rxfilter
& FIF_BCN_PRBRESP_PROMISC
))
410 rfilt
|= ATH9K_RX_FILTER_MYBEACON
;
412 rfilt
|= ATH9K_RX_FILTER_BEACON
;
414 if ((sc
->sc_ah
->opmode
== NL80211_IFTYPE_AP
) ||
415 (sc
->cur_chan
->rxfilter
& FIF_PSPOLL
))
416 rfilt
|= ATH9K_RX_FILTER_PSPOLL
;
418 if (sc
->cur_chandef
.width
!= NL80211_CHAN_WIDTH_20_NOHT
)
419 rfilt
|= ATH9K_RX_FILTER_COMP_BAR
;
421 if (sc
->cur_chan
->nvifs
> 1 || (sc
->cur_chan
->rxfilter
& FIF_OTHER_BSS
)) {
422 /* This is needed for older chips */
423 if (sc
->sc_ah
->hw_version
.macVersion
<= AR_SREV_VERSION_9160
)
424 rfilt
|= ATH9K_RX_FILTER_PROM
;
425 rfilt
|= ATH9K_RX_FILTER_MCAST_BCAST_ALL
;
428 if (AR_SREV_9550(sc
->sc_ah
) || AR_SREV_9531(sc
->sc_ah
))
429 rfilt
|= ATH9K_RX_FILTER_4ADDRESS
;
431 if (ath9k_is_chanctx_enabled() &&
432 test_bit(ATH_OP_SCANNING
, &common
->op_flags
))
433 rfilt
|= ATH9K_RX_FILTER_BEACON
;
435 spin_unlock_bh(&sc
->chan_lock
);
441 void ath_startrecv(struct ath_softc
*sc
)
443 struct ath_hw
*ah
= sc
->sc_ah
;
444 struct ath_rxbuf
*bf
, *tbf
;
446 if (ah
->caps
.hw_caps
& ATH9K_HW_CAP_EDMA
) {
447 ath_edma_start_recv(sc
);
451 if (list_empty(&sc
->rx
.rxbuf
))
454 sc
->rx
.buf_hold
= NULL
;
455 sc
->rx
.rxlink
= NULL
;
456 list_for_each_entry_safe(bf
, tbf
, &sc
->rx
.rxbuf
, list
) {
457 ath_rx_buf_link(sc
, bf
, false);
460 /* We could have deleted elements so the list may be empty now */
461 if (list_empty(&sc
->rx
.rxbuf
))
464 bf
= list_first_entry(&sc
->rx
.rxbuf
, struct ath_rxbuf
, list
);
465 ath9k_hw_putrxbuf(ah
, bf
->bf_daddr
);
470 ath9k_hw_startpcureceive(ah
, sc
->cur_chan
->offchannel
);
473 static void ath_flushrecv(struct ath_softc
*sc
)
475 if (sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_EDMA
)
476 ath_rx_tasklet(sc
, 1, true);
477 ath_rx_tasklet(sc
, 1, false);
480 bool ath_stoprecv(struct ath_softc
*sc
)
482 struct ath_hw
*ah
= sc
->sc_ah
;
483 bool stopped
, reset
= false;
485 ath9k_hw_abortpcurecv(ah
);
486 ath9k_hw_setrxfilter(ah
, 0);
487 stopped
= ath9k_hw_stopdmarecv(ah
, &reset
);
491 if (sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_EDMA
)
492 ath_edma_stop_recv(sc
);
494 sc
->rx
.rxlink
= NULL
;
496 if (!(ah
->ah_flags
& AH_UNPLUGGED
) &&
497 unlikely(!stopped
)) {
498 ath_err(ath9k_hw_common(sc
->sc_ah
),
499 "Could not stop RX, we could be "
500 "confusing the DMA engine when we start RX up\n");
501 ATH_DBG_WARN_ON_ONCE(!stopped
);
503 return stopped
&& !reset
;
506 static bool ath_beacon_dtim_pending_cab(struct sk_buff
*skb
)
508 /* Check whether the Beacon frame has DTIM indicating buffered bc/mc */
509 struct ieee80211_mgmt
*mgmt
;
510 u8
*pos
, *end
, id
, elen
;
511 struct ieee80211_tim_ie
*tim
;
513 mgmt
= (struct ieee80211_mgmt
*)skb
->data
;
514 pos
= mgmt
->u
.beacon
.variable
;
515 end
= skb
->data
+ skb
->len
;
517 while (pos
+ 2 < end
) {
520 if (pos
+ elen
> end
)
523 if (id
== WLAN_EID_TIM
) {
524 if (elen
< sizeof(*tim
))
526 tim
= (struct ieee80211_tim_ie
*) pos
;
527 if (tim
->dtim_count
!= 0)
529 return tim
->bitmap_ctrl
& 0x01;
538 static void ath_rx_ps_beacon(struct ath_softc
*sc
, struct sk_buff
*skb
)
540 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
541 bool skip_beacon
= false;
543 if (skb
->len
< 24 + 8 + 2 + 2)
546 sc
->ps_flags
&= ~PS_WAIT_FOR_BEACON
;
548 if (sc
->ps_flags
& PS_BEACON_SYNC
) {
549 sc
->ps_flags
&= ~PS_BEACON_SYNC
;
551 "Reconfigure beacon timers based on synchronized timestamp\n");
553 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
554 if (ath9k_is_chanctx_enabled()) {
555 if (sc
->cur_chan
== &sc
->offchannel
.chan
)
561 !(WARN_ON_ONCE(sc
->cur_chan
->beacon
.beacon_interval
== 0)))
562 ath9k_set_beacon(sc
);
564 ath9k_p2p_beacon_sync(sc
);
567 if (ath_beacon_dtim_pending_cab(skb
)) {
569 * Remain awake waiting for buffered broadcast/multicast
570 * frames. If the last broadcast/multicast frame is not
571 * received properly, the next beacon frame will work as
572 * a backup trigger for returning into NETWORK SLEEP state,
573 * so we are waiting for it as well.
576 "Received DTIM beacon indicating buffered broadcast/multicast frame(s)\n");
577 sc
->ps_flags
|= PS_WAIT_FOR_CAB
| PS_WAIT_FOR_BEACON
;
581 if (sc
->ps_flags
& PS_WAIT_FOR_CAB
) {
583 * This can happen if a broadcast frame is dropped or the AP
584 * fails to send a frame indicating that all CAB frames have
587 sc
->ps_flags
&= ~PS_WAIT_FOR_CAB
;
588 ath_dbg(common
, PS
, "PS wait for CAB frames timed out\n");
592 static void ath_rx_ps(struct ath_softc
*sc
, struct sk_buff
*skb
, bool mybeacon
)
594 struct ieee80211_hdr
*hdr
;
595 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
597 hdr
= (struct ieee80211_hdr
*)skb
->data
;
599 /* Process Beacon and CAB receive in PS state */
600 if (((sc
->ps_flags
& PS_WAIT_FOR_BEACON
) || ath9k_check_auto_sleep(sc
))
602 ath_rx_ps_beacon(sc
, skb
);
603 } else if ((sc
->ps_flags
& PS_WAIT_FOR_CAB
) &&
604 (ieee80211_is_data(hdr
->frame_control
) ||
605 ieee80211_is_action(hdr
->frame_control
)) &&
606 is_multicast_ether_addr(hdr
->addr1
) &&
607 !ieee80211_has_moredata(hdr
->frame_control
)) {
609 * No more broadcast/multicast frames to be received at this
612 sc
->ps_flags
&= ~(PS_WAIT_FOR_CAB
| PS_WAIT_FOR_BEACON
);
614 "All PS CAB frames received, back to sleep\n");
615 } else if ((sc
->ps_flags
& PS_WAIT_FOR_PSPOLL_DATA
) &&
616 !is_multicast_ether_addr(hdr
->addr1
) &&
617 !ieee80211_has_morefrags(hdr
->frame_control
)) {
618 sc
->ps_flags
&= ~PS_WAIT_FOR_PSPOLL_DATA
;
620 "Going back to sleep after having received PS-Poll data (0x%lx)\n",
621 sc
->ps_flags
& (PS_WAIT_FOR_BEACON
|
623 PS_WAIT_FOR_PSPOLL_DATA
|
624 PS_WAIT_FOR_TX_ACK
));
628 static bool ath_edma_get_buffers(struct ath_softc
*sc
,
629 enum ath9k_rx_qtype qtype
,
630 struct ath_rx_status
*rs
,
631 struct ath_rxbuf
**dest
)
633 struct ath_rx_edma
*rx_edma
= &sc
->rx
.rx_edma
[qtype
];
634 struct ath_hw
*ah
= sc
->sc_ah
;
635 struct ath_common
*common
= ath9k_hw_common(ah
);
637 struct ath_rxbuf
*bf
;
640 skb
= skb_peek(&rx_edma
->rx_fifo
);
644 bf
= SKB_CB_ATHBUF(skb
);
647 dma_sync_single_for_cpu(sc
->dev
, bf
->bf_buf_addr
,
648 common
->rx_bufsize
, DMA_FROM_DEVICE
);
650 ret
= ath9k_hw_process_rxdesc_edma(ah
, rs
, skb
->data
);
651 if (ret
== -EINPROGRESS
) {
652 /*let device gain the buffer again*/
653 dma_sync_single_for_device(sc
->dev
, bf
->bf_buf_addr
,
654 common
->rx_bufsize
, DMA_FROM_DEVICE
);
658 __skb_unlink(skb
, &rx_edma
->rx_fifo
);
659 if (ret
== -EINVAL
) {
660 /* corrupt descriptor, skip this one and the following one */
661 list_add_tail(&bf
->list
, &sc
->rx
.rxbuf
);
662 ath_rx_edma_buf_link(sc
, qtype
);
664 skb
= skb_peek(&rx_edma
->rx_fifo
);
666 bf
= SKB_CB_ATHBUF(skb
);
669 __skb_unlink(skb
, &rx_edma
->rx_fifo
);
670 list_add_tail(&bf
->list
, &sc
->rx
.rxbuf
);
671 ath_rx_edma_buf_link(sc
, qtype
);
681 static struct ath_rxbuf
*ath_edma_get_next_rx_buf(struct ath_softc
*sc
,
682 struct ath_rx_status
*rs
,
683 enum ath9k_rx_qtype qtype
)
685 struct ath_rxbuf
*bf
= NULL
;
687 while (ath_edma_get_buffers(sc
, qtype
, rs
, &bf
)) {
696 static struct ath_rxbuf
*ath_get_next_rx_buf(struct ath_softc
*sc
,
697 struct ath_rx_status
*rs
)
699 struct ath_hw
*ah
= sc
->sc_ah
;
700 struct ath_common
*common
= ath9k_hw_common(ah
);
702 struct ath_rxbuf
*bf
;
705 if (list_empty(&sc
->rx
.rxbuf
)) {
706 sc
->rx
.rxlink
= NULL
;
710 bf
= list_first_entry(&sc
->rx
.rxbuf
, struct ath_rxbuf
, list
);
711 if (bf
== sc
->rx
.buf_hold
)
717 * Must provide the virtual address of the current
718 * descriptor, the physical address, and the virtual
719 * address of the next descriptor in the h/w chain.
720 * This allows the HAL to look ahead to see if the
721 * hardware is done with a descriptor by checking the
722 * done bit in the following descriptor and the address
723 * of the current descriptor the DMA engine is working
724 * on. All this is necessary because of our use of
725 * a self-linked list to avoid rx overruns.
727 ret
= ath9k_hw_rxprocdesc(ah
, ds
, rs
);
728 if (ret
== -EINPROGRESS
) {
729 struct ath_rx_status trs
;
730 struct ath_rxbuf
*tbf
;
731 struct ath_desc
*tds
;
733 memset(&trs
, 0, sizeof(trs
));
734 if (list_is_last(&bf
->list
, &sc
->rx
.rxbuf
)) {
735 sc
->rx
.rxlink
= NULL
;
739 tbf
= list_entry(bf
->list
.next
, struct ath_rxbuf
, list
);
742 * On some hardware the descriptor status words could
743 * get corrupted, including the done bit. Because of
744 * this, check if the next descriptor's done bit is
747 * If the next descriptor's done bit is set, the current
748 * descriptor has been corrupted. Force s/w to discard
749 * this descriptor and continue...
753 ret
= ath9k_hw_rxprocdesc(ah
, tds
, &trs
);
754 if (ret
== -EINPROGRESS
)
758 * Re-check previous descriptor, in case it has been filled
761 ret
= ath9k_hw_rxprocdesc(ah
, ds
, rs
);
762 if (ret
== -EINPROGRESS
) {
764 * mark descriptor as zero-length and set the 'more'
765 * flag to ensure that both buffers get discarded
777 * Synchronize the DMA transfer with CPU before
778 * 1. accessing the frame
779 * 2. requeueing the same buffer to h/w
781 dma_sync_single_for_cpu(sc
->dev
, bf
->bf_buf_addr
,
788 static void ath9k_process_tsf(struct ath_rx_status
*rs
,
789 struct ieee80211_rx_status
*rxs
,
792 u32 tsf_lower
= tsf
& 0xffffffff;
794 rxs
->mactime
= (tsf
& ~0xffffffffULL
) | rs
->rs_tstamp
;
795 if (rs
->rs_tstamp
> tsf_lower
&&
796 unlikely(rs
->rs_tstamp
- tsf_lower
> 0x10000000))
797 rxs
->mactime
-= 0x100000000ULL
;
799 if (rs
->rs_tstamp
< tsf_lower
&&
800 unlikely(tsf_lower
- rs
->rs_tstamp
> 0x10000000))
801 rxs
->mactime
+= 0x100000000ULL
;
805 * For Decrypt or Demic errors, we only mark packet status here and always push
806 * up the frame up to let mac80211 handle the actual error case, be it no
807 * decryption key or real decryption error. This let us keep statistics there.
809 static int ath9k_rx_skb_preprocess(struct ath_softc
*sc
,
811 struct ath_rx_status
*rx_stats
,
812 struct ieee80211_rx_status
*rx_status
,
813 bool *decrypt_error
, u64 tsf
)
815 struct ieee80211_hw
*hw
= sc
->hw
;
816 struct ath_hw
*ah
= sc
->sc_ah
;
817 struct ath_common
*common
= ath9k_hw_common(ah
);
818 struct ieee80211_hdr
*hdr
;
819 bool discard_current
= sc
->rx
.discard_next
;
822 * Discard corrupt descriptors which are marked in
823 * ath_get_next_rx_buf().
828 sc
->rx
.discard_next
= false;
831 * Discard zero-length packets.
833 if (!rx_stats
->rs_datalen
) {
834 RX_STAT_INC(rx_len_err
);
839 * rs_status follows rs_datalen so if rs_datalen is too large
840 * we can take a hint that hardware corrupted it, so ignore
843 if (rx_stats
->rs_datalen
> (common
->rx_bufsize
- ah
->caps
.rx_status_len
)) {
844 RX_STAT_INC(rx_len_err
);
848 /* Only use status info from the last fragment */
849 if (rx_stats
->rs_more
)
853 * Return immediately if the RX descriptor has been marked
854 * as corrupt based on the various error bits.
856 * This is different from the other corrupt descriptor
857 * condition handled above.
859 if (rx_stats
->rs_status
& ATH9K_RXERR_CORRUPT_DESC
)
862 hdr
= (struct ieee80211_hdr
*) (skb
->data
+ ah
->caps
.rx_status_len
);
864 ath9k_process_tsf(rx_stats
, rx_status
, tsf
);
865 ath_debug_stat_rx(sc
, rx_stats
);
868 * Process PHY errors and return so that the packet
871 if (rx_stats
->rs_status
& ATH9K_RXERR_PHY
) {
872 ath9k_dfs_process_phyerr(sc
, hdr
, rx_stats
, rx_status
->mactime
);
873 if (ath_cmn_process_fft(&sc
->spec_priv
, hdr
, rx_stats
, rx_status
->mactime
))
874 RX_STAT_INC(rx_spectral
);
880 * everything but the rate is checked here, the rate check is done
881 * separately to avoid doing two lookups for a rate for each frame.
883 spin_lock_bh(&sc
->chan_lock
);
884 if (!ath9k_cmn_rx_accept(common
, hdr
, rx_status
, rx_stats
, decrypt_error
,
885 sc
->cur_chan
->rxfilter
)) {
886 spin_unlock_bh(&sc
->chan_lock
);
889 spin_unlock_bh(&sc
->chan_lock
);
891 if (ath_is_mybeacon(common
, hdr
)) {
892 RX_STAT_INC(rx_beacons
);
893 rx_stats
->is_mybeacon
= true;
897 * This shouldn't happen, but have a safety check anyway.
899 if (WARN_ON(!ah
->curchan
))
902 if (ath9k_cmn_process_rate(common
, hw
, rx_stats
, rx_status
)) {
904 * No valid hardware bitrate found -- we should not get here
905 * because hardware has already validated this frame as OK.
907 ath_dbg(common
, ANY
, "unsupported hw bitrate detected 0x%02x using 1 Mbit\n",
909 RX_STAT_INC(rx_rate_err
);
913 if (ath9k_is_chanctx_enabled()) {
914 if (rx_stats
->is_mybeacon
)
915 ath_chanctx_beacon_recv_ev(sc
,
916 ATH_CHANCTX_EVENT_BEACON_RECEIVED
);
919 ath9k_cmn_process_rssi(common
, hw
, rx_stats
, rx_status
);
921 rx_status
->band
= ah
->curchan
->chan
->band
;
922 rx_status
->freq
= ah
->curchan
->chan
->center_freq
;
923 rx_status
->antenna
= rx_stats
->rs_antenna
;
924 rx_status
->flag
|= RX_FLAG_MACTIME_END
;
926 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
927 if (ieee80211_is_data_present(hdr
->frame_control
) &&
928 !ieee80211_is_qos_nullfunc(hdr
->frame_control
))
935 sc
->rx
.discard_next
= rx_stats
->rs_more
;
940 * Run the LNA combining algorithm only in these cases:
942 * Standalone WLAN cards with both LNA/Antenna diversity
943 * enabled in the EEPROM.
945 * WLAN+BT cards which are in the supported card list
946 * in ath_pci_id_table and the user has loaded the
947 * driver with "bt_ant_diversity" set to true.
949 static void ath9k_antenna_check(struct ath_softc
*sc
,
950 struct ath_rx_status
*rs
)
952 struct ath_hw
*ah
= sc
->sc_ah
;
953 struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
954 struct ath_common
*common
= ath9k_hw_common(ah
);
956 if (!(ah
->caps
.hw_caps
& ATH9K_HW_CAP_ANT_DIV_COMB
))
960 * Change the default rx antenna if rx diversity
961 * chooses the other antenna 3 times in a row.
963 if (sc
->rx
.defant
!= rs
->rs_antenna
) {
964 if (++sc
->rx
.rxotherant
>= 3)
965 ath_setdefantenna(sc
, rs
->rs_antenna
);
967 sc
->rx
.rxotherant
= 0;
970 if (pCap
->hw_caps
& ATH9K_HW_CAP_BT_ANT_DIV
) {
971 if (common
->bt_ant_diversity
)
972 ath_ant_comb_scan(sc
, rs
);
974 ath_ant_comb_scan(sc
, rs
);
978 static void ath9k_apply_ampdu_details(struct ath_softc
*sc
,
979 struct ath_rx_status
*rs
, struct ieee80211_rx_status
*rxs
)
982 rxs
->flag
|= RX_FLAG_AMPDU_DETAILS
| RX_FLAG_AMPDU_LAST_KNOWN
;
984 rxs
->ampdu_reference
= sc
->rx
.ampdu_ref
;
986 if (!rs
->rs_moreaggr
) {
987 rxs
->flag
|= RX_FLAG_AMPDU_IS_LAST
;
991 if (rs
->rs_flags
& ATH9K_RX_DELIM_CRC_PRE
)
992 rxs
->flag
|= RX_FLAG_AMPDU_DELIM_CRC_ERROR
;
996 int ath_rx_tasklet(struct ath_softc
*sc
, int flush
, bool hp
)
998 struct ath_rxbuf
*bf
;
999 struct sk_buff
*skb
= NULL
, *requeue_skb
, *hdr_skb
;
1000 struct ieee80211_rx_status
*rxs
;
1001 struct ath_hw
*ah
= sc
->sc_ah
;
1002 struct ath_common
*common
= ath9k_hw_common(ah
);
1003 struct ieee80211_hw
*hw
= sc
->hw
;
1005 struct ath_rx_status rs
;
1006 enum ath9k_rx_qtype qtype
;
1007 bool edma
= !!(ah
->caps
.hw_caps
& ATH9K_HW_CAP_EDMA
);
1010 unsigned long flags
;
1011 dma_addr_t new_buf_addr
;
1012 unsigned int budget
= 512;
1013 struct ieee80211_hdr
*hdr
;
1016 dma_type
= DMA_BIDIRECTIONAL
;
1018 dma_type
= DMA_FROM_DEVICE
;
1020 qtype
= hp
? ATH9K_RX_QUEUE_HP
: ATH9K_RX_QUEUE_LP
;
1022 tsf
= ath9k_hw_gettsf64(ah
);
1025 bool decrypt_error
= false;
1027 memset(&rs
, 0, sizeof(rs
));
1029 bf
= ath_edma_get_next_rx_buf(sc
, &rs
, qtype
);
1031 bf
= ath_get_next_rx_buf(sc
, &rs
);
1041 * Take frame header from the first fragment and RX status from
1045 hdr_skb
= sc
->rx
.frag
;
1049 rxs
= IEEE80211_SKB_RXCB(hdr_skb
);
1050 memset(rxs
, 0, sizeof(struct ieee80211_rx_status
));
1052 retval
= ath9k_rx_skb_preprocess(sc
, hdr_skb
, &rs
, rxs
,
1053 &decrypt_error
, tsf
);
1055 goto requeue_drop_frag
;
1057 /* Ensure we always have an skb to requeue once we are done
1058 * processing the current buffer's skb */
1059 requeue_skb
= ath_rxbuf_alloc(common
, common
->rx_bufsize
, GFP_ATOMIC
);
1061 /* If there is no memory we ignore the current RX'd frame,
1062 * tell hardware it can give us a new frame using the old
1063 * skb and put it at the tail of the sc->rx.rxbuf list for
1066 RX_STAT_INC(rx_oom_err
);
1067 goto requeue_drop_frag
;
1070 /* We will now give hardware our shiny new allocated skb */
1071 new_buf_addr
= dma_map_single(sc
->dev
, requeue_skb
->data
,
1072 common
->rx_bufsize
, dma_type
);
1073 if (unlikely(dma_mapping_error(sc
->dev
, new_buf_addr
))) {
1074 dev_kfree_skb_any(requeue_skb
);
1075 goto requeue_drop_frag
;
1078 /* Unmap the frame */
1079 dma_unmap_single(sc
->dev
, bf
->bf_buf_addr
,
1080 common
->rx_bufsize
, dma_type
);
1082 bf
->bf_mpdu
= requeue_skb
;
1083 bf
->bf_buf_addr
= new_buf_addr
;
1085 skb_put(skb
, rs
.rs_datalen
+ ah
->caps
.rx_status_len
);
1086 if (ah
->caps
.rx_status_len
)
1087 skb_pull(skb
, ah
->caps
.rx_status_len
);
1090 ath9k_cmn_rx_skb_postprocess(common
, hdr_skb
, &rs
,
1091 rxs
, decrypt_error
);
1094 RX_STAT_INC(rx_frags
);
1096 * rs_more indicates chained descriptors which can be
1097 * used to link buffers together for a sort of
1098 * scatter-gather operation.
1101 /* too many fragments - cannot handle frame */
1102 dev_kfree_skb_any(sc
->rx
.frag
);
1103 dev_kfree_skb_any(skb
);
1104 RX_STAT_INC(rx_too_many_frags_err
);
1112 int space
= skb
->len
- skb_tailroom(hdr_skb
);
1114 if (pskb_expand_head(hdr_skb
, 0, space
, GFP_ATOMIC
) < 0) {
1116 RX_STAT_INC(rx_oom_err
);
1117 goto requeue_drop_frag
;
1122 skb_copy_from_linear_data(skb
, skb_put(hdr_skb
, skb
->len
),
1124 dev_kfree_skb_any(skb
);
1128 if (rxs
->flag
& RX_FLAG_MMIC_STRIPPED
)
1129 skb_trim(skb
, skb
->len
- 8);
1131 spin_lock_irqsave(&sc
->sc_pm_lock
, flags
);
1132 if ((sc
->ps_flags
& (PS_WAIT_FOR_BEACON
|
1134 PS_WAIT_FOR_PSPOLL_DATA
)) ||
1135 ath9k_check_auto_sleep(sc
))
1136 ath_rx_ps(sc
, skb
, rs
.is_mybeacon
);
1137 spin_unlock_irqrestore(&sc
->sc_pm_lock
, flags
);
1139 ath9k_antenna_check(sc
, &rs
);
1140 ath9k_apply_ampdu_details(sc
, &rs
, rxs
);
1141 ath_debug_rate_stats(sc
, &rs
, skb
);
1143 hdr
= (struct ieee80211_hdr
*)skb
->data
;
1144 if (ieee80211_is_ack(hdr
->frame_control
))
1145 ath_dynack_sample_ack_ts(sc
->sc_ah
, skb
, rs
.rs_tstamp
);
1147 ieee80211_rx(hw
, skb
);
1151 dev_kfree_skb_any(sc
->rx
.frag
);
1155 list_add_tail(&bf
->list
, &sc
->rx
.rxbuf
);
1158 ath_rx_buf_relink(sc
, bf
, flush
);
1161 } else if (!flush
) {
1162 ath_rx_edma_buf_link(sc
, qtype
);
1169 if (!(ah
->imask
& ATH9K_INT_RXEOL
)) {
1170 ah
->imask
|= (ATH9K_INT_RXEOL
| ATH9K_INT_RXORN
);
1171 ath9k_hw_set_interrupts(ah
);