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02df4cbf179f4ab1ebdb3cf93c66cc2be7273df4
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / xmit.c
1 /*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include "ath9k.h"
18
19 #define BITS_PER_BYTE 8
20 #define OFDM_PLCP_BITS 22
21 #define HT_RC_2_MCS(_rc) ((_rc) & 0x0f)
22 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
23 #define L_STF 8
24 #define L_LTF 8
25 #define L_SIG 4
26 #define HT_SIG 8
27 #define HT_STF 4
28 #define HT_LTF(_ns) (4 * (_ns))
29 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
30 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
31 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
32 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
33
34 #define OFDM_SIFS_TIME 16
35
36 static u32 bits_per_symbol[][2] = {
37 /* 20MHz 40MHz */
38 { 26, 54 }, /* 0: BPSK */
39 { 52, 108 }, /* 1: QPSK 1/2 */
40 { 78, 162 }, /* 2: QPSK 3/4 */
41 { 104, 216 }, /* 3: 16-QAM 1/2 */
42 { 156, 324 }, /* 4: 16-QAM 3/4 */
43 { 208, 432 }, /* 5: 64-QAM 2/3 */
44 { 234, 486 }, /* 6: 64-QAM 3/4 */
45 { 260, 540 }, /* 7: 64-QAM 5/6 */
46 { 52, 108 }, /* 8: BPSK */
47 { 104, 216 }, /* 9: QPSK 1/2 */
48 { 156, 324 }, /* 10: QPSK 3/4 */
49 { 208, 432 }, /* 11: 16-QAM 1/2 */
50 { 312, 648 }, /* 12: 16-QAM 3/4 */
51 { 416, 864 }, /* 13: 64-QAM 2/3 */
52 { 468, 972 }, /* 14: 64-QAM 3/4 */
53 { 520, 1080 }, /* 15: 64-QAM 5/6 */
54 };
55
56 #define IS_HT_RATE(_rate) ((_rate) & 0x80)
57
58 static void ath_tx_send_ht_normal(struct ath_softc *sc, struct ath_txq *txq,
59 struct ath_atx_tid *tid,
60 struct list_head *bf_head);
61 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
62 struct ath_txq *txq, struct list_head *bf_q,
63 struct ath_tx_status *ts, int txok, int sendbar);
64 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
65 struct list_head *head);
66 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf);
67 static int ath_tx_num_badfrms(struct ath_softc *sc, struct ath_buf *bf,
68 struct ath_tx_status *ts, int txok);
69 static void ath_tx_rc_status(struct ath_buf *bf, struct ath_tx_status *ts,
70 int nbad, int txok, bool update_rc);
71
72 enum {
73 MCS_DEFAULT,
74 MCS_HT40,
75 MCS_HT40_SGI,
76 };
77
78 static int ath_max_4ms_framelen[3][16] = {
79 [MCS_DEFAULT] = {
80 3216, 6434, 9650, 12868, 19304, 25740, 28956, 32180,
81 6430, 12860, 19300, 25736, 38600, 51472, 57890, 64320,
82 },
83 [MCS_HT40] = {
84 6684, 13368, 20052, 26738, 40104, 53476, 60156, 66840,
85 13360, 26720, 40080, 53440, 80160, 106880, 120240, 133600,
86 },
87 [MCS_HT40_SGI] = {
88 /* TODO: Only MCS 7 and 15 updated, recalculate the rest */
89 6684, 13368, 20052, 26738, 40104, 53476, 60156, 74200,
90 13360, 26720, 40080, 53440, 80160, 106880, 120240, 148400,
91 }
92 };
93
94
95 /*********************/
96 /* Aggregation logic */
97 /*********************/
98
99 static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
100 {
101 struct ath_atx_ac *ac = tid->ac;
102
103 if (tid->paused)
104 return;
105
106 if (tid->sched)
107 return;
108
109 tid->sched = true;
110 list_add_tail(&tid->list, &ac->tid_q);
111
112 if (ac->sched)
113 return;
114
115 ac->sched = true;
116 list_add_tail(&ac->list, &txq->axq_acq);
117 }
118
119 static void ath_tx_pause_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
120 {
121 struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum];
122
123 spin_lock_bh(&txq->axq_lock);
124 tid->paused++;
125 spin_unlock_bh(&txq->axq_lock);
126 }
127
128 static void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
129 {
130 struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum];
131
132 BUG_ON(tid->paused <= 0);
133 spin_lock_bh(&txq->axq_lock);
134
135 tid->paused--;
136
137 if (tid->paused > 0)
138 goto unlock;
139
140 if (list_empty(&tid->buf_q))
141 goto unlock;
142
143 ath_tx_queue_tid(txq, tid);
144 ath_txq_schedule(sc, txq);
145 unlock:
146 spin_unlock_bh(&txq->axq_lock);
147 }
148
149 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
150 {
151 struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum];
152 struct ath_buf *bf;
153 struct list_head bf_head;
154 INIT_LIST_HEAD(&bf_head);
155
156 BUG_ON(tid->paused <= 0);
157 spin_lock_bh(&txq->axq_lock);
158
159 tid->paused--;
160
161 if (tid->paused > 0) {
162 spin_unlock_bh(&txq->axq_lock);
163 return;
164 }
165
166 while (!list_empty(&tid->buf_q)) {
167 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
168 BUG_ON(bf_isretried(bf));
169 list_move_tail(&bf->list, &bf_head);
170 ath_tx_send_ht_normal(sc, txq, tid, &bf_head);
171 }
172
173 spin_unlock_bh(&txq->axq_lock);
174 }
175
176 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
177 int seqno)
178 {
179 int index, cindex;
180
181 index = ATH_BA_INDEX(tid->seq_start, seqno);
182 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
183
184 tid->tx_buf[cindex] = NULL;
185
186 while (tid->baw_head != tid->baw_tail && !tid->tx_buf[tid->baw_head]) {
187 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
188 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
189 }
190 }
191
192 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
193 struct ath_buf *bf)
194 {
195 int index, cindex;
196
197 if (bf_isretried(bf))
198 return;
199
200 index = ATH_BA_INDEX(tid->seq_start, bf->bf_seqno);
201 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
202
203 BUG_ON(tid->tx_buf[cindex] != NULL);
204 tid->tx_buf[cindex] = bf;
205
206 if (index >= ((tid->baw_tail - tid->baw_head) &
207 (ATH_TID_MAX_BUFS - 1))) {
208 tid->baw_tail = cindex;
209 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
210 }
211 }
212
213 /*
214 * TODO: For frame(s) that are in the retry state, we will reuse the
215 * sequence number(s) without setting the retry bit. The
216 * alternative is to give up on these and BAR the receiver's window
217 * forward.
218 */
219 static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
220 struct ath_atx_tid *tid)
221
222 {
223 struct ath_buf *bf;
224 struct list_head bf_head;
225 struct ath_tx_status ts;
226
227 memset(&ts, 0, sizeof(ts));
228 INIT_LIST_HEAD(&bf_head);
229
230 for (;;) {
231 if (list_empty(&tid->buf_q))
232 break;
233
234 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
235 list_move_tail(&bf->list, &bf_head);
236
237 if (bf_isretried(bf))
238 ath_tx_update_baw(sc, tid, bf->bf_seqno);
239
240 spin_unlock(&txq->axq_lock);
241 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
242 spin_lock(&txq->axq_lock);
243 }
244
245 tid->seq_next = tid->seq_start;
246 tid->baw_tail = tid->baw_head;
247 }
248
249 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq,
250 struct ath_buf *bf)
251 {
252 struct sk_buff *skb;
253 struct ieee80211_hdr *hdr;
254
255 bf->bf_state.bf_type |= BUF_RETRY;
256 bf->bf_retries++;
257 TX_STAT_INC(txq->axq_qnum, a_retries);
258
259 skb = bf->bf_mpdu;
260 hdr = (struct ieee80211_hdr *)skb->data;
261 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
262 }
263
264 static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
265 {
266 struct ath_buf *tbf;
267
268 spin_lock_bh(&sc->tx.txbuflock);
269 if (WARN_ON(list_empty(&sc->tx.txbuf))) {
270 spin_unlock_bh(&sc->tx.txbuflock);
271 return NULL;
272 }
273 tbf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
274 list_del(&tbf->list);
275 spin_unlock_bh(&sc->tx.txbuflock);
276
277 ATH_TXBUF_RESET(tbf);
278
279 tbf->aphy = bf->aphy;
280 tbf->bf_mpdu = bf->bf_mpdu;
281 tbf->bf_buf_addr = bf->bf_buf_addr;
282 *(tbf->bf_desc) = *(bf->bf_desc);
283 tbf->bf_state = bf->bf_state;
284 tbf->bf_dmacontext = bf->bf_dmacontext;
285
286 return tbf;
287 }
288
289 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
290 struct ath_buf *bf, struct list_head *bf_q,
291 struct ath_tx_status *ts, int txok)
292 {
293 struct ath_node *an = NULL;
294 struct sk_buff *skb;
295 struct ieee80211_sta *sta;
296 struct ieee80211_hw *hw;
297 struct ieee80211_hdr *hdr;
298 struct ieee80211_tx_info *tx_info;
299 struct ath_atx_tid *tid = NULL;
300 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
301 struct list_head bf_head, bf_pending;
302 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0;
303 u32 ba[WME_BA_BMP_SIZE >> 5];
304 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
305 bool rc_update = true;
306
307 skb = bf->bf_mpdu;
308 hdr = (struct ieee80211_hdr *)skb->data;
309
310 tx_info = IEEE80211_SKB_CB(skb);
311 hw = bf->aphy->hw;
312
313 rcu_read_lock();
314
315 /* XXX: use ieee80211_find_sta! */
316 sta = ieee80211_find_sta_by_hw(hw, hdr->addr1);
317 if (!sta) {
318 rcu_read_unlock();
319 return;
320 }
321
322 an = (struct ath_node *)sta->drv_priv;
323 tid = ATH_AN_2_TID(an, bf->bf_tidno);
324
325 isaggr = bf_isaggr(bf);
326 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
327
328 if (isaggr && txok) {
329 if (ts->ts_flags & ATH9K_TX_BA) {
330 seq_st = ts->ts_seqnum;
331 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
332 } else {
333 /*
334 * AR5416 can become deaf/mute when BA
335 * issue happens. Chip needs to be reset.
336 * But AP code may have sychronization issues
337 * when perform internal reset in this routine.
338 * Only enable reset in STA mode for now.
339 */
340 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
341 needreset = 1;
342 }
343 }
344
345 INIT_LIST_HEAD(&bf_pending);
346 INIT_LIST_HEAD(&bf_head);
347
348 nbad = ath_tx_num_badfrms(sc, bf, ts, txok);
349 while (bf) {
350 txfail = txpending = 0;
351 bf_next = bf->bf_next;
352
353 if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, bf->bf_seqno))) {
354 /* transmit completion, subframe is
355 * acked by block ack */
356 acked_cnt++;
357 } else if (!isaggr && txok) {
358 /* transmit completion */
359 acked_cnt++;
360 } else {
361 if (!(tid->state & AGGR_CLEANUP) &&
362 ts->ts_flags != ATH9K_TX_SW_ABORTED) {
363 if (bf->bf_retries < ATH_MAX_SW_RETRIES) {
364 ath_tx_set_retry(sc, txq, bf);
365 txpending = 1;
366 } else {
367 bf->bf_state.bf_type |= BUF_XRETRY;
368 txfail = 1;
369 sendbar = 1;
370 txfail_cnt++;
371 }
372 } else {
373 /*
374 * cleanup in progress, just fail
375 * the un-acked sub-frames
376 */
377 txfail = 1;
378 }
379 }
380
381 if (bf_next == NULL) {
382 /*
383 * Make sure the last desc is reclaimed if it
384 * not a holding desc.
385 */
386 if (!bf_last->bf_stale)
387 list_move_tail(&bf->list, &bf_head);
388 else
389 INIT_LIST_HEAD(&bf_head);
390 } else {
391 BUG_ON(list_empty(bf_q));
392 list_move_tail(&bf->list, &bf_head);
393 }
394
395 if (!txpending) {
396 /*
397 * complete the acked-ones/xretried ones; update
398 * block-ack window
399 */
400 spin_lock_bh(&txq->axq_lock);
401 ath_tx_update_baw(sc, tid, bf->bf_seqno);
402 spin_unlock_bh(&txq->axq_lock);
403
404 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
405 ath_tx_rc_status(bf, ts, nbad, txok, true);
406 rc_update = false;
407 } else {
408 ath_tx_rc_status(bf, ts, nbad, txok, false);
409 }
410
411 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
412 !txfail, sendbar);
413 } else {
414 /* retry the un-acked ones */
415 if (bf->bf_next == NULL && bf_last->bf_stale) {
416 struct ath_buf *tbf;
417
418 tbf = ath_clone_txbuf(sc, bf_last);
419 /*
420 * Update tx baw and complete the frame with
421 * failed status if we run out of tx buf
422 */
423 if (!tbf) {
424 spin_lock_bh(&txq->axq_lock);
425 ath_tx_update_baw(sc, tid,
426 bf->bf_seqno);
427 spin_unlock_bh(&txq->axq_lock);
428
429 bf->bf_state.bf_type |= BUF_XRETRY;
430 ath_tx_rc_status(bf, ts, nbad,
431 0, false);
432 ath_tx_complete_buf(sc, bf, txq,
433 &bf_head, ts, 0, 0);
434 break;
435 }
436
437 ath9k_hw_cleartxdesc(sc->sc_ah, tbf->bf_desc);
438 list_add_tail(&tbf->list, &bf_head);
439 } else {
440 /*
441 * Clear descriptor status words for
442 * software retry
443 */
444 ath9k_hw_cleartxdesc(sc->sc_ah, bf->bf_desc);
445 }
446
447 /*
448 * Put this buffer to the temporary pending
449 * queue to retain ordering
450 */
451 list_splice_tail_init(&bf_head, &bf_pending);
452 }
453
454 bf = bf_next;
455 }
456
457 if (tid->state & AGGR_CLEANUP) {
458 if (tid->baw_head == tid->baw_tail) {
459 tid->state &= ~AGGR_ADDBA_COMPLETE;
460 tid->state &= ~AGGR_CLEANUP;
461
462 /* send buffered frames as singles */
463 ath_tx_flush_tid(sc, tid);
464 }
465 rcu_read_unlock();
466 return;
467 }
468
469 /* prepend un-acked frames to the beginning of the pending frame queue */
470 if (!list_empty(&bf_pending)) {
471 spin_lock_bh(&txq->axq_lock);
472 list_splice(&bf_pending, &tid->buf_q);
473 ath_tx_queue_tid(txq, tid);
474 spin_unlock_bh(&txq->axq_lock);
475 }
476
477 rcu_read_unlock();
478
479 if (needreset)
480 ath_reset(sc, false);
481 }
482
483 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
484 struct ath_atx_tid *tid)
485 {
486 struct sk_buff *skb;
487 struct ieee80211_tx_info *tx_info;
488 struct ieee80211_tx_rate *rates;
489 u32 max_4ms_framelen, frmlen;
490 u16 aggr_limit, legacy = 0;
491 int i;
492
493 skb = bf->bf_mpdu;
494 tx_info = IEEE80211_SKB_CB(skb);
495 rates = tx_info->control.rates;
496
497 /*
498 * Find the lowest frame length among the rate series that will have a
499 * 4ms transmit duration.
500 * TODO - TXOP limit needs to be considered.
501 */
502 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
503
504 for (i = 0; i < 4; i++) {
505 if (rates[i].count) {
506 int modeidx;
507 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) {
508 legacy = 1;
509 break;
510 }
511
512 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
513 modeidx = MCS_HT40_SGI;
514 else if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
515 modeidx = MCS_HT40;
516 else
517 modeidx = MCS_DEFAULT;
518
519 frmlen = ath_max_4ms_framelen[modeidx][rates[i].idx];
520 max_4ms_framelen = min(max_4ms_framelen, frmlen);
521 }
522 }
523
524 /*
525 * limit aggregate size by the minimum rate if rate selected is
526 * not a probe rate, if rate selected is a probe rate then
527 * avoid aggregation of this packet.
528 */
529 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
530 return 0;
531
532 if (sc->sc_flags & SC_OP_BT_PRIORITY_DETECTED)
533 aggr_limit = min((max_4ms_framelen * 3) / 8,
534 (u32)ATH_AMPDU_LIMIT_MAX);
535 else
536 aggr_limit = min(max_4ms_framelen,
537 (u32)ATH_AMPDU_LIMIT_MAX);
538
539 /*
540 * h/w can accept aggregates upto 16 bit lengths (65535).
541 * The IE, however can hold upto 65536, which shows up here
542 * as zero. Ignore 65536 since we are constrained by hw.
543 */
544 if (tid->an->maxampdu)
545 aggr_limit = min(aggr_limit, tid->an->maxampdu);
546
547 return aggr_limit;
548 }
549
550 /*
551 * Returns the number of delimiters to be added to
552 * meet the minimum required mpdudensity.
553 */
554 static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
555 struct ath_buf *bf, u16 frmlen)
556 {
557 struct sk_buff *skb = bf->bf_mpdu;
558 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
559 u32 nsymbits, nsymbols;
560 u16 minlen;
561 u8 flags, rix;
562 int width, half_gi, ndelim, mindelim;
563
564 /* Select standard number of delimiters based on frame length alone */
565 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
566
567 /*
568 * If encryption enabled, hardware requires some more padding between
569 * subframes.
570 * TODO - this could be improved to be dependent on the rate.
571 * The hardware can keep up at lower rates, but not higher rates
572 */
573 if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR)
574 ndelim += ATH_AGGR_ENCRYPTDELIM;
575
576 /*
577 * Convert desired mpdu density from microeconds to bytes based
578 * on highest rate in rate series (i.e. first rate) to determine
579 * required minimum length for subframe. Take into account
580 * whether high rate is 20 or 40Mhz and half or full GI.
581 *
582 * If there is no mpdu density restriction, no further calculation
583 * is needed.
584 */
585
586 if (tid->an->mpdudensity == 0)
587 return ndelim;
588
589 rix = tx_info->control.rates[0].idx;
590 flags = tx_info->control.rates[0].flags;
591 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
592 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
593
594 if (half_gi)
595 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity);
596 else
597 nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity);
598
599 if (nsymbols == 0)
600 nsymbols = 1;
601
602 nsymbits = bits_per_symbol[rix][width];
603 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
604
605 if (frmlen < minlen) {
606 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
607 ndelim = max(mindelim, ndelim);
608 }
609
610 return ndelim;
611 }
612
613 static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
614 struct ath_txq *txq,
615 struct ath_atx_tid *tid,
616 struct list_head *bf_q)
617 {
618 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
619 struct ath_buf *bf, *bf_first, *bf_prev = NULL;
620 int rl = 0, nframes = 0, ndelim, prev_al = 0;
621 u16 aggr_limit = 0, al = 0, bpad = 0,
622 al_delta, h_baw = tid->baw_size / 2;
623 enum ATH_AGGR_STATUS status = ATH_AGGR_DONE;
624
625 bf_first = list_first_entry(&tid->buf_q, struct ath_buf, list);
626
627 do {
628 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
629
630 /* do not step over block-ack window */
631 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno)) {
632 status = ATH_AGGR_BAW_CLOSED;
633 break;
634 }
635
636 if (!rl) {
637 aggr_limit = ath_lookup_rate(sc, bf, tid);
638 rl = 1;
639 }
640
641 /* do not exceed aggregation limit */
642 al_delta = ATH_AGGR_DELIM_SZ + bf->bf_frmlen;
643
644 if (nframes &&
645 (aggr_limit < (al + bpad + al_delta + prev_al))) {
646 status = ATH_AGGR_LIMITED;
647 break;
648 }
649
650 /* do not exceed subframe limit */
651 if (nframes >= min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) {
652 status = ATH_AGGR_LIMITED;
653 break;
654 }
655 nframes++;
656
657 /* add padding for previous frame to aggregation length */
658 al += bpad + al_delta;
659
660 /*
661 * Get the delimiters needed to meet the MPDU
662 * density for this node.
663 */
664 ndelim = ath_compute_num_delims(sc, tid, bf_first, bf->bf_frmlen);
665 bpad = PADBYTES(al_delta) + (ndelim << 2);
666
667 bf->bf_next = NULL;
668 bf->bf_desc->ds_link = 0;
669
670 /* link buffers of this frame to the aggregate */
671 ath_tx_addto_baw(sc, tid, bf);
672 ath9k_hw_set11n_aggr_middle(sc->sc_ah, bf->bf_desc, ndelim);
673 list_move_tail(&bf->list, bf_q);
674 if (bf_prev) {
675 bf_prev->bf_next = bf;
676 bf_prev->bf_desc->ds_link = bf->bf_daddr;
677 }
678 bf_prev = bf;
679
680 } while (!list_empty(&tid->buf_q));
681
682 bf_first->bf_al = al;
683 bf_first->bf_nframes = nframes;
684
685 return status;
686 #undef PADBYTES
687 }
688
689 static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
690 struct ath_atx_tid *tid)
691 {
692 struct ath_buf *bf;
693 enum ATH_AGGR_STATUS status;
694 struct list_head bf_q;
695
696 do {
697 if (list_empty(&tid->buf_q))
698 return;
699
700 INIT_LIST_HEAD(&bf_q);
701
702 status = ath_tx_form_aggr(sc, txq, tid, &bf_q);
703
704 /*
705 * no frames picked up to be aggregated;
706 * block-ack window is not open.
707 */
708 if (list_empty(&bf_q))
709 break;
710
711 bf = list_first_entry(&bf_q, struct ath_buf, list);
712 bf->bf_lastbf = list_entry(bf_q.prev, struct ath_buf, list);
713
714 /* if only one frame, send as non-aggregate */
715 if (bf->bf_nframes == 1) {
716 bf->bf_state.bf_type &= ~BUF_AGGR;
717 ath9k_hw_clr11n_aggr(sc->sc_ah, bf->bf_desc);
718 ath_buf_set_rate(sc, bf);
719 ath_tx_txqaddbuf(sc, txq, &bf_q);
720 continue;
721 }
722
723 /* setup first desc of aggregate */
724 bf->bf_state.bf_type |= BUF_AGGR;
725 ath_buf_set_rate(sc, bf);
726 ath9k_hw_set11n_aggr_first(sc->sc_ah, bf->bf_desc, bf->bf_al);
727
728 /* anchor last desc of aggregate */
729 ath9k_hw_set11n_aggr_last(sc->sc_ah, bf->bf_lastbf->bf_desc);
730
731 ath_tx_txqaddbuf(sc, txq, &bf_q);
732 TX_STAT_INC(txq->axq_qnum, a_aggr);
733
734 } while (txq->axq_depth < ATH_AGGR_MIN_QDEPTH &&
735 status != ATH_AGGR_BAW_CLOSED);
736 }
737
738 void ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
739 u16 tid, u16 *ssn)
740 {
741 struct ath_atx_tid *txtid;
742 struct ath_node *an;
743
744 an = (struct ath_node *)sta->drv_priv;
745 txtid = ATH_AN_2_TID(an, tid);
746 txtid->state |= AGGR_ADDBA_PROGRESS;
747 ath_tx_pause_tid(sc, txtid);
748 *ssn = txtid->seq_start;
749 }
750
751 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
752 {
753 struct ath_node *an = (struct ath_node *)sta->drv_priv;
754 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
755 struct ath_txq *txq = &sc->tx.txq[txtid->ac->qnum];
756 struct ath_tx_status ts;
757 struct ath_buf *bf;
758 struct list_head bf_head;
759
760 memset(&ts, 0, sizeof(ts));
761 INIT_LIST_HEAD(&bf_head);
762
763 if (txtid->state & AGGR_CLEANUP)
764 return;
765
766 if (!(txtid->state & AGGR_ADDBA_COMPLETE)) {
767 txtid->state &= ~AGGR_ADDBA_PROGRESS;
768 return;
769 }
770
771 ath_tx_pause_tid(sc, txtid);
772
773 /* drop all software retried frames and mark this TID */
774 spin_lock_bh(&txq->axq_lock);
775 while (!list_empty(&txtid->buf_q)) {
776 bf = list_first_entry(&txtid->buf_q, struct ath_buf, list);
777 if (!bf_isretried(bf)) {
778 /*
779 * NB: it's based on the assumption that
780 * software retried frame will always stay
781 * at the head of software queue.
782 */
783 break;
784 }
785 list_move_tail(&bf->list, &bf_head);
786 ath_tx_update_baw(sc, txtid, bf->bf_seqno);
787 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
788 }
789 spin_unlock_bh(&txq->axq_lock);
790
791 if (txtid->baw_head != txtid->baw_tail) {
792 txtid->state |= AGGR_CLEANUP;
793 } else {
794 txtid->state &= ~AGGR_ADDBA_COMPLETE;
795 ath_tx_flush_tid(sc, txtid);
796 }
797 }
798
799 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
800 {
801 struct ath_atx_tid *txtid;
802 struct ath_node *an;
803
804 an = (struct ath_node *)sta->drv_priv;
805
806 if (sc->sc_flags & SC_OP_TXAGGR) {
807 txtid = ATH_AN_2_TID(an, tid);
808 txtid->baw_size =
809 IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
810 txtid->state |= AGGR_ADDBA_COMPLETE;
811 txtid->state &= ~AGGR_ADDBA_PROGRESS;
812 ath_tx_resume_tid(sc, txtid);
813 }
814 }
815
816 bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno)
817 {
818 struct ath_atx_tid *txtid;
819
820 if (!(sc->sc_flags & SC_OP_TXAGGR))
821 return false;
822
823 txtid = ATH_AN_2_TID(an, tidno);
824
825 if (!(txtid->state & (AGGR_ADDBA_COMPLETE | AGGR_ADDBA_PROGRESS)))
826 return true;
827 return false;
828 }
829
830 /********************/
831 /* Queue Management */
832 /********************/
833
834 static void ath_txq_drain_pending_buffers(struct ath_softc *sc,
835 struct ath_txq *txq)
836 {
837 struct ath_atx_ac *ac, *ac_tmp;
838 struct ath_atx_tid *tid, *tid_tmp;
839
840 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
841 list_del(&ac->list);
842 ac->sched = false;
843 list_for_each_entry_safe(tid, tid_tmp, &ac->tid_q, list) {
844 list_del(&tid->list);
845 tid->sched = false;
846 ath_tid_drain(sc, txq, tid);
847 }
848 }
849 }
850
851 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
852 {
853 struct ath_hw *ah = sc->sc_ah;
854 struct ath_common *common = ath9k_hw_common(ah);
855 struct ath9k_tx_queue_info qi;
856 int qnum;
857
858 memset(&qi, 0, sizeof(qi));
859 qi.tqi_subtype = subtype;
860 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
861 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
862 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
863 qi.tqi_physCompBuf = 0;
864
865 /*
866 * Enable interrupts only for EOL and DESC conditions.
867 * We mark tx descriptors to receive a DESC interrupt
868 * when a tx queue gets deep; otherwise waiting for the
869 * EOL to reap descriptors. Note that this is done to
870 * reduce interrupt load and this only defers reaping
871 * descriptors, never transmitting frames. Aside from
872 * reducing interrupts this also permits more concurrency.
873 * The only potential downside is if the tx queue backs
874 * up in which case the top half of the kernel may backup
875 * due to a lack of tx descriptors.
876 *
877 * The UAPSD queue is an exception, since we take a desc-
878 * based intr on the EOSP frames.
879 */
880 if (qtype == ATH9K_TX_QUEUE_UAPSD)
881 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
882 else
883 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
884 TXQ_FLAG_TXDESCINT_ENABLE;
885 qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
886 if (qnum == -1) {
887 /*
888 * NB: don't print a message, this happens
889 * normally on parts with too few tx queues
890 */
891 return NULL;
892 }
893 if (qnum >= ARRAY_SIZE(sc->tx.txq)) {
894 ath_print(common, ATH_DBG_FATAL,
895 "qnum %u out of range, max %u!\n",
896 qnum, (unsigned int)ARRAY_SIZE(sc->tx.txq));
897 ath9k_hw_releasetxqueue(ah, qnum);
898 return NULL;
899 }
900 if (!ATH_TXQ_SETUP(sc, qnum)) {
901 struct ath_txq *txq = &sc->tx.txq[qnum];
902
903 txq->axq_qnum = qnum;
904 txq->axq_link = NULL;
905 INIT_LIST_HEAD(&txq->axq_q);
906 INIT_LIST_HEAD(&txq->axq_acq);
907 spin_lock_init(&txq->axq_lock);
908 txq->axq_depth = 0;
909 txq->axq_tx_inprogress = false;
910 sc->tx.txqsetup |= 1<<qnum;
911 }
912 return &sc->tx.txq[qnum];
913 }
914
915 int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype)
916 {
917 int qnum;
918
919 switch (qtype) {
920 case ATH9K_TX_QUEUE_DATA:
921 if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) {
922 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
923 "HAL AC %u out of range, max %zu!\n",
924 haltype, ARRAY_SIZE(sc->tx.hwq_map));
925 return -1;
926 }
927 qnum = sc->tx.hwq_map[haltype];
928 break;
929 case ATH9K_TX_QUEUE_BEACON:
930 qnum = sc->beacon.beaconq;
931 break;
932 case ATH9K_TX_QUEUE_CAB:
933 qnum = sc->beacon.cabq->axq_qnum;
934 break;
935 default:
936 qnum = -1;
937 }
938 return qnum;
939 }
940
941 struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb)
942 {
943 struct ath_txq *txq = NULL;
944 u16 skb_queue = skb_get_queue_mapping(skb);
945 int qnum;
946
947 qnum = ath_get_hal_qnum(skb_queue, sc);
948 txq = &sc->tx.txq[qnum];
949
950 spin_lock_bh(&txq->axq_lock);
951
952 if (txq->axq_depth >= (ATH_TXBUF - 20)) {
953 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_XMIT,
954 "TX queue: %d is full, depth: %d\n",
955 qnum, txq->axq_depth);
956 ath_mac80211_stop_queue(sc, skb_queue);
957 txq->stopped = 1;
958 spin_unlock_bh(&txq->axq_lock);
959 return NULL;
960 }
961
962 spin_unlock_bh(&txq->axq_lock);
963
964 return txq;
965 }
966
967 int ath_txq_update(struct ath_softc *sc, int qnum,
968 struct ath9k_tx_queue_info *qinfo)
969 {
970 struct ath_hw *ah = sc->sc_ah;
971 int error = 0;
972 struct ath9k_tx_queue_info qi;
973
974 if (qnum == sc->beacon.beaconq) {
975 /*
976 * XXX: for beacon queue, we just save the parameter.
977 * It will be picked up by ath_beaconq_config when
978 * it's necessary.
979 */
980 sc->beacon.beacon_qi = *qinfo;
981 return 0;
982 }
983
984 BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum);
985
986 ath9k_hw_get_txq_props(ah, qnum, &qi);
987 qi.tqi_aifs = qinfo->tqi_aifs;
988 qi.tqi_cwmin = qinfo->tqi_cwmin;
989 qi.tqi_cwmax = qinfo->tqi_cwmax;
990 qi.tqi_burstTime = qinfo->tqi_burstTime;
991 qi.tqi_readyTime = qinfo->tqi_readyTime;
992
993 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
994 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
995 "Unable to update hardware queue %u!\n", qnum);
996 error = -EIO;
997 } else {
998 ath9k_hw_resettxqueue(ah, qnum);
999 }
1000
1001 return error;
1002 }
1003
1004 int ath_cabq_update(struct ath_softc *sc)
1005 {
1006 struct ath9k_tx_queue_info qi;
1007 int qnum = sc->beacon.cabq->axq_qnum;
1008
1009 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
1010 /*
1011 * Ensure the readytime % is within the bounds.
1012 */
1013 if (sc->config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND)
1014 sc->config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND;
1015 else if (sc->config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND)
1016 sc->config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND;
1017
1018 qi.tqi_readyTime = (sc->beacon_interval *
1019 sc->config.cabqReadytime) / 100;
1020 ath_txq_update(sc, qnum, &qi);
1021
1022 return 0;
1023 }
1024
1025 /*
1026 * Drain a given TX queue (could be Beacon or Data)
1027 *
1028 * This assumes output has been stopped and
1029 * we do not need to block ath_tx_tasklet.
1030 */
1031 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
1032 {
1033 struct ath_buf *bf, *lastbf;
1034 struct list_head bf_head;
1035 struct ath_tx_status ts;
1036
1037 memset(&ts, 0, sizeof(ts));
1038 if (!retry_tx)
1039 ts.ts_flags = ATH9K_TX_SW_ABORTED;
1040
1041 INIT_LIST_HEAD(&bf_head);
1042
1043 for (;;) {
1044 spin_lock_bh(&txq->axq_lock);
1045
1046 if (list_empty(&txq->axq_q)) {
1047 txq->axq_link = NULL;
1048 spin_unlock_bh(&txq->axq_lock);
1049 break;
1050 }
1051
1052 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
1053
1054 if (bf->bf_stale) {
1055 list_del(&bf->list);
1056 spin_unlock_bh(&txq->axq_lock);
1057
1058 spin_lock_bh(&sc->tx.txbuflock);
1059 list_add_tail(&bf->list, &sc->tx.txbuf);
1060 spin_unlock_bh(&sc->tx.txbuflock);
1061 continue;
1062 }
1063
1064 lastbf = bf->bf_lastbf;
1065
1066 /* remove ath_buf's of the same mpdu from txq */
1067 list_cut_position(&bf_head, &txq->axq_q, &lastbf->list);
1068 txq->axq_depth--;
1069
1070 spin_unlock_bh(&txq->axq_lock);
1071
1072 if (bf_isampdu(bf))
1073 ath_tx_complete_aggr(sc, txq, bf, &bf_head, &ts, 0);
1074 else
1075 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
1076 }
1077
1078 spin_lock_bh(&txq->axq_lock);
1079 txq->axq_tx_inprogress = false;
1080 spin_unlock_bh(&txq->axq_lock);
1081
1082 /* flush any pending frames if aggregation is enabled */
1083 if (sc->sc_flags & SC_OP_TXAGGR) {
1084 if (!retry_tx) {
1085 spin_lock_bh(&txq->axq_lock);
1086 ath_txq_drain_pending_buffers(sc, txq);
1087 spin_unlock_bh(&txq->axq_lock);
1088 }
1089 }
1090 }
1091
1092 void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
1093 {
1094 struct ath_hw *ah = sc->sc_ah;
1095 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1096 struct ath_txq *txq;
1097 int i, npend = 0;
1098
1099 if (sc->sc_flags & SC_OP_INVALID)
1100 return;
1101
1102 /* Stop beacon queue */
1103 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
1104
1105 /* Stop data queues */
1106 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1107 if (ATH_TXQ_SETUP(sc, i)) {
1108 txq = &sc->tx.txq[i];
1109 ath9k_hw_stoptxdma(ah, txq->axq_qnum);
1110 npend += ath9k_hw_numtxpending(ah, txq->axq_qnum);
1111 }
1112 }
1113
1114 if (npend) {
1115 int r;
1116
1117 ath_print(common, ATH_DBG_FATAL,
1118 "Unable to stop TxDMA. Reset HAL!\n");
1119
1120 spin_lock_bh(&sc->sc_resetlock);
1121 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
1122 if (r)
1123 ath_print(common, ATH_DBG_FATAL,
1124 "Unable to reset hardware; reset status %d\n",
1125 r);
1126 spin_unlock_bh(&sc->sc_resetlock);
1127 }
1128
1129 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1130 if (ATH_TXQ_SETUP(sc, i))
1131 ath_draintxq(sc, &sc->tx.txq[i], retry_tx);
1132 }
1133 }
1134
1135 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
1136 {
1137 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1138 sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
1139 }
1140
1141 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1142 {
1143 struct ath_atx_ac *ac;
1144 struct ath_atx_tid *tid;
1145
1146 if (list_empty(&txq->axq_acq))
1147 return;
1148
1149 ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list);
1150 list_del(&ac->list);
1151 ac->sched = false;
1152
1153 do {
1154 if (list_empty(&ac->tid_q))
1155 return;
1156
1157 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid, list);
1158 list_del(&tid->list);
1159 tid->sched = false;
1160
1161 if (tid->paused)
1162 continue;
1163
1164 ath_tx_sched_aggr(sc, txq, tid);
1165
1166 /*
1167 * add tid to round-robin queue if more frames
1168 * are pending for the tid
1169 */
1170 if (!list_empty(&tid->buf_q))
1171 ath_tx_queue_tid(txq, tid);
1172
1173 break;
1174 } while (!list_empty(&ac->tid_q));
1175
1176 if (!list_empty(&ac->tid_q)) {
1177 if (!ac->sched) {
1178 ac->sched = true;
1179 list_add_tail(&ac->list, &txq->axq_acq);
1180 }
1181 }
1182 }
1183
1184 int ath_tx_setup(struct ath_softc *sc, int haltype)
1185 {
1186 struct ath_txq *txq;
1187
1188 if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) {
1189 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
1190 "HAL AC %u out of range, max %zu!\n",
1191 haltype, ARRAY_SIZE(sc->tx.hwq_map));
1192 return 0;
1193 }
1194 txq = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, haltype);
1195 if (txq != NULL) {
1196 sc->tx.hwq_map[haltype] = txq->axq_qnum;
1197 return 1;
1198 } else
1199 return 0;
1200 }
1201
1202 /***********/
1203 /* TX, DMA */
1204 /***********/
1205
1206 /*
1207 * Insert a chain of ath_buf (descriptors) on a txq and
1208 * assume the descriptors are already chained together by caller.
1209 */
1210 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1211 struct list_head *head)
1212 {
1213 struct ath_hw *ah = sc->sc_ah;
1214 struct ath_common *common = ath9k_hw_common(ah);
1215 struct ath_buf *bf;
1216
1217 /*
1218 * Insert the frame on the outbound list and
1219 * pass it on to the hardware.
1220 */
1221
1222 if (list_empty(head))
1223 return;
1224
1225 bf = list_first_entry(head, struct ath_buf, list);
1226
1227 list_splice_tail_init(head, &txq->axq_q);
1228 txq->axq_depth++;
1229
1230 ath_print(common, ATH_DBG_QUEUE,
1231 "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth);
1232
1233 if (txq->axq_link == NULL) {
1234 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1235 ath_print(common, ATH_DBG_XMIT,
1236 "TXDP[%u] = %llx (%p)\n",
1237 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
1238 } else {
1239 *txq->axq_link = bf->bf_daddr;
1240 ath_print(common, ATH_DBG_XMIT, "link[%u] (%p)=%llx (%p)\n",
1241 txq->axq_qnum, txq->axq_link,
1242 ito64(bf->bf_daddr), bf->bf_desc);
1243 }
1244 txq->axq_link = &(bf->bf_lastbf->bf_desc->ds_link);
1245 ath9k_hw_txstart(ah, txq->axq_qnum);
1246 }
1247
1248 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
1249 {
1250 struct ath_buf *bf = NULL;
1251
1252 spin_lock_bh(&sc->tx.txbuflock);
1253
1254 if (unlikely(list_empty(&sc->tx.txbuf))) {
1255 spin_unlock_bh(&sc->tx.txbuflock);
1256 return NULL;
1257 }
1258
1259 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
1260 list_del(&bf->list);
1261
1262 spin_unlock_bh(&sc->tx.txbuflock);
1263
1264 return bf;
1265 }
1266
1267 static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid,
1268 struct list_head *bf_head,
1269 struct ath_tx_control *txctl)
1270 {
1271 struct ath_buf *bf;
1272
1273 bf = list_first_entry(bf_head, struct ath_buf, list);
1274 bf->bf_state.bf_type |= BUF_AMPDU;
1275 TX_STAT_INC(txctl->txq->axq_qnum, a_queued);
1276
1277 /*
1278 * Do not queue to h/w when any of the following conditions is true:
1279 * - there are pending frames in software queue
1280 * - the TID is currently paused for ADDBA/BAR request
1281 * - seqno is not within block-ack window
1282 * - h/w queue depth exceeds low water mark
1283 */
1284 if (!list_empty(&tid->buf_q) || tid->paused ||
1285 !BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno) ||
1286 txctl->txq->axq_depth >= ATH_AGGR_MIN_QDEPTH) {
1287 /*
1288 * Add this frame to software queue for scheduling later
1289 * for aggregation.
1290 */
1291 list_move_tail(&bf->list, &tid->buf_q);
1292 ath_tx_queue_tid(txctl->txq, tid);
1293 return;
1294 }
1295
1296 /* Add sub-frame to BAW */
1297 ath_tx_addto_baw(sc, tid, bf);
1298
1299 /* Queue to h/w without aggregation */
1300 bf->bf_nframes = 1;
1301 bf->bf_lastbf = bf;
1302 ath_buf_set_rate(sc, bf);
1303 ath_tx_txqaddbuf(sc, txctl->txq, bf_head);
1304 }
1305
1306 static void ath_tx_send_ht_normal(struct ath_softc *sc, struct ath_txq *txq,
1307 struct ath_atx_tid *tid,
1308 struct list_head *bf_head)
1309 {
1310 struct ath_buf *bf;
1311
1312 bf = list_first_entry(bf_head, struct ath_buf, list);
1313 bf->bf_state.bf_type &= ~BUF_AMPDU;
1314
1315 /* update starting sequence number for subsequent ADDBA request */
1316 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
1317
1318 bf->bf_nframes = 1;
1319 bf->bf_lastbf = bf;
1320 ath_buf_set_rate(sc, bf);
1321 ath_tx_txqaddbuf(sc, txq, bf_head);
1322 TX_STAT_INC(txq->axq_qnum, queued);
1323 }
1324
1325 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
1326 struct list_head *bf_head)
1327 {
1328 struct ath_buf *bf;
1329
1330 bf = list_first_entry(bf_head, struct ath_buf, list);
1331
1332 bf->bf_lastbf = bf;
1333 bf->bf_nframes = 1;
1334 ath_buf_set_rate(sc, bf);
1335 ath_tx_txqaddbuf(sc, txq, bf_head);
1336 TX_STAT_INC(txq->axq_qnum, queued);
1337 }
1338
1339 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1340 {
1341 struct ieee80211_hdr *hdr;
1342 enum ath9k_pkt_type htype;
1343 __le16 fc;
1344
1345 hdr = (struct ieee80211_hdr *)skb->data;
1346 fc = hdr->frame_control;
1347
1348 if (ieee80211_is_beacon(fc))
1349 htype = ATH9K_PKT_TYPE_BEACON;
1350 else if (ieee80211_is_probe_resp(fc))
1351 htype = ATH9K_PKT_TYPE_PROBE_RESP;
1352 else if (ieee80211_is_atim(fc))
1353 htype = ATH9K_PKT_TYPE_ATIM;
1354 else if (ieee80211_is_pspoll(fc))
1355 htype = ATH9K_PKT_TYPE_PSPOLL;
1356 else
1357 htype = ATH9K_PKT_TYPE_NORMAL;
1358
1359 return htype;
1360 }
1361
1362 static int get_hw_crypto_keytype(struct sk_buff *skb)
1363 {
1364 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1365
1366 if (tx_info->control.hw_key) {
1367 if (tx_info->control.hw_key->alg == ALG_WEP)
1368 return ATH9K_KEY_TYPE_WEP;
1369 else if (tx_info->control.hw_key->alg == ALG_TKIP)
1370 return ATH9K_KEY_TYPE_TKIP;
1371 else if (tx_info->control.hw_key->alg == ALG_CCMP)
1372 return ATH9K_KEY_TYPE_AES;
1373 }
1374
1375 return ATH9K_KEY_TYPE_CLEAR;
1376 }
1377
1378 static void assign_aggr_tid_seqno(struct sk_buff *skb,
1379 struct ath_buf *bf)
1380 {
1381 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1382 struct ieee80211_hdr *hdr;
1383 struct ath_node *an;
1384 struct ath_atx_tid *tid;
1385 __le16 fc;
1386 u8 *qc;
1387
1388 if (!tx_info->control.sta)
1389 return;
1390
1391 an = (struct ath_node *)tx_info->control.sta->drv_priv;
1392 hdr = (struct ieee80211_hdr *)skb->data;
1393 fc = hdr->frame_control;
1394
1395 if (ieee80211_is_data_qos(fc)) {
1396 qc = ieee80211_get_qos_ctl(hdr);
1397 bf->bf_tidno = qc[0] & 0xf;
1398 }
1399
1400 /*
1401 * For HT capable stations, we save tidno for later use.
1402 * We also override seqno set by upper layer with the one
1403 * in tx aggregation state.
1404 */
1405 tid = ATH_AN_2_TID(an, bf->bf_tidno);
1406 hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT);
1407 bf->bf_seqno = tid->seq_next;
1408 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
1409 }
1410
1411 static int setup_tx_flags(struct ath_softc *sc, struct sk_buff *skb,
1412 struct ath_txq *txq)
1413 {
1414 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1415 int flags = 0;
1416
1417 flags |= ATH9K_TXDESC_CLRDMASK; /* needed for crypto errors */
1418 flags |= ATH9K_TXDESC_INTREQ;
1419
1420 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1421 flags |= ATH9K_TXDESC_NOACK;
1422
1423 return flags;
1424 }
1425
1426 /*
1427 * rix - rate index
1428 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
1429 * width - 0 for 20 MHz, 1 for 40 MHz
1430 * half_gi - to use 4us v/s 3.6 us for symbol time
1431 */
1432 static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, struct ath_buf *bf,
1433 int width, int half_gi, bool shortPreamble)
1434 {
1435 u32 nbits, nsymbits, duration, nsymbols;
1436 int streams, pktlen;
1437
1438 pktlen = bf_isaggr(bf) ? bf->bf_al : bf->bf_frmlen;
1439
1440 /* find number of symbols: PLCP + data */
1441 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
1442 nsymbits = bits_per_symbol[rix][width];
1443 nsymbols = (nbits + nsymbits - 1) / nsymbits;
1444
1445 if (!half_gi)
1446 duration = SYMBOL_TIME(nsymbols);
1447 else
1448 duration = SYMBOL_TIME_HALFGI(nsymbols);
1449
1450 /* addup duration for legacy/ht training and signal fields */
1451 streams = HT_RC_2_STREAMS(rix);
1452 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1453
1454 return duration;
1455 }
1456
1457 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
1458 {
1459 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1460 struct ath9k_11n_rate_series series[4];
1461 struct sk_buff *skb;
1462 struct ieee80211_tx_info *tx_info;
1463 struct ieee80211_tx_rate *rates;
1464 const struct ieee80211_rate *rate;
1465 struct ieee80211_hdr *hdr;
1466 int i, flags = 0;
1467 u8 rix = 0, ctsrate = 0;
1468 bool is_pspoll;
1469
1470 memset(series, 0, sizeof(struct ath9k_11n_rate_series) * 4);
1471
1472 skb = bf->bf_mpdu;
1473 tx_info = IEEE80211_SKB_CB(skb);
1474 rates = tx_info->control.rates;
1475 hdr = (struct ieee80211_hdr *)skb->data;
1476 is_pspoll = ieee80211_is_pspoll(hdr->frame_control);
1477
1478 /*
1479 * We check if Short Preamble is needed for the CTS rate by
1480 * checking the BSS's global flag.
1481 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
1482 */
1483 rate = ieee80211_get_rts_cts_rate(sc->hw, tx_info);
1484 ctsrate = rate->hw_value;
1485 if (sc->sc_flags & SC_OP_PREAMBLE_SHORT)
1486 ctsrate |= rate->hw_value_short;
1487
1488 for (i = 0; i < 4; i++) {
1489 bool is_40, is_sgi, is_sp;
1490 int phy;
1491
1492 if (!rates[i].count || (rates[i].idx < 0))
1493 continue;
1494
1495 rix = rates[i].idx;
1496 series[i].Tries = rates[i].count;
1497 series[i].ChSel = common->tx_chainmask;
1498
1499 if ((sc->config.ath_aggr_prot && bf_isaggr(bf)) ||
1500 (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS)) {
1501 series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1502 flags |= ATH9K_TXDESC_RTSENA;
1503 } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1504 series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1505 flags |= ATH9K_TXDESC_CTSENA;
1506 }
1507
1508 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
1509 series[i].RateFlags |= ATH9K_RATESERIES_2040;
1510 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
1511 series[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
1512
1513 is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI);
1514 is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
1515 is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
1516
1517 if (rates[i].flags & IEEE80211_TX_RC_MCS) {
1518 /* MCS rates */
1519 series[i].Rate = rix | 0x80;
1520 series[i].PktDuration = ath_pkt_duration(sc, rix, bf,
1521 is_40, is_sgi, is_sp);
1522 continue;
1523 }
1524
1525 /* legcay rates */
1526 if ((tx_info->band == IEEE80211_BAND_2GHZ) &&
1527 !(rate->flags & IEEE80211_RATE_ERP_G))
1528 phy = WLAN_RC_PHY_CCK;
1529 else
1530 phy = WLAN_RC_PHY_OFDM;
1531
1532 rate = &sc->sbands[tx_info->band].bitrates[rates[i].idx];
1533 series[i].Rate = rate->hw_value;
1534 if (rate->hw_value_short) {
1535 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
1536 series[i].Rate |= rate->hw_value_short;
1537 } else {
1538 is_sp = false;
1539 }
1540
1541 series[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah,
1542 phy, rate->bitrate * 100, bf->bf_frmlen, rix, is_sp);
1543 }
1544
1545 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1546 if (bf_isaggr(bf) && (bf->bf_al > sc->sc_ah->caps.rts_aggr_limit))
1547 flags &= ~ATH9K_TXDESC_RTSENA;
1548
1549 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
1550 if (flags & ATH9K_TXDESC_RTSENA)
1551 flags &= ~ATH9K_TXDESC_CTSENA;
1552
1553 /* set dur_update_en for l-sig computation except for PS-Poll frames */
1554 ath9k_hw_set11n_ratescenario(sc->sc_ah, bf->bf_desc,
1555 bf->bf_lastbf->bf_desc,
1556 !is_pspoll, ctsrate,
1557 0, series, 4, flags);
1558
1559 if (sc->config.ath_aggr_prot && flags)
1560 ath9k_hw_set11n_burstduration(sc->sc_ah, bf->bf_desc, 8192);
1561 }
1562
1563 static int ath_tx_setup_buffer(struct ieee80211_hw *hw, struct ath_buf *bf,
1564 struct sk_buff *skb,
1565 struct ath_tx_control *txctl)
1566 {
1567 struct ath_wiphy *aphy = hw->priv;
1568 struct ath_softc *sc = aphy->sc;
1569 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1570 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1571 int hdrlen;
1572 __le16 fc;
1573 int padpos, padsize;
1574
1575 tx_info->pad[0] = 0;
1576 switch (txctl->frame_type) {
1577 case ATH9K_IFT_NOT_INTERNAL:
1578 break;
1579 case ATH9K_IFT_PAUSE:
1580 tx_info->pad[0] |= ATH_TX_INFO_FRAME_TYPE_PAUSE;
1581 /* fall through */
1582 case ATH9K_IFT_UNPAUSE:
1583 tx_info->pad[0] |= ATH_TX_INFO_FRAME_TYPE_INTERNAL;
1584 break;
1585 }
1586 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1587 fc = hdr->frame_control;
1588
1589 ATH_TXBUF_RESET(bf);
1590
1591 bf->aphy = aphy;
1592 bf->bf_frmlen = skb->len + FCS_LEN;
1593 /* Remove the padding size from bf_frmlen, if any */
1594 padpos = ath9k_cmn_padpos(hdr->frame_control);
1595 padsize = padpos & 3;
1596 if (padsize && skb->len>padpos+padsize) {
1597 bf->bf_frmlen -= padsize;
1598 }
1599
1600 if (conf_is_ht(&hw->conf))
1601 bf->bf_state.bf_type |= BUF_HT;
1602
1603 bf->bf_flags = setup_tx_flags(sc, skb, txctl->txq);
1604
1605 bf->bf_keytype = get_hw_crypto_keytype(skb);
1606 if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR) {
1607 bf->bf_frmlen += tx_info->control.hw_key->icv_len;
1608 bf->bf_keyix = tx_info->control.hw_key->hw_key_idx;
1609 } else {
1610 bf->bf_keyix = ATH9K_TXKEYIX_INVALID;
1611 }
1612
1613 if (ieee80211_is_data_qos(fc) && bf_isht(bf) &&
1614 (sc->sc_flags & SC_OP_TXAGGR))
1615 assign_aggr_tid_seqno(skb, bf);
1616
1617 bf->bf_mpdu = skb;
1618
1619 bf->bf_dmacontext = dma_map_single(sc->dev, skb->data,
1620 skb->len, DMA_TO_DEVICE);
1621 if (unlikely(dma_mapping_error(sc->dev, bf->bf_dmacontext))) {
1622 bf->bf_mpdu = NULL;
1623 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
1624 "dma_mapping_error() on TX\n");
1625 return -ENOMEM;
1626 }
1627
1628 bf->bf_buf_addr = bf->bf_dmacontext;
1629
1630 /* tag if this is a nullfunc frame to enable PS when AP acks it */
1631 if (ieee80211_is_nullfunc(fc) && ieee80211_has_pm(fc)) {
1632 bf->bf_isnullfunc = true;
1633 sc->ps_flags &= ~PS_NULLFUNC_COMPLETED;
1634 } else
1635 bf->bf_isnullfunc = false;
1636
1637 return 0;
1638 }
1639
1640 /* FIXME: tx power */
1641 static void ath_tx_start_dma(struct ath_softc *sc, struct ath_buf *bf,
1642 struct ath_tx_control *txctl)
1643 {
1644 struct sk_buff *skb = bf->bf_mpdu;
1645 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1646 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1647 struct ath_node *an = NULL;
1648 struct list_head bf_head;
1649 struct ath_desc *ds;
1650 struct ath_atx_tid *tid;
1651 struct ath_hw *ah = sc->sc_ah;
1652 int frm_type;
1653 __le16 fc;
1654
1655 frm_type = get_hw_packet_type(skb);
1656 fc = hdr->frame_control;
1657
1658 INIT_LIST_HEAD(&bf_head);
1659 list_add_tail(&bf->list, &bf_head);
1660
1661 ds = bf->bf_desc;
1662 ds->ds_link = 0;
1663 ds->ds_data = bf->bf_buf_addr;
1664
1665 ath9k_hw_set11n_txdesc(ah, ds, bf->bf_frmlen, frm_type, MAX_RATE_POWER,
1666 bf->bf_keyix, bf->bf_keytype, bf->bf_flags);
1667
1668 ath9k_hw_filltxdesc(ah, ds,
1669 skb->len, /* segment length */
1670 true, /* first segment */
1671 true, /* last segment */
1672 ds); /* first descriptor */
1673
1674 spin_lock_bh(&txctl->txq->axq_lock);
1675
1676 if (bf_isht(bf) && (sc->sc_flags & SC_OP_TXAGGR) &&
1677 tx_info->control.sta) {
1678 an = (struct ath_node *)tx_info->control.sta->drv_priv;
1679 tid = ATH_AN_2_TID(an, bf->bf_tidno);
1680
1681 if (!ieee80211_is_data_qos(fc)) {
1682 ath_tx_send_normal(sc, txctl->txq, &bf_head);
1683 goto tx_done;
1684 }
1685
1686 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
1687 /*
1688 * Try aggregation if it's a unicast data frame
1689 * and the destination is HT capable.
1690 */
1691 ath_tx_send_ampdu(sc, tid, &bf_head, txctl);
1692 } else {
1693 /*
1694 * Send this frame as regular when ADDBA
1695 * exchange is neither complete nor pending.
1696 */
1697 ath_tx_send_ht_normal(sc, txctl->txq,
1698 tid, &bf_head);
1699 }
1700 } else {
1701 ath_tx_send_normal(sc, txctl->txq, &bf_head);
1702 }
1703
1704 tx_done:
1705 spin_unlock_bh(&txctl->txq->axq_lock);
1706 }
1707
1708 /* Upon failure caller should free skb */
1709 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
1710 struct ath_tx_control *txctl)
1711 {
1712 struct ath_wiphy *aphy = hw->priv;
1713 struct ath_softc *sc = aphy->sc;
1714 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1715 struct ath_buf *bf;
1716 int r;
1717
1718 bf = ath_tx_get_buffer(sc);
1719 if (!bf) {
1720 ath_print(common, ATH_DBG_XMIT, "TX buffers are full\n");
1721 return -1;
1722 }
1723
1724 r = ath_tx_setup_buffer(hw, bf, skb, txctl);
1725 if (unlikely(r)) {
1726 struct ath_txq *txq = txctl->txq;
1727
1728 ath_print(common, ATH_DBG_FATAL, "TX mem alloc failure\n");
1729
1730 /* upon ath_tx_processq() this TX queue will be resumed, we
1731 * guarantee this will happen by knowing beforehand that
1732 * we will at least have to run TX completionon one buffer
1733 * on the queue */
1734 spin_lock_bh(&txq->axq_lock);
1735 if (sc->tx.txq[txq->axq_qnum].axq_depth > 1) {
1736 ath_mac80211_stop_queue(sc, skb_get_queue_mapping(skb));
1737 txq->stopped = 1;
1738 }
1739 spin_unlock_bh(&txq->axq_lock);
1740
1741 spin_lock_bh(&sc->tx.txbuflock);
1742 list_add_tail(&bf->list, &sc->tx.txbuf);
1743 spin_unlock_bh(&sc->tx.txbuflock);
1744
1745 return r;
1746 }
1747
1748 ath_tx_start_dma(sc, bf, txctl);
1749
1750 return 0;
1751 }
1752
1753 void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb)
1754 {
1755 struct ath_wiphy *aphy = hw->priv;
1756 struct ath_softc *sc = aphy->sc;
1757 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1758 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1759 int padpos, padsize;
1760 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1761 struct ath_tx_control txctl;
1762
1763 memset(&txctl, 0, sizeof(struct ath_tx_control));
1764
1765 /*
1766 * As a temporary workaround, assign seq# here; this will likely need
1767 * to be cleaned up to work better with Beacon transmission and virtual
1768 * BSSes.
1769 */
1770 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1771 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
1772 sc->tx.seq_no += 0x10;
1773 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1774 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
1775 }
1776
1777 /* Add the padding after the header if this is not already done */
1778 padpos = ath9k_cmn_padpos(hdr->frame_control);
1779 padsize = padpos & 3;
1780 if (padsize && skb->len>padpos) {
1781 if (skb_headroom(skb) < padsize) {
1782 ath_print(common, ATH_DBG_XMIT,
1783 "TX CABQ padding failed\n");
1784 dev_kfree_skb_any(skb);
1785 return;
1786 }
1787 skb_push(skb, padsize);
1788 memmove(skb->data, skb->data + padsize, padpos);
1789 }
1790
1791 txctl.txq = sc->beacon.cabq;
1792
1793 ath_print(common, ATH_DBG_XMIT,
1794 "transmitting CABQ packet, skb: %p\n", skb);
1795
1796 if (ath_tx_start(hw, skb, &txctl) != 0) {
1797 ath_print(common, ATH_DBG_XMIT, "CABQ TX failed\n");
1798 goto exit;
1799 }
1800
1801 return;
1802 exit:
1803 dev_kfree_skb_any(skb);
1804 }
1805
1806 /*****************/
1807 /* TX Completion */
1808 /*****************/
1809
1810 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
1811 struct ath_wiphy *aphy, int tx_flags)
1812 {
1813 struct ieee80211_hw *hw = sc->hw;
1814 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1815 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1816 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
1817 int padpos, padsize;
1818
1819 ath_print(common, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb);
1820
1821 if (aphy)
1822 hw = aphy->hw;
1823
1824 if (tx_flags & ATH_TX_BAR)
1825 tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
1826
1827 if (!(tx_flags & (ATH_TX_ERROR | ATH_TX_XRETRY))) {
1828 /* Frame was ACKed */
1829 tx_info->flags |= IEEE80211_TX_STAT_ACK;
1830 }
1831
1832 padpos = ath9k_cmn_padpos(hdr->frame_control);
1833 padsize = padpos & 3;
1834 if (padsize && skb->len>padpos+padsize) {
1835 /*
1836 * Remove MAC header padding before giving the frame back to
1837 * mac80211.
1838 */
1839 memmove(skb->data + padsize, skb->data, padpos);
1840 skb_pull(skb, padsize);
1841 }
1842
1843 if (sc->ps_flags & PS_WAIT_FOR_TX_ACK) {
1844 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK;
1845 ath_print(common, ATH_DBG_PS,
1846 "Going back to sleep after having "
1847 "received TX status (0x%lx)\n",
1848 sc->ps_flags & (PS_WAIT_FOR_BEACON |
1849 PS_WAIT_FOR_CAB |
1850 PS_WAIT_FOR_PSPOLL_DATA |
1851 PS_WAIT_FOR_TX_ACK));
1852 }
1853
1854 if (unlikely(tx_info->pad[0] & ATH_TX_INFO_FRAME_TYPE_INTERNAL))
1855 ath9k_tx_status(hw, skb);
1856 else
1857 ieee80211_tx_status(hw, skb);
1858 }
1859
1860 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
1861 struct ath_txq *txq, struct list_head *bf_q,
1862 struct ath_tx_status *ts, int txok, int sendbar)
1863 {
1864 struct sk_buff *skb = bf->bf_mpdu;
1865 unsigned long flags;
1866 int tx_flags = 0;
1867
1868 if (sendbar)
1869 tx_flags = ATH_TX_BAR;
1870
1871 if (!txok) {
1872 tx_flags |= ATH_TX_ERROR;
1873
1874 if (bf_isxretried(bf))
1875 tx_flags |= ATH_TX_XRETRY;
1876 }
1877
1878 dma_unmap_single(sc->dev, bf->bf_dmacontext, skb->len, DMA_TO_DEVICE);
1879 ath_tx_complete(sc, skb, bf->aphy, tx_flags);
1880 ath_debug_stat_tx(sc, txq, bf, ts);
1881
1882 /*
1883 * Return the list of ath_buf of this mpdu to free queue
1884 */
1885 spin_lock_irqsave(&sc->tx.txbuflock, flags);
1886 list_splice_tail_init(bf_q, &sc->tx.txbuf);
1887 spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
1888 }
1889
1890 static int ath_tx_num_badfrms(struct ath_softc *sc, struct ath_buf *bf,
1891 struct ath_tx_status *ts, int txok)
1892 {
1893 u16 seq_st = 0;
1894 u32 ba[WME_BA_BMP_SIZE >> 5];
1895 int ba_index;
1896 int nbad = 0;
1897 int isaggr = 0;
1898
1899 if (ts->ts_flags == ATH9K_TX_SW_ABORTED)
1900 return 0;
1901
1902 isaggr = bf_isaggr(bf);
1903 if (isaggr) {
1904 seq_st = ts->ts_seqnum;
1905 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
1906 }
1907
1908 while (bf) {
1909 ba_index = ATH_BA_INDEX(seq_st, bf->bf_seqno);
1910 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
1911 nbad++;
1912
1913 bf = bf->bf_next;
1914 }
1915
1916 return nbad;
1917 }
1918
1919 static void ath_tx_rc_status(struct ath_buf *bf, struct ath_tx_status *ts,
1920 int nbad, int txok, bool update_rc)
1921 {
1922 struct sk_buff *skb = bf->bf_mpdu;
1923 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1924 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1925 struct ieee80211_hw *hw = bf->aphy->hw;
1926 u8 i, tx_rateindex;
1927
1928 if (txok)
1929 tx_info->status.ack_signal = ts->ts_rssi;
1930
1931 tx_rateindex = ts->ts_rateindex;
1932 WARN_ON(tx_rateindex >= hw->max_rates);
1933
1934 if (ts->ts_status & ATH9K_TXERR_FILT)
1935 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1936 if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && update_rc)
1937 tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
1938
1939 if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 &&
1940 (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0 && update_rc) {
1941 if (ieee80211_is_data(hdr->frame_control)) {
1942 if (ts->ts_flags &
1943 (ATH9K_TX_DATA_UNDERRUN | ATH9K_TX_DELIM_UNDERRUN))
1944 tx_info->pad[0] |= ATH_TX_INFO_UNDERRUN;
1945 if ((ts->ts_status & ATH9K_TXERR_XRETRY) ||
1946 (ts->ts_status & ATH9K_TXERR_FIFO))
1947 tx_info->pad[0] |= ATH_TX_INFO_XRETRY;
1948 tx_info->status.ampdu_len = bf->bf_nframes;
1949 tx_info->status.ampdu_ack_len = bf->bf_nframes - nbad;
1950 }
1951 }
1952
1953 for (i = tx_rateindex + 1; i < hw->max_rates; i++) {
1954 tx_info->status.rates[i].count = 0;
1955 tx_info->status.rates[i].idx = -1;
1956 }
1957
1958 tx_info->status.rates[tx_rateindex].count = bf->bf_retries + 1;
1959 }
1960
1961 static void ath_wake_mac80211_queue(struct ath_softc *sc, struct ath_txq *txq)
1962 {
1963 int qnum;
1964
1965 spin_lock_bh(&txq->axq_lock);
1966 if (txq->stopped &&
1967 sc->tx.txq[txq->axq_qnum].axq_depth <= (ATH_TXBUF - 20)) {
1968 qnum = ath_get_mac80211_qnum(txq->axq_qnum, sc);
1969 if (qnum != -1) {
1970 ath_mac80211_start_queue(sc, qnum);
1971 txq->stopped = 0;
1972 }
1973 }
1974 spin_unlock_bh(&txq->axq_lock);
1975 }
1976
1977 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
1978 {
1979 struct ath_hw *ah = sc->sc_ah;
1980 struct ath_common *common = ath9k_hw_common(ah);
1981 struct ath_buf *bf, *lastbf, *bf_held = NULL;
1982 struct list_head bf_head;
1983 struct ath_desc *ds;
1984 struct ath_tx_status ts;
1985 int txok;
1986 int status;
1987
1988 ath_print(common, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n",
1989 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
1990 txq->axq_link);
1991
1992 for (;;) {
1993 spin_lock_bh(&txq->axq_lock);
1994 if (list_empty(&txq->axq_q)) {
1995 txq->axq_link = NULL;
1996 spin_unlock_bh(&txq->axq_lock);
1997 break;
1998 }
1999 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
2000
2001 /*
2002 * There is a race condition that a BH gets scheduled
2003 * after sw writes TxE and before hw re-load the last
2004 * descriptor to get the newly chained one.
2005 * Software must keep the last DONE descriptor as a
2006 * holding descriptor - software does so by marking
2007 * it with the STALE flag.
2008 */
2009 bf_held = NULL;
2010 if (bf->bf_stale) {
2011 bf_held = bf;
2012 if (list_is_last(&bf_held->list, &txq->axq_q)) {
2013 spin_unlock_bh(&txq->axq_lock);
2014 break;
2015 } else {
2016 bf = list_entry(bf_held->list.next,
2017 struct ath_buf, list);
2018 }
2019 }
2020
2021 lastbf = bf->bf_lastbf;
2022 ds = lastbf->bf_desc;
2023
2024 memset(&ts, 0, sizeof(ts));
2025 status = ath9k_hw_txprocdesc(ah, ds, &ts);
2026 if (status == -EINPROGRESS) {
2027 spin_unlock_bh(&txq->axq_lock);
2028 break;
2029 }
2030
2031 /*
2032 * We now know the nullfunc frame has been ACKed so we
2033 * can disable RX.
2034 */
2035 if (bf->bf_isnullfunc &&
2036 (ts.ts_status & ATH9K_TX_ACKED)) {
2037 if ((sc->ps_flags & PS_ENABLED))
2038 ath9k_enable_ps(sc);
2039 else
2040 sc->ps_flags |= PS_NULLFUNC_COMPLETED;
2041 }
2042
2043 /*
2044 * Remove ath_buf's of the same transmit unit from txq,
2045 * however leave the last descriptor back as the holding
2046 * descriptor for hw.
2047 */
2048 lastbf->bf_stale = true;
2049 INIT_LIST_HEAD(&bf_head);
2050 if (!list_is_singular(&lastbf->list))
2051 list_cut_position(&bf_head,
2052 &txq->axq_q, lastbf->list.prev);
2053
2054 txq->axq_depth--;
2055 txok = !(ts.ts_status & ATH9K_TXERR_MASK);
2056 txq->axq_tx_inprogress = false;
2057 spin_unlock_bh(&txq->axq_lock);
2058
2059 if (bf_held) {
2060 spin_lock_bh(&sc->tx.txbuflock);
2061 list_move_tail(&bf_held->list, &sc->tx.txbuf);
2062 spin_unlock_bh(&sc->tx.txbuflock);
2063 }
2064
2065 if (!bf_isampdu(bf)) {
2066 /*
2067 * This frame is sent out as a single frame.
2068 * Use hardware retry status for this frame.
2069 */
2070 bf->bf_retries = ts.ts_longretry;
2071 if (ts.ts_status & ATH9K_TXERR_XRETRY)
2072 bf->bf_state.bf_type |= BUF_XRETRY;
2073 ath_tx_rc_status(bf, &ts, 0, txok, true);
2074 }
2075
2076 if (bf_isampdu(bf))
2077 ath_tx_complete_aggr(sc, txq, bf, &bf_head, &ts, txok);
2078 else
2079 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, txok, 0);
2080
2081 ath_wake_mac80211_queue(sc, txq);
2082
2083 spin_lock_bh(&txq->axq_lock);
2084 if (sc->sc_flags & SC_OP_TXAGGR)
2085 ath_txq_schedule(sc, txq);
2086 spin_unlock_bh(&txq->axq_lock);
2087 }
2088 }
2089
2090 static void ath_tx_complete_poll_work(struct work_struct *work)
2091 {
2092 struct ath_softc *sc = container_of(work, struct ath_softc,
2093 tx_complete_work.work);
2094 struct ath_txq *txq;
2095 int i;
2096 bool needreset = false;
2097
2098 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
2099 if (ATH_TXQ_SETUP(sc, i)) {
2100 txq = &sc->tx.txq[i];
2101 spin_lock_bh(&txq->axq_lock);
2102 if (txq->axq_depth) {
2103 if (txq->axq_tx_inprogress) {
2104 needreset = true;
2105 spin_unlock_bh(&txq->axq_lock);
2106 break;
2107 } else {
2108 txq->axq_tx_inprogress = true;
2109 }
2110 }
2111 spin_unlock_bh(&txq->axq_lock);
2112 }
2113
2114 if (needreset) {
2115 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_RESET,
2116 "tx hung, resetting the chip\n");
2117 ath9k_ps_wakeup(sc);
2118 ath_reset(sc, false);
2119 ath9k_ps_restore(sc);
2120 }
2121
2122 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
2123 msecs_to_jiffies(ATH_TX_COMPLETE_POLL_INT));
2124 }
2125
2126
2127
2128 void ath_tx_tasklet(struct ath_softc *sc)
2129 {
2130 int i;
2131 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1);
2132
2133 ath9k_hw_gettxintrtxqs(sc->sc_ah, &qcumask);
2134
2135 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2136 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2137 ath_tx_processq(sc, &sc->tx.txq[i]);
2138 }
2139 }
2140
2141 /*****************/
2142 /* Init, Cleanup */
2143 /*****************/
2144
2145 int ath_tx_init(struct ath_softc *sc, int nbufs)
2146 {
2147 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2148 int error = 0;
2149
2150 spin_lock_init(&sc->tx.txbuflock);
2151
2152 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2153 "tx", nbufs, 1);
2154 if (error != 0) {
2155 ath_print(common, ATH_DBG_FATAL,
2156 "Failed to allocate tx descriptors: %d\n", error);
2157 goto err;
2158 }
2159
2160 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2161 "beacon", ATH_BCBUF, 1);
2162 if (error != 0) {
2163 ath_print(common, ATH_DBG_FATAL,
2164 "Failed to allocate beacon descriptors: %d\n", error);
2165 goto err;
2166 }
2167
2168 INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work);
2169
2170 err:
2171 if (error != 0)
2172 ath_tx_cleanup(sc);
2173
2174 return error;
2175 }
2176
2177 void ath_tx_cleanup(struct ath_softc *sc)
2178 {
2179 if (sc->beacon.bdma.dd_desc_len != 0)
2180 ath_descdma_cleanup(sc, &sc->beacon.bdma, &sc->beacon.bbuf);
2181
2182 if (sc->tx.txdma.dd_desc_len != 0)
2183 ath_descdma_cleanup(sc, &sc->tx.txdma, &sc->tx.txbuf);
2184 }
2185
2186 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2187 {
2188 struct ath_atx_tid *tid;
2189 struct ath_atx_ac *ac;
2190 int tidno, acno;
2191
2192 for (tidno = 0, tid = &an->tid[tidno];
2193 tidno < WME_NUM_TID;
2194 tidno++, tid++) {
2195 tid->an = an;
2196 tid->tidno = tidno;
2197 tid->seq_start = tid->seq_next = 0;
2198 tid->baw_size = WME_MAX_BA;
2199 tid->baw_head = tid->baw_tail = 0;
2200 tid->sched = false;
2201 tid->paused = false;
2202 tid->state &= ~AGGR_CLEANUP;
2203 INIT_LIST_HEAD(&tid->buf_q);
2204 acno = TID_TO_WME_AC(tidno);
2205 tid->ac = &an->ac[acno];
2206 tid->state &= ~AGGR_ADDBA_COMPLETE;
2207 tid->state &= ~AGGR_ADDBA_PROGRESS;
2208 }
2209
2210 for (acno = 0, ac = &an->ac[acno];
2211 acno < WME_NUM_AC; acno++, ac++) {
2212 ac->sched = false;
2213 INIT_LIST_HEAD(&ac->tid_q);
2214
2215 switch (acno) {
2216 case WME_AC_BE:
2217 ac->qnum = ath_tx_get_qnum(sc,
2218 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BE);
2219 break;
2220 case WME_AC_BK:
2221 ac->qnum = ath_tx_get_qnum(sc,
2222 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BK);
2223 break;
2224 case WME_AC_VI:
2225 ac->qnum = ath_tx_get_qnum(sc,
2226 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VI);
2227 break;
2228 case WME_AC_VO:
2229 ac->qnum = ath_tx_get_qnum(sc,
2230 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VO);
2231 break;
2232 }
2233 }
2234 }
2235
2236 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2237 {
2238 int i;
2239 struct ath_atx_ac *ac, *ac_tmp;
2240 struct ath_atx_tid *tid, *tid_tmp;
2241 struct ath_txq *txq;
2242
2243 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2244 if (ATH_TXQ_SETUP(sc, i)) {
2245 txq = &sc->tx.txq[i];
2246
2247 spin_lock_bh(&txq->axq_lock);
2248
2249 list_for_each_entry_safe(ac,
2250 ac_tmp, &txq->axq_acq, list) {
2251 tid = list_first_entry(&ac->tid_q,
2252 struct ath_atx_tid, list);
2253 if (tid && tid->an != an)
2254 continue;
2255 list_del(&ac->list);
2256 ac->sched = false;
2257
2258 list_for_each_entry_safe(tid,
2259 tid_tmp, &ac->tid_q, list) {
2260 list_del(&tid->list);
2261 tid->sched = false;
2262 ath_tid_drain(sc, txq, tid);
2263 tid->state &= ~AGGR_ADDBA_COMPLETE;
2264 tid->state &= ~AGGR_CLEANUP;
2265 }
2266 }
2267
2268 spin_unlock_bh(&txq->axq_lock);
2269 }
2270 }
2271 }
Linux kernel - Deliverables
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