2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 #define BITS_PER_BYTE 8
20 #define OFDM_PLCP_BITS 22
21 #define HT_RC_2_MCS(_rc) ((_rc) & 0x0f)
22 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
28 #define HT_LTF(_ns) (4 * (_ns))
29 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
30 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
31 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
32 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
34 #define OFDM_SIFS_TIME 16
36 static u32 bits_per_symbol
[][2] = {
38 { 26, 54 }, /* 0: BPSK */
39 { 52, 108 }, /* 1: QPSK 1/2 */
40 { 78, 162 }, /* 2: QPSK 3/4 */
41 { 104, 216 }, /* 3: 16-QAM 1/2 */
42 { 156, 324 }, /* 4: 16-QAM 3/4 */
43 { 208, 432 }, /* 5: 64-QAM 2/3 */
44 { 234, 486 }, /* 6: 64-QAM 3/4 */
45 { 260, 540 }, /* 7: 64-QAM 5/6 */
46 { 52, 108 }, /* 8: BPSK */
47 { 104, 216 }, /* 9: QPSK 1/2 */
48 { 156, 324 }, /* 10: QPSK 3/4 */
49 { 208, 432 }, /* 11: 16-QAM 1/2 */
50 { 312, 648 }, /* 12: 16-QAM 3/4 */
51 { 416, 864 }, /* 13: 64-QAM 2/3 */
52 { 468, 972 }, /* 14: 64-QAM 3/4 */
53 { 520, 1080 }, /* 15: 64-QAM 5/6 */
56 #define IS_HT_RATE(_rate) ((_rate) & 0x80)
58 static void ath_tx_send_ht_normal(struct ath_softc
*sc
, struct ath_txq
*txq
,
59 struct ath_atx_tid
*tid
,
60 struct list_head
*bf_head
);
61 static void ath_tx_complete_buf(struct ath_softc
*sc
, struct ath_buf
*bf
,
63 struct list_head
*bf_q
,
64 int txok
, int sendbar
);
65 static void ath_tx_txqaddbuf(struct ath_softc
*sc
, struct ath_txq
*txq
,
66 struct list_head
*head
);
67 static void ath_buf_set_rate(struct ath_softc
*sc
, struct ath_buf
*bf
);
68 static int ath_tx_num_badfrms(struct ath_softc
*sc
, struct ath_buf
*bf
,
70 static void ath_tx_rc_status(struct ath_buf
*bf
, struct ath_desc
*ds
,
71 int nbad
, int txok
, bool update_rc
);
79 static int ath_max_4ms_framelen
[3][16] = {
81 3216, 6434, 9650, 12868, 19304, 25740, 28956, 32180,
82 6430, 12860, 19300, 25736, 38600, 51472, 57890, 64320,
85 6684, 13368, 20052, 26738, 40104, 53476, 60156, 66840,
86 13360, 26720, 40080, 53440, 80160, 106880, 120240, 133600,
89 /* TODO: Only MCS 7 and 15 updated, recalculate the rest */
90 6684, 13368, 20052, 26738, 40104, 53476, 60156, 74200,
91 13360, 26720, 40080, 53440, 80160, 106880, 120240, 148400,
96 /*********************/
97 /* Aggregation logic */
98 /*********************/
100 static void ath_tx_queue_tid(struct ath_txq
*txq
, struct ath_atx_tid
*tid
)
102 struct ath_atx_ac
*ac
= tid
->ac
;
111 list_add_tail(&tid
->list
, &ac
->tid_q
);
117 list_add_tail(&ac
->list
, &txq
->axq_acq
);
120 static void ath_tx_pause_tid(struct ath_softc
*sc
, struct ath_atx_tid
*tid
)
122 struct ath_txq
*txq
= &sc
->tx
.txq
[tid
->ac
->qnum
];
124 spin_lock_bh(&txq
->axq_lock
);
126 spin_unlock_bh(&txq
->axq_lock
);
129 static void ath_tx_resume_tid(struct ath_softc
*sc
, struct ath_atx_tid
*tid
)
131 struct ath_txq
*txq
= &sc
->tx
.txq
[tid
->ac
->qnum
];
133 BUG_ON(tid
->paused
<= 0);
134 spin_lock_bh(&txq
->axq_lock
);
141 if (list_empty(&tid
->buf_q
))
144 ath_tx_queue_tid(txq
, tid
);
145 ath_txq_schedule(sc
, txq
);
147 spin_unlock_bh(&txq
->axq_lock
);
150 static void ath_tx_flush_tid(struct ath_softc
*sc
, struct ath_atx_tid
*tid
)
152 struct ath_txq
*txq
= &sc
->tx
.txq
[tid
->ac
->qnum
];
154 struct list_head bf_head
;
155 INIT_LIST_HEAD(&bf_head
);
157 BUG_ON(tid
->paused
<= 0);
158 spin_lock_bh(&txq
->axq_lock
);
162 if (tid
->paused
> 0) {
163 spin_unlock_bh(&txq
->axq_lock
);
167 while (!list_empty(&tid
->buf_q
)) {
168 bf
= list_first_entry(&tid
->buf_q
, struct ath_buf
, list
);
169 BUG_ON(bf_isretried(bf
));
170 list_move_tail(&bf
->list
, &bf_head
);
171 ath_tx_send_ht_normal(sc
, txq
, tid
, &bf_head
);
174 spin_unlock_bh(&txq
->axq_lock
);
177 static void ath_tx_update_baw(struct ath_softc
*sc
, struct ath_atx_tid
*tid
,
182 index
= ATH_BA_INDEX(tid
->seq_start
, seqno
);
183 cindex
= (tid
->baw_head
+ index
) & (ATH_TID_MAX_BUFS
- 1);
185 tid
->tx_buf
[cindex
] = NULL
;
187 while (tid
->baw_head
!= tid
->baw_tail
&& !tid
->tx_buf
[tid
->baw_head
]) {
188 INCR(tid
->seq_start
, IEEE80211_SEQ_MAX
);
189 INCR(tid
->baw_head
, ATH_TID_MAX_BUFS
);
193 static void ath_tx_addto_baw(struct ath_softc
*sc
, struct ath_atx_tid
*tid
,
198 if (bf_isretried(bf
))
201 index
= ATH_BA_INDEX(tid
->seq_start
, bf
->bf_seqno
);
202 cindex
= (tid
->baw_head
+ index
) & (ATH_TID_MAX_BUFS
- 1);
204 BUG_ON(tid
->tx_buf
[cindex
] != NULL
);
205 tid
->tx_buf
[cindex
] = bf
;
207 if (index
>= ((tid
->baw_tail
- tid
->baw_head
) &
208 (ATH_TID_MAX_BUFS
- 1))) {
209 tid
->baw_tail
= cindex
;
210 INCR(tid
->baw_tail
, ATH_TID_MAX_BUFS
);
215 * TODO: For frame(s) that are in the retry state, we will reuse the
216 * sequence number(s) without setting the retry bit. The
217 * alternative is to give up on these and BAR the receiver's window
220 static void ath_tid_drain(struct ath_softc
*sc
, struct ath_txq
*txq
,
221 struct ath_atx_tid
*tid
)
225 struct list_head bf_head
;
226 INIT_LIST_HEAD(&bf_head
);
229 if (list_empty(&tid
->buf_q
))
232 bf
= list_first_entry(&tid
->buf_q
, struct ath_buf
, list
);
233 list_move_tail(&bf
->list
, &bf_head
);
235 if (bf_isretried(bf
))
236 ath_tx_update_baw(sc
, tid
, bf
->bf_seqno
);
238 spin_unlock(&txq
->axq_lock
);
239 ath_tx_complete_buf(sc
, bf
, txq
, &bf_head
, 0, 0);
240 spin_lock(&txq
->axq_lock
);
243 tid
->seq_next
= tid
->seq_start
;
244 tid
->baw_tail
= tid
->baw_head
;
247 static void ath_tx_set_retry(struct ath_softc
*sc
, struct ath_txq
*txq
,
251 struct ieee80211_hdr
*hdr
;
253 bf
->bf_state
.bf_type
|= BUF_RETRY
;
255 TX_STAT_INC(txq
->axq_qnum
, a_retries
);
258 hdr
= (struct ieee80211_hdr
*)skb
->data
;
259 hdr
->frame_control
|= cpu_to_le16(IEEE80211_FCTL_RETRY
);
262 static struct ath_buf
* ath_clone_txbuf(struct ath_softc
*sc
, struct ath_buf
*bf
)
266 spin_lock_bh(&sc
->tx
.txbuflock
);
267 if (WARN_ON(list_empty(&sc
->tx
.txbuf
))) {
268 spin_unlock_bh(&sc
->tx
.txbuflock
);
271 tbf
= list_first_entry(&sc
->tx
.txbuf
, struct ath_buf
, list
);
272 list_del(&tbf
->list
);
273 spin_unlock_bh(&sc
->tx
.txbuflock
);
275 ATH_TXBUF_RESET(tbf
);
277 tbf
->aphy
= bf
->aphy
;
278 tbf
->bf_mpdu
= bf
->bf_mpdu
;
279 tbf
->bf_buf_addr
= bf
->bf_buf_addr
;
280 *(tbf
->bf_desc
) = *(bf
->bf_desc
);
281 tbf
->bf_state
= bf
->bf_state
;
282 tbf
->bf_dmacontext
= bf
->bf_dmacontext
;
287 static void ath_tx_complete_aggr(struct ath_softc
*sc
, struct ath_txq
*txq
,
288 struct ath_buf
*bf
, struct list_head
*bf_q
,
291 struct ath_node
*an
= NULL
;
293 struct ieee80211_sta
*sta
;
294 struct ieee80211_hw
*hw
;
295 struct ieee80211_hdr
*hdr
;
296 struct ieee80211_tx_info
*tx_info
;
297 struct ath_atx_tid
*tid
= NULL
;
298 struct ath_buf
*bf_next
, *bf_last
= bf
->bf_lastbf
;
299 struct ath_desc
*ds
= bf_last
->bf_desc
;
300 struct list_head bf_head
, bf_pending
;
301 u16 seq_st
= 0, acked_cnt
= 0, txfail_cnt
= 0;
302 u32 ba
[WME_BA_BMP_SIZE
>> 5];
303 int isaggr
, txfail
, txpending
, sendbar
= 0, needreset
= 0, nbad
= 0;
304 bool rc_update
= true;
307 hdr
= (struct ieee80211_hdr
*)skb
->data
;
309 tx_info
= IEEE80211_SKB_CB(skb
);
314 /* XXX: use ieee80211_find_sta! */
315 sta
= ieee80211_find_sta_by_hw(hw
, hdr
->addr1
);
321 an
= (struct ath_node
*)sta
->drv_priv
;
322 tid
= ATH_AN_2_TID(an
, bf
->bf_tidno
);
324 isaggr
= bf_isaggr(bf
);
325 memset(ba
, 0, WME_BA_BMP_SIZE
>> 3);
327 if (isaggr
&& txok
) {
328 if (ATH_DS_TX_BA(ds
)) {
329 seq_st
= ATH_DS_BA_SEQ(ds
);
330 memcpy(ba
, ATH_DS_BA_BITMAP(ds
),
331 WME_BA_BMP_SIZE
>> 3);
334 * AR5416 can become deaf/mute when BA
335 * issue happens. Chip needs to be reset.
336 * But AP code may have sychronization issues
337 * when perform internal reset in this routine.
338 * Only enable reset in STA mode for now.
340 if (sc
->sc_ah
->opmode
== NL80211_IFTYPE_STATION
)
345 INIT_LIST_HEAD(&bf_pending
);
346 INIT_LIST_HEAD(&bf_head
);
348 nbad
= ath_tx_num_badfrms(sc
, bf
, txok
);
350 txfail
= txpending
= 0;
351 bf_next
= bf
->bf_next
;
353 if (ATH_BA_ISSET(ba
, ATH_BA_INDEX(seq_st
, bf
->bf_seqno
))) {
354 /* transmit completion, subframe is
355 * acked by block ack */
357 } else if (!isaggr
&& txok
) {
358 /* transmit completion */
361 if (!(tid
->state
& AGGR_CLEANUP
) &&
362 ds
->ds_txstat
.ts_flags
!= ATH9K_TX_SW_ABORTED
) {
363 if (bf
->bf_retries
< ATH_MAX_SW_RETRIES
) {
364 ath_tx_set_retry(sc
, txq
, bf
);
367 bf
->bf_state
.bf_type
|= BUF_XRETRY
;
374 * cleanup in progress, just fail
375 * the un-acked sub-frames
381 if (bf_next
== NULL
) {
383 * Make sure the last desc is reclaimed if it
384 * not a holding desc.
386 if (!bf_last
->bf_stale
)
387 list_move_tail(&bf
->list
, &bf_head
);
389 INIT_LIST_HEAD(&bf_head
);
391 BUG_ON(list_empty(bf_q
));
392 list_move_tail(&bf
->list
, &bf_head
);
397 * complete the acked-ones/xretried ones; update
400 spin_lock_bh(&txq
->axq_lock
);
401 ath_tx_update_baw(sc
, tid
, bf
->bf_seqno
);
402 spin_unlock_bh(&txq
->axq_lock
);
404 if (rc_update
&& (acked_cnt
== 1 || txfail_cnt
== 1)) {
405 ath_tx_rc_status(bf
, ds
, nbad
, txok
, true);
408 ath_tx_rc_status(bf
, ds
, nbad
, txok
, false);
411 ath_tx_complete_buf(sc
, bf
, txq
, &bf_head
, !txfail
, sendbar
);
413 /* retry the un-acked ones */
414 if (bf
->bf_next
== NULL
&& bf_last
->bf_stale
) {
417 tbf
= ath_clone_txbuf(sc
, bf_last
);
419 * Update tx baw and complete the frame with
420 * failed status if we run out of tx buf
423 spin_lock_bh(&txq
->axq_lock
);
424 ath_tx_update_baw(sc
, tid
,
426 spin_unlock_bh(&txq
->axq_lock
);
428 bf
->bf_state
.bf_type
|= BUF_XRETRY
;
429 ath_tx_rc_status(bf
, ds
, nbad
,
431 ath_tx_complete_buf(sc
, bf
, txq
,
436 ath9k_hw_cleartxdesc(sc
->sc_ah
, tbf
->bf_desc
);
437 list_add_tail(&tbf
->list
, &bf_head
);
440 * Clear descriptor status words for
443 ath9k_hw_cleartxdesc(sc
->sc_ah
, bf
->bf_desc
);
447 * Put this buffer to the temporary pending
448 * queue to retain ordering
450 list_splice_tail_init(&bf_head
, &bf_pending
);
456 if (tid
->state
& AGGR_CLEANUP
) {
457 if (tid
->baw_head
== tid
->baw_tail
) {
458 tid
->state
&= ~AGGR_ADDBA_COMPLETE
;
459 tid
->state
&= ~AGGR_CLEANUP
;
461 /* send buffered frames as singles */
462 ath_tx_flush_tid(sc
, tid
);
468 /* prepend un-acked frames to the beginning of the pending frame queue */
469 if (!list_empty(&bf_pending
)) {
470 spin_lock_bh(&txq
->axq_lock
);
471 list_splice(&bf_pending
, &tid
->buf_q
);
472 ath_tx_queue_tid(txq
, tid
);
473 spin_unlock_bh(&txq
->axq_lock
);
479 ath_reset(sc
, false);
482 static u32
ath_lookup_rate(struct ath_softc
*sc
, struct ath_buf
*bf
,
483 struct ath_atx_tid
*tid
)
486 struct ieee80211_tx_info
*tx_info
;
487 struct ieee80211_tx_rate
*rates
;
488 u32 max_4ms_framelen
, frmlen
;
489 u16 aggr_limit
, legacy
= 0;
493 tx_info
= IEEE80211_SKB_CB(skb
);
494 rates
= tx_info
->control
.rates
;
497 * Find the lowest frame length among the rate series that will have a
498 * 4ms transmit duration.
499 * TODO - TXOP limit needs to be considered.
501 max_4ms_framelen
= ATH_AMPDU_LIMIT_MAX
;
503 for (i
= 0; i
< 4; i
++) {
504 if (rates
[i
].count
) {
506 if (!(rates
[i
].flags
& IEEE80211_TX_RC_MCS
)) {
511 if (rates
[i
].flags
& IEEE80211_TX_RC_SHORT_GI
)
512 modeidx
= MCS_HT40_SGI
;
513 else if (rates
[i
].flags
& IEEE80211_TX_RC_40_MHZ_WIDTH
)
516 modeidx
= MCS_DEFAULT
;
518 frmlen
= ath_max_4ms_framelen
[modeidx
][rates
[i
].idx
];
519 max_4ms_framelen
= min(max_4ms_framelen
, frmlen
);
524 * limit aggregate size by the minimum rate if rate selected is
525 * not a probe rate, if rate selected is a probe rate then
526 * avoid aggregation of this packet.
528 if (tx_info
->flags
& IEEE80211_TX_CTL_RATE_CTRL_PROBE
|| legacy
)
531 if (sc
->sc_flags
& SC_OP_BT_PRIORITY_DETECTED
)
532 aggr_limit
= min((max_4ms_framelen
* 3) / 8,
533 (u32
)ATH_AMPDU_LIMIT_MAX
);
535 aggr_limit
= min(max_4ms_framelen
,
536 (u32
)ATH_AMPDU_LIMIT_MAX
);
539 * h/w can accept aggregates upto 16 bit lengths (65535).
540 * The IE, however can hold upto 65536, which shows up here
541 * as zero. Ignore 65536 since we are constrained by hw.
543 if (tid
->an
->maxampdu
)
544 aggr_limit
= min(aggr_limit
, tid
->an
->maxampdu
);
550 * Returns the number of delimiters to be added to
551 * meet the minimum required mpdudensity.
553 static int ath_compute_num_delims(struct ath_softc
*sc
, struct ath_atx_tid
*tid
,
554 struct ath_buf
*bf
, u16 frmlen
)
556 struct sk_buff
*skb
= bf
->bf_mpdu
;
557 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
558 u32 nsymbits
, nsymbols
;
561 int width
, half_gi
, ndelim
, mindelim
;
563 /* Select standard number of delimiters based on frame length alone */
564 ndelim
= ATH_AGGR_GET_NDELIM(frmlen
);
567 * If encryption enabled, hardware requires some more padding between
569 * TODO - this could be improved to be dependent on the rate.
570 * The hardware can keep up at lower rates, but not higher rates
572 if (bf
->bf_keytype
!= ATH9K_KEY_TYPE_CLEAR
)
573 ndelim
+= ATH_AGGR_ENCRYPTDELIM
;
576 * Convert desired mpdu density from microeconds to bytes based
577 * on highest rate in rate series (i.e. first rate) to determine
578 * required minimum length for subframe. Take into account
579 * whether high rate is 20 or 40Mhz and half or full GI.
581 * If there is no mpdu density restriction, no further calculation
585 if (tid
->an
->mpdudensity
== 0)
588 rix
= tx_info
->control
.rates
[0].idx
;
589 flags
= tx_info
->control
.rates
[0].flags
;
590 width
= (flags
& IEEE80211_TX_RC_40_MHZ_WIDTH
) ? 1 : 0;
591 half_gi
= (flags
& IEEE80211_TX_RC_SHORT_GI
) ? 1 : 0;
594 nsymbols
= NUM_SYMBOLS_PER_USEC_HALFGI(tid
->an
->mpdudensity
);
596 nsymbols
= NUM_SYMBOLS_PER_USEC(tid
->an
->mpdudensity
);
601 nsymbits
= bits_per_symbol
[rix
][width
];
602 minlen
= (nsymbols
* nsymbits
) / BITS_PER_BYTE
;
604 if (frmlen
< minlen
) {
605 mindelim
= (minlen
- frmlen
) / ATH_AGGR_DELIM_SZ
;
606 ndelim
= max(mindelim
, ndelim
);
612 static enum ATH_AGGR_STATUS
ath_tx_form_aggr(struct ath_softc
*sc
,
614 struct ath_atx_tid
*tid
,
615 struct list_head
*bf_q
)
617 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
618 struct ath_buf
*bf
, *bf_first
, *bf_prev
= NULL
;
619 int rl
= 0, nframes
= 0, ndelim
, prev_al
= 0;
620 u16 aggr_limit
= 0, al
= 0, bpad
= 0,
621 al_delta
, h_baw
= tid
->baw_size
/ 2;
622 enum ATH_AGGR_STATUS status
= ATH_AGGR_DONE
;
624 bf_first
= list_first_entry(&tid
->buf_q
, struct ath_buf
, list
);
627 bf
= list_first_entry(&tid
->buf_q
, struct ath_buf
, list
);
629 /* do not step over block-ack window */
630 if (!BAW_WITHIN(tid
->seq_start
, tid
->baw_size
, bf
->bf_seqno
)) {
631 status
= ATH_AGGR_BAW_CLOSED
;
636 aggr_limit
= ath_lookup_rate(sc
, bf
, tid
);
640 /* do not exceed aggregation limit */
641 al_delta
= ATH_AGGR_DELIM_SZ
+ bf
->bf_frmlen
;
644 (aggr_limit
< (al
+ bpad
+ al_delta
+ prev_al
))) {
645 status
= ATH_AGGR_LIMITED
;
649 /* do not exceed subframe limit */
650 if (nframes
>= min((int)h_baw
, ATH_AMPDU_SUBFRAME_DEFAULT
)) {
651 status
= ATH_AGGR_LIMITED
;
656 /* add padding for previous frame to aggregation length */
657 al
+= bpad
+ al_delta
;
660 * Get the delimiters needed to meet the MPDU
661 * density for this node.
663 ndelim
= ath_compute_num_delims(sc
, tid
, bf_first
, bf
->bf_frmlen
);
664 bpad
= PADBYTES(al_delta
) + (ndelim
<< 2);
667 bf
->bf_desc
->ds_link
= 0;
669 /* link buffers of this frame to the aggregate */
670 ath_tx_addto_baw(sc
, tid
, bf
);
671 ath9k_hw_set11n_aggr_middle(sc
->sc_ah
, bf
->bf_desc
, ndelim
);
672 list_move_tail(&bf
->list
, bf_q
);
674 bf_prev
->bf_next
= bf
;
675 bf_prev
->bf_desc
->ds_link
= bf
->bf_daddr
;
679 } while (!list_empty(&tid
->buf_q
));
681 bf_first
->bf_al
= al
;
682 bf_first
->bf_nframes
= nframes
;
688 static void ath_tx_sched_aggr(struct ath_softc
*sc
, struct ath_txq
*txq
,
689 struct ath_atx_tid
*tid
)
692 enum ATH_AGGR_STATUS status
;
693 struct list_head bf_q
;
696 if (list_empty(&tid
->buf_q
))
699 INIT_LIST_HEAD(&bf_q
);
701 status
= ath_tx_form_aggr(sc
, txq
, tid
, &bf_q
);
704 * no frames picked up to be aggregated;
705 * block-ack window is not open.
707 if (list_empty(&bf_q
))
710 bf
= list_first_entry(&bf_q
, struct ath_buf
, list
);
711 bf
->bf_lastbf
= list_entry(bf_q
.prev
, struct ath_buf
, list
);
713 /* if only one frame, send as non-aggregate */
714 if (bf
->bf_nframes
== 1) {
715 bf
->bf_state
.bf_type
&= ~BUF_AGGR
;
716 ath9k_hw_clr11n_aggr(sc
->sc_ah
, bf
->bf_desc
);
717 ath_buf_set_rate(sc
, bf
);
718 ath_tx_txqaddbuf(sc
, txq
, &bf_q
);
722 /* setup first desc of aggregate */
723 bf
->bf_state
.bf_type
|= BUF_AGGR
;
724 ath_buf_set_rate(sc
, bf
);
725 ath9k_hw_set11n_aggr_first(sc
->sc_ah
, bf
->bf_desc
, bf
->bf_al
);
727 /* anchor last desc of aggregate */
728 ath9k_hw_set11n_aggr_last(sc
->sc_ah
, bf
->bf_lastbf
->bf_desc
);
730 ath_tx_txqaddbuf(sc
, txq
, &bf_q
);
731 TX_STAT_INC(txq
->axq_qnum
, a_aggr
);
733 } while (txq
->axq_depth
< ATH_AGGR_MIN_QDEPTH
&&
734 status
!= ATH_AGGR_BAW_CLOSED
);
737 void ath_tx_aggr_start(struct ath_softc
*sc
, struct ieee80211_sta
*sta
,
740 struct ath_atx_tid
*txtid
;
743 an
= (struct ath_node
*)sta
->drv_priv
;
744 txtid
= ATH_AN_2_TID(an
, tid
);
745 txtid
->state
|= AGGR_ADDBA_PROGRESS
;
746 ath_tx_pause_tid(sc
, txtid
);
747 *ssn
= txtid
->seq_start
;
750 void ath_tx_aggr_stop(struct ath_softc
*sc
, struct ieee80211_sta
*sta
, u16 tid
)
752 struct ath_node
*an
= (struct ath_node
*)sta
->drv_priv
;
753 struct ath_atx_tid
*txtid
= ATH_AN_2_TID(an
, tid
);
754 struct ath_txq
*txq
= &sc
->tx
.txq
[txtid
->ac
->qnum
];
756 struct list_head bf_head
;
757 INIT_LIST_HEAD(&bf_head
);
759 if (txtid
->state
& AGGR_CLEANUP
)
762 if (!(txtid
->state
& AGGR_ADDBA_COMPLETE
)) {
763 txtid
->state
&= ~AGGR_ADDBA_PROGRESS
;
767 ath_tx_pause_tid(sc
, txtid
);
769 /* drop all software retried frames and mark this TID */
770 spin_lock_bh(&txq
->axq_lock
);
771 while (!list_empty(&txtid
->buf_q
)) {
772 bf
= list_first_entry(&txtid
->buf_q
, struct ath_buf
, list
);
773 if (!bf_isretried(bf
)) {
775 * NB: it's based on the assumption that
776 * software retried frame will always stay
777 * at the head of software queue.
781 list_move_tail(&bf
->list
, &bf_head
);
782 ath_tx_update_baw(sc
, txtid
, bf
->bf_seqno
);
783 ath_tx_complete_buf(sc
, bf
, txq
, &bf_head
, 0, 0);
785 spin_unlock_bh(&txq
->axq_lock
);
787 if (txtid
->baw_head
!= txtid
->baw_tail
) {
788 txtid
->state
|= AGGR_CLEANUP
;
790 txtid
->state
&= ~AGGR_ADDBA_COMPLETE
;
791 ath_tx_flush_tid(sc
, txtid
);
795 void ath_tx_aggr_resume(struct ath_softc
*sc
, struct ieee80211_sta
*sta
, u16 tid
)
797 struct ath_atx_tid
*txtid
;
800 an
= (struct ath_node
*)sta
->drv_priv
;
802 if (sc
->sc_flags
& SC_OP_TXAGGR
) {
803 txtid
= ATH_AN_2_TID(an
, tid
);
805 IEEE80211_MIN_AMPDU_BUF
<< sta
->ht_cap
.ampdu_factor
;
806 txtid
->state
|= AGGR_ADDBA_COMPLETE
;
807 txtid
->state
&= ~AGGR_ADDBA_PROGRESS
;
808 ath_tx_resume_tid(sc
, txtid
);
812 bool ath_tx_aggr_check(struct ath_softc
*sc
, struct ath_node
*an
, u8 tidno
)
814 struct ath_atx_tid
*txtid
;
816 if (!(sc
->sc_flags
& SC_OP_TXAGGR
))
819 txtid
= ATH_AN_2_TID(an
, tidno
);
821 if (!(txtid
->state
& (AGGR_ADDBA_COMPLETE
| AGGR_ADDBA_PROGRESS
)))
826 /********************/
827 /* Queue Management */
828 /********************/
830 static void ath_txq_drain_pending_buffers(struct ath_softc
*sc
,
833 struct ath_atx_ac
*ac
, *ac_tmp
;
834 struct ath_atx_tid
*tid
, *tid_tmp
;
836 list_for_each_entry_safe(ac
, ac_tmp
, &txq
->axq_acq
, list
) {
839 list_for_each_entry_safe(tid
, tid_tmp
, &ac
->tid_q
, list
) {
840 list_del(&tid
->list
);
842 ath_tid_drain(sc
, txq
, tid
);
847 struct ath_txq
*ath_txq_setup(struct ath_softc
*sc
, int qtype
, int subtype
)
849 struct ath_hw
*ah
= sc
->sc_ah
;
850 struct ath_common
*common
= ath9k_hw_common(ah
);
851 struct ath9k_tx_queue_info qi
;
854 memset(&qi
, 0, sizeof(qi
));
855 qi
.tqi_subtype
= subtype
;
856 qi
.tqi_aifs
= ATH9K_TXQ_USEDEFAULT
;
857 qi
.tqi_cwmin
= ATH9K_TXQ_USEDEFAULT
;
858 qi
.tqi_cwmax
= ATH9K_TXQ_USEDEFAULT
;
859 qi
.tqi_physCompBuf
= 0;
862 * Enable interrupts only for EOL and DESC conditions.
863 * We mark tx descriptors to receive a DESC interrupt
864 * when a tx queue gets deep; otherwise waiting for the
865 * EOL to reap descriptors. Note that this is done to
866 * reduce interrupt load and this only defers reaping
867 * descriptors, never transmitting frames. Aside from
868 * reducing interrupts this also permits more concurrency.
869 * The only potential downside is if the tx queue backs
870 * up in which case the top half of the kernel may backup
871 * due to a lack of tx descriptors.
873 * The UAPSD queue is an exception, since we take a desc-
874 * based intr on the EOSP frames.
876 if (qtype
== ATH9K_TX_QUEUE_UAPSD
)
877 qi
.tqi_qflags
= TXQ_FLAG_TXDESCINT_ENABLE
;
879 qi
.tqi_qflags
= TXQ_FLAG_TXEOLINT_ENABLE
|
880 TXQ_FLAG_TXDESCINT_ENABLE
;
881 qnum
= ath9k_hw_setuptxqueue(ah
, qtype
, &qi
);
884 * NB: don't print a message, this happens
885 * normally on parts with too few tx queues
889 if (qnum
>= ARRAY_SIZE(sc
->tx
.txq
)) {
890 ath_print(common
, ATH_DBG_FATAL
,
891 "qnum %u out of range, max %u!\n",
892 qnum
, (unsigned int)ARRAY_SIZE(sc
->tx
.txq
));
893 ath9k_hw_releasetxqueue(ah
, qnum
);
896 if (!ATH_TXQ_SETUP(sc
, qnum
)) {
897 struct ath_txq
*txq
= &sc
->tx
.txq
[qnum
];
899 txq
->axq_qnum
= qnum
;
900 txq
->axq_link
= NULL
;
901 INIT_LIST_HEAD(&txq
->axq_q
);
902 INIT_LIST_HEAD(&txq
->axq_acq
);
903 spin_lock_init(&txq
->axq_lock
);
905 txq
->axq_tx_inprogress
= false;
906 sc
->tx
.txqsetup
|= 1<<qnum
;
908 return &sc
->tx
.txq
[qnum
];
911 int ath_tx_get_qnum(struct ath_softc
*sc
, int qtype
, int haltype
)
916 case ATH9K_TX_QUEUE_DATA
:
917 if (haltype
>= ARRAY_SIZE(sc
->tx
.hwq_map
)) {
918 ath_print(ath9k_hw_common(sc
->sc_ah
), ATH_DBG_FATAL
,
919 "HAL AC %u out of range, max %zu!\n",
920 haltype
, ARRAY_SIZE(sc
->tx
.hwq_map
));
923 qnum
= sc
->tx
.hwq_map
[haltype
];
925 case ATH9K_TX_QUEUE_BEACON
:
926 qnum
= sc
->beacon
.beaconq
;
928 case ATH9K_TX_QUEUE_CAB
:
929 qnum
= sc
->beacon
.cabq
->axq_qnum
;
937 struct ath_txq
*ath_test_get_txq(struct ath_softc
*sc
, struct sk_buff
*skb
)
939 struct ath_txq
*txq
= NULL
;
940 u16 skb_queue
= skb_get_queue_mapping(skb
);
943 qnum
= ath_get_hal_qnum(skb_queue
, sc
);
944 txq
= &sc
->tx
.txq
[qnum
];
946 spin_lock_bh(&txq
->axq_lock
);
948 if (txq
->axq_depth
>= (ATH_TXBUF
- 20)) {
949 ath_print(ath9k_hw_common(sc
->sc_ah
), ATH_DBG_XMIT
,
950 "TX queue: %d is full, depth: %d\n",
951 qnum
, txq
->axq_depth
);
952 ath_mac80211_stop_queue(sc
, skb_queue
);
954 spin_unlock_bh(&txq
->axq_lock
);
958 spin_unlock_bh(&txq
->axq_lock
);
963 int ath_txq_update(struct ath_softc
*sc
, int qnum
,
964 struct ath9k_tx_queue_info
*qinfo
)
966 struct ath_hw
*ah
= sc
->sc_ah
;
968 struct ath9k_tx_queue_info qi
;
970 if (qnum
== sc
->beacon
.beaconq
) {
972 * XXX: for beacon queue, we just save the parameter.
973 * It will be picked up by ath_beaconq_config when
976 sc
->beacon
.beacon_qi
= *qinfo
;
980 BUG_ON(sc
->tx
.txq
[qnum
].axq_qnum
!= qnum
);
982 ath9k_hw_get_txq_props(ah
, qnum
, &qi
);
983 qi
.tqi_aifs
= qinfo
->tqi_aifs
;
984 qi
.tqi_cwmin
= qinfo
->tqi_cwmin
;
985 qi
.tqi_cwmax
= qinfo
->tqi_cwmax
;
986 qi
.tqi_burstTime
= qinfo
->tqi_burstTime
;
987 qi
.tqi_readyTime
= qinfo
->tqi_readyTime
;
989 if (!ath9k_hw_set_txq_props(ah
, qnum
, &qi
)) {
990 ath_print(ath9k_hw_common(sc
->sc_ah
), ATH_DBG_FATAL
,
991 "Unable to update hardware queue %u!\n", qnum
);
994 ath9k_hw_resettxqueue(ah
, qnum
);
1000 int ath_cabq_update(struct ath_softc
*sc
)
1002 struct ath9k_tx_queue_info qi
;
1003 int qnum
= sc
->beacon
.cabq
->axq_qnum
;
1005 ath9k_hw_get_txq_props(sc
->sc_ah
, qnum
, &qi
);
1007 * Ensure the readytime % is within the bounds.
1009 if (sc
->config
.cabqReadytime
< ATH9K_READY_TIME_LO_BOUND
)
1010 sc
->config
.cabqReadytime
= ATH9K_READY_TIME_LO_BOUND
;
1011 else if (sc
->config
.cabqReadytime
> ATH9K_READY_TIME_HI_BOUND
)
1012 sc
->config
.cabqReadytime
= ATH9K_READY_TIME_HI_BOUND
;
1014 qi
.tqi_readyTime
= (sc
->beacon_interval
*
1015 sc
->config
.cabqReadytime
) / 100;
1016 ath_txq_update(sc
, qnum
, &qi
);
1022 * Drain a given TX queue (could be Beacon or Data)
1024 * This assumes output has been stopped and
1025 * we do not need to block ath_tx_tasklet.
1027 void ath_draintxq(struct ath_softc
*sc
, struct ath_txq
*txq
, bool retry_tx
)
1029 struct ath_buf
*bf
, *lastbf
;
1030 struct list_head bf_head
;
1032 INIT_LIST_HEAD(&bf_head
);
1035 spin_lock_bh(&txq
->axq_lock
);
1037 if (list_empty(&txq
->axq_q
)) {
1038 txq
->axq_link
= NULL
;
1039 spin_unlock_bh(&txq
->axq_lock
);
1043 bf
= list_first_entry(&txq
->axq_q
, struct ath_buf
, list
);
1046 list_del(&bf
->list
);
1047 spin_unlock_bh(&txq
->axq_lock
);
1049 spin_lock_bh(&sc
->tx
.txbuflock
);
1050 list_add_tail(&bf
->list
, &sc
->tx
.txbuf
);
1051 spin_unlock_bh(&sc
->tx
.txbuflock
);
1055 lastbf
= bf
->bf_lastbf
;
1057 lastbf
->bf_desc
->ds_txstat
.ts_flags
=
1058 ATH9K_TX_SW_ABORTED
;
1060 /* remove ath_buf's of the same mpdu from txq */
1061 list_cut_position(&bf_head
, &txq
->axq_q
, &lastbf
->list
);
1064 spin_unlock_bh(&txq
->axq_lock
);
1067 ath_tx_complete_aggr(sc
, txq
, bf
, &bf_head
, 0);
1069 ath_tx_complete_buf(sc
, bf
, txq
, &bf_head
, 0, 0);
1072 spin_lock_bh(&txq
->axq_lock
);
1073 txq
->axq_tx_inprogress
= false;
1074 spin_unlock_bh(&txq
->axq_lock
);
1076 /* flush any pending frames if aggregation is enabled */
1077 if (sc
->sc_flags
& SC_OP_TXAGGR
) {
1079 spin_lock_bh(&txq
->axq_lock
);
1080 ath_txq_drain_pending_buffers(sc
, txq
);
1081 spin_unlock_bh(&txq
->axq_lock
);
1086 void ath_drain_all_txq(struct ath_softc
*sc
, bool retry_tx
)
1088 struct ath_hw
*ah
= sc
->sc_ah
;
1089 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
1090 struct ath_txq
*txq
;
1093 if (sc
->sc_flags
& SC_OP_INVALID
)
1096 /* Stop beacon queue */
1097 ath9k_hw_stoptxdma(sc
->sc_ah
, sc
->beacon
.beaconq
);
1099 /* Stop data queues */
1100 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++) {
1101 if (ATH_TXQ_SETUP(sc
, i
)) {
1102 txq
= &sc
->tx
.txq
[i
];
1103 ath9k_hw_stoptxdma(ah
, txq
->axq_qnum
);
1104 npend
+= ath9k_hw_numtxpending(ah
, txq
->axq_qnum
);
1111 ath_print(common
, ATH_DBG_XMIT
,
1112 "Unable to stop TxDMA. Reset HAL!\n");
1114 spin_lock_bh(&sc
->sc_resetlock
);
1115 r
= ath9k_hw_reset(ah
, sc
->sc_ah
->curchan
, true);
1117 ath_print(common
, ATH_DBG_FATAL
,
1118 "Unable to reset hardware; reset status %d\n",
1120 spin_unlock_bh(&sc
->sc_resetlock
);
1123 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++) {
1124 if (ATH_TXQ_SETUP(sc
, i
))
1125 ath_draintxq(sc
, &sc
->tx
.txq
[i
], retry_tx
);
1129 void ath_tx_cleanupq(struct ath_softc
*sc
, struct ath_txq
*txq
)
1131 ath9k_hw_releasetxqueue(sc
->sc_ah
, txq
->axq_qnum
);
1132 sc
->tx
.txqsetup
&= ~(1<<txq
->axq_qnum
);
1135 void ath_txq_schedule(struct ath_softc
*sc
, struct ath_txq
*txq
)
1137 struct ath_atx_ac
*ac
;
1138 struct ath_atx_tid
*tid
;
1140 if (list_empty(&txq
->axq_acq
))
1143 ac
= list_first_entry(&txq
->axq_acq
, struct ath_atx_ac
, list
);
1144 list_del(&ac
->list
);
1148 if (list_empty(&ac
->tid_q
))
1151 tid
= list_first_entry(&ac
->tid_q
, struct ath_atx_tid
, list
);
1152 list_del(&tid
->list
);
1158 ath_tx_sched_aggr(sc
, txq
, tid
);
1161 * add tid to round-robin queue if more frames
1162 * are pending for the tid
1164 if (!list_empty(&tid
->buf_q
))
1165 ath_tx_queue_tid(txq
, tid
);
1168 } while (!list_empty(&ac
->tid_q
));
1170 if (!list_empty(&ac
->tid_q
)) {
1173 list_add_tail(&ac
->list
, &txq
->axq_acq
);
1178 int ath_tx_setup(struct ath_softc
*sc
, int haltype
)
1180 struct ath_txq
*txq
;
1182 if (haltype
>= ARRAY_SIZE(sc
->tx
.hwq_map
)) {
1183 ath_print(ath9k_hw_common(sc
->sc_ah
), ATH_DBG_FATAL
,
1184 "HAL AC %u out of range, max %zu!\n",
1185 haltype
, ARRAY_SIZE(sc
->tx
.hwq_map
));
1188 txq
= ath_txq_setup(sc
, ATH9K_TX_QUEUE_DATA
, haltype
);
1190 sc
->tx
.hwq_map
[haltype
] = txq
->axq_qnum
;
1201 * Insert a chain of ath_buf (descriptors) on a txq and
1202 * assume the descriptors are already chained together by caller.
1204 static void ath_tx_txqaddbuf(struct ath_softc
*sc
, struct ath_txq
*txq
,
1205 struct list_head
*head
)
1207 struct ath_hw
*ah
= sc
->sc_ah
;
1208 struct ath_common
*common
= ath9k_hw_common(ah
);
1212 * Insert the frame on the outbound list and
1213 * pass it on to the hardware.
1216 if (list_empty(head
))
1219 bf
= list_first_entry(head
, struct ath_buf
, list
);
1221 list_splice_tail_init(head
, &txq
->axq_q
);
1224 ath_print(common
, ATH_DBG_QUEUE
,
1225 "qnum: %d, txq depth: %d\n", txq
->axq_qnum
, txq
->axq_depth
);
1227 if (txq
->axq_link
== NULL
) {
1228 ath9k_hw_puttxbuf(ah
, txq
->axq_qnum
, bf
->bf_daddr
);
1229 ath_print(common
, ATH_DBG_XMIT
,
1230 "TXDP[%u] = %llx (%p)\n",
1231 txq
->axq_qnum
, ito64(bf
->bf_daddr
), bf
->bf_desc
);
1233 *txq
->axq_link
= bf
->bf_daddr
;
1234 ath_print(common
, ATH_DBG_XMIT
, "link[%u] (%p)=%llx (%p)\n",
1235 txq
->axq_qnum
, txq
->axq_link
,
1236 ito64(bf
->bf_daddr
), bf
->bf_desc
);
1238 txq
->axq_link
= &(bf
->bf_lastbf
->bf_desc
->ds_link
);
1239 ath9k_hw_txstart(ah
, txq
->axq_qnum
);
1242 static struct ath_buf
*ath_tx_get_buffer(struct ath_softc
*sc
)
1244 struct ath_buf
*bf
= NULL
;
1246 spin_lock_bh(&sc
->tx
.txbuflock
);
1248 if (unlikely(list_empty(&sc
->tx
.txbuf
))) {
1249 spin_unlock_bh(&sc
->tx
.txbuflock
);
1253 bf
= list_first_entry(&sc
->tx
.txbuf
, struct ath_buf
, list
);
1254 list_del(&bf
->list
);
1256 spin_unlock_bh(&sc
->tx
.txbuflock
);
1261 static void ath_tx_send_ampdu(struct ath_softc
*sc
, struct ath_atx_tid
*tid
,
1262 struct list_head
*bf_head
,
1263 struct ath_tx_control
*txctl
)
1267 bf
= list_first_entry(bf_head
, struct ath_buf
, list
);
1268 bf
->bf_state
.bf_type
|= BUF_AMPDU
;
1269 TX_STAT_INC(txctl
->txq
->axq_qnum
, a_queued
);
1272 * Do not queue to h/w when any of the following conditions is true:
1273 * - there are pending frames in software queue
1274 * - the TID is currently paused for ADDBA/BAR request
1275 * - seqno is not within block-ack window
1276 * - h/w queue depth exceeds low water mark
1278 if (!list_empty(&tid
->buf_q
) || tid
->paused
||
1279 !BAW_WITHIN(tid
->seq_start
, tid
->baw_size
, bf
->bf_seqno
) ||
1280 txctl
->txq
->axq_depth
>= ATH_AGGR_MIN_QDEPTH
) {
1282 * Add this frame to software queue for scheduling later
1285 list_move_tail(&bf
->list
, &tid
->buf_q
);
1286 ath_tx_queue_tid(txctl
->txq
, tid
);
1290 /* Add sub-frame to BAW */
1291 ath_tx_addto_baw(sc
, tid
, bf
);
1293 /* Queue to h/w without aggregation */
1296 ath_buf_set_rate(sc
, bf
);
1297 ath_tx_txqaddbuf(sc
, txctl
->txq
, bf_head
);
1300 static void ath_tx_send_ht_normal(struct ath_softc
*sc
, struct ath_txq
*txq
,
1301 struct ath_atx_tid
*tid
,
1302 struct list_head
*bf_head
)
1306 bf
= list_first_entry(bf_head
, struct ath_buf
, list
);
1307 bf
->bf_state
.bf_type
&= ~BUF_AMPDU
;
1309 /* update starting sequence number for subsequent ADDBA request */
1310 INCR(tid
->seq_start
, IEEE80211_SEQ_MAX
);
1314 ath_buf_set_rate(sc
, bf
);
1315 ath_tx_txqaddbuf(sc
, txq
, bf_head
);
1316 TX_STAT_INC(txq
->axq_qnum
, queued
);
1319 static void ath_tx_send_normal(struct ath_softc
*sc
, struct ath_txq
*txq
,
1320 struct list_head
*bf_head
)
1324 bf
= list_first_entry(bf_head
, struct ath_buf
, list
);
1328 ath_buf_set_rate(sc
, bf
);
1329 ath_tx_txqaddbuf(sc
, txq
, bf_head
);
1330 TX_STAT_INC(txq
->axq_qnum
, queued
);
1333 static enum ath9k_pkt_type
get_hw_packet_type(struct sk_buff
*skb
)
1335 struct ieee80211_hdr
*hdr
;
1336 enum ath9k_pkt_type htype
;
1339 hdr
= (struct ieee80211_hdr
*)skb
->data
;
1340 fc
= hdr
->frame_control
;
1342 if (ieee80211_is_beacon(fc
))
1343 htype
= ATH9K_PKT_TYPE_BEACON
;
1344 else if (ieee80211_is_probe_resp(fc
))
1345 htype
= ATH9K_PKT_TYPE_PROBE_RESP
;
1346 else if (ieee80211_is_atim(fc
))
1347 htype
= ATH9K_PKT_TYPE_ATIM
;
1348 else if (ieee80211_is_pspoll(fc
))
1349 htype
= ATH9K_PKT_TYPE_PSPOLL
;
1351 htype
= ATH9K_PKT_TYPE_NORMAL
;
1356 static bool is_pae(struct sk_buff
*skb
)
1358 struct ieee80211_hdr
*hdr
;
1361 hdr
= (struct ieee80211_hdr
*)skb
->data
;
1362 fc
= hdr
->frame_control
;
1364 if (ieee80211_is_data(fc
)) {
1365 if (ieee80211_is_nullfunc(fc
) ||
1366 /* Port Access Entity (IEEE 802.1X) */
1367 (skb
->protocol
== cpu_to_be16(ETH_P_PAE
))) {
1375 static int get_hw_crypto_keytype(struct sk_buff
*skb
)
1377 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
1379 if (tx_info
->control
.hw_key
) {
1380 if (tx_info
->control
.hw_key
->alg
== ALG_WEP
)
1381 return ATH9K_KEY_TYPE_WEP
;
1382 else if (tx_info
->control
.hw_key
->alg
== ALG_TKIP
)
1383 return ATH9K_KEY_TYPE_TKIP
;
1384 else if (tx_info
->control
.hw_key
->alg
== ALG_CCMP
)
1385 return ATH9K_KEY_TYPE_AES
;
1388 return ATH9K_KEY_TYPE_CLEAR
;
1391 static void assign_aggr_tid_seqno(struct sk_buff
*skb
,
1394 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
1395 struct ieee80211_hdr
*hdr
;
1396 struct ath_node
*an
;
1397 struct ath_atx_tid
*tid
;
1401 if (!tx_info
->control
.sta
)
1404 an
= (struct ath_node
*)tx_info
->control
.sta
->drv_priv
;
1405 hdr
= (struct ieee80211_hdr
*)skb
->data
;
1406 fc
= hdr
->frame_control
;
1408 if (ieee80211_is_data_qos(fc
)) {
1409 qc
= ieee80211_get_qos_ctl(hdr
);
1410 bf
->bf_tidno
= qc
[0] & 0xf;
1414 * For HT capable stations, we save tidno for later use.
1415 * We also override seqno set by upper layer with the one
1416 * in tx aggregation state.
1418 * If fragmentation is on, the sequence number is
1419 * not overridden, since it has been
1420 * incremented by the fragmentation routine.
1422 * FIXME: check if the fragmentation threshold exceeds
1425 tid
= ATH_AN_2_TID(an
, bf
->bf_tidno
);
1426 hdr
->seq_ctrl
= cpu_to_le16(tid
->seq_next
<<
1427 IEEE80211_SEQ_SEQ_SHIFT
);
1428 bf
->bf_seqno
= tid
->seq_next
;
1429 INCR(tid
->seq_next
, IEEE80211_SEQ_MAX
);
1432 static int setup_tx_flags(struct ath_softc
*sc
, struct sk_buff
*skb
,
1433 struct ath_txq
*txq
)
1435 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
1438 flags
|= ATH9K_TXDESC_CLRDMASK
; /* needed for crypto errors */
1439 flags
|= ATH9K_TXDESC_INTREQ
;
1441 if (tx_info
->flags
& IEEE80211_TX_CTL_NO_ACK
)
1442 flags
|= ATH9K_TXDESC_NOACK
;
1449 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
1450 * width - 0 for 20 MHz, 1 for 40 MHz
1451 * half_gi - to use 4us v/s 3.6 us for symbol time
1453 static u32
ath_pkt_duration(struct ath_softc
*sc
, u8 rix
, struct ath_buf
*bf
,
1454 int width
, int half_gi
, bool shortPreamble
)
1456 u32 nbits
, nsymbits
, duration
, nsymbols
;
1457 int streams
, pktlen
;
1459 pktlen
= bf_isaggr(bf
) ? bf
->bf_al
: bf
->bf_frmlen
;
1461 /* find number of symbols: PLCP + data */
1462 nbits
= (pktlen
<< 3) + OFDM_PLCP_BITS
;
1463 nsymbits
= bits_per_symbol
[rix
][width
];
1464 nsymbols
= (nbits
+ nsymbits
- 1) / nsymbits
;
1467 duration
= SYMBOL_TIME(nsymbols
);
1469 duration
= SYMBOL_TIME_HALFGI(nsymbols
);
1471 /* addup duration for legacy/ht training and signal fields */
1472 streams
= HT_RC_2_STREAMS(rix
);
1473 duration
+= L_STF
+ L_LTF
+ L_SIG
+ HT_SIG
+ HT_STF
+ HT_LTF(streams
);
1478 static void ath_buf_set_rate(struct ath_softc
*sc
, struct ath_buf
*bf
)
1480 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
1481 struct ath9k_11n_rate_series series
[4];
1482 struct sk_buff
*skb
;
1483 struct ieee80211_tx_info
*tx_info
;
1484 struct ieee80211_tx_rate
*rates
;
1485 const struct ieee80211_rate
*rate
;
1486 struct ieee80211_hdr
*hdr
;
1488 u8 rix
= 0, ctsrate
= 0;
1491 memset(series
, 0, sizeof(struct ath9k_11n_rate_series
) * 4);
1494 tx_info
= IEEE80211_SKB_CB(skb
);
1495 rates
= tx_info
->control
.rates
;
1496 hdr
= (struct ieee80211_hdr
*)skb
->data
;
1497 is_pspoll
= ieee80211_is_pspoll(hdr
->frame_control
);
1500 * We check if Short Preamble is needed for the CTS rate by
1501 * checking the BSS's global flag.
1502 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
1504 rate
= ieee80211_get_rts_cts_rate(sc
->hw
, tx_info
);
1505 ctsrate
= rate
->hw_value
;
1506 if (sc
->sc_flags
& SC_OP_PREAMBLE_SHORT
)
1507 ctsrate
|= rate
->hw_value_short
;
1510 * ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive.
1511 * Check the first rate in the series to decide whether RTS/CTS
1512 * or CTS-to-self has to be used.
1514 if (rates
[0].flags
& IEEE80211_TX_RC_USE_CTS_PROTECT
)
1515 flags
= ATH9K_TXDESC_CTSENA
;
1516 else if (rates
[0].flags
& IEEE80211_TX_RC_USE_RTS_CTS
)
1517 flags
= ATH9K_TXDESC_RTSENA
;
1519 /* FIXME: Handle aggregation protection */
1520 if (sc
->config
.ath_aggr_prot
&&
1521 (!bf_isaggr(bf
) || (bf_isaggr(bf
) && bf
->bf_al
< 8192))) {
1522 flags
= ATH9K_TXDESC_RTSENA
;
1525 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1526 if (bf_isaggr(bf
) && (bf
->bf_al
> sc
->sc_ah
->caps
.rts_aggr_limit
))
1527 flags
&= ~(ATH9K_TXDESC_RTSENA
);
1529 for (i
= 0; i
< 4; i
++) {
1530 bool is_40
, is_sgi
, is_sp
;
1533 if (!rates
[i
].count
|| (rates
[i
].idx
< 0))
1537 series
[i
].Tries
= rates
[i
].count
;
1538 series
[i
].ChSel
= common
->tx_chainmask
;
1540 if (rates
[i
].flags
& IEEE80211_TX_RC_USE_RTS_CTS
)
1541 series
[i
].RateFlags
|= ATH9K_RATESERIES_RTS_CTS
;
1542 if (rates
[i
].flags
& IEEE80211_TX_RC_40_MHZ_WIDTH
)
1543 series
[i
].RateFlags
|= ATH9K_RATESERIES_2040
;
1544 if (rates
[i
].flags
& IEEE80211_TX_RC_SHORT_GI
)
1545 series
[i
].RateFlags
|= ATH9K_RATESERIES_HALFGI
;
1547 is_sgi
= !!(rates
[i
].flags
& IEEE80211_TX_RC_SHORT_GI
);
1548 is_40
= !!(rates
[i
].flags
& IEEE80211_TX_RC_40_MHZ_WIDTH
);
1549 is_sp
= !!(rates
[i
].flags
& IEEE80211_TX_RC_USE_SHORT_PREAMBLE
);
1551 if (rates
[i
].flags
& IEEE80211_TX_RC_MCS
) {
1553 series
[i
].Rate
= rix
| 0x80;
1554 series
[i
].PktDuration
= ath_pkt_duration(sc
, rix
, bf
,
1555 is_40
, is_sgi
, is_sp
);
1560 if ((tx_info
->band
== IEEE80211_BAND_2GHZ
) &&
1561 !(rate
->flags
& IEEE80211_RATE_ERP_G
))
1562 phy
= WLAN_RC_PHY_CCK
;
1564 phy
= WLAN_RC_PHY_OFDM
;
1566 rate
= &sc
->sbands
[tx_info
->band
].bitrates
[rates
[i
].idx
];
1567 series
[i
].Rate
= rate
->hw_value
;
1568 if (rate
->hw_value_short
) {
1569 if (rates
[i
].flags
& IEEE80211_TX_RC_USE_SHORT_PREAMBLE
)
1570 series
[i
].Rate
|= rate
->hw_value_short
;
1575 series
[i
].PktDuration
= ath9k_hw_computetxtime(sc
->sc_ah
,
1576 phy
, rate
->bitrate
* 100, bf
->bf_frmlen
, rix
, is_sp
);
1579 /* set dur_update_en for l-sig computation except for PS-Poll frames */
1580 ath9k_hw_set11n_ratescenario(sc
->sc_ah
, bf
->bf_desc
,
1581 bf
->bf_lastbf
->bf_desc
,
1582 !is_pspoll
, ctsrate
,
1583 0, series
, 4, flags
);
1585 if (sc
->config
.ath_aggr_prot
&& flags
)
1586 ath9k_hw_set11n_burstduration(sc
->sc_ah
, bf
->bf_desc
, 8192);
1589 static int ath_tx_setup_buffer(struct ieee80211_hw
*hw
, struct ath_buf
*bf
,
1590 struct sk_buff
*skb
,
1591 struct ath_tx_control
*txctl
)
1593 struct ath_wiphy
*aphy
= hw
->priv
;
1594 struct ath_softc
*sc
= aphy
->sc
;
1595 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
1596 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
1599 int padpos
, padsize
;
1601 tx_info
->pad
[0] = 0;
1602 switch (txctl
->frame_type
) {
1603 case ATH9K_NOT_INTERNAL
:
1605 case ATH9K_INT_PAUSE
:
1606 tx_info
->pad
[0] |= ATH_TX_INFO_FRAME_TYPE_PAUSE
;
1608 case ATH9K_INT_UNPAUSE
:
1609 tx_info
->pad
[0] |= ATH_TX_INFO_FRAME_TYPE_INTERNAL
;
1612 hdrlen
= ieee80211_get_hdrlen_from_skb(skb
);
1613 fc
= hdr
->frame_control
;
1615 ATH_TXBUF_RESET(bf
);
1618 bf
->bf_frmlen
= skb
->len
+ FCS_LEN
;
1619 /* Remove the padding size from bf_frmlen, if any */
1620 padpos
= ath9k_cmn_padpos(hdr
->frame_control
);
1621 padsize
= padpos
& 3;
1622 if (padsize
&& skb
->len
>padpos
+padsize
) {
1623 bf
->bf_frmlen
-= padsize
;
1626 if (conf_is_ht(&hw
->conf
) && !is_pae(skb
))
1627 bf
->bf_state
.bf_type
|= BUF_HT
;
1629 bf
->bf_flags
= setup_tx_flags(sc
, skb
, txctl
->txq
);
1631 bf
->bf_keytype
= get_hw_crypto_keytype(skb
);
1632 if (bf
->bf_keytype
!= ATH9K_KEY_TYPE_CLEAR
) {
1633 bf
->bf_frmlen
+= tx_info
->control
.hw_key
->icv_len
;
1634 bf
->bf_keyix
= tx_info
->control
.hw_key
->hw_key_idx
;
1636 bf
->bf_keyix
= ATH9K_TXKEYIX_INVALID
;
1639 if (ieee80211_is_data_qos(fc
) && (sc
->sc_flags
& SC_OP_TXAGGR
))
1640 assign_aggr_tid_seqno(skb
, bf
);
1644 bf
->bf_dmacontext
= dma_map_single(sc
->dev
, skb
->data
,
1645 skb
->len
, DMA_TO_DEVICE
);
1646 if (unlikely(dma_mapping_error(sc
->dev
, bf
->bf_dmacontext
))) {
1648 ath_print(ath9k_hw_common(sc
->sc_ah
), ATH_DBG_FATAL
,
1649 "dma_mapping_error() on TX\n");
1653 bf
->bf_buf_addr
= bf
->bf_dmacontext
;
1655 /* tag if this is a nullfunc frame to enable PS when AP acks it */
1656 if (ieee80211_is_nullfunc(fc
) && ieee80211_has_pm(fc
)) {
1657 bf
->bf_isnullfunc
= true;
1658 sc
->sc_flags
&= ~SC_OP_NULLFUNC_COMPLETED
;
1660 bf
->bf_isnullfunc
= false;
1665 /* FIXME: tx power */
1666 static void ath_tx_start_dma(struct ath_softc
*sc
, struct ath_buf
*bf
,
1667 struct ath_tx_control
*txctl
)
1669 struct sk_buff
*skb
= bf
->bf_mpdu
;
1670 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
1671 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
1672 struct ath_node
*an
= NULL
;
1673 struct list_head bf_head
;
1674 struct ath_desc
*ds
;
1675 struct ath_atx_tid
*tid
;
1676 struct ath_hw
*ah
= sc
->sc_ah
;
1680 frm_type
= get_hw_packet_type(skb
);
1681 fc
= hdr
->frame_control
;
1683 INIT_LIST_HEAD(&bf_head
);
1684 list_add_tail(&bf
->list
, &bf_head
);
1688 ds
->ds_data
= bf
->bf_buf_addr
;
1690 ath9k_hw_set11n_txdesc(ah
, ds
, bf
->bf_frmlen
, frm_type
, MAX_RATE_POWER
,
1691 bf
->bf_keyix
, bf
->bf_keytype
, bf
->bf_flags
);
1693 ath9k_hw_filltxdesc(ah
, ds
,
1694 skb
->len
, /* segment length */
1695 true, /* first segment */
1696 true, /* last segment */
1697 ds
); /* first descriptor */
1699 spin_lock_bh(&txctl
->txq
->axq_lock
);
1701 if (bf_isht(bf
) && (sc
->sc_flags
& SC_OP_TXAGGR
) &&
1702 tx_info
->control
.sta
) {
1703 an
= (struct ath_node
*)tx_info
->control
.sta
->drv_priv
;
1704 tid
= ATH_AN_2_TID(an
, bf
->bf_tidno
);
1706 if (!ieee80211_is_data_qos(fc
)) {
1707 ath_tx_send_normal(sc
, txctl
->txq
, &bf_head
);
1711 if (tx_info
->flags
& IEEE80211_TX_CTL_AMPDU
) {
1713 * Try aggregation if it's a unicast data frame
1714 * and the destination is HT capable.
1716 ath_tx_send_ampdu(sc
, tid
, &bf_head
, txctl
);
1719 * Send this frame as regular when ADDBA
1720 * exchange is neither complete nor pending.
1722 ath_tx_send_ht_normal(sc
, txctl
->txq
,
1726 ath_tx_send_normal(sc
, txctl
->txq
, &bf_head
);
1730 spin_unlock_bh(&txctl
->txq
->axq_lock
);
1733 /* Upon failure caller should free skb */
1734 int ath_tx_start(struct ieee80211_hw
*hw
, struct sk_buff
*skb
,
1735 struct ath_tx_control
*txctl
)
1737 struct ath_wiphy
*aphy
= hw
->priv
;
1738 struct ath_softc
*sc
= aphy
->sc
;
1739 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
1743 bf
= ath_tx_get_buffer(sc
);
1745 ath_print(common
, ATH_DBG_XMIT
, "TX buffers are full\n");
1749 r
= ath_tx_setup_buffer(hw
, bf
, skb
, txctl
);
1751 struct ath_txq
*txq
= txctl
->txq
;
1753 ath_print(common
, ATH_DBG_FATAL
, "TX mem alloc failure\n");
1755 /* upon ath_tx_processq() this TX queue will be resumed, we
1756 * guarantee this will happen by knowing beforehand that
1757 * we will at least have to run TX completionon one buffer
1759 spin_lock_bh(&txq
->axq_lock
);
1760 if (sc
->tx
.txq
[txq
->axq_qnum
].axq_depth
> 1) {
1761 ath_mac80211_stop_queue(sc
, skb_get_queue_mapping(skb
));
1764 spin_unlock_bh(&txq
->axq_lock
);
1766 spin_lock_bh(&sc
->tx
.txbuflock
);
1767 list_add_tail(&bf
->list
, &sc
->tx
.txbuf
);
1768 spin_unlock_bh(&sc
->tx
.txbuflock
);
1773 ath_tx_start_dma(sc
, bf
, txctl
);
1778 void ath_tx_cabq(struct ieee80211_hw
*hw
, struct sk_buff
*skb
)
1780 struct ath_wiphy
*aphy
= hw
->priv
;
1781 struct ath_softc
*sc
= aphy
->sc
;
1782 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
1783 int hdrlen
, padsize
;
1784 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
1785 struct ath_tx_control txctl
;
1787 memset(&txctl
, 0, sizeof(struct ath_tx_control
));
1790 * As a temporary workaround, assign seq# here; this will likely need
1791 * to be cleaned up to work better with Beacon transmission and virtual
1794 if (info
->flags
& IEEE80211_TX_CTL_ASSIGN_SEQ
) {
1795 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*) skb
->data
;
1796 if (info
->flags
& IEEE80211_TX_CTL_FIRST_FRAGMENT
)
1797 sc
->tx
.seq_no
+= 0x10;
1798 hdr
->seq_ctrl
&= cpu_to_le16(IEEE80211_SCTL_FRAG
);
1799 hdr
->seq_ctrl
|= cpu_to_le16(sc
->tx
.seq_no
);
1802 /* Add the padding after the header if this is not already done */
1803 hdrlen
= ieee80211_get_hdrlen_from_skb(skb
);
1805 padsize
= hdrlen
% 4;
1806 if (skb_headroom(skb
) < padsize
) {
1807 ath_print(common
, ATH_DBG_XMIT
,
1808 "TX CABQ padding failed\n");
1809 dev_kfree_skb_any(skb
);
1812 skb_push(skb
, padsize
);
1813 memmove(skb
->data
, skb
->data
+ padsize
, hdrlen
);
1816 txctl
.txq
= sc
->beacon
.cabq
;
1818 ath_print(common
, ATH_DBG_XMIT
,
1819 "transmitting CABQ packet, skb: %p\n", skb
);
1821 if (ath_tx_start(hw
, skb
, &txctl
) != 0) {
1822 ath_print(common
, ATH_DBG_XMIT
, "CABQ TX failed\n");
1828 dev_kfree_skb_any(skb
);
1835 static void ath_tx_complete(struct ath_softc
*sc
, struct sk_buff
*skb
,
1836 struct ath_wiphy
*aphy
, int tx_flags
)
1838 struct ieee80211_hw
*hw
= sc
->hw
;
1839 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
1840 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
1841 int hdrlen
, padsize
;
1843 ath_print(common
, ATH_DBG_XMIT
, "TX complete: skb: %p\n", skb
);
1848 if (tx_flags
& ATH_TX_BAR
)
1849 tx_info
->flags
|= IEEE80211_TX_STAT_AMPDU_NO_BACK
;
1851 if (!(tx_flags
& (ATH_TX_ERROR
| ATH_TX_XRETRY
))) {
1852 /* Frame was ACKed */
1853 tx_info
->flags
|= IEEE80211_TX_STAT_ACK
;
1856 hdrlen
= ieee80211_get_hdrlen_from_skb(skb
);
1857 padsize
= hdrlen
& 3;
1858 if (padsize
&& hdrlen
>= 24) {
1860 * Remove MAC header padding before giving the frame back to
1863 memmove(skb
->data
+ padsize
, skb
->data
, hdrlen
);
1864 skb_pull(skb
, padsize
);
1867 if (sc
->sc_flags
& SC_OP_WAIT_FOR_TX_ACK
) {
1868 sc
->sc_flags
&= ~SC_OP_WAIT_FOR_TX_ACK
;
1869 ath_print(common
, ATH_DBG_PS
,
1870 "Going back to sleep after having "
1871 "received TX status (0x%x)\n",
1872 sc
->sc_flags
& (SC_OP_WAIT_FOR_BEACON
|
1873 SC_OP_WAIT_FOR_CAB
|
1874 SC_OP_WAIT_FOR_PSPOLL_DATA
|
1875 SC_OP_WAIT_FOR_TX_ACK
));
1878 if (unlikely(tx_info
->pad
[0] & ATH_TX_INFO_FRAME_TYPE_INTERNAL
))
1879 ath9k_tx_status(hw
, skb
);
1881 ieee80211_tx_status(hw
, skb
);
1884 static void ath_tx_complete_buf(struct ath_softc
*sc
, struct ath_buf
*bf
,
1885 struct ath_txq
*txq
,
1886 struct list_head
*bf_q
,
1887 int txok
, int sendbar
)
1889 struct sk_buff
*skb
= bf
->bf_mpdu
;
1890 unsigned long flags
;
1894 tx_flags
= ATH_TX_BAR
;
1897 tx_flags
|= ATH_TX_ERROR
;
1899 if (bf_isxretried(bf
))
1900 tx_flags
|= ATH_TX_XRETRY
;
1903 dma_unmap_single(sc
->dev
, bf
->bf_dmacontext
, skb
->len
, DMA_TO_DEVICE
);
1904 ath_tx_complete(sc
, skb
, bf
->aphy
, tx_flags
);
1905 ath_debug_stat_tx(sc
, txq
, bf
);
1908 * Return the list of ath_buf of this mpdu to free queue
1910 spin_lock_irqsave(&sc
->tx
.txbuflock
, flags
);
1911 list_splice_tail_init(bf_q
, &sc
->tx
.txbuf
);
1912 spin_unlock_irqrestore(&sc
->tx
.txbuflock
, flags
);
1915 static int ath_tx_num_badfrms(struct ath_softc
*sc
, struct ath_buf
*bf
,
1918 struct ath_buf
*bf_last
= bf
->bf_lastbf
;
1919 struct ath_desc
*ds
= bf_last
->bf_desc
;
1921 u32 ba
[WME_BA_BMP_SIZE
>> 5];
1926 if (ds
->ds_txstat
.ts_flags
== ATH9K_TX_SW_ABORTED
)
1929 isaggr
= bf_isaggr(bf
);
1931 seq_st
= ATH_DS_BA_SEQ(ds
);
1932 memcpy(ba
, ATH_DS_BA_BITMAP(ds
), WME_BA_BMP_SIZE
>> 3);
1936 ba_index
= ATH_BA_INDEX(seq_st
, bf
->bf_seqno
);
1937 if (!txok
|| (isaggr
&& !ATH_BA_ISSET(ba
, ba_index
)))
1946 static void ath_tx_rc_status(struct ath_buf
*bf
, struct ath_desc
*ds
,
1947 int nbad
, int txok
, bool update_rc
)
1949 struct sk_buff
*skb
= bf
->bf_mpdu
;
1950 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
1951 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
1952 struct ieee80211_hw
*hw
= bf
->aphy
->hw
;
1956 tx_info
->status
.ack_signal
= ds
->ds_txstat
.ts_rssi
;
1958 tx_rateindex
= ds
->ds_txstat
.ts_rateindex
;
1959 WARN_ON(tx_rateindex
>= hw
->max_rates
);
1962 tx_info
->pad
[0] |= ATH_TX_INFO_UPDATE_RC
;
1963 if (ds
->ds_txstat
.ts_status
& ATH9K_TXERR_FILT
)
1964 tx_info
->flags
|= IEEE80211_TX_STAT_TX_FILTERED
;
1966 if ((ds
->ds_txstat
.ts_status
& ATH9K_TXERR_FILT
) == 0 &&
1967 (bf
->bf_flags
& ATH9K_TXDESC_NOACK
) == 0 && update_rc
) {
1968 if (ieee80211_is_data(hdr
->frame_control
)) {
1969 if (ds
->ds_txstat
.ts_flags
&
1970 (ATH9K_TX_DATA_UNDERRUN
| ATH9K_TX_DELIM_UNDERRUN
))
1971 tx_info
->pad
[0] |= ATH_TX_INFO_UNDERRUN
;
1972 if ((ds
->ds_txstat
.ts_status
& ATH9K_TXERR_XRETRY
) ||
1973 (ds
->ds_txstat
.ts_status
& ATH9K_TXERR_FIFO
))
1974 tx_info
->pad
[0] |= ATH_TX_INFO_XRETRY
;
1975 tx_info
->status
.ampdu_len
= bf
->bf_nframes
;
1976 tx_info
->status
.ampdu_ack_len
= bf
->bf_nframes
- nbad
;
1980 for (i
= tx_rateindex
+ 1; i
< hw
->max_rates
; i
++) {
1981 tx_info
->status
.rates
[i
].count
= 0;
1982 tx_info
->status
.rates
[i
].idx
= -1;
1985 tx_info
->status
.rates
[tx_rateindex
].count
= bf
->bf_retries
+ 1;
1988 static void ath_wake_mac80211_queue(struct ath_softc
*sc
, struct ath_txq
*txq
)
1992 spin_lock_bh(&txq
->axq_lock
);
1994 sc
->tx
.txq
[txq
->axq_qnum
].axq_depth
<= (ATH_TXBUF
- 20)) {
1995 qnum
= ath_get_mac80211_qnum(txq
->axq_qnum
, sc
);
1997 ath_mac80211_start_queue(sc
, qnum
);
2001 spin_unlock_bh(&txq
->axq_lock
);
2004 static void ath_tx_processq(struct ath_softc
*sc
, struct ath_txq
*txq
)
2006 struct ath_hw
*ah
= sc
->sc_ah
;
2007 struct ath_common
*common
= ath9k_hw_common(ah
);
2008 struct ath_buf
*bf
, *lastbf
, *bf_held
= NULL
;
2009 struct list_head bf_head
;
2010 struct ath_desc
*ds
;
2014 ath_print(common
, ATH_DBG_QUEUE
, "tx queue %d (%x), link %p\n",
2015 txq
->axq_qnum
, ath9k_hw_gettxbuf(sc
->sc_ah
, txq
->axq_qnum
),
2019 spin_lock_bh(&txq
->axq_lock
);
2020 if (list_empty(&txq
->axq_q
)) {
2021 txq
->axq_link
= NULL
;
2022 spin_unlock_bh(&txq
->axq_lock
);
2025 bf
= list_first_entry(&txq
->axq_q
, struct ath_buf
, list
);
2028 * There is a race condition that a BH gets scheduled
2029 * after sw writes TxE and before hw re-load the last
2030 * descriptor to get the newly chained one.
2031 * Software must keep the last DONE descriptor as a
2032 * holding descriptor - software does so by marking
2033 * it with the STALE flag.
2038 if (list_is_last(&bf_held
->list
, &txq
->axq_q
)) {
2039 spin_unlock_bh(&txq
->axq_lock
);
2042 bf
= list_entry(bf_held
->list
.next
,
2043 struct ath_buf
, list
);
2047 lastbf
= bf
->bf_lastbf
;
2048 ds
= lastbf
->bf_desc
;
2050 status
= ath9k_hw_txprocdesc(ah
, ds
);
2051 if (status
== -EINPROGRESS
) {
2052 spin_unlock_bh(&txq
->axq_lock
);
2057 * We now know the nullfunc frame has been ACKed so we
2060 if (bf
->bf_isnullfunc
&&
2061 (ds
->ds_txstat
.ts_status
& ATH9K_TX_ACKED
)) {
2062 if ((sc
->sc_flags
& SC_OP_PS_ENABLED
)) {
2063 sc
->ps_enabled
= true;
2064 ath9k_hw_setrxabort(sc
->sc_ah
, 1);
2066 sc
->sc_flags
|= SC_OP_NULLFUNC_COMPLETED
;
2070 * Remove ath_buf's of the same transmit unit from txq,
2071 * however leave the last descriptor back as the holding
2072 * descriptor for hw.
2074 lastbf
->bf_stale
= true;
2075 INIT_LIST_HEAD(&bf_head
);
2076 if (!list_is_singular(&lastbf
->list
))
2077 list_cut_position(&bf_head
,
2078 &txq
->axq_q
, lastbf
->list
.prev
);
2081 txok
= !(ds
->ds_txstat
.ts_status
& ATH9K_TXERR_FILT
);
2082 txq
->axq_tx_inprogress
= false;
2083 spin_unlock_bh(&txq
->axq_lock
);
2086 spin_lock_bh(&sc
->tx
.txbuflock
);
2087 list_move_tail(&bf_held
->list
, &sc
->tx
.txbuf
);
2088 spin_unlock_bh(&sc
->tx
.txbuflock
);
2091 if (!bf_isampdu(bf
)) {
2093 * This frame is sent out as a single frame.
2094 * Use hardware retry status for this frame.
2096 bf
->bf_retries
= ds
->ds_txstat
.ts_longretry
;
2097 if (ds
->ds_txstat
.ts_status
& ATH9K_TXERR_XRETRY
)
2098 bf
->bf_state
.bf_type
|= BUF_XRETRY
;
2099 ath_tx_rc_status(bf
, ds
, 0, txok
, true);
2103 ath_tx_complete_aggr(sc
, txq
, bf
, &bf_head
, txok
);
2105 ath_tx_complete_buf(sc
, bf
, txq
, &bf_head
, txok
, 0);
2107 ath_wake_mac80211_queue(sc
, txq
);
2109 spin_lock_bh(&txq
->axq_lock
);
2110 if (sc
->sc_flags
& SC_OP_TXAGGR
)
2111 ath_txq_schedule(sc
, txq
);
2112 spin_unlock_bh(&txq
->axq_lock
);
2116 static void ath_tx_complete_poll_work(struct work_struct
*work
)
2118 struct ath_softc
*sc
= container_of(work
, struct ath_softc
,
2119 tx_complete_work
.work
);
2120 struct ath_txq
*txq
;
2122 bool needreset
= false;
2124 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++)
2125 if (ATH_TXQ_SETUP(sc
, i
)) {
2126 txq
= &sc
->tx
.txq
[i
];
2127 spin_lock_bh(&txq
->axq_lock
);
2128 if (txq
->axq_depth
) {
2129 if (txq
->axq_tx_inprogress
) {
2131 spin_unlock_bh(&txq
->axq_lock
);
2134 txq
->axq_tx_inprogress
= true;
2137 spin_unlock_bh(&txq
->axq_lock
);
2141 ath_print(ath9k_hw_common(sc
->sc_ah
), ATH_DBG_RESET
,
2142 "tx hung, resetting the chip\n");
2143 ath9k_ps_wakeup(sc
);
2144 ath_reset(sc
, false);
2145 ath9k_ps_restore(sc
);
2148 ieee80211_queue_delayed_work(sc
->hw
, &sc
->tx_complete_work
,
2149 msecs_to_jiffies(ATH_TX_COMPLETE_POLL_INT
));
2154 void ath_tx_tasklet(struct ath_softc
*sc
)
2157 u32 qcumask
= ((1 << ATH9K_NUM_TX_QUEUES
) - 1);
2159 ath9k_hw_gettxintrtxqs(sc
->sc_ah
, &qcumask
);
2161 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++) {
2162 if (ATH_TXQ_SETUP(sc
, i
) && (qcumask
& (1 << i
)))
2163 ath_tx_processq(sc
, &sc
->tx
.txq
[i
]);
2171 int ath_tx_init(struct ath_softc
*sc
, int nbufs
)
2173 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
2176 spin_lock_init(&sc
->tx
.txbuflock
);
2178 error
= ath_descdma_setup(sc
, &sc
->tx
.txdma
, &sc
->tx
.txbuf
,
2181 ath_print(common
, ATH_DBG_FATAL
,
2182 "Failed to allocate tx descriptors: %d\n", error
);
2186 error
= ath_descdma_setup(sc
, &sc
->beacon
.bdma
, &sc
->beacon
.bbuf
,
2187 "beacon", ATH_BCBUF
, 1);
2189 ath_print(common
, ATH_DBG_FATAL
,
2190 "Failed to allocate beacon descriptors: %d\n", error
);
2194 INIT_DELAYED_WORK(&sc
->tx_complete_work
, ath_tx_complete_poll_work
);
2203 void ath_tx_cleanup(struct ath_softc
*sc
)
2205 if (sc
->beacon
.bdma
.dd_desc_len
!= 0)
2206 ath_descdma_cleanup(sc
, &sc
->beacon
.bdma
, &sc
->beacon
.bbuf
);
2208 if (sc
->tx
.txdma
.dd_desc_len
!= 0)
2209 ath_descdma_cleanup(sc
, &sc
->tx
.txdma
, &sc
->tx
.txbuf
);
2212 void ath_tx_node_init(struct ath_softc
*sc
, struct ath_node
*an
)
2214 struct ath_atx_tid
*tid
;
2215 struct ath_atx_ac
*ac
;
2218 for (tidno
= 0, tid
= &an
->tid
[tidno
];
2219 tidno
< WME_NUM_TID
;
2223 tid
->seq_start
= tid
->seq_next
= 0;
2224 tid
->baw_size
= WME_MAX_BA
;
2225 tid
->baw_head
= tid
->baw_tail
= 0;
2227 tid
->paused
= false;
2228 tid
->state
&= ~AGGR_CLEANUP
;
2229 INIT_LIST_HEAD(&tid
->buf_q
);
2230 acno
= TID_TO_WME_AC(tidno
);
2231 tid
->ac
= &an
->ac
[acno
];
2232 tid
->state
&= ~AGGR_ADDBA_COMPLETE
;
2233 tid
->state
&= ~AGGR_ADDBA_PROGRESS
;
2236 for (acno
= 0, ac
= &an
->ac
[acno
];
2237 acno
< WME_NUM_AC
; acno
++, ac
++) {
2239 INIT_LIST_HEAD(&ac
->tid_q
);
2243 ac
->qnum
= ath_tx_get_qnum(sc
,
2244 ATH9K_TX_QUEUE_DATA
, ATH9K_WME_AC_BE
);
2247 ac
->qnum
= ath_tx_get_qnum(sc
,
2248 ATH9K_TX_QUEUE_DATA
, ATH9K_WME_AC_BK
);
2251 ac
->qnum
= ath_tx_get_qnum(sc
,
2252 ATH9K_TX_QUEUE_DATA
, ATH9K_WME_AC_VI
);
2255 ac
->qnum
= ath_tx_get_qnum(sc
,
2256 ATH9K_TX_QUEUE_DATA
, ATH9K_WME_AC_VO
);
2262 void ath_tx_node_cleanup(struct ath_softc
*sc
, struct ath_node
*an
)
2265 struct ath_atx_ac
*ac
, *ac_tmp
;
2266 struct ath_atx_tid
*tid
, *tid_tmp
;
2267 struct ath_txq
*txq
;
2269 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++) {
2270 if (ATH_TXQ_SETUP(sc
, i
)) {
2271 txq
= &sc
->tx
.txq
[i
];
2273 spin_lock(&txq
->axq_lock
);
2275 list_for_each_entry_safe(ac
,
2276 ac_tmp
, &txq
->axq_acq
, list
) {
2277 tid
= list_first_entry(&ac
->tid_q
,
2278 struct ath_atx_tid
, list
);
2279 if (tid
&& tid
->an
!= an
)
2281 list_del(&ac
->list
);
2284 list_for_each_entry_safe(tid
,
2285 tid_tmp
, &ac
->tid_q
, list
) {
2286 list_del(&tid
->list
);
2288 ath_tid_drain(sc
, txq
, tid
);
2289 tid
->state
&= ~AGGR_ADDBA_COMPLETE
;
2290 tid
->state
&= ~AGGR_CLEANUP
;
2294 spin_unlock(&txq
->axq_lock
);